From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <Alistair.Francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: Bin Meng <bin.meng@windriver.com>,
Alistair Francis <alistair.francis@wdc.com>
Subject: [PATCH v4 2/7] target/riscv: machine: Add debug state description
Date: Tue, 15 Mar 2022 14:55:24 +0800 [thread overview]
Message-ID: <20220315065529.62198-3-bmeng.cn@gmail.com> (raw)
In-Reply-To: <20220315065529.62198-1-bmeng.cn@gmail.com>
From: Bin Meng <bin.meng@windriver.com>
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v2)
Changes in v2:
- new patch: add debug state description
target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 5178b3fec9..4921dad09d 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = {
VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static bool debug_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_feature(env, RISCV_FEATURE_DEBUG);
+}
+static const VMStateDescription vmstate_debug_type2 = {
+ .name = "cpu/debug/type2",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(mcontrol, type2_trigger_t),
+ VMSTATE_UINTTL(maddress, type2_trigger_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_debug = {
+ .name = "cpu/debug",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = debug_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
+ VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM,
+ 0, vmstate_debug_type2, type2_trigger_t),
VMSTATE_END_OF_LIST()
}
};
@@ -292,6 +323,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_pointermasking,
&vmstate_rv128,
&vmstate_kvmtimer,
+ &vmstate_debug,
NULL
}
};
--
2.25.1
next prev parent reply other threads:[~2022-03-15 7:18 UTC|newest]
Thread overview: 35+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-03-15 6:55 [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Bin Meng
2022-03-15 6:55 ` [PATCH v4 1/7] target/riscv: Add initial support for the Sdtrig extension Bin Meng
2022-03-18 2:11 ` Alistair Francis
2022-03-18 2:11 ` Alistair Francis
2022-03-15 6:55 ` Bin Meng [this message]
2022-04-20 7:30 ` [PATCH v4 2/7] target/riscv: machine: Add debug state description Alistair Francis
2022-04-20 7:30 ` Alistair Francis
2022-04-20 7:33 ` Bin Meng
2022-04-20 7:33 ` Bin Meng
2022-04-20 9:52 ` Bin Meng
2022-04-20 9:52 ` Bin Meng
2022-04-20 22:45 ` Alistair Francis
2022-04-20 22:45 ` Alistair Francis
2022-04-20 23:46 ` Bin Meng
2022-04-20 23:46 ` Bin Meng
2022-04-21 0:13 ` Alistair Francis
2022-04-21 0:13 ` Alistair Francis
2022-04-21 0:19 ` Bin Meng
2022-04-21 0:19 ` Bin Meng
2022-04-21 15:51 ` Richard Henderson
2022-04-21 15:51 ` Richard Henderson
2022-04-22 1:22 ` Bin Meng
2022-04-22 1:22 ` Bin Meng
2022-03-15 6:55 ` [PATCH v4 3/7] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng
2022-03-15 6:55 ` [PATCH v4 4/7] target/riscv: cpu: Add a config option for native debug Bin Meng
2022-03-15 6:55 ` [PATCH v4 5/7] target/riscv: csr: Hook debug CSR read/write Bin Meng
2022-03-18 2:14 ` Alistair Francis
2022-03-18 2:14 ` Alistair Francis
2022-03-15 6:55 ` [PATCH v4 6/7] target/riscv: cpu: Enable native debug feature Bin Meng
2022-03-18 2:17 ` Alistair Francis
2022-03-18 2:17 ` Alistair Francis
2022-03-15 6:55 ` [PATCH v4 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Bin Meng
2022-03-15 6:55 ` Bin Meng
2022-03-18 7:38 ` [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Alistair Francis
2022-03-18 7:38 ` Alistair Francis
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