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From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: "open list:RISC-V" <qemu-riscv@nongnu.org>,
	Bin Meng <bin.meng@windriver.com>,
	Alistair Francis <Alistair.Francis@wdc.com>,
	"qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>
Subject: Re: [PATCH v4 2/7] target/riscv: machine: Add debug state description
Date: Wed, 20 Apr 2022 15:33:24 +0800	[thread overview]
Message-ID: <CAEUhbmX0SdEcD8UWJUmmPm2SubT6gd991jNMAZJA8WFbRsdoaQ@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKMoRqbfSsUNM1O1cQGHaL9rc6fsCqJxEktQNrgrLCimgA@mail.gmail.com>

On Wed, Apr 20, 2022 at 3:31 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Mar 15, 2022 at 5:17 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > Add a subsection to machine.c to migrate debug CSR state.
> >
> > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >
> > (no changes since v2)
> >
> > Changes in v2:
> > - new patch: add debug state description
> >
> >  target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++
> >  1 file changed, 32 insertions(+)
> >
> > diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> > index 5178b3fec9..4921dad09d 100644
> > --- a/target/riscv/machine.c
> > +++ b/target/riscv/machine.c
> > @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = {
> >          VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
> >          VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
> >          VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
> > +        VMSTATE_END_OF_LIST()
> > +    }
> > +};
> > +
> > +static bool debug_needed(void *opaque)
> > +{
> > +    RISCVCPU *cpu = opaque;
> > +    CPURISCVState *env = &cpu->env;
> > +
> > +    return riscv_feature(env, RISCV_FEATURE_DEBUG);
>
> This fails to build:
>
> ../target/riscv/machine.c: In function ‘debug_needed’:
> ../target/riscv/machine.c:228:31: error: ‘RISCV_FEATURE_DEBUG’
> undeclared (first use in this function); did you mean
> ‘RISCV_FEATURE_EPMP’?
>  228 |     return riscv_feature(env, RISCV_FEATURE_DEBUG);
>      |                               ^~~~~~~~~~~~~~~~~~~
>      |                               RISCV_FEATURE_EPMP
> ../target/riscv/machine.c:228:31: note: each undeclared identifier is
> reported only once for each function it appears in
> ../target/riscv/machine.c:229:1: warning: control reaches end of
> non-void function [-Wreturn-type]
>  229 | }
>      | ^

That's weird. Maybe it's out of sync or merge conflict? I will take a look.

Regards,
Bin


WARNING: multiple messages have this Message-ID (diff)
From: Bin Meng <bmeng.cn@gmail.com>
To: Alistair Francis <alistair23@gmail.com>
Cc: Alistair Francis <Alistair.Francis@wdc.com>,
	 "qemu-devel@nongnu.org Developers" <qemu-devel@nongnu.org>,
	"open list:RISC-V" <qemu-riscv@nongnu.org>,
	 Bin Meng <bin.meng@windriver.com>
Subject: Re: [PATCH v4 2/7] target/riscv: machine: Add debug state description
Date: Wed, 20 Apr 2022 15:33:24 +0800	[thread overview]
Message-ID: <CAEUhbmX0SdEcD8UWJUmmPm2SubT6gd991jNMAZJA8WFbRsdoaQ@mail.gmail.com> (raw)
In-Reply-To: <CAKmqyKMoRqbfSsUNM1O1cQGHaL9rc6fsCqJxEktQNrgrLCimgA@mail.gmail.com>

On Wed, Apr 20, 2022 at 3:31 PM Alistair Francis <alistair23@gmail.com> wrote:
>
> On Tue, Mar 15, 2022 at 5:17 PM Bin Meng <bmeng.cn@gmail.com> wrote:
> >
> > From: Bin Meng <bin.meng@windriver.com>
> >
> > Add a subsection to machine.c to migrate debug CSR state.
> >
> > Signed-off-by: Bin Meng <bin.meng@windriver.com>
> > Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
> > ---
> >
> > (no changes since v2)
> >
> > Changes in v2:
> > - new patch: add debug state description
> >
> >  target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++
> >  1 file changed, 32 insertions(+)
> >
> > diff --git a/target/riscv/machine.c b/target/riscv/machine.c
> > index 5178b3fec9..4921dad09d 100644
> > --- a/target/riscv/machine.c
> > +++ b/target/riscv/machine.c
> > @@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = {
> >          VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
> >          VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
> >          VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
> > +        VMSTATE_END_OF_LIST()
> > +    }
> > +};
> > +
> > +static bool debug_needed(void *opaque)
> > +{
> > +    RISCVCPU *cpu = opaque;
> > +    CPURISCVState *env = &cpu->env;
> > +
> > +    return riscv_feature(env, RISCV_FEATURE_DEBUG);
>
> This fails to build:
>
> ../target/riscv/machine.c: In function ‘debug_needed’:
> ../target/riscv/machine.c:228:31: error: ‘RISCV_FEATURE_DEBUG’
> undeclared (first use in this function); did you mean
> ‘RISCV_FEATURE_EPMP’?
>  228 |     return riscv_feature(env, RISCV_FEATURE_DEBUG);
>      |                               ^~~~~~~~~~~~~~~~~~~
>      |                               RISCV_FEATURE_EPMP
> ../target/riscv/machine.c:228:31: note: each undeclared identifier is
> reported only once for each function it appears in
> ../target/riscv/machine.c:229:1: warning: control reaches end of
> non-void function [-Wreturn-type]
>  229 | }
>      | ^

That's weird. Maybe it's out of sync or merge conflict? I will take a look.

Regards,
Bin


  reply	other threads:[~2022-04-20  7:39 UTC|newest]

Thread overview: 35+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-15  6:55 [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Bin Meng
2022-03-15  6:55 ` [PATCH v4 1/7] target/riscv: Add initial support for the Sdtrig extension Bin Meng
2022-03-18  2:11   ` Alistair Francis
2022-03-18  2:11     ` Alistair Francis
2022-03-15  6:55 ` [PATCH v4 2/7] target/riscv: machine: Add debug state description Bin Meng
2022-04-20  7:30   ` Alistair Francis
2022-04-20  7:30     ` Alistair Francis
2022-04-20  7:33     ` Bin Meng [this message]
2022-04-20  7:33       ` Bin Meng
2022-04-20  9:52       ` Bin Meng
2022-04-20  9:52         ` Bin Meng
2022-04-20 22:45         ` Alistair Francis
2022-04-20 22:45           ` Alistair Francis
2022-04-20 23:46           ` Bin Meng
2022-04-20 23:46             ` Bin Meng
2022-04-21  0:13             ` Alistair Francis
2022-04-21  0:13               ` Alistair Francis
2022-04-21  0:19               ` Bin Meng
2022-04-21  0:19                 ` Bin Meng
2022-04-21 15:51             ` Richard Henderson
2022-04-21 15:51               ` Richard Henderson
2022-04-22  1:22               ` Bin Meng
2022-04-22  1:22                 ` Bin Meng
2022-03-15  6:55 ` [PATCH v4 3/7] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng
2022-03-15  6:55 ` [PATCH v4 4/7] target/riscv: cpu: Add a config option for native debug Bin Meng
2022-03-15  6:55 ` [PATCH v4 5/7] target/riscv: csr: Hook debug CSR read/write Bin Meng
2022-03-18  2:14   ` Alistair Francis
2022-03-18  2:14     ` Alistair Francis
2022-03-15  6:55 ` [PATCH v4 6/7] target/riscv: cpu: Enable native debug feature Bin Meng
2022-03-18  2:17   ` Alistair Francis
2022-03-18  2:17     ` Alistair Francis
2022-03-15  6:55 ` [PATCH v4 7/7] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Bin Meng
2022-03-15  6:55   ` Bin Meng
2022-03-18  7:38 ` [PATCH v4 0/7] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Alistair Francis
2022-03-18  7:38   ` Alistair Francis

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