* [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor slpc shared data access to use iosys_map
@ 2022-03-16 12:56 Mullati Siva
2022-03-16 12:56 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert slpc to iosys_map Mullati Siva
` (3 more replies)
0 siblings, 4 replies; 9+ messages in thread
From: Mullati Siva @ 2022-03-16 12:56 UTC (permalink / raw)
To: intel-gfx, siva.mullati; +Cc: lucas.demarchi
From: Siva Mullati <siva.mullati@intel.com>
This is continuation to the original patch series to use iosys map
APIs to use slpc shared data commands and descriptors.
https://patchwork.freedesktop.org/series/99711/
Siva Mullati (1):
drm/i915/guc: Convert slpc to iosys_map
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 79 +++++++++++--------
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 5 +-
2 files changed, 47 insertions(+), 37 deletions(-)
--
2.33.0
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert slpc to iosys_map
2022-03-16 12:56 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor slpc shared data access to use iosys_map Mullati Siva
@ 2022-03-16 12:56 ` Mullati Siva
2022-04-18 11:03 ` Balasubramani Vivekanandan
2022-03-16 13:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor slpc shared data access to use iosys_map Patchwork
` (2 subsequent siblings)
3 siblings, 1 reply; 9+ messages in thread
From: Mullati Siva @ 2022-03-16 12:56 UTC (permalink / raw)
To: intel-gfx, siva.mullati; +Cc: lucas.demarchi
From: Siva Mullati <siva.mullati@intel.com>
Convert slpc shared data to use iosys_map rather than
plain pointer and save it in the intel_guc_slpc struct.
This will help with in read and update slpc shared data
after the slpc init by abstracting the IO vs system memory.
Signed-off-by: Siva Mullati <siva.mullati@intel.com>
---
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 79 +++++++++++--------
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 5 +-
2 files changed, 47 insertions(+), 37 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
index 9f032c65a488..3a9ec6b03ceb 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
@@ -14,6 +14,13 @@
#include "gt/intel_gt_regs.h"
#include "gt/intel_rps.h"
+#define slpc_blob_read(slpc_, field_) \
+ iosys_map_rd_field(&(slpc_)->slpc_map, 0, \
+ struct slpc_shared_data, field_)
+#define slpc_blob_write(slpc_, field_, val_) \
+ iosys_map_wr_field(&(slpc_)->slpc_map, 0, \
+ struct slpc_shared_data, field_, val_)
+
static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
{
return container_of(slpc, struct intel_guc, slpc);
@@ -52,50 +59,50 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
slpc->selected = __guc_slpc_selected(guc);
}
-static void slpc_mem_set_param(struct slpc_shared_data *data,
+static void slpc_mem_set_param(struct intel_guc_slpc *slpc,
u32 id, u32 value)
{
+ u32 bits = slpc_blob_read(slpc, override_params.bits[id >> 5]);
+
GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS);
/*
* When the flag bit is set, corresponding value will be read
* and applied by SLPC.
*/
- data->override_params.bits[id >> 5] |= (1 << (id % 32));
- data->override_params.values[id] = value;
+ bits |= (1 << (id % 32));
+ slpc_blob_write(slpc, override_params.bits[id >> 5], bits);
+ slpc_blob_write(slpc, override_params.values[id], value);
}
-static void slpc_mem_set_enabled(struct slpc_shared_data *data,
+static void slpc_mem_set_enabled(struct intel_guc_slpc *slpc,
u8 enable_id, u8 disable_id)
{
/*
* Enabling a param involves setting the enable_id
* to 1 and disable_id to 0.
*/
- slpc_mem_set_param(data, enable_id, 1);
- slpc_mem_set_param(data, disable_id, 0);
+ slpc_mem_set_param(slpc, enable_id, 1);
+ slpc_mem_set_param(slpc, disable_id, 0);
}
-static void slpc_mem_set_disabled(struct slpc_shared_data *data,
+static void slpc_mem_set_disabled(struct intel_guc_slpc *slpc,
u8 enable_id, u8 disable_id)
{
/*
* Disabling a param involves setting the enable_id
* to 0 and disable_id to 1.
*/
- slpc_mem_set_param(data, disable_id, 1);
- slpc_mem_set_param(data, enable_id, 0);
+ slpc_mem_set_param(slpc, disable_id, 1);
+ slpc_mem_set_param(slpc, enable_id, 0);
}
static u32 slpc_get_state(struct intel_guc_slpc *slpc)
{
- struct slpc_shared_data *data;
-
GEM_BUG_ON(!slpc->vma);
- drm_clflush_virt_range(slpc->vaddr, sizeof(u32));
- data = slpc->vaddr;
+ drm_clflush_virt_range(slpc->slpc_map.vaddr, sizeof(u32));
- return data->header.global_state;
+ return slpc_blob_read(slpc, header.global_state);
}
static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
@@ -156,7 +163,7 @@ static int slpc_query_task_state(struct intel_guc_slpc *slpc)
drm_err(&i915->drm, "Failed to query task state (%pe)\n",
ERR_PTR(ret));
- drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
+ drm_clflush_virt_range(slpc->slpc_map.vaddr, SLPC_PAGE_SIZE_BYTES);
return ret;
}
@@ -243,10 +250,11 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
struct drm_i915_private *i915 = slpc_to_i915(slpc);
u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
int err;
+ void *vaddr;
GEM_BUG_ON(slpc->vma);
- err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&slpc->vaddr);
+ err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&vaddr);
if (unlikely(err)) {
drm_err(&i915->drm,
"Failed to allocate SLPC struct (err=%pe)\n",
@@ -254,6 +262,12 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
return err;
}
+ if (i915_gem_object_is_lmem(slpc->vma->obj))
+ iosys_map_set_vaddr_iomem(&slpc->slpc_map,
+ (void __iomem *)vaddr);
+ else
+ iosys_map_set_vaddr(&slpc->slpc_map, vaddr);
+
slpc->max_freq_softlimit = 0;
slpc->min_freq_softlimit = 0;
@@ -335,40 +349,37 @@ static int slpc_reset(struct intel_guc_slpc *slpc)
static u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
{
- struct slpc_shared_data *data = slpc->vaddr;
-
GEM_BUG_ON(!slpc->vma);
return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK,
- data->task_state_data.freq) *
+ slpc_blob_read(slpc, task_state_data.freq)) *
GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
}
static u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
{
- struct slpc_shared_data *data = slpc->vaddr;
-
GEM_BUG_ON(!slpc->vma);
return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK,
- data->task_state_data.freq) *
+ slpc_blob_read(slpc, task_state_data.freq)) *
GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
}
-static void slpc_shared_data_reset(struct slpc_shared_data *data)
+static void slpc_shared_data_reset(struct intel_guc_slpc *slpc)
{
- memset(data, 0, sizeof(struct slpc_shared_data));
-
- data->header.size = sizeof(struct slpc_shared_data);
+ iosys_map_memset(&slpc->slpc_map,
+ 0, 0, sizeof(struct slpc_shared_data));
+ slpc_blob_write(slpc,
+ header.size, sizeof(struct slpc_shared_data));
/* Enable only GTPERF task, disable others */
- slpc_mem_set_enabled(data, SLPC_PARAM_TASK_ENABLE_GTPERF,
+ slpc_mem_set_enabled(slpc, SLPC_PARAM_TASK_ENABLE_GTPERF,
SLPC_PARAM_TASK_DISABLE_GTPERF);
- slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_BALANCER,
+ slpc_mem_set_disabled(slpc, SLPC_PARAM_TASK_ENABLE_BALANCER,
SLPC_PARAM_TASK_DISABLE_BALANCER);
- slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_DCC,
+ slpc_mem_set_disabled(slpc, SLPC_PARAM_TASK_ENABLE_DCC,
SLPC_PARAM_TASK_DISABLE_DCC);
}
@@ -617,7 +628,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
GEM_BUG_ON(!slpc->vma);
- slpc_shared_data_reset(slpc->vaddr);
+ slpc_shared_data_reset(slpc);
ret = slpc_reset(slpc);
if (unlikely(ret < 0)) {
@@ -705,8 +716,6 @@ void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc)
int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p)
{
struct drm_i915_private *i915 = slpc_to_i915(slpc);
- struct slpc_shared_data *data = slpc->vaddr;
- struct slpc_task_state_data *slpc_tasks;
intel_wakeref_t wakeref;
int ret = 0;
@@ -716,11 +725,10 @@ int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p
ret = slpc_query_task_state(slpc);
if (!ret) {
- slpc_tasks = &data->task_state_data;
-
drm_printf(p, "\tSLPC state: %s\n", slpc_get_state_string(slpc));
drm_printf(p, "\tGTPERF task active: %s\n",
- str_yes_no(slpc_tasks->status & SLPC_GTPERF_TASK_ENABLED));
+ str_yes_no(slpc_blob_read(slpc, task_state_data.status) &
+ SLPC_GTPERF_TASK_ENABLED));
drm_printf(p, "\tMax freq: %u MHz\n",
slpc_decode_max_freq(slpc));
drm_printf(p, "\tMin freq: %u MHz\n",
@@ -739,4 +747,5 @@ void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
return;
i915_vma_unpin_and_release(&slpc->vma, I915_VMA_RELEASE_MAP);
+ iosys_map_clear(&slpc->slpc_map);
}
diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
index bf5b9a563c09..96f524f25b52 100644
--- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
+++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
@@ -7,15 +7,16 @@
#define _INTEL_GUC_SLPC_TYPES_H_
#include <linux/atomic.h>
-#include <linux/workqueue.h>
+#include <linux/iosys-map.h>
#include <linux/mutex.h>
#include <linux/types.h>
+#include <linux/workqueue.h>
#define SLPC_RESET_TIMEOUT_MS 5
struct intel_guc_slpc {
struct i915_vma *vma;
- struct slpc_shared_data *vaddr;
+ struct iosys_map slpc_map;
bool supported;
bool selected;
--
2.33.0
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor slpc shared data access to use iosys_map
2022-03-16 12:56 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor slpc shared data access to use iosys_map Mullati Siva
2022-03-16 12:56 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert slpc to iosys_map Mullati Siva
@ 2022-03-16 13:37 ` Patchwork
2022-03-16 14:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-16 15:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-03-16 13:37 UTC (permalink / raw)
To: Mullati Siva; +Cc: intel-gfx
== Series Details ==
Series: drm/i915/guc: Refactor slpc shared data access to use iosys_map
URL : https://patchwork.freedesktop.org/series/101430/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/guc: Refactor slpc shared data access to use iosys_map
2022-03-16 12:56 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor slpc shared data access to use iosys_map Mullati Siva
2022-03-16 12:56 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert slpc to iosys_map Mullati Siva
2022-03-16 13:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor slpc shared data access to use iosys_map Patchwork
@ 2022-03-16 14:13 ` Patchwork
2022-03-16 15:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-03-16 14:13 UTC (permalink / raw)
To: Mullati Siva; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 13353 bytes --]
== Series Details ==
Series: drm/i915/guc: Refactor slpc shared data access to use iosys_map
URL : https://patchwork.freedesktop.org/series/101430/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11368 -> Patchwork_22585
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/index.html
Participating hosts (48 -> 44)
------------------------------
Additional (4): bat-rpls-1 bat-dg2-9 bat-dg1-6 bat-dg1-5
Missing (8): shard-tglu fi-hsw-4200u fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 shard-rkl shard-dg1 fi-bdw-samus
Known issues
------------
Here are the changes found in Patchwork_22585 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@fbdev@eof:
- bat-dg1-5: NOTRUN -> [SKIP][1] ([i915#2582]) +4 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@fbdev@eof.html
* igt@gem_exec_gttfill@basic:
- bat-dg1-6: NOTRUN -> [SKIP][2] ([i915#4086])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@gem_exec_gttfill@basic.html
- bat-dg1-5: NOTRUN -> [SKIP][3] ([i915#4086])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@gem_exec_gttfill@basic.html
* igt@gem_mmap@basic:
- bat-dg1-5: NOTRUN -> [SKIP][4] ([i915#4083])
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@gem_mmap@basic.html
- bat-dg1-6: NOTRUN -> [SKIP][5] ([i915#4083])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@gem_mmap@basic.html
* igt@gem_mmap_gtt@basic:
- bat-dg1-5: NOTRUN -> [SKIP][6] ([i915#4077]) +2 similar issues
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@gem_mmap_gtt@basic.html
* igt@gem_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#4077]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#4079]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@gem_tiled_pread_basic.html
- bat-dg1-5: NOTRUN -> [SKIP][9] ([i915#4079]) +1 similar issue
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- bat-dg1-5: NOTRUN -> [SKIP][10] ([i915#1155])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@i915_pm_backlight@basic-brightness.html
- bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#1155])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rps@basic-api:
- bat-dg1-6: NOTRUN -> [FAIL][12] ([i915#4032])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@hangcheck:
- bat-dg1-5: NOTRUN -> [DMESG-FAIL][13] ([i915#4957])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@i915_selftest@live@hangcheck.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][14] ([i915#4212]) +7 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-5: NOTRUN -> [SKIP][15] ([i915#4215])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@kms_addfb_basic@basic-y-tiled-legacy.html
- bat-dg1-6: NOTRUN -> [SKIP][16] ([i915#4215])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- bat-dg1-5: NOTRUN -> [SKIP][17] ([i915#4212]) +7 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_busy@basic:
- bat-dg1-5: NOTRUN -> [SKIP][18] ([i915#4303])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@kms_busy@basic.html
* igt@kms_chamelium@dp-hpd-fast:
- bat-dg1-5: NOTRUN -> [SKIP][19] ([fdo#111827]) +8 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-edid-read:
- bat-dg1-6: NOTRUN -> [SKIP][20] ([fdo#111827]) +8 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- bat-dg1-5: NOTRUN -> [SKIP][21] ([i915#4103] / [i915#4213]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- bat-dg1-6: NOTRUN -> [SKIP][22] ([i915#4103] / [i915#4213]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-6: NOTRUN -> [SKIP][23] ([fdo#109285])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@kms_force_connector_basic@force-load-detect.html
- bat-dg1-5: NOTRUN -> [SKIP][24] ([fdo#109285])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- bat-dg1-5: NOTRUN -> [SKIP][25] ([i915#4078] / [i915#5341])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-a:
- bat-dg1-5: NOTRUN -> [SKIP][26] ([i915#4078]) +23 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@kms_pipe_crc_basic@hang-read-crc-pipe-a.html
* igt@kms_psr@cursor_plane_move:
- bat-dg1-6: NOTRUN -> [SKIP][27] ([i915#1072] / [i915#4078]) +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@primary_page_flip:
- bat-dg1-5: NOTRUN -> [SKIP][28] ([i915#1072] / [i915#4078]) +3 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@kms_psr@primary_page_flip.html
* igt@kms_setmode@basic-clone-single-crtc:
- bat-dg1-6: NOTRUN -> [SKIP][29] ([i915#3555])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg1-5: NOTRUN -> [SKIP][30] ([i915#3555])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg1-5: NOTRUN -> [SKIP][31] ([i915#3708]) +3 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@prime_vgem@basic-fence-flip.html
- bat-dg1-6: NOTRUN -> [SKIP][32] ([i915#3708]) +3 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-fence-mmap:
- bat-dg1-5: NOTRUN -> [SKIP][33] ([i915#3708] / [i915#4077]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@prime_vgem@basic-fence-mmap.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-6: NOTRUN -> [SKIP][34] ([i915#3708] / [i915#4077]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-userptr:
- bat-dg1-6: NOTRUN -> [SKIP][35] ([i915#3708] / [i915#4873])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-6/igt@prime_vgem@basic-userptr.html
- bat-dg1-5: NOTRUN -> [SKIP][36] ([i915#3708] / [i915#4873])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-dg1-5/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-bdw-5557u: NOTRUN -> [FAIL][37] ([i915#2426] / [i915#4312])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/fi-bdw-5557u/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_selftest@live@hugepages:
- {bat-rpls-2}: [DMESG-WARN][38] ([i915#5278]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/bat-rpls-2/igt@i915_selftest@live@hugepages.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-rpls-2/igt@i915_selftest@live@hugepages.html
* igt@i915_selftest@live@sanitycheck:
- {bat-rpls-2}: [DMESG-WARN][40] ([i915#4391]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/bat-rpls-2/igt@i915_selftest@live@sanitycheck.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-rpls-2/igt@i915_selftest@live@sanitycheck.html
* igt@kms_flip@basic-flip-vs-modeset@a-edp1:
- {bat-adlp-6}: [DMESG-WARN][42] ([i915#3576]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2426]: https://gitlab.freedesktop.org/drm/intel/issues/2426
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#4032]: https://gitlab.freedesktop.org/drm/intel/issues/4032
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4086]: https://gitlab.freedesktop.org/drm/intel/issues/4086
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4303]: https://gitlab.freedesktop.org/drm/intel/issues/4303
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5192]: https://gitlab.freedesktop.org/drm/intel/issues/5192
[i915#5193]: https://gitlab.freedesktop.org/drm/intel/issues/5193
[i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
[i915#5276]: https://gitlab.freedesktop.org/drm/intel/issues/5276
[i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
[i915#5323]: https://gitlab.freedesktop.org/drm/intel/issues/5323
[i915#5339]: https://gitlab.freedesktop.org/drm/intel/issues/5339
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5342]: https://gitlab.freedesktop.org/drm/intel/issues/5342
Build changes
-------------
* Linux: CI_DRM_11368 -> Patchwork_22585
CI-20190529: 20190529
CI_DRM_11368: 66b3d1ac616565206cddf4327ca7c102b651b032 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6382: a6a5a178cb1cbe0dab8d8d092a4aee932ccb93cc @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22585: c85bd165867c45ba22073ba278d819183e28f9e5 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
c85bd165867c drm/i915/guc: Convert slpc to iosys_map
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/index.html
[-- Attachment #2: Type: text/html, Size: 15590 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/guc: Refactor slpc shared data access to use iosys_map
2022-03-16 12:56 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor slpc shared data access to use iosys_map Mullati Siva
` (2 preceding siblings ...)
2022-03-16 14:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-03-16 15:36 ` Patchwork
3 siblings, 0 replies; 9+ messages in thread
From: Patchwork @ 2022-03-16 15:36 UTC (permalink / raw)
To: Mullati Siva; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30287 bytes --]
== Series Details ==
Series: drm/i915/guc: Refactor slpc shared data access to use iosys_map
URL : https://patchwork.freedesktop.org/series/101430/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11368_full -> Patchwork_22585_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22585_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22585_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (12 -> 10)
------------------------------
Missing (2): shard-rkl shard-tglu
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22585_full:
### Piglit changes ###
#### Possible regressions ####
* spec@ext_transform_feedback@query-primitives_written-bufferrange:
- pig-kbl-iris: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/pig-kbl-iris/spec@ext_transform_feedback@query-primitives_written-bufferrange.html
Known issues
------------
Here are the changes found in Patchwork_22585_full that come from known issues:
### CI changes ###
#### Possible fixes ####
* boot:
- shard-glk: ([PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [FAIL][26]) ([i915#4392]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [PASS][49], [PASS][50], [PASS][51])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk9/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk9/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk9/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk9/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk8/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk8/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk8/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk7/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk7/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk6/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk6/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk6/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk5/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk5/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk5/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk4/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk4/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk3/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk3/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk2/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk2/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk1/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk1/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk1/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk4/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk5/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk5/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk3/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk6/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk4/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk6/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk3/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk3/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk2/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk2/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk6/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk6/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk6/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk7/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk2/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk1/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk7/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk8/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk8/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk1/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk9/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk9/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk9/boot.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk1/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_capture@pi@rcs0:
- shard-skl: [PASS][52] -> [INCOMPLETE][53] ([i915#4547])
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl6/igt@gem_exec_capture@pi@rcs0.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl6/igt@gem_exec_capture@pi@rcs0.html
* igt@gem_exec_fair@basic-deadline:
- shard-glk: [PASS][54] -> [FAIL][55] ([i915#2846])
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk9/igt@gem_exec_fair@basic-deadline.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk6/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none@vcs1:
- shard-iclb: NOTRUN -> [FAIL][56] ([i915#2842])
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-iclb4/igt@gem_exec_fair@basic-none@vcs1.html
* igt@gem_exec_fair@basic-pace@rcs0:
- shard-kbl: [PASS][57] -> [FAIL][58] ([i915#2851]) +1 similar issue
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl4/igt@gem_exec_fair@basic-pace@rcs0.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl3/igt@gem_exec_fair@basic-pace@rcs0.html
* igt@gem_exec_fair@basic-pace@vecs0:
- shard-kbl: [PASS][59] -> [SKIP][60] ([fdo#109271])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl4/igt@gem_exec_fair@basic-pace@vecs0.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl3/igt@gem_exec_fair@basic-pace@vecs0.html
* igt@gem_exec_whisper@basic-fds:
- shard-glk: [PASS][61] -> [DMESG-WARN][62] ([i915#118]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk8/igt@gem_exec_whisper@basic-fds.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk1/igt@gem_exec_whisper@basic-fds.html
* igt@gem_huc_copy@huc-copy:
- shard-skl: NOTRUN -> [SKIP][63] ([fdo#109271] / [i915#2190])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl7/igt@gem_huc_copy@huc-copy.html
* igt@gem_media_vme:
- shard-skl: NOTRUN -> [SKIP][64] ([fdo#109271]) +56 similar issues
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl7/igt@gem_media_vme.html
* igt@gem_render_copy@y-tiled-to-vebox-x-tiled:
- shard-glk: NOTRUN -> [SKIP][65] ([fdo#109271]) +48 similar issues
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk3/igt@gem_render_copy@y-tiled-to-vebox-x-tiled.html
* igt@gem_userptr_blits@access-control:
- shard-iclb: NOTRUN -> [SKIP][66] ([i915#3297])
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-iclb7/igt@gem_userptr_blits@access-control.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [PASS][67] -> [DMESG-WARN][68] ([i915#1436] / [i915#716])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl10/igt@gen9_exec_parse@allowed-single.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl7/igt@gen9_exec_parse@allowed-single.html
* igt@kms_async_flips@alternate-sync-async-flip:
- shard-skl: [PASS][69] -> [FAIL][70] ([i915#2521])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl9/igt@kms_async_flips@alternate-sync-async-flip.html
* igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][71] ([i915#3743])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-skl: NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#3777]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl2/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#3886]) +1 similar issue
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl3/igt@kms_ccs@pipe-b-crc-primary-rotation-180-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs:
- shard-glk: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#3886]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk3/igt@kms_ccs@pipe-b-missing-ccs-buffer-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#3886]) +3 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl1/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-c-bad-rotation-90-yf_tiled_ccs:
- shard-kbl: NOTRUN -> [SKIP][76] ([fdo#109271]) +11 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl3/igt@kms_ccs@pipe-c-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_chamelium@dp-frame-dump:
- shard-skl: NOTRUN -> [SKIP][77] ([fdo#109271] / [fdo#111827]) +4 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl7/igt@kms_chamelium@dp-frame-dump.html
* igt@kms_color_chamelium@pipe-a-ctm-0-25:
- shard-kbl: NOTRUN -> [SKIP][78] ([fdo#109271] / [fdo#111827])
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl3/igt@kms_color_chamelium@pipe-a-ctm-0-25.html
* igt@kms_color_chamelium@pipe-b-ctm-green-to-red:
- shard-glk: NOTRUN -> [SKIP][79] ([fdo#109271] / [fdo#111827]) +1 similar issue
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk3/igt@kms_color_chamelium@pipe-b-ctm-green-to-red.html
* igt@kms_cursor_crc@pipe-b-cursor-512x512-offscreen:
- shard-iclb: NOTRUN -> [SKIP][80] ([fdo#109278] / [fdo#109279])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-iclb7/igt@kms_cursor_crc@pipe-b-cursor-512x512-offscreen.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-apl: [PASS][81] -> [DMESG-WARN][82] ([i915#180]) +5 similar issues
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-apl7/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-apl1/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@a-edp1:
- shard-skl: [PASS][83] -> [FAIL][84] ([i915#79])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl10/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
* igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
- shard-skl: [PASS][85] -> [FAIL][86] ([i915#2122]) +2 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl2/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-iclb: [PASS][87] -> [SKIP][88] ([i915#3701]) +1 similar issue
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-iclb6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_hdr@bpc-switch@bpc-switch-edp-1-pipe-a:
- shard-skl: [PASS][89] -> [FAIL][90] ([i915#1188])
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl10/igt@kms_hdr@bpc-switch@bpc-switch-edp-1-pipe-a.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl8/igt@kms_hdr@bpc-switch@bpc-switch-edp-1-pipe-a.html
* igt@kms_lease@cursor_implicit_plane:
- shard-kbl: [PASS][91] -> [DMESG-WARN][92] ([i915#1982])
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl3/igt@kms_lease@cursor_implicit_plane.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl6/igt@kms_lease@cursor_implicit_plane.html
* igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes:
- shard-kbl: [PASS][93] -> [DMESG-WARN][94] ([i915#180])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl3/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl4/igt@kms_plane@plane-panning-bottom-right-suspend@pipe-b-planes.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: NOTRUN -> [FAIL][95] ([fdo#108145] / [i915#265])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl2/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [PASS][96] -> [FAIL][97] ([fdo#108145] / [i915#265])
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl4/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale:
- shard-iclb: [PASS][98] -> [SKIP][99] ([i915#5235]) +2 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-iclb6/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-iclb2/igt@kms_plane_scaling@planes-downscale-factor-0-5@pipe-a-edp-1-planes-downscale.html
* igt@kms_psr@psr2_basic:
- shard-iclb: [PASS][100] -> [SKIP][101] ([fdo#109441]) +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-iclb2/igt@kms_psr@psr2_basic.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-iclb3/igt@kms_psr@psr2_basic.html
* igt@kms_sysfs_edid_timing:
- shard-skl: NOTRUN -> [FAIL][102] ([IGT#2])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl2/igt@kms_sysfs_edid_timing.html
* igt@perf@short-reads:
- shard-skl: [PASS][103] -> [FAIL][104] ([i915#51])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl4/igt@perf@short-reads.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl2/igt@perf@short-reads.html
* igt@sysfs_clients@split-10:
- shard-skl: NOTRUN -> [SKIP][105] ([fdo#109271] / [i915#2994]) +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl2/igt@sysfs_clients@split-10.html
#### Possible fixes ####
* igt@gem_exec_fair@basic-none@vecs0:
- shard-kbl: [FAIL][106] ([i915#2842]) -> [PASS][107] +1 similar issue
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl4/igt@gem_exec_fair@basic-none@vecs0.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl6/igt@gem_exec_fair@basic-none@vecs0.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [SKIP][108] ([i915#4281]) -> [PASS][109]
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-iclb4/igt@i915_pm_dc@dc9-dpms.html
* igt@kms_big_fb@y-tiled-16bpp-rotate-0:
- shard-iclb: [DMESG-WARN][110] ([i915#1888] / [i915#3891]) -> [PASS][111]
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-iclb8/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-iclb7/igt@kms_big_fb@y-tiled-16bpp-rotate-0.html
* igt@kms_cursor_crc@pipe-c-cursor-suspend:
- shard-kbl: [DMESG-WARN][112] ([i915#180]) -> [PASS][113]
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl3/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
* igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1:
- shard-glk: [FAIL][114] ([i915#79]) -> [PASS][115]
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-glk6/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-glk9/igt@kms_flip@flip-vs-expired-vblank@c-hdmi-a1.html
* igt@kms_flip@flip-vs-suspend@a-dp1:
- shard-apl: [DMESG-WARN][116] ([i915#180]) -> [PASS][117]
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-apl3/igt@kms_flip@flip-vs-suspend@a-dp1.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-apl2/igt@kms_flip@flip-vs-suspend@a-dp1.html
* igt@kms_flip@flip-vs-suspend@b-edp1:
- shard-skl: [INCOMPLETE][118] ([i915#4839] / [i915#636]) -> [PASS][119]
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl4/igt@kms_flip@flip-vs-suspend@b-edp1.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl2/igt@kms_flip@flip-vs-suspend@b-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling:
- shard-iclb: [SKIP][120] ([i915#3701]) -> [PASS][121]
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-iclb4/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytile-downscaling.html
* igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-edp-1-pipe-a:
- shard-skl: [FAIL][122] ([i915#1188]) -> [PASS][123]
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl8/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-edp-1-pipe-a.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl6/igt@kms_hdr@bpc-switch-suspend@bpc-switch-suspend-edp-1-pipe-a.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-iclb: [SKIP][124] ([fdo#109642] / [fdo#111068] / [i915#658]) -> [PASS][125]
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-iclb6/igt@kms_psr2_su@frontbuffer-xrgb8888.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-iclb2/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_suspend:
- shard-iclb: [SKIP][126] ([fdo#109441]) -> [PASS][127] +1 similar issue
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-iclb1/igt@kms_psr@psr2_suspend.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-iclb2/igt@kms_psr@psr2_suspend.html
* igt@sysfs_heartbeat_interval@mixed@bcs0:
- shard-skl: [WARN][128] ([i915#4055]) -> [PASS][129]
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl1/igt@sysfs_heartbeat_interval@mixed@bcs0.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl10/igt@sysfs_heartbeat_interval@mixed@bcs0.html
* igt@sysfs_heartbeat_interval@mixed@vcs0:
- shard-skl: [FAIL][130] ([i915#1731]) -> [PASS][131]
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl1/igt@sysfs_heartbeat_interval@mixed@vcs0.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl10/igt@sysfs_heartbeat_interval@mixed@vcs0.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [SKIP][132] ([i915#4525]) -> [DMESG-WARN][133] ([i915#5076])
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-iclb6/igt@gem_exec_balancer@parallel-contexts.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-iclb2/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-pace@vcs0:
- shard-kbl: [SKIP][134] ([fdo#109271]) -> [FAIL][135] ([i915#2842])
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs0.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl3/igt@gem_exec_fair@basic-pace@vcs0.html
* igt@i915_pm_rc6_residency@rc6-fence:
- shard-iclb: [WARN][136] ([i915#2684]) -> [WARN][137] ([i915#1804] / [i915#2684])
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-iclb2/igt@i915_pm_rc6_residency@rc6-fence.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-iclb4/igt@i915_pm_rc6_residency@rc6-fence.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [WARN][138] ([i915#1804] / [i915#2684]) -> [WARN][139] ([i915#2684])
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-iclb4/igt@i915_pm_rc6_residency@rc6-idle.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-iclb5/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1:
- shard-skl: [FAIL][140] ([i915#79]) -> [FAIL][141] ([i915#2122])
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-edp1.html
* igt@runner@aborted:
- shard-kbl: ([FAIL][142], [FAIL][143], [FAIL][144], [FAIL][145], [FAIL][146], [FAIL][147], [FAIL][148], [FAIL][149], [FAIL][150], [FAIL][151], [FAIL][152]) ([i915#1436] / [i915#1814] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][153], [FAIL][154], [FAIL][155], [FAIL][156], [FAIL][157], [FAIL][158], [FAIL][159], [FAIL][160], [FAIL][161], [FAIL][162], [FAIL][163]) ([i915#1814] / [i915#3002] / [i915#4312] / [i915#5257])
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl4/igt@runner@aborted.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl6/igt@runner@aborted.html
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl7/igt@runner@aborted.html
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl7/igt@runner@aborted.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl1/igt@runner@aborted.html
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl1/igt@runner@aborted.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl1/igt@runner@aborted.html
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl1/igt@runner@aborted.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl1/igt@runner@aborted.html
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl3/igt@runner@aborted.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-kbl7/igt@runner@aborted.html
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl4/igt@runner@aborted.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl4/igt@runner@aborted.html
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl4/igt@runner@aborted.html
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl7/igt@runner@aborted.html
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl4/igt@runner@aborted.html
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl3/igt@runner@aborted.html
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl4/igt@runner@aborted.html
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl6/igt@runner@aborted.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl1/igt@runner@aborted.html
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl4/igt@runner@aborted.html
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-kbl3/igt@runner@aborted.html
- shard-apl: ([FAIL][164], [FAIL][165], [FAIL][166], [FAIL][167], [FAIL][168], [FAIL][169]) ([i915#180] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][170], [FAIL][171], [FAIL][172], [FAIL][173], [FAIL][174], [FAIL][175], [FAIL][176], [FAIL][177], [FAIL][178], [FAIL][179]) ([fdo#109271] / [i915#180] / [i915#1814] / [i915#3002] / [i915#4312] / [i915#5257])
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-apl7/igt@runner@aborted.html
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-apl2/igt@runner@aborted.html
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-apl2/igt@runner@aborted.html
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-apl6/igt@runner@aborted.html
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-apl4/igt@runner@aborted.html
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-apl3/igt@runner@aborted.html
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-apl2/igt@runner@aborted.html
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-apl8/igt@runner@aborted.html
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-apl1/igt@runner@aborted.html
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-apl2/igt@runner@aborted.html
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-apl4/igt@runner@aborted.html
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-apl4/igt@runner@aborted.html
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-apl8/igt@runner@aborted.html
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-apl8/igt@runner@aborted.html
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-apl7/igt@runner@aborted.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-apl6/igt@runner@aborted.html
- shard-skl: ([FAIL][180], [FAIL][181], [FAIL][182], [FAIL][183], [FAIL][184]) ([i915#2029] / [i915#3002] / [i915#4312] / [i915#5257]) -> ([FAIL][185], [FAIL][186], [FAIL][187], [FAIL][188], [FAIL][189]) ([i915#1436] / [i915#3002] / [i915#4312] / [i915#5257])
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl9/igt@runner@aborted.html
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl2/igt@runner@aborted.html
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl4/igt@runner@aborted.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl7/igt@runner@aborted.html
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11368/shard-skl6/igt@runner@aborted.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl8/igt@runner@aborted.html
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl6/igt@runner@aborted.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/shard-skl9/igt@runner@aborted.html
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22585/index.html
[-- Attachment #2: Type: text/html, Size: 32636 bytes --]
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert slpc to iosys_map
2022-03-16 12:56 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert slpc to iosys_map Mullati Siva
@ 2022-04-18 11:03 ` Balasubramani Vivekanandan
2022-04-19 8:17 ` Siva Mullati
0 siblings, 1 reply; 9+ messages in thread
From: Balasubramani Vivekanandan @ 2022-04-18 11:03 UTC (permalink / raw)
To: Mullati Siva, intel-gfx; +Cc: lucas.demarchi
On 16.03.2022 18:26, Mullati Siva wrote:
> From: Siva Mullati <siva.mullati@intel.com>
>
> Convert slpc shared data to use iosys_map rather than
> plain pointer and save it in the intel_guc_slpc struct.
> This will help with in read and update slpc shared data
> after the slpc init by abstracting the IO vs system memory.
>
> Signed-off-by: Siva Mullati <siva.mullati@intel.com>
> ---
> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 79 +++++++++++--------
> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 5 +-
> 2 files changed, 47 insertions(+), 37 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> index 9f032c65a488..3a9ec6b03ceb 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
> @@ -14,6 +14,13 @@
> #include "gt/intel_gt_regs.h"
> #include "gt/intel_rps.h"
>
> +#define slpc_blob_read(slpc_, field_) \
> + iosys_map_rd_field(&(slpc_)->slpc_map, 0, \
> + struct slpc_shared_data, field_)
> +#define slpc_blob_write(slpc_, field_, val_) \
> + iosys_map_wr_field(&(slpc_)->slpc_map, 0, \
> + struct slpc_shared_data, field_, val_)
> +
> static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
> {
> return container_of(slpc, struct intel_guc, slpc);
> @@ -52,50 +59,50 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
> slpc->selected = __guc_slpc_selected(guc);
> }
>
> -static void slpc_mem_set_param(struct slpc_shared_data *data,
> +static void slpc_mem_set_param(struct intel_guc_slpc *slpc,
> u32 id, u32 value)
> {
> + u32 bits = slpc_blob_read(slpc, override_params.bits[id >> 5]);
> +
> GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS);
> /*
> * When the flag bit is set, corresponding value will be read
> * and applied by SLPC.
> */
> - data->override_params.bits[id >> 5] |= (1 << (id % 32));
> - data->override_params.values[id] = value;
> + bits |= (1 << (id % 32));
> + slpc_blob_write(slpc, override_params.bits[id >> 5], bits);
> + slpc_blob_write(slpc, override_params.values[id], value);
> }
>
> -static void slpc_mem_set_enabled(struct slpc_shared_data *data,
> +static void slpc_mem_set_enabled(struct intel_guc_slpc *slpc,
> u8 enable_id, u8 disable_id)
> {
> /*
> * Enabling a param involves setting the enable_id
> * to 1 and disable_id to 0.
> */
> - slpc_mem_set_param(data, enable_id, 1);
> - slpc_mem_set_param(data, disable_id, 0);
> + slpc_mem_set_param(slpc, enable_id, 1);
> + slpc_mem_set_param(slpc, disable_id, 0);
> }
>
> -static void slpc_mem_set_disabled(struct slpc_shared_data *data,
> +static void slpc_mem_set_disabled(struct intel_guc_slpc *slpc,
> u8 enable_id, u8 disable_id)
> {
> /*
> * Disabling a param involves setting the enable_id
> * to 0 and disable_id to 1.
> */
> - slpc_mem_set_param(data, disable_id, 1);
> - slpc_mem_set_param(data, enable_id, 0);
> + slpc_mem_set_param(slpc, disable_id, 1);
> + slpc_mem_set_param(slpc, enable_id, 0);
> }
>
> static u32 slpc_get_state(struct intel_guc_slpc *slpc)
> {
> - struct slpc_shared_data *data;
> -
> GEM_BUG_ON(!slpc->vma);
>
> - drm_clflush_virt_range(slpc->vaddr, sizeof(u32));
> - data = slpc->vaddr;
> + drm_clflush_virt_range(slpc->slpc_map.vaddr, sizeof(u32));
clflush will not be required if the slpc_map contains io memory address.
So the drm_clflush_virt_range can be added under a check for system
memory
>
> - return data->header.global_state;
> + return slpc_blob_read(slpc, header.global_state);
> }
>
> static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
> @@ -156,7 +163,7 @@ static int slpc_query_task_state(struct intel_guc_slpc *slpc)
> drm_err(&i915->drm, "Failed to query task state (%pe)\n",
> ERR_PTR(ret));
>
> - drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
> + drm_clflush_virt_range(slpc->slpc_map.vaddr, SLPC_PAGE_SIZE_BYTES);
Also here we need clfush only for system memory address.
>
> return ret;
> }
> @@ -243,10 +250,11 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
> struct drm_i915_private *i915 = slpc_to_i915(slpc);
> u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
> int err;
> + void *vaddr;
>
> GEM_BUG_ON(slpc->vma);
>
> - err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&slpc->vaddr);
> + err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&vaddr);
> if (unlikely(err)) {
> drm_err(&i915->drm,
> "Failed to allocate SLPC struct (err=%pe)\n",
> @@ -254,6 +262,12 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
> return err;
> }
>
> + if (i915_gem_object_is_lmem(slpc->vma->obj))
> + iosys_map_set_vaddr_iomem(&slpc->slpc_map,
> + (void __iomem *)vaddr);
> + else
> + iosys_map_set_vaddr(&slpc->slpc_map, vaddr);
> +
> slpc->max_freq_softlimit = 0;
> slpc->min_freq_softlimit = 0;
>
> @@ -335,40 +349,37 @@ static int slpc_reset(struct intel_guc_slpc *slpc)
>
> static u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
> {
> - struct slpc_shared_data *data = slpc->vaddr;
> -
> GEM_BUG_ON(!slpc->vma);
>
> return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK,
> - data->task_state_data.freq) *
> + slpc_blob_read(slpc, task_state_data.freq)) *
> GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
> }
>
> static u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
> {
> - struct slpc_shared_data *data = slpc->vaddr;
> -
> GEM_BUG_ON(!slpc->vma);
>
> return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK,
> - data->task_state_data.freq) *
> + slpc_blob_read(slpc, task_state_data.freq)) *
> GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
> }
>
> -static void slpc_shared_data_reset(struct slpc_shared_data *data)
> +static void slpc_shared_data_reset(struct intel_guc_slpc *slpc)
> {
> - memset(data, 0, sizeof(struct slpc_shared_data));
> -
> - data->header.size = sizeof(struct slpc_shared_data);
> + iosys_map_memset(&slpc->slpc_map,
> + 0, 0, sizeof(struct slpc_shared_data));
> + slpc_blob_write(slpc,
> + header.size, sizeof(struct slpc_shared_data));
>
> /* Enable only GTPERF task, disable others */
> - slpc_mem_set_enabled(data, SLPC_PARAM_TASK_ENABLE_GTPERF,
> + slpc_mem_set_enabled(slpc, SLPC_PARAM_TASK_ENABLE_GTPERF,
> SLPC_PARAM_TASK_DISABLE_GTPERF);
>
> - slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_BALANCER,
> + slpc_mem_set_disabled(slpc, SLPC_PARAM_TASK_ENABLE_BALANCER,
> SLPC_PARAM_TASK_DISABLE_BALANCER);
>
> - slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_DCC,
> + slpc_mem_set_disabled(slpc, SLPC_PARAM_TASK_ENABLE_DCC,
> SLPC_PARAM_TASK_DISABLE_DCC);
After converting to iosys_map instance, each
slpc_mem_set_enabled/disabled calls slpc_mem_set_param twice and each
slpc_mem_set_param calls slpc_blob_read/write 3 times resulting in 18
calls to memcpy.
Therefore it is efficient to consolidate all updates by reading the
complete override_params field, update necessary members and finally
overwrite the entire override_params.
Regards,
Bala
> }
>
> @@ -617,7 +628,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>
> GEM_BUG_ON(!slpc->vma);
>
> - slpc_shared_data_reset(slpc->vaddr);
> + slpc_shared_data_reset(slpc);
>
> ret = slpc_reset(slpc);
> if (unlikely(ret < 0)) {
> @@ -705,8 +716,6 @@ void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc)
> int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p)
> {
> struct drm_i915_private *i915 = slpc_to_i915(slpc);
> - struct slpc_shared_data *data = slpc->vaddr;
> - struct slpc_task_state_data *slpc_tasks;
> intel_wakeref_t wakeref;
> int ret = 0;
>
> @@ -716,11 +725,10 @@ int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p
> ret = slpc_query_task_state(slpc);
>
> if (!ret) {
> - slpc_tasks = &data->task_state_data;
> -
> drm_printf(p, "\tSLPC state: %s\n", slpc_get_state_string(slpc));
> drm_printf(p, "\tGTPERF task active: %s\n",
> - str_yes_no(slpc_tasks->status & SLPC_GTPERF_TASK_ENABLED));
> + str_yes_no(slpc_blob_read(slpc, task_state_data.status) &
> + SLPC_GTPERF_TASK_ENABLED));
> drm_printf(p, "\tMax freq: %u MHz\n",
> slpc_decode_max_freq(slpc));
> drm_printf(p, "\tMin freq: %u MHz\n",
> @@ -739,4 +747,5 @@ void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
> return;
>
> i915_vma_unpin_and_release(&slpc->vma, I915_VMA_RELEASE_MAP);
> + iosys_map_clear(&slpc->slpc_map);
> }
> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> index bf5b9a563c09..96f524f25b52 100644
> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
> @@ -7,15 +7,16 @@
> #define _INTEL_GUC_SLPC_TYPES_H_
>
> #include <linux/atomic.h>
> -#include <linux/workqueue.h>
> +#include <linux/iosys-map.h>
> #include <linux/mutex.h>
> #include <linux/types.h>
> +#include <linux/workqueue.h>
>
> #define SLPC_RESET_TIMEOUT_MS 5
>
> struct intel_guc_slpc {
> struct i915_vma *vma;
> - struct slpc_shared_data *vaddr;
> + struct iosys_map slpc_map;
> bool supported;
> bool selected;
>
> --
> 2.33.0
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert slpc to iosys_map
2022-04-18 11:03 ` Balasubramani Vivekanandan
@ 2022-04-19 8:17 ` Siva Mullati
2022-05-09 5:28 ` Siva Mullati
0 siblings, 1 reply; 9+ messages in thread
From: Siva Mullati @ 2022-04-19 8:17 UTC (permalink / raw)
To: Balasubramani Vivekanandan, intel-gfx; +Cc: lucas.demarchi
On 18/04/22 16:33, Balasubramani Vivekanandan wrote:
> On 16.03.2022 18:26, Mullati Siva wrote:
>> From: Siva Mullati <siva.mullati@intel.com>
>>
>> Convert slpc shared data to use iosys_map rather than
>> plain pointer and save it in the intel_guc_slpc struct.
>> This will help with in read and update slpc shared data
>> after the slpc init by abstracting the IO vs system memory.
>>
>> Signed-off-by: Siva Mullati <siva.mullati@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 79 +++++++++++--------
>> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 5 +-
>> 2 files changed, 47 insertions(+), 37 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> index 9f032c65a488..3a9ec6b03ceb 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>> @@ -14,6 +14,13 @@
>> #include "gt/intel_gt_regs.h"
>> #include "gt/intel_rps.h"
>>
>> +#define slpc_blob_read(slpc_, field_) \
>> + iosys_map_rd_field(&(slpc_)->slpc_map, 0, \
>> + struct slpc_shared_data, field_)
>> +#define slpc_blob_write(slpc_, field_, val_) \
>> + iosys_map_wr_field(&(slpc_)->slpc_map, 0, \
>> + struct slpc_shared_data, field_, val_)
>> +
>> static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
>> {
>> return container_of(slpc, struct intel_guc, slpc);
>> @@ -52,50 +59,50 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
>> slpc->selected = __guc_slpc_selected(guc);
>> }
>>
>> -static void slpc_mem_set_param(struct slpc_shared_data *data,
>> +static void slpc_mem_set_param(struct intel_guc_slpc *slpc,
>> u32 id, u32 value)
>> {
>> + u32 bits = slpc_blob_read(slpc, override_params.bits[id >> 5]);
>> +
>> GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS);
>> /*
>> * When the flag bit is set, corresponding value will be read
>> * and applied by SLPC.
>> */
>> - data->override_params.bits[id >> 5] |= (1 << (id % 32));
>> - data->override_params.values[id] = value;
>> + bits |= (1 << (id % 32));
>> + slpc_blob_write(slpc, override_params.bits[id >> 5], bits);
>> + slpc_blob_write(slpc, override_params.values[id], value);
>> }
>>
>> -static void slpc_mem_set_enabled(struct slpc_shared_data *data,
>> +static void slpc_mem_set_enabled(struct intel_guc_slpc *slpc,
>> u8 enable_id, u8 disable_id)
>> {
>> /*
>> * Enabling a param involves setting the enable_id
>> * to 1 and disable_id to 0.
>> */
>> - slpc_mem_set_param(data, enable_id, 1);
>> - slpc_mem_set_param(data, disable_id, 0);
>> + slpc_mem_set_param(slpc, enable_id, 1);
>> + slpc_mem_set_param(slpc, disable_id, 0);
>> }
>>
>> -static void slpc_mem_set_disabled(struct slpc_shared_data *data,
>> +static void slpc_mem_set_disabled(struct intel_guc_slpc *slpc,
>> u8 enable_id, u8 disable_id)
>> {
>> /*
>> * Disabling a param involves setting the enable_id
>> * to 0 and disable_id to 1.
>> */
>> - slpc_mem_set_param(data, disable_id, 1);
>> - slpc_mem_set_param(data, enable_id, 0);
>> + slpc_mem_set_param(slpc, disable_id, 1);
>> + slpc_mem_set_param(slpc, enable_id, 0);
>> }
>>
>> static u32 slpc_get_state(struct intel_guc_slpc *slpc)
>> {
>> - struct slpc_shared_data *data;
>> -
>> GEM_BUG_ON(!slpc->vma);
>>
>> - drm_clflush_virt_range(slpc->vaddr, sizeof(u32));
>> - data = slpc->vaddr;
>> + drm_clflush_virt_range(slpc->slpc_map.vaddr, sizeof(u32));
> clflush will not be required if the slpc_map contains io memory address.
> So the drm_clflush_virt_range can be added under a check for system
> memory
Agreed!
>>
>> - return data->header.global_state;
>> + return slpc_blob_read(slpc, header.global_state);
>> }
>>
>> static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
>> @@ -156,7 +163,7 @@ static int slpc_query_task_state(struct intel_guc_slpc *slpc)
>> drm_err(&i915->drm, "Failed to query task state (%pe)\n",
>> ERR_PTR(ret));
>>
>> - drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
>> + drm_clflush_virt_range(slpc->slpc_map.vaddr, SLPC_PAGE_SIZE_BYTES);
> Also here we need clfush only for system memory address.
>>
>> return ret;
>> }
>> @@ -243,10 +250,11 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>> struct drm_i915_private *i915 = slpc_to_i915(slpc);
>> u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
>> int err;
>> + void *vaddr;
>>
>> GEM_BUG_ON(slpc->vma);
>>
>> - err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&slpc->vaddr);
>> + err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&vaddr);
>> if (unlikely(err)) {
>> drm_err(&i915->drm,
>> "Failed to allocate SLPC struct (err=%pe)\n",
>> @@ -254,6 +262,12 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>> return err;
>> }
>>
>> + if (i915_gem_object_is_lmem(slpc->vma->obj))
>> + iosys_map_set_vaddr_iomem(&slpc->slpc_map,
>> + (void __iomem *)vaddr);
>> + else
>> + iosys_map_set_vaddr(&slpc->slpc_map, vaddr);
>> +
>> slpc->max_freq_softlimit = 0;
>> slpc->min_freq_softlimit = 0;
>>
>> @@ -335,40 +349,37 @@ static int slpc_reset(struct intel_guc_slpc *slpc)
>>
>> static u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
>> {
>> - struct slpc_shared_data *data = slpc->vaddr;
>> -
>> GEM_BUG_ON(!slpc->vma);
>>
>> return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK,
>> - data->task_state_data.freq) *
>> + slpc_blob_read(slpc, task_state_data.freq)) *
>> GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
>> }
>>
>> static u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
>> {
>> - struct slpc_shared_data *data = slpc->vaddr;
>> -
>> GEM_BUG_ON(!slpc->vma);
>>
>> return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK,
>> - data->task_state_data.freq) *
>> + slpc_blob_read(slpc, task_state_data.freq)) *
>> GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
>> }
>>
>> -static void slpc_shared_data_reset(struct slpc_shared_data *data)
>> +static void slpc_shared_data_reset(struct intel_guc_slpc *slpc)
>> {
>> - memset(data, 0, sizeof(struct slpc_shared_data));
>> -
>> - data->header.size = sizeof(struct slpc_shared_data);
>> + iosys_map_memset(&slpc->slpc_map,
>> + 0, 0, sizeof(struct slpc_shared_data));
>> + slpc_blob_write(slpc,
>> + header.size, sizeof(struct slpc_shared_data));
>>
>> /* Enable only GTPERF task, disable others */
>> - slpc_mem_set_enabled(data, SLPC_PARAM_TASK_ENABLE_GTPERF,
>> + slpc_mem_set_enabled(slpc, SLPC_PARAM_TASK_ENABLE_GTPERF,
>> SLPC_PARAM_TASK_DISABLE_GTPERF);
>>
>> - slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_BALANCER,
>> + slpc_mem_set_disabled(slpc, SLPC_PARAM_TASK_ENABLE_BALANCER,
>> SLPC_PARAM_TASK_DISABLE_BALANCER);
>>
>> - slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_DCC,
>> + slpc_mem_set_disabled(slpc, SLPC_PARAM_TASK_ENABLE_DCC,
>> SLPC_PARAM_TASK_DISABLE_DCC);
> After converting to iosys_map instance, each
> slpc_mem_set_enabled/disabled calls slpc_mem_set_param twice and each
> slpc_mem_set_param calls slpc_blob_read/write 3 times resulting in 18
> calls to memcpy.
> Therefore it is efficient to consolidate all updates by reading the
> complete override_params field, update necessary members and finally
> overwrite the entire override_params.
>
> Regards,
> Bala
>> }
>>
>> @@ -617,7 +628,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>>
>> GEM_BUG_ON(!slpc->vma);
>>
>> - slpc_shared_data_reset(slpc->vaddr);
>> + slpc_shared_data_reset(slpc);
>>
>> ret = slpc_reset(slpc);
>> if (unlikely(ret < 0)) {
>> @@ -705,8 +716,6 @@ void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc)
>> int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p)
>> {
>> struct drm_i915_private *i915 = slpc_to_i915(slpc);
>> - struct slpc_shared_data *data = slpc->vaddr;
>> - struct slpc_task_state_data *slpc_tasks;
>> intel_wakeref_t wakeref;
>> int ret = 0;
>>
>> @@ -716,11 +725,10 @@ int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p
>> ret = slpc_query_task_state(slpc);
>>
>> if (!ret) {
>> - slpc_tasks = &data->task_state_data;
>> -
>> drm_printf(p, "\tSLPC state: %s\n", slpc_get_state_string(slpc));
>> drm_printf(p, "\tGTPERF task active: %s\n",
>> - str_yes_no(slpc_tasks->status & SLPC_GTPERF_TASK_ENABLED));
>> + str_yes_no(slpc_blob_read(slpc, task_state_data.status) &
>> + SLPC_GTPERF_TASK_ENABLED));
>> drm_printf(p, "\tMax freq: %u MHz\n",
>> slpc_decode_max_freq(slpc));
>> drm_printf(p, "\tMin freq: %u MHz\n",
>> @@ -739,4 +747,5 @@ void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
>> return;
>>
>> i915_vma_unpin_and_release(&slpc->vma, I915_VMA_RELEASE_MAP);
>> + iosys_map_clear(&slpc->slpc_map);
>> }
>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> index bf5b9a563c09..96f524f25b52 100644
>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>> @@ -7,15 +7,16 @@
>> #define _INTEL_GUC_SLPC_TYPES_H_
>>
>> #include <linux/atomic.h>
>> -#include <linux/workqueue.h>
>> +#include <linux/iosys-map.h>
>> #include <linux/mutex.h>
>> #include <linux/types.h>
>> +#include <linux/workqueue.h>
>>
>> #define SLPC_RESET_TIMEOUT_MS 5
>>
>> struct intel_guc_slpc {
>> struct i915_vma *vma;
>> - struct slpc_shared_data *vaddr;
>> + struct iosys_map slpc_map;
>> bool supported;
>> bool selected;
>>
>> --
>> 2.33.0
>>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert slpc to iosys_map
2022-04-19 8:17 ` Siva Mullati
@ 2022-05-09 5:28 ` Siva Mullati
0 siblings, 0 replies; 9+ messages in thread
From: Siva Mullati @ 2022-05-09 5:28 UTC (permalink / raw)
To: Balasubramani Vivekanandan, intel-gfx; +Cc: lucas.demarchi
On 19/04/22 13:47, Siva Mullati wrote:
> On 18/04/22 16:33, Balasubramani Vivekanandan wrote:
>> On 16.03.2022 18:26, Mullati Siva wrote:
>>> From: Siva Mullati <siva.mullati@intel.com>
>>>
>>> Convert slpc shared data to use iosys_map rather than
>>> plain pointer and save it in the intel_guc_slpc struct.
>>> This will help with in read and update slpc shared data
>>> after the slpc init by abstracting the IO vs system memory.
>>>
>>> Signed-off-by: Siva Mullati <siva.mullati@intel.com>
>>> ---
>>> drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 79 +++++++++++--------
>>> .../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 5 +-
>>> 2 files changed, 47 insertions(+), 37 deletions(-)
>>>
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>>> index 9f032c65a488..3a9ec6b03ceb 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c
>>> @@ -14,6 +14,13 @@
>>> #include "gt/intel_gt_regs.h"
>>> #include "gt/intel_rps.h"
>>>
>>> +#define slpc_blob_read(slpc_, field_) \
>>> + iosys_map_rd_field(&(slpc_)->slpc_map, 0, \
>>> + struct slpc_shared_data, field_)
>>> +#define slpc_blob_write(slpc_, field_, val_) \
>>> + iosys_map_wr_field(&(slpc_)->slpc_map, 0, \
>>> + struct slpc_shared_data, field_, val_)
>>> +
>>> static inline struct intel_guc *slpc_to_guc(struct intel_guc_slpc *slpc)
>>> {
>>> return container_of(slpc, struct intel_guc, slpc);
>>> @@ -52,50 +59,50 @@ void intel_guc_slpc_init_early(struct intel_guc_slpc *slpc)
>>> slpc->selected = __guc_slpc_selected(guc);
>>> }
>>>
>>> -static void slpc_mem_set_param(struct slpc_shared_data *data,
>>> +static void slpc_mem_set_param(struct intel_guc_slpc *slpc,
>>> u32 id, u32 value)
>>> {
>>> + u32 bits = slpc_blob_read(slpc, override_params.bits[id >> 5]);
>>> +
>>> GEM_BUG_ON(id >= SLPC_MAX_OVERRIDE_PARAMETERS);
>>> /*
>>> * When the flag bit is set, corresponding value will be read
>>> * and applied by SLPC.
>>> */
>>> - data->override_params.bits[id >> 5] |= (1 << (id % 32));
>>> - data->override_params.values[id] = value;
>>> + bits |= (1 << (id % 32));
>>> + slpc_blob_write(slpc, override_params.bits[id >> 5], bits);
>>> + slpc_blob_write(slpc, override_params.values[id], value);
>>> }
>>>
>>> -static void slpc_mem_set_enabled(struct slpc_shared_data *data,
>>> +static void slpc_mem_set_enabled(struct intel_guc_slpc *slpc,
>>> u8 enable_id, u8 disable_id)
>>> {
>>> /*
>>> * Enabling a param involves setting the enable_id
>>> * to 1 and disable_id to 0.
>>> */
>>> - slpc_mem_set_param(data, enable_id, 1);
>>> - slpc_mem_set_param(data, disable_id, 0);
>>> + slpc_mem_set_param(slpc, enable_id, 1);
>>> + slpc_mem_set_param(slpc, disable_id, 0);
>>> }
>>>
>>> -static void slpc_mem_set_disabled(struct slpc_shared_data *data,
>>> +static void slpc_mem_set_disabled(struct intel_guc_slpc *slpc,
>>> u8 enable_id, u8 disable_id)
>>> {
>>> /*
>>> * Disabling a param involves setting the enable_id
>>> * to 0 and disable_id to 1.
>>> */
>>> - slpc_mem_set_param(data, disable_id, 1);
>>> - slpc_mem_set_param(data, enable_id, 0);
>>> + slpc_mem_set_param(slpc, disable_id, 1);
>>> + slpc_mem_set_param(slpc, enable_id, 0);
>>> }
>>>
>>> static u32 slpc_get_state(struct intel_guc_slpc *slpc)
>>> {
>>> - struct slpc_shared_data *data;
>>> -
>>> GEM_BUG_ON(!slpc->vma);
>>>
>>> - drm_clflush_virt_range(slpc->vaddr, sizeof(u32));
>>> - data = slpc->vaddr;
>>> + drm_clflush_virt_range(slpc->slpc_map.vaddr, sizeof(u32));
>> clflush will not be required if the slpc_map contains io memory address.
>> So the drm_clflush_virt_range can be added under a check for system
>> memory
> Agreed!
>>>
>>> - return data->header.global_state;
>>> + return slpc_blob_read(slpc, header.global_state);
>>> }
>>>
>>> static int guc_action_slpc_set_param(struct intel_guc *guc, u8 id, u32 value)
>>> @@ -156,7 +163,7 @@ static int slpc_query_task_state(struct intel_guc_slpc *slpc)
>>> drm_err(&i915->drm, "Failed to query task state (%pe)\n",
>>> ERR_PTR(ret));
>>>
>>> - drm_clflush_virt_range(slpc->vaddr, SLPC_PAGE_SIZE_BYTES);
>>> + drm_clflush_virt_range(slpc->slpc_map.vaddr, SLPC_PAGE_SIZE_BYTES);
>> Also here we need clfush only for system memory address.
>>>
>>> return ret;
>>> }
>>> @@ -243,10 +250,11 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>>> struct drm_i915_private *i915 = slpc_to_i915(slpc);
>>> u32 size = PAGE_ALIGN(sizeof(struct slpc_shared_data));
>>> int err;
>>> + void *vaddr;
>>>
>>> GEM_BUG_ON(slpc->vma);
>>>
>>> - err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&slpc->vaddr);
>>> + err = intel_guc_allocate_and_map_vma(guc, size, &slpc->vma, (void **)&vaddr);
>>> if (unlikely(err)) {
>>> drm_err(&i915->drm,
>>> "Failed to allocate SLPC struct (err=%pe)\n",
>>> @@ -254,6 +262,12 @@ int intel_guc_slpc_init(struct intel_guc_slpc *slpc)
>>> return err;
>>> }
>>>
>>> + if (i915_gem_object_is_lmem(slpc->vma->obj))
>>> + iosys_map_set_vaddr_iomem(&slpc->slpc_map,
>>> + (void __iomem *)vaddr);
>>> + else
>>> + iosys_map_set_vaddr(&slpc->slpc_map, vaddr);
>>> +
>>> slpc->max_freq_softlimit = 0;
>>> slpc->min_freq_softlimit = 0;
>>>
>>> @@ -335,40 +349,37 @@ static int slpc_reset(struct intel_guc_slpc *slpc)
>>>
>>> static u32 slpc_decode_min_freq(struct intel_guc_slpc *slpc)
>>> {
>>> - struct slpc_shared_data *data = slpc->vaddr;
>>> -
>>> GEM_BUG_ON(!slpc->vma);
>>>
>>> return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MIN_UNSLICE_FREQ_MASK,
>>> - data->task_state_data.freq) *
>>> + slpc_blob_read(slpc, task_state_data.freq)) *
>>> GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
>>> }
>>>
>>> static u32 slpc_decode_max_freq(struct intel_guc_slpc *slpc)
>>> {
>>> - struct slpc_shared_data *data = slpc->vaddr;
>>> -
>>> GEM_BUG_ON(!slpc->vma);
>>>
>>> return DIV_ROUND_CLOSEST(REG_FIELD_GET(SLPC_MAX_UNSLICE_FREQ_MASK,
>>> - data->task_state_data.freq) *
>>> + slpc_blob_read(slpc, task_state_data.freq)) *
>>> GT_FREQUENCY_MULTIPLIER, GEN9_FREQ_SCALER);
>>> }
>>>
>>> -static void slpc_shared_data_reset(struct slpc_shared_data *data)
>>> +static void slpc_shared_data_reset(struct intel_guc_slpc *slpc)
>>> {
>>> - memset(data, 0, sizeof(struct slpc_shared_data));
>>> -
>>> - data->header.size = sizeof(struct slpc_shared_data);
>>> + iosys_map_memset(&slpc->slpc_map,
>>> + 0, 0, sizeof(struct slpc_shared_data));
>>> + slpc_blob_write(slpc,
>>> + header.size, sizeof(struct slpc_shared_data));
>>>
>>> /* Enable only GTPERF task, disable others */
>>> - slpc_mem_set_enabled(data, SLPC_PARAM_TASK_ENABLE_GTPERF,
>>> + slpc_mem_set_enabled(slpc, SLPC_PARAM_TASK_ENABLE_GTPERF,
>>> SLPC_PARAM_TASK_DISABLE_GTPERF);
>>>
>>> - slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_BALANCER,
>>> + slpc_mem_set_disabled(slpc, SLPC_PARAM_TASK_ENABLE_BALANCER,
>>> SLPC_PARAM_TASK_DISABLE_BALANCER);
>>>
>>> - slpc_mem_set_disabled(data, SLPC_PARAM_TASK_ENABLE_DCC,
>>> + slpc_mem_set_disabled(slpc, SLPC_PARAM_TASK_ENABLE_DCC,
>>> SLPC_PARAM_TASK_DISABLE_DCC);
>> After converting to iosys_map instance, each
>> slpc_mem_set_enabled/disabled calls slpc_mem_set_param twice and each
>> slpc_mem_set_param calls slpc_blob_read/write 3 times resulting in 18
>> calls to memcpy.
>> Therefore it is efficient to consolidate all updates by reading the
>> complete override_params field, update necessary members and finally
>> overwrite the entire override_params.
>>
>> Regards,
>> Bala
From what we discussed, I am leaving this comment and remain
this change as is, since the suggested change would require entire
struct slpc_override_param copying which is about 264 words size.
>>> }
>>>
>>> @@ -617,7 +628,7 @@ int intel_guc_slpc_enable(struct intel_guc_slpc *slpc)
>>>
>>> GEM_BUG_ON(!slpc->vma);
>>>
>>> - slpc_shared_data_reset(slpc->vaddr);
>>> + slpc_shared_data_reset(slpc);
>>>
>>> ret = slpc_reset(slpc);
>>> if (unlikely(ret < 0)) {
>>> @@ -705,8 +716,6 @@ void intel_guc_slpc_dec_waiters(struct intel_guc_slpc *slpc)
>>> int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p)
>>> {
>>> struct drm_i915_private *i915 = slpc_to_i915(slpc);
>>> - struct slpc_shared_data *data = slpc->vaddr;
>>> - struct slpc_task_state_data *slpc_tasks;
>>> intel_wakeref_t wakeref;
>>> int ret = 0;
>>>
>>> @@ -716,11 +725,10 @@ int intel_guc_slpc_print_info(struct intel_guc_slpc *slpc, struct drm_printer *p
>>> ret = slpc_query_task_state(slpc);
>>>
>>> if (!ret) {
>>> - slpc_tasks = &data->task_state_data;
>>> -
>>> drm_printf(p, "\tSLPC state: %s\n", slpc_get_state_string(slpc));
>>> drm_printf(p, "\tGTPERF task active: %s\n",
>>> - str_yes_no(slpc_tasks->status & SLPC_GTPERF_TASK_ENABLED));
>>> + str_yes_no(slpc_blob_read(slpc, task_state_data.status) &
>>> + SLPC_GTPERF_TASK_ENABLED));
>>> drm_printf(p, "\tMax freq: %u MHz\n",
>>> slpc_decode_max_freq(slpc));
>>> drm_printf(p, "\tMin freq: %u MHz\n",
>>> @@ -739,4 +747,5 @@ void intel_guc_slpc_fini(struct intel_guc_slpc *slpc)
>>> return;
>>>
>>> i915_vma_unpin_and_release(&slpc->vma, I915_VMA_RELEASE_MAP);
>>> + iosys_map_clear(&slpc->slpc_map);
>>> }
>>> diff --git a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>>> index bf5b9a563c09..96f524f25b52 100644
>>> --- a/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>>> +++ b/drivers/gpu/drm/i915/gt/uc/intel_guc_slpc_types.h
>>> @@ -7,15 +7,16 @@
>>> #define _INTEL_GUC_SLPC_TYPES_H_
>>>
>>> #include <linux/atomic.h>
>>> -#include <linux/workqueue.h>
>>> +#include <linux/iosys-map.h>
>>> #include <linux/mutex.h>
>>> #include <linux/types.h>
>>> +#include <linux/workqueue.h>
>>>
>>> #define SLPC_RESET_TIMEOUT_MS 5
>>>
>>> struct intel_guc_slpc {
>>> struct i915_vma *vma;
>>> - struct slpc_shared_data *vaddr;
>>> + struct iosys_map slpc_map;
>>> bool supported;
>>> bool selected;
>>>
>>> --
>>> 2.33.0
>>>
^ permalink raw reply [flat|nested] 9+ messages in thread
* [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor slpc shared data access to use iosys_map
@ 2022-05-09 15:35 Mullati Siva
0 siblings, 0 replies; 9+ messages in thread
From: Mullati Siva @ 2022-05-09 15:35 UTC (permalink / raw)
To: intel-gfx, siva.mullati; +Cc: lucas.demarchi
From: Siva Mullati <siva.mullati@intel.com>
Ver2: remove accessing drm_cflush for io memory
This is continuation to the original patch series to use iosys map
APIs to use slpc shared data commands and descriptors.
https://patchwork.freedesktop.org/series/99711/
Siva Mullati (1):
drm/i915/guc: Convert slpc to iosys_map
drivers/gpu/drm/i915/gt/uc/intel_guc_slpc.c | 82 +++++++++++--------
.../gpu/drm/i915/gt/uc/intel_guc_slpc_types.h | 5 +-
2 files changed, 50 insertions(+), 37 deletions(-)
--
2.33.0
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-05-09 15:35 UTC | newest]
Thread overview: 9+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-16 12:56 [Intel-gfx] [PATCH 0/1] drm/i915/guc: Refactor slpc shared data access to use iosys_map Mullati Siva
2022-03-16 12:56 ` [Intel-gfx] [PATCH 1/1] drm/i915/guc: Convert slpc to iosys_map Mullati Siva
2022-04-18 11:03 ` Balasubramani Vivekanandan
2022-04-19 8:17 ` Siva Mullati
2022-05-09 5:28 ` Siva Mullati
2022-03-16 13:37 ` [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/guc: Refactor slpc shared data access to use iosys_map Patchwork
2022-03-16 14:13 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
2022-03-16 15:36 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-05-09 15:35 [Intel-gfx] [PATCH 0/1] " Mullati Siva
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