[PATCH v2 0/7] Add RZ/G2L Display support

[PATCH v2 0/7] Add RZ/G2L Display support

[Biju Das]

RZ/G2L LCD controller composed of Frame compression Processor(FCPVD),
Video signal processor (VSPD) and Display unit(DU). The output of LCDC is
connected to Display parallel interface and MIPI link video interface.

This patch series aims to add basic display support on RZ/G2L SMARC EVK
platform. The output from DSI is connected to ADV7535.

The DU controller is similar to R-Car as it is connected to VSPD,
so reusing most of R-Car code with new CRTC driver specific to
RZ/G2L

v1->v2:
 * Based on [1], all references to 'rzg2l_lcdc' replaced with 'rzg2l_du'
 * Updated commit description for bindings
 * Removed LCDC references from bindings
 * Changed clock name from du.0->aclk from bindings
 * Changed reset name from du.0->du from bindings
 * Replaced crtc_helper_funcs->rcar_crtc_helper_funcs
 * Updated macro DRM_RZG2L_LCDC->DRM_RZG2L_DU
 * Replaced rzg2l-lcdc-drm->rzg2l-du-drm
 * Added forward declaration for struct reset_control

[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220312084205.31462-2-biju.das.jz@bp.renesas.com/

RFC->v1:
 * Changed  minItems->maxItems for renesas,vsps.
 * Added RZ/G2L LCDC driver with special handling for CRTC reusing
   most of RCar DU code
 * Fixed the comments for num_rpf from rpf's->RPFs/ and vsp->VSP.
RFC:
 https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-18-biju.das.jz@bp.renesas.com/
 https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-12-biju.das.jz@bp.renesas.com/
 https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-13-biju.das.jz@bp.renesas.com/
 https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-19-biju.das.jz@bp.renesas.com/

Biju Das (7):
  dt-bindings: display: renesas,du: Document r9a07g044l bindings
  drm: rcar-du: Add num_rpf to struct rcar_du_device_info
  drm: rcar-du: Add max_width and max_height to struct
    rcar_du_device_info
  drm: rcar-du: Move rcar_du_output_name() to rcar_du_common.c
  drm: rcar-du: Factorise rcar_du_{atomic_check,modeset_init}
  drm: rcar-du: Factorise
    rcar_du_vsp{complete,enable,plane_atomic_check}
  drm: rcar-du: Add RZ/G2L DU Support

 .../bindings/display/renesas,du.yaml          |  54 ++
 drivers/gpu/drm/rcar-du/Kconfig               |  18 +-
 drivers/gpu/drm/rcar-du/Makefile              |  13 +
 drivers/gpu/drm/rcar-du/rcar_du_common.c      |  30 +
 drivers/gpu/drm/rcar-du/rcar_du_crtc.h        |   8 +
 drivers/gpu/drm/rcar-du/rcar_du_drv.c         | 100 ++-
 drivers/gpu/drm/rcar-du/rcar_du_drv.h         |  31 +
 drivers/gpu/drm/rcar-du/rcar_du_kms.c         |  23 +-
 drivers/gpu/drm/rcar-du/rcar_du_plane.h       |  12 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c         |  18 +-
 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c       | 705 ++++++++++++++++++
 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c        | 221 ++++++
 drivers/gpu/drm/rcar-du/rzg2l_du_plane.c      |  82 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h       |  64 ++
 14 files changed, 1334 insertions(+), 45 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_common.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_plane.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h

-- 
2.17.1

[PATCH v2 0/7] Add RZ/G2L Display support

[Biju Das]

RZ/G2L LCD controller composed of Frame compression Processor(FCPVD),
Video signal processor (VSPD) and Display unit(DU). The output of LCDC is
connected to Display parallel interface and MIPI link video interface.

This patch series aims to add basic display support on RZ/G2L SMARC EVK
platform. The output from DSI is connected to ADV7535.

The DU controller is similar to R-Car as it is connected to VSPD,
so reusing most of R-Car code with new CRTC driver specific to
RZ/G2L

v1->v2:
 * Based on [1], all references to 'rzg2l_lcdc' replaced with 'rzg2l_du'
 * Updated commit description for bindings
 * Removed LCDC references from bindings
 * Changed clock name from du.0->aclk from bindings
 * Changed reset name from du.0->du from bindings
 * Replaced crtc_helper_funcs->rcar_crtc_helper_funcs
 * Updated macro DRM_RZG2L_LCDC->DRM_RZG2L_DU
 * Replaced rzg2l-lcdc-drm->rzg2l-du-drm
 * Added forward declaration for struct reset_control

[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220312084205.31462-2-biju.das.jz@bp.renesas.com/

RFC->v1:
 * Changed  minItems->maxItems for renesas,vsps.
 * Added RZ/G2L LCDC driver with special handling for CRTC reusing
   most of RCar DU code
 * Fixed the comments for num_rpf from rpf's->RPFs/ and vsp->VSP.
RFC:
 https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-18-biju.das.jz@bp.renesas.com/
 https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-12-biju.das.jz@bp.renesas.com/
 https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-13-biju.das.jz@bp.renesas.com/
 https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-19-biju.das.jz@bp.renesas.com/

Biju Das (7):
  dt-bindings: display: renesas,du: Document r9a07g044l bindings
  drm: rcar-du: Add num_rpf to struct rcar_du_device_info
  drm: rcar-du: Add max_width and max_height to struct
    rcar_du_device_info
  drm: rcar-du: Move rcar_du_output_name() to rcar_du_common.c
  drm: rcar-du: Factorise rcar_du_{atomic_check,modeset_init}
  drm: rcar-du: Factorise
    rcar_du_vsp{complete,enable,plane_atomic_check}
  drm: rcar-du: Add RZ/G2L DU Support

 .../bindings/display/renesas,du.yaml          |  54 ++
 drivers/gpu/drm/rcar-du/Kconfig               |  18 +-
 drivers/gpu/drm/rcar-du/Makefile              |  13 +
 drivers/gpu/drm/rcar-du/rcar_du_common.c      |  30 +
 drivers/gpu/drm/rcar-du/rcar_du_crtc.h        |   8 +
 drivers/gpu/drm/rcar-du/rcar_du_drv.c         | 100 ++-
 drivers/gpu/drm/rcar-du/rcar_du_drv.h         |  31 +
 drivers/gpu/drm/rcar-du/rcar_du_kms.c         |  23 +-
 drivers/gpu/drm/rcar-du/rcar_du_plane.h       |  12 +
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c         |  18 +-
 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c       | 705 ++++++++++++++++++
 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c        | 221 ++++++
 drivers/gpu/drm/rcar-du/rzg2l_du_plane.c      |  82 ++
 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h       |  64 ++
 14 files changed, 1334 insertions(+), 45 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_common.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_plane.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h

-- 
2.17.1

[PATCH v2 1/7] dt-bindings: display: renesas,du: Document r9a07g044l bindings

[Biju Das]

Extend the Renesas DU display bindings to support the r9a07g044l
DU module found on RZ/G2L LCDC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * Updated commit description.
 * Removed LCDC references
 * Changed clock name from du.0->aclk
 * Changed reset name from du.0->du
RFC->v1:
 * Changed  minItems->maxItems for renesas,vsps.
RFC:
 https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-18-biju.das.jz@bp.renesas.com/
---
 .../bindings/display/renesas,du.yaml          | 54 +++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml
index 13efea574584..f560608bf4e8 100644
--- a/Documentation/devicetree/bindings/display/renesas,du.yaml
+++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
@@ -40,6 +40,7 @@ properties:
       - renesas,du-r8a77990 # for R-Car E3 compatible DU
       - renesas,du-r8a77995 # for R-Car D3 compatible DU
       - renesas,du-r8a779a0 # for R-Car V3U compatible DU
+      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
 
   reg:
     maxItems: 1
@@ -824,6 +825,59 @@ allOf:
         - reset-names
         - renesas,vsps
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,du-r9a07g044l
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Main clock
+            - description: Register access clock
+            - description: Video clock
+
+        clock-names:
+          items:
+            - const: aclk
+            - const: pclk
+            - const: vclk
+
+        interrupts:
+          maxItems: 1
+
+        resets:
+          maxItems: 1
+
+        reset-names:
+          items:
+            - const: du
+
+        ports:
+          properties:
+            port@0:
+              description: DPAD 0
+            port@1:
+              description: DSI 0
+            port@2: false
+            port@3: false
+
+          required:
+            - port@0
+            - port@1
+
+        renesas,vsps:
+          maxItems: 1
+
+      required:
+        - clock-names
+        - interrupts
+        - resets
+        - reset-names
+        - renesas,vsps
+
 additionalProperties: false
 
 examples:
-- 
2.17.1

[PATCH v2 1/7] dt-bindings: display: renesas, du: Document r9a07g044l bindings

[Biju Das]

Extend the Renesas DU display bindings to support the r9a07g044l
DU module found on RZ/G2L LCDC.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * Updated commit description.
 * Removed LCDC references
 * Changed clock name from du.0->aclk
 * Changed reset name from du.0->du
RFC->v1:
 * Changed  minItems->maxItems for renesas,vsps.
RFC:
 https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-18-biju.das.jz@bp.renesas.com/
---
 .../bindings/display/renesas,du.yaml          | 54 +++++++++++++++++++
 1 file changed, 54 insertions(+)

diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml
index 13efea574584..f560608bf4e8 100644
--- a/Documentation/devicetree/bindings/display/renesas,du.yaml
+++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
@@ -40,6 +40,7 @@ properties:
       - renesas,du-r8a77990 # for R-Car E3 compatible DU
       - renesas,du-r8a77995 # for R-Car D3 compatible DU
       - renesas,du-r8a779a0 # for R-Car V3U compatible DU
+      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
 
   reg:
     maxItems: 1
@@ -824,6 +825,59 @@ allOf:
         - reset-names
         - renesas,vsps
 
+  - if:
+      properties:
+        compatible:
+          contains:
+            enum:
+              - renesas,du-r9a07g044l
+    then:
+      properties:
+        clocks:
+          items:
+            - description: Main clock
+            - description: Register access clock
+            - description: Video clock
+
+        clock-names:
+          items:
+            - const: aclk
+            - const: pclk
+            - const: vclk
+
+        interrupts:
+          maxItems: 1
+
+        resets:
+          maxItems: 1
+
+        reset-names:
+          items:
+            - const: du
+
+        ports:
+          properties:
+            port@0:
+              description: DPAD 0
+            port@1:
+              description: DSI 0
+            port@2: false
+            port@3: false
+
+          required:
+            - port@0
+            - port@1
+
+        renesas,vsps:
+          maxItems: 1
+
+      required:
+        - clock-names
+        - interrupts
+        - resets
+        - reset-names
+        - renesas,vsps
+
 additionalProperties: false
 
 examples:
-- 
2.17.1

[PATCH v2 2/7] drm: rcar-du: Add num_rpf to struct rcar_du_device_info

[Biju Das]

Number of RPF's VSP is different on R-Car and RZ/G2L
 R-Car Gen3 -> 5 RPFs
 R-Car Gen2 -> 4 RPFs
 RZ/G2L -> 2 RPFs

Add num_rpf to struct rcar_du_device_info to support later
SoC without any code changes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No change
RFC->v1:
 * Fixed the comment for num_rpf s/rpf's/RPFs/ and s/vsp/VSP/
RFC:
 * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-12-biju.das.jz@bp.renesas.com/
---
 drivers/gpu/drm/rcar-du/rcar_du_drv.c | 17 +++++++++++++++++
 drivers/gpu/drm/rcar-du/rcar_du_drv.h |  2 ++
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c |  6 +-----
 3 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index 957ea97541d5..1bc7325aa356 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -55,6 +55,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
@@ -77,6 +78,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
 			.port = 1,
 		},
 	},
+	.num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
@@ -104,6 +106,7 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
 			.port = 2,
 		},
 	},
+	.num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
@@ -133,6 +136,7 @@ static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 5,
 	.dpll_mask =  BIT(1),
 };
 
@@ -163,6 +167,7 @@ static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 5,
 	.dpll_mask =  BIT(1),
 };
 
@@ -190,6 +195,7 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
 		},
 	},
 	.num_lvds = 2,
+	.num_rpf = 4,
 	.lvds_clk_mask =  BIT(1) | BIT(0),
 };
 
@@ -220,6 +226,7 @@ static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 5,
 	.dpll_mask =  BIT(1),
 };
 
@@ -272,6 +279,7 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
 		},
 	},
 	.num_lvds = 2,
+	.num_rpf = 4,
 };
 
 /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
@@ -297,6 +305,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7792_info = {
@@ -317,6 +326,7 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
 			.port = 1,
 		},
 	},
+	.num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7794_info = {
@@ -340,6 +350,7 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
 			.port = 1,
 		},
 	},
+	.num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7795_info = {
@@ -373,6 +384,7 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 5,
 	.dpll_mask =  BIT(2) | BIT(1),
 };
 
@@ -403,6 +415,7 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 5,
 	.dpll_mask =  BIT(1),
 };
 
@@ -433,6 +446,7 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 5,
 	.dpll_mask =  BIT(1),
 };
 
@@ -459,6 +473,7 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 5,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
@@ -486,6 +501,7 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
 		},
 	},
 	.num_lvds = 2,
+	.num_rpf = 5,
 	.lvds_clk_mask =  BIT(1) | BIT(0),
 };
 
@@ -505,6 +521,7 @@ static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
 			.port = 1,
 		},
 	},
+	.num_rpf = 5,
 	.dsi_clk_mask =  BIT(1) | BIT(0),
 };
 
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
index 101f42df86ea..68c5de59d18d 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
@@ -69,6 +69,7 @@ struct rcar_du_output_routing {
  * @channels_mask: bit mask of available DU channels
  * @routes: array of CRTC to output routes, indexed by output (RCAR_DU_OUTPUT_*)
  * @num_lvds: number of internal LVDS encoders
+ * @num_rpf: max number of RPFs in VSP
  * @dpll_mask: bit mask of DU channels equipped with a DPLL
  * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot clock
  * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
@@ -80,6 +81,7 @@ struct rcar_du_device_info {
 	unsigned int channels_mask;
 	struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
 	unsigned int num_lvds;
+	unsigned int num_rpf;
 	unsigned int dpll_mask;
 	unsigned int dsi_clk_mask;
 	unsigned int lvds_clk_mask;
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index b7fc5b069cbc..cf045a203aa5 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -415,11 +415,7 @@ int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
 	if (ret < 0)
 		return ret;
 
-	 /*
-	  * The VSP2D (Gen3) has 5 RPFs, but the VSP1D (Gen2) is limited to
-	  * 4 RPFs.
-	  */
-	num_planes = rcdu->info->gen >= 3 ? 5 : 4;
+	num_planes = rcdu->info->num_rpf;
 
 	vsp->planes = kcalloc(num_planes, sizeof(*vsp->planes), GFP_KERNEL);
 	if (!vsp->planes)
-- 
2.17.1

[PATCH v2 2/7] drm: rcar-du: Add num_rpf to struct rcar_du_device_info

[Biju Das]

Number of RPF's VSP is different on R-Car and RZ/G2L
 R-Car Gen3 -> 5 RPFs
 R-Car Gen2 -> 4 RPFs
 RZ/G2L -> 2 RPFs

Add num_rpf to struct rcar_du_device_info to support later
SoC without any code changes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No change
RFC->v1:
 * Fixed the comment for num_rpf s/rpf's/RPFs/ and s/vsp/VSP/
RFC:
 * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-12-biju.das.jz@bp.renesas.com/
---
 drivers/gpu/drm/rcar-du/rcar_du_drv.c | 17 +++++++++++++++++
 drivers/gpu/drm/rcar-du/rcar_du_drv.h |  2 ++
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c |  6 +-----
 3 files changed, 20 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index 957ea97541d5..1bc7325aa356 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -55,6 +55,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
@@ -77,6 +78,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
 			.port = 1,
 		},
 	},
+	.num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
@@ -104,6 +106,7 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
 			.port = 2,
 		},
 	},
+	.num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
@@ -133,6 +136,7 @@ static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 5,
 	.dpll_mask =  BIT(1),
 };
 
@@ -163,6 +167,7 @@ static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 5,
 	.dpll_mask =  BIT(1),
 };
 
@@ -190,6 +195,7 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
 		},
 	},
 	.num_lvds = 2,
+	.num_rpf = 4,
 	.lvds_clk_mask =  BIT(1) | BIT(0),
 };
 
@@ -220,6 +226,7 @@ static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 5,
 	.dpll_mask =  BIT(1),
 };
 
@@ -272,6 +279,7 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
 		},
 	},
 	.num_lvds = 2,
+	.num_rpf = 4,
 };
 
 /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
@@ -297,6 +305,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7792_info = {
@@ -317,6 +326,7 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
 			.port = 1,
 		},
 	},
+	.num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7794_info = {
@@ -340,6 +350,7 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
 			.port = 1,
 		},
 	},
+	.num_rpf = 4,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7795_info = {
@@ -373,6 +384,7 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 5,
 	.dpll_mask =  BIT(2) | BIT(1),
 };
 
@@ -403,6 +415,7 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 5,
 	.dpll_mask =  BIT(1),
 };
 
@@ -433,6 +446,7 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 5,
 	.dpll_mask =  BIT(1),
 };
 
@@ -459,6 +473,7 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
 		},
 	},
 	.num_lvds = 1,
+	.num_rpf = 5,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
@@ -486,6 +501,7 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
 		},
 	},
 	.num_lvds = 2,
+	.num_rpf = 5,
 	.lvds_clk_mask =  BIT(1) | BIT(0),
 };
 
@@ -505,6 +521,7 @@ static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
 			.port = 1,
 		},
 	},
+	.num_rpf = 5,
 	.dsi_clk_mask =  BIT(1) | BIT(0),
 };
 
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
index 101f42df86ea..68c5de59d18d 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
@@ -69,6 +69,7 @@ struct rcar_du_output_routing {
  * @channels_mask: bit mask of available DU channels
  * @routes: array of CRTC to output routes, indexed by output (RCAR_DU_OUTPUT_*)
  * @num_lvds: number of internal LVDS encoders
+ * @num_rpf: max number of RPFs in VSP
  * @dpll_mask: bit mask of DU channels equipped with a DPLL
  * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot clock
  * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
@@ -80,6 +81,7 @@ struct rcar_du_device_info {
 	unsigned int channels_mask;
 	struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
 	unsigned int num_lvds;
+	unsigned int num_rpf;
 	unsigned int dpll_mask;
 	unsigned int dsi_clk_mask;
 	unsigned int lvds_clk_mask;
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index b7fc5b069cbc..cf045a203aa5 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -415,11 +415,7 @@ int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
 	if (ret < 0)
 		return ret;
 
-	 /*
-	  * The VSP2D (Gen3) has 5 RPFs, but the VSP1D (Gen2) is limited to
-	  * 4 RPFs.
-	  */
-	num_planes = rcdu->info->gen >= 3 ? 5 : 4;
+	num_planes = rcdu->info->num_rpf;
 
 	vsp->planes = kcalloc(num_planes, sizeof(*vsp->planes), GFP_KERNEL);
 	if (!vsp->planes)
-- 
2.17.1

[PATCH v2 3/7] drm: rcar-du: Add max_width and max_height to struct rcar_du_device_info

[Biju Das]

There are some differences related to max frame size supported by different
R-Car/RZ-G family of SoC's

Max frame size supported by R-Car Gen1 & R-Car Gen2 is 4095x2047
Max frame size supported by R-Car Gen3 is 8190x8190
Max frame size supported by RZ/G2L is 1920x1080

Add max_width and max_height to struct rcar_du_device_info to support later
SoC without any code changes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No Change
RFC->V1:
 * No Change
RFC:
 * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-13-biju.das.jz@bp.renesas.com/
---
 drivers/gpu/drm/rcar-du/rcar_du_drv.c | 36 +++++++++++++++++++++++++++
 drivers/gpu/drm/rcar-du/rcar_du_drv.h |  4 +++
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 17 +++++--------
 3 files changed, 46 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index 1bc7325aa356..4640c356a532 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -56,6 +56,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 4,
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
@@ -79,6 +81,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
 		},
 	},
 	.num_rpf = 4,
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
@@ -107,6 +111,8 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
 		},
 	},
 	.num_rpf = 4,
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
@@ -137,6 +143,8 @@ static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.dpll_mask =  BIT(1),
 };
 
@@ -168,6 +176,8 @@ static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.dpll_mask =  BIT(1),
 };
 
@@ -196,6 +206,8 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
 	},
 	.num_lvds = 2,
 	.num_rpf = 4,
+	.max_width = 8190,
+	.max_height = 8190,
 	.lvds_clk_mask =  BIT(1) | BIT(0),
 };
 
@@ -227,6 +239,8 @@ static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.dpll_mask =  BIT(1),
 };
 
@@ -249,6 +263,8 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
 			.port = 1,
 		},
 	},
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7790_info = {
@@ -280,6 +296,8 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
 	},
 	.num_lvds = 2,
 	.num_rpf = 4,
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
@@ -306,6 +324,8 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 4,
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7792_info = {
@@ -327,6 +347,8 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
 		},
 	},
 	.num_rpf = 4,
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7794_info = {
@@ -351,6 +373,8 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
 		},
 	},
 	.num_rpf = 4,
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7795_info = {
@@ -385,6 +409,8 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.dpll_mask =  BIT(2) | BIT(1),
 };
 
@@ -416,6 +442,8 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.dpll_mask =  BIT(1),
 };
 
@@ -447,6 +475,8 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.dpll_mask =  BIT(1),
 };
 
@@ -474,6 +504,8 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
@@ -502,6 +534,8 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
 	},
 	.num_lvds = 2,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.lvds_clk_mask =  BIT(1) | BIT(0),
 };
 
@@ -522,6 +556,8 @@ static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
 		},
 	},
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.dsi_clk_mask =  BIT(1) | BIT(0),
 };
 
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
index 68c5de59d18d..b0553b43363b 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
@@ -70,6 +70,8 @@ struct rcar_du_output_routing {
  * @routes: array of CRTC to output routes, indexed by output (RCAR_DU_OUTPUT_*)
  * @num_lvds: number of internal LVDS encoders
  * @num_rpf: max number of RPFs in VSP
+ * @max_width: max frame width
+ * @max_height: max frame height
  * @dpll_mask: bit mask of DU channels equipped with a DPLL
  * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot clock
  * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
@@ -82,6 +84,8 @@ struct rcar_du_device_info {
 	struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
 	unsigned int num_lvds;
 	unsigned int num_rpf;
+	unsigned int max_width;
+	unsigned int max_height;
 	unsigned int dpll_mask;
 	unsigned int dsi_clk_mask;
 	unsigned int lvds_clk_mask;
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index 190dbb7f15dd..5857705aac20 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -834,17 +834,12 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
 	dev->mode_config.funcs = &rcar_du_mode_config_funcs;
 	dev->mode_config.helper_private = &rcar_du_mode_config_helper;
 
-	if (rcdu->info->gen < 3) {
-		dev->mode_config.max_width = 4095;
-		dev->mode_config.max_height = 2047;
-	} else {
-		/*
-		 * The Gen3 DU uses the VSP1 for memory access, and is limited
-		 * to frame sizes of 8190x8190.
-		 */
-		dev->mode_config.max_width = 8190;
-		dev->mode_config.max_height = 8190;
-	}
+	/*
+	 * The Gen3 DU uses the VSP1 for memory access, and is limited
+	 * to frame sizes of 8190x8190.
+	 */
+	dev->mode_config.max_width = rcdu->info->max_width;
+	dev->mode_config.max_height = rcdu->info->max_height;
 
 	rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
 
-- 
2.17.1

[PATCH v2 3/7] drm: rcar-du: Add max_width and max_height to struct rcar_du_device_info

[Biju Das]

There are some differences related to max frame size supported by different
R-Car/RZ-G family of SoC's

Max frame size supported by R-Car Gen1 & R-Car Gen2 is 4095x2047
Max frame size supported by R-Car Gen3 is 8190x8190
Max frame size supported by RZ/G2L is 1920x1080

Add max_width and max_height to struct rcar_du_device_info to support later
SoC without any code changes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No Change
RFC->V1:
 * No Change
RFC:
 * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-13-biju.das.jz@bp.renesas.com/
---
 drivers/gpu/drm/rcar-du/rcar_du_drv.c | 36 +++++++++++++++++++++++++++
 drivers/gpu/drm/rcar-du/rcar_du_drv.h |  4 +++
 drivers/gpu/drm/rcar-du/rcar_du_kms.c | 17 +++++--------
 3 files changed, 46 insertions(+), 11 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index 1bc7325aa356..4640c356a532 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -56,6 +56,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 4,
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
@@ -79,6 +81,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
 		},
 	},
 	.num_rpf = 4,
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
@@ -107,6 +111,8 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
 		},
 	},
 	.num_rpf = 4,
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
@@ -137,6 +143,8 @@ static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.dpll_mask =  BIT(1),
 };
 
@@ -168,6 +176,8 @@ static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.dpll_mask =  BIT(1),
 };
 
@@ -196,6 +206,8 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
 	},
 	.num_lvds = 2,
 	.num_rpf = 4,
+	.max_width = 8190,
+	.max_height = 8190,
 	.lvds_clk_mask =  BIT(1) | BIT(0),
 };
 
@@ -227,6 +239,8 @@ static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.dpll_mask =  BIT(1),
 };
 
@@ -249,6 +263,8 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
 			.port = 1,
 		},
 	},
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7790_info = {
@@ -280,6 +296,8 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
 	},
 	.num_lvds = 2,
 	.num_rpf = 4,
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
@@ -306,6 +324,8 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 4,
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7792_info = {
@@ -327,6 +347,8 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
 		},
 	},
 	.num_rpf = 4,
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7794_info = {
@@ -351,6 +373,8 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
 		},
 	},
 	.num_rpf = 4,
+	.max_width = 4095,
+	.max_height = 2047,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7795_info = {
@@ -385,6 +409,8 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.dpll_mask =  BIT(2) | BIT(1),
 };
 
@@ -416,6 +442,8 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.dpll_mask =  BIT(1),
 };
 
@@ -447,6 +475,8 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.dpll_mask =  BIT(1),
 };
 
@@ -474,6 +504,8 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
 	},
 	.num_lvds = 1,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
@@ -502,6 +534,8 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
 	},
 	.num_lvds = 2,
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.lvds_clk_mask =  BIT(1) | BIT(0),
 };
 
@@ -522,6 +556,8 @@ static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
 		},
 	},
 	.num_rpf = 5,
+	.max_width = 8190,
+	.max_height = 8190,
 	.dsi_clk_mask =  BIT(1) | BIT(0),
 };
 
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
index 68c5de59d18d..b0553b43363b 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
@@ -70,6 +70,8 @@ struct rcar_du_output_routing {
  * @routes: array of CRTC to output routes, indexed by output (RCAR_DU_OUTPUT_*)
  * @num_lvds: number of internal LVDS encoders
  * @num_rpf: max number of RPFs in VSP
+ * @max_width: max frame width
+ * @max_height: max frame height
  * @dpll_mask: bit mask of DU channels equipped with a DPLL
  * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot clock
  * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
@@ -82,6 +84,8 @@ struct rcar_du_device_info {
 	struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
 	unsigned int num_lvds;
 	unsigned int num_rpf;
+	unsigned int max_width;
+	unsigned int max_height;
 	unsigned int dpll_mask;
 	unsigned int dsi_clk_mask;
 	unsigned int lvds_clk_mask;
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index 190dbb7f15dd..5857705aac20 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -834,17 +834,12 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
 	dev->mode_config.funcs = &rcar_du_mode_config_funcs;
 	dev->mode_config.helper_private = &rcar_du_mode_config_helper;
 
-	if (rcdu->info->gen < 3) {
-		dev->mode_config.max_width = 4095;
-		dev->mode_config.max_height = 2047;
-	} else {
-		/*
-		 * The Gen3 DU uses the VSP1 for memory access, and is limited
-		 * to frame sizes of 8190x8190.
-		 */
-		dev->mode_config.max_width = 8190;
-		dev->mode_config.max_height = 8190;
-	}
+	/*
+	 * The Gen3 DU uses the VSP1 for memory access, and is limited
+	 * to frame sizes of 8190x8190.
+	 */
+	dev->mode_config.max_width = rcdu->info->max_width;
+	dev->mode_config.max_height = rcdu->info->max_height;
 
 	rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
 
-- 
2.17.1

[PATCH v2 4/7] drm: rcar-du: Move rcar_du_output_name() to rcar_du_common.c

[Biju Das]

RZ/G2L SoC's does not have group/plane registers compared to RCar, hence it
needs a different CRTC implementation.

Move rcar_du_output_name() to a new common file rcar_du_common.c, So that
the same function can be reused by RZ/G2L SoC later.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No change
RFC->v1:
 New patch
---
 drivers/gpu/drm/rcar-du/Makefile         |  1 +
 drivers/gpu/drm/rcar-du/rcar_du_common.c | 30 ++++++++++++++++++++++++
 drivers/gpu/drm/rcar-du/rcar_du_drv.c    | 20 ----------------
 3 files changed, 31 insertions(+), 20 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_common.c

diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index e7275b5e7ec8..331e12d65a6b 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 rcar-du-drm-y := rcar_du_crtc.o \
+		 rcar_du_common.o \
 		 rcar_du_drv.o \
 		 rcar_du_encoder.o \
 		 rcar_du_group.o \
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_common.c b/drivers/gpu/drm/rcar-du/rcar_du_common.c
new file mode 100644
index 000000000000..f9f9908cda6d
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rcar_du_common.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * rcar_du_common.c  --  R-Car Display Unit Common
+ *
+ * Copyright (C) 2013-2022 Renesas Electronics Corporation
+ *
+ * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+ */
+
+#include "rcar_du_drv.h"
+
+const char *rcar_du_output_name(enum rcar_du_output output)
+{
+	static const char * const names[] = {
+		[RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
+		[RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
+		[RCAR_DU_OUTPUT_DSI0] = "DSI0",
+		[RCAR_DU_OUTPUT_DSI1] = "DSI1",
+		[RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
+		[RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
+		[RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
+		[RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
+		[RCAR_DU_OUTPUT_TCON] = "TCON",
+	};
+
+	if (output >= ARRAY_SIZE(names) || !names[output])
+		return "UNKNOWN";
+
+	return names[output];
+}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index 4640c356a532..f6e234dafb72 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -591,26 +591,6 @@ static const struct of_device_id rcar_du_of_table[] = {
 
 MODULE_DEVICE_TABLE(of, rcar_du_of_table);
 
-const char *rcar_du_output_name(enum rcar_du_output output)
-{
-	static const char * const names[] = {
-		[RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
-		[RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
-		[RCAR_DU_OUTPUT_DSI0] = "DSI0",
-		[RCAR_DU_OUTPUT_DSI1] = "DSI1",
-		[RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
-		[RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
-		[RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
-		[RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
-		[RCAR_DU_OUTPUT_TCON] = "TCON",
-	};
-
-	if (output >= ARRAY_SIZE(names) || !names[output])
-		return "UNKNOWN";
-
-	return names[output];
-}
-
 /* -----------------------------------------------------------------------------
  * DRM operations
  */
-- 
2.17.1

[PATCH v2 4/7] drm: rcar-du: Move rcar_du_output_name() to rcar_du_common.c

[Biju Das]

RZ/G2L SoC's does not have group/plane registers compared to RCar, hence it
needs a different CRTC implementation.

Move rcar_du_output_name() to a new common file rcar_du_common.c, So that
the same function can be reused by RZ/G2L SoC later.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No change
RFC->v1:
 New patch
---
 drivers/gpu/drm/rcar-du/Makefile         |  1 +
 drivers/gpu/drm/rcar-du/rcar_du_common.c | 30 ++++++++++++++++++++++++
 drivers/gpu/drm/rcar-du/rcar_du_drv.c    | 20 ----------------
 3 files changed, 31 insertions(+), 20 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_common.c

diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index e7275b5e7ec8..331e12d65a6b 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -1,5 +1,6 @@
 # SPDX-License-Identifier: GPL-2.0
 rcar-du-drm-y := rcar_du_crtc.o \
+		 rcar_du_common.o \
 		 rcar_du_drv.o \
 		 rcar_du_encoder.o \
 		 rcar_du_group.o \
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_common.c b/drivers/gpu/drm/rcar-du/rcar_du_common.c
new file mode 100644
index 000000000000..f9f9908cda6d
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rcar_du_common.c
@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * rcar_du_common.c  --  R-Car Display Unit Common
+ *
+ * Copyright (C) 2013-2022 Renesas Electronics Corporation
+ *
+ * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
+ */
+
+#include "rcar_du_drv.h"
+
+const char *rcar_du_output_name(enum rcar_du_output output)
+{
+	static const char * const names[] = {
+		[RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
+		[RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
+		[RCAR_DU_OUTPUT_DSI0] = "DSI0",
+		[RCAR_DU_OUTPUT_DSI1] = "DSI1",
+		[RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
+		[RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
+		[RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
+		[RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
+		[RCAR_DU_OUTPUT_TCON] = "TCON",
+	};
+
+	if (output >= ARRAY_SIZE(names) || !names[output])
+		return "UNKNOWN";
+
+	return names[output];
+}
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index 4640c356a532..f6e234dafb72 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -591,26 +591,6 @@ static const struct of_device_id rcar_du_of_table[] = {
 
 MODULE_DEVICE_TABLE(of, rcar_du_of_table);
 
-const char *rcar_du_output_name(enum rcar_du_output output)
-{
-	static const char * const names[] = {
-		[RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
-		[RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
-		[RCAR_DU_OUTPUT_DSI0] = "DSI0",
-		[RCAR_DU_OUTPUT_DSI1] = "DSI1",
-		[RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
-		[RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
-		[RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
-		[RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
-		[RCAR_DU_OUTPUT_TCON] = "TCON",
-	};
-
-	if (output >= ARRAY_SIZE(names) || !names[output])
-		return "UNKNOWN";
-
-	return names[output];
-}
-
 /* -----------------------------------------------------------------------------
  * DRM operations
  */
-- 
2.17.1

[PATCH v2 5/7] drm: rcar-du: Factorise rcar_du_{atomic_check,modeset_init}

[Biju Das]

RZ/G2L SoC's does not have group/plane registers compared to RCar, hence it
needs a different CRTC implementation. Factorise rcar_du_{atomic_check,
modeset_init} by adding struct rcar_du_crtc_helper_funcs to struct
rcar_du_device_info, so that it can support RZ/G2L SoC without any code
changes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * Changed crtc_helper_funcs->rcar_crtc_helper_funcs
RFC->v1:
 * New patch
---
 drivers/gpu/drm/rcar-du/rcar_du_drv.c | 24 ++++++++++++++++++++++++
 drivers/gpu/drm/rcar-du/rcar_du_drv.h | 16 ++++++++++++++++
 drivers/gpu/drm/rcar-du/rcar_du_kms.c |  6 +++---
 3 files changed, 43 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index f6e234dafb72..0df1430b9664 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -34,6 +34,12 @@
  * Device Information
  */
 
+static struct rcar_du_crtc_helper_funcs rcar_crtc_helper_funcs = {
+	.du_planes_init = rcar_du_planes_init,
+	.du_crtc_create = rcar_du_crtc_create,
+	.du_atomic_check_planes = rcar_du_atomic_check_planes,
+};
+
 static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
 	.gen = 2,
 	.features = RCAR_DU_FEATURE_CRTC_IRQ
@@ -58,6 +64,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
 	.num_rpf = 4,
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
@@ -83,6 +90,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
 	.num_rpf = 4,
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
@@ -113,6 +121,7 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
 	.num_rpf = 4,
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
@@ -146,6 +155,7 @@ static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.dpll_mask =  BIT(1),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
@@ -179,6 +189,7 @@ static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.dpll_mask =  BIT(1),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
@@ -209,6 +220,7 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.lvds_clk_mask =  BIT(1) | BIT(0),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
@@ -242,6 +254,7 @@ static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.dpll_mask =  BIT(1),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7779_info = {
@@ -265,6 +278,7 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
 	},
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7790_info = {
@@ -298,6 +312,7 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
 	.num_rpf = 4,
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
@@ -326,6 +341,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
 	.num_rpf = 4,
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7792_info = {
@@ -349,6 +365,7 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
 	.num_rpf = 4,
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7794_info = {
@@ -375,6 +392,7 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
 	.num_rpf = 4,
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7795_info = {
@@ -412,6 +430,7 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.dpll_mask =  BIT(2) | BIT(1),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7796_info = {
@@ -445,6 +464,7 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.dpll_mask =  BIT(1),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a77965_info = {
@@ -478,6 +498,7 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.dpll_mask =  BIT(1),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a77970_info = {
@@ -506,6 +527,7 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
 	.num_rpf = 5,
 	.max_width = 8190,
 	.max_height = 8190,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
@@ -537,6 +559,7 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.lvds_clk_mask =  BIT(1) | BIT(0),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
@@ -559,6 +582,7 @@ static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.dsi_clk_mask =  BIT(1) | BIT(0),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct of_device_id rcar_du_of_table[] = {
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
index b0553b43363b..164cd9854aaf 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
@@ -61,6 +61,20 @@ struct rcar_du_output_routing {
 	unsigned int port;
 };
 
+/*
+ * struct rcar_du_crtc_helper_funcs - CRTC helper functions
+ * @du_planes_init: pointer to du_plane_init function
+ * @du_crtc_create: pointer to du_crtc_create function
+ * @du_atomic_check_planes: pointer to du_atomic_check_planes function
+ */
+struct rcar_du_crtc_helper_funcs {
+	int (*du_planes_init)(struct rcar_du_group *rgrp);
+	int (*du_crtc_create)(struct rcar_du_group *rgrp, unsigned int swindex,
+			      unsigned int hwindex);
+	int (*du_atomic_check_planes)(struct drm_device *dev,
+				      struct drm_atomic_state *state);
+};
+
 /*
  * struct rcar_du_device_info - DU model-specific information
  * @gen: device generation (2 or 3)
@@ -75,6 +89,7 @@ struct rcar_du_output_routing {
  * @dpll_mask: bit mask of DU channels equipped with a DPLL
  * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot clock
  * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
+ * @fns: SoC specific CRTC helper functions
  */
 struct rcar_du_device_info {
 	unsigned int gen;
@@ -89,6 +104,7 @@ struct rcar_du_device_info {
 	unsigned int dpll_mask;
 	unsigned int dsi_clk_mask;
 	unsigned int lvds_clk_mask;
+	struct rcar_du_crtc_helper_funcs *fns;
 };
 
 #define RCAR_DU_MAX_CRTCS		4
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index 5857705aac20..a74417510894 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -478,7 +478,7 @@ static int rcar_du_atomic_check(struct drm_device *dev,
 	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
 		return 0;
 
-	return rcar_du_atomic_check_planes(dev, state);
+	return rcdu->info->fns->du_atomic_check_planes(dev, state);
 }
 
 static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
@@ -882,7 +882,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
 				   : 0;
 
 		if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
-			ret = rcar_du_planes_init(rgrp);
+			ret = rcdu->info->fns->du_planes_init(rgrp);
 			if (ret < 0)
 				return ret;
 		}
@@ -910,7 +910,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
 
 		rgrp = &rcdu->groups[hwindex / 2];
 
-		ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
+		ret = rcdu->info->fns->du_crtc_create(rgrp, swindex++, hwindex);
 		if (ret < 0)
 			return ret;
 	}
-- 
2.17.1

[PATCH v2 5/7] drm: rcar-du: Factorise rcar_du_{atomic_check, modeset_init}

[Biju Das]

RZ/G2L SoC's does not have group/plane registers compared to RCar, hence it
needs a different CRTC implementation. Factorise rcar_du_{atomic_check,
modeset_init} by adding struct rcar_du_crtc_helper_funcs to struct
rcar_du_device_info, so that it can support RZ/G2L SoC without any code
changes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * Changed crtc_helper_funcs->rcar_crtc_helper_funcs
RFC->v1:
 * New patch
---
 drivers/gpu/drm/rcar-du/rcar_du_drv.c | 24 ++++++++++++++++++++++++
 drivers/gpu/drm/rcar-du/rcar_du_drv.h | 16 ++++++++++++++++
 drivers/gpu/drm/rcar-du/rcar_du_kms.c |  6 +++---
 3 files changed, 43 insertions(+), 3 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index f6e234dafb72..0df1430b9664 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -34,6 +34,12 @@
  * Device Information
  */
 
+static struct rcar_du_crtc_helper_funcs rcar_crtc_helper_funcs = {
+	.du_planes_init = rcar_du_planes_init,
+	.du_crtc_create = rcar_du_crtc_create,
+	.du_atomic_check_planes = rcar_du_atomic_check_planes,
+};
+
 static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
 	.gen = 2,
 	.features = RCAR_DU_FEATURE_CRTC_IRQ
@@ -58,6 +64,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
 	.num_rpf = 4,
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
@@ -83,6 +90,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
 	.num_rpf = 4,
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
@@ -113,6 +121,7 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
 	.num_rpf = 4,
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
@@ -146,6 +155,7 @@ static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.dpll_mask =  BIT(1),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
@@ -179,6 +189,7 @@ static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.dpll_mask =  BIT(1),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
@@ -209,6 +220,7 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.lvds_clk_mask =  BIT(1) | BIT(0),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
@@ -242,6 +254,7 @@ static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.dpll_mask =  BIT(1),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7779_info = {
@@ -265,6 +278,7 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
 	},
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7790_info = {
@@ -298,6 +312,7 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
 	.num_rpf = 4,
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
@@ -326,6 +341,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
 	.num_rpf = 4,
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7792_info = {
@@ -349,6 +365,7 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
 	.num_rpf = 4,
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7794_info = {
@@ -375,6 +392,7 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
 	.num_rpf = 4,
 	.max_width = 4095,
 	.max_height = 2047,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7795_info = {
@@ -412,6 +430,7 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.dpll_mask =  BIT(2) | BIT(1),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7796_info = {
@@ -445,6 +464,7 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.dpll_mask =  BIT(1),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a77965_info = {
@@ -478,6 +498,7 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.dpll_mask =  BIT(1),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a77970_info = {
@@ -506,6 +527,7 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
 	.num_rpf = 5,
 	.max_width = 8190,
 	.max_height = 8190,
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
@@ -537,6 +559,7 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.lvds_clk_mask =  BIT(1) | BIT(0),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
@@ -559,6 +582,7 @@ static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
 	.max_width = 8190,
 	.max_height = 8190,
 	.dsi_clk_mask =  BIT(1) | BIT(0),
+	.fns = &rcar_crtc_helper_funcs,
 };
 
 static const struct of_device_id rcar_du_of_table[] = {
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
index b0553b43363b..164cd9854aaf 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
@@ -61,6 +61,20 @@ struct rcar_du_output_routing {
 	unsigned int port;
 };
 
+/*
+ * struct rcar_du_crtc_helper_funcs - CRTC helper functions
+ * @du_planes_init: pointer to du_plane_init function
+ * @du_crtc_create: pointer to du_crtc_create function
+ * @du_atomic_check_planes: pointer to du_atomic_check_planes function
+ */
+struct rcar_du_crtc_helper_funcs {
+	int (*du_planes_init)(struct rcar_du_group *rgrp);
+	int (*du_crtc_create)(struct rcar_du_group *rgrp, unsigned int swindex,
+			      unsigned int hwindex);
+	int (*du_atomic_check_planes)(struct drm_device *dev,
+				      struct drm_atomic_state *state);
+};
+
 /*
  * struct rcar_du_device_info - DU model-specific information
  * @gen: device generation (2 or 3)
@@ -75,6 +89,7 @@ struct rcar_du_output_routing {
  * @dpll_mask: bit mask of DU channels equipped with a DPLL
  * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot clock
  * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
+ * @fns: SoC specific CRTC helper functions
  */
 struct rcar_du_device_info {
 	unsigned int gen;
@@ -89,6 +104,7 @@ struct rcar_du_device_info {
 	unsigned int dpll_mask;
 	unsigned int dsi_clk_mask;
 	unsigned int lvds_clk_mask;
+	struct rcar_du_crtc_helper_funcs *fns;
 };
 
 #define RCAR_DU_MAX_CRTCS		4
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
index 5857705aac20..a74417510894 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
@@ -478,7 +478,7 @@ static int rcar_du_atomic_check(struct drm_device *dev,
 	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
 		return 0;
 
-	return rcar_du_atomic_check_planes(dev, state);
+	return rcdu->info->fns->du_atomic_check_planes(dev, state);
 }
 
 static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
@@ -882,7 +882,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
 				   : 0;
 
 		if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
-			ret = rcar_du_planes_init(rgrp);
+			ret = rcdu->info->fns->du_planes_init(rgrp);
 			if (ret < 0)
 				return ret;
 		}
@@ -910,7 +910,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
 
 		rgrp = &rcdu->groups[hwindex / 2];
 
-		ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
+		ret = rcdu->info->fns->du_crtc_create(rgrp, swindex++, hwindex);
 		if (ret < 0)
 			return ret;
 	}
-- 
2.17.1

[PATCH v2 6/7] drm: rcar-du: Factorise rcar_du_vsp{complete,enable,plane_atomic_check}

[Biju Das]

RZ/G2L SoC's does not have group/plane registers compared to RCar, hence
it needs a different CRTC implementation. Factorise rcar_du_vsp{complete,
enable,plane_atomic_check} so that it can support RZ/G2L SoC without any
code changes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No change
RFC->v1:
 * New patch
---
 drivers/gpu/drm/rcar-du/rcar_du_drv.c |  3 +++
 drivers/gpu/drm/rcar-du/rcar_du_drv.h |  9 +++++++++
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 12 ++++++++----
 3 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index 0df1430b9664..b944885d7f65 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -38,6 +38,9 @@ static struct rcar_du_crtc_helper_funcs rcar_crtc_helper_funcs = {
 	.du_planes_init = rcar_du_planes_init,
 	.du_crtc_create = rcar_du_crtc_create,
 	.du_atomic_check_planes = rcar_du_atomic_check_planes,
+	.__du_plane_setup = __rcar_du_plane_setup,
+	.__du_plane_atomic_check = __rcar_du_plane_atomic_check,
+	.du_crtc_finish_page_flip = rcar_du_crtc_finish_page_flip,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
index 164cd9854aaf..bb2146621eb4 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
@@ -66,6 +66,9 @@ struct rcar_du_output_routing {
  * @du_planes_init: pointer to du_plane_init function
  * @du_crtc_create: pointer to du_crtc_create function
  * @du_atomic_check_planes: pointer to du_atomic_check_planes function
+ * @__du_plane_setup: pointer to __du_plane_setup function
+ * @__du_plane_atomic_check: pointer to __du_plane_atomic_check function
+ * @du_crtc_finish_page_flip: pointer to du_crtc_finish_page_flip function
  */
 struct rcar_du_crtc_helper_funcs {
 	int (*du_planes_init)(struct rcar_du_group *rgrp);
@@ -73,6 +76,12 @@ struct rcar_du_crtc_helper_funcs {
 			      unsigned int hwindex);
 	int (*du_atomic_check_planes)(struct drm_device *dev,
 				      struct drm_atomic_state *state);
+	void (*__du_plane_setup)(struct rcar_du_group *rgrp,
+				 const struct rcar_du_plane_state *state);
+	int (*__du_plane_atomic_check)(struct drm_plane *plane,
+				       struct drm_plane_state *state,
+				const struct rcar_du_format_info **format);
+	void (*du_crtc_finish_page_flip)(struct rcar_du_crtc *rcrtc);
 };
 
 /*
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index cf045a203aa5..41928a94c903 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -35,12 +35,13 @@
 static void rcar_du_vsp_complete(void *private, unsigned int status, u32 crc)
 {
 	struct rcar_du_crtc *crtc = private;
+	struct rcar_du_device *rcdu = crtc->dev;
 
 	if (crtc->vblank_enable)
 		drm_crtc_handle_vblank(&crtc->crtc);
 
 	if (status & VSP1_DU_STATUS_COMPLETE)
-		rcar_du_crtc_finish_page_flip(crtc);
+		rcdu->info->fns->du_crtc_finish_page_flip(crtc);
 	if (status & VSP1_DU_STATUS_WRITEBACK)
 		rcar_du_writeback_complete(crtc);
 
@@ -82,7 +83,7 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
 	else
 		state.hwindex = crtc->index % 2;
 
-	__rcar_du_plane_setup(crtc->group, &state);
+	rcdu->info->fns->__du_plane_setup(crtc->group, &state);
 
 	/*
 	 * Ensure that the plane source configuration takes effect by requesting
@@ -294,12 +295,15 @@ static void rcar_du_vsp_plane_cleanup_fb(struct drm_plane *plane,
 static int rcar_du_vsp_plane_atomic_check(struct drm_plane *plane,
 					  struct drm_atomic_state *state)
 {
+	struct rcar_du_vsp *vsp = to_rcar_vsp_plane(plane)->vsp;
+	struct rcar_du_device *rcdu = vsp->dev;
+
 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 										 plane);
 	struct rcar_du_vsp_plane_state *rstate = to_rcar_vsp_plane_state(new_plane_state);
 
-	return __rcar_du_plane_atomic_check(plane, new_plane_state,
-					    &rstate->format);
+	return rcdu->info->fns->__du_plane_atomic_check(plane, new_plane_state,
+							&rstate->format);
 }
 
 static void rcar_du_vsp_plane_atomic_update(struct drm_plane *plane,
-- 
2.17.1

[PATCH v2 6/7] drm: rcar-du: Factorise rcar_du_vsp{complete, enable, plane_atomic_check}

[Biju Das]

RZ/G2L SoC's does not have group/plane registers compared to RCar, hence
it needs a different CRTC implementation. Factorise rcar_du_vsp{complete,
enable,plane_atomic_check} so that it can support RZ/G2L SoC without any
code changes.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * No change
RFC->v1:
 * New patch
---
 drivers/gpu/drm/rcar-du/rcar_du_drv.c |  3 +++
 drivers/gpu/drm/rcar-du/rcar_du_drv.h |  9 +++++++++
 drivers/gpu/drm/rcar-du/rcar_du_vsp.c | 12 ++++++++----
 3 files changed, 20 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
index 0df1430b9664..b944885d7f65 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
@@ -38,6 +38,9 @@ static struct rcar_du_crtc_helper_funcs rcar_crtc_helper_funcs = {
 	.du_planes_init = rcar_du_planes_init,
 	.du_crtc_create = rcar_du_crtc_create,
 	.du_atomic_check_planes = rcar_du_atomic_check_planes,
+	.__du_plane_setup = __rcar_du_plane_setup,
+	.__du_plane_atomic_check = __rcar_du_plane_atomic_check,
+	.du_crtc_finish_page_flip = rcar_du_crtc_finish_page_flip,
 };
 
 static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
index 164cd9854aaf..bb2146621eb4 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
@@ -66,6 +66,9 @@ struct rcar_du_output_routing {
  * @du_planes_init: pointer to du_plane_init function
  * @du_crtc_create: pointer to du_crtc_create function
  * @du_atomic_check_planes: pointer to du_atomic_check_planes function
+ * @__du_plane_setup: pointer to __du_plane_setup function
+ * @__du_plane_atomic_check: pointer to __du_plane_atomic_check function
+ * @du_crtc_finish_page_flip: pointer to du_crtc_finish_page_flip function
  */
 struct rcar_du_crtc_helper_funcs {
 	int (*du_planes_init)(struct rcar_du_group *rgrp);
@@ -73,6 +76,12 @@ struct rcar_du_crtc_helper_funcs {
 			      unsigned int hwindex);
 	int (*du_atomic_check_planes)(struct drm_device *dev,
 				      struct drm_atomic_state *state);
+	void (*__du_plane_setup)(struct rcar_du_group *rgrp,
+				 const struct rcar_du_plane_state *state);
+	int (*__du_plane_atomic_check)(struct drm_plane *plane,
+				       struct drm_plane_state *state,
+				const struct rcar_du_format_info **format);
+	void (*du_crtc_finish_page_flip)(struct rcar_du_crtc *rcrtc);
 };
 
 /*
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
index cf045a203aa5..41928a94c903 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
+++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
@@ -35,12 +35,13 @@
 static void rcar_du_vsp_complete(void *private, unsigned int status, u32 crc)
 {
 	struct rcar_du_crtc *crtc = private;
+	struct rcar_du_device *rcdu = crtc->dev;
 
 	if (crtc->vblank_enable)
 		drm_crtc_handle_vblank(&crtc->crtc);
 
 	if (status & VSP1_DU_STATUS_COMPLETE)
-		rcar_du_crtc_finish_page_flip(crtc);
+		rcdu->info->fns->du_crtc_finish_page_flip(crtc);
 	if (status & VSP1_DU_STATUS_WRITEBACK)
 		rcar_du_writeback_complete(crtc);
 
@@ -82,7 +83,7 @@ void rcar_du_vsp_enable(struct rcar_du_crtc *crtc)
 	else
 		state.hwindex = crtc->index % 2;
 
-	__rcar_du_plane_setup(crtc->group, &state);
+	rcdu->info->fns->__du_plane_setup(crtc->group, &state);
 
 	/*
 	 * Ensure that the plane source configuration takes effect by requesting
@@ -294,12 +295,15 @@ static void rcar_du_vsp_plane_cleanup_fb(struct drm_plane *plane,
 static int rcar_du_vsp_plane_atomic_check(struct drm_plane *plane,
 					  struct drm_atomic_state *state)
 {
+	struct rcar_du_vsp *vsp = to_rcar_vsp_plane(plane)->vsp;
+	struct rcar_du_device *rcdu = vsp->dev;
+
 	struct drm_plane_state *new_plane_state = drm_atomic_get_new_plane_state(state,
 										 plane);
 	struct rcar_du_vsp_plane_state *rstate = to_rcar_vsp_plane_state(new_plane_state);
 
-	return __rcar_du_plane_atomic_check(plane, new_plane_state,
-					    &rstate->format);
+	return rcdu->info->fns->__du_plane_atomic_check(plane, new_plane_state,
+							&rstate->format);
 }
 
 static void rcar_du_vsp_plane_atomic_update(struct drm_plane *plane,
-- 
2.17.1

[PATCH v2 7/7] drm: rcar-du: Add RZ/G2L DU Support

[Biju Das]

The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).

It has DPI/DSI interfaces and supports a maximum resolution of 1080p
along with 2 RPFs to support blending of two picture layers and
raster operations (ROPs).

The DU part is similar to RCar like DU is connected to VSPD, so reusing
most of the functionality from RCar. This patch introduces separate CRTC
handling as it does not have plane/group registers.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * Based on [1], all references to 'rzg2l_lcdc' replaced with 'rzg2l_du'
 * Updated commit header
 * Updated macro DRM_RZG2L_LCDC->DRM_RZG2L_DU
 * Replaced rzg2l-lcdc-drm->rzg2l-du-drm
 * Added forward declaration for struct reset_control

[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220312084205.31462-2-biju.das.jz@bp.renesas.com/
RFC->v1:
 * Added RZ/G2L LCDC driver with special handling for CRTC reusing
   most of RCar DU code
RFC:
 https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-19-biju.das.jz@bp.renesas.com/
---
 drivers/gpu/drm/rcar-du/Kconfig          |  18 +-
 drivers/gpu/drm/rcar-du/Makefile         |  12 +
 drivers/gpu/drm/rcar-du/rcar_du_crtc.h   |   8 +
 drivers/gpu/drm/rcar-du/rcar_du_plane.h  |  12 +
 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c  | 705 +++++++++++++++++++++++
 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c   | 221 +++++++
 drivers/gpu/drm/rcar-du/rzg2l_du_plane.c |  82 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h  |  64 ++
 8 files changed, 1120 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_plane.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index f6e6a6d5d987..e40fb0c53f9b 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -11,6 +11,19 @@ config DRM_RCAR_DU
 	  Choose this option if you have an R-Car chipset.
 	  If M is selected the module will be called rcar-du-drm.
 
+config DRM_RZG2L_DU
+	tristate "DRM Support for RZ/G2L DU"
+	depends on DRM && OF
+	depends on ARM || ARM64
+	depends on ARCH_RENESAS || COMPILE_TEST
+	select DRM_KMS_HELPER
+	select DRM_GEM_CMA_HELPER
+	select VIDEOMODE_HELPERS
+	help
+	  Choose this option if you have an RZ/G2L chipset.
+	  If M is selected the module will be called rzg2l-du-drm.
+
+
 config DRM_RCAR_USE_CMM
 	bool "R-Car DU Color Management Module (CMM) Support"
 	depends on DRM_RCAR_DU
@@ -54,12 +67,13 @@ config DRM_RCAR_MIPI_DSI
 config DRM_RCAR_VSP
 	bool "R-Car DU VSP Compositor Support" if ARM
 	default y if ARM64
-	depends on DRM_RCAR_DU
+	depends on DRM_RCAR_DU || DRM_RZG2L_DU
 	depends on VIDEO_RENESAS_VSP1=y || (VIDEO_RENESAS_VSP1 && DRM_RCAR_DU=m)
+	depends on VIDEO_RENESAS_VSP1=y || (VIDEO_RENESAS_VSP1 && DRM_RZG2L_DU=m)
 	help
 	  Enable support to expose the R-Car VSP Compositor as KMS planes.
 
 config DRM_RCAR_WRITEBACK
 	bool
 	default y if ARM64
-	depends on DRM_RCAR_DU
+	depends on DRM_RCAR_DU || DRM_RZG2L_DU
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index 331e12d65a6b..01ba78e56b53 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -7,15 +7,27 @@ rcar-du-drm-y := rcar_du_crtc.o \
 		 rcar_du_kms.o \
 		 rcar_du_plane.o \
 
+rzg2l-du-drm-y := rzg2l_du_crtc.o \
+		  rcar_du_common.o \
+		  rzg2l_du_drv.o \
+		  rcar_du_encoder.o \
+		  rcar_du_kms.o \
+		  rzg2l_du_plane.o \
+
 rcar-du-drm-$(CONFIG_DRM_RCAR_VSP)	+= rcar_du_vsp.o
 rcar-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rcar_du_writeback.o
 
+rzg2l-du-drm-$(CONFIG_DRM_RCAR_VSP)	+= rcar_du_vsp.o
+rzg2l-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rcar_du_writeback.o
+
 obj-$(CONFIG_DRM_RCAR_CMM)		+= rcar_cmm.o
 obj-$(CONFIG_DRM_RCAR_DU)		+= rcar-du-drm.o
 obj-$(CONFIG_DRM_RCAR_DW_HDMI)		+= rcar_dw_hdmi.o
 obj-$(CONFIG_DRM_RCAR_LVDS)		+= rcar_lvds.o
 obj-$(CONFIG_DRM_RCAR_MIPI_DSI)		+= rcar_mipi_dsi.o
 
+obj-$(CONFIG_DRM_RZG2L_DU)		+= rzg2l-du-drm.o
+
 # 'remote-endpoint' is fixed up at run-time
 DTC_FLAGS_rcar_du_of_lvds_r8a7790 += -Wno-graph_endpoint
 DTC_FLAGS_rcar_du_of_lvds_r8a7791 += -Wno-graph_endpoint
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
index 66e8839db708..65c1bf9a7e97 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
@@ -21,6 +21,7 @@
 
 struct rcar_du_group;
 struct rcar_du_vsp;
+struct reset_control;
 
 /**
  * struct rcar_du_crtc - the CRTC, representing a DU superposition processor
@@ -28,6 +29,7 @@ struct rcar_du_vsp;
  * @dev: the DU device
  * @clock: the CRTC functional clock
  * @extclock: external pixel dot clock (optional)
+ * @rstc: reset controller (optional)
  * @mmio_offset: offset of the CRTC registers in the DU MMIO block
  * @index: CRTC hardware index
  * @initialized: whether the CRTC has been initialized and clocks enabled
@@ -50,6 +52,7 @@ struct rcar_du_crtc {
 	struct rcar_du_device *dev;
 	struct clk *clock;
 	struct clk *extclock;
+	struct reset_control *rstc;
 	unsigned int mmio_offset;
 	unsigned int index;
 	bool initialized;
@@ -100,4 +103,9 @@ void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc);
 
 void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set);
 
+int rzg2l_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
+			 unsigned int hwindex);
+
+void rzg2l_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc);
+
 #endif /* __RCAR_DU_CRTC_H__ */
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.h b/drivers/gpu/drm/rcar-du/rcar_du_plane.h
index 81bbf207ad0e..62caeebf0c76 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.h
@@ -83,4 +83,16 @@ static inline void rcar_du_plane_setup(struct rcar_du_plane *plane)
 	return __rcar_du_plane_setup(plane->group, state);
 }
 
+int rzg2l_du_atomic_check_planes(struct drm_device *dev,
+				 struct drm_atomic_state *state);
+
+int __rzg2l_du_plane_atomic_check(struct drm_plane *plane,
+				  struct drm_plane_state *state,
+				  const struct rcar_du_format_info **format);
+
+int rzg2l_du_planes_init(struct rcar_du_group *rgrp);
+
+void __rzg2l_du_plane_setup(struct rcar_du_group *rgrp,
+			    const struct rcar_du_plane_state *state);
+
 #endif /* __RCAR_DU_PLANE_H__ */
diff --git a/drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c b/drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
new file mode 100644
index 000000000000..2eeb99c686af
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
@@ -0,0 +1,705 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * rzg2l_du_crtc.c  --  RZ/G2L DU CRTCs
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ *
+ * Based on rcar_du_crtc.c
+ */
+
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/sys_soc.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_device.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_plane_helper.h>
+#include <drm/drm_vblank.h>
+
+#include "rcar_du_crtc.h"
+#include "rcar_du_drv.h"
+#include "rcar_du_encoder.h"
+#include "rcar_du_kms.h"
+#include "rcar_du_plane.h"
+#include "rcar_du_vsp.h"
+#include "rzg2l_du_regs.h"
+
+/* -----------------------------------------------------------------------------
+ * Hardware Setup
+ */
+
+static void rzg2l_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
+{
+	const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
+	struct rcar_du_device *rcdu = rcrtc->dev;
+	unsigned long mode_clock = mode->clock * 1000;
+	u32 ditr0, ditr1, ditr2, ditr3, ditr4, ditr5, pbcr0;
+
+	clk_set_rate(rcrtc->extclock, mode_clock);
+
+	ditr0 = (DU_DITR0_DEMD_HIGH
+		 | ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DU_DITR0_VSPOL : 0)
+		 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DU_DITR0_HSPOL : 0));
+
+	ditr1 = DU_DITR1_VSA(mode->vsync_end - mode->vsync_start)
+		| DU_DITR1_VACTIVE(mode->vdisplay);
+
+	ditr2 = DU_DITR2_VBP(mode->vtotal - mode->vsync_end)
+		| DU_DITR2_VFP(mode->vsync_start - mode->vdisplay);
+
+	ditr3 = DU_DITR3_HSA(mode->hsync_end - mode->hsync_start)
+		| DU_DITR3_HACTIVE(mode->hdisplay);
+
+	ditr4 = DU_DITR4_HBP(mode->htotal - mode->hsync_end)
+		| DU_DITR4_HFP(mode->hsync_start - mode->hdisplay);
+
+	ditr5 = DU_DITR5_VSFT(0) | DU_DITR5_HSFT(0);
+
+	pbcr0 = DU_PBCR0_PB_DEP(0x1F);
+
+	rcar_du_write(rcdu, DU_DITR0, ditr0);
+	rcar_du_write(rcdu, DU_DITR1, ditr1);
+	rcar_du_write(rcdu, DU_DITR2, ditr2);
+	rcar_du_write(rcdu, DU_DITR3, ditr3);
+	rcar_du_write(rcdu, DU_DITR4, ditr4);
+	rcar_du_write(rcdu, DU_DITR5, ditr5);
+	rcar_du_write(rcdu, DU_PBCR0, pbcr0);
+}
+
+static void rzg2l_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
+{
+}
+
+/* -----------------------------------------------------------------------------
+ * Page Flip
+ */
+
+void rzg2l_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
+{
+	struct drm_pending_vblank_event *event;
+	struct drm_device *dev = rcrtc->crtc.dev;
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev->event_lock, flags);
+	event = rcrtc->event;
+	rcrtc->event = NULL;
+	spin_unlock_irqrestore(&dev->event_lock, flags);
+
+	if (!event)
+		return;
+
+	spin_lock_irqsave(&dev->event_lock, flags);
+	drm_crtc_send_vblank_event(&rcrtc->crtc, event);
+	wake_up(&rcrtc->flip_wait);
+	spin_unlock_irqrestore(&dev->event_lock, flags);
+
+	drm_crtc_vblank_put(&rcrtc->crtc);
+}
+
+static bool rzg2l_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
+{
+	struct drm_device *dev = rcrtc->crtc.dev;
+	unsigned long flags;
+	bool pending;
+
+	spin_lock_irqsave(&dev->event_lock, flags);
+	pending = rcrtc->event;
+	spin_unlock_irqrestore(&dev->event_lock, flags);
+
+	return pending;
+}
+
+static void rzg2l_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
+{
+	struct rcar_du_device *rcdu = rcrtc->dev;
+
+	if (wait_event_timeout(rcrtc->flip_wait,
+			       !rzg2l_du_crtc_page_flip_pending(rcrtc),
+			       msecs_to_jiffies(50)))
+		return;
+
+	dev_warn(rcdu->dev, "page flip timeout\n");
+
+	rzg2l_du_crtc_finish_page_flip(rcrtc);
+}
+
+/* -----------------------------------------------------------------------------
+ * Start/Stop and Suspend/Resume
+ */
+
+static void rzg2l_du_crtc_setup(struct rcar_du_crtc *rcrtc)
+{
+	/* Configure display timings and output routing */
+	rzg2l_du_crtc_set_display_timing(rcrtc);
+
+	/* Enable the VSP compositor. */
+	rcar_du_vsp_enable(rcrtc);
+
+	/* Turn vertical blanking interrupt reporting on. */
+	drm_crtc_vblank_on(&rcrtc->crtc);
+}
+
+static int rzg2l_du_crtc_get(struct rcar_du_crtc *rcrtc)
+{
+	int ret;
+
+	/*
+	 * Guard against double-get, as the function is called from both the
+	 * .atomic_enable() and .atomic_begin() handlers.
+	 */
+	if (rcrtc->initialized)
+		return 0;
+
+	ret = reset_control_deassert(rcrtc->rstc);
+	if (ret < 0)
+		goto error_reset;
+
+	ret = clk_prepare_enable(rcrtc->clock);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_prepare_enable(rcrtc->extclock);
+	if (ret < 0)
+		goto error_clock;
+
+	rzg2l_du_crtc_setup(rcrtc);
+	rcrtc->initialized = true;
+
+	return 0;
+
+error_clock:
+	clk_disable_unprepare(rcrtc->clock);
+error_reset:
+	reset_control_assert(rcrtc->rstc);
+	return ret;
+}
+
+static void rzg2l_du_crtc_put(struct rcar_du_crtc *rcrtc)
+{
+	clk_disable_unprepare(rcrtc->extclock);
+	clk_disable_unprepare(rcrtc->clock);
+	reset_control_assert(rcrtc->rstc);
+
+	rcrtc->initialized = false;
+}
+
+static void __rzg2l_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
+{
+	rcar_du_write(rgrp->dev, DU_MCR0, start ? DU_MCR0_DI_EN : 0);
+}
+
+static void rzg2l_du_crtc_start(struct rcar_du_crtc *rcrtc)
+{
+	__rzg2l_du_group_start_stop(rcrtc->group, true);
+}
+
+static void rzg2l_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
+{
+	struct rcar_du_device *rcdu = rcrtc->dev;
+	struct drm_crtc *crtc = &rcrtc->crtc;
+
+	/* Make sure vblank interrupts are enabled. */
+	drm_crtc_vblank_get(crtc);
+
+	if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
+				msecs_to_jiffies(100)))
+		dev_warn(rcdu->dev, "vertical blanking timeout\n");
+
+	drm_crtc_vblank_put(crtc);
+}
+
+static void rzg2l_du_crtc_stop(struct rcar_du_crtc *rcrtc)
+{
+	struct drm_crtc *crtc = &rcrtc->crtc;
+
+	/*
+	 * Disable all planes and wait for the change to take effect. This is
+	 * required as the plane enable registers are updated on vblank, and no
+	 * vblank will occur once the CRTC is stopped. Disabling planes when
+	 * starting the CRTC thus wouldn't be enough as it would start scanning
+	 * out immediately from old frame buffers until the next vblank.
+	 *
+	 * This increases the CRTC stop delay, especially when multiple CRTCs
+	 * are stopped in one operation as we now wait for one vblank per CRTC.
+	 * Whether this can be improved needs to be researched.
+	 */
+	rzg2l_du_crtc_disable_planes(rcrtc);
+
+	/*
+	 * Disable vertical blanking interrupt reporting. We first need to wait
+	 * for page flip completion before stopping the CRTC as userspace
+	 * expects page flips to eventually complete.
+	 */
+	rzg2l_du_crtc_wait_page_flip(rcrtc);
+	drm_crtc_vblank_off(crtc);
+
+	/* Disable the VSP compositor. */
+	rcar_du_vsp_disable(rcrtc);
+
+	__rzg2l_du_group_start_stop(rcrtc->group, false);
+}
+
+/* -----------------------------------------------------------------------------
+ * CRTC Functions
+ */
+
+static int rzg2l_du_crtc_atomic_check(struct drm_crtc *crtc,
+				      struct drm_atomic_state *state)
+{
+	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
+									  crtc);
+	struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc_state);
+	struct drm_encoder *encoder;
+
+	/* Store the routes from the CRTC output to the DU outputs. */
+	rstate->outputs = 0;
+
+	drm_for_each_encoder_mask(encoder, crtc->dev,
+				  crtc_state->encoder_mask) {
+		struct rcar_du_encoder *renc;
+
+		/* Skip the writeback encoder. */
+		if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
+			continue;
+
+		renc = to_rcar_encoder(encoder);
+		rstate->outputs |= BIT(renc->output);
+	}
+
+	return 0;
+}
+
+static void rzg2l_du_crtc_atomic_enable(struct drm_crtc *crtc,
+					struct drm_atomic_state *state)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+	rzg2l_du_crtc_get(rcrtc);
+
+	rzg2l_du_crtc_start(rcrtc);
+}
+
+static void rzg2l_du_crtc_atomic_disable(struct drm_crtc *crtc,
+					 struct drm_atomic_state *state)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+	rzg2l_du_crtc_stop(rcrtc);
+	rzg2l_du_crtc_put(rcrtc);
+
+	spin_lock_irq(&crtc->dev->event_lock);
+	if (crtc->state->event) {
+		drm_crtc_send_vblank_event(crtc, crtc->state->event);
+		crtc->state->event = NULL;
+	}
+	spin_unlock_irq(&crtc->dev->event_lock);
+}
+
+static void rzg2l_du_crtc_atomic_begin(struct drm_crtc *crtc,
+				       struct drm_atomic_state *state)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+	WARN_ON(!crtc->state->enable);
+
+	/*
+	 * If a mode set is in progress we can be called with the CRTC disabled.
+	 * We thus need to first get and setup the CRTC in order to configure
+	 * planes. We must *not* put the CRTC in .atomic_flush(), as it must be
+	 * kept awake until the .atomic_enable() call that will follow. The get
+	 * operation in .atomic_enable() will in that case be a no-op, and the
+	 * CRTC will be put later in .atomic_disable().
+	 *
+	 * If a mode set is not in progress the CRTC is enabled, and the
+	 * following get call will be a no-op. There is thus no need to balance
+	 * it in .atomic_flush() either.
+	 */
+	rzg2l_du_crtc_get(rcrtc);
+
+	rcar_du_vsp_atomic_begin(rcrtc);
+}
+
+void rzg2l_du_group_restart(struct rcar_du_group *rgrp)
+{
+	__rzg2l_du_group_start_stop(rgrp, false);
+	__rzg2l_du_group_start_stop(rgrp, true);
+}
+
+static void rzg2l_du_crtc_atomic_flush(struct drm_crtc *crtc,
+				       struct drm_atomic_state *state)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+	struct drm_device *dev = rcrtc->crtc.dev;
+	unsigned long flags;
+
+	rzg2l_du_crtc_update_planes(rcrtc);
+
+	if (crtc->state->event) {
+		WARN_ON(drm_crtc_vblank_get(crtc) != 0);
+
+		spin_lock_irqsave(&dev->event_lock, flags);
+		rcrtc->event = crtc->state->event;
+		crtc->state->event = NULL;
+		spin_unlock_irqrestore(&dev->event_lock, flags);
+	}
+
+	rcar_du_vsp_atomic_flush(rcrtc);
+}
+
+static enum drm_mode_status
+rzg2l_du_crtc_mode_valid(struct drm_crtc *crtc,
+			 const struct drm_display_mode *mode)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+	struct rcar_du_device *rcdu = rcrtc->dev;
+	bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
+	unsigned int min_sync_porch;
+	unsigned int vbp;
+
+	if (interlaced && !rcar_du_has(rcdu, RCAR_DU_FEATURE_INTERLACED))
+		return MODE_NO_INTERLACE;
+
+	/*
+	 * The hardware requires a minimum combined horizontal sync and back
+	 * porch of 20 pixels (when CMM isn't used) or 45 pixels (when CMM is
+	 * used), and a minimum vertical back porch of 3 lines.
+	 */
+	min_sync_porch = 20;
+
+	if (mode->htotal - mode->hsync_start < min_sync_porch)
+		return MODE_HBLANK_NARROW;
+
+	vbp = (mode->vtotal - mode->vsync_end) / (interlaced ? 2 : 1);
+	if (vbp < 3)
+		return MODE_VBLANK_NARROW;
+
+	return MODE_OK;
+}
+
+static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
+	.atomic_check = rzg2l_du_crtc_atomic_check,
+	.atomic_begin = rzg2l_du_crtc_atomic_begin,
+	.atomic_flush = rzg2l_du_crtc_atomic_flush,
+	.atomic_enable = rzg2l_du_crtc_atomic_enable,
+	.atomic_disable = rzg2l_du_crtc_atomic_disable,
+	.mode_valid = rzg2l_du_crtc_mode_valid,
+};
+
+static void rzg2l_du_crtc_crc_init(struct rcar_du_crtc *rcrtc)
+{
+	const char **sources;
+	unsigned int count;
+	int i = -1;
+
+	/* Reserve 1 for "auto" source. */
+	count = rcrtc->vsp->num_planes + 1;
+
+	sources = kmalloc_array(count, sizeof(*sources), GFP_KERNEL);
+	if (!sources)
+		return;
+
+	sources[0] = kstrdup("auto", GFP_KERNEL);
+	if (!sources[0])
+		goto error;
+
+	for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
+		struct drm_plane *plane = &rcrtc->vsp->planes[i].plane;
+		char name[16];
+
+		sprintf(name, "plane%u", plane->base.id);
+		sources[i + 1] = kstrdup(name, GFP_KERNEL);
+		if (!sources[i + 1])
+			goto error;
+	}
+
+	rcrtc->sources = sources;
+	rcrtc->sources_count = count;
+	return;
+
+error:
+	while (i >= 0) {
+		kfree(sources[i]);
+		i--;
+	}
+	kfree(sources);
+}
+
+static void rzg2l_du_crtc_crc_cleanup(struct rcar_du_crtc *rcrtc)
+{
+	unsigned int i;
+
+	if (!rcrtc->sources)
+		return;
+
+	for (i = 0; i < rcrtc->sources_count; i++)
+		kfree(rcrtc->sources[i]);
+	kfree(rcrtc->sources);
+
+	rcrtc->sources = NULL;
+	rcrtc->sources_count = 0;
+}
+
+static struct drm_crtc_state *
+rzg2l_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
+{
+	struct rcar_du_crtc_state *state;
+	struct rcar_du_crtc_state *copy;
+
+	if (WARN_ON(!crtc->state))
+		return NULL;
+
+	state = to_rcar_crtc_state(crtc->state);
+	copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
+	if (!copy)
+		return NULL;
+
+	__drm_atomic_helper_crtc_duplicate_state(crtc, &copy->state);
+
+	return &copy->state;
+}
+
+static void rzg2l_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
+					       struct drm_crtc_state *state)
+{
+	__drm_atomic_helper_crtc_destroy_state(state);
+	kfree(to_rcar_crtc_state(state));
+}
+
+static void rzg2l_du_crtc_cleanup(struct drm_crtc *crtc)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+	rzg2l_du_crtc_crc_cleanup(rcrtc);
+
+	return drm_crtc_cleanup(crtc);
+}
+
+static void rzg2l_du_crtc_reset(struct drm_crtc *crtc)
+{
+	struct rcar_du_crtc_state *state;
+
+	if (crtc->state) {
+		rzg2l_du_crtc_atomic_destroy_state(crtc, crtc->state);
+		crtc->state = NULL;
+	}
+
+	state = kzalloc(sizeof(*state), GFP_KERNEL);
+	if (!state)
+		return;
+
+	state->crc.source = VSP1_DU_CRC_NONE;
+	state->crc.index = 0;
+
+	__drm_atomic_helper_crtc_reset(crtc, &state->state);
+}
+
+static int rzg2l_du_crtc_enable_vblank(struct drm_crtc *crtc)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+	rcrtc->vblank_enable = true;
+
+	return 0;
+}
+
+static void rzg2l_du_crtc_disable_vblank(struct drm_crtc *crtc)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+	rcrtc->vblank_enable = false;
+}
+
+static int rzg2l_du_crtc_parse_crc_source(struct rcar_du_crtc *rcrtc,
+					  const char *source_name,
+					  enum vsp1_du_crc_source *source)
+{
+	unsigned int index;
+	int ret;
+
+	/*
+	 * Parse the source name. Supported values are "plane%u" to compute the
+	 * CRC on an input plane (%u is the plane ID), and "auto" to compute the
+	 * CRC on the composer (VSP) output.
+	 */
+
+	if (!source_name) {
+		*source = VSP1_DU_CRC_NONE;
+		return 0;
+	} else if (!strcmp(source_name, "auto")) {
+		*source = VSP1_DU_CRC_OUTPUT;
+		return 0;
+	} else if (strstarts(source_name, "plane")) {
+		unsigned int i;
+
+		*source = VSP1_DU_CRC_PLANE;
+
+		ret = kstrtouint(source_name + strlen("plane"), 10, &index);
+		if (ret < 0)
+			return ret;
+
+		for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
+			if (index == rcrtc->vsp->planes[i].plane.base.id)
+				return i;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static int rzg2l_du_crtc_verify_crc_source(struct drm_crtc *crtc,
+					   const char *source_name,
+					   size_t *values_cnt)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+	enum vsp1_du_crc_source source;
+
+	if (rzg2l_du_crtc_parse_crc_source(rcrtc, source_name, &source) < 0) {
+		DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
+		return -EINVAL;
+	}
+
+	*values_cnt = 1;
+	return 0;
+}
+
+static const char *const *
+rzg2l_du_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+	*count = rcrtc->sources_count;
+	return rcrtc->sources;
+}
+
+static int rzg2l_du_crtc_set_crc_source(struct drm_crtc *crtc,
+					const char *source_name)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+	struct drm_modeset_acquire_ctx ctx;
+	struct drm_crtc_state *crtc_state;
+	struct drm_atomic_state *state;
+	enum vsp1_du_crc_source source;
+	unsigned int index;
+	int ret;
+
+	ret = rzg2l_du_crtc_parse_crc_source(rcrtc, source_name, &source);
+	if (ret < 0)
+		return ret;
+
+	index = ret;
+
+	/* Perform an atomic commit to set the CRC source. */
+	drm_modeset_acquire_init(&ctx, 0);
+
+	state = drm_atomic_state_alloc(crtc->dev);
+	if (!state) {
+		ret = -ENOMEM;
+		goto unlock;
+	}
+
+	state->acquire_ctx = &ctx;
+
+retry:
+	crtc_state = drm_atomic_get_crtc_state(state, crtc);
+	if (!IS_ERR(crtc_state)) {
+		struct rcar_du_crtc_state *rcrtc_state;
+
+		rcrtc_state = to_rcar_crtc_state(crtc_state);
+		rcrtc_state->crc.source = source;
+		rcrtc_state->crc.index = index;
+
+		ret = drm_atomic_commit(state);
+	} else {
+		ret = PTR_ERR(crtc_state);
+	}
+
+	if (ret == -EDEADLK) {
+		drm_atomic_state_clear(state);
+		drm_modeset_backoff(&ctx);
+		goto retry;
+	}
+
+	drm_atomic_state_put(state);
+
+unlock:
+	drm_modeset_drop_locks(&ctx);
+	drm_modeset_acquire_fini(&ctx);
+
+	return ret;
+}
+
+static const struct drm_crtc_funcs crtc_funcs_rzg2l = {
+	.reset = rzg2l_du_crtc_reset,
+	.destroy = rzg2l_du_crtc_cleanup,
+	.set_config = drm_atomic_helper_set_config,
+	.page_flip = drm_atomic_helper_page_flip,
+	.atomic_duplicate_state = rzg2l_du_crtc_atomic_duplicate_state,
+	.atomic_destroy_state = rzg2l_du_crtc_atomic_destroy_state,
+	.enable_vblank = rzg2l_du_crtc_enable_vblank,
+	.disable_vblank = rzg2l_du_crtc_disable_vblank,
+	.set_crc_source = rzg2l_du_crtc_set_crc_source,
+	.verify_crc_source = rzg2l_du_crtc_verify_crc_source,
+	.get_crc_sources = rzg2l_du_crtc_get_crc_sources,
+};
+
+/* -----------------------------------------------------------------------------
+ * Initialization
+ */
+
+int rzg2l_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
+			 unsigned int hwindex)
+{
+	struct rcar_du_device *rcdu = rgrp->dev;
+	struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex];
+	struct drm_crtc *crtc = &rcrtc->crtc;
+	struct drm_plane *primary;
+	struct clk *clk;
+	int ret;
+
+	rcrtc->rstc = devm_reset_control_get_shared(rcdu->dev, NULL);
+	if (IS_ERR(rcrtc->rstc)) {
+		dev_err(rcdu->dev, "can't get cpg reset\n");
+		return PTR_ERR(rcrtc->rstc);
+	}
+
+	rcrtc->clock = devm_clk_get(rcdu->dev, "aclk");
+	if (IS_ERR(rcrtc->clock)) {
+		dev_err(rcdu->dev, "no DU main clock\n");
+		return PTR_ERR(rcrtc->clock);
+	}
+
+	clk = devm_clk_get(rcdu->dev, "vclk");
+	if (!IS_ERR(clk))
+		rcrtc->extclock = clk;
+	else if (PTR_ERR(clk) == -EPROBE_DEFER)
+		return -EPROBE_DEFER;
+
+	init_waitqueue_head(&rcrtc->flip_wait);
+	init_waitqueue_head(&rcrtc->vblank_wait);
+	spin_lock_init(&rcrtc->vblank_lock);
+
+	rcrtc->dev = rcdu;
+	rcrtc->group = rgrp;
+	rcrtc->index = hwindex;
+
+	primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
+
+	ret = drm_crtc_init_with_planes(&rcdu->ddev, crtc, primary, NULL,
+					&crtc_funcs_rzg2l,
+					NULL);
+	if (ret < 0)
+		return ret;
+
+	drm_crtc_helper_add(crtc, &crtc_helper_funcs);
+
+	rzg2l_du_crtc_crc_init(rcrtc);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/rcar-du/rzg2l_du_drv.c b/drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
new file mode 100644
index 000000000000..bfdaea500e6f
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * rzg2l_du_drv.c  --  RZ/G2L DU DRM driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ *
+ * Based on rcar_du_drv.c
+ */
+
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/slab.h>
+#include <linux/wait.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_probe_helper.h>
+
+#include "rcar_du_drv.h"
+#include "rcar_du_kms.h"
+
+/* -----------------------------------------------------------------------------
+ * Device Information
+ */
+
+static struct rcar_du_crtc_helper_funcs rzg2l_crtc_helper_funcs = {
+	.du_planes_init = rzg2l_du_planes_init,
+	.du_crtc_create = rzg2l_du_crtc_create,
+	.du_atomic_check_planes = rzg2l_du_atomic_check_planes,
+	.__du_plane_setup = __rzg2l_du_plane_setup,
+	.__du_plane_atomic_check = __rzg2l_du_plane_atomic_check,
+	.du_crtc_finish_page_flip = rzg2l_du_crtc_finish_page_flip,
+};
+
+static const struct rcar_du_device_info rzg2l_du_r9a07g044l_info = {
+	.gen = 3,
+	.features = RCAR_DU_FEATURE_CRTC_IRQ
+		  | RCAR_DU_FEATURE_CRTC_CLOCK
+		  | RCAR_DU_FEATURE_VSP1_SOURCE,
+	.channels_mask = BIT(0),
+	.routes = {
+		[RCAR_DU_OUTPUT_DPAD0] = {
+			.possible_crtcs = BIT(0),
+			.port = 0,
+		},
+		[RCAR_DU_OUTPUT_DSI0] = {
+			.possible_crtcs = BIT(0),
+			.port = 1,
+		},
+	},
+	.num_rpf = 2,
+	.max_width = 1920,
+	.max_height = 1080,
+	.fns = &rzg2l_crtc_helper_funcs,
+};
+
+static const struct of_device_id rzg2l_du_of_table[] = {
+	{ .compatible = "renesas,du-r9a07g044l", .data = &rzg2l_du_r9a07g044l_info },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, rzg2l_du_of_table);
+
+/* -----------------------------------------------------------------------------
+ * DRM operations
+ */
+
+DEFINE_DRM_GEM_CMA_FOPS(rzg2l_du_fops);
+
+static const struct drm_driver rzg2l_du_driver = {
+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
+	.dumb_create		= rcar_du_dumb_create,
+	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
+	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
+	.gem_prime_import_sg_table = rcar_du_gem_prime_import_sg_table,
+	.gem_prime_mmap		= drm_gem_prime_mmap,
+	.fops			= &rzg2l_du_fops,
+	.name			= "rzg2l-du",
+	.desc			= "Renesas RZ/G2L DU",
+	.date			= "20220305",
+	.major			= 1,
+	.minor			= 0,
+};
+
+/* -----------------------------------------------------------------------------
+ * Power management
+ */
+
+#ifdef CONFIG_PM_SLEEP
+static int rzg2l_du_pm_suspend(struct device *dev)
+{
+	struct rcar_du_device *rcdu = dev_get_drvdata(dev);
+
+	return drm_mode_config_helper_suspend(&rcdu->ddev);
+}
+
+static int rzg2l_du_pm_resume(struct device *dev)
+{
+	struct rcar_du_device *rcdu = dev_get_drvdata(dev);
+
+	return drm_mode_config_helper_resume(&rcdu->ddev);
+}
+#endif
+
+static const struct dev_pm_ops rzg2l_du_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(rzg2l_du_pm_suspend, rzg2l_du_pm_resume)
+};
+
+/* -----------------------------------------------------------------------------
+ * Platform driver
+ */
+
+static int rzg2l_du_remove(struct platform_device *pdev)
+{
+	struct rcar_du_device *rcdu = platform_get_drvdata(pdev);
+	struct drm_device *ddev = &rcdu->ddev;
+
+	drm_dev_unregister(ddev);
+	drm_atomic_helper_shutdown(ddev);
+
+	drm_kms_helper_poll_fini(ddev);
+
+	return 0;
+}
+
+static void rzg2l_du_shutdown(struct platform_device *pdev)
+{
+	struct rcar_du_device *rcdu = platform_get_drvdata(pdev);
+
+	drm_atomic_helper_shutdown(&rcdu->ddev);
+}
+
+static int rzg2l_du_probe(struct platform_device *pdev)
+{
+	struct rcar_du_device *rcdu;
+	unsigned int mask;
+	int ret;
+
+	if (drm_firmware_drivers_only())
+		return -ENODEV;
+
+	/* Allocate and initialize the R-Car device structure. */
+	rcdu = devm_drm_dev_alloc(&pdev->dev, &rzg2l_du_driver,
+				  struct rcar_du_device, ddev);
+	if (IS_ERR(rcdu))
+		return PTR_ERR(rcdu);
+
+	rcdu->dev = &pdev->dev;
+	rcdu->info = of_device_get_match_data(rcdu->dev);
+
+	platform_set_drvdata(pdev, rcdu);
+
+	/* I/O resources */
+	rcdu->mmio = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(rcdu->mmio))
+		return PTR_ERR(rcdu->mmio);
+
+	/*
+	 * Set the DMA coherent mask to reflect the DU 32-bit DMA address space
+	 * limitations. When sourcing frames from a VSP the DU doesn't perform
+	 * any memory access so set the mask to 40 bits to accept all buffers.
+	 */
+	mask = rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE) ? 40 : 32;
+	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(mask));
+	if (ret)
+		return ret;
+
+	/* DRM/KMS objects */
+	ret = rcar_du_modeset_init(rcdu);
+	if (ret < 0) {
+		if (ret != -EPROBE_DEFER)
+			dev_err(&pdev->dev,
+				"failed to initialize DRM/KMS (%d)\n", ret);
+		goto error;
+	}
+
+	/*
+	 * Register the DRM device with the core and the connectors with
+	 * sysfs.
+	 */
+	ret = drm_dev_register(&rcdu->ddev, 0);
+	if (ret)
+		goto error;
+
+	DRM_INFO("Device %s probed\n", dev_name(&pdev->dev));
+
+	drm_fbdev_generic_setup(&rcdu->ddev, 32);
+
+	return 0;
+
+error:
+	drm_kms_helper_poll_fini(&rcdu->ddev);
+	return ret;
+}
+
+static struct platform_driver rzg2l_du_platform_driver = {
+	.probe		= rzg2l_du_probe,
+	.remove		= rzg2l_du_remove,
+	.shutdown	= rzg2l_du_shutdown,
+	.driver		= {
+		.name	= "rzg2l-du",
+		.pm	= &rzg2l_du_pm_ops,
+		.of_match_table = rzg2l_du_of_table,
+	},
+};
+
+module_platform_driver(rzg2l_du_platform_driver);
+
+MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/G2L LCDC DRM Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/rcar-du/rzg2l_du_plane.c b/drivers/gpu/drm/rcar-du/rzg2l_du_plane.c
new file mode 100644
index 000000000000..a736a5f2e7a5
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rzg2l_du_plane.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * rzg2l_du_plane.c  --  RZ/G2L DU Planes
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ *
+ * Based on rcar_du_plane.c
+ */
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_device.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_plane_helper.h>
+
+#include "rcar_du_drv.h"
+#include "rcar_du_group.h"
+#include "rcar_du_kms.h"
+#include "rcar_du_plane.h"
+
+int rzg2l_du_atomic_check_planes(struct drm_device *dev,
+				 struct drm_atomic_state *state)
+{
+	return 0;
+}
+
+void __rzg2l_du_plane_setup(struct rcar_du_group *rgrp,
+			    const struct rcar_du_plane_state *state)
+{
+}
+
+int __rzg2l_du_plane_atomic_check(struct drm_plane *plane,
+				  struct drm_plane_state *state,
+				  const struct rcar_du_format_info **format)
+{
+	struct drm_device *dev = plane->dev;
+	struct drm_crtc_state *crtc_state;
+	int ret;
+
+	if (!state->crtc) {
+		/*
+		 * The visible field is not reset by the DRM core but only
+		 * updated by drm_plane_helper_check_state(), set it manually.
+		 */
+		state->visible = false;
+		*format = NULL;
+		return 0;
+	}
+
+	crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
+	if (IS_ERR(crtc_state))
+		return PTR_ERR(crtc_state);
+
+	ret = drm_atomic_helper_check_plane_state(state, crtc_state,
+						  DRM_PLANE_HELPER_NO_SCALING,
+						  DRM_PLANE_HELPER_NO_SCALING,
+						  true, true);
+	if (ret < 0)
+		return ret;
+
+	if (!state->visible) {
+		*format = NULL;
+		return 0;
+	}
+
+	*format = rcar_du_format_info(state->fb->format->format);
+	if (*format == NULL) {
+		dev_dbg(dev->dev, "%s: unsupported format %08x\n", __func__,
+			state->fb->format->format);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int rzg2l_du_planes_init(struct rcar_du_group *rgrp)
+{
+	return 0;
+}
diff --git a/drivers/gpu/drm/rcar-du/rzg2l_du_regs.h b/drivers/gpu/drm/rcar-du/rzg2l_du_regs.h
new file mode 100644
index 000000000000..cc2897649cde
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rzg2l_du_regs.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * rzg2l_lcdc_regs.h  --  RZ/G2L LCDC Registers Definitions
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ *
+ */
+
+#ifndef __RZG2L_DU_REGS_H__
+#define __RZG2L_DU_REGS_H__
+
+/* -----------------------------------------------------------------------------
+ * RZ/G2L Display Registers
+ */
+
+#define DU_MCR0			0x00
+#define DU_MCR0_DPI_OE		BIT(0)
+#define DU_MCR0_DI_EN		BIT(8)
+#define DU_MCR0_PB_CLR		BIT(16)
+
+#define DU_MSR0			0x04
+#define DU_MSR0_ST_DI_BSY	BIT(8)
+#define DU_MSR0_ST_PB_WFULL	BIT(16)
+#define DU_MSR0_ST_PB_WINIT	BIT(18)
+#define DU_MSR0_ST_PB_REMPTY	BIT(20)
+#define DU_MSR0_ST_PB_RUF	BIT(21)
+#define DU_MSR0_ST_PB_RINIT	BIT(22)
+
+#define DU_MSR1			0x08
+
+#define DU_IMR0			0x0C
+#define DU_MSR0_IM_PB_RUF	BIT(0)
+
+#define DU_DITR0		0x10
+#define DU_DITR0_DPI_CLKMD	BIT(0)
+#define DU_DITR0_DEMD_LOW	0x0
+#define DU_DITR0_DEMD_HIGH	(BIT(8) | BIT(9))
+#define DU_DITR0_VSPOL		BIT(16)
+#define DU_DITR0_HSPOL		BIT(17)
+
+#define DU_DITR1		0x14
+#define DU_DITR1_VSA(x)		((x) << 0)
+#define DU_DITR1_VACTIVE(x)	((x) << 16)
+
+#define DU_DITR2		0x18
+#define DU_DITR2_VBP(x)		((x) << 0)
+#define DU_DITR2_VFP(x)		((x) << 16)
+
+#define DU_DITR3		0x1C
+#define DU_DITR3_HSA(x)		((x) << 0)
+#define DU_DITR3_HACTIVE(x)	((x) << 16)
+
+#define DU_DITR4		0x20
+#define DU_DITR4_HBP(x)		((x) << 0)
+#define DU_DITR4_HFP(x)		((x) << 16)
+
+#define DU_DITR5		0x24
+#define DU_DITR5_VSFT(x)	((x) << 0)
+#define DU_DITR5_HSFT(x)	((x) << 16)
+
+#define DU_PBCR0		0x4C
+#define DU_PBCR0_PB_DEP(x)	((x) << 0)
+
+#endif /* __RZG2L_DU_REGS_H__ */
-- 
2.17.1

[PATCH v2 7/7] drm: rcar-du: Add RZ/G2L DU Support

[Biju Das]

The LCD controller is composed of Frame Compression Processor (FCPVD),
Video Signal Processor (VSPD), and Display Unit (DU).

It has DPI/DSI interfaces and supports a maximum resolution of 1080p
along with 2 RPFs to support blending of two picture layers and
raster operations (ROPs).

The DU part is similar to RCar like DU is connected to VSPD, so reusing
most of the functionality from RCar. This patch introduces separate CRTC
handling as it does not have plane/group registers.

Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v1->v2:
 * Based on [1], all references to 'rzg2l_lcdc' replaced with 'rzg2l_du'
 * Updated commit header
 * Updated macro DRM_RZG2L_LCDC->DRM_RZG2L_DU
 * Replaced rzg2l-lcdc-drm->rzg2l-du-drm
 * Added forward declaration for struct reset_control

[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220312084205.31462-2-biju.das.jz@bp.renesas.com/
RFC->v1:
 * Added RZ/G2L LCDC driver with special handling for CRTC reusing
   most of RCar DU code
RFC:
 https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-19-biju.das.jz@bp.renesas.com/
---
 drivers/gpu/drm/rcar-du/Kconfig          |  18 +-
 drivers/gpu/drm/rcar-du/Makefile         |  12 +
 drivers/gpu/drm/rcar-du/rcar_du_crtc.h   |   8 +
 drivers/gpu/drm/rcar-du/rcar_du_plane.h  |  12 +
 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c  | 705 +++++++++++++++++++++++
 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c   | 221 +++++++
 drivers/gpu/drm/rcar-du/rzg2l_du_plane.c |  82 +++
 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h  |  64 ++
 8 files changed, 1120 insertions(+), 2 deletions(-)
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_plane.c
 create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h

diff --git a/drivers/gpu/drm/rcar-du/Kconfig b/drivers/gpu/drm/rcar-du/Kconfig
index f6e6a6d5d987..e40fb0c53f9b 100644
--- a/drivers/gpu/drm/rcar-du/Kconfig
+++ b/drivers/gpu/drm/rcar-du/Kconfig
@@ -11,6 +11,19 @@ config DRM_RCAR_DU
 	  Choose this option if you have an R-Car chipset.
 	  If M is selected the module will be called rcar-du-drm.
 
+config DRM_RZG2L_DU
+	tristate "DRM Support for RZ/G2L DU"
+	depends on DRM && OF
+	depends on ARM || ARM64
+	depends on ARCH_RENESAS || COMPILE_TEST
+	select DRM_KMS_HELPER
+	select DRM_GEM_CMA_HELPER
+	select VIDEOMODE_HELPERS
+	help
+	  Choose this option if you have an RZ/G2L chipset.
+	  If M is selected the module will be called rzg2l-du-drm.
+
+
 config DRM_RCAR_USE_CMM
 	bool "R-Car DU Color Management Module (CMM) Support"
 	depends on DRM_RCAR_DU
@@ -54,12 +67,13 @@ config DRM_RCAR_MIPI_DSI
 config DRM_RCAR_VSP
 	bool "R-Car DU VSP Compositor Support" if ARM
 	default y if ARM64
-	depends on DRM_RCAR_DU
+	depends on DRM_RCAR_DU || DRM_RZG2L_DU
 	depends on VIDEO_RENESAS_VSP1=y || (VIDEO_RENESAS_VSP1 && DRM_RCAR_DU=m)
+	depends on VIDEO_RENESAS_VSP1=y || (VIDEO_RENESAS_VSP1 && DRM_RZG2L_DU=m)
 	help
 	  Enable support to expose the R-Car VSP Compositor as KMS planes.
 
 config DRM_RCAR_WRITEBACK
 	bool
 	default y if ARM64
-	depends on DRM_RCAR_DU
+	depends on DRM_RCAR_DU || DRM_RZG2L_DU
diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
index 331e12d65a6b..01ba78e56b53 100644
--- a/drivers/gpu/drm/rcar-du/Makefile
+++ b/drivers/gpu/drm/rcar-du/Makefile
@@ -7,15 +7,27 @@ rcar-du-drm-y := rcar_du_crtc.o \
 		 rcar_du_kms.o \
 		 rcar_du_plane.o \
 
+rzg2l-du-drm-y := rzg2l_du_crtc.o \
+		  rcar_du_common.o \
+		  rzg2l_du_drv.o \
+		  rcar_du_encoder.o \
+		  rcar_du_kms.o \
+		  rzg2l_du_plane.o \
+
 rcar-du-drm-$(CONFIG_DRM_RCAR_VSP)	+= rcar_du_vsp.o
 rcar-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rcar_du_writeback.o
 
+rzg2l-du-drm-$(CONFIG_DRM_RCAR_VSP)	+= rcar_du_vsp.o
+rzg2l-du-drm-$(CONFIG_DRM_RCAR_WRITEBACK) += rcar_du_writeback.o
+
 obj-$(CONFIG_DRM_RCAR_CMM)		+= rcar_cmm.o
 obj-$(CONFIG_DRM_RCAR_DU)		+= rcar-du-drm.o
 obj-$(CONFIG_DRM_RCAR_DW_HDMI)		+= rcar_dw_hdmi.o
 obj-$(CONFIG_DRM_RCAR_LVDS)		+= rcar_lvds.o
 obj-$(CONFIG_DRM_RCAR_MIPI_DSI)		+= rcar_mipi_dsi.o
 
+obj-$(CONFIG_DRM_RZG2L_DU)		+= rzg2l-du-drm.o
+
 # 'remote-endpoint' is fixed up at run-time
 DTC_FLAGS_rcar_du_of_lvds_r8a7790 += -Wno-graph_endpoint
 DTC_FLAGS_rcar_du_of_lvds_r8a7791 += -Wno-graph_endpoint
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
index 66e8839db708..65c1bf9a7e97 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_crtc.h
@@ -21,6 +21,7 @@
 
 struct rcar_du_group;
 struct rcar_du_vsp;
+struct reset_control;
 
 /**
  * struct rcar_du_crtc - the CRTC, representing a DU superposition processor
@@ -28,6 +29,7 @@ struct rcar_du_vsp;
  * @dev: the DU device
  * @clock: the CRTC functional clock
  * @extclock: external pixel dot clock (optional)
+ * @rstc: reset controller (optional)
  * @mmio_offset: offset of the CRTC registers in the DU MMIO block
  * @index: CRTC hardware index
  * @initialized: whether the CRTC has been initialized and clocks enabled
@@ -50,6 +52,7 @@ struct rcar_du_crtc {
 	struct rcar_du_device *dev;
 	struct clk *clock;
 	struct clk *extclock;
+	struct reset_control *rstc;
 	unsigned int mmio_offset;
 	unsigned int index;
 	bool initialized;
@@ -100,4 +103,9 @@ void rcar_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc);
 
 void rcar_du_crtc_dsysr_clr_set(struct rcar_du_crtc *rcrtc, u32 clr, u32 set);
 
+int rzg2l_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
+			 unsigned int hwindex);
+
+void rzg2l_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc);
+
 #endif /* __RCAR_DU_CRTC_H__ */
diff --git a/drivers/gpu/drm/rcar-du/rcar_du_plane.h b/drivers/gpu/drm/rcar-du/rcar_du_plane.h
index 81bbf207ad0e..62caeebf0c76 100644
--- a/drivers/gpu/drm/rcar-du/rcar_du_plane.h
+++ b/drivers/gpu/drm/rcar-du/rcar_du_plane.h
@@ -83,4 +83,16 @@ static inline void rcar_du_plane_setup(struct rcar_du_plane *plane)
 	return __rcar_du_plane_setup(plane->group, state);
 }
 
+int rzg2l_du_atomic_check_planes(struct drm_device *dev,
+				 struct drm_atomic_state *state);
+
+int __rzg2l_du_plane_atomic_check(struct drm_plane *plane,
+				  struct drm_plane_state *state,
+				  const struct rcar_du_format_info **format);
+
+int rzg2l_du_planes_init(struct rcar_du_group *rgrp);
+
+void __rzg2l_du_plane_setup(struct rcar_du_group *rgrp,
+			    const struct rcar_du_plane_state *state);
+
 #endif /* __RCAR_DU_PLANE_H__ */
diff --git a/drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c b/drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
new file mode 100644
index 000000000000..2eeb99c686af
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
@@ -0,0 +1,705 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * rzg2l_du_crtc.c  --  RZ/G2L DU CRTCs
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ *
+ * Based on rcar_du_crtc.c
+ */
+
+#include <linux/clk.h>
+#include <linux/mutex.h>
+#include <linux/platform_device.h>
+#include <linux/reset.h>
+#include <linux/sys_soc.h>
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_bridge.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_device.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_plane_helper.h>
+#include <drm/drm_vblank.h>
+
+#include "rcar_du_crtc.h"
+#include "rcar_du_drv.h"
+#include "rcar_du_encoder.h"
+#include "rcar_du_kms.h"
+#include "rcar_du_plane.h"
+#include "rcar_du_vsp.h"
+#include "rzg2l_du_regs.h"
+
+/* -----------------------------------------------------------------------------
+ * Hardware Setup
+ */
+
+static void rzg2l_du_crtc_set_display_timing(struct rcar_du_crtc *rcrtc)
+{
+	const struct drm_display_mode *mode = &rcrtc->crtc.state->adjusted_mode;
+	struct rcar_du_device *rcdu = rcrtc->dev;
+	unsigned long mode_clock = mode->clock * 1000;
+	u32 ditr0, ditr1, ditr2, ditr3, ditr4, ditr5, pbcr0;
+
+	clk_set_rate(rcrtc->extclock, mode_clock);
+
+	ditr0 = (DU_DITR0_DEMD_HIGH
+		 | ((mode->flags & DRM_MODE_FLAG_PVSYNC) ? DU_DITR0_VSPOL : 0)
+		 | ((mode->flags & DRM_MODE_FLAG_PHSYNC) ? DU_DITR0_HSPOL : 0));
+
+	ditr1 = DU_DITR1_VSA(mode->vsync_end - mode->vsync_start)
+		| DU_DITR1_VACTIVE(mode->vdisplay);
+
+	ditr2 = DU_DITR2_VBP(mode->vtotal - mode->vsync_end)
+		| DU_DITR2_VFP(mode->vsync_start - mode->vdisplay);
+
+	ditr3 = DU_DITR3_HSA(mode->hsync_end - mode->hsync_start)
+		| DU_DITR3_HACTIVE(mode->hdisplay);
+
+	ditr4 = DU_DITR4_HBP(mode->htotal - mode->hsync_end)
+		| DU_DITR4_HFP(mode->hsync_start - mode->hdisplay);
+
+	ditr5 = DU_DITR5_VSFT(0) | DU_DITR5_HSFT(0);
+
+	pbcr0 = DU_PBCR0_PB_DEP(0x1F);
+
+	rcar_du_write(rcdu, DU_DITR0, ditr0);
+	rcar_du_write(rcdu, DU_DITR1, ditr1);
+	rcar_du_write(rcdu, DU_DITR2, ditr2);
+	rcar_du_write(rcdu, DU_DITR3, ditr3);
+	rcar_du_write(rcdu, DU_DITR4, ditr4);
+	rcar_du_write(rcdu, DU_DITR5, ditr5);
+	rcar_du_write(rcdu, DU_PBCR0, pbcr0);
+}
+
+static void rzg2l_du_crtc_update_planes(struct rcar_du_crtc *rcrtc)
+{
+}
+
+/* -----------------------------------------------------------------------------
+ * Page Flip
+ */
+
+void rzg2l_du_crtc_finish_page_flip(struct rcar_du_crtc *rcrtc)
+{
+	struct drm_pending_vblank_event *event;
+	struct drm_device *dev = rcrtc->crtc.dev;
+	unsigned long flags;
+
+	spin_lock_irqsave(&dev->event_lock, flags);
+	event = rcrtc->event;
+	rcrtc->event = NULL;
+	spin_unlock_irqrestore(&dev->event_lock, flags);
+
+	if (!event)
+		return;
+
+	spin_lock_irqsave(&dev->event_lock, flags);
+	drm_crtc_send_vblank_event(&rcrtc->crtc, event);
+	wake_up(&rcrtc->flip_wait);
+	spin_unlock_irqrestore(&dev->event_lock, flags);
+
+	drm_crtc_vblank_put(&rcrtc->crtc);
+}
+
+static bool rzg2l_du_crtc_page_flip_pending(struct rcar_du_crtc *rcrtc)
+{
+	struct drm_device *dev = rcrtc->crtc.dev;
+	unsigned long flags;
+	bool pending;
+
+	spin_lock_irqsave(&dev->event_lock, flags);
+	pending = rcrtc->event;
+	spin_unlock_irqrestore(&dev->event_lock, flags);
+
+	return pending;
+}
+
+static void rzg2l_du_crtc_wait_page_flip(struct rcar_du_crtc *rcrtc)
+{
+	struct rcar_du_device *rcdu = rcrtc->dev;
+
+	if (wait_event_timeout(rcrtc->flip_wait,
+			       !rzg2l_du_crtc_page_flip_pending(rcrtc),
+			       msecs_to_jiffies(50)))
+		return;
+
+	dev_warn(rcdu->dev, "page flip timeout\n");
+
+	rzg2l_du_crtc_finish_page_flip(rcrtc);
+}
+
+/* -----------------------------------------------------------------------------
+ * Start/Stop and Suspend/Resume
+ */
+
+static void rzg2l_du_crtc_setup(struct rcar_du_crtc *rcrtc)
+{
+	/* Configure display timings and output routing */
+	rzg2l_du_crtc_set_display_timing(rcrtc);
+
+	/* Enable the VSP compositor. */
+	rcar_du_vsp_enable(rcrtc);
+
+	/* Turn vertical blanking interrupt reporting on. */
+	drm_crtc_vblank_on(&rcrtc->crtc);
+}
+
+static int rzg2l_du_crtc_get(struct rcar_du_crtc *rcrtc)
+{
+	int ret;
+
+	/*
+	 * Guard against double-get, as the function is called from both the
+	 * .atomic_enable() and .atomic_begin() handlers.
+	 */
+	if (rcrtc->initialized)
+		return 0;
+
+	ret = reset_control_deassert(rcrtc->rstc);
+	if (ret < 0)
+		goto error_reset;
+
+	ret = clk_prepare_enable(rcrtc->clock);
+	if (ret < 0)
+		return ret;
+
+	ret = clk_prepare_enable(rcrtc->extclock);
+	if (ret < 0)
+		goto error_clock;
+
+	rzg2l_du_crtc_setup(rcrtc);
+	rcrtc->initialized = true;
+
+	return 0;
+
+error_clock:
+	clk_disable_unprepare(rcrtc->clock);
+error_reset:
+	reset_control_assert(rcrtc->rstc);
+	return ret;
+}
+
+static void rzg2l_du_crtc_put(struct rcar_du_crtc *rcrtc)
+{
+	clk_disable_unprepare(rcrtc->extclock);
+	clk_disable_unprepare(rcrtc->clock);
+	reset_control_assert(rcrtc->rstc);
+
+	rcrtc->initialized = false;
+}
+
+static void __rzg2l_du_group_start_stop(struct rcar_du_group *rgrp, bool start)
+{
+	rcar_du_write(rgrp->dev, DU_MCR0, start ? DU_MCR0_DI_EN : 0);
+}
+
+static void rzg2l_du_crtc_start(struct rcar_du_crtc *rcrtc)
+{
+	__rzg2l_du_group_start_stop(rcrtc->group, true);
+}
+
+static void rzg2l_du_crtc_disable_planes(struct rcar_du_crtc *rcrtc)
+{
+	struct rcar_du_device *rcdu = rcrtc->dev;
+	struct drm_crtc *crtc = &rcrtc->crtc;
+
+	/* Make sure vblank interrupts are enabled. */
+	drm_crtc_vblank_get(crtc);
+
+	if (!wait_event_timeout(rcrtc->vblank_wait, rcrtc->vblank_count == 0,
+				msecs_to_jiffies(100)))
+		dev_warn(rcdu->dev, "vertical blanking timeout\n");
+
+	drm_crtc_vblank_put(crtc);
+}
+
+static void rzg2l_du_crtc_stop(struct rcar_du_crtc *rcrtc)
+{
+	struct drm_crtc *crtc = &rcrtc->crtc;
+
+	/*
+	 * Disable all planes and wait for the change to take effect. This is
+	 * required as the plane enable registers are updated on vblank, and no
+	 * vblank will occur once the CRTC is stopped. Disabling planes when
+	 * starting the CRTC thus wouldn't be enough as it would start scanning
+	 * out immediately from old frame buffers until the next vblank.
+	 *
+	 * This increases the CRTC stop delay, especially when multiple CRTCs
+	 * are stopped in one operation as we now wait for one vblank per CRTC.
+	 * Whether this can be improved needs to be researched.
+	 */
+	rzg2l_du_crtc_disable_planes(rcrtc);
+
+	/*
+	 * Disable vertical blanking interrupt reporting. We first need to wait
+	 * for page flip completion before stopping the CRTC as userspace
+	 * expects page flips to eventually complete.
+	 */
+	rzg2l_du_crtc_wait_page_flip(rcrtc);
+	drm_crtc_vblank_off(crtc);
+
+	/* Disable the VSP compositor. */
+	rcar_du_vsp_disable(rcrtc);
+
+	__rzg2l_du_group_start_stop(rcrtc->group, false);
+}
+
+/* -----------------------------------------------------------------------------
+ * CRTC Functions
+ */
+
+static int rzg2l_du_crtc_atomic_check(struct drm_crtc *crtc,
+				      struct drm_atomic_state *state)
+{
+	struct drm_crtc_state *crtc_state = drm_atomic_get_new_crtc_state(state,
+									  crtc);
+	struct rcar_du_crtc_state *rstate = to_rcar_crtc_state(crtc_state);
+	struct drm_encoder *encoder;
+
+	/* Store the routes from the CRTC output to the DU outputs. */
+	rstate->outputs = 0;
+
+	drm_for_each_encoder_mask(encoder, crtc->dev,
+				  crtc_state->encoder_mask) {
+		struct rcar_du_encoder *renc;
+
+		/* Skip the writeback encoder. */
+		if (encoder->encoder_type == DRM_MODE_ENCODER_VIRTUAL)
+			continue;
+
+		renc = to_rcar_encoder(encoder);
+		rstate->outputs |= BIT(renc->output);
+	}
+
+	return 0;
+}
+
+static void rzg2l_du_crtc_atomic_enable(struct drm_crtc *crtc,
+					struct drm_atomic_state *state)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+	rzg2l_du_crtc_get(rcrtc);
+
+	rzg2l_du_crtc_start(rcrtc);
+}
+
+static void rzg2l_du_crtc_atomic_disable(struct drm_crtc *crtc,
+					 struct drm_atomic_state *state)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+	rzg2l_du_crtc_stop(rcrtc);
+	rzg2l_du_crtc_put(rcrtc);
+
+	spin_lock_irq(&crtc->dev->event_lock);
+	if (crtc->state->event) {
+		drm_crtc_send_vblank_event(crtc, crtc->state->event);
+		crtc->state->event = NULL;
+	}
+	spin_unlock_irq(&crtc->dev->event_lock);
+}
+
+static void rzg2l_du_crtc_atomic_begin(struct drm_crtc *crtc,
+				       struct drm_atomic_state *state)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+	WARN_ON(!crtc->state->enable);
+
+	/*
+	 * If a mode set is in progress we can be called with the CRTC disabled.
+	 * We thus need to first get and setup the CRTC in order to configure
+	 * planes. We must *not* put the CRTC in .atomic_flush(), as it must be
+	 * kept awake until the .atomic_enable() call that will follow. The get
+	 * operation in .atomic_enable() will in that case be a no-op, and the
+	 * CRTC will be put later in .atomic_disable().
+	 *
+	 * If a mode set is not in progress the CRTC is enabled, and the
+	 * following get call will be a no-op. There is thus no need to balance
+	 * it in .atomic_flush() either.
+	 */
+	rzg2l_du_crtc_get(rcrtc);
+
+	rcar_du_vsp_atomic_begin(rcrtc);
+}
+
+void rzg2l_du_group_restart(struct rcar_du_group *rgrp)
+{
+	__rzg2l_du_group_start_stop(rgrp, false);
+	__rzg2l_du_group_start_stop(rgrp, true);
+}
+
+static void rzg2l_du_crtc_atomic_flush(struct drm_crtc *crtc,
+				       struct drm_atomic_state *state)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+	struct drm_device *dev = rcrtc->crtc.dev;
+	unsigned long flags;
+
+	rzg2l_du_crtc_update_planes(rcrtc);
+
+	if (crtc->state->event) {
+		WARN_ON(drm_crtc_vblank_get(crtc) != 0);
+
+		spin_lock_irqsave(&dev->event_lock, flags);
+		rcrtc->event = crtc->state->event;
+		crtc->state->event = NULL;
+		spin_unlock_irqrestore(&dev->event_lock, flags);
+	}
+
+	rcar_du_vsp_atomic_flush(rcrtc);
+}
+
+static enum drm_mode_status
+rzg2l_du_crtc_mode_valid(struct drm_crtc *crtc,
+			 const struct drm_display_mode *mode)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+	struct rcar_du_device *rcdu = rcrtc->dev;
+	bool interlaced = mode->flags & DRM_MODE_FLAG_INTERLACE;
+	unsigned int min_sync_porch;
+	unsigned int vbp;
+
+	if (interlaced && !rcar_du_has(rcdu, RCAR_DU_FEATURE_INTERLACED))
+		return MODE_NO_INTERLACE;
+
+	/*
+	 * The hardware requires a minimum combined horizontal sync and back
+	 * porch of 20 pixels (when CMM isn't used) or 45 pixels (when CMM is
+	 * used), and a minimum vertical back porch of 3 lines.
+	 */
+	min_sync_porch = 20;
+
+	if (mode->htotal - mode->hsync_start < min_sync_porch)
+		return MODE_HBLANK_NARROW;
+
+	vbp = (mode->vtotal - mode->vsync_end) / (interlaced ? 2 : 1);
+	if (vbp < 3)
+		return MODE_VBLANK_NARROW;
+
+	return MODE_OK;
+}
+
+static const struct drm_crtc_helper_funcs crtc_helper_funcs = {
+	.atomic_check = rzg2l_du_crtc_atomic_check,
+	.atomic_begin = rzg2l_du_crtc_atomic_begin,
+	.atomic_flush = rzg2l_du_crtc_atomic_flush,
+	.atomic_enable = rzg2l_du_crtc_atomic_enable,
+	.atomic_disable = rzg2l_du_crtc_atomic_disable,
+	.mode_valid = rzg2l_du_crtc_mode_valid,
+};
+
+static void rzg2l_du_crtc_crc_init(struct rcar_du_crtc *rcrtc)
+{
+	const char **sources;
+	unsigned int count;
+	int i = -1;
+
+	/* Reserve 1 for "auto" source. */
+	count = rcrtc->vsp->num_planes + 1;
+
+	sources = kmalloc_array(count, sizeof(*sources), GFP_KERNEL);
+	if (!sources)
+		return;
+
+	sources[0] = kstrdup("auto", GFP_KERNEL);
+	if (!sources[0])
+		goto error;
+
+	for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
+		struct drm_plane *plane = &rcrtc->vsp->planes[i].plane;
+		char name[16];
+
+		sprintf(name, "plane%u", plane->base.id);
+		sources[i + 1] = kstrdup(name, GFP_KERNEL);
+		if (!sources[i + 1])
+			goto error;
+	}
+
+	rcrtc->sources = sources;
+	rcrtc->sources_count = count;
+	return;
+
+error:
+	while (i >= 0) {
+		kfree(sources[i]);
+		i--;
+	}
+	kfree(sources);
+}
+
+static void rzg2l_du_crtc_crc_cleanup(struct rcar_du_crtc *rcrtc)
+{
+	unsigned int i;
+
+	if (!rcrtc->sources)
+		return;
+
+	for (i = 0; i < rcrtc->sources_count; i++)
+		kfree(rcrtc->sources[i]);
+	kfree(rcrtc->sources);
+
+	rcrtc->sources = NULL;
+	rcrtc->sources_count = 0;
+}
+
+static struct drm_crtc_state *
+rzg2l_du_crtc_atomic_duplicate_state(struct drm_crtc *crtc)
+{
+	struct rcar_du_crtc_state *state;
+	struct rcar_du_crtc_state *copy;
+
+	if (WARN_ON(!crtc->state))
+		return NULL;
+
+	state = to_rcar_crtc_state(crtc->state);
+	copy = kmemdup(state, sizeof(*state), GFP_KERNEL);
+	if (!copy)
+		return NULL;
+
+	__drm_atomic_helper_crtc_duplicate_state(crtc, &copy->state);
+
+	return &copy->state;
+}
+
+static void rzg2l_du_crtc_atomic_destroy_state(struct drm_crtc *crtc,
+					       struct drm_crtc_state *state)
+{
+	__drm_atomic_helper_crtc_destroy_state(state);
+	kfree(to_rcar_crtc_state(state));
+}
+
+static void rzg2l_du_crtc_cleanup(struct drm_crtc *crtc)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+	rzg2l_du_crtc_crc_cleanup(rcrtc);
+
+	return drm_crtc_cleanup(crtc);
+}
+
+static void rzg2l_du_crtc_reset(struct drm_crtc *crtc)
+{
+	struct rcar_du_crtc_state *state;
+
+	if (crtc->state) {
+		rzg2l_du_crtc_atomic_destroy_state(crtc, crtc->state);
+		crtc->state = NULL;
+	}
+
+	state = kzalloc(sizeof(*state), GFP_KERNEL);
+	if (!state)
+		return;
+
+	state->crc.source = VSP1_DU_CRC_NONE;
+	state->crc.index = 0;
+
+	__drm_atomic_helper_crtc_reset(crtc, &state->state);
+}
+
+static int rzg2l_du_crtc_enable_vblank(struct drm_crtc *crtc)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+	rcrtc->vblank_enable = true;
+
+	return 0;
+}
+
+static void rzg2l_du_crtc_disable_vblank(struct drm_crtc *crtc)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+	rcrtc->vblank_enable = false;
+}
+
+static int rzg2l_du_crtc_parse_crc_source(struct rcar_du_crtc *rcrtc,
+					  const char *source_name,
+					  enum vsp1_du_crc_source *source)
+{
+	unsigned int index;
+	int ret;
+
+	/*
+	 * Parse the source name. Supported values are "plane%u" to compute the
+	 * CRC on an input plane (%u is the plane ID), and "auto" to compute the
+	 * CRC on the composer (VSP) output.
+	 */
+
+	if (!source_name) {
+		*source = VSP1_DU_CRC_NONE;
+		return 0;
+	} else if (!strcmp(source_name, "auto")) {
+		*source = VSP1_DU_CRC_OUTPUT;
+		return 0;
+	} else if (strstarts(source_name, "plane")) {
+		unsigned int i;
+
+		*source = VSP1_DU_CRC_PLANE;
+
+		ret = kstrtouint(source_name + strlen("plane"), 10, &index);
+		if (ret < 0)
+			return ret;
+
+		for (i = 0; i < rcrtc->vsp->num_planes; ++i) {
+			if (index == rcrtc->vsp->planes[i].plane.base.id)
+				return i;
+		}
+	}
+
+	return -EINVAL;
+}
+
+static int rzg2l_du_crtc_verify_crc_source(struct drm_crtc *crtc,
+					   const char *source_name,
+					   size_t *values_cnt)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+	enum vsp1_du_crc_source source;
+
+	if (rzg2l_du_crtc_parse_crc_source(rcrtc, source_name, &source) < 0) {
+		DRM_DEBUG_DRIVER("unknown source %s\n", source_name);
+		return -EINVAL;
+	}
+
+	*values_cnt = 1;
+	return 0;
+}
+
+static const char *const *
+rzg2l_du_crtc_get_crc_sources(struct drm_crtc *crtc, size_t *count)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+
+	*count = rcrtc->sources_count;
+	return rcrtc->sources;
+}
+
+static int rzg2l_du_crtc_set_crc_source(struct drm_crtc *crtc,
+					const char *source_name)
+{
+	struct rcar_du_crtc *rcrtc = to_rcar_crtc(crtc);
+	struct drm_modeset_acquire_ctx ctx;
+	struct drm_crtc_state *crtc_state;
+	struct drm_atomic_state *state;
+	enum vsp1_du_crc_source source;
+	unsigned int index;
+	int ret;
+
+	ret = rzg2l_du_crtc_parse_crc_source(rcrtc, source_name, &source);
+	if (ret < 0)
+		return ret;
+
+	index = ret;
+
+	/* Perform an atomic commit to set the CRC source. */
+	drm_modeset_acquire_init(&ctx, 0);
+
+	state = drm_atomic_state_alloc(crtc->dev);
+	if (!state) {
+		ret = -ENOMEM;
+		goto unlock;
+	}
+
+	state->acquire_ctx = &ctx;
+
+retry:
+	crtc_state = drm_atomic_get_crtc_state(state, crtc);
+	if (!IS_ERR(crtc_state)) {
+		struct rcar_du_crtc_state *rcrtc_state;
+
+		rcrtc_state = to_rcar_crtc_state(crtc_state);
+		rcrtc_state->crc.source = source;
+		rcrtc_state->crc.index = index;
+
+		ret = drm_atomic_commit(state);
+	} else {
+		ret = PTR_ERR(crtc_state);
+	}
+
+	if (ret == -EDEADLK) {
+		drm_atomic_state_clear(state);
+		drm_modeset_backoff(&ctx);
+		goto retry;
+	}
+
+	drm_atomic_state_put(state);
+
+unlock:
+	drm_modeset_drop_locks(&ctx);
+	drm_modeset_acquire_fini(&ctx);
+
+	return ret;
+}
+
+static const struct drm_crtc_funcs crtc_funcs_rzg2l = {
+	.reset = rzg2l_du_crtc_reset,
+	.destroy = rzg2l_du_crtc_cleanup,
+	.set_config = drm_atomic_helper_set_config,
+	.page_flip = drm_atomic_helper_page_flip,
+	.atomic_duplicate_state = rzg2l_du_crtc_atomic_duplicate_state,
+	.atomic_destroy_state = rzg2l_du_crtc_atomic_destroy_state,
+	.enable_vblank = rzg2l_du_crtc_enable_vblank,
+	.disable_vblank = rzg2l_du_crtc_disable_vblank,
+	.set_crc_source = rzg2l_du_crtc_set_crc_source,
+	.verify_crc_source = rzg2l_du_crtc_verify_crc_source,
+	.get_crc_sources = rzg2l_du_crtc_get_crc_sources,
+};
+
+/* -----------------------------------------------------------------------------
+ * Initialization
+ */
+
+int rzg2l_du_crtc_create(struct rcar_du_group *rgrp, unsigned int swindex,
+			 unsigned int hwindex)
+{
+	struct rcar_du_device *rcdu = rgrp->dev;
+	struct rcar_du_crtc *rcrtc = &rcdu->crtcs[swindex];
+	struct drm_crtc *crtc = &rcrtc->crtc;
+	struct drm_plane *primary;
+	struct clk *clk;
+	int ret;
+
+	rcrtc->rstc = devm_reset_control_get_shared(rcdu->dev, NULL);
+	if (IS_ERR(rcrtc->rstc)) {
+		dev_err(rcdu->dev, "can't get cpg reset\n");
+		return PTR_ERR(rcrtc->rstc);
+	}
+
+	rcrtc->clock = devm_clk_get(rcdu->dev, "aclk");
+	if (IS_ERR(rcrtc->clock)) {
+		dev_err(rcdu->dev, "no DU main clock\n");
+		return PTR_ERR(rcrtc->clock);
+	}
+
+	clk = devm_clk_get(rcdu->dev, "vclk");
+	if (!IS_ERR(clk))
+		rcrtc->extclock = clk;
+	else if (PTR_ERR(clk) == -EPROBE_DEFER)
+		return -EPROBE_DEFER;
+
+	init_waitqueue_head(&rcrtc->flip_wait);
+	init_waitqueue_head(&rcrtc->vblank_wait);
+	spin_lock_init(&rcrtc->vblank_lock);
+
+	rcrtc->dev = rcdu;
+	rcrtc->group = rgrp;
+	rcrtc->index = hwindex;
+
+	primary = &rcrtc->vsp->planes[rcrtc->vsp_pipe].plane;
+
+	ret = drm_crtc_init_with_planes(&rcdu->ddev, crtc, primary, NULL,
+					&crtc_funcs_rzg2l,
+					NULL);
+	if (ret < 0)
+		return ret;
+
+	drm_crtc_helper_add(crtc, &crtc_helper_funcs);
+
+	rzg2l_du_crtc_crc_init(rcrtc);
+
+	return 0;
+}
diff --git a/drivers/gpu/drm/rcar-du/rzg2l_du_drv.c b/drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
new file mode 100644
index 000000000000..bfdaea500e6f
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
@@ -0,0 +1,221 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * rzg2l_du_drv.c  --  RZ/G2L DU DRM driver
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ *
+ * Based on rcar_du_drv.c
+ */
+
+#include <linux/clk.h>
+#include <linux/dma-mapping.h>
+#include <linux/io.h>
+#include <linux/mm.h>
+#include <linux/module.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm.h>
+#include <linux/slab.h>
+#include <linux/wait.h>
+
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_drv.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_fb_helper.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_managed.h>
+#include <drm/drm_probe_helper.h>
+
+#include "rcar_du_drv.h"
+#include "rcar_du_kms.h"
+
+/* -----------------------------------------------------------------------------
+ * Device Information
+ */
+
+static struct rcar_du_crtc_helper_funcs rzg2l_crtc_helper_funcs = {
+	.du_planes_init = rzg2l_du_planes_init,
+	.du_crtc_create = rzg2l_du_crtc_create,
+	.du_atomic_check_planes = rzg2l_du_atomic_check_planes,
+	.__du_plane_setup = __rzg2l_du_plane_setup,
+	.__du_plane_atomic_check = __rzg2l_du_plane_atomic_check,
+	.du_crtc_finish_page_flip = rzg2l_du_crtc_finish_page_flip,
+};
+
+static const struct rcar_du_device_info rzg2l_du_r9a07g044l_info = {
+	.gen = 3,
+	.features = RCAR_DU_FEATURE_CRTC_IRQ
+		  | RCAR_DU_FEATURE_CRTC_CLOCK
+		  | RCAR_DU_FEATURE_VSP1_SOURCE,
+	.channels_mask = BIT(0),
+	.routes = {
+		[RCAR_DU_OUTPUT_DPAD0] = {
+			.possible_crtcs = BIT(0),
+			.port = 0,
+		},
+		[RCAR_DU_OUTPUT_DSI0] = {
+			.possible_crtcs = BIT(0),
+			.port = 1,
+		},
+	},
+	.num_rpf = 2,
+	.max_width = 1920,
+	.max_height = 1080,
+	.fns = &rzg2l_crtc_helper_funcs,
+};
+
+static const struct of_device_id rzg2l_du_of_table[] = {
+	{ .compatible = "renesas,du-r9a07g044l", .data = &rzg2l_du_r9a07g044l_info },
+	{ }
+};
+
+MODULE_DEVICE_TABLE(of, rzg2l_du_of_table);
+
+/* -----------------------------------------------------------------------------
+ * DRM operations
+ */
+
+DEFINE_DRM_GEM_CMA_FOPS(rzg2l_du_fops);
+
+static const struct drm_driver rzg2l_du_driver = {
+	.driver_features	= DRIVER_GEM | DRIVER_MODESET | DRIVER_ATOMIC,
+	.dumb_create		= rcar_du_dumb_create,
+	.prime_handle_to_fd	= drm_gem_prime_handle_to_fd,
+	.prime_fd_to_handle	= drm_gem_prime_fd_to_handle,
+	.gem_prime_import_sg_table = rcar_du_gem_prime_import_sg_table,
+	.gem_prime_mmap		= drm_gem_prime_mmap,
+	.fops			= &rzg2l_du_fops,
+	.name			= "rzg2l-du",
+	.desc			= "Renesas RZ/G2L DU",
+	.date			= "20220305",
+	.major			= 1,
+	.minor			= 0,
+};
+
+/* -----------------------------------------------------------------------------
+ * Power management
+ */
+
+#ifdef CONFIG_PM_SLEEP
+static int rzg2l_du_pm_suspend(struct device *dev)
+{
+	struct rcar_du_device *rcdu = dev_get_drvdata(dev);
+
+	return drm_mode_config_helper_suspend(&rcdu->ddev);
+}
+
+static int rzg2l_du_pm_resume(struct device *dev)
+{
+	struct rcar_du_device *rcdu = dev_get_drvdata(dev);
+
+	return drm_mode_config_helper_resume(&rcdu->ddev);
+}
+#endif
+
+static const struct dev_pm_ops rzg2l_du_pm_ops = {
+	SET_SYSTEM_SLEEP_PM_OPS(rzg2l_du_pm_suspend, rzg2l_du_pm_resume)
+};
+
+/* -----------------------------------------------------------------------------
+ * Platform driver
+ */
+
+static int rzg2l_du_remove(struct platform_device *pdev)
+{
+	struct rcar_du_device *rcdu = platform_get_drvdata(pdev);
+	struct drm_device *ddev = &rcdu->ddev;
+
+	drm_dev_unregister(ddev);
+	drm_atomic_helper_shutdown(ddev);
+
+	drm_kms_helper_poll_fini(ddev);
+
+	return 0;
+}
+
+static void rzg2l_du_shutdown(struct platform_device *pdev)
+{
+	struct rcar_du_device *rcdu = platform_get_drvdata(pdev);
+
+	drm_atomic_helper_shutdown(&rcdu->ddev);
+}
+
+static int rzg2l_du_probe(struct platform_device *pdev)
+{
+	struct rcar_du_device *rcdu;
+	unsigned int mask;
+	int ret;
+
+	if (drm_firmware_drivers_only())
+		return -ENODEV;
+
+	/* Allocate and initialize the R-Car device structure. */
+	rcdu = devm_drm_dev_alloc(&pdev->dev, &rzg2l_du_driver,
+				  struct rcar_du_device, ddev);
+	if (IS_ERR(rcdu))
+		return PTR_ERR(rcdu);
+
+	rcdu->dev = &pdev->dev;
+	rcdu->info = of_device_get_match_data(rcdu->dev);
+
+	platform_set_drvdata(pdev, rcdu);
+
+	/* I/O resources */
+	rcdu->mmio = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(rcdu->mmio))
+		return PTR_ERR(rcdu->mmio);
+
+	/*
+	 * Set the DMA coherent mask to reflect the DU 32-bit DMA address space
+	 * limitations. When sourcing frames from a VSP the DU doesn't perform
+	 * any memory access so set the mask to 40 bits to accept all buffers.
+	 */
+	mask = rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE) ? 40 : 32;
+	ret = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(mask));
+	if (ret)
+		return ret;
+
+	/* DRM/KMS objects */
+	ret = rcar_du_modeset_init(rcdu);
+	if (ret < 0) {
+		if (ret != -EPROBE_DEFER)
+			dev_err(&pdev->dev,
+				"failed to initialize DRM/KMS (%d)\n", ret);
+		goto error;
+	}
+
+	/*
+	 * Register the DRM device with the core and the connectors with
+	 * sysfs.
+	 */
+	ret = drm_dev_register(&rcdu->ddev, 0);
+	if (ret)
+		goto error;
+
+	DRM_INFO("Device %s probed\n", dev_name(&pdev->dev));
+
+	drm_fbdev_generic_setup(&rcdu->ddev, 32);
+
+	return 0;
+
+error:
+	drm_kms_helper_poll_fini(&rcdu->ddev);
+	return ret;
+}
+
+static struct platform_driver rzg2l_du_platform_driver = {
+	.probe		= rzg2l_du_probe,
+	.remove		= rzg2l_du_remove,
+	.shutdown	= rzg2l_du_shutdown,
+	.driver		= {
+		.name	= "rzg2l-du",
+		.pm	= &rzg2l_du_pm_ops,
+		.of_match_table = rzg2l_du_of_table,
+	},
+};
+
+module_platform_driver(rzg2l_du_platform_driver);
+
+MODULE_AUTHOR("Biju Das <biju.das.jz@bp.renesas.com>");
+MODULE_DESCRIPTION("Renesas RZ/G2L LCDC DRM Driver");
+MODULE_LICENSE("GPL");
diff --git a/drivers/gpu/drm/rcar-du/rzg2l_du_plane.c b/drivers/gpu/drm/rcar-du/rzg2l_du_plane.c
new file mode 100644
index 000000000000..a736a5f2e7a5
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rzg2l_du_plane.c
@@ -0,0 +1,82 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * rzg2l_du_plane.c  --  RZ/G2L DU Planes
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ *
+ * Based on rcar_du_plane.c
+ */
+
+#include <drm/drm_atomic.h>
+#include <drm/drm_atomic_helper.h>
+#include <drm/drm_crtc.h>
+#include <drm/drm_device.h>
+#include <drm/drm_fb_cma_helper.h>
+#include <drm/drm_fourcc.h>
+#include <drm/drm_gem_cma_helper.h>
+#include <drm/drm_plane_helper.h>
+
+#include "rcar_du_drv.h"
+#include "rcar_du_group.h"
+#include "rcar_du_kms.h"
+#include "rcar_du_plane.h"
+
+int rzg2l_du_atomic_check_planes(struct drm_device *dev,
+				 struct drm_atomic_state *state)
+{
+	return 0;
+}
+
+void __rzg2l_du_plane_setup(struct rcar_du_group *rgrp,
+			    const struct rcar_du_plane_state *state)
+{
+}
+
+int __rzg2l_du_plane_atomic_check(struct drm_plane *plane,
+				  struct drm_plane_state *state,
+				  const struct rcar_du_format_info **format)
+{
+	struct drm_device *dev = plane->dev;
+	struct drm_crtc_state *crtc_state;
+	int ret;
+
+	if (!state->crtc) {
+		/*
+		 * The visible field is not reset by the DRM core but only
+		 * updated by drm_plane_helper_check_state(), set it manually.
+		 */
+		state->visible = false;
+		*format = NULL;
+		return 0;
+	}
+
+	crtc_state = drm_atomic_get_crtc_state(state->state, state->crtc);
+	if (IS_ERR(crtc_state))
+		return PTR_ERR(crtc_state);
+
+	ret = drm_atomic_helper_check_plane_state(state, crtc_state,
+						  DRM_PLANE_HELPER_NO_SCALING,
+						  DRM_PLANE_HELPER_NO_SCALING,
+						  true, true);
+	if (ret < 0)
+		return ret;
+
+	if (!state->visible) {
+		*format = NULL;
+		return 0;
+	}
+
+	*format = rcar_du_format_info(state->fb->format->format);
+	if (*format == NULL) {
+		dev_dbg(dev->dev, "%s: unsupported format %08x\n", __func__,
+			state->fb->format->format);
+		return -EINVAL;
+	}
+
+	return 0;
+}
+
+int rzg2l_du_planes_init(struct rcar_du_group *rgrp)
+{
+	return 0;
+}
diff --git a/drivers/gpu/drm/rcar-du/rzg2l_du_regs.h b/drivers/gpu/drm/rcar-du/rzg2l_du_regs.h
new file mode 100644
index 000000000000..cc2897649cde
--- /dev/null
+++ b/drivers/gpu/drm/rcar-du/rzg2l_du_regs.h
@@ -0,0 +1,64 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * rzg2l_lcdc_regs.h  --  RZ/G2L LCDC Registers Definitions
+ *
+ * Copyright (C) 2022 Renesas Electronics Corporation
+ *
+ */
+
+#ifndef __RZG2L_DU_REGS_H__
+#define __RZG2L_DU_REGS_H__
+
+/* -----------------------------------------------------------------------------
+ * RZ/G2L Display Registers
+ */
+
+#define DU_MCR0			0x00
+#define DU_MCR0_DPI_OE		BIT(0)
+#define DU_MCR0_DI_EN		BIT(8)
+#define DU_MCR0_PB_CLR		BIT(16)
+
+#define DU_MSR0			0x04
+#define DU_MSR0_ST_DI_BSY	BIT(8)
+#define DU_MSR0_ST_PB_WFULL	BIT(16)
+#define DU_MSR0_ST_PB_WINIT	BIT(18)
+#define DU_MSR0_ST_PB_REMPTY	BIT(20)
+#define DU_MSR0_ST_PB_RUF	BIT(21)
+#define DU_MSR0_ST_PB_RINIT	BIT(22)
+
+#define DU_MSR1			0x08
+
+#define DU_IMR0			0x0C
+#define DU_MSR0_IM_PB_RUF	BIT(0)
+
+#define DU_DITR0		0x10
+#define DU_DITR0_DPI_CLKMD	BIT(0)
+#define DU_DITR0_DEMD_LOW	0x0
+#define DU_DITR0_DEMD_HIGH	(BIT(8) | BIT(9))
+#define DU_DITR0_VSPOL		BIT(16)
+#define DU_DITR0_HSPOL		BIT(17)
+
+#define DU_DITR1		0x14
+#define DU_DITR1_VSA(x)		((x) << 0)
+#define DU_DITR1_VACTIVE(x)	((x) << 16)
+
+#define DU_DITR2		0x18
+#define DU_DITR2_VBP(x)		((x) << 0)
+#define DU_DITR2_VFP(x)		((x) << 16)
+
+#define DU_DITR3		0x1C
+#define DU_DITR3_HSA(x)		((x) << 0)
+#define DU_DITR3_HACTIVE(x)	((x) << 16)
+
+#define DU_DITR4		0x20
+#define DU_DITR4_HBP(x)		((x) << 0)
+#define DU_DITR4_HFP(x)		((x) << 16)
+
+#define DU_DITR5		0x24
+#define DU_DITR5_VSFT(x)	((x) << 0)
+#define DU_DITR5_HSFT(x)	((x) << 16)
+
+#define DU_PBCR0		0x4C
+#define DU_PBCR0_PB_DEP(x)	((x) << 0)
+
+#endif /* __RZG2L_DU_REGS_H__ */
-- 
2.17.1

Re: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document r9a07g044l bindings

[Rob Herring]

On Wed, 16 Mar 2022 13:10:54 +0000, Biju Das wrote:
> Extend the Renesas DU display bindings to support the r9a07g044l
> DU module found on RZ/G2L LCDC.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * Updated commit description.
>  * Removed LCDC references
>  * Changed clock name from du.0->aclk
>  * Changed reset name from du.0->du
> RFC->v1:
>  * Changed  minItems->maxItems for renesas,vsps.
> RFC:
>  https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-18-biju.das.jz@bp.renesas.com/
> ---
>  .../bindings/display/renesas,du.yaml          | 54 +++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document r9a07g044l bindings

[Rob Herring]

On Wed, 16 Mar 2022 13:10:54 +0000, Biju Das wrote:
> Extend the Renesas DU display bindings to support the r9a07g044l
> DU module found on RZ/G2L LCDC.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * Updated commit description.
>  * Removed LCDC references
>  * Changed clock name from du.0->aclk
>  * Changed reset name from du.0->du
> RFC->v1:
>  * Changed  minItems->maxItems for renesas,vsps.
> RFC:
>  https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-18-biju.das.jz@bp.renesas.com/
> ---
>  .../bindings/display/renesas,du.yaml          | 54 +++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 

Reviewed-by: Rob Herring <robh@kernel.org>

Re: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document r9a07g044l bindings

[Geert Uytterhoeven]

Hi Biju,

On Wed, Mar 16, 2022 at 2:11 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Extend the Renesas DU display bindings to support the r9a07g044l
> DU module found on RZ/G2L LCDC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/display/renesas,du.yaml
> +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
> @@ -40,6 +40,7 @@ properties:
>        - renesas,du-r8a77990 # for R-Car E3 compatible DU
>        - renesas,du-r8a77995 # for R-Car D3 compatible DU
>        - renesas,du-r8a779a0 # for R-Car V3U compatible DU
> +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU

"renesas,du-r9a07g044"? Both RZ/G2L and RZ/G2LC have an LCDC.
I believe the lack of parallel data support on RZ/G2LC is just a
limitation of the package?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

Re: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document r9a07g044l bindings

[Geert Uytterhoeven]

Hi Biju,

On Wed, Mar 16, 2022 at 2:11 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Extend the Renesas DU display bindings to support the r9a07g044l
> DU module found on RZ/G2L LCDC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>

Thanks for your patch!

> --- a/Documentation/devicetree/bindings/display/renesas,du.yaml
> +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
> @@ -40,6 +40,7 @@ properties:
>        - renesas,du-r8a77990 # for R-Car E3 compatible DU
>        - renesas,du-r8a77995 # for R-Car D3 compatible DU
>        - renesas,du-r8a779a0 # for R-Car V3U compatible DU
> +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU

"renesas,du-r9a07g044"? Both RZ/G2L and RZ/G2LC have an LCDC.
I believe the lack of parallel data support on RZ/G2LC is just a
limitation of the package?

Gr{oetje,eeting}s,

                        Geert

--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org

In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
                                -- Linus Torvalds

RE: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document r9a07g044l bindings

[Biju Das]

Hi Geert,

Thanks for the feedback

> Subject: Re: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document
> r9a07g044l bindings
> 
> Hi Biju,
> 
> On Wed, Mar 16, 2022 at 2:11 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Extend the Renesas DU display bindings to support the r9a07g044l DU
> > module found on RZ/G2L LCDC.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/Documentation/devicetree/bindings/display/renesas,du.yaml
> > +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
> > @@ -40,6 +40,7 @@ properties:
> >        - renesas,du-r8a77990 # for R-Car E3 compatible DU
> >        - renesas,du-r8a77995 # for R-Car D3 compatible DU
> >        - renesas,du-r8a779a0 # for R-Car V3U compatible DU
> > +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
> 
> "renesas,du-r9a07g044"? Both RZ/G2L and RZ/G2LC have an LCDC.
> I believe the lack of parallel data support on RZ/G2LC is just a
> limitation of the package?

From the block diagram 24-bit video data from DU is connected to both DSI and parallel interface.
However, SoC packaging wise RZ/G2LC supports only DSI interface.

RZ/G2L supports both DSI and parallel interface
RZ/G2LC supports only DSI interface

OK, we could use "renesas,du-r9a07g044" as well. 

Regards,
Biju

RE: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document r9a07g044l bindings

[Biju Das]

Hi Geert,

Thanks for the feedback

> Subject: Re: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document
> r9a07g044l bindings
> 
> Hi Biju,
> 
> On Wed, Mar 16, 2022 at 2:11 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Extend the Renesas DU display bindings to support the r9a07g044l DU
> > module found on RZ/G2L LCDC.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> 
> Thanks for your patch!
> 
> > --- a/Documentation/devicetree/bindings/display/renesas,du.yaml
> > +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
> > @@ -40,6 +40,7 @@ properties:
> >        - renesas,du-r8a77990 # for R-Car E3 compatible DU
> >        - renesas,du-r8a77995 # for R-Car D3 compatible DU
> >        - renesas,du-r8a779a0 # for R-Car V3U compatible DU
> > +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
> 
> "renesas,du-r9a07g044"? Both RZ/G2L and RZ/G2LC have an LCDC.
> I believe the lack of parallel data support on RZ/G2LC is just a
> limitation of the package?

From the block diagram 24-bit video data from DU is connected to both DSI and parallel interface.
However, SoC packaging wise RZ/G2LC supports only DSI interface.

RZ/G2L supports both DSI and parallel interface
RZ/G2LC supports only DSI interface

OK, we could use "renesas,du-r9a07g044" as well. 

Regards,
Biju

RE: [PATCH v2 0/7] Add RZ/G2L Display support

[Biju Das]

Hi All,

Gentle ping, Are we happy with this patch series?

Cheers,
Biju

> Subject: [PATCH v2 0/7] Add RZ/G2L Display support
> 
> RZ/G2L LCD controller composed of Frame compression Processor(FCPVD),
> Video signal processor (VSPD) and Display unit(DU). The output of LCDC is
> connected to Display parallel interface and MIPI link video interface.
> 
> This patch series aims to add basic display support on RZ/G2L SMARC EVK
> platform. The output from DSI is connected to ADV7535.
> 
> The DU controller is similar to R-Car as it is connected to VSPD, so
> reusing most of R-Car code with new CRTC driver specific to RZ/G2L
> 
> v1->v2:
>  * Based on [1], all references to 'rzg2l_lcdc' replaced with 'rzg2l_du'
>  * Updated commit description for bindings
>  * Removed LCDC references from bindings
>  * Changed clock name from du.0->aclk from bindings
>  * Changed reset name from du.0->du from bindings
>  * Replaced crtc_helper_funcs->rcar_crtc_helper_funcs
>  * Updated macro DRM_RZG2L_LCDC->DRM_RZG2L_DU
>  * Replaced rzg2l-lcdc-drm->rzg2l-du-drm
>  * Added forward declaration for struct reset_control
> 
> [1]
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220312084205.31462-
> 2-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=3zlHOfdKJ
> XLmDLGaMbbw%2BDUxQreKIEtvGUHNSuukDmg%3D&reserved=0
> 
> RFC->v1:
>  * Changed  minItems->maxItems for renesas,vsps.
>  * Added RZ/G2L LCDC driver with special handling for CRTC reusing
>    most of RCar DU code
>  * Fixed the comments for num_rpf from rpf's->RPFs/ and vsp->VSP.
> RFC:
> 
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220112174612.10773-
> 18-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=SXadiMRg%
> 2Fw%2Fnt3R6K02Zke67CSFqIQtt34si2RCqyH0%3D&reserved=0
> 
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220112174612.10773-
> 12-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=uRkp8himf
> 53knLtbWBxfRa4HGY3SxmyLT5FBrpmFtqg%3D&reserved=0
> 
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220112174612.10773-
> 13-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=MQAEyp28C
> rxHTvdHtarXlO6j0CkpCXZuqVHcbNWkXYI%3D&reserved=0
> 
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220112174612.10773-
> 19-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=1y%2Bd5Yb
> UoXnMZL97%2F4LTcG8IDtze%2FW%2BwzHRXBEbUgSw%3D&reserved=0
> 
> Biju Das (7):
>   dt-bindings: display: renesas,du: Document r9a07g044l bindings
>   drm: rcar-du: Add num_rpf to struct rcar_du_device_info
>   drm: rcar-du: Add max_width and max_height to struct
>     rcar_du_device_info
>   drm: rcar-du: Move rcar_du_output_name() to rcar_du_common.c
>   drm: rcar-du: Factorise rcar_du_{atomic_check,modeset_init}
>   drm: rcar-du: Factorise
>     rcar_du_vsp{complete,enable,plane_atomic_check}
>   drm: rcar-du: Add RZ/G2L DU Support
> 
>  .../bindings/display/renesas,du.yaml          |  54 ++
>  drivers/gpu/drm/rcar-du/Kconfig               |  18 +-
>  drivers/gpu/drm/rcar-du/Makefile              |  13 +
>  drivers/gpu/drm/rcar-du/rcar_du_common.c      |  30 +
>  drivers/gpu/drm/rcar-du/rcar_du_crtc.h        |   8 +
>  drivers/gpu/drm/rcar-du/rcar_du_drv.c         | 100 ++-
>  drivers/gpu/drm/rcar-du/rcar_du_drv.h         |  31 +
>  drivers/gpu/drm/rcar-du/rcar_du_kms.c         |  23 +-
>  drivers/gpu/drm/rcar-du/rcar_du_plane.h       |  12 +
>  drivers/gpu/drm/rcar-du/rcar_du_vsp.c         |  18 +-
>  drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c       | 705 ++++++++++++++++++
>  drivers/gpu/drm/rcar-du/rzg2l_du_drv.c        | 221 ++++++
>  drivers/gpu/drm/rcar-du/rzg2l_du_plane.c      |  82 ++
>  drivers/gpu/drm/rcar-du/rzg2l_du_regs.h       |  64 ++
>  14 files changed, 1334 insertions(+), 45 deletions(-)  create mode 100644
> drivers/gpu/drm/rcar-du/rcar_du_common.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_plane.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h
> 
> --
> 2.17.1

RE: [PATCH v2 0/7] Add RZ/G2L Display support

[Biju Das]

Hi All,

Gentle ping, Are we happy with this patch series?

Cheers,
Biju

> Subject: [PATCH v2 0/7] Add RZ/G2L Display support
> 
> RZ/G2L LCD controller composed of Frame compression Processor(FCPVD),
> Video signal processor (VSPD) and Display unit(DU). The output of LCDC is
> connected to Display parallel interface and MIPI link video interface.
> 
> This patch series aims to add basic display support on RZ/G2L SMARC EVK
> platform. The output from DSI is connected to ADV7535.
> 
> The DU controller is similar to R-Car as it is connected to VSPD, so
> reusing most of R-Car code with new CRTC driver specific to RZ/G2L
> 
> v1->v2:
>  * Based on [1], all references to 'rzg2l_lcdc' replaced with 'rzg2l_du'
>  * Updated commit description for bindings
>  * Removed LCDC references from bindings
>  * Changed clock name from du.0->aclk from bindings
>  * Changed reset name from du.0->du from bindings
>  * Replaced crtc_helper_funcs->rcar_crtc_helper_funcs
>  * Updated macro DRM_RZG2L_LCDC->DRM_RZG2L_DU
>  * Replaced rzg2l-lcdc-drm->rzg2l-du-drm
>  * Added forward declaration for struct reset_control
> 
> [1]
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220312084205.31462-
> 2-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=3zlHOfdKJ
> XLmDLGaMbbw%2BDUxQreKIEtvGUHNSuukDmg%3D&reserved=0
> 
> RFC->v1:
>  * Changed  minItems->maxItems for renesas,vsps.
>  * Added RZ/G2L LCDC driver with special handling for CRTC reusing
>    most of RCar DU code
>  * Fixed the comments for num_rpf from rpf's->RPFs/ and vsp->VSP.
> RFC:
> 
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220112174612.10773-
> 18-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=SXadiMRg%
> 2Fw%2Fnt3R6K02Zke67CSFqIQtt34si2RCqyH0%3D&reserved=0
> 
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220112174612.10773-
> 12-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=uRkp8himf
> 53knLtbWBxfRa4HGY3SxmyLT5FBrpmFtqg%3D&reserved=0
> 
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220112174612.10773-
> 13-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=MQAEyp28C
> rxHTvdHtarXlO6j0CkpCXZuqVHcbNWkXYI%3D&reserved=0
> 
> https://jpn01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fpatchwor
> k.kernel.org%2Fproject%2Flinux-renesas-soc%2Fpatch%2F20220112174612.10773-
> 19-
> biju.das.jz%40bp.renesas.com%2F&data=04%7C01%7Cbiju.das.jz%40bp.renesa
> s.com%7C619fcf75486d47a9954408da074e6e1b%7C53d82571da1947e49cb4625a166a4a2
> a%7C0%7C0%7C637830330678043182%7CUnknown%7CTWFpbGZsb3d8eyJWIjoiMC4wLjAwMDA
> iLCJQIjoiV2luMzIiLCJBTiI6Ik1haWwiLCJXVCI6Mn0%3D%7C3000&sdata=1y%2Bd5Yb
> UoXnMZL97%2F4LTcG8IDtze%2FW%2BwzHRXBEbUgSw%3D&reserved=0
> 
> Biju Das (7):
>   dt-bindings: display: renesas,du: Document r9a07g044l bindings
>   drm: rcar-du: Add num_rpf to struct rcar_du_device_info
>   drm: rcar-du: Add max_width and max_height to struct
>     rcar_du_device_info
>   drm: rcar-du: Move rcar_du_output_name() to rcar_du_common.c
>   drm: rcar-du: Factorise rcar_du_{atomic_check,modeset_init}
>   drm: rcar-du: Factorise
>     rcar_du_vsp{complete,enable,plane_atomic_check}
>   drm: rcar-du: Add RZ/G2L DU Support
> 
>  .../bindings/display/renesas,du.yaml          |  54 ++
>  drivers/gpu/drm/rcar-du/Kconfig               |  18 +-
>  drivers/gpu/drm/rcar-du/Makefile              |  13 +
>  drivers/gpu/drm/rcar-du/rcar_du_common.c      |  30 +
>  drivers/gpu/drm/rcar-du/rcar_du_crtc.h        |   8 +
>  drivers/gpu/drm/rcar-du/rcar_du_drv.c         | 100 ++-
>  drivers/gpu/drm/rcar-du/rcar_du_drv.h         |  31 +
>  drivers/gpu/drm/rcar-du/rcar_du_kms.c         |  23 +-
>  drivers/gpu/drm/rcar-du/rcar_du_plane.h       |  12 +
>  drivers/gpu/drm/rcar-du/rcar_du_vsp.c         |  18 +-
>  drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c       | 705 ++++++++++++++++++
>  drivers/gpu/drm/rcar-du/rzg2l_du_drv.c        | 221 ++++++
>  drivers/gpu/drm/rcar-du/rzg2l_du_plane.c      |  82 ++
>  drivers/gpu/drm/rcar-du/rzg2l_du_regs.h       |  64 ++
>  14 files changed, 1334 insertions(+), 45 deletions(-)  create mode 100644
> drivers/gpu/drm/rcar-du/rcar_du_common.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_crtc.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_drv.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_plane.c
>  create mode 100644 drivers/gpu/drm/rcar-du/rzg2l_du_regs.h
> 
> --
> 2.17.1

Re: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document r9a07g044l bindings

[Laurent Pinchart]

Hi Biju,

Thank you for the patch.

On Wed, Mar 16, 2022 at 01:10:54PM +0000, Biju Das wrote:
> Extend the Renesas DU display bindings to support the r9a07g044l
> DU module found on RZ/G2L LCDC.

Stupid question, but as this DU and the R-Car DU are completely
different pieces of hardware, wouldn't a separate bindings file make
sense ?

The DT description in this patch looks good to me.

> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * Updated commit description.
>  * Removed LCDC references
>  * Changed clock name from du.0->aclk
>  * Changed reset name from du.0->du
> RFC->v1:
>  * Changed  minItems->maxItems for renesas,vsps.
> RFC:
>  https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-18-biju.das.jz@bp.renesas.com/
> ---
>  .../bindings/display/renesas,du.yaml          | 54 +++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml
> index 13efea574584..f560608bf4e8 100644
> --- a/Documentation/devicetree/bindings/display/renesas,du.yaml
> +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
> @@ -40,6 +40,7 @@ properties:
>        - renesas,du-r8a77990 # for R-Car E3 compatible DU
>        - renesas,du-r8a77995 # for R-Car D3 compatible DU
>        - renesas,du-r8a779a0 # for R-Car V3U compatible DU
> +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
>  
>    reg:
>      maxItems: 1
> @@ -824,6 +825,59 @@ allOf:
>          - reset-names
>          - renesas,vsps
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - renesas,du-r9a07g044l
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: Main clock
> +            - description: Register access clock
> +            - description: Video clock
> +
> +        clock-names:
> +          items:
> +            - const: aclk
> +            - const: pclk
> +            - const: vclk
> +
> +        interrupts:
> +          maxItems: 1
> +
> +        resets:
> +          maxItems: 1
> +
> +        reset-names:
> +          items:
> +            - const: du
> +
> +        ports:
> +          properties:
> +            port@0:
> +              description: DPAD 0
> +            port@1:
> +              description: DSI 0
> +            port@2: false
> +            port@3: false
> +
> +          required:
> +            - port@0
> +            - port@1
> +
> +        renesas,vsps:
> +          maxItems: 1
> +
> +      required:
> +        - clock-names
> +        - interrupts
> +        - resets
> +        - reset-names
> +        - renesas,vsps
> +
>  additionalProperties: false
>  
>  examples:

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document r9a07g044l bindings

[Laurent Pinchart]

Hi Biju,

Thank you for the patch.

On Wed, Mar 16, 2022 at 01:10:54PM +0000, Biju Das wrote:
> Extend the Renesas DU display bindings to support the r9a07g044l
> DU module found on RZ/G2L LCDC.

Stupid question, but as this DU and the R-Car DU are completely
different pieces of hardware, wouldn't a separate bindings file make
sense ?

The DT description in this patch looks good to me.

> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * Updated commit description.
>  * Removed LCDC references
>  * Changed clock name from du.0->aclk
>  * Changed reset name from du.0->du
> RFC->v1:
>  * Changed  minItems->maxItems for renesas,vsps.
> RFC:
>  https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-18-biju.das.jz@bp.renesas.com/
> ---
>  .../bindings/display/renesas,du.yaml          | 54 +++++++++++++++++++
>  1 file changed, 54 insertions(+)
> 
> diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml b/Documentation/devicetree/bindings/display/renesas,du.yaml
> index 13efea574584..f560608bf4e8 100644
> --- a/Documentation/devicetree/bindings/display/renesas,du.yaml
> +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
> @@ -40,6 +40,7 @@ properties:
>        - renesas,du-r8a77990 # for R-Car E3 compatible DU
>        - renesas,du-r8a77995 # for R-Car D3 compatible DU
>        - renesas,du-r8a779a0 # for R-Car V3U compatible DU
> +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
>  
>    reg:
>      maxItems: 1
> @@ -824,6 +825,59 @@ allOf:
>          - reset-names
>          - renesas,vsps
>  
> +  - if:
> +      properties:
> +        compatible:
> +          contains:
> +            enum:
> +              - renesas,du-r9a07g044l
> +    then:
> +      properties:
> +        clocks:
> +          items:
> +            - description: Main clock
> +            - description: Register access clock
> +            - description: Video clock
> +
> +        clock-names:
> +          items:
> +            - const: aclk
> +            - const: pclk
> +            - const: vclk
> +
> +        interrupts:
> +          maxItems: 1
> +
> +        resets:
> +          maxItems: 1
> +
> +        reset-names:
> +          items:
> +            - const: du
> +
> +        ports:
> +          properties:
> +            port@0:
> +              description: DPAD 0
> +            port@1:
> +              description: DSI 0
> +            port@2: false
> +            port@3: false
> +
> +          required:
> +            - port@0
> +            - port@1
> +
> +        renesas,vsps:
> +          maxItems: 1
> +
> +      required:
> +        - clock-names
> +        - interrupts
> +        - resets
> +        - reset-names
> +        - renesas,vsps
> +
>  additionalProperties: false
>  
>  examples:

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 2/7] drm: rcar-du: Add num_rpf to struct rcar_du_device_info

[Laurent Pinchart]

Hi Biju,

Thank you for the patch.

On Wed, Mar 16, 2022 at 01:10:55PM +0000, Biju Das wrote:
> Number of RPF's VSP is different on R-Car and RZ/G2L
>  R-Car Gen3 -> 5 RPFs
>  R-Car Gen2 -> 4 RPFs
>  RZ/G2L -> 2 RPFs
> 
> Add num_rpf to struct rcar_du_device_info to support later
> SoC without any code changes.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * No change
> RFC->v1:
>  * Fixed the comment for num_rpf s/rpf's/RPFs/ and s/vsp/VSP/
> RFC:
>  * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-12-biju.das.jz@bp.renesas.com/
> ---
>  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 17 +++++++++++++++++
>  drivers/gpu/drm/rcar-du/rcar_du_drv.h |  2 ++
>  drivers/gpu/drm/rcar-du/rcar_du_vsp.c |  6 +-----
>  3 files changed, 20 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> index 957ea97541d5..1bc7325aa356 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> @@ -55,6 +55,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 4,
>  };
>  
>  static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
> @@ -77,6 +78,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
>  			.port = 1,
>  		},
>  	},
> +	.num_rpf = 4,
>  };
>  
>  static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
> @@ -104,6 +106,7 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
>  			.port = 2,
>  		},
>  	},
> +	.num_rpf = 4,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
> @@ -133,6 +136,7 @@ static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 5,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -163,6 +167,7 @@ static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 5,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -190,6 +195,7 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
>  		},
>  	},
>  	.num_lvds = 2,
> +	.num_rpf = 4,
>  	.lvds_clk_mask =  BIT(1) | BIT(0),
>  };
>  
> @@ -220,6 +226,7 @@ static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 5,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -272,6 +279,7 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
>  		},
>  	},
>  	.num_lvds = 2,
> +	.num_rpf = 4,
>  };
>  
>  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
> @@ -297,6 +305,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 4,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7792_info = {
> @@ -317,6 +326,7 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
>  			.port = 1,
>  		},
>  	},
> +	.num_rpf = 4,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7794_info = {
> @@ -340,6 +350,7 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
>  			.port = 1,
>  		},
>  	},
> +	.num_rpf = 4,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7795_info = {
> @@ -373,6 +384,7 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 5,
>  	.dpll_mask =  BIT(2) | BIT(1),
>  };
>  
> @@ -403,6 +415,7 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 5,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -433,6 +446,7 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 5,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -459,6 +473,7 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 5,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
> @@ -486,6 +501,7 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
>  		},
>  	},
>  	.num_lvds = 2,
> +	.num_rpf = 5,
>  	.lvds_clk_mask =  BIT(1) | BIT(0),
>  };
>  
> @@ -505,6 +521,7 @@ static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
>  			.port = 1,
>  		},
>  	},
> +	.num_rpf = 5,
>  	.dsi_clk_mask =  BIT(1) | BIT(0),
>  };
>  
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> index 101f42df86ea..68c5de59d18d 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> @@ -69,6 +69,7 @@ struct rcar_du_output_routing {
>   * @channels_mask: bit mask of available DU channels
>   * @routes: array of CRTC to output routes, indexed by output (RCAR_DU_OUTPUT_*)
>   * @num_lvds: number of internal LVDS encoders
> + * @num_rpf: max number of RPFs in VSP

s/max //

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

>   * @dpll_mask: bit mask of DU channels equipped with a DPLL
>   * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot clock
>   * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
> @@ -80,6 +81,7 @@ struct rcar_du_device_info {
>  	unsigned int channels_mask;
>  	struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
>  	unsigned int num_lvds;
> +	unsigned int num_rpf;
>  	unsigned int dpll_mask;
>  	unsigned int dsi_clk_mask;
>  	unsigned int lvds_clk_mask;
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> index b7fc5b069cbc..cf045a203aa5 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> @@ -415,11 +415,7 @@ int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
>  	if (ret < 0)
>  		return ret;
>  
> -	 /*
> -	  * The VSP2D (Gen3) has 5 RPFs, but the VSP1D (Gen2) is limited to
> -	  * 4 RPFs.
> -	  */
> -	num_planes = rcdu->info->gen >= 3 ? 5 : 4;
> +	num_planes = rcdu->info->num_rpf;
>  
>  	vsp->planes = kcalloc(num_planes, sizeof(*vsp->planes), GFP_KERNEL);
>  	if (!vsp->planes)

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 2/7] drm: rcar-du: Add num_rpf to struct rcar_du_device_info

[Laurent Pinchart]

Hi Biju,

Thank you for the patch.

On Wed, Mar 16, 2022 at 01:10:55PM +0000, Biju Das wrote:
> Number of RPF's VSP is different on R-Car and RZ/G2L
>  R-Car Gen3 -> 5 RPFs
>  R-Car Gen2 -> 4 RPFs
>  RZ/G2L -> 2 RPFs
> 
> Add num_rpf to struct rcar_du_device_info to support later
> SoC without any code changes.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * No change
> RFC->v1:
>  * Fixed the comment for num_rpf s/rpf's/RPFs/ and s/vsp/VSP/
> RFC:
>  * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-12-biju.das.jz@bp.renesas.com/
> ---
>  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 17 +++++++++++++++++
>  drivers/gpu/drm/rcar-du/rcar_du_drv.h |  2 ++
>  drivers/gpu/drm/rcar-du/rcar_du_vsp.c |  6 +-----
>  3 files changed, 20 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> index 957ea97541d5..1bc7325aa356 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> @@ -55,6 +55,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 4,
>  };
>  
>  static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
> @@ -77,6 +78,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
>  			.port = 1,
>  		},
>  	},
> +	.num_rpf = 4,
>  };
>  
>  static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
> @@ -104,6 +106,7 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
>  			.port = 2,
>  		},
>  	},
> +	.num_rpf = 4,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
> @@ -133,6 +136,7 @@ static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 5,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -163,6 +167,7 @@ static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 5,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -190,6 +195,7 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
>  		},
>  	},
>  	.num_lvds = 2,
> +	.num_rpf = 4,
>  	.lvds_clk_mask =  BIT(1) | BIT(0),
>  };
>  
> @@ -220,6 +226,7 @@ static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 5,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -272,6 +279,7 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
>  		},
>  	},
>  	.num_lvds = 2,
> +	.num_rpf = 4,
>  };
>  
>  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
> @@ -297,6 +305,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 4,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7792_info = {
> @@ -317,6 +326,7 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
>  			.port = 1,
>  		},
>  	},
> +	.num_rpf = 4,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7794_info = {
> @@ -340,6 +350,7 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
>  			.port = 1,
>  		},
>  	},
> +	.num_rpf = 4,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7795_info = {
> @@ -373,6 +384,7 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 5,
>  	.dpll_mask =  BIT(2) | BIT(1),
>  };
>  
> @@ -403,6 +415,7 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 5,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -433,6 +446,7 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 5,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -459,6 +473,7 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
>  		},
>  	},
>  	.num_lvds = 1,
> +	.num_rpf = 5,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
> @@ -486,6 +501,7 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
>  		},
>  	},
>  	.num_lvds = 2,
> +	.num_rpf = 5,
>  	.lvds_clk_mask =  BIT(1) | BIT(0),
>  };
>  
> @@ -505,6 +521,7 @@ static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
>  			.port = 1,
>  		},
>  	},
> +	.num_rpf = 5,
>  	.dsi_clk_mask =  BIT(1) | BIT(0),
>  };
>  
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> index 101f42df86ea..68c5de59d18d 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> @@ -69,6 +69,7 @@ struct rcar_du_output_routing {
>   * @channels_mask: bit mask of available DU channels
>   * @routes: array of CRTC to output routes, indexed by output (RCAR_DU_OUTPUT_*)
>   * @num_lvds: number of internal LVDS encoders
> + * @num_rpf: max number of RPFs in VSP

s/max //

Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>

>   * @dpll_mask: bit mask of DU channels equipped with a DPLL
>   * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot clock
>   * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
> @@ -80,6 +81,7 @@ struct rcar_du_device_info {
>  	unsigned int channels_mask;
>  	struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
>  	unsigned int num_lvds;
> +	unsigned int num_rpf;
>  	unsigned int dpll_mask;
>  	unsigned int dsi_clk_mask;
>  	unsigned int lvds_clk_mask;
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> index b7fc5b069cbc..cf045a203aa5 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> @@ -415,11 +415,7 @@ int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct device_node *np,
>  	if (ret < 0)
>  		return ret;
>  
> -	 /*
> -	  * The VSP2D (Gen3) has 5 RPFs, but the VSP1D (Gen2) is limited to
> -	  * 4 RPFs.
> -	  */
> -	num_planes = rcdu->info->gen >= 3 ? 5 : 4;
> +	num_planes = rcdu->info->num_rpf;
>  
>  	vsp->planes = kcalloc(num_planes, sizeof(*vsp->planes), GFP_KERNEL);
>  	if (!vsp->planes)

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 3/7] drm: rcar-du: Add max_width and max_height to struct rcar_du_device_info

[Laurent Pinchart]

Hi Biju,

Thank you for the patch.

On Wed, Mar 16, 2022 at 01:10:56PM +0000, Biju Das wrote:
> There are some differences related to max frame size supported by different
> R-Car/RZ-G family of SoC's
> 
> Max frame size supported by R-Car Gen1 & R-Car Gen2 is 4095x2047
> Max frame size supported by R-Car Gen3 is 8190x8190
> Max frame size supported by RZ/G2L is 1920x1080
> 
> Add max_width and max_height to struct rcar_du_device_info to support later
> SoC without any code changes.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * No Change
> RFC->V1:
>  * No Change
> RFC:
>  * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-13-biju.das.jz@bp.renesas.com/
> ---
>  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 36 +++++++++++++++++++++++++++
>  drivers/gpu/drm/rcar-du/rcar_du_drv.h |  4 +++
>  drivers/gpu/drm/rcar-du/rcar_du_kms.c | 17 +++++--------
>  3 files changed, 46 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> index 1bc7325aa356..4640c356a532 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> @@ -56,6 +56,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 4,
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
> @@ -79,6 +81,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
>  		},
>  	},
>  	.num_rpf = 4,
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
> @@ -107,6 +111,8 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
>  		},
>  	},
>  	.num_rpf = 4,
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
> @@ -137,6 +143,8 @@ static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -168,6 +176,8 @@ static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -196,6 +206,8 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
>  	},
>  	.num_lvds = 2,
>  	.num_rpf = 4,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.lvds_clk_mask =  BIT(1) | BIT(0),
>  };
>  
> @@ -227,6 +239,8 @@ static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -249,6 +263,8 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
>  			.port = 1,
>  		},
>  	},
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7790_info = {
> @@ -280,6 +296,8 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
>  	},
>  	.num_lvds = 2,
>  	.num_rpf = 4,
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
> @@ -306,6 +324,8 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 4,
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7792_info = {
> @@ -327,6 +347,8 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
>  		},
>  	},
>  	.num_rpf = 4,
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7794_info = {
> @@ -351,6 +373,8 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
>  		},
>  	},
>  	.num_rpf = 4,
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7795_info = {
> @@ -385,6 +409,8 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.dpll_mask =  BIT(2) | BIT(1),
>  };
>  
> @@ -416,6 +442,8 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -447,6 +475,8 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -474,6 +504,8 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
> @@ -502,6 +534,8 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
>  	},
>  	.num_lvds = 2,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.lvds_clk_mask =  BIT(1) | BIT(0),
>  };
>  
> @@ -522,6 +556,8 @@ static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
>  		},
>  	},
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.dsi_clk_mask =  BIT(1) | BIT(0),
>  };
>  
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> index 68c5de59d18d..b0553b43363b 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> @@ -70,6 +70,8 @@ struct rcar_du_output_routing {
>   * @routes: array of CRTC to output routes, indexed by output (RCAR_DU_OUTPUT_*)
>   * @num_lvds: number of internal LVDS encoders
>   * @num_rpf: max number of RPFs in VSP
> + * @max_width: max frame width
> + * @max_height: max frame height
>   * @dpll_mask: bit mask of DU channels equipped with a DPLL
>   * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot clock
>   * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
> @@ -82,6 +84,8 @@ struct rcar_du_device_info {
>  	struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
>  	unsigned int num_lvds;
>  	unsigned int num_rpf;
> +	unsigned int max_width;
> +	unsigned int max_height;
>  	unsigned int dpll_mask;
>  	unsigned int dsi_clk_mask;
>  	unsigned int lvds_clk_mask;
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> index 190dbb7f15dd..5857705aac20 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> @@ -834,17 +834,12 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
>  	dev->mode_config.funcs = &rcar_du_mode_config_funcs;
>  	dev->mode_config.helper_private = &rcar_du_mode_config_helper;
>  
> -	if (rcdu->info->gen < 3) {
> -		dev->mode_config.max_width = 4095;
> -		dev->mode_config.max_height = 2047;
> -	} else {
> -		/*
> -		 * The Gen3 DU uses the VSP1 for memory access, and is limited
> -		 * to frame sizes of 8190x8190.
> -		 */
> -		dev->mode_config.max_width = 8190;
> -		dev->mode_config.max_height = 8190;
> -	}
> +	/*
> +	 * The Gen3 DU uses the VSP1 for memory access, and is limited
> +	 * to frame sizes of 8190x8190.
> +	 */

This comment doesn't make much sense here anymore, but I think it's
useful to keep the information. How about defining macros for the
maximum width and height on different platforms, and moving the comment
just before the macro definitions ?

> +	dev->mode_config.max_width = rcdu->info->max_width;
> +	dev->mode_config.max_height = rcdu->info->max_height;
>  
>  	rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
>  

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 3/7] drm: rcar-du: Add max_width and max_height to struct rcar_du_device_info

[Laurent Pinchart]

Hi Biju,

Thank you for the patch.

On Wed, Mar 16, 2022 at 01:10:56PM +0000, Biju Das wrote:
> There are some differences related to max frame size supported by different
> R-Car/RZ-G family of SoC's
> 
> Max frame size supported by R-Car Gen1 & R-Car Gen2 is 4095x2047
> Max frame size supported by R-Car Gen3 is 8190x8190
> Max frame size supported by RZ/G2L is 1920x1080
> 
> Add max_width and max_height to struct rcar_du_device_info to support later
> SoC without any code changes.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * No Change
> RFC->V1:
>  * No Change
> RFC:
>  * https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-13-biju.das.jz@bp.renesas.com/
> ---
>  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 36 +++++++++++++++++++++++++++
>  drivers/gpu/drm/rcar-du/rcar_du_drv.h |  4 +++
>  drivers/gpu/drm/rcar-du/rcar_du_kms.c | 17 +++++--------
>  3 files changed, 46 insertions(+), 11 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> index 1bc7325aa356..4640c356a532 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> @@ -56,6 +56,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 4,
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
> @@ -79,6 +81,8 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
>  		},
>  	},
>  	.num_rpf = 4,
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
> @@ -107,6 +111,8 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
>  		},
>  	},
>  	.num_rpf = 4,
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
> @@ -137,6 +143,8 @@ static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -168,6 +176,8 @@ static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -196,6 +206,8 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
>  	},
>  	.num_lvds = 2,
>  	.num_rpf = 4,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.lvds_clk_mask =  BIT(1) | BIT(0),
>  };
>  
> @@ -227,6 +239,8 @@ static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -249,6 +263,8 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
>  			.port = 1,
>  		},
>  	},
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7790_info = {
> @@ -280,6 +296,8 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
>  	},
>  	.num_lvds = 2,
>  	.num_rpf = 4,
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
> @@ -306,6 +324,8 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 4,
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7792_info = {
> @@ -327,6 +347,8 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
>  		},
>  	},
>  	.num_rpf = 4,
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7794_info = {
> @@ -351,6 +373,8 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
>  		},
>  	},
>  	.num_rpf = 4,
> +	.max_width = 4095,
> +	.max_height = 2047,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7795_info = {
> @@ -385,6 +409,8 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.dpll_mask =  BIT(2) | BIT(1),
>  };
>  
> @@ -416,6 +442,8 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -447,6 +475,8 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
>  };
>  
> @@ -474,6 +504,8 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
>  	},
>  	.num_lvds = 1,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
> @@ -502,6 +534,8 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
>  	},
>  	.num_lvds = 2,
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.lvds_clk_mask =  BIT(1) | BIT(0),
>  };
>  
> @@ -522,6 +556,8 @@ static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
>  		},
>  	},
>  	.num_rpf = 5,
> +	.max_width = 8190,
> +	.max_height = 8190,
>  	.dsi_clk_mask =  BIT(1) | BIT(0),
>  };
>  
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> index 68c5de59d18d..b0553b43363b 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> @@ -70,6 +70,8 @@ struct rcar_du_output_routing {
>   * @routes: array of CRTC to output routes, indexed by output (RCAR_DU_OUTPUT_*)
>   * @num_lvds: number of internal LVDS encoders
>   * @num_rpf: max number of RPFs in VSP
> + * @max_width: max frame width
> + * @max_height: max frame height
>   * @dpll_mask: bit mask of DU channels equipped with a DPLL
>   * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot clock
>   * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
> @@ -82,6 +84,8 @@ struct rcar_du_device_info {
>  	struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
>  	unsigned int num_lvds;
>  	unsigned int num_rpf;
> +	unsigned int max_width;
> +	unsigned int max_height;
>  	unsigned int dpll_mask;
>  	unsigned int dsi_clk_mask;
>  	unsigned int lvds_clk_mask;
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> index 190dbb7f15dd..5857705aac20 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> @@ -834,17 +834,12 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
>  	dev->mode_config.funcs = &rcar_du_mode_config_funcs;
>  	dev->mode_config.helper_private = &rcar_du_mode_config_helper;
>  
> -	if (rcdu->info->gen < 3) {
> -		dev->mode_config.max_width = 4095;
> -		dev->mode_config.max_height = 2047;
> -	} else {
> -		/*
> -		 * The Gen3 DU uses the VSP1 for memory access, and is limited
> -		 * to frame sizes of 8190x8190.
> -		 */
> -		dev->mode_config.max_width = 8190;
> -		dev->mode_config.max_height = 8190;
> -	}
> +	/*
> +	 * The Gen3 DU uses the VSP1 for memory access, and is limited
> +	 * to frame sizes of 8190x8190.
> +	 */

This comment doesn't make much sense here anymore, but I think it's
useful to keep the information. How about defining macros for the
maximum width and height on different platforms, and moving the comment
just before the macro definitions ?

> +	dev->mode_config.max_width = rcdu->info->max_width;
> +	dev->mode_config.max_height = rcdu->info->max_height;
>  
>  	rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
>  

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 4/7] drm: rcar-du: Move rcar_du_output_name() to rcar_du_common.c

[Laurent Pinchart]

Hi Biju,

Thank you for the patch.

On Wed, Mar 16, 2022 at 01:10:57PM +0000, Biju Das wrote:
> RZ/G2L SoC's does not have group/plane registers compared to RCar, hence it
> needs a different CRTC implementation.
> 
> Move rcar_du_output_name() to a new common file rcar_du_common.c, So that
> the same function can be reused by RZ/G2L SoC later.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * No change
> RFC->v1:
>  New patch
> ---
>  drivers/gpu/drm/rcar-du/Makefile         |  1 +
>  drivers/gpu/drm/rcar-du/rcar_du_common.c | 30 ++++++++++++++++++++++++
>  drivers/gpu/drm/rcar-du/rcar_du_drv.c    | 20 ----------------
>  3 files changed, 31 insertions(+), 20 deletions(-)
>  create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_common.c
> 
> diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
> index e7275b5e7ec8..331e12d65a6b 100644
> --- a/drivers/gpu/drm/rcar-du/Makefile
> +++ b/drivers/gpu/drm/rcar-du/Makefile
> @@ -1,5 +1,6 @@
>  # SPDX-License-Identifier: GPL-2.0
>  rcar-du-drm-y := rcar_du_crtc.o \
> +		 rcar_du_common.o \
>  		 rcar_du_drv.o \
>  		 rcar_du_encoder.o \
>  		 rcar_du_group.o \
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_common.c b/drivers/gpu/drm/rcar-du/rcar_du_common.c
> new file mode 100644
> index 000000000000..f9f9908cda6d
> --- /dev/null
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_common.c
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * rcar_du_common.c  --  R-Car Display Unit Common
> + *
> + * Copyright (C) 2013-2022 Renesas Electronics Corporation
> + *
> + * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
> + */
> +
> +#include "rcar_du_drv.h"
> +
> +const char *rcar_du_output_name(enum rcar_du_output output)
> +{
> +	static const char * const names[] = {
> +		[RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
> +		[RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
> +		[RCAR_DU_OUTPUT_DSI0] = "DSI0",
> +		[RCAR_DU_OUTPUT_DSI1] = "DSI1",
> +		[RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
> +		[RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
> +		[RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
> +		[RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
> +		[RCAR_DU_OUTPUT_TCON] = "TCON",
> +	};
> +
> +	if (output >= ARRAY_SIZE(names) || !names[output])
> +		return "UNKNOWN";
> +
> +	return names[output];
> +}

As we have nothing else than this function in this file, how about
moving it to rcar_du_drv.c instead, to avoid adding a new file ?

You also need to add a declaration for rcar_du_output_name() in the
appropriate header.

> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> index 4640c356a532..f6e234dafb72 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> @@ -591,26 +591,6 @@ static const struct of_device_id rcar_du_of_table[] = {
>  
>  MODULE_DEVICE_TABLE(of, rcar_du_of_table);
>  
> -const char *rcar_du_output_name(enum rcar_du_output output)
> -{
> -	static const char * const names[] = {
> -		[RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
> -		[RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
> -		[RCAR_DU_OUTPUT_DSI0] = "DSI0",
> -		[RCAR_DU_OUTPUT_DSI1] = "DSI1",
> -		[RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
> -		[RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
> -		[RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
> -		[RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
> -		[RCAR_DU_OUTPUT_TCON] = "TCON",
> -	};
> -
> -	if (output >= ARRAY_SIZE(names) || !names[output])
> -		return "UNKNOWN";
> -
> -	return names[output];
> -}
> -
>  /* -----------------------------------------------------------------------------
>   * DRM operations
>   */

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 4/7] drm: rcar-du: Move rcar_du_output_name() to rcar_du_common.c

[Laurent Pinchart]

Hi Biju,

Thank you for the patch.

On Wed, Mar 16, 2022 at 01:10:57PM +0000, Biju Das wrote:
> RZ/G2L SoC's does not have group/plane registers compared to RCar, hence it
> needs a different CRTC implementation.
> 
> Move rcar_du_output_name() to a new common file rcar_du_common.c, So that
> the same function can be reused by RZ/G2L SoC later.
> 
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * No change
> RFC->v1:
>  New patch
> ---
>  drivers/gpu/drm/rcar-du/Makefile         |  1 +
>  drivers/gpu/drm/rcar-du/rcar_du_common.c | 30 ++++++++++++++++++++++++
>  drivers/gpu/drm/rcar-du/rcar_du_drv.c    | 20 ----------------
>  3 files changed, 31 insertions(+), 20 deletions(-)
>  create mode 100644 drivers/gpu/drm/rcar-du/rcar_du_common.c
> 
> diff --git a/drivers/gpu/drm/rcar-du/Makefile b/drivers/gpu/drm/rcar-du/Makefile
> index e7275b5e7ec8..331e12d65a6b 100644
> --- a/drivers/gpu/drm/rcar-du/Makefile
> +++ b/drivers/gpu/drm/rcar-du/Makefile
> @@ -1,5 +1,6 @@
>  # SPDX-License-Identifier: GPL-2.0
>  rcar-du-drm-y := rcar_du_crtc.o \
> +		 rcar_du_common.o \
>  		 rcar_du_drv.o \
>  		 rcar_du_encoder.o \
>  		 rcar_du_group.o \
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_common.c b/drivers/gpu/drm/rcar-du/rcar_du_common.c
> new file mode 100644
> index 000000000000..f9f9908cda6d
> --- /dev/null
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_common.c
> @@ -0,0 +1,30 @@
> +// SPDX-License-Identifier: GPL-2.0+
> +/*
> + * rcar_du_common.c  --  R-Car Display Unit Common
> + *
> + * Copyright (C) 2013-2022 Renesas Electronics Corporation
> + *
> + * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
> + */
> +
> +#include "rcar_du_drv.h"
> +
> +const char *rcar_du_output_name(enum rcar_du_output output)
> +{
> +	static const char * const names[] = {
> +		[RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
> +		[RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
> +		[RCAR_DU_OUTPUT_DSI0] = "DSI0",
> +		[RCAR_DU_OUTPUT_DSI1] = "DSI1",
> +		[RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
> +		[RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
> +		[RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
> +		[RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
> +		[RCAR_DU_OUTPUT_TCON] = "TCON",
> +	};
> +
> +	if (output >= ARRAY_SIZE(names) || !names[output])
> +		return "UNKNOWN";
> +
> +	return names[output];
> +}

As we have nothing else than this function in this file, how about
moving it to rcar_du_drv.c instead, to avoid adding a new file ?

You also need to add a declaration for rcar_du_output_name() in the
appropriate header.

> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> index 4640c356a532..f6e234dafb72 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> @@ -591,26 +591,6 @@ static const struct of_device_id rcar_du_of_table[] = {
>  
>  MODULE_DEVICE_TABLE(of, rcar_du_of_table);
>  
> -const char *rcar_du_output_name(enum rcar_du_output output)
> -{
> -	static const char * const names[] = {
> -		[RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
> -		[RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
> -		[RCAR_DU_OUTPUT_DSI0] = "DSI0",
> -		[RCAR_DU_OUTPUT_DSI1] = "DSI1",
> -		[RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
> -		[RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
> -		[RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
> -		[RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
> -		[RCAR_DU_OUTPUT_TCON] = "TCON",
> -	};
> -
> -	if (output >= ARRAY_SIZE(names) || !names[output])
> -		return "UNKNOWN";
> -
> -	return names[output];
> -}
> -
>  /* -----------------------------------------------------------------------------
>   * DRM operations
>   */

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 5/7] drm: rcar-du: Factorise rcar_du_{atomic_check,modeset_init}

[Laurent Pinchart]

Hi Biju,

Thank you for the patch.

On Wed, Mar 16, 2022 at 01:10:58PM +0000, Biju Das wrote:
> RZ/G2L SoC's does not have group/plane registers compared to RCar, hence it
> needs a different CRTC implementation. Factorise rcar_du_{atomic_check,
> modeset_init} by adding struct rcar_du_crtc_helper_funcs to struct
> rcar_du_device_info, so that it can support RZ/G2L SoC without any code
> changes.

I'd like to go the other way around. Instead of adding a layer of
indirection in the DU driver, could you create a new DRM driver, and
share common code with the DU driver ?

> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * Changed crtc_helper_funcs->rcar_crtc_helper_funcs
> RFC->v1:
>  * New patch
> ---
>  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 24 ++++++++++++++++++++++++
>  drivers/gpu/drm/rcar-du/rcar_du_drv.h | 16 ++++++++++++++++
>  drivers/gpu/drm/rcar-du/rcar_du_kms.c |  6 +++---
>  3 files changed, 43 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> index f6e234dafb72..0df1430b9664 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> @@ -34,6 +34,12 @@
>   * Device Information
>   */
>  
> +static struct rcar_du_crtc_helper_funcs rcar_crtc_helper_funcs = {
> +	.du_planes_init = rcar_du_planes_init,
> +	.du_crtc_create = rcar_du_crtc_create,
> +	.du_atomic_check_planes = rcar_du_atomic_check_planes,
> +};
> +
>  static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
>  	.gen = 2,
>  	.features = RCAR_DU_FEATURE_CRTC_IRQ
> @@ -58,6 +64,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
>  	.num_rpf = 4,
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
> @@ -83,6 +90,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
>  	.num_rpf = 4,
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
> @@ -113,6 +121,7 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
>  	.num_rpf = 4,
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
> @@ -146,6 +155,7 @@ static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
> @@ -179,6 +189,7 @@ static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
> @@ -209,6 +220,7 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.lvds_clk_mask =  BIT(1) | BIT(0),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
> @@ -242,6 +254,7 @@ static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7779_info = {
> @@ -265,6 +278,7 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
>  	},
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7790_info = {
> @@ -298,6 +312,7 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
>  	.num_rpf = 4,
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
> @@ -326,6 +341,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
>  	.num_rpf = 4,
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7792_info = {
> @@ -349,6 +365,7 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
>  	.num_rpf = 4,
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7794_info = {
> @@ -375,6 +392,7 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
>  	.num_rpf = 4,
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7795_info = {
> @@ -412,6 +430,7 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.dpll_mask =  BIT(2) | BIT(1),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7796_info = {
> @@ -445,6 +464,7 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a77965_info = {
> @@ -478,6 +498,7 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a77970_info = {
> @@ -506,6 +527,7 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
>  	.num_rpf = 5,
>  	.max_width = 8190,
>  	.max_height = 8190,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
> @@ -537,6 +559,7 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.lvds_clk_mask =  BIT(1) | BIT(0),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
> @@ -559,6 +582,7 @@ static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.dsi_clk_mask =  BIT(1) | BIT(0),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct of_device_id rcar_du_of_table[] = {
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> index b0553b43363b..164cd9854aaf 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> @@ -61,6 +61,20 @@ struct rcar_du_output_routing {
>  	unsigned int port;
>  };
>  
> +/*
> + * struct rcar_du_crtc_helper_funcs - CRTC helper functions
> + * @du_planes_init: pointer to du_plane_init function
> + * @du_crtc_create: pointer to du_crtc_create function
> + * @du_atomic_check_planes: pointer to du_atomic_check_planes function
> + */
> +struct rcar_du_crtc_helper_funcs {
> +	int (*du_planes_init)(struct rcar_du_group *rgrp);
> +	int (*du_crtc_create)(struct rcar_du_group *rgrp, unsigned int swindex,
> +			      unsigned int hwindex);
> +	int (*du_atomic_check_planes)(struct drm_device *dev,
> +				      struct drm_atomic_state *state);
> +};
> +
>  /*
>   * struct rcar_du_device_info - DU model-specific information
>   * @gen: device generation (2 or 3)
> @@ -75,6 +89,7 @@ struct rcar_du_output_routing {
>   * @dpll_mask: bit mask of DU channels equipped with a DPLL
>   * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot clock
>   * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
> + * @fns: SoC specific CRTC helper functions
>   */
>  struct rcar_du_device_info {
>  	unsigned int gen;
> @@ -89,6 +104,7 @@ struct rcar_du_device_info {
>  	unsigned int dpll_mask;
>  	unsigned int dsi_clk_mask;
>  	unsigned int lvds_clk_mask;
> +	struct rcar_du_crtc_helper_funcs *fns;
>  };
>  
>  #define RCAR_DU_MAX_CRTCS		4
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> index 5857705aac20..a74417510894 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> @@ -478,7 +478,7 @@ static int rcar_du_atomic_check(struct drm_device *dev,
>  	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
>  		return 0;
>  
> -	return rcar_du_atomic_check_planes(dev, state);
> +	return rcdu->info->fns->du_atomic_check_planes(dev, state);
>  }
>  
>  static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
> @@ -882,7 +882,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
>  				   : 0;
>  
>  		if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
> -			ret = rcar_du_planes_init(rgrp);
> +			ret = rcdu->info->fns->du_planes_init(rgrp);
>  			if (ret < 0)
>  				return ret;
>  		}
> @@ -910,7 +910,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
>  
>  		rgrp = &rcdu->groups[hwindex / 2];
>  
> -		ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
> +		ret = rcdu->info->fns->du_crtc_create(rgrp, swindex++, hwindex);
>  		if (ret < 0)
>  			return ret;
>  	}

-- 
Regards,

Laurent Pinchart

Re: [PATCH v2 5/7] drm: rcar-du: Factorise rcar_du_{atomic_check,modeset_init}

[Laurent Pinchart]

Hi Biju,

Thank you for the patch.

On Wed, Mar 16, 2022 at 01:10:58PM +0000, Biju Das wrote:
> RZ/G2L SoC's does not have group/plane registers compared to RCar, hence it
> needs a different CRTC implementation. Factorise rcar_du_{atomic_check,
> modeset_init} by adding struct rcar_du_crtc_helper_funcs to struct
> rcar_du_device_info, so that it can support RZ/G2L SoC without any code
> changes.

I'd like to go the other way around. Instead of adding a layer of
indirection in the DU driver, could you create a new DRM driver, and
share common code with the DU driver ?

> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> v1->v2:
>  * Changed crtc_helper_funcs->rcar_crtc_helper_funcs
> RFC->v1:
>  * New patch
> ---
>  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 24 ++++++++++++++++++++++++
>  drivers/gpu/drm/rcar-du/rcar_du_drv.h | 16 ++++++++++++++++
>  drivers/gpu/drm/rcar-du/rcar_du_kms.c |  6 +++---
>  3 files changed, 43 insertions(+), 3 deletions(-)
> 
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> index f6e234dafb72..0df1430b9664 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> @@ -34,6 +34,12 @@
>   * Device Information
>   */
>  
> +static struct rcar_du_crtc_helper_funcs rcar_crtc_helper_funcs = {
> +	.du_planes_init = rcar_du_planes_init,
> +	.du_crtc_create = rcar_du_crtc_create,
> +	.du_atomic_check_planes = rcar_du_atomic_check_planes,
> +};
> +
>  static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
>  	.gen = 2,
>  	.features = RCAR_DU_FEATURE_CRTC_IRQ
> @@ -58,6 +64,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
>  	.num_rpf = 4,
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
> @@ -83,6 +90,7 @@ static const struct rcar_du_device_info rzg1_du_r8a7745_info = {
>  	.num_rpf = 4,
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
> @@ -113,6 +121,7 @@ static const struct rcar_du_device_info rzg1_du_r8a77470_info = {
>  	.num_rpf = 4,
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
> @@ -146,6 +155,7 @@ static const struct rcar_du_device_info rcar_du_r8a774a1_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
> @@ -179,6 +189,7 @@ static const struct rcar_du_device_info rcar_du_r8a774b1_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
> @@ -209,6 +220,7 @@ static const struct rcar_du_device_info rcar_du_r8a774c0_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.lvds_clk_mask =  BIT(1) | BIT(0),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
> @@ -242,6 +254,7 @@ static const struct rcar_du_device_info rcar_du_r8a774e1_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7779_info = {
> @@ -265,6 +278,7 @@ static const struct rcar_du_device_info rcar_du_r8a7779_info = {
>  	},
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7790_info = {
> @@ -298,6 +312,7 @@ static const struct rcar_du_device_info rcar_du_r8a7790_info = {
>  	.num_rpf = 4,
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */
> @@ -326,6 +341,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info = {
>  	.num_rpf = 4,
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7792_info = {
> @@ -349,6 +365,7 @@ static const struct rcar_du_device_info rcar_du_r8a7792_info = {
>  	.num_rpf = 4,
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7794_info = {
> @@ -375,6 +392,7 @@ static const struct rcar_du_device_info rcar_du_r8a7794_info = {
>  	.num_rpf = 4,
>  	.max_width = 4095,
>  	.max_height = 2047,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7795_info = {
> @@ -412,6 +430,7 @@ static const struct rcar_du_device_info rcar_du_r8a7795_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.dpll_mask =  BIT(2) | BIT(1),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7796_info = {
> @@ -445,6 +464,7 @@ static const struct rcar_du_device_info rcar_du_r8a7796_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a77965_info = {
> @@ -478,6 +498,7 @@ static const struct rcar_du_device_info rcar_du_r8a77965_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.dpll_mask =  BIT(1),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a77970_info = {
> @@ -506,6 +527,7 @@ static const struct rcar_du_device_info rcar_du_r8a77970_info = {
>  	.num_rpf = 5,
>  	.max_width = 8190,
>  	.max_height = 8190,
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
> @@ -537,6 +559,7 @@ static const struct rcar_du_device_info rcar_du_r8a7799x_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.lvds_clk_mask =  BIT(1) | BIT(0),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
> @@ -559,6 +582,7 @@ static const struct rcar_du_device_info rcar_du_r8a779a0_info = {
>  	.max_width = 8190,
>  	.max_height = 8190,
>  	.dsi_clk_mask =  BIT(1) | BIT(0),
> +	.fns = &rcar_crtc_helper_funcs,
>  };
>  
>  static const struct of_device_id rcar_du_of_table[] = {
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> index b0553b43363b..164cd9854aaf 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> @@ -61,6 +61,20 @@ struct rcar_du_output_routing {
>  	unsigned int port;
>  };
>  
> +/*
> + * struct rcar_du_crtc_helper_funcs - CRTC helper functions
> + * @du_planes_init: pointer to du_plane_init function
> + * @du_crtc_create: pointer to du_crtc_create function
> + * @du_atomic_check_planes: pointer to du_atomic_check_planes function
> + */
> +struct rcar_du_crtc_helper_funcs {
> +	int (*du_planes_init)(struct rcar_du_group *rgrp);
> +	int (*du_crtc_create)(struct rcar_du_group *rgrp, unsigned int swindex,
> +			      unsigned int hwindex);
> +	int (*du_atomic_check_planes)(struct drm_device *dev,
> +				      struct drm_atomic_state *state);
> +};
> +
>  /*
>   * struct rcar_du_device_info - DU model-specific information
>   * @gen: device generation (2 or 3)
> @@ -75,6 +89,7 @@ struct rcar_du_output_routing {
>   * @dpll_mask: bit mask of DU channels equipped with a DPLL
>   * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot clock
>   * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as dot clock
> + * @fns: SoC specific CRTC helper functions
>   */
>  struct rcar_du_device_info {
>  	unsigned int gen;
> @@ -89,6 +104,7 @@ struct rcar_du_device_info {
>  	unsigned int dpll_mask;
>  	unsigned int dsi_clk_mask;
>  	unsigned int lvds_clk_mask;
> +	struct rcar_du_crtc_helper_funcs *fns;
>  };
>  
>  #define RCAR_DU_MAX_CRTCS		4
> diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> index 5857705aac20..a74417510894 100644
> --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> @@ -478,7 +478,7 @@ static int rcar_du_atomic_check(struct drm_device *dev,
>  	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
>  		return 0;
>  
> -	return rcar_du_atomic_check_planes(dev, state);
> +	return rcdu->info->fns->du_atomic_check_planes(dev, state);
>  }
>  
>  static void rcar_du_atomic_commit_tail(struct drm_atomic_state *old_state)
> @@ -882,7 +882,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
>  				   : 0;
>  
>  		if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
> -			ret = rcar_du_planes_init(rgrp);
> +			ret = rcdu->info->fns->du_planes_init(rgrp);
>  			if (ret < 0)
>  				return ret;
>  		}
> @@ -910,7 +910,7 @@ int rcar_du_modeset_init(struct rcar_du_device *rcdu)
>  
>  		rgrp = &rcdu->groups[hwindex / 2];
>  
> -		ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
> +		ret = rcdu->info->fns->du_crtc_create(rgrp, swindex++, hwindex);
>  		if (ret < 0)
>  			return ret;
>  	}

-- 
Regards,

Laurent Pinchart

RE: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document r9a07g044l bindings

[Biju Das]

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document
> r9a07g044l bindings
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:54PM +0000, Biju Das wrote:
> > Extend the Renesas DU display bindings to support the r9a07g044l DU
> > module found on RZ/G2L LCDC.
> 
> Stupid question, but as this DU and the R-Car DU are completely different
> pieces of hardware, wouldn't a separate bindings file make sense ?

OK, will create separate bindings for RZ/G2L DU

Cheers,
Biju

> 
> The DT description in this patch looks good to me.
> 
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> >  * Updated commit description.
> >  * Removed LCDC references
> >  * Changed clock name from du.0->aclk
> >  * Changed reset name from du.0->du
> > RFC->v1:
> >  * Changed  minItems->maxItems for renesas,vsps.
> > RFC:
> >
> > ---
> >  .../bindings/display/renesas,du.yaml          | 54 +++++++++++++++++++
> >  1 file changed, 54 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml
> > b/Documentation/devicetree/bindings/display/renesas,du.yaml
> > index 13efea574584..f560608bf4e8 100644
> > --- a/Documentation/devicetree/bindings/display/renesas,du.yaml
> > +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
> > @@ -40,6 +40,7 @@ properties:
> >        - renesas,du-r8a77990 # for R-Car E3 compatible DU
> >        - renesas,du-r8a77995 # for R-Car D3 compatible DU
> >        - renesas,du-r8a779a0 # for R-Car V3U compatible DU
> > +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
> >
> >    reg:
> >      maxItems: 1
> > @@ -824,6 +825,59 @@ allOf:
> >          - reset-names
> >          - renesas,vsps
> >
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - renesas,du-r9a07g044l
> > +    then:
> > +      properties:
> > +        clocks:
> > +          items:
> > +            - description: Main clock
> > +            - description: Register access clock
> > +            - description: Video clock
> > +
> > +        clock-names:
> > +          items:
> > +            - const: aclk
> > +            - const: pclk
> > +            - const: vclk
> > +
> > +        interrupts:
> > +          maxItems: 1
> > +
> > +        resets:
> > +          maxItems: 1
> > +
> > +        reset-names:
> > +          items:
> > +            - const: du
> > +
> > +        ports:
> > +          properties:
> > +            port@0:
> > +              description: DPAD 0
> > +            port@1:
> > +              description: DSI 0
> > +            port@2: false
> > +            port@3: false
> > +
> > +          required:
> > +            - port@0
> > +            - port@1
> > +
> > +        renesas,vsps:
> > +          maxItems: 1
> > +
> > +      required:
> > +        - clock-names
> > +        - interrupts
> > +        - resets
> > +        - reset-names
> > +        - renesas,vsps
> > +
> >  additionalProperties: false
> >
> >  examples:
> 
> --
> Regards,
> 
> Laurent Pinchart

RE: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document r9a07g044l bindings

[Biju Das]

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 1/7] dt-bindings: display: renesas,du: Document
> r9a07g044l bindings
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:54PM +0000, Biju Das wrote:
> > Extend the Renesas DU display bindings to support the r9a07g044l DU
> > module found on RZ/G2L LCDC.
> 
> Stupid question, but as this DU and the R-Car DU are completely different
> pieces of hardware, wouldn't a separate bindings file make sense ?

OK, will create separate bindings for RZ/G2L DU

Cheers,
Biju

> 
> The DT description in this patch looks good to me.
> 
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> >  * Updated commit description.
> >  * Removed LCDC references
> >  * Changed clock name from du.0->aclk
> >  * Changed reset name from du.0->du
> > RFC->v1:
> >  * Changed  minItems->maxItems for renesas,vsps.
> > RFC:
> >
> > ---
> >  .../bindings/display/renesas,du.yaml          | 54 +++++++++++++++++++
> >  1 file changed, 54 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/display/renesas,du.yaml
> > b/Documentation/devicetree/bindings/display/renesas,du.yaml
> > index 13efea574584..f560608bf4e8 100644
> > --- a/Documentation/devicetree/bindings/display/renesas,du.yaml
> > +++ b/Documentation/devicetree/bindings/display/renesas,du.yaml
> > @@ -40,6 +40,7 @@ properties:
> >        - renesas,du-r8a77990 # for R-Car E3 compatible DU
> >        - renesas,du-r8a77995 # for R-Car D3 compatible DU
> >        - renesas,du-r8a779a0 # for R-Car V3U compatible DU
> > +      - renesas,du-r9a07g044l # for RZ/G2L compatible DU
> >
> >    reg:
> >      maxItems: 1
> > @@ -824,6 +825,59 @@ allOf:
> >          - reset-names
> >          - renesas,vsps
> >
> > +  - if:
> > +      properties:
> > +        compatible:
> > +          contains:
> > +            enum:
> > +              - renesas,du-r9a07g044l
> > +    then:
> > +      properties:
> > +        clocks:
> > +          items:
> > +            - description: Main clock
> > +            - description: Register access clock
> > +            - description: Video clock
> > +
> > +        clock-names:
> > +          items:
> > +            - const: aclk
> > +            - const: pclk
> > +            - const: vclk
> > +
> > +        interrupts:
> > +          maxItems: 1
> > +
> > +        resets:
> > +          maxItems: 1
> > +
> > +        reset-names:
> > +          items:
> > +            - const: du
> > +
> > +        ports:
> > +          properties:
> > +            port@0:
> > +              description: DPAD 0
> > +            port@1:
> > +              description: DSI 0
> > +            port@2: false
> > +            port@3: false
> > +
> > +          required:
> > +            - port@0
> > +            - port@1
> > +
> > +        renesas,vsps:
> > +          maxItems: 1
> > +
> > +      required:
> > +        - clock-names
> > +        - interrupts
> > +        - resets
> > +        - reset-names
> > +        - renesas,vsps
> > +
> >  additionalProperties: false
> >
> >  examples:
> 
> --
> Regards,
> 
> Laurent Pinchart

RE: [PATCH v2 2/7] drm: rcar-du: Add num_rpf to struct rcar_du_device_info

[Biju Das]

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 2/7] drm: rcar-du: Add num_rpf to struct
> rcar_du_device_info
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:55PM +0000, Biju Das wrote:
> > Number of RPF's VSP is different on R-Car and RZ/G2L  R-Car Gen3 -> 5
> > RPFs  R-Car Gen2 -> 4 RPFs  RZ/G2L -> 2 RPFs
> >
> > Add num_rpf to struct rcar_du_device_info to support later SoC without
> > any code changes.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> >  * No change
> > RFC->v1:
> >  * Fixed the comment for num_rpf s/rpf's/RPFs/ and s/vsp/VSP/
> > RFC:
> >  *
> > ---
> >  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 17 +++++++++++++++++
> > drivers/gpu/drm/rcar-du/rcar_du_drv.h |  2 ++
> > drivers/gpu/drm/rcar-du/rcar_du_vsp.c |  6 +-----
> >  3 files changed, 20 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > index 957ea97541d5..1bc7325aa356 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > @@ -55,6 +55,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7743_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a7745_info = { @@
> > -77,6 +78,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7745_info = {
> >  			.port = 1,
> >  		},
> >  	},
> > +	.num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a77470_info = { @@
> > -104,6 +106,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a77470_info = {
> >  			.port = 2,
> >  		},
> >  	},
> > +	.num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774a1_info = { @@
> > -133,6 +136,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774a1_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 5,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -163,6 +167,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774b1_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 5,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -190,6 +195,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774c0_info = {
> >  		},
> >  	},
> >  	.num_lvds = 2,
> > +	.num_rpf = 4,
> >  	.lvds_clk_mask =  BIT(1) | BIT(0),
> >  };
> >
> > @@ -220,6 +226,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774e1_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 5,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -272,6 +279,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7790_info = {
> >  		},
> >  	},
> >  	.num_lvds = 2,
> > +	.num_rpf = 4,
> >  };
> >
> >  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */ @@ -297,6
> > +305,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info =
> {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7792_info = { @@
> > -317,6 +326,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7792_info = {
> >  			.port = 1,
> >  		},
> >  	},
> > +	.num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7794_info = { @@
> > -340,6 +350,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7794_info = {
> >  			.port = 1,
> >  		},
> >  	},
> > +	.num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7795_info = { @@
> > -373,6 +384,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7795_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 5,
> >  	.dpll_mask =  BIT(2) | BIT(1),
> >  };
> >
> > @@ -403,6 +415,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7796_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 5,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -433,6 +446,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a77965_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 5,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -459,6 +473,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a77970_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 5,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7799x_info = { @@
> > -486,6 +501,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7799x_info = {
> >  		},
> >  	},
> >  	.num_lvds = 2,
> > +	.num_rpf = 5,
> >  	.lvds_clk_mask =  BIT(1) | BIT(0),
> >  };
> >
> > @@ -505,6 +521,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a779a0_info = {
> >  			.port = 1,
> >  		},
> >  	},
> > +	.num_rpf = 5,
> >  	.dsi_clk_mask =  BIT(1) | BIT(0),
> >  };
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > index 101f42df86ea..68c5de59d18d 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > @@ -69,6 +69,7 @@ struct rcar_du_output_routing {
> >   * @channels_mask: bit mask of available DU channels
> >   * @routes: array of CRTC to output routes, indexed by output
> (RCAR_DU_OUTPUT_*)
> >   * @num_lvds: number of internal LVDS encoders
> > + * @num_rpf: max number of RPFs in VSP
> 
> s/max //

OK, Will fix this.

Cheers,
Biju

> 
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> 
> >   * @dpll_mask: bit mask of DU channels equipped with a DPLL
> >   * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot
> clock
> >   * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as
> > dot clock @@ -80,6 +81,7 @@ struct rcar_du_device_info {
> >  	unsigned int channels_mask;
> >  	struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
> >  	unsigned int num_lvds;
> > +	unsigned int num_rpf;
> >  	unsigned int dpll_mask;
> >  	unsigned int dsi_clk_mask;
> >  	unsigned int lvds_clk_mask;
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> > index b7fc5b069cbc..cf045a203aa5 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> > @@ -415,11 +415,7 @@ int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct
> device_node *np,
> >  	if (ret < 0)
> >  		return ret;
> >
> > -	 /*
> > -	  * The VSP2D (Gen3) has 5 RPFs, but the VSP1D (Gen2) is limited to
> > -	  * 4 RPFs.
> > -	  */
> > -	num_planes = rcdu->info->gen >= 3 ? 5 : 4;
> > +	num_planes = rcdu->info->num_rpf;
> >
> >  	vsp->planes = kcalloc(num_planes, sizeof(*vsp->planes), GFP_KERNEL);
> >  	if (!vsp->planes)
> 
> --
> Regards,
> 
> Laurent Pinchart

RE: [PATCH v2 2/7] drm: rcar-du: Add num_rpf to struct rcar_du_device_info

[Biju Das]

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 2/7] drm: rcar-du: Add num_rpf to struct
> rcar_du_device_info
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:55PM +0000, Biju Das wrote:
> > Number of RPF's VSP is different on R-Car and RZ/G2L  R-Car Gen3 -> 5
> > RPFs  R-Car Gen2 -> 4 RPFs  RZ/G2L -> 2 RPFs
> >
> > Add num_rpf to struct rcar_du_device_info to support later SoC without
> > any code changes.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> >  * No change
> > RFC->v1:
> >  * Fixed the comment for num_rpf s/rpf's/RPFs/ and s/vsp/VSP/
> > RFC:
> >  *
> > ---
> >  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 17 +++++++++++++++++
> > drivers/gpu/drm/rcar-du/rcar_du_drv.h |  2 ++
> > drivers/gpu/drm/rcar-du/rcar_du_vsp.c |  6 +-----
> >  3 files changed, 20 insertions(+), 5 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > index 957ea97541d5..1bc7325aa356 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > @@ -55,6 +55,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7743_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a7745_info = { @@
> > -77,6 +78,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7745_info = {
> >  			.port = 1,
> >  		},
> >  	},
> > +	.num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a77470_info = { @@
> > -104,6 +106,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a77470_info = {
> >  			.port = 2,
> >  		},
> >  	},
> > +	.num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774a1_info = { @@
> > -133,6 +136,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774a1_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 5,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -163,6 +167,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774b1_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 5,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -190,6 +195,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774c0_info = {
> >  		},
> >  	},
> >  	.num_lvds = 2,
> > +	.num_rpf = 4,
> >  	.lvds_clk_mask =  BIT(1) | BIT(0),
> >  };
> >
> > @@ -220,6 +226,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774e1_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 5,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -272,6 +279,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7790_info = {
> >  		},
> >  	},
> >  	.num_lvds = 2,
> > +	.num_rpf = 4,
> >  };
> >
> >  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */ @@ -297,6
> > +305,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info =
> {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7792_info = { @@
> > -317,6 +326,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7792_info = {
> >  			.port = 1,
> >  		},
> >  	},
> > +	.num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7794_info = { @@
> > -340,6 +350,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7794_info = {
> >  			.port = 1,
> >  		},
> >  	},
> > +	.num_rpf = 4,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7795_info = { @@
> > -373,6 +384,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7795_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 5,
> >  	.dpll_mask =  BIT(2) | BIT(1),
> >  };
> >
> > @@ -403,6 +415,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7796_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 5,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -433,6 +446,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a77965_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 5,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -459,6 +473,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a77970_info = {
> >  		},
> >  	},
> >  	.num_lvds = 1,
> > +	.num_rpf = 5,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7799x_info = { @@
> > -486,6 +501,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7799x_info = {
> >  		},
> >  	},
> >  	.num_lvds = 2,
> > +	.num_rpf = 5,
> >  	.lvds_clk_mask =  BIT(1) | BIT(0),
> >  };
> >
> > @@ -505,6 +521,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a779a0_info = {
> >  			.port = 1,
> >  		},
> >  	},
> > +	.num_rpf = 5,
> >  	.dsi_clk_mask =  BIT(1) | BIT(0),
> >  };
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > index 101f42df86ea..68c5de59d18d 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > @@ -69,6 +69,7 @@ struct rcar_du_output_routing {
> >   * @channels_mask: bit mask of available DU channels
> >   * @routes: array of CRTC to output routes, indexed by output
> (RCAR_DU_OUTPUT_*)
> >   * @num_lvds: number of internal LVDS encoders
> > + * @num_rpf: max number of RPFs in VSP
> 
> s/max //

OK, Will fix this.

Cheers,
Biju

> 
> Reviewed-by: Laurent Pinchart <laurent.pinchart@ideasonboard.com>
> 
> >   * @dpll_mask: bit mask of DU channels equipped with a DPLL
> >   * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot
> clock
> >   * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as
> > dot clock @@ -80,6 +81,7 @@ struct rcar_du_device_info {
> >  	unsigned int channels_mask;
> >  	struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
> >  	unsigned int num_lvds;
> > +	unsigned int num_rpf;
> >  	unsigned int dpll_mask;
> >  	unsigned int dsi_clk_mask;
> >  	unsigned int lvds_clk_mask;
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> > index b7fc5b069cbc..cf045a203aa5 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_vsp.c
> > @@ -415,11 +415,7 @@ int rcar_du_vsp_init(struct rcar_du_vsp *vsp, struct
> device_node *np,
> >  	if (ret < 0)
> >  		return ret;
> >
> > -	 /*
> > -	  * The VSP2D (Gen3) has 5 RPFs, but the VSP1D (Gen2) is limited to
> > -	  * 4 RPFs.
> > -	  */
> > -	num_planes = rcdu->info->gen >= 3 ? 5 : 4;
> > +	num_planes = rcdu->info->num_rpf;
> >
> >  	vsp->planes = kcalloc(num_planes, sizeof(*vsp->planes), GFP_KERNEL);
> >  	if (!vsp->planes)
> 
> --
> Regards,
> 
> Laurent Pinchart

RE: [PATCH v2 3/7] drm: rcar-du: Add max_width and max_height to struct rcar_du_device_info

[Biju Das]

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 3/7] drm: rcar-du: Add max_width and max_height to
> struct rcar_du_device_info
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:56PM +0000, Biju Das wrote:
> > There are some differences related to max frame size supported by
> > different R-Car/RZ-G family of SoC's
> >
> > Max frame size supported by R-Car Gen1 & R-Car Gen2 is 4095x2047 Max
> > frame size supported by R-Car Gen3 is 8190x8190 Max frame size
> > supported by RZ/G2L is 1920x1080
> >
> > Add max_width and max_height to struct rcar_du_device_info to support
> > later SoC without any code changes.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> >  * No Change
> > RFC->V1:
> >  * No Change
> > RFC:
> >  *
> > ---
> >  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 36
> > +++++++++++++++++++++++++++  drivers/gpu/drm/rcar-du/rcar_du_drv.h |
> > 4 +++  drivers/gpu/drm/rcar-du/rcar_du_kms.c | 17 +++++--------
> >  3 files changed, 46 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > index 1bc7325aa356..4640c356a532 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > @@ -56,6 +56,8 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7743_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 4,
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a7745_info = { @@
> > -79,6 +81,8 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7745_info = {
> >  		},
> >  	},
> >  	.num_rpf = 4,
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a77470_info = { @@
> > -107,6 +111,8 @@ static const struct rcar_du_device_info
> rzg1_du_r8a77470_info = {
> >  		},
> >  	},
> >  	.num_rpf = 4,
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774a1_info = { @@
> > -137,6 +143,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a774a1_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -168,6 +176,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a774b1_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -196,6 +206,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a774c0_info = {
> >  	},
> >  	.num_lvds = 2,
> >  	.num_rpf = 4,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.lvds_clk_mask =  BIT(1) | BIT(0),
> >  };
> >
> > @@ -227,6 +239,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a774e1_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -249,6 +263,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7779_info = {
> >  			.port = 1,
> >  		},
> >  	},
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7790_info = { @@
> > -280,6 +296,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7790_info = {
> >  	},
> >  	.num_lvds = 2,
> >  	.num_rpf = 4,
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */ @@ -306,6
> > +324,8 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info =
> {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 4,
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7792_info = { @@
> > -327,6 +347,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7792_info = {
> >  		},
> >  	},
> >  	.num_rpf = 4,
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7794_info = { @@
> > -351,6 +373,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7794_info = {
> >  		},
> >  	},
> >  	.num_rpf = 4,
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7795_info = { @@
> > -385,6 +409,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7795_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.dpll_mask =  BIT(2) | BIT(1),
> >  };
> >
> > @@ -416,6 +442,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7796_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -447,6 +475,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a77965_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -474,6 +504,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a77970_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7799x_info = { @@
> > -502,6 +534,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7799x_info = {
> >  	},
> >  	.num_lvds = 2,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.lvds_clk_mask =  BIT(1) | BIT(0),
> >  };
> >
> > @@ -522,6 +556,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a779a0_info = {
> >  		},
> >  	},
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.dsi_clk_mask =  BIT(1) | BIT(0),
> >  };
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > index 68c5de59d18d..b0553b43363b 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > @@ -70,6 +70,8 @@ struct rcar_du_output_routing {
> >   * @routes: array of CRTC to output routes, indexed by output
> (RCAR_DU_OUTPUT_*)
> >   * @num_lvds: number of internal LVDS encoders
> >   * @num_rpf: max number of RPFs in VSP
> > + * @max_width: max frame width
> > + * @max_height: max frame height
> >   * @dpll_mask: bit mask of DU channels equipped with a DPLL
> >   * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot
> clock
> >   * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as
> > dot clock @@ -82,6 +84,8 @@ struct rcar_du_device_info {
> >  	struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
> >  	unsigned int num_lvds;
> >  	unsigned int num_rpf;
> > +	unsigned int max_width;
> > +	unsigned int max_height;
> >  	unsigned int dpll_mask;
> >  	unsigned int dsi_clk_mask;
> >  	unsigned int lvds_clk_mask;
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > index 190dbb7f15dd..5857705aac20 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > @@ -834,17 +834,12 @@ int rcar_du_modeset_init(struct rcar_du_device
> *rcdu)
> >  	dev->mode_config.funcs = &rcar_du_mode_config_funcs;
> >  	dev->mode_config.helper_private = &rcar_du_mode_config_helper;
> >
> > -	if (rcdu->info->gen < 3) {
> > -		dev->mode_config.max_width = 4095;
> > -		dev->mode_config.max_height = 2047;
> > -	} else {
> > -		/*
> > -		 * The Gen3 DU uses the VSP1 for memory access, and is limited
> > -		 * to frame sizes of 8190x8190.
> > -		 */
> > -		dev->mode_config.max_width = 8190;
> > -		dev->mode_config.max_height = 8190;
> > -	}
> > +	/*
> > +	 * The Gen3 DU uses the VSP1 for memory access, and is limited
> > +	 * to frame sizes of 8190x8190.
> > +	 */
> 
> This comment doesn't make much sense here anymore, but I think it's useful
> to keep the information. How about defining macros for the maximum width
> and height on different platforms, and moving the comment just before the
> macro definitions ?

This patch may not required as planning to add rzg2l_du_kms.c which will take care this
Differences in Next version.

Cheers,
Biju

> 
> > +	dev->mode_config.max_width = rcdu->info->max_width;
> > +	dev->mode_config.max_height = rcdu->info->max_height;
> >
> >  	rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
> >
> 
> --
> Regards,
> 
> Laurent Pinchart

RE: [PATCH v2 3/7] drm: rcar-du: Add max_width and max_height to struct rcar_du_device_info

[Biju Das]

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 3/7] drm: rcar-du: Add max_width and max_height to
> struct rcar_du_device_info
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:56PM +0000, Biju Das wrote:
> > There are some differences related to max frame size supported by
> > different R-Car/RZ-G family of SoC's
> >
> > Max frame size supported by R-Car Gen1 & R-Car Gen2 is 4095x2047 Max
> > frame size supported by R-Car Gen3 is 8190x8190 Max frame size
> > supported by RZ/G2L is 1920x1080
> >
> > Add max_width and max_height to struct rcar_du_device_info to support
> > later SoC without any code changes.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> >  * No Change
> > RFC->V1:
> >  * No Change
> > RFC:
> >  *
> > ---
> >  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 36
> > +++++++++++++++++++++++++++  drivers/gpu/drm/rcar-du/rcar_du_drv.h |
> > 4 +++  drivers/gpu/drm/rcar-du/rcar_du_kms.c | 17 +++++--------
> >  3 files changed, 46 insertions(+), 11 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > index 1bc7325aa356..4640c356a532 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > @@ -56,6 +56,8 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7743_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 4,
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a7745_info = { @@
> > -79,6 +81,8 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7745_info = {
> >  		},
> >  	},
> >  	.num_rpf = 4,
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a77470_info = { @@
> > -107,6 +111,8 @@ static const struct rcar_du_device_info
> rzg1_du_r8a77470_info = {
> >  		},
> >  	},
> >  	.num_rpf = 4,
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774a1_info = { @@
> > -137,6 +143,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a774a1_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -168,6 +176,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a774b1_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -196,6 +206,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a774c0_info = {
> >  	},
> >  	.num_lvds = 2,
> >  	.num_rpf = 4,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.lvds_clk_mask =  BIT(1) | BIT(0),
> >  };
> >
> > @@ -227,6 +239,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a774e1_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -249,6 +263,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7779_info = {
> >  			.port = 1,
> >  		},
> >  	},
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7790_info = { @@
> > -280,6 +296,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7790_info = {
> >  	},
> >  	.num_lvds = 2,
> >  	.num_rpf = 4,
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */ @@ -306,6
> > +324,8 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info =
> {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 4,
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7792_info = { @@
> > -327,6 +347,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7792_info = {
> >  		},
> >  	},
> >  	.num_rpf = 4,
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7794_info = { @@
> > -351,6 +373,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7794_info = {
> >  		},
> >  	},
> >  	.num_rpf = 4,
> > +	.max_width = 4095,
> > +	.max_height = 2047,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7795_info = { @@
> > -385,6 +409,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7795_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.dpll_mask =  BIT(2) | BIT(1),
> >  };
> >
> > @@ -416,6 +442,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7796_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -447,6 +475,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a77965_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> >  };
> >
> > @@ -474,6 +504,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a77970_info = {
> >  	},
> >  	.num_lvds = 1,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7799x_info = { @@
> > -502,6 +534,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a7799x_info = {
> >  	},
> >  	.num_lvds = 2,
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.lvds_clk_mask =  BIT(1) | BIT(0),
> >  };
> >
> > @@ -522,6 +556,8 @@ static const struct rcar_du_device_info
> rcar_du_r8a779a0_info = {
> >  		},
> >  	},
> >  	.num_rpf = 5,
> > +	.max_width = 8190,
> > +	.max_height = 8190,
> >  	.dsi_clk_mask =  BIT(1) | BIT(0),
> >  };
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > index 68c5de59d18d..b0553b43363b 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > @@ -70,6 +70,8 @@ struct rcar_du_output_routing {
> >   * @routes: array of CRTC to output routes, indexed by output
> (RCAR_DU_OUTPUT_*)
> >   * @num_lvds: number of internal LVDS encoders
> >   * @num_rpf: max number of RPFs in VSP
> > + * @max_width: max frame width
> > + * @max_height: max frame height
> >   * @dpll_mask: bit mask of DU channels equipped with a DPLL
> >   * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot
> clock
> >   * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as
> > dot clock @@ -82,6 +84,8 @@ struct rcar_du_device_info {
> >  	struct rcar_du_output_routing routes[RCAR_DU_OUTPUT_MAX];
> >  	unsigned int num_lvds;
> >  	unsigned int num_rpf;
> > +	unsigned int max_width;
> > +	unsigned int max_height;
> >  	unsigned int dpll_mask;
> >  	unsigned int dsi_clk_mask;
> >  	unsigned int lvds_clk_mask;
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > index 190dbb7f15dd..5857705aac20 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > @@ -834,17 +834,12 @@ int rcar_du_modeset_init(struct rcar_du_device
> *rcdu)
> >  	dev->mode_config.funcs = &rcar_du_mode_config_funcs;
> >  	dev->mode_config.helper_private = &rcar_du_mode_config_helper;
> >
> > -	if (rcdu->info->gen < 3) {
> > -		dev->mode_config.max_width = 4095;
> > -		dev->mode_config.max_height = 2047;
> > -	} else {
> > -		/*
> > -		 * The Gen3 DU uses the VSP1 for memory access, and is limited
> > -		 * to frame sizes of 8190x8190.
> > -		 */
> > -		dev->mode_config.max_width = 8190;
> > -		dev->mode_config.max_height = 8190;
> > -	}
> > +	/*
> > +	 * The Gen3 DU uses the VSP1 for memory access, and is limited
> > +	 * to frame sizes of 8190x8190.
> > +	 */
> 
> This comment doesn't make much sense here anymore, but I think it's useful
> to keep the information. How about defining macros for the maximum width
> and height on different platforms, and moving the comment just before the
> macro definitions ?

This patch may not required as planning to add rzg2l_du_kms.c which will take care this
Differences in Next version.

Cheers,
Biju

> 
> > +	dev->mode_config.max_width = rcdu->info->max_width;
> > +	dev->mode_config.max_height = rcdu->info->max_height;
> >
> >  	rcdu->num_crtcs = hweight8(rcdu->info->channels_mask);
> >
> 
> --
> Regards,
> 
> Laurent Pinchart

RE: [PATCH v2 4/7] drm: rcar-du: Move rcar_du_output_name() to rcar_du_common.c

[Biju Das]

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 4/7] drm: rcar-du: Move rcar_du_output_name() to
> rcar_du_common.c
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:57PM +0000, Biju Das wrote:
> > RZ/G2L SoC's does not have group/plane registers compared to RCar,
> > hence it needs a different CRTC implementation.
> >
> > Move rcar_du_output_name() to a new common file rcar_du_common.c, So
> > that the same function can be reused by RZ/G2L SoC later.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> >  * No change
> > RFC->v1:
> >  New patch
> > ---
> >  drivers/gpu/drm/rcar-du/Makefile         |  1 +
> >  drivers/gpu/drm/rcar-du/rcar_du_common.c | 30 ++++++++++++++++++++++++
> >  drivers/gpu/drm/rcar-du/rcar_du_drv.c    | 20 ----------------
> >  3 files changed, 31 insertions(+), 20 deletions(-)  create mode
> > 100644 drivers/gpu/drm/rcar-du/rcar_du_common.c
> >
> > diff --git a/drivers/gpu/drm/rcar-du/Makefile
> > b/drivers/gpu/drm/rcar-du/Makefile
> > index e7275b5e7ec8..331e12d65a6b 100644
> > --- a/drivers/gpu/drm/rcar-du/Makefile
> > +++ b/drivers/gpu/drm/rcar-du/Makefile
> > @@ -1,5 +1,6 @@
> >  # SPDX-License-Identifier: GPL-2.0
> >  rcar-du-drm-y := rcar_du_crtc.o \
> > +		 rcar_du_common.o \
> >  		 rcar_du_drv.o \
> >  		 rcar_du_encoder.o \
> >  		 rcar_du_group.o \
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_common.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_common.c
> > new file mode 100644
> > index 000000000000..f9f9908cda6d
> > --- /dev/null
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_common.c
> > @@ -0,0 +1,30 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * rcar_du_common.c  --  R-Car Display Unit Common
> > + *
> > + * Copyright (C) 2013-2022 Renesas Electronics Corporation
> > + *
> > + * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
> > + */
> > +
> > +#include "rcar_du_drv.h"
> > +
> > +const char *rcar_du_output_name(enum rcar_du_output output) {
> > +	static const char * const names[] = {
> > +		[RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
> > +		[RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
> > +		[RCAR_DU_OUTPUT_DSI0] = "DSI0",
> > +		[RCAR_DU_OUTPUT_DSI1] = "DSI1",
> > +		[RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
> > +		[RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
> > +		[RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
> > +		[RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
> > +		[RCAR_DU_OUTPUT_TCON] = "TCON",
> > +	};
> > +
> > +	if (output >= ARRAY_SIZE(names) || !names[output])
> > +		return "UNKNOWN";
> > +
> > +	return names[output];
> > +}
> 
> As we have nothing else than this function in this file, how about moving
> it to rcar_du_drv.c instead, to avoid adding a new file ?

OK, since it is small change will add the same in rzg2l_du_drv.c file.

Cheers,
Biju

> You also need to add a declaration for rcar_du_output_name() in the
> appropriate header.
> 
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > index 4640c356a532..f6e234dafb72 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > @@ -591,26 +591,6 @@ static const struct of_device_id
> > rcar_du_of_table[] = {
> >
> >  MODULE_DEVICE_TABLE(of, rcar_du_of_table);
> >
> > -const char *rcar_du_output_name(enum rcar_du_output output) -{
> > -	static const char * const names[] = {
> > -		[RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
> > -		[RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
> > -		[RCAR_DU_OUTPUT_DSI0] = "DSI0",
> > -		[RCAR_DU_OUTPUT_DSI1] = "DSI1",
> > -		[RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
> > -		[RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
> > -		[RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
> > -		[RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
> > -		[RCAR_DU_OUTPUT_TCON] = "TCON",
> > -	};
> > -
> > -	if (output >= ARRAY_SIZE(names) || !names[output])
> > -		return "UNKNOWN";
> > -
> > -	return names[output];
> > -}
> > -
> >  /* ---------------------------------------------------------------------
> --------
> >   * DRM operations
> >   */
> 
> --
> Regards,
> 
> Laurent Pinchart

RE: [PATCH v2 4/7] drm: rcar-du: Move rcar_du_output_name() to rcar_du_common.c

[Biju Das]

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 4/7] drm: rcar-du: Move rcar_du_output_name() to
> rcar_du_common.c
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:57PM +0000, Biju Das wrote:
> > RZ/G2L SoC's does not have group/plane registers compared to RCar,
> > hence it needs a different CRTC implementation.
> >
> > Move rcar_du_output_name() to a new common file rcar_du_common.c, So
> > that the same function can be reused by RZ/G2L SoC later.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> >  * No change
> > RFC->v1:
> >  New patch
> > ---
> >  drivers/gpu/drm/rcar-du/Makefile         |  1 +
> >  drivers/gpu/drm/rcar-du/rcar_du_common.c | 30 ++++++++++++++++++++++++
> >  drivers/gpu/drm/rcar-du/rcar_du_drv.c    | 20 ----------------
> >  3 files changed, 31 insertions(+), 20 deletions(-)  create mode
> > 100644 drivers/gpu/drm/rcar-du/rcar_du_common.c
> >
> > diff --git a/drivers/gpu/drm/rcar-du/Makefile
> > b/drivers/gpu/drm/rcar-du/Makefile
> > index e7275b5e7ec8..331e12d65a6b 100644
> > --- a/drivers/gpu/drm/rcar-du/Makefile
> > +++ b/drivers/gpu/drm/rcar-du/Makefile
> > @@ -1,5 +1,6 @@
> >  # SPDX-License-Identifier: GPL-2.0
> >  rcar-du-drm-y := rcar_du_crtc.o \
> > +		 rcar_du_common.o \
> >  		 rcar_du_drv.o \
> >  		 rcar_du_encoder.o \
> >  		 rcar_du_group.o \
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_common.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_common.c
> > new file mode 100644
> > index 000000000000..f9f9908cda6d
> > --- /dev/null
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_common.c
> > @@ -0,0 +1,30 @@
> > +// SPDX-License-Identifier: GPL-2.0+
> > +/*
> > + * rcar_du_common.c  --  R-Car Display Unit Common
> > + *
> > + * Copyright (C) 2013-2022 Renesas Electronics Corporation
> > + *
> > + * Contact: Laurent Pinchart (laurent.pinchart@ideasonboard.com)
> > + */
> > +
> > +#include "rcar_du_drv.h"
> > +
> > +const char *rcar_du_output_name(enum rcar_du_output output) {
> > +	static const char * const names[] = {
> > +		[RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
> > +		[RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
> > +		[RCAR_DU_OUTPUT_DSI0] = "DSI0",
> > +		[RCAR_DU_OUTPUT_DSI1] = "DSI1",
> > +		[RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
> > +		[RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
> > +		[RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
> > +		[RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
> > +		[RCAR_DU_OUTPUT_TCON] = "TCON",
> > +	};
> > +
> > +	if (output >= ARRAY_SIZE(names) || !names[output])
> > +		return "UNKNOWN";
> > +
> > +	return names[output];
> > +}
> 
> As we have nothing else than this function in this file, how about moving
> it to rcar_du_drv.c instead, to avoid adding a new file ?

OK, since it is small change will add the same in rzg2l_du_drv.c file.

Cheers,
Biju

> You also need to add a declaration for rcar_du_output_name() in the
> appropriate header.
> 
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > index 4640c356a532..f6e234dafb72 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > @@ -591,26 +591,6 @@ static const struct of_device_id
> > rcar_du_of_table[] = {
> >
> >  MODULE_DEVICE_TABLE(of, rcar_du_of_table);
> >
> > -const char *rcar_du_output_name(enum rcar_du_output output) -{
> > -	static const char * const names[] = {
> > -		[RCAR_DU_OUTPUT_DPAD0] = "DPAD0",
> > -		[RCAR_DU_OUTPUT_DPAD1] = "DPAD1",
> > -		[RCAR_DU_OUTPUT_DSI0] = "DSI0",
> > -		[RCAR_DU_OUTPUT_DSI1] = "DSI1",
> > -		[RCAR_DU_OUTPUT_HDMI0] = "HDMI0",
> > -		[RCAR_DU_OUTPUT_HDMI1] = "HDMI1",
> > -		[RCAR_DU_OUTPUT_LVDS0] = "LVDS0",
> > -		[RCAR_DU_OUTPUT_LVDS1] = "LVDS1",
> > -		[RCAR_DU_OUTPUT_TCON] = "TCON",
> > -	};
> > -
> > -	if (output >= ARRAY_SIZE(names) || !names[output])
> > -		return "UNKNOWN";
> > -
> > -	return names[output];
> > -}
> > -
> >  /* ---------------------------------------------------------------------
> --------
> >   * DRM operations
> >   */
> 
> --
> Regards,
> 
> Laurent Pinchart

RE: [PATCH v2 5/7] drm: rcar-du: Factorise rcar_du_{atomic_check,modeset_init}

[Biju Das]

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 5/7] drm: rcar-du: Factorise
> rcar_du_{atomic_check,modeset_init}
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:58PM +0000, Biju Das wrote:
> > RZ/G2L SoC's does not have group/plane registers compared to RCar,
> > hence it needs a different CRTC implementation. Factorise
> > rcar_du_{atomic_check, modeset_init} by adding struct
> > rcar_du_crtc_helper_funcs to struct rcar_du_device_info, so that it
> > can support RZ/G2L SoC without any code changes.
> 
> I'd like to go the other way around. Instead of adding a layer of
> indirection in the DU driver, could you create a new DRM driver, and share
> common code with the DU driver ?

OK will crate new DRM driver and avoid all the indirection in DU driver.

Regards,
Biju

> 
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> >  * Changed crtc_helper_funcs->rcar_crtc_helper_funcs
> > RFC->v1:
> >  * New patch
> > ---
> >  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 24 ++++++++++++++++++++++++
> > drivers/gpu/drm/rcar-du/rcar_du_drv.h | 16 ++++++++++++++++
> > drivers/gpu/drm/rcar-du/rcar_du_kms.c |  6 +++---
> >  3 files changed, 43 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > index f6e234dafb72..0df1430b9664 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > @@ -34,6 +34,12 @@
> >   * Device Information
> >   */
> >
> > +static struct rcar_du_crtc_helper_funcs rcar_crtc_helper_funcs = {
> > +	.du_planes_init = rcar_du_planes_init,
> > +	.du_crtc_create = rcar_du_crtc_create,
> > +	.du_atomic_check_planes = rcar_du_atomic_check_planes, };
> > +
> >  static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
> >  	.gen = 2,
> >  	.features = RCAR_DU_FEATURE_CRTC_IRQ @@ -58,6 +64,7 @@ static const
> > struct rcar_du_device_info rzg1_du_r8a7743_info = {
> >  	.num_rpf = 4,
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a7745_info = { @@
> > -83,6 +90,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7745_info = {
> >  	.num_rpf = 4,
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a77470_info = { @@
> > -113,6 +121,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a77470_info = {
> >  	.num_rpf = 4,
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774a1_info = { @@
> > -146,6 +155,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774a1_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774b1_info = { @@
> > -179,6 +189,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774b1_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774c0_info = { @@
> > -209,6 +220,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774c0_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.lvds_clk_mask =  BIT(1) | BIT(0),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774e1_info = { @@
> > -242,6 +254,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774e1_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7779_info = { @@
> > -265,6 +278,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7779_info = {
> >  	},
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7790_info = { @@
> > -298,6 +312,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7790_info = {
> >  	.num_rpf = 4,
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */ @@ -326,6
> > +341,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info =
> {
> >  	.num_rpf = 4,
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7792_info = { @@
> > -349,6 +365,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7792_info = {
> >  	.num_rpf = 4,
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7794_info = { @@
> > -375,6 +392,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7794_info = {
> >  	.num_rpf = 4,
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7795_info = { @@
> > -412,6 +430,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7795_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.dpll_mask =  BIT(2) | BIT(1),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7796_info = { @@
> > -445,6 +464,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7796_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a77965_info = { @@
> > -478,6 +498,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a77965_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a77970_info = { @@
> > -506,6 +527,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a77970_info = {
> >  	.num_rpf = 5,
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7799x_info = { @@
> > -537,6 +559,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7799x_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.lvds_clk_mask =  BIT(1) | BIT(0),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a779a0_info = { @@
> > -559,6 +582,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a779a0_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.dsi_clk_mask =  BIT(1) | BIT(0),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct of_device_id rcar_du_of_table[] = { diff --git
> > a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > index b0553b43363b..164cd9854aaf 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > @@ -61,6 +61,20 @@ struct rcar_du_output_routing {
> >  	unsigned int port;
> >  };
> >
> > +/*
> > + * struct rcar_du_crtc_helper_funcs - CRTC helper functions
> > + * @du_planes_init: pointer to du_plane_init function
> > + * @du_crtc_create: pointer to du_crtc_create function
> > + * @du_atomic_check_planes: pointer to du_atomic_check_planes
> > +function  */ struct rcar_du_crtc_helper_funcs {
> > +	int (*du_planes_init)(struct rcar_du_group *rgrp);
> > +	int (*du_crtc_create)(struct rcar_du_group *rgrp, unsigned int
> swindex,
> > +			      unsigned int hwindex);
> > +	int (*du_atomic_check_planes)(struct drm_device *dev,
> > +				      struct drm_atomic_state *state); };
> > +
> >  /*
> >   * struct rcar_du_device_info - DU model-specific information
> >   * @gen: device generation (2 or 3)
> > @@ -75,6 +89,7 @@ struct rcar_du_output_routing {
> >   * @dpll_mask: bit mask of DU channels equipped with a DPLL
> >   * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot
> clock
> >   * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as
> > dot clock
> > + * @fns: SoC specific CRTC helper functions
> >   */
> >  struct rcar_du_device_info {
> >  	unsigned int gen;
> > @@ -89,6 +104,7 @@ struct rcar_du_device_info {
> >  	unsigned int dpll_mask;
> >  	unsigned int dsi_clk_mask;
> >  	unsigned int lvds_clk_mask;
> > +	struct rcar_du_crtc_helper_funcs *fns;
> >  };
> >
> >  #define RCAR_DU_MAX_CRTCS		4
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > index 5857705aac20..a74417510894 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > @@ -478,7 +478,7 @@ static int rcar_du_atomic_check(struct drm_device
> *dev,
> >  	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
> >  		return 0;
> >
> > -	return rcar_du_atomic_check_planes(dev, state);
> > +	return rcdu->info->fns->du_atomic_check_planes(dev, state);
> >  }
> >
> >  static void rcar_du_atomic_commit_tail(struct drm_atomic_state
> > *old_state) @@ -882,7 +882,7 @@ int rcar_du_modeset_init(struct
> rcar_du_device *rcdu)
> >  				   : 0;
> >
> >  		if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
> > -			ret = rcar_du_planes_init(rgrp);
> > +			ret = rcdu->info->fns->du_planes_init(rgrp);
> >  			if (ret < 0)
> >  				return ret;
> >  		}
> > @@ -910,7 +910,7 @@ int rcar_du_modeset_init(struct rcar_du_device
> > *rcdu)
> >
> >  		rgrp = &rcdu->groups[hwindex / 2];
> >
> > -		ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
> > +		ret = rcdu->info->fns->du_crtc_create(rgrp, swindex++,
> hwindex);
> >  		if (ret < 0)
> >  			return ret;
> >  	}
> 
> --
> Regards,
> 
> Laurent Pinchart

RE: [PATCH v2 5/7] drm: rcar-du: Factorise rcar_du_{atomic_check,modeset_init}

[Biju Das]

Hi Laurent,

Thanks for the feedback.

> Subject: Re: [PATCH v2 5/7] drm: rcar-du: Factorise
> rcar_du_{atomic_check,modeset_init}
> 
> Hi Biju,
> 
> Thank you for the patch.
> 
> On Wed, Mar 16, 2022 at 01:10:58PM +0000, Biju Das wrote:
> > RZ/G2L SoC's does not have group/plane registers compared to RCar,
> > hence it needs a different CRTC implementation. Factorise
> > rcar_du_{atomic_check, modeset_init} by adding struct
> > rcar_du_crtc_helper_funcs to struct rcar_du_device_info, so that it
> > can support RZ/G2L SoC without any code changes.
> 
> I'd like to go the other way around. Instead of adding a layer of
> indirection in the DU driver, could you create a new DRM driver, and share
> common code with the DU driver ?

OK will crate new DRM driver and avoid all the indirection in DU driver.

Regards,
Biju

> 
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > v1->v2:
> >  * Changed crtc_helper_funcs->rcar_crtc_helper_funcs
> > RFC->v1:
> >  * New patch
> > ---
> >  drivers/gpu/drm/rcar-du/rcar_du_drv.c | 24 ++++++++++++++++++++++++
> > drivers/gpu/drm/rcar-du/rcar_du_drv.h | 16 ++++++++++++++++
> > drivers/gpu/drm/rcar-du/rcar_du_kms.c |  6 +++---
> >  3 files changed, 43 insertions(+), 3 deletions(-)
> >
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > index f6e234dafb72..0df1430b9664 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.c
> > @@ -34,6 +34,12 @@
> >   * Device Information
> >   */
> >
> > +static struct rcar_du_crtc_helper_funcs rcar_crtc_helper_funcs = {
> > +	.du_planes_init = rcar_du_planes_init,
> > +	.du_crtc_create = rcar_du_crtc_create,
> > +	.du_atomic_check_planes = rcar_du_atomic_check_planes, };
> > +
> >  static const struct rcar_du_device_info rzg1_du_r8a7743_info = {
> >  	.gen = 2,
> >  	.features = RCAR_DU_FEATURE_CRTC_IRQ @@ -58,6 +64,7 @@ static const
> > struct rcar_du_device_info rzg1_du_r8a7743_info = {
> >  	.num_rpf = 4,
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a7745_info = { @@
> > -83,6 +90,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a7745_info = {
> >  	.num_rpf = 4,
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rzg1_du_r8a77470_info = { @@
> > -113,6 +121,7 @@ static const struct rcar_du_device_info
> rzg1_du_r8a77470_info = {
> >  	.num_rpf = 4,
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774a1_info = { @@
> > -146,6 +155,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774a1_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774b1_info = { @@
> > -179,6 +189,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774b1_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774c0_info = { @@
> > -209,6 +220,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774c0_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.lvds_clk_mask =  BIT(1) | BIT(0),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a774e1_info = { @@
> > -242,6 +254,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a774e1_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7779_info = { @@
> > -265,6 +278,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7779_info = {
> >  	},
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7790_info = { @@
> > -298,6 +312,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7790_info = {
> >  	.num_rpf = 4,
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  /* M2-W (r8a7791) and M2-N (r8a7793) are identical */ @@ -326,6
> > +341,7 @@ static const struct rcar_du_device_info rcar_du_r8a7791_info =
> {
> >  	.num_rpf = 4,
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7792_info = { @@
> > -349,6 +365,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7792_info = {
> >  	.num_rpf = 4,
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7794_info = { @@
> > -375,6 +392,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7794_info = {
> >  	.num_rpf = 4,
> >  	.max_width = 4095,
> >  	.max_height = 2047,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7795_info = { @@
> > -412,6 +430,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7795_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.dpll_mask =  BIT(2) | BIT(1),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7796_info = { @@
> > -445,6 +464,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7796_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a77965_info = { @@
> > -478,6 +498,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a77965_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.dpll_mask =  BIT(1),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a77970_info = { @@
> > -506,6 +527,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a77970_info = {
> >  	.num_rpf = 5,
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a7799x_info = { @@
> > -537,6 +559,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a7799x_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.lvds_clk_mask =  BIT(1) | BIT(0),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct rcar_du_device_info rcar_du_r8a779a0_info = { @@
> > -559,6 +582,7 @@ static const struct rcar_du_device_info
> rcar_du_r8a779a0_info = {
> >  	.max_width = 8190,
> >  	.max_height = 8190,
> >  	.dsi_clk_mask =  BIT(1) | BIT(0),
> > +	.fns = &rcar_crtc_helper_funcs,
> >  };
> >
> >  static const struct of_device_id rcar_du_of_table[] = { diff --git
> > a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > index b0553b43363b..164cd9854aaf 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_drv.h
> > @@ -61,6 +61,20 @@ struct rcar_du_output_routing {
> >  	unsigned int port;
> >  };
> >
> > +/*
> > + * struct rcar_du_crtc_helper_funcs - CRTC helper functions
> > + * @du_planes_init: pointer to du_plane_init function
> > + * @du_crtc_create: pointer to du_crtc_create function
> > + * @du_atomic_check_planes: pointer to du_atomic_check_planes
> > +function  */ struct rcar_du_crtc_helper_funcs {
> > +	int (*du_planes_init)(struct rcar_du_group *rgrp);
> > +	int (*du_crtc_create)(struct rcar_du_group *rgrp, unsigned int
> swindex,
> > +			      unsigned int hwindex);
> > +	int (*du_atomic_check_planes)(struct drm_device *dev,
> > +				      struct drm_atomic_state *state); };
> > +
> >  /*
> >   * struct rcar_du_device_info - DU model-specific information
> >   * @gen: device generation (2 or 3)
> > @@ -75,6 +89,7 @@ struct rcar_du_output_routing {
> >   * @dpll_mask: bit mask of DU channels equipped with a DPLL
> >   * @dsi_clk_mask: bitmask of channels that can use the DSI clock as dot
> clock
> >   * @lvds_clk_mask: bitmask of channels that can use the LVDS clock as
> > dot clock
> > + * @fns: SoC specific CRTC helper functions
> >   */
> >  struct rcar_du_device_info {
> >  	unsigned int gen;
> > @@ -89,6 +104,7 @@ struct rcar_du_device_info {
> >  	unsigned int dpll_mask;
> >  	unsigned int dsi_clk_mask;
> >  	unsigned int lvds_clk_mask;
> > +	struct rcar_du_crtc_helper_funcs *fns;
> >  };
> >
> >  #define RCAR_DU_MAX_CRTCS		4
> > diff --git a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > index 5857705aac20..a74417510894 100644
> > --- a/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > +++ b/drivers/gpu/drm/rcar-du/rcar_du_kms.c
> > @@ -478,7 +478,7 @@ static int rcar_du_atomic_check(struct drm_device
> *dev,
> >  	if (rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE))
> >  		return 0;
> >
> > -	return rcar_du_atomic_check_planes(dev, state);
> > +	return rcdu->info->fns->du_atomic_check_planes(dev, state);
> >  }
> >
> >  static void rcar_du_atomic_commit_tail(struct drm_atomic_state
> > *old_state) @@ -882,7 +882,7 @@ int rcar_du_modeset_init(struct
> rcar_du_device *rcdu)
> >  				   : 0;
> >
> >  		if (!rcar_du_has(rcdu, RCAR_DU_FEATURE_VSP1_SOURCE)) {
> > -			ret = rcar_du_planes_init(rgrp);
> > +			ret = rcdu->info->fns->du_planes_init(rgrp);
> >  			if (ret < 0)
> >  				return ret;
> >  		}
> > @@ -910,7 +910,7 @@ int rcar_du_modeset_init(struct rcar_du_device
> > *rcdu)
> >
> >  		rgrp = &rcdu->groups[hwindex / 2];
> >
> > -		ret = rcar_du_crtc_create(rgrp, swindex++, hwindex);
> > +		ret = rcdu->info->fns->du_crtc_create(rgrp, swindex++,
> hwindex);
> >  		if (ret < 0)
> >  			return ret;
> >  	}
> 
> --
> Regards,
> 
> Laurent Pinchart