* [PATCH 00/19] ASoC: fsl_micfil: Driver updates
@ 2022-03-17 8:27 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:27 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
This series has a bunch of cleanups for the FSL MICFIL driver. There is
not much chance for regressions in this series as the driver currently
can't work at all. The MICFIL needs multififo support in the i.MX SDMA
engine which is added with this series, see 10/19.
The multififo support is selected in the dma phandle arguments in the
device tree, the transfer type must be '25' aka IMX_DMATYPE_MULTI_SAI.
This is set already to 25 in the upstream i.MX8M[NM] dtsi files, but the
SDMA driver silently ignores unsupported values instead of throwing an
error. This is fixed in this series and multififo support is added.
I think the series should go via the ASoC tree, so I'll need an ack from
the DMA guys for 9/19 and 10/10.
Sascha
Sascha Hauer (19):
ASoC: fsl_micfil: Drop unnecessary register read
ASoC: fsl_micfil: Drop unused register read
ASoC: fsl_micfil: drop fsl_micfil_set_mclk_rate()
ASoC: fsl_micfil: do not define SHIFT/MASK for single bits
ASoC: fsl_micfil: use GENMASK to define register bit fields
ASoC: fsl_micfil: use clear/set bits
ASoC: fsl_micfil: drop error messages from failed register accesses
ASoC: fsl_micfil: drop unused variables
dma: imx-sdma: error out on unsupported transfer types
dma: imx-sdma: Add multi fifo support
ASoC: fsl_micfil: add multi fifo support
ASoC: fsl_micfil: use define for OSR default value
ASoC: fsl_micfil: Drop get_pdm_clk()
ASoC: fsl_micfil: simplify clock setting
ASoC: fsl_micfil: rework quality setting
ASoC: fsl_micfil: drop unused include
ASoC: fsl_micfil: drop only once used defines
ASoC: fsl_micfil: drop support for undocumented property
ASoC: fsl_micfil: fold fsl_set_clock_params() into its only user
drivers/dma/imx-sdma.c | 71 ++++-
include/linux/platform_data/dma-imx.h | 7 +
sound/soc/fsl/fsl_micfil.c | 368 +++++++++-----------------
sound/soc/fsl/fsl_micfil.h | 269 +++++--------------
4 files changed, 265 insertions(+), 450 deletions(-)
--
2.30.2
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 00/19] ASoC: fsl_micfil: Driver updates
@ 2022-03-17 8:27 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:27 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
This series has a bunch of cleanups for the FSL MICFIL driver. There is
not much chance for regressions in this series as the driver currently
can't work at all. The MICFIL needs multififo support in the i.MX SDMA
engine which is added with this series, see 10/19.
The multififo support is selected in the dma phandle arguments in the
device tree, the transfer type must be '25' aka IMX_DMATYPE_MULTI_SAI.
This is set already to 25 in the upstream i.MX8M[NM] dtsi files, but the
SDMA driver silently ignores unsupported values instead of throwing an
error. This is fixed in this series and multififo support is added.
I think the series should go via the ASoC tree, so I'll need an ack from
the DMA guys for 9/19 and 10/10.
Sascha
Sascha Hauer (19):
ASoC: fsl_micfil: Drop unnecessary register read
ASoC: fsl_micfil: Drop unused register read
ASoC: fsl_micfil: drop fsl_micfil_set_mclk_rate()
ASoC: fsl_micfil: do not define SHIFT/MASK for single bits
ASoC: fsl_micfil: use GENMASK to define register bit fields
ASoC: fsl_micfil: use clear/set bits
ASoC: fsl_micfil: drop error messages from failed register accesses
ASoC: fsl_micfil: drop unused variables
dma: imx-sdma: error out on unsupported transfer types
dma: imx-sdma: Add multi fifo support
ASoC: fsl_micfil: add multi fifo support
ASoC: fsl_micfil: use define for OSR default value
ASoC: fsl_micfil: Drop get_pdm_clk()
ASoC: fsl_micfil: simplify clock setting
ASoC: fsl_micfil: rework quality setting
ASoC: fsl_micfil: drop unused include
ASoC: fsl_micfil: drop only once used defines
ASoC: fsl_micfil: drop support for undocumented property
ASoC: fsl_micfil: fold fsl_set_clock_params() into its only user
drivers/dma/imx-sdma.c | 71 ++++-
include/linux/platform_data/dma-imx.h | 7 +
sound/soc/fsl/fsl_micfil.c | 368 +++++++++-----------------
sound/soc/fsl/fsl_micfil.h | 269 +++++--------------
4 files changed, 265 insertions(+), 450 deletions(-)
--
2.30.2
^ permalink raw reply [flat|nested] 48+ messages in thread
* [PATCH 01/19] ASoC: fsl_micfil: Drop unnecessary register read
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
in get_pdm_clk() REG_MICFIL_CTRL2 is read twice. Drop second read.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 9f90989ac59a6..64019d003784b 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -118,8 +118,6 @@ static inline int get_pdm_clk(struct fsl_micfil *micfil,
regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
>> MICFIL_CTRL2_CICOSR_SHIFT);
-
- regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
switch (qsel) {
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 01/19] ASoC: fsl_micfil: Drop unnecessary register read
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
in get_pdm_clk() REG_MICFIL_CTRL2 is read twice. Drop second read.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 2 --
1 file changed, 2 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 9f90989ac59a6..64019d003784b 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -118,8 +118,6 @@ static inline int get_pdm_clk(struct fsl_micfil *micfil,
regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
>> MICFIL_CTRL2_CICOSR_SHIFT);
-
- regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
switch (qsel) {
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 02/19] ASoC: fsl_micfil: Drop unused register read
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
In get_pdm_clk() REG_MICFIL_CTRL2 is read, but the result is never used.
Drop the unused code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 64019d003784b..cf10c212d770d 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -148,12 +148,9 @@ static inline int get_pdm_clk(struct fsl_micfil *micfil,
static inline int get_clk_div(struct fsl_micfil *micfil,
unsigned int rate)
{
- u32 ctrl2_reg;
long mclk_rate;
int clk_div;
- regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
-
mclk_rate = clk_get_rate(micfil->mclk);
clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 02/19] ASoC: fsl_micfil: Drop unused register read
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
In get_pdm_clk() REG_MICFIL_CTRL2 is read, but the result is never used.
Drop the unused code.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 3 ---
1 file changed, 3 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 64019d003784b..cf10c212d770d 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -148,12 +148,9 @@ static inline int get_pdm_clk(struct fsl_micfil *micfil,
static inline int get_clk_div(struct fsl_micfil *micfil,
unsigned int rate)
{
- u32 ctrl2_reg;
long mclk_rate;
int clk_div;
- regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
-
mclk_rate = clk_get_rate(micfil->mclk);
clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 03/19] ASoC: fsl_micfil: drop fsl_micfil_set_mclk_rate()
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
All that the .set_sysclk hook in the micfil driver does is to pass
the sysclk frequency to fsl_micfil_set_mclk_rate(). This function
expects the sample rate as argument though, not any kind of sysclk
frequency. The resulting rate setting of the clock is overwritten
in hw_params anyway, so drop this altogether.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 20 --------------------
1 file changed, 20 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index cf10c212d770d..5353474d0ff2b 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -358,30 +358,10 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
return 0;
}
-static int fsl_micfil_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
- unsigned int freq, int dir)
-{
- struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
- struct device *dev = &micfil->pdev->dev;
-
- int ret;
-
- if (!freq)
- return 0;
-
- ret = fsl_micfil_set_mclk_rate(micfil, freq);
- if (ret < 0)
- dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
- clk_get_rate(micfil->mclk), freq);
-
- return ret;
-}
-
static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
.startup = fsl_micfil_startup,
.trigger = fsl_micfil_trigger,
.hw_params = fsl_micfil_hw_params,
- .set_sysclk = fsl_micfil_set_dai_sysclk,
};
static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 03/19] ASoC: fsl_micfil: drop fsl_micfil_set_mclk_rate()
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
All that the .set_sysclk hook in the micfil driver does is to pass
the sysclk frequency to fsl_micfil_set_mclk_rate(). This function
expects the sample rate as argument though, not any kind of sysclk
frequency. The resulting rate setting of the clock is overwritten
in hw_params anyway, so drop this altogether.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 20 --------------------
1 file changed, 20 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index cf10c212d770d..5353474d0ff2b 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -358,30 +358,10 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
return 0;
}
-static int fsl_micfil_set_dai_sysclk(struct snd_soc_dai *dai, int clk_id,
- unsigned int freq, int dir)
-{
- struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
- struct device *dev = &micfil->pdev->dev;
-
- int ret;
-
- if (!freq)
- return 0;
-
- ret = fsl_micfil_set_mclk_rate(micfil, freq);
- if (ret < 0)
- dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
- clk_get_rate(micfil->mclk), freq);
-
- return ret;
-}
-
static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
.startup = fsl_micfil_startup,
.trigger = fsl_micfil_trigger,
.hw_params = fsl_micfil_hw_params,
- .set_sysclk = fsl_micfil_set_dai_sysclk,
};
static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 04/19] ASoC: fsl_micfil: do not define SHIFT/MASK for single bits
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
No need to have defines for the mask of single bits. Also shift is
unused. Drop all these unnecessary defines.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 18 +++---
sound/soc/fsl/fsl_micfil.h | 125 +++++++++----------------------------
2 files changed, 40 insertions(+), 103 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 5353474d0ff2b..878d24fde3581 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -170,7 +170,7 @@ static int fsl_micfil_reset(struct device *dev)
ret = regmap_update_bits(micfil->regmap,
REG_MICFIL_CTRL1,
- MICFIL_CTRL1_MDIS_MASK,
+ MICFIL_CTRL1_MDIS,
0);
if (ret) {
dev_err(dev, "failed to clear MDIS bit %d\n", ret);
@@ -179,7 +179,7 @@ static int fsl_micfil_reset(struct device *dev)
ret = regmap_update_bits(micfil->regmap,
REG_MICFIL_CTRL1,
- MICFIL_CTRL1_SRES_MASK,
+ MICFIL_CTRL1_SRES,
MICFIL_CTRL1_SRES);
if (ret) {
dev_err(dev, "failed to reset MICFIL: %d\n", ret);
@@ -253,7 +253,7 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
/* Enable the module */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_PDMIEN_MASK,
+ MICFIL_CTRL1_PDMIEN,
MICFIL_CTRL1_PDMIEN);
if (ret) {
dev_err(dev, "failed to enable the module\n");
@@ -266,7 +266,7 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
/* Disable the module */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_PDMIEN_MASK,
+ MICFIL_CTRL1_PDMIEN,
0);
if (ret) {
dev_err(dev, "failed to enable the module\n");
@@ -332,7 +332,7 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
/* 1. Disable the module */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_PDMIEN_MASK, 0);
+ MICFIL_CTRL1_PDMIEN, 0);
if (ret) {
dev_err(dev, "failed to disable the module\n");
return ret;
@@ -593,16 +593,16 @@ static irqreturn_t micfil_err_isr(int irq, void *devid)
regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
- if (stat_reg & MICFIL_STAT_BSY_FIL_MASK)
+ if (stat_reg & MICFIL_STAT_BSY_FIL)
dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
- if (stat_reg & MICFIL_STAT_FIR_RDY_MASK)
+ if (stat_reg & MICFIL_STAT_FIR_RDY)
dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
- if (stat_reg & MICFIL_STAT_LOWFREQF_MASK) {
+ if (stat_reg & MICFIL_STAT_LOWFREQF) {
dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
- MICFIL_STAT_LOWFREQF_MASK, 1);
+ MICFIL_STAT_LOWFREQF, 1);
}
return IRQ_HANDLED;
diff --git a/sound/soc/fsl/fsl_micfil.h b/sound/soc/fsl/fsl_micfil.h
index bac825c3135a0..11ccc08523b2e 100644
--- a/sound/soc/fsl/fsl_micfil.h
+++ b/sound/soc/fsl/fsl_micfil.h
@@ -33,33 +33,17 @@
#define REG_MICFIL_VAD0_ZCD 0xA8
/* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
-#define MICFIL_CTRL1_MDIS_SHIFT 31
-#define MICFIL_CTRL1_MDIS_MASK BIT(MICFIL_CTRL1_MDIS_SHIFT)
-#define MICFIL_CTRL1_MDIS BIT(MICFIL_CTRL1_MDIS_SHIFT)
-#define MICFIL_CTRL1_DOZEN_SHIFT 30
-#define MICFIL_CTRL1_DOZEN_MASK BIT(MICFIL_CTRL1_DOZEN_SHIFT)
-#define MICFIL_CTRL1_DOZEN BIT(MICFIL_CTRL1_DOZEN_SHIFT)
-#define MICFIL_CTRL1_PDMIEN_SHIFT 29
-#define MICFIL_CTRL1_PDMIEN_MASK BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
-#define MICFIL_CTRL1_PDMIEN BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
-#define MICFIL_CTRL1_DBG_SHIFT 28
-#define MICFIL_CTRL1_DBG_MASK BIT(MICFIL_CTRL1_DBG_SHIFT)
-#define MICFIL_CTRL1_DBG BIT(MICFIL_CTRL1_DBG_SHIFT)
-#define MICFIL_CTRL1_SRES_SHIFT 27
-#define MICFIL_CTRL1_SRES_MASK BIT(MICFIL_CTRL1_SRES_SHIFT)
-#define MICFIL_CTRL1_SRES BIT(MICFIL_CTRL1_SRES_SHIFT)
-#define MICFIL_CTRL1_DBGE_SHIFT 26
-#define MICFIL_CTRL1_DBGE_MASK BIT(MICFIL_CTRL1_DBGE_SHIFT)
-#define MICFIL_CTRL1_DBGE BIT(MICFIL_CTRL1_DBGE_SHIFT)
+#define MICFIL_CTRL1_MDIS BIT(31)
+#define MICFIL_CTRL1_DOZEN BIT(30)
+#define MICFIL_CTRL1_PDMIEN BIT(29)
+#define MICFIL_CTRL1_DBG BIT(28)
+#define MICFIL_CTRL1_SRES BIT(27)
+#define MICFIL_CTRL1_DBGE BIT(26)
#define MICFIL_CTRL1_DISEL_SHIFT 24
#define MICFIL_CTRL1_DISEL_WIDTH 2
#define MICFIL_CTRL1_DISEL_MASK ((BIT(MICFIL_CTRL1_DISEL_WIDTH) - 1) \
<< MICFIL_CTRL1_DISEL_SHIFT)
-#define MICFIL_CTRL1_DISEL(v) (((v) << MICFIL_CTRL1_DISEL_SHIFT) \
- & MICFIL_CTRL1_DISEL_MASK)
-#define MICFIL_CTRL1_ERREN_SHIFT 23
-#define MICFIL_CTRL1_ERREN_MASK BIT(MICFIL_CTRL1_ERREN_SHIFT)
-#define MICFIL_CTRL1_ERREN BIT(MICFIL_CTRL1_ERREN_SHIFT)
+#define MICFIL_CTRL1_ERREN BIT(23)
#define MICFIL_CTRL1_CHEN_SHIFT 0
#define MICFIL_CTRL1_CHEN_WIDTH 8
#define MICFIL_CTRL1_CHEN_MASK(x) (BIT(x) << MICFIL_CTRL1_CHEN_SHIFT)
@@ -91,15 +75,9 @@
& MICFIL_CTRL2_CLKDIV_MASK)
/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
-#define MICFIL_STAT_BSY_FIL_SHIFT 31
-#define MICFIL_STAT_BSY_FIL_MASK BIT(MICFIL_STAT_BSY_FIL_SHIFT)
-#define MICFIL_STAT_BSY_FIL BIT(MICFIL_STAT_BSY_FIL_SHIFT)
-#define MICFIL_STAT_FIR_RDY_SHIFT 30
-#define MICFIL_STAT_FIR_RDY_MASK BIT(MICFIL_STAT_FIR_RDY_SHIFT)
-#define MICFIL_STAT_FIR_RDY BIT(MICFIL_STAT_FIR_RDY_SHIFT)
-#define MICFIL_STAT_LOWFREQF_SHIFT 29
-#define MICFIL_STAT_LOWFREQF_MASK BIT(MICFIL_STAT_LOWFREQF_SHIFT)
-#define MICFIL_STAT_LOWFREQF BIT(MICFIL_STAT_LOWFREQF_SHIFT)
+#define MICFIL_STAT_BSY_FIL BIT(31)
+#define MICFIL_STAT_FIR_RDY BIT(30)
+#define MICFIL_STAT_LOWFREQF BIT(29)
#define MICFIL_STAT_CHXF_SHIFT(v) (v)
#define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
#define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
@@ -137,32 +115,16 @@
<< MICFIL_VAD0_CTRL1_INITT_SHIFT)
#define MICFIL_VAD0_CTRL1_INITT(v) (((v) << MICFIL_VAD0_CTRL1_INITT_SHIFT) \
& MICFIL_VAD0_CTRL1_INITT_MASK)
-#define MICFIL_VAD0_CTRL1_ST10_SHIFT 4
-#define MICFIL_VAD0_CTRL1_ST10_MASK BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT)
-#define MICFIL_VAD0_CTRL1_ST10 BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT)
-#define MICFIL_VAD0_CTRL1_ERIE_SHIFT 3
-#define MICFIL_VAD0_CTRL1_ERIE_MASK BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT)
-#define MICFIL_VAD0_CTRL1_ERIE BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT)
-#define MICFIL_VAD0_CTRL1_IE_SHIFT 2
-#define MICFIL_VAD0_CTRL1_IE_MASK BIT(MICFIL_VAD0_CTRL1_IE_SHIFT)
-#define MICFIL_VAD0_CTRL1_IE BIT(MICFIL_VAD0_CTRL1_IE_SHIFT)
-#define MICFIL_VAD0_CTRL1_RST_SHIFT 1
-#define MICFIL_VAD0_CTRL1_RST_MASK BIT(MICFIL_VAD0_CTRL1_RST_SHIFT)
-#define MICFIL_VAD0_CTRL1_RST BIT(MICFIL_VAD0_CTRL1_RST_SHIFT)
-#define MICFIL_VAD0_CTRL1_EN_SHIFT 0
-#define MICFIL_VAD0_CTRL1_EN_MASK BIT(MICFIL_VAD0_CTRL1_EN_SHIFT)
-#define MICFIL_VAD0_CTRL1_EN BIT(MICFIL_VAD0_CTRL1_EN_SHIFT)
+#define MICFIL_VAD0_CTRL1_ST10 BIT(4)
+#define MICFIL_VAD0_CTRL1_ERIE BIT(3)
+#define MICFIL_VAD0_CTRL1_IE BIT(2)
+#define MICFIL_VAD0_CTRL1_RST BIT(1)
+#define MICFIL_VAD0_CTRL1_EN BIT(0)
/* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
-#define MICFIL_VAD0_CTRL2_FRENDIS_SHIFT 31
-#define MICFIL_VAD0_CTRL2_FRENDIS_MASK BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT)
-#define MICFIL_VAD0_CTRL2_FRENDIS BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT)
-#define MICFIL_VAD0_CTRL2_PREFEN_SHIFT 30
-#define MICFIL_VAD0_CTRL2_PREFEN_MASK BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT)
-#define MICFIL_VAD0_CTRL2_PREFEN BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT)
-#define MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT 28
-#define MICFIL_VAD0_CTRL2_FOUTDIS_MASK BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT)
-#define MICFIL_VAD0_CTRL2_FOUTDIS BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT)
+#define MICFIL_VAD0_CTRL2_FRENDIS BIT(31)
+#define MICFIL_VAD0_CTRL2_PREFEN BIT(30)
+#define MICFIL_VAD0_CTRL2_FOUTDIS BIT(28)
#define MICFIL_VAD0_CTRL2_FRAMET_SHIFT 16
#define MICFIL_VAD0_CTRL2_FRAMET_WIDTH 6
#define MICFIL_VAD0_CTRL2_FRAMET_MASK ((BIT(MICFIL_VAD0_CTRL2_FRAMET_WIDTH) - 1) \
@@ -183,12 +145,8 @@
& MICFIL_VAD0_CTRL2_HPF_MASK)
/* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
-#define MICFIL_VAD0_SCONFIG_SFILEN_SHIFT 31
-#define MICFIL_VAD0_SCONFIG_SFILEN_MASK BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT)
-#define MICFIL_VAD0_SCONFIG_SFILEN BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT)
-#define MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT 30
-#define MICFIL_VAD0_SCONFIG_SMAXEN_MASK BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT)
-#define MICFIL_VAD0_SCONFIG_SMAXEN BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT)
+#define MICFIL_VAD0_SCONFIG_SFILEN BIT(31)
+#define MICFIL_VAD0_SCONFIG_SMAXEN BIT(30)
#define MICFIL_VAD0_SCONFIG_SGAIN_SHIFT 0
#define MICFIL_VAD0_SCONFIG_SGAIN_WIDTH 4
#define MICFIL_VAD0_SCONFIG_SGAIN_MASK ((BIT(MICFIL_VAD0_SCONFIG_SGAIN_WIDTH) - 1) \
@@ -197,17 +155,10 @@
& MICFIL_VAD0_SCONFIG_SGAIN_MASK)
/* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
-#define MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT 31
-#define MICFIL_VAD0_NCONFIG_NFILAUT_MASK BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NFILAUT BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NMINEN_SHIFT 30
-#define MICFIL_VAD0_NCONFIG_NMINEN_MASK BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NMINEN BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NDECEN_SHIFT 29
-#define MICFIL_VAD0_NCONFIG_NDECEN_MASK BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NDECEN BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NOREN_SHIFT 28
-#define MICFIL_VAD0_NCONFIG_NOREN BIT(MICFIL_VAD0_NCONFIG_NOREN_SHIFT)
+#define MICFIL_VAD0_NCONFIG_NFILAUT BIT(31)
+#define MICFIL_VAD0_NCONFIG_NMINEN BIT(30)
+#define MICFIL_VAD0_NCONFIG_NDECEN BIT(29)
+#define MICFIL_VAD0_NCONFIG_NOREN BIT(28)
#define MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT 8
#define MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH 5
#define MICFIL_VAD0_NCONFIG_NFILADJ_MASK ((BIT(MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH) - 1) \
@@ -234,29 +185,15 @@
<< MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)
#define MICFIL_VAD0_ZCD_ZCDADJ(v) (((v) << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)\
& MICFIL_VAD0_ZCD_ZCDADJ_MASK)
-#define MICFIL_VAD0_ZCD_ZCDAND_SHIFT 4
-#define MICFIL_VAD0_ZCD_ZCDAND_MASK BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT)
-#define MICFIL_VAD0_ZCD_ZCDAND BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT)
-#define MICFIL_VAD0_ZCD_ZCDAUT_SHIFT 2
-#define MICFIL_VAD0_ZCD_ZCDAUT_MASK BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT)
-#define MICFIL_VAD0_ZCD_ZCDAUT BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT)
-#define MICFIL_VAD0_ZCD_ZCDEN_SHIFT 0
-#define MICFIL_VAD0_ZCD_ZCDEN_MASK BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT)
-#define MICFIL_VAD0_ZCD_ZCDEN BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT)
+#define MICFIL_VAD0_ZCD_ZCDAND BIT(4)
+#define MICFIL_VAD0_ZCD_ZCDAUT BIT(2)
+#define MICFIL_VAD0_ZCD_ZCDEN BIT(0)
/* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
-#define MICFIL_VAD0_STAT_INITF_SHIFT 31
-#define MICFIL_VAD0_STAT_INITF_MASK BIT(MICFIL_VAD0_STAT_INITF_SHIFT)
-#define MICFIL_VAD0_STAT_INITF BIT(MICFIL_VAD0_STAT_INITF_SHIFT)
-#define MICFIL_VAD0_STAT_INSATF_SHIFT 16
-#define MICFIL_VAD0_STAT_INSATF_MASK BIT(MICFIL_VAD0_STAT_INSATF_SHIFT)
-#define MICFIL_VAD0_STAT_INSATF BIT(MICFIL_VAD0_STAT_INSATF_SHIFT)
-#define MICFIL_VAD0_STAT_EF_SHIFT 15
-#define MICFIL_VAD0_STAT_EF_MASK BIT(MICFIL_VAD0_STAT_EF_SHIFT)
-#define MICFIL_VAD0_STAT_EF BIT(MICFIL_VAD0_STAT_EF_SHIFT)
-#define MICFIL_VAD0_STAT_IF_SHIFT 0
-#define MICFIL_VAD0_STAT_IF_MASK BIT(MICFIL_VAD0_STAT_IF_SHIFT)
-#define MICFIL_VAD0_STAT_IF BIT(MICFIL_VAD0_STAT_IF_SHIFT)
+#define MICFIL_VAD0_STAT_INITF BIT(31)
+#define MICFIL_VAD0_STAT_INSATF BIT(16)
+#define MICFIL_VAD0_STAT_EF BIT(15)
+#define MICFIL_VAD0_STAT_IF BIT(0)
/* MICFIL Output Control Register */
#define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v))
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 04/19] ASoC: fsl_micfil: do not define SHIFT/MASK for single bits
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
No need to have defines for the mask of single bits. Also shift is
unused. Drop all these unnecessary defines.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 18 +++---
sound/soc/fsl/fsl_micfil.h | 125 +++++++++----------------------------
2 files changed, 40 insertions(+), 103 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 5353474d0ff2b..878d24fde3581 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -170,7 +170,7 @@ static int fsl_micfil_reset(struct device *dev)
ret = regmap_update_bits(micfil->regmap,
REG_MICFIL_CTRL1,
- MICFIL_CTRL1_MDIS_MASK,
+ MICFIL_CTRL1_MDIS,
0);
if (ret) {
dev_err(dev, "failed to clear MDIS bit %d\n", ret);
@@ -179,7 +179,7 @@ static int fsl_micfil_reset(struct device *dev)
ret = regmap_update_bits(micfil->regmap,
REG_MICFIL_CTRL1,
- MICFIL_CTRL1_SRES_MASK,
+ MICFIL_CTRL1_SRES,
MICFIL_CTRL1_SRES);
if (ret) {
dev_err(dev, "failed to reset MICFIL: %d\n", ret);
@@ -253,7 +253,7 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
/* Enable the module */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_PDMIEN_MASK,
+ MICFIL_CTRL1_PDMIEN,
MICFIL_CTRL1_PDMIEN);
if (ret) {
dev_err(dev, "failed to enable the module\n");
@@ -266,7 +266,7 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
/* Disable the module */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_PDMIEN_MASK,
+ MICFIL_CTRL1_PDMIEN,
0);
if (ret) {
dev_err(dev, "failed to enable the module\n");
@@ -332,7 +332,7 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
/* 1. Disable the module */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_PDMIEN_MASK, 0);
+ MICFIL_CTRL1_PDMIEN, 0);
if (ret) {
dev_err(dev, "failed to disable the module\n");
return ret;
@@ -593,16 +593,16 @@ static irqreturn_t micfil_err_isr(int irq, void *devid)
regmap_read(micfil->regmap, REG_MICFIL_STAT, &stat_reg);
- if (stat_reg & MICFIL_STAT_BSY_FIL_MASK)
+ if (stat_reg & MICFIL_STAT_BSY_FIL)
dev_dbg(&pdev->dev, "isr: Decimation Filter is running\n");
- if (stat_reg & MICFIL_STAT_FIR_RDY_MASK)
+ if (stat_reg & MICFIL_STAT_FIR_RDY)
dev_dbg(&pdev->dev, "isr: FIR Filter Data ready\n");
- if (stat_reg & MICFIL_STAT_LOWFREQF_MASK) {
+ if (stat_reg & MICFIL_STAT_LOWFREQF) {
dev_dbg(&pdev->dev, "isr: ipg_clk_app is too low\n");
regmap_write_bits(micfil->regmap, REG_MICFIL_STAT,
- MICFIL_STAT_LOWFREQF_MASK, 1);
+ MICFIL_STAT_LOWFREQF, 1);
}
return IRQ_HANDLED;
diff --git a/sound/soc/fsl/fsl_micfil.h b/sound/soc/fsl/fsl_micfil.h
index bac825c3135a0..11ccc08523b2e 100644
--- a/sound/soc/fsl/fsl_micfil.h
+++ b/sound/soc/fsl/fsl_micfil.h
@@ -33,33 +33,17 @@
#define REG_MICFIL_VAD0_ZCD 0xA8
/* MICFIL Control Register 1 -- REG_MICFILL_CTRL1 0x00 */
-#define MICFIL_CTRL1_MDIS_SHIFT 31
-#define MICFIL_CTRL1_MDIS_MASK BIT(MICFIL_CTRL1_MDIS_SHIFT)
-#define MICFIL_CTRL1_MDIS BIT(MICFIL_CTRL1_MDIS_SHIFT)
-#define MICFIL_CTRL1_DOZEN_SHIFT 30
-#define MICFIL_CTRL1_DOZEN_MASK BIT(MICFIL_CTRL1_DOZEN_SHIFT)
-#define MICFIL_CTRL1_DOZEN BIT(MICFIL_CTRL1_DOZEN_SHIFT)
-#define MICFIL_CTRL1_PDMIEN_SHIFT 29
-#define MICFIL_CTRL1_PDMIEN_MASK BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
-#define MICFIL_CTRL1_PDMIEN BIT(MICFIL_CTRL1_PDMIEN_SHIFT)
-#define MICFIL_CTRL1_DBG_SHIFT 28
-#define MICFIL_CTRL1_DBG_MASK BIT(MICFIL_CTRL1_DBG_SHIFT)
-#define MICFIL_CTRL1_DBG BIT(MICFIL_CTRL1_DBG_SHIFT)
-#define MICFIL_CTRL1_SRES_SHIFT 27
-#define MICFIL_CTRL1_SRES_MASK BIT(MICFIL_CTRL1_SRES_SHIFT)
-#define MICFIL_CTRL1_SRES BIT(MICFIL_CTRL1_SRES_SHIFT)
-#define MICFIL_CTRL1_DBGE_SHIFT 26
-#define MICFIL_CTRL1_DBGE_MASK BIT(MICFIL_CTRL1_DBGE_SHIFT)
-#define MICFIL_CTRL1_DBGE BIT(MICFIL_CTRL1_DBGE_SHIFT)
+#define MICFIL_CTRL1_MDIS BIT(31)
+#define MICFIL_CTRL1_DOZEN BIT(30)
+#define MICFIL_CTRL1_PDMIEN BIT(29)
+#define MICFIL_CTRL1_DBG BIT(28)
+#define MICFIL_CTRL1_SRES BIT(27)
+#define MICFIL_CTRL1_DBGE BIT(26)
#define MICFIL_CTRL1_DISEL_SHIFT 24
#define MICFIL_CTRL1_DISEL_WIDTH 2
#define MICFIL_CTRL1_DISEL_MASK ((BIT(MICFIL_CTRL1_DISEL_WIDTH) - 1) \
<< MICFIL_CTRL1_DISEL_SHIFT)
-#define MICFIL_CTRL1_DISEL(v) (((v) << MICFIL_CTRL1_DISEL_SHIFT) \
- & MICFIL_CTRL1_DISEL_MASK)
-#define MICFIL_CTRL1_ERREN_SHIFT 23
-#define MICFIL_CTRL1_ERREN_MASK BIT(MICFIL_CTRL1_ERREN_SHIFT)
-#define MICFIL_CTRL1_ERREN BIT(MICFIL_CTRL1_ERREN_SHIFT)
+#define MICFIL_CTRL1_ERREN BIT(23)
#define MICFIL_CTRL1_CHEN_SHIFT 0
#define MICFIL_CTRL1_CHEN_WIDTH 8
#define MICFIL_CTRL1_CHEN_MASK(x) (BIT(x) << MICFIL_CTRL1_CHEN_SHIFT)
@@ -91,15 +75,9 @@
& MICFIL_CTRL2_CLKDIV_MASK)
/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
-#define MICFIL_STAT_BSY_FIL_SHIFT 31
-#define MICFIL_STAT_BSY_FIL_MASK BIT(MICFIL_STAT_BSY_FIL_SHIFT)
-#define MICFIL_STAT_BSY_FIL BIT(MICFIL_STAT_BSY_FIL_SHIFT)
-#define MICFIL_STAT_FIR_RDY_SHIFT 30
-#define MICFIL_STAT_FIR_RDY_MASK BIT(MICFIL_STAT_FIR_RDY_SHIFT)
-#define MICFIL_STAT_FIR_RDY BIT(MICFIL_STAT_FIR_RDY_SHIFT)
-#define MICFIL_STAT_LOWFREQF_SHIFT 29
-#define MICFIL_STAT_LOWFREQF_MASK BIT(MICFIL_STAT_LOWFREQF_SHIFT)
-#define MICFIL_STAT_LOWFREQF BIT(MICFIL_STAT_LOWFREQF_SHIFT)
+#define MICFIL_STAT_BSY_FIL BIT(31)
+#define MICFIL_STAT_FIR_RDY BIT(30)
+#define MICFIL_STAT_LOWFREQF BIT(29)
#define MICFIL_STAT_CHXF_SHIFT(v) (v)
#define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
#define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
@@ -137,32 +115,16 @@
<< MICFIL_VAD0_CTRL1_INITT_SHIFT)
#define MICFIL_VAD0_CTRL1_INITT(v) (((v) << MICFIL_VAD0_CTRL1_INITT_SHIFT) \
& MICFIL_VAD0_CTRL1_INITT_MASK)
-#define MICFIL_VAD0_CTRL1_ST10_SHIFT 4
-#define MICFIL_VAD0_CTRL1_ST10_MASK BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT)
-#define MICFIL_VAD0_CTRL1_ST10 BIT(MICFIL_VAD0_CTRL1_ST10_SHIFT)
-#define MICFIL_VAD0_CTRL1_ERIE_SHIFT 3
-#define MICFIL_VAD0_CTRL1_ERIE_MASK BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT)
-#define MICFIL_VAD0_CTRL1_ERIE BIT(MICFIL_VAD0_CTRL1_ERIE_SHIFT)
-#define MICFIL_VAD0_CTRL1_IE_SHIFT 2
-#define MICFIL_VAD0_CTRL1_IE_MASK BIT(MICFIL_VAD0_CTRL1_IE_SHIFT)
-#define MICFIL_VAD0_CTRL1_IE BIT(MICFIL_VAD0_CTRL1_IE_SHIFT)
-#define MICFIL_VAD0_CTRL1_RST_SHIFT 1
-#define MICFIL_VAD0_CTRL1_RST_MASK BIT(MICFIL_VAD0_CTRL1_RST_SHIFT)
-#define MICFIL_VAD0_CTRL1_RST BIT(MICFIL_VAD0_CTRL1_RST_SHIFT)
-#define MICFIL_VAD0_CTRL1_EN_SHIFT 0
-#define MICFIL_VAD0_CTRL1_EN_MASK BIT(MICFIL_VAD0_CTRL1_EN_SHIFT)
-#define MICFIL_VAD0_CTRL1_EN BIT(MICFIL_VAD0_CTRL1_EN_SHIFT)
+#define MICFIL_VAD0_CTRL1_ST10 BIT(4)
+#define MICFIL_VAD0_CTRL1_ERIE BIT(3)
+#define MICFIL_VAD0_CTRL1_IE BIT(2)
+#define MICFIL_VAD0_CTRL1_RST BIT(1)
+#define MICFIL_VAD0_CTRL1_EN BIT(0)
/* MICFIL HWVAD0 Control 2 Register -- REG_MICFIL_VAD0_CTRL2*/
-#define MICFIL_VAD0_CTRL2_FRENDIS_SHIFT 31
-#define MICFIL_VAD0_CTRL2_FRENDIS_MASK BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT)
-#define MICFIL_VAD0_CTRL2_FRENDIS BIT(MICFIL_VAD0_CTRL2_FRENDIS_SHIFT)
-#define MICFIL_VAD0_CTRL2_PREFEN_SHIFT 30
-#define MICFIL_VAD0_CTRL2_PREFEN_MASK BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT)
-#define MICFIL_VAD0_CTRL2_PREFEN BIT(MICFIL_VAD0_CTRL2_PREFEN_SHIFT)
-#define MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT 28
-#define MICFIL_VAD0_CTRL2_FOUTDIS_MASK BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT)
-#define MICFIL_VAD0_CTRL2_FOUTDIS BIT(MICFIL_VAD0_CTRL2_FOUTDIS_SHIFT)
+#define MICFIL_VAD0_CTRL2_FRENDIS BIT(31)
+#define MICFIL_VAD0_CTRL2_PREFEN BIT(30)
+#define MICFIL_VAD0_CTRL2_FOUTDIS BIT(28)
#define MICFIL_VAD0_CTRL2_FRAMET_SHIFT 16
#define MICFIL_VAD0_CTRL2_FRAMET_WIDTH 6
#define MICFIL_VAD0_CTRL2_FRAMET_MASK ((BIT(MICFIL_VAD0_CTRL2_FRAMET_WIDTH) - 1) \
@@ -183,12 +145,8 @@
& MICFIL_VAD0_CTRL2_HPF_MASK)
/* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
-#define MICFIL_VAD0_SCONFIG_SFILEN_SHIFT 31
-#define MICFIL_VAD0_SCONFIG_SFILEN_MASK BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT)
-#define MICFIL_VAD0_SCONFIG_SFILEN BIT(MICFIL_VAD0_SCONFIG_SFILEN_SHIFT)
-#define MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT 30
-#define MICFIL_VAD0_SCONFIG_SMAXEN_MASK BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT)
-#define MICFIL_VAD0_SCONFIG_SMAXEN BIT(MICFIL_VAD0_SCONFIG_SMAXEN_SHIFT)
+#define MICFIL_VAD0_SCONFIG_SFILEN BIT(31)
+#define MICFIL_VAD0_SCONFIG_SMAXEN BIT(30)
#define MICFIL_VAD0_SCONFIG_SGAIN_SHIFT 0
#define MICFIL_VAD0_SCONFIG_SGAIN_WIDTH 4
#define MICFIL_VAD0_SCONFIG_SGAIN_MASK ((BIT(MICFIL_VAD0_SCONFIG_SGAIN_WIDTH) - 1) \
@@ -197,17 +155,10 @@
& MICFIL_VAD0_SCONFIG_SGAIN_MASK)
/* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
-#define MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT 31
-#define MICFIL_VAD0_NCONFIG_NFILAUT_MASK BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NFILAUT BIT(MICFIL_VAD0_NCONFIG_NFILAUT_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NMINEN_SHIFT 30
-#define MICFIL_VAD0_NCONFIG_NMINEN_MASK BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NMINEN BIT(MICFIL_VAD0_NCONFIG_NMINEN_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NDECEN_SHIFT 29
-#define MICFIL_VAD0_NCONFIG_NDECEN_MASK BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NDECEN BIT(MICFIL_VAD0_NCONFIG_NDECEN_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NOREN_SHIFT 28
-#define MICFIL_VAD0_NCONFIG_NOREN BIT(MICFIL_VAD0_NCONFIG_NOREN_SHIFT)
+#define MICFIL_VAD0_NCONFIG_NFILAUT BIT(31)
+#define MICFIL_VAD0_NCONFIG_NMINEN BIT(30)
+#define MICFIL_VAD0_NCONFIG_NDECEN BIT(29)
+#define MICFIL_VAD0_NCONFIG_NOREN BIT(28)
#define MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT 8
#define MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH 5
#define MICFIL_VAD0_NCONFIG_NFILADJ_MASK ((BIT(MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH) - 1) \
@@ -234,29 +185,15 @@
<< MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)
#define MICFIL_VAD0_ZCD_ZCDADJ(v) (((v) << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)\
& MICFIL_VAD0_ZCD_ZCDADJ_MASK)
-#define MICFIL_VAD0_ZCD_ZCDAND_SHIFT 4
-#define MICFIL_VAD0_ZCD_ZCDAND_MASK BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT)
-#define MICFIL_VAD0_ZCD_ZCDAND BIT(MICFIL_VAD0_ZCD_ZCDAND_SHIFT)
-#define MICFIL_VAD0_ZCD_ZCDAUT_SHIFT 2
-#define MICFIL_VAD0_ZCD_ZCDAUT_MASK BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT)
-#define MICFIL_VAD0_ZCD_ZCDAUT BIT(MICFIL_VAD0_ZCD_ZCDAUT_SHIFT)
-#define MICFIL_VAD0_ZCD_ZCDEN_SHIFT 0
-#define MICFIL_VAD0_ZCD_ZCDEN_MASK BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT)
-#define MICFIL_VAD0_ZCD_ZCDEN BIT(MICFIL_VAD0_ZCD_ZCDEN_SHIFT)
+#define MICFIL_VAD0_ZCD_ZCDAND BIT(4)
+#define MICFIL_VAD0_ZCD_ZCDAUT BIT(2)
+#define MICFIL_VAD0_ZCD_ZCDEN BIT(0)
/* MICFIL HWVAD0 Status Register - REG_MICFIL_VAD0_STAT */
-#define MICFIL_VAD0_STAT_INITF_SHIFT 31
-#define MICFIL_VAD0_STAT_INITF_MASK BIT(MICFIL_VAD0_STAT_INITF_SHIFT)
-#define MICFIL_VAD0_STAT_INITF BIT(MICFIL_VAD0_STAT_INITF_SHIFT)
-#define MICFIL_VAD0_STAT_INSATF_SHIFT 16
-#define MICFIL_VAD0_STAT_INSATF_MASK BIT(MICFIL_VAD0_STAT_INSATF_SHIFT)
-#define MICFIL_VAD0_STAT_INSATF BIT(MICFIL_VAD0_STAT_INSATF_SHIFT)
-#define MICFIL_VAD0_STAT_EF_SHIFT 15
-#define MICFIL_VAD0_STAT_EF_MASK BIT(MICFIL_VAD0_STAT_EF_SHIFT)
-#define MICFIL_VAD0_STAT_EF BIT(MICFIL_VAD0_STAT_EF_SHIFT)
-#define MICFIL_VAD0_STAT_IF_SHIFT 0
-#define MICFIL_VAD0_STAT_IF_MASK BIT(MICFIL_VAD0_STAT_IF_SHIFT)
-#define MICFIL_VAD0_STAT_IF BIT(MICFIL_VAD0_STAT_IF_SHIFT)
+#define MICFIL_VAD0_STAT_INITF BIT(31)
+#define MICFIL_VAD0_STAT_INSATF BIT(16)
+#define MICFIL_VAD0_STAT_EF BIT(15)
+#define MICFIL_VAD0_STAT_IF BIT(0)
/* MICFIL Output Control Register */
#define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v))
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 05/19] ASoC: fsl_micfil: use GENMASK to define register bit fields
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
Use GENMASK along with FIELD_PREP and FIELD_GET to access bitfields in
registers to straighten register access and to drop a lot of defines.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 51 +++++++------
sound/soc/fsl/fsl_micfil.h | 147 ++++++++-----------------------------
2 files changed, 57 insertions(+), 141 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 878d24fde3581..4a537cf17bad8 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -116,23 +116,22 @@ static inline int get_pdm_clk(struct fsl_micfil *micfil,
int bclk;
regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
- osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
- >> MICFIL_CTRL2_CICOSR_SHIFT);
- qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
+ osr = 16 - FIELD_GET(MICFIL_CTRL2_CICOSR, ctrl2_reg);
+ qsel = FIELD_GET(MICFIL_CTRL2_QSEL, ctrl2_reg);
switch (qsel) {
- case MICFIL_HIGH_QUALITY:
+ case MICFIL_QSEL_HIGH_QUALITY:
bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
break;
- case MICFIL_MEDIUM_QUALITY:
- case MICFIL_VLOW0_QUALITY:
+ case MICFIL_QSEL_MEDIUM_QUALITY:
+ case MICFIL_QSEL_VLOW0_QUALITY:
bclk = rate * 4 * osr * 1; /* kfactor = 1 */
break;
- case MICFIL_LOW_QUALITY:
- case MICFIL_VLOW1_QUALITY:
+ case MICFIL_QSEL_LOW_QUALITY:
+ case MICFIL_QSEL_VLOW1_QUALITY:
bclk = rate * 2 * osr * 2; /* kfactor = 2 */
break;
- case MICFIL_VLOW2_QUALITY:
+ case MICFIL_QSEL_VLOW2_QUALITY:
bclk = rate * osr * 4; /* kfactor = 4 */
break;
default:
@@ -244,8 +243,8 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
* 11 - reserved
*/
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_DISEL_MASK,
- (1 << MICFIL_CTRL1_DISEL_SHIFT));
+ MICFIL_CTRL1_DISEL,
+ FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
if (ret) {
dev_err(dev, "failed to update DISEL bits\n");
return ret;
@@ -274,8 +273,8 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
}
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_DISEL_MASK,
- (0 << MICFIL_CTRL1_DISEL_SHIFT));
+ MICFIL_CTRL1_DISEL,
+ FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
if (ret) {
dev_err(dev, "failed to update DISEL bits\n");
return ret;
@@ -300,8 +299,8 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
/* set CICOSR */
ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
- MICFIL_CTRL2_CICOSR_MASK,
- MICFIL_CTRL2_OSR_DEFAULT);
+ MICFIL_CTRL2_CICOSR,
+ FIELD_PREP(MICFIL_CTRL2_CICOSR, MICFIL_CTRL2_CICOSR_DEFAULT));
if (ret)
dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
REG_MICFIL_CTRL2);
@@ -312,7 +311,8 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
ret = -EINVAL;
ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
- MICFIL_CTRL2_CLKDIV_MASK, clk_div);
+ MICFIL_CTRL2_CLKDIV,
+ FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div));
if (ret)
dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
REG_MICFIL_CTRL2);
@@ -368,13 +368,13 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
struct device *dev = cpu_dai->dev;
- unsigned int val;
int ret;
int i;
/* set qsel to medium */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
- MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY);
+ MICFIL_CTRL2_QSEL,
+ FIELD_PREP(MICFIL_CTRL2_QSEL, MICFIL_QSEL_MEDIUM_QUALITY));
if (ret) {
dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
REG_MICFIL_CTRL2);
@@ -390,10 +390,9 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
&micfil->dma_params_rx);
/* FIFO Watermark Control - FIFOWMK*/
- val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1;
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
- MICFIL_FIFO_CTRL_FIFOWMK_MASK,
- val);
+ MICFIL_FIFO_CTRL_FIFOWMK,
+ FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
if (ret) {
dev_err(dev, "failed to set FIFOWMK\n");
return ret;
@@ -553,11 +552,11 @@ static irqreturn_t micfil_isr(int irq, void *devid)
regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
- dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg);
+ dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
/* Channel 0-7 Output Data Flags */
for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
- if (stat_reg & MICFIL_STAT_CHXF_MASK(i))
+ if (stat_reg & MICFIL_STAT_CHXF(i))
dev_dbg(&pdev->dev,
"Data available in Data Channel %d\n", i);
/* if DMA is not enabled, field must be written with 1
@@ -566,17 +565,17 @@ static irqreturn_t micfil_isr(int irq, void *devid)
if (!dma_enabled)
regmap_write_bits(micfil->regmap,
REG_MICFIL_STAT,
- MICFIL_STAT_CHXF_MASK(i),
+ MICFIL_STAT_CHXF(i),
1);
}
for (i = 0; i < MICFIL_FIFO_NUM; i++) {
- if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER_MASK(i))
+ if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
dev_dbg(&pdev->dev,
"FIFO Overflow Exception flag for channel %d\n",
i);
- if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(i))
+ if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
dev_dbg(&pdev->dev,
"FIFO Underflow Exception flag for channel %d\n",
i);
diff --git a/sound/soc/fsl/fsl_micfil.h b/sound/soc/fsl/fsl_micfil.h
index 11ccc08523b2e..5cecae2519795 100644
--- a/sound/soc/fsl/fsl_micfil.h
+++ b/sound/soc/fsl/fsl_micfil.h
@@ -39,82 +39,45 @@
#define MICFIL_CTRL1_DBG BIT(28)
#define MICFIL_CTRL1_SRES BIT(27)
#define MICFIL_CTRL1_DBGE BIT(26)
-#define MICFIL_CTRL1_DISEL_SHIFT 24
-#define MICFIL_CTRL1_DISEL_WIDTH 2
-#define MICFIL_CTRL1_DISEL_MASK ((BIT(MICFIL_CTRL1_DISEL_WIDTH) - 1) \
- << MICFIL_CTRL1_DISEL_SHIFT)
+
+#define MICFIL_CTRL1_DISEL_DISABLE 0
+#define MICFIL_CTRL1_DISEL_DMA 1
+#define MICFIL_CTRL1_DISEL_IRQ 2
+#define MICFIL_CTRL1_DISEL GENMASK(25, 24)
#define MICFIL_CTRL1_ERREN BIT(23)
-#define MICFIL_CTRL1_CHEN_SHIFT 0
-#define MICFIL_CTRL1_CHEN_WIDTH 8
-#define MICFIL_CTRL1_CHEN_MASK(x) (BIT(x) << MICFIL_CTRL1_CHEN_SHIFT)
-#define MICFIL_CTRL1_CHEN(x) (MICFIL_CTRL1_CHEN_MASK(x))
+#define MICFIL_CTRL1_CHEN(ch) BIT(ch)
/* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
#define MICFIL_CTRL2_QSEL_SHIFT 25
-#define MICFIL_CTRL2_QSEL_WIDTH 3
-#define MICFIL_CTRL2_QSEL_MASK ((BIT(MICFIL_CTRL2_QSEL_WIDTH) - 1) \
- << MICFIL_CTRL2_QSEL_SHIFT)
-#define MICFIL_HIGH_QUALITY BIT(MICFIL_CTRL2_QSEL_SHIFT)
-#define MICFIL_MEDIUM_QUALITY (0 << MICFIL_CTRL2_QSEL_SHIFT)
-#define MICFIL_LOW_QUALITY (7 << MICFIL_CTRL2_QSEL_SHIFT)
-#define MICFIL_VLOW0_QUALITY (6 << MICFIL_CTRL2_QSEL_SHIFT)
-#define MICFIL_VLOW1_QUALITY (5 << MICFIL_CTRL2_QSEL_SHIFT)
-#define MICFIL_VLOW2_QUALITY (4 << MICFIL_CTRL2_QSEL_SHIFT)
-
-#define MICFIL_CTRL2_CICOSR_SHIFT 16
-#define MICFIL_CTRL2_CICOSR_WIDTH 4
-#define MICFIL_CTRL2_CICOSR_MASK ((BIT(MICFIL_CTRL2_CICOSR_WIDTH) - 1) \
- << MICFIL_CTRL2_CICOSR_SHIFT)
-#define MICFIL_CTRL2_CICOSR(v) (((v) << MICFIL_CTRL2_CICOSR_SHIFT) \
- & MICFIL_CTRL2_CICOSR_MASK)
-#define MICFIL_CTRL2_CLKDIV_SHIFT 0
-#define MICFIL_CTRL2_CLKDIV_WIDTH 8
-#define MICFIL_CTRL2_CLKDIV_MASK ((BIT(MICFIL_CTRL2_CLKDIV_WIDTH) - 1) \
- << MICFIL_CTRL2_CLKDIV_SHIFT)
-#define MICFIL_CTRL2_CLKDIV(v) (((v) << MICFIL_CTRL2_CLKDIV_SHIFT) \
- & MICFIL_CTRL2_CLKDIV_MASK)
+#define MICFIL_CTRL2_QSEL GENMASK(27, 25)
+#define MICFIL_QSEL_MEDIUM_QUALITY 0
+#define MICFIL_QSEL_HIGH_QUALITY 1
+#define MICFIL_QSEL_LOW_QUALITY 7
+#define MICFIL_QSEL_VLOW0_QUALITY 6
+#define MICFIL_QSEL_VLOW1_QUALITY 5
+#define MICFIL_QSEL_VLOW2_QUALITY 4
+
+#define MICFIL_CTRL2_CICOSR GENMASK(19, 16)
+#define MICFIL_CTRL2_CICOSR_DEFAULT 0
+#define MICFIL_CTRL2_CLKDIV GENMASK(7, 0)
/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
#define MICFIL_STAT_BSY_FIL BIT(31)
#define MICFIL_STAT_FIR_RDY BIT(30)
#define MICFIL_STAT_LOWFREQF BIT(29)
-#define MICFIL_STAT_CHXF_SHIFT(v) (v)
-#define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
-#define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
+#define MICFIL_STAT_CHXF(ch) BIT(ch)
/* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
-#define MICFIL_FIFO_CTRL_FIFOWMK_SHIFT 0
-#define MICFIL_FIFO_CTRL_FIFOWMK_WIDTH 3
-#define MICFIL_FIFO_CTRL_FIFOWMK_MASK ((BIT(MICFIL_FIFO_CTRL_FIFOWMK_WIDTH) - 1) \
- << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT)
-#define MICFIL_FIFO_CTRL_FIFOWMK(v) (((v) << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) \
- & MICFIL_FIFO_CTRL_FIFOWMK_MASK)
+#define MICFIL_FIFO_CTRL_FIFOWMK GENMASK(2, 0)
/* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
-#define MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v) (v)
-#define MICFIL_FIFO_STAT_FIFOX_OVER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v))
-#define MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v) ((v) + 8)
-#define MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v))
+#define MICFIL_FIFO_STAT_FIFOX_OVER(ch) BIT(ch)
+#define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8)
/* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
-#define MICFIL_VAD0_CTRL1_CHSEL_SHIFT 24
-#define MICFIL_VAD0_CTRL1_CHSEL_WIDTH 3
-#define MICFIL_VAD0_CTRL1_CHSEL_MASK ((BIT(MICFIL_VAD0_CTRL1_CHSEL_WIDTH) - 1) \
- << MICFIL_VAD0_CTRL1_CHSEL_SHIFT)
-#define MICFIL_VAD0_CTRL1_CHSEL(v) (((v) << MICFIL_VAD0_CTRL1_CHSEL_SHIFT) \
- & MICFIL_VAD0_CTRL1_CHSEL_MASK)
-#define MICFIL_VAD0_CTRL1_CICOSR_SHIFT 16
-#define MICFIL_VAD0_CTRL1_CICOSR_WIDTH 4
-#define MICFIL_VAD0_CTRL1_CICOSR_MASK ((BIT(MICFIL_VAD0_CTRL1_CICOSR_WIDTH) - 1) \
- << MICFIL_VAD0_CTRL1_CICOSR_SHIFT)
-#define MICFIL_VAD0_CTRL1_CICOSR(v) (((v) << MICFIL_VAD0_CTRL1_CICOSR_SHIFT) \
- & MICFIL_VAD0_CTRL1_CICOSR_MASK)
-#define MICFIL_VAD0_CTRL1_INITT_SHIFT 8
-#define MICFIL_VAD0_CTRL1_INITT_WIDTH 5
-#define MICFIL_VAD0_CTRL1_INITT_MASK ((BIT(MICFIL_VAD0_CTRL1_INITT_WIDTH) - 1) \
- << MICFIL_VAD0_CTRL1_INITT_SHIFT)
-#define MICFIL_VAD0_CTRL1_INITT(v) (((v) << MICFIL_VAD0_CTRL1_INITT_SHIFT) \
- & MICFIL_VAD0_CTRL1_INITT_MASK)
+#define MICFIL_VAD0_CTRL1_CHSEL_SHIFT GENMASK(26, 24)
+#define MICFIL_VAD0_CTRL1_CICOSR_SHIFT GENMASK(19, 16)
+#define MICFIL_VAD0_CTRL1_INITT_SHIFT GENMASK(12, 8)
#define MICFIL_VAD0_CTRL1_ST10 BIT(4)
#define MICFIL_VAD0_CTRL1_ERIE BIT(3)
#define MICFIL_VAD0_CTRL1_IE BIT(2)
@@ -125,66 +88,26 @@
#define MICFIL_VAD0_CTRL2_FRENDIS BIT(31)
#define MICFIL_VAD0_CTRL2_PREFEN BIT(30)
#define MICFIL_VAD0_CTRL2_FOUTDIS BIT(28)
-#define MICFIL_VAD0_CTRL2_FRAMET_SHIFT 16
-#define MICFIL_VAD0_CTRL2_FRAMET_WIDTH 6
-#define MICFIL_VAD0_CTRL2_FRAMET_MASK ((BIT(MICFIL_VAD0_CTRL2_FRAMET_WIDTH) - 1) \
- << MICFIL_VAD0_CTRL2_FRAMET_SHIFT)
-#define MICFIL_VAD0_CTRL2_FRAMET(v) (((v) << MICFIL_VAD0_CTRL2_FRAMET_SHIFT) \
- & MICFIL_VAD0_CTRL2_FRAMET_MASK)
-#define MICFIL_VAD0_CTRL2_INPGAIN_SHIFT 8
-#define MICFIL_VAD0_CTRL2_INPGAIN_WIDTH 4
-#define MICFIL_VAD0_CTRL2_INPGAIN_MASK ((BIT(MICFIL_VAD0_CTRL2_INPGAIN_WIDTH) - 1) \
- << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT)
-#define MICFIL_VAD0_CTRL2_INPGAIN(v) (((v) << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT) \
- & MICFIL_VAD0_CTRL2_INPGAIN_MASK)
-#define MICFIL_VAD0_CTRL2_HPF_SHIFT 0
-#define MICFIL_VAD0_CTRL2_HPF_WIDTH 2
-#define MICFIL_VAD0_CTRL2_HPF_MASK ((BIT(MICFIL_VAD0_CTRL2_HPF_WIDTH) - 1) \
- << MICFIL_VAD0_CTRL2_HPF_SHIFT)
-#define MICFIL_VAD0_CTRL2_HPF(v) (((v) << MICFIL_VAD0_CTRL2_HPF_SHIFT) \
- & MICFIL_VAD0_CTRL2_HPF_MASK)
+#define MICFIL_VAD0_CTRL2_FRAMET GENMASK(21, 16)
+#define MICFIL_VAD0_CTRL2_INPGAIN GENMASK(11, 8)
+#define MICFIL_VAD0_CTRL2_HPF GENMASK(1, 0)
/* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
#define MICFIL_VAD0_SCONFIG_SFILEN BIT(31)
#define MICFIL_VAD0_SCONFIG_SMAXEN BIT(30)
-#define MICFIL_VAD0_SCONFIG_SGAIN_SHIFT 0
-#define MICFIL_VAD0_SCONFIG_SGAIN_WIDTH 4
-#define MICFIL_VAD0_SCONFIG_SGAIN_MASK ((BIT(MICFIL_VAD0_SCONFIG_SGAIN_WIDTH) - 1) \
- << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT)
-#define MICFIL_VAD0_SCONFIG_SGAIN(v) (((v) << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT) \
- & MICFIL_VAD0_SCONFIG_SGAIN_MASK)
+#define MICFIL_VAD0_SCONFIG_SGAIN GENMASK(3, 0)
/* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
#define MICFIL_VAD0_NCONFIG_NFILAUT BIT(31)
#define MICFIL_VAD0_NCONFIG_NMINEN BIT(30)
#define MICFIL_VAD0_NCONFIG_NDECEN BIT(29)
#define MICFIL_VAD0_NCONFIG_NOREN BIT(28)
-#define MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT 8
-#define MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH 5
-#define MICFIL_VAD0_NCONFIG_NFILADJ_MASK ((BIT(MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH) - 1) \
- << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NFILADJ(v) (((v) << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT) \
- & MICFIL_VAD0_NCONFIG_NFILADJ_MASK)
-#define MICFIL_VAD0_NCONFIG_NGAIN_SHIFT 0
-#define MICFIL_VAD0_NCONFIG_NGAIN_WIDTH 4
-#define MICFIL_VAD0_NCONFIG_NGAIN_MASK ((BIT(MICFIL_VAD0_NCONFIG_NGAIN_WIDTH) - 1) \
- << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NGAIN(v) (((v) << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT) \
- & MICFIL_VAD0_NCONFIG_NGAIN_MASK)
+#define MICFIL_VAD0_NCONFIG_NFILADJ GENMASK(12, 8)
+#define MICFIL_VAD0_NCONFIG_NGAIN GENMASK(3, 0)
/* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
-#define MICFIL_VAD0_ZCD_ZCDTH_SHIFT 16
-#define MICFIL_VAD0_ZCD_ZCDTH_WIDTH 10
-#define MICFIL_VAD0_ZCD_ZCDTH_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDTH_WIDTH) - 1) \
- << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)
-#define MICFIL_VAD0_ZCD_ZCDTH(v) (((v) << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)\
- & MICFIL_VAD0_ZCD_ZCDTH_MASK)
-#define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT 8
-#define MICFIL_VAD0_ZCD_ZCDADJ_WIDTH 4
-#define MICFIL_VAD0_ZCD_ZCDADJ_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDADJ_WIDTH) - 1)\
- << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)
-#define MICFIL_VAD0_ZCD_ZCDADJ(v) (((v) << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)\
- & MICFIL_VAD0_ZCD_ZCDADJ_MASK)
+#define MICFIL_VAD0_ZCD_ZCDTH GENMASK(25, 16)
+#define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT GENMASK(11, 8)
#define MICFIL_VAD0_ZCD_ZCDAND BIT(4)
#define MICFIL_VAD0_ZCD_ZCDAUT BIT(2)
#define MICFIL_VAD0_ZCD_ZCDEN BIT(0)
@@ -199,11 +122,6 @@
#define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v))
/* Constants */
-#define MICFIL_DMA_IRQ_DISABLED(v) ((v) & MICFIL_CTRL1_DISEL_MASK)
-#define MICFIL_DMA_ENABLED(v) ((0x1 << MICFIL_CTRL1_DISEL_SHIFT) \
- == ((v) & MICFIL_CTRL1_DISEL_MASK))
-#define MICFIL_IRQ_ENABLED(v) ((0x2 << MICFIL_CTRL1_DISEL_SHIFT) \
- == ((v) & MICFIL_CTRL1_DISEL_MASK))
#define MICFIL_OUTPUT_CHANNELS 8
#define MICFIL_FIFO_NUM 8
@@ -215,6 +133,5 @@
#define MICFIL_SLEEP_MIN 90000 /* in us */
#define MICFIL_SLEEP_MAX 100000 /* in us */
#define MICFIL_DMA_MAXBURST_RX 6
-#define MICFIL_CTRL2_OSR_DEFAULT (0 << MICFIL_CTRL2_CICOSR_SHIFT)
#endif /* _FSL_MICFIL_H */
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 05/19] ASoC: fsl_micfil: use GENMASK to define register bit fields
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
Use GENMASK along with FIELD_PREP and FIELD_GET to access bitfields in
registers to straighten register access and to drop a lot of defines.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 51 +++++++------
sound/soc/fsl/fsl_micfil.h | 147 ++++++++-----------------------------
2 files changed, 57 insertions(+), 141 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 878d24fde3581..4a537cf17bad8 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -116,23 +116,22 @@ static inline int get_pdm_clk(struct fsl_micfil *micfil,
int bclk;
regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
- osr = 16 - ((ctrl2_reg & MICFIL_CTRL2_CICOSR_MASK)
- >> MICFIL_CTRL2_CICOSR_SHIFT);
- qsel = ctrl2_reg & MICFIL_CTRL2_QSEL_MASK;
+ osr = 16 - FIELD_GET(MICFIL_CTRL2_CICOSR, ctrl2_reg);
+ qsel = FIELD_GET(MICFIL_CTRL2_QSEL, ctrl2_reg);
switch (qsel) {
- case MICFIL_HIGH_QUALITY:
+ case MICFIL_QSEL_HIGH_QUALITY:
bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
break;
- case MICFIL_MEDIUM_QUALITY:
- case MICFIL_VLOW0_QUALITY:
+ case MICFIL_QSEL_MEDIUM_QUALITY:
+ case MICFIL_QSEL_VLOW0_QUALITY:
bclk = rate * 4 * osr * 1; /* kfactor = 1 */
break;
- case MICFIL_LOW_QUALITY:
- case MICFIL_VLOW1_QUALITY:
+ case MICFIL_QSEL_LOW_QUALITY:
+ case MICFIL_QSEL_VLOW1_QUALITY:
bclk = rate * 2 * osr * 2; /* kfactor = 2 */
break;
- case MICFIL_VLOW2_QUALITY:
+ case MICFIL_QSEL_VLOW2_QUALITY:
bclk = rate * osr * 4; /* kfactor = 4 */
break;
default:
@@ -244,8 +243,8 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
* 11 - reserved
*/
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_DISEL_MASK,
- (1 << MICFIL_CTRL1_DISEL_SHIFT));
+ MICFIL_CTRL1_DISEL,
+ FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
if (ret) {
dev_err(dev, "failed to update DISEL bits\n");
return ret;
@@ -274,8 +273,8 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
}
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_DISEL_MASK,
- (0 << MICFIL_CTRL1_DISEL_SHIFT));
+ MICFIL_CTRL1_DISEL,
+ FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
if (ret) {
dev_err(dev, "failed to update DISEL bits\n");
return ret;
@@ -300,8 +299,8 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
/* set CICOSR */
ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
- MICFIL_CTRL2_CICOSR_MASK,
- MICFIL_CTRL2_OSR_DEFAULT);
+ MICFIL_CTRL2_CICOSR,
+ FIELD_PREP(MICFIL_CTRL2_CICOSR, MICFIL_CTRL2_CICOSR_DEFAULT));
if (ret)
dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
REG_MICFIL_CTRL2);
@@ -312,7 +311,8 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
ret = -EINVAL;
ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
- MICFIL_CTRL2_CLKDIV_MASK, clk_div);
+ MICFIL_CTRL2_CLKDIV,
+ FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div));
if (ret)
dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
REG_MICFIL_CTRL2);
@@ -368,13 +368,13 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
struct device *dev = cpu_dai->dev;
- unsigned int val;
int ret;
int i;
/* set qsel to medium */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
- MICFIL_CTRL2_QSEL_MASK, MICFIL_MEDIUM_QUALITY);
+ MICFIL_CTRL2_QSEL,
+ FIELD_PREP(MICFIL_CTRL2_QSEL, MICFIL_QSEL_MEDIUM_QUALITY));
if (ret) {
dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
REG_MICFIL_CTRL2);
@@ -390,10 +390,9 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
&micfil->dma_params_rx);
/* FIFO Watermark Control - FIFOWMK*/
- val = MICFIL_FIFO_CTRL_FIFOWMK(micfil->soc->fifo_depth) - 1;
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
- MICFIL_FIFO_CTRL_FIFOWMK_MASK,
- val);
+ MICFIL_FIFO_CTRL_FIFOWMK,
+ FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
if (ret) {
dev_err(dev, "failed to set FIFOWMK\n");
return ret;
@@ -553,11 +552,11 @@ static irqreturn_t micfil_isr(int irq, void *devid)
regmap_read(micfil->regmap, REG_MICFIL_CTRL1, &ctrl1_reg);
regmap_read(micfil->regmap, REG_MICFIL_FIFO_STAT, &fifo_stat_reg);
- dma_enabled = MICFIL_DMA_ENABLED(ctrl1_reg);
+ dma_enabled = FIELD_GET(MICFIL_CTRL1_DISEL, ctrl1_reg) == MICFIL_CTRL1_DISEL_DMA;
/* Channel 0-7 Output Data Flags */
for (i = 0; i < MICFIL_OUTPUT_CHANNELS; i++) {
- if (stat_reg & MICFIL_STAT_CHXF_MASK(i))
+ if (stat_reg & MICFIL_STAT_CHXF(i))
dev_dbg(&pdev->dev,
"Data available in Data Channel %d\n", i);
/* if DMA is not enabled, field must be written with 1
@@ -566,17 +565,17 @@ static irqreturn_t micfil_isr(int irq, void *devid)
if (!dma_enabled)
regmap_write_bits(micfil->regmap,
REG_MICFIL_STAT,
- MICFIL_STAT_CHXF_MASK(i),
+ MICFIL_STAT_CHXF(i),
1);
}
for (i = 0; i < MICFIL_FIFO_NUM; i++) {
- if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER_MASK(i))
+ if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_OVER(i))
dev_dbg(&pdev->dev,
"FIFO Overflow Exception flag for channel %d\n",
i);
- if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(i))
+ if (fifo_stat_reg & MICFIL_FIFO_STAT_FIFOX_UNDER(i))
dev_dbg(&pdev->dev,
"FIFO Underflow Exception flag for channel %d\n",
i);
diff --git a/sound/soc/fsl/fsl_micfil.h b/sound/soc/fsl/fsl_micfil.h
index 11ccc08523b2e..5cecae2519795 100644
--- a/sound/soc/fsl/fsl_micfil.h
+++ b/sound/soc/fsl/fsl_micfil.h
@@ -39,82 +39,45 @@
#define MICFIL_CTRL1_DBG BIT(28)
#define MICFIL_CTRL1_SRES BIT(27)
#define MICFIL_CTRL1_DBGE BIT(26)
-#define MICFIL_CTRL1_DISEL_SHIFT 24
-#define MICFIL_CTRL1_DISEL_WIDTH 2
-#define MICFIL_CTRL1_DISEL_MASK ((BIT(MICFIL_CTRL1_DISEL_WIDTH) - 1) \
- << MICFIL_CTRL1_DISEL_SHIFT)
+
+#define MICFIL_CTRL1_DISEL_DISABLE 0
+#define MICFIL_CTRL1_DISEL_DMA 1
+#define MICFIL_CTRL1_DISEL_IRQ 2
+#define MICFIL_CTRL1_DISEL GENMASK(25, 24)
#define MICFIL_CTRL1_ERREN BIT(23)
-#define MICFIL_CTRL1_CHEN_SHIFT 0
-#define MICFIL_CTRL1_CHEN_WIDTH 8
-#define MICFIL_CTRL1_CHEN_MASK(x) (BIT(x) << MICFIL_CTRL1_CHEN_SHIFT)
-#define MICFIL_CTRL1_CHEN(x) (MICFIL_CTRL1_CHEN_MASK(x))
+#define MICFIL_CTRL1_CHEN(ch) BIT(ch)
/* MICFIL Control Register 2 -- REG_MICFILL_CTRL2 0x04 */
#define MICFIL_CTRL2_QSEL_SHIFT 25
-#define MICFIL_CTRL2_QSEL_WIDTH 3
-#define MICFIL_CTRL2_QSEL_MASK ((BIT(MICFIL_CTRL2_QSEL_WIDTH) - 1) \
- << MICFIL_CTRL2_QSEL_SHIFT)
-#define MICFIL_HIGH_QUALITY BIT(MICFIL_CTRL2_QSEL_SHIFT)
-#define MICFIL_MEDIUM_QUALITY (0 << MICFIL_CTRL2_QSEL_SHIFT)
-#define MICFIL_LOW_QUALITY (7 << MICFIL_CTRL2_QSEL_SHIFT)
-#define MICFIL_VLOW0_QUALITY (6 << MICFIL_CTRL2_QSEL_SHIFT)
-#define MICFIL_VLOW1_QUALITY (5 << MICFIL_CTRL2_QSEL_SHIFT)
-#define MICFIL_VLOW2_QUALITY (4 << MICFIL_CTRL2_QSEL_SHIFT)
-
-#define MICFIL_CTRL2_CICOSR_SHIFT 16
-#define MICFIL_CTRL2_CICOSR_WIDTH 4
-#define MICFIL_CTRL2_CICOSR_MASK ((BIT(MICFIL_CTRL2_CICOSR_WIDTH) - 1) \
- << MICFIL_CTRL2_CICOSR_SHIFT)
-#define MICFIL_CTRL2_CICOSR(v) (((v) << MICFIL_CTRL2_CICOSR_SHIFT) \
- & MICFIL_CTRL2_CICOSR_MASK)
-#define MICFIL_CTRL2_CLKDIV_SHIFT 0
-#define MICFIL_CTRL2_CLKDIV_WIDTH 8
-#define MICFIL_CTRL2_CLKDIV_MASK ((BIT(MICFIL_CTRL2_CLKDIV_WIDTH) - 1) \
- << MICFIL_CTRL2_CLKDIV_SHIFT)
-#define MICFIL_CTRL2_CLKDIV(v) (((v) << MICFIL_CTRL2_CLKDIV_SHIFT) \
- & MICFIL_CTRL2_CLKDIV_MASK)
+#define MICFIL_CTRL2_QSEL GENMASK(27, 25)
+#define MICFIL_QSEL_MEDIUM_QUALITY 0
+#define MICFIL_QSEL_HIGH_QUALITY 1
+#define MICFIL_QSEL_LOW_QUALITY 7
+#define MICFIL_QSEL_VLOW0_QUALITY 6
+#define MICFIL_QSEL_VLOW1_QUALITY 5
+#define MICFIL_QSEL_VLOW2_QUALITY 4
+
+#define MICFIL_CTRL2_CICOSR GENMASK(19, 16)
+#define MICFIL_CTRL2_CICOSR_DEFAULT 0
+#define MICFIL_CTRL2_CLKDIV GENMASK(7, 0)
/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
#define MICFIL_STAT_BSY_FIL BIT(31)
#define MICFIL_STAT_FIR_RDY BIT(30)
#define MICFIL_STAT_LOWFREQF BIT(29)
-#define MICFIL_STAT_CHXF_SHIFT(v) (v)
-#define MICFIL_STAT_CHXF_MASK(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
-#define MICFIL_STAT_CHXF(v) BIT(MICFIL_STAT_CHXF_SHIFT(v))
+#define MICFIL_STAT_CHXF(ch) BIT(ch)
/* MICFIL FIFO Control Register -- REG_MICFIL_FIFO_CTRL 0x10 */
-#define MICFIL_FIFO_CTRL_FIFOWMK_SHIFT 0
-#define MICFIL_FIFO_CTRL_FIFOWMK_WIDTH 3
-#define MICFIL_FIFO_CTRL_FIFOWMK_MASK ((BIT(MICFIL_FIFO_CTRL_FIFOWMK_WIDTH) - 1) \
- << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT)
-#define MICFIL_FIFO_CTRL_FIFOWMK(v) (((v) << MICFIL_FIFO_CTRL_FIFOWMK_SHIFT) \
- & MICFIL_FIFO_CTRL_FIFOWMK_MASK)
+#define MICFIL_FIFO_CTRL_FIFOWMK GENMASK(2, 0)
/* MICFIL FIFO Status Register -- REG_MICFIL_FIFO_STAT 0x14 */
-#define MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v) (v)
-#define MICFIL_FIFO_STAT_FIFOX_OVER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_OVER_SHIFT(v))
-#define MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v) ((v) + 8)
-#define MICFIL_FIFO_STAT_FIFOX_UNDER_MASK(v) BIT(MICFIL_FIFO_STAT_FIFOX_UNDER_SHIFT(v))
+#define MICFIL_FIFO_STAT_FIFOX_OVER(ch) BIT(ch)
+#define MICFIL_FIFO_STAT_FIFOX_UNDER(ch) BIT((ch) + 8)
/* MICFIL HWVAD0 Control 1 Register -- REG_MICFIL_VAD0_CTRL1*/
-#define MICFIL_VAD0_CTRL1_CHSEL_SHIFT 24
-#define MICFIL_VAD0_CTRL1_CHSEL_WIDTH 3
-#define MICFIL_VAD0_CTRL1_CHSEL_MASK ((BIT(MICFIL_VAD0_CTRL1_CHSEL_WIDTH) - 1) \
- << MICFIL_VAD0_CTRL1_CHSEL_SHIFT)
-#define MICFIL_VAD0_CTRL1_CHSEL(v) (((v) << MICFIL_VAD0_CTRL1_CHSEL_SHIFT) \
- & MICFIL_VAD0_CTRL1_CHSEL_MASK)
-#define MICFIL_VAD0_CTRL1_CICOSR_SHIFT 16
-#define MICFIL_VAD0_CTRL1_CICOSR_WIDTH 4
-#define MICFIL_VAD0_CTRL1_CICOSR_MASK ((BIT(MICFIL_VAD0_CTRL1_CICOSR_WIDTH) - 1) \
- << MICFIL_VAD0_CTRL1_CICOSR_SHIFT)
-#define MICFIL_VAD0_CTRL1_CICOSR(v) (((v) << MICFIL_VAD0_CTRL1_CICOSR_SHIFT) \
- & MICFIL_VAD0_CTRL1_CICOSR_MASK)
-#define MICFIL_VAD0_CTRL1_INITT_SHIFT 8
-#define MICFIL_VAD0_CTRL1_INITT_WIDTH 5
-#define MICFIL_VAD0_CTRL1_INITT_MASK ((BIT(MICFIL_VAD0_CTRL1_INITT_WIDTH) - 1) \
- << MICFIL_VAD0_CTRL1_INITT_SHIFT)
-#define MICFIL_VAD0_CTRL1_INITT(v) (((v) << MICFIL_VAD0_CTRL1_INITT_SHIFT) \
- & MICFIL_VAD0_CTRL1_INITT_MASK)
+#define MICFIL_VAD0_CTRL1_CHSEL_SHIFT GENMASK(26, 24)
+#define MICFIL_VAD0_CTRL1_CICOSR_SHIFT GENMASK(19, 16)
+#define MICFIL_VAD0_CTRL1_INITT_SHIFT GENMASK(12, 8)
#define MICFIL_VAD0_CTRL1_ST10 BIT(4)
#define MICFIL_VAD0_CTRL1_ERIE BIT(3)
#define MICFIL_VAD0_CTRL1_IE BIT(2)
@@ -125,66 +88,26 @@
#define MICFIL_VAD0_CTRL2_FRENDIS BIT(31)
#define MICFIL_VAD0_CTRL2_PREFEN BIT(30)
#define MICFIL_VAD0_CTRL2_FOUTDIS BIT(28)
-#define MICFIL_VAD0_CTRL2_FRAMET_SHIFT 16
-#define MICFIL_VAD0_CTRL2_FRAMET_WIDTH 6
-#define MICFIL_VAD0_CTRL2_FRAMET_MASK ((BIT(MICFIL_VAD0_CTRL2_FRAMET_WIDTH) - 1) \
- << MICFIL_VAD0_CTRL2_FRAMET_SHIFT)
-#define MICFIL_VAD0_CTRL2_FRAMET(v) (((v) << MICFIL_VAD0_CTRL2_FRAMET_SHIFT) \
- & MICFIL_VAD0_CTRL2_FRAMET_MASK)
-#define MICFIL_VAD0_CTRL2_INPGAIN_SHIFT 8
-#define MICFIL_VAD0_CTRL2_INPGAIN_WIDTH 4
-#define MICFIL_VAD0_CTRL2_INPGAIN_MASK ((BIT(MICFIL_VAD0_CTRL2_INPGAIN_WIDTH) - 1) \
- << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT)
-#define MICFIL_VAD0_CTRL2_INPGAIN(v) (((v) << MICFIL_VAD0_CTRL2_INPGAIN_SHIFT) \
- & MICFIL_VAD0_CTRL2_INPGAIN_MASK)
-#define MICFIL_VAD0_CTRL2_HPF_SHIFT 0
-#define MICFIL_VAD0_CTRL2_HPF_WIDTH 2
-#define MICFIL_VAD0_CTRL2_HPF_MASK ((BIT(MICFIL_VAD0_CTRL2_HPF_WIDTH) - 1) \
- << MICFIL_VAD0_CTRL2_HPF_SHIFT)
-#define MICFIL_VAD0_CTRL2_HPF(v) (((v) << MICFIL_VAD0_CTRL2_HPF_SHIFT) \
- & MICFIL_VAD0_CTRL2_HPF_MASK)
+#define MICFIL_VAD0_CTRL2_FRAMET GENMASK(21, 16)
+#define MICFIL_VAD0_CTRL2_INPGAIN GENMASK(11, 8)
+#define MICFIL_VAD0_CTRL2_HPF GENMASK(1, 0)
/* MICFIL HWVAD0 Signal CONFIG Register -- REG_MICFIL_VAD0_SCONFIG */
#define MICFIL_VAD0_SCONFIG_SFILEN BIT(31)
#define MICFIL_VAD0_SCONFIG_SMAXEN BIT(30)
-#define MICFIL_VAD0_SCONFIG_SGAIN_SHIFT 0
-#define MICFIL_VAD0_SCONFIG_SGAIN_WIDTH 4
-#define MICFIL_VAD0_SCONFIG_SGAIN_MASK ((BIT(MICFIL_VAD0_SCONFIG_SGAIN_WIDTH) - 1) \
- << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT)
-#define MICFIL_VAD0_SCONFIG_SGAIN(v) (((v) << MICFIL_VAD0_SCONFIG_SGAIN_SHIFT) \
- & MICFIL_VAD0_SCONFIG_SGAIN_MASK)
+#define MICFIL_VAD0_SCONFIG_SGAIN GENMASK(3, 0)
/* MICFIL HWVAD0 Noise CONFIG Register -- REG_MICFIL_VAD0_NCONFIG */
#define MICFIL_VAD0_NCONFIG_NFILAUT BIT(31)
#define MICFIL_VAD0_NCONFIG_NMINEN BIT(30)
#define MICFIL_VAD0_NCONFIG_NDECEN BIT(29)
#define MICFIL_VAD0_NCONFIG_NOREN BIT(28)
-#define MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT 8
-#define MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH 5
-#define MICFIL_VAD0_NCONFIG_NFILADJ_MASK ((BIT(MICFIL_VAD0_NCONFIG_NFILADJ_WIDTH) - 1) \
- << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NFILADJ(v) (((v) << MICFIL_VAD0_NCONFIG_NFILADJ_SHIFT) \
- & MICFIL_VAD0_NCONFIG_NFILADJ_MASK)
-#define MICFIL_VAD0_NCONFIG_NGAIN_SHIFT 0
-#define MICFIL_VAD0_NCONFIG_NGAIN_WIDTH 4
-#define MICFIL_VAD0_NCONFIG_NGAIN_MASK ((BIT(MICFIL_VAD0_NCONFIG_NGAIN_WIDTH) - 1) \
- << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT)
-#define MICFIL_VAD0_NCONFIG_NGAIN(v) (((v) << MICFIL_VAD0_NCONFIG_NGAIN_SHIFT) \
- & MICFIL_VAD0_NCONFIG_NGAIN_MASK)
+#define MICFIL_VAD0_NCONFIG_NFILADJ GENMASK(12, 8)
+#define MICFIL_VAD0_NCONFIG_NGAIN GENMASK(3, 0)
/* MICFIL HWVAD0 Zero-Crossing Detector - REG_MICFIL_VAD0_ZCD */
-#define MICFIL_VAD0_ZCD_ZCDTH_SHIFT 16
-#define MICFIL_VAD0_ZCD_ZCDTH_WIDTH 10
-#define MICFIL_VAD0_ZCD_ZCDTH_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDTH_WIDTH) - 1) \
- << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)
-#define MICFIL_VAD0_ZCD_ZCDTH(v) (((v) << MICFIL_VAD0_ZCD_ZCDTH_SHIFT)\
- & MICFIL_VAD0_ZCD_ZCDTH_MASK)
-#define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT 8
-#define MICFIL_VAD0_ZCD_ZCDADJ_WIDTH 4
-#define MICFIL_VAD0_ZCD_ZCDADJ_MASK ((BIT(MICFIL_VAD0_ZCD_ZCDADJ_WIDTH) - 1)\
- << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)
-#define MICFIL_VAD0_ZCD_ZCDADJ(v) (((v) << MICFIL_VAD0_ZCD_ZCDADJ_SHIFT)\
- & MICFIL_VAD0_ZCD_ZCDADJ_MASK)
+#define MICFIL_VAD0_ZCD_ZCDTH GENMASK(25, 16)
+#define MICFIL_VAD0_ZCD_ZCDADJ_SHIFT GENMASK(11, 8)
#define MICFIL_VAD0_ZCD_ZCDAND BIT(4)
#define MICFIL_VAD0_ZCD_ZCDAUT BIT(2)
#define MICFIL_VAD0_ZCD_ZCDEN BIT(0)
@@ -199,11 +122,6 @@
#define MICFIL_OUTGAIN_CHX_SHIFT(v) (4 * (v))
/* Constants */
-#define MICFIL_DMA_IRQ_DISABLED(v) ((v) & MICFIL_CTRL1_DISEL_MASK)
-#define MICFIL_DMA_ENABLED(v) ((0x1 << MICFIL_CTRL1_DISEL_SHIFT) \
- == ((v) & MICFIL_CTRL1_DISEL_MASK))
-#define MICFIL_IRQ_ENABLED(v) ((0x2 << MICFIL_CTRL1_DISEL_SHIFT) \
- == ((v) & MICFIL_CTRL1_DISEL_MASK))
#define MICFIL_OUTPUT_CHANNELS 8
#define MICFIL_FIFO_NUM 8
@@ -215,6 +133,5 @@
#define MICFIL_SLEEP_MIN 90000 /* in us */
#define MICFIL_SLEEP_MAX 100000 /* in us */
#define MICFIL_DMA_MAXBURST_RX 6
-#define MICFIL_CTRL2_OSR_DEFAULT (0 << MICFIL_CTRL2_CICOSR_SHIFT)
#endif /* _FSL_MICFIL_H */
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 06/19] ASoC: fsl_micfil: use clear/set bits
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
Instead regmap_update_bits() use the simpler variants
regmap_[set|clear]_bits() where appropriate.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 26 ++++++++++----------------
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 4a537cf17bad8..9314f31f950c6 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -167,19 +167,15 @@ static int fsl_micfil_reset(struct device *dev)
struct fsl_micfil *micfil = dev_get_drvdata(dev);
int ret;
- ret = regmap_update_bits(micfil->regmap,
- REG_MICFIL_CTRL1,
- MICFIL_CTRL1_MDIS,
- 0);
+ ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
+ MICFIL_CTRL1_MDIS);
if (ret) {
dev_err(dev, "failed to clear MDIS bit %d\n", ret);
return ret;
}
- ret = regmap_update_bits(micfil->regmap,
- REG_MICFIL_CTRL1,
- MICFIL_CTRL1_SRES,
- MICFIL_CTRL1_SRES);
+ ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
+ MICFIL_CTRL1_SRES);
if (ret) {
dev_err(dev, "failed to reset MICFIL: %d\n", ret);
return ret;
@@ -251,9 +247,8 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
}
/* Enable the module */
- ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_PDMIEN,
- MICFIL_CTRL1_PDMIEN);
+ ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
+ MICFIL_CTRL1_PDMIEN);
if (ret) {
dev_err(dev, "failed to enable the module\n");
return ret;
@@ -264,9 +259,8 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
/* Disable the module */
- ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_PDMIEN,
- 0);
+ ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
+ MICFIL_CTRL1_PDMIEN);
if (ret) {
dev_err(dev, "failed to enable the module\n");
return ret;
@@ -331,8 +325,8 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
int ret;
/* 1. Disable the module */
- ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_PDMIEN, 0);
+ ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
+ MICFIL_CTRL1_PDMIEN);
if (ret) {
dev_err(dev, "failed to disable the module\n");
return ret;
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 06/19] ASoC: fsl_micfil: use clear/set bits
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
Instead regmap_update_bits() use the simpler variants
regmap_[set|clear]_bits() where appropriate.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 26 ++++++++++----------------
1 file changed, 10 insertions(+), 16 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 4a537cf17bad8..9314f31f950c6 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -167,19 +167,15 @@ static int fsl_micfil_reset(struct device *dev)
struct fsl_micfil *micfil = dev_get_drvdata(dev);
int ret;
- ret = regmap_update_bits(micfil->regmap,
- REG_MICFIL_CTRL1,
- MICFIL_CTRL1_MDIS,
- 0);
+ ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
+ MICFIL_CTRL1_MDIS);
if (ret) {
dev_err(dev, "failed to clear MDIS bit %d\n", ret);
return ret;
}
- ret = regmap_update_bits(micfil->regmap,
- REG_MICFIL_CTRL1,
- MICFIL_CTRL1_SRES,
- MICFIL_CTRL1_SRES);
+ ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
+ MICFIL_CTRL1_SRES);
if (ret) {
dev_err(dev, "failed to reset MICFIL: %d\n", ret);
return ret;
@@ -251,9 +247,8 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
}
/* Enable the module */
- ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_PDMIEN,
- MICFIL_CTRL1_PDMIEN);
+ ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
+ MICFIL_CTRL1_PDMIEN);
if (ret) {
dev_err(dev, "failed to enable the module\n");
return ret;
@@ -264,9 +259,8 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
case SNDRV_PCM_TRIGGER_SUSPEND:
case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
/* Disable the module */
- ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_PDMIEN,
- 0);
+ ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
+ MICFIL_CTRL1_PDMIEN);
if (ret) {
dev_err(dev, "failed to enable the module\n");
return ret;
@@ -331,8 +325,8 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
int ret;
/* 1. Disable the module */
- ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
- MICFIL_CTRL1_PDMIEN, 0);
+ ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
+ MICFIL_CTRL1_PDMIEN);
if (ret) {
dev_err(dev, "failed to disable the module\n");
return ret;
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 07/19] ASoC: fsl_micfil: drop error messages from failed register accesses
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
Failed register accesses are really not expected in memory mapped
registers. When it fails then the register access itself is likely not
the reason, so no need to have extra error messages for each regmap
access. Just drop the error messages. This also fixes some places where
a return value is concatenated using 'ret |=' and then returned as
error value.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 53 ++++++++++----------------------------
1 file changed, 13 insertions(+), 40 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 9314f31f950c6..61f45d72a857b 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -169,17 +169,13 @@ static int fsl_micfil_reset(struct device *dev)
ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_MDIS);
- if (ret) {
- dev_err(dev, "failed to clear MDIS bit %d\n", ret);
+ if (ret)
return ret;
- }
ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_SRES);
- if (ret) {
- dev_err(dev, "failed to reset MICFIL: %d\n", ret);
+ if (ret)
return ret;
- }
return 0;
}
@@ -241,18 +237,14 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_DISEL,
FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
- if (ret) {
- dev_err(dev, "failed to update DISEL bits\n");
+ if (ret)
return ret;
- }
/* Enable the module */
ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_PDMIEN);
- if (ret) {
- dev_err(dev, "failed to enable the module\n");
+ if (ret)
return ret;
- }
break;
case SNDRV_PCM_TRIGGER_STOP:
@@ -261,18 +253,14 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
/* Disable the module */
ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_PDMIEN);
- if (ret) {
- dev_err(dev, "failed to enable the module\n");
+ if (ret)
return ret;
- }
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_DISEL,
FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
- if (ret) {
- dev_err(dev, "failed to update DISEL bits\n");
+ if (ret)
return ret;
- }
break;
default:
return -EINVAL;
@@ -292,24 +280,20 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
clk_get_rate(micfil->mclk), rate);
/* set CICOSR */
- ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
+ ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_CICOSR,
FIELD_PREP(MICFIL_CTRL2_CICOSR, MICFIL_CTRL2_CICOSR_DEFAULT));
if (ret)
- dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
- REG_MICFIL_CTRL2);
+ return ret;
/* set CLK_DIV */
clk_div = get_clk_div(micfil, rate);
if (clk_div < 0)
ret = -EINVAL;
- ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
+ ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_CLKDIV,
FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div));
- if (ret)
- dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
- REG_MICFIL_CTRL2);
return ret;
}
@@ -327,19 +311,14 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
/* 1. Disable the module */
ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_PDMIEN);
- if (ret) {
- dev_err(dev, "failed to disable the module\n");
+ if (ret)
return ret;
- }
/* enable channels */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
0xFF, ((1 << channels) - 1));
- if (ret) {
- dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret,
- REG_MICFIL_CTRL1);
+ if (ret)
return ret;
- }
ret = fsl_set_clock_params(dev, rate);
if (ret < 0) {
@@ -361,7 +340,6 @@ static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
- struct device *dev = cpu_dai->dev;
int ret;
int i;
@@ -369,11 +347,8 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_QSEL,
FIELD_PREP(MICFIL_CTRL2_QSEL, MICFIL_QSEL_MEDIUM_QUALITY));
- if (ret) {
- dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
- REG_MICFIL_CTRL2);
+ if (ret)
return ret;
- }
/* set default gain to max_gain */
regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
@@ -387,10 +362,8 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
MICFIL_FIFO_CTRL_FIFOWMK,
FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
- if (ret) {
- dev_err(dev, "failed to set FIFOWMK\n");
+ if (ret)
return ret;
- }
return 0;
}
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 07/19] ASoC: fsl_micfil: drop error messages from failed register accesses
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
Failed register accesses are really not expected in memory mapped
registers. When it fails then the register access itself is likely not
the reason, so no need to have extra error messages for each regmap
access. Just drop the error messages. This also fixes some places where
a return value is concatenated using 'ret |=' and then returned as
error value.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 53 ++++++++++----------------------------
1 file changed, 13 insertions(+), 40 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 9314f31f950c6..61f45d72a857b 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -169,17 +169,13 @@ static int fsl_micfil_reset(struct device *dev)
ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_MDIS);
- if (ret) {
- dev_err(dev, "failed to clear MDIS bit %d\n", ret);
+ if (ret)
return ret;
- }
ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_SRES);
- if (ret) {
- dev_err(dev, "failed to reset MICFIL: %d\n", ret);
+ if (ret)
return ret;
- }
return 0;
}
@@ -241,18 +237,14 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_DISEL,
FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
- if (ret) {
- dev_err(dev, "failed to update DISEL bits\n");
+ if (ret)
return ret;
- }
/* Enable the module */
ret = regmap_set_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_PDMIEN);
- if (ret) {
- dev_err(dev, "failed to enable the module\n");
+ if (ret)
return ret;
- }
break;
case SNDRV_PCM_TRIGGER_STOP:
@@ -261,18 +253,14 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
/* Disable the module */
ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_PDMIEN);
- if (ret) {
- dev_err(dev, "failed to enable the module\n");
+ if (ret)
return ret;
- }
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_DISEL,
FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
- if (ret) {
- dev_err(dev, "failed to update DISEL bits\n");
+ if (ret)
return ret;
- }
break;
default:
return -EINVAL;
@@ -292,24 +280,20 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
clk_get_rate(micfil->mclk), rate);
/* set CICOSR */
- ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
+ ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_CICOSR,
FIELD_PREP(MICFIL_CTRL2_CICOSR, MICFIL_CTRL2_CICOSR_DEFAULT));
if (ret)
- dev_err(dev, "failed to set CICOSR in reg 0x%X\n",
- REG_MICFIL_CTRL2);
+ return ret;
/* set CLK_DIV */
clk_div = get_clk_div(micfil, rate);
if (clk_div < 0)
ret = -EINVAL;
- ret |= regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
+ ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_CLKDIV,
FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div));
- if (ret)
- dev_err(dev, "failed to set CLKDIV in reg 0x%X\n",
- REG_MICFIL_CTRL2);
return ret;
}
@@ -327,19 +311,14 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
/* 1. Disable the module */
ret = regmap_clear_bits(micfil->regmap, REG_MICFIL_CTRL1,
MICFIL_CTRL1_PDMIEN);
- if (ret) {
- dev_err(dev, "failed to disable the module\n");
+ if (ret)
return ret;
- }
/* enable channels */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
0xFF, ((1 << channels) - 1));
- if (ret) {
- dev_err(dev, "failed to enable channels %d, reg 0x%X\n", ret,
- REG_MICFIL_CTRL1);
+ if (ret)
return ret;
- }
ret = fsl_set_clock_params(dev, rate);
if (ret < 0) {
@@ -361,7 +340,6 @@ static const struct snd_soc_dai_ops fsl_micfil_dai_ops = {
static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
- struct device *dev = cpu_dai->dev;
int ret;
int i;
@@ -369,11 +347,8 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_QSEL,
FIELD_PREP(MICFIL_CTRL2_QSEL, MICFIL_QSEL_MEDIUM_QUALITY));
- if (ret) {
- dev_err(dev, "failed to set quality mode bits, reg 0x%X\n",
- REG_MICFIL_CTRL2);
+ if (ret)
return ret;
- }
/* set default gain to max_gain */
regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
@@ -387,10 +362,8 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_FIFO_CTRL,
MICFIL_FIFO_CTRL_FIFOWMK,
FIELD_PREP(MICFIL_FIFO_CTRL_FIFOWMK, micfil->soc->fifo_depth - 1));
- if (ret) {
- dev_err(dev, "failed to set FIFOWMK\n");
+ if (ret)
return ret;
- }
return 0;
}
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 08/19] ASoC: fsl_micfil: drop unused variables
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 61f45d72a857b..82b8fc83fd361 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -37,10 +37,7 @@ struct fsl_micfil {
unsigned int dataline;
char name[32];
int irq[MICFIL_IRQ_LINES];
- unsigned int mclk_streams;
int quality; /*QUALITY 2-0 bits */
- bool slave_mode;
- int channel_gain[8];
};
struct fsl_micfil_soc_data {
@@ -341,7 +338,6 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
int ret;
- int i;
/* set qsel to medium */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
@@ -352,8 +348,6 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
/* set default gain to max_gain */
regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
- for (i = 0; i < 8; i++)
- micfil->channel_gain[i] = 0xF;
snd_soc_dai_init_dma_data(cpu_dai, NULL,
&micfil->dma_params_rx);
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 08/19] ASoC: fsl_micfil: drop unused variables
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 6 ------
1 file changed, 6 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 61f45d72a857b..82b8fc83fd361 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -37,10 +37,7 @@ struct fsl_micfil {
unsigned int dataline;
char name[32];
int irq[MICFIL_IRQ_LINES];
- unsigned int mclk_streams;
int quality; /*QUALITY 2-0 bits */
- bool slave_mode;
- int channel_gain[8];
};
struct fsl_micfil_soc_data {
@@ -341,7 +338,6 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
{
struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
int ret;
- int i;
/* set qsel to medium */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
@@ -352,8 +348,6 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
/* set default gain to max_gain */
regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
- for (i = 0; i < 8; i++)
- micfil->channel_gain[i] = 0xF;
snd_soc_dai_init_dma_data(cpu_dai, NULL,
&micfil->dma_params_rx);
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 09/19] dma: imx-sdma: error out on unsupported transfer types
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
The i.MX SDMA driver currently silently ignores unsupported transfer
types. These transfer types are specified in the dma channel description
in the device tree, so they should really be checked.
Issue a message and error out when we hit unsupported transfer types.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/dma/imx-sdma.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 75ec0754d4ad4..1038f6bc7f846 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -924,7 +924,7 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
/*
* sets the pc of SDMA script according to the peripheral type
*/
-static void sdma_get_pc(struct sdma_channel *sdmac,
+static int sdma_get_pc(struct sdma_channel *sdmac,
enum sdma_peripheral_type peripheral_type)
{
struct sdma_engine *sdma = sdmac->sdma;
@@ -1023,13 +1023,17 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
break;
default:
- break;
+ dev_err(sdma->dev, "Unsupported transfer type %d\n",
+ peripheral_type);
+ return -EINVAL;
}
sdmac->pc_from_device = per_2_emi;
sdmac->pc_to_device = emi_2_per;
sdmac->device_to_device = per_2_per;
sdmac->pc_to_pc = emi_2_emi;
+
+ return 0;
}
static int sdma_load_context(struct sdma_channel *sdmac)
@@ -1197,6 +1201,7 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
static int sdma_config_channel(struct dma_chan *chan)
{
struct sdma_channel *sdmac = to_sdma_chan(chan);
+ int ret;
sdma_disable_channel(chan);
@@ -1217,7 +1222,9 @@ static int sdma_config_channel(struct dma_chan *chan)
break;
}
- sdma_get_pc(sdmac, sdmac->peripheral_type);
+ ret = sdma_get_pc(sdmac, sdmac->peripheral_type);
+ if (ret)
+ return ret;
if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
(sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
@@ -1333,7 +1340,9 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan)
mem_data.dma_request2 = 0;
data = &mem_data;
- sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
+ ret = sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
+ if (ret)
+ return ret;
}
switch (data->priority) {
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 09/19] dma: imx-sdma: error out on unsupported transfer types
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
The i.MX SDMA driver currently silently ignores unsupported transfer
types. These transfer types are specified in the dma channel description
in the device tree, so they should really be checked.
Issue a message and error out when we hit unsupported transfer types.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/dma/imx-sdma.c | 17 +++++++++++++----
1 file changed, 13 insertions(+), 4 deletions(-)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 75ec0754d4ad4..1038f6bc7f846 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -924,7 +924,7 @@ static irqreturn_t sdma_int_handler(int irq, void *dev_id)
/*
* sets the pc of SDMA script according to the peripheral type
*/
-static void sdma_get_pc(struct sdma_channel *sdmac,
+static int sdma_get_pc(struct sdma_channel *sdmac,
enum sdma_peripheral_type peripheral_type)
{
struct sdma_engine *sdma = sdmac->sdma;
@@ -1023,13 +1023,17 @@ static void sdma_get_pc(struct sdma_channel *sdmac,
emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
break;
default:
- break;
+ dev_err(sdma->dev, "Unsupported transfer type %d\n",
+ peripheral_type);
+ return -EINVAL;
}
sdmac->pc_from_device = per_2_emi;
sdmac->pc_to_device = emi_2_per;
sdmac->device_to_device = per_2_per;
sdmac->pc_to_pc = emi_2_emi;
+
+ return 0;
}
static int sdma_load_context(struct sdma_channel *sdmac)
@@ -1197,6 +1201,7 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
static int sdma_config_channel(struct dma_chan *chan)
{
struct sdma_channel *sdmac = to_sdma_chan(chan);
+ int ret;
sdma_disable_channel(chan);
@@ -1217,7 +1222,9 @@ static int sdma_config_channel(struct dma_chan *chan)
break;
}
- sdma_get_pc(sdmac, sdmac->peripheral_type);
+ ret = sdma_get_pc(sdmac, sdmac->peripheral_type);
+ if (ret)
+ return ret;
if ((sdmac->peripheral_type != IMX_DMATYPE_MEMORY) &&
(sdmac->peripheral_type != IMX_DMATYPE_DSP)) {
@@ -1333,7 +1340,9 @@ static int sdma_alloc_chan_resources(struct dma_chan *chan)
mem_data.dma_request2 = 0;
data = &mem_data;
- sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
+ ret = sdma_get_pc(sdmac, IMX_DMATYPE_MEMORY);
+ if (ret)
+ return ret;
}
switch (data->priority) {
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 10/19] dma: imx-sdma: Add multi fifo support
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/dma/imx-sdma.c | 54 +++++++++++++++++++++++++++
include/linux/platform_data/dma-imx.h | 7 ++++
2 files changed, 61 insertions(+)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 1038f6bc7f846..21e1cec2ffde9 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -14,6 +14,7 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/types.h>
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
@@ -73,6 +74,7 @@
#define SDMA_CHNENBL0_IMX35 0x200
#define SDMA_CHNENBL0_IMX31 0x080
#define SDMA_CHNPRI_0 0x100
+#define SDMA_DONE0_CONFIG 0x1000
/*
* Buffer descriptor status values.
@@ -180,6 +182,12 @@
BIT(DMA_MEM_TO_DEV) | \
BIT(DMA_DEV_TO_DEV))
+#define SDMA_WATERMARK_LEVEL_N_FIFOS GENMASK(15, 12)
+#define SDMA_WATERMARK_LEVEL_SW_DONE BIT(23)
+
+#define SDMA_DONE0_CONFIG_DONE_SEL BIT(7)
+#define SDMA_DONE0_CONFIG_DONE_DIS BIT(6)
+
/**
* struct sdma_script_start_addrs - SDMA script start pointers
*
@@ -441,6 +449,11 @@ struct sdma_channel {
struct work_struct terminate_worker;
struct list_head terminated;
bool is_ram_script;
+ unsigned int n_fifos;
+ unsigned int n_fifos_src;
+ unsigned int n_fifos_dst;
+ bool sw_done;
+ u32 sw_done_sel;
};
#define IMX_DMA_SG_LOOP BIT(0)
@@ -773,6 +786,14 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
val = readl_relaxed(sdma->regs + chnenbl);
__set_bit(channel, &val);
writel_relaxed(val, sdma->regs + chnenbl);
+
+ /* Set SDMA_DONEx_CONFIG is sw_done enabled */
+ if (sdmac->sw_done) {
+ val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG);
+ val |= SDMA_DONE0_CONFIG_DONE_SEL;
+ val &= ~SDMA_DONE0_CONFIG_DONE_DIS;
+ writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG);
+ }
}
static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
@@ -1022,6 +1043,10 @@ static int sdma_get_pc(struct sdma_channel *sdmac,
case IMX_DMATYPE_IPU_MEMORY:
emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
break;
+ case IMX_DMATYPE_MULTI_SAI:
+ per_2_emi = sdma->script_addrs->sai_2_mcu_addr;
+ emi_2_per = sdma->script_addrs->mcu_2_sai_addr;
+ break;
default:
dev_err(sdma->dev, "Unsupported transfer type %d\n",
peripheral_type);
@@ -1198,6 +1223,15 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
}
+static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac)
+{
+ if (sdmac->sw_done)
+ sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE;
+
+ sdmac->watermark_level |=
+ FIELD_PREP(SDMA_WATERMARK_LEVEL_N_FIFOS, sdmac->n_fifos);
+}
+
static int sdma_config_channel(struct dma_chan *chan)
{
struct sdma_channel *sdmac = to_sdma_chan(chan);
@@ -1234,6 +1268,10 @@ static int sdma_config_channel(struct dma_chan *chan)
sdmac->peripheral_type == IMX_DMATYPE_ASRC)
sdma_set_watermarklevel_for_p2p(sdmac);
} else {
+ if (sdmac->peripheral_type ==
+ IMX_DMATYPE_MULTI_SAI)
+ sdma_set_watermarklevel_for_sais(sdmac);
+
__set_bit(sdmac->event_id0, sdmac->event_mask);
}
@@ -1669,6 +1707,7 @@ static int sdma_config_write(struct dma_chan *chan,
sdmac->watermark_level = dmaengine_cfg->src_maxburst *
dmaengine_cfg->src_addr_width;
sdmac->word_size = dmaengine_cfg->src_addr_width;
+ sdmac->n_fifos = sdmac->n_fifos_src;
} else if (direction == DMA_DEV_TO_DEV) {
sdmac->per_address2 = dmaengine_cfg->src_addr;
sdmac->per_address = dmaengine_cfg->dst_addr;
@@ -1682,6 +1721,7 @@ static int sdma_config_write(struct dma_chan *chan,
sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
dmaengine_cfg->dst_addr_width;
sdmac->word_size = dmaengine_cfg->dst_addr_width;
+ sdmac->n_fifos = sdmac->n_fifos_dst;
}
sdmac->direction = direction;
return sdma_config_channel(chan);
@@ -1691,9 +1731,23 @@ static int sdma_config(struct dma_chan *chan,
struct dma_slave_config *dmaengine_cfg)
{
struct sdma_channel *sdmac = to_sdma_chan(chan);
+ struct sdma_engine *sdma = sdmac->sdma;
memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
+ if (dmaengine_cfg->peripheral_config) {
+ struct sdma_peripheral_config *sdmacfg = dmaengine_cfg->peripheral_config;
+ if (dmaengine_cfg->peripheral_size != sizeof(struct sdma_peripheral_config)) {
+ dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n",
+ dmaengine_cfg->peripheral_size,
+ sizeof(struct sdma_peripheral_config));
+ return -EINVAL;
+ }
+ sdmac->n_fifos_src = sdmacfg->n_fifos_src;
+ sdmac->n_fifos_dst = sdmacfg->n_fifos_dst;
+ sdmac->sw_done = sdmacfg->sw_done;
+ }
+
/* Set ENBLn earlier to make sure dma request triggered after that */
if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
return -EINVAL;
diff --git a/include/linux/platform_data/dma-imx.h b/include/linux/platform_data/dma-imx.h
index 281adbb26e6bd..4a43a048e1b4d 100644
--- a/include/linux/platform_data/dma-imx.h
+++ b/include/linux/platform_data/dma-imx.h
@@ -39,6 +39,7 @@ enum sdma_peripheral_type {
IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */
IMX_DMATYPE_ASRC_SP, /* Shared ASRC */
IMX_DMATYPE_SAI, /* SAI */
+ IMX_DMATYPE_MULTI_SAI, /* MULTI FIFOs For Audio */
};
enum imx_dma_prio {
@@ -65,4 +66,10 @@ static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
!strcmp(chan->device->dev->driver->name, "imx-dma");
}
+struct sdma_peripheral_config {
+ int n_fifos_src;
+ int n_fifos_dst;
+ bool sw_done;
+};
+
#endif
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 10/19] dma: imx-sdma: Add multi fifo support
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
drivers/dma/imx-sdma.c | 54 +++++++++++++++++++++++++++
include/linux/platform_data/dma-imx.h | 7 ++++
2 files changed, 61 insertions(+)
diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
index 1038f6bc7f846..21e1cec2ffde9 100644
--- a/drivers/dma/imx-sdma.c
+++ b/drivers/dma/imx-sdma.c
@@ -14,6 +14,7 @@
#include <linux/iopoll.h>
#include <linux/module.h>
#include <linux/types.h>
+#include <linux/bitfield.h>
#include <linux/bitops.h>
#include <linux/mm.h>
#include <linux/interrupt.h>
@@ -73,6 +74,7 @@
#define SDMA_CHNENBL0_IMX35 0x200
#define SDMA_CHNENBL0_IMX31 0x080
#define SDMA_CHNPRI_0 0x100
+#define SDMA_DONE0_CONFIG 0x1000
/*
* Buffer descriptor status values.
@@ -180,6 +182,12 @@
BIT(DMA_MEM_TO_DEV) | \
BIT(DMA_DEV_TO_DEV))
+#define SDMA_WATERMARK_LEVEL_N_FIFOS GENMASK(15, 12)
+#define SDMA_WATERMARK_LEVEL_SW_DONE BIT(23)
+
+#define SDMA_DONE0_CONFIG_DONE_SEL BIT(7)
+#define SDMA_DONE0_CONFIG_DONE_DIS BIT(6)
+
/**
* struct sdma_script_start_addrs - SDMA script start pointers
*
@@ -441,6 +449,11 @@ struct sdma_channel {
struct work_struct terminate_worker;
struct list_head terminated;
bool is_ram_script;
+ unsigned int n_fifos;
+ unsigned int n_fifos_src;
+ unsigned int n_fifos_dst;
+ bool sw_done;
+ u32 sw_done_sel;
};
#define IMX_DMA_SG_LOOP BIT(0)
@@ -773,6 +786,14 @@ static void sdma_event_enable(struct sdma_channel *sdmac, unsigned int event)
val = readl_relaxed(sdma->regs + chnenbl);
__set_bit(channel, &val);
writel_relaxed(val, sdma->regs + chnenbl);
+
+ /* Set SDMA_DONEx_CONFIG is sw_done enabled */
+ if (sdmac->sw_done) {
+ val = readl_relaxed(sdma->regs + SDMA_DONE0_CONFIG);
+ val |= SDMA_DONE0_CONFIG_DONE_SEL;
+ val &= ~SDMA_DONE0_CONFIG_DONE_DIS;
+ writel_relaxed(val, sdma->regs + SDMA_DONE0_CONFIG);
+ }
}
static void sdma_event_disable(struct sdma_channel *sdmac, unsigned int event)
@@ -1022,6 +1043,10 @@ static int sdma_get_pc(struct sdma_channel *sdmac,
case IMX_DMATYPE_IPU_MEMORY:
emi_2_per = sdma->script_addrs->ext_mem_2_ipu_addr;
break;
+ case IMX_DMATYPE_MULTI_SAI:
+ per_2_emi = sdma->script_addrs->sai_2_mcu_addr;
+ emi_2_per = sdma->script_addrs->mcu_2_sai_addr;
+ break;
default:
dev_err(sdma->dev, "Unsupported transfer type %d\n",
peripheral_type);
@@ -1198,6 +1223,15 @@ static void sdma_set_watermarklevel_for_p2p(struct sdma_channel *sdmac)
sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_CONT;
}
+static void sdma_set_watermarklevel_for_sais(struct sdma_channel *sdmac)
+{
+ if (sdmac->sw_done)
+ sdmac->watermark_level |= SDMA_WATERMARK_LEVEL_SW_DONE;
+
+ sdmac->watermark_level |=
+ FIELD_PREP(SDMA_WATERMARK_LEVEL_N_FIFOS, sdmac->n_fifos);
+}
+
static int sdma_config_channel(struct dma_chan *chan)
{
struct sdma_channel *sdmac = to_sdma_chan(chan);
@@ -1234,6 +1268,10 @@ static int sdma_config_channel(struct dma_chan *chan)
sdmac->peripheral_type == IMX_DMATYPE_ASRC)
sdma_set_watermarklevel_for_p2p(sdmac);
} else {
+ if (sdmac->peripheral_type ==
+ IMX_DMATYPE_MULTI_SAI)
+ sdma_set_watermarklevel_for_sais(sdmac);
+
__set_bit(sdmac->event_id0, sdmac->event_mask);
}
@@ -1669,6 +1707,7 @@ static int sdma_config_write(struct dma_chan *chan,
sdmac->watermark_level = dmaengine_cfg->src_maxburst *
dmaengine_cfg->src_addr_width;
sdmac->word_size = dmaengine_cfg->src_addr_width;
+ sdmac->n_fifos = sdmac->n_fifos_src;
} else if (direction == DMA_DEV_TO_DEV) {
sdmac->per_address2 = dmaengine_cfg->src_addr;
sdmac->per_address = dmaengine_cfg->dst_addr;
@@ -1682,6 +1721,7 @@ static int sdma_config_write(struct dma_chan *chan,
sdmac->watermark_level = dmaengine_cfg->dst_maxburst *
dmaengine_cfg->dst_addr_width;
sdmac->word_size = dmaengine_cfg->dst_addr_width;
+ sdmac->n_fifos = sdmac->n_fifos_dst;
}
sdmac->direction = direction;
return sdma_config_channel(chan);
@@ -1691,9 +1731,23 @@ static int sdma_config(struct dma_chan *chan,
struct dma_slave_config *dmaengine_cfg)
{
struct sdma_channel *sdmac = to_sdma_chan(chan);
+ struct sdma_engine *sdma = sdmac->sdma;
memcpy(&sdmac->slave_config, dmaengine_cfg, sizeof(*dmaengine_cfg));
+ if (dmaengine_cfg->peripheral_config) {
+ struct sdma_peripheral_config *sdmacfg = dmaengine_cfg->peripheral_config;
+ if (dmaengine_cfg->peripheral_size != sizeof(struct sdma_peripheral_config)) {
+ dev_err(sdma->dev, "Invalid peripheral size %zu, expected %zu\n",
+ dmaengine_cfg->peripheral_size,
+ sizeof(struct sdma_peripheral_config));
+ return -EINVAL;
+ }
+ sdmac->n_fifos_src = sdmacfg->n_fifos_src;
+ sdmac->n_fifos_dst = sdmacfg->n_fifos_dst;
+ sdmac->sw_done = sdmacfg->sw_done;
+ }
+
/* Set ENBLn earlier to make sure dma request triggered after that */
if (sdmac->event_id0 >= sdmac->sdma->drvdata->num_events)
return -EINVAL;
diff --git a/include/linux/platform_data/dma-imx.h b/include/linux/platform_data/dma-imx.h
index 281adbb26e6bd..4a43a048e1b4d 100644
--- a/include/linux/platform_data/dma-imx.h
+++ b/include/linux/platform_data/dma-imx.h
@@ -39,6 +39,7 @@ enum sdma_peripheral_type {
IMX_DMATYPE_SSI_DUAL, /* SSI Dual FIFO */
IMX_DMATYPE_ASRC_SP, /* Shared ASRC */
IMX_DMATYPE_SAI, /* SAI */
+ IMX_DMATYPE_MULTI_SAI, /* MULTI FIFOs For Audio */
};
enum imx_dma_prio {
@@ -65,4 +66,10 @@ static inline int imx_dma_is_general_purpose(struct dma_chan *chan)
!strcmp(chan->device->dev->driver->name, "imx-dma");
}
+struct sdma_peripheral_config {
+ int n_fifos_src;
+ int n_fifos_dst;
+ bool sw_done;
+};
+
#endif
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 11/19] ASoC: fsl_micfil: add multi fifo support
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 82b8fc83fd361..7795fc59d7d1a 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -15,6 +15,7 @@
#include <linux/regmap.h>
#include <linux/sysfs.h>
#include <linux/types.h>
+#include <linux/platform_data/dma-imx.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm.h>
#include <sound/soc.h>
@@ -34,6 +35,7 @@ struct fsl_micfil {
struct clk *busclk;
struct clk *mclk;
struct snd_dmaengine_dai_dma_data dma_params_rx;
+ struct sdma_peripheral_config sdmacfg;
unsigned int dataline;
char name[32];
int irq[MICFIL_IRQ_LINES];
@@ -323,6 +325,10 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
return ret;
}
+ micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
+ micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
+ micfil->sdmacfg.n_fifos_src = channels;
+ micfil->sdmacfg.sw_done = true;
micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
return 0;
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 11/19] ASoC: fsl_micfil: add multi fifo support
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 82b8fc83fd361..7795fc59d7d1a 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -15,6 +15,7 @@
#include <linux/regmap.h>
#include <linux/sysfs.h>
#include <linux/types.h>
+#include <linux/platform_data/dma-imx.h>
#include <sound/dmaengine_pcm.h>
#include <sound/pcm.h>
#include <sound/soc.h>
@@ -34,6 +35,7 @@ struct fsl_micfil {
struct clk *busclk;
struct clk *mclk;
struct snd_dmaengine_dai_dma_data dma_params_rx;
+ struct sdma_peripheral_config sdmacfg;
unsigned int dataline;
char name[32];
int irq[MICFIL_IRQ_LINES];
@@ -323,6 +325,10 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
return ret;
}
+ micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
+ micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
+ micfil->sdmacfg.n_fifos_src = channels;
+ micfil->sdmacfg.sw_done = true;
micfil->dma_params_rx.maxburst = channels * MICFIL_DMA_MAXBURST_RX;
return 0;
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 12/19] ASoC: fsl_micfil: use define for OSR default value
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
The OSR (OverSampling Rate) setting is set once to the default value
and never changed throughout the driver. Nevertheless the value is
read back from the register for further calculations. Just use the
default value because we know what we have written.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 10 ++++++----
sound/soc/fsl/fsl_micfil.h | 1 -
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 7795fc59d7d1a..48054b9bd4bb2 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -28,6 +28,8 @@
#define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
#define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
+#define MICFIL_OSR_DEFAULT 16
+
struct fsl_micfil {
struct platform_device *pdev;
struct regmap *regmap;
@@ -40,6 +42,7 @@ struct fsl_micfil {
char name[32];
int irq[MICFIL_IRQ_LINES];
int quality; /*QUALITY 2-0 bits */
+ unsigned int osr;
};
struct fsl_micfil_soc_data {
@@ -111,11 +114,11 @@ static inline int get_pdm_clk(struct fsl_micfil *micfil,
unsigned int rate)
{
u32 ctrl2_reg;
- int qsel, osr;
+ int qsel;
int bclk;
+ int osr = MICFIL_OSR_DEFAULT;
regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
- osr = 16 - FIELD_GET(MICFIL_CTRL2_CICOSR, ctrl2_reg);
qsel = FIELD_GET(MICFIL_CTRL2_QSEL, ctrl2_reg);
switch (qsel) {
@@ -281,7 +284,7 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
/* set CICOSR */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_CICOSR,
- FIELD_PREP(MICFIL_CTRL2_CICOSR, MICFIL_CTRL2_CICOSR_DEFAULT));
+ FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - MICFIL_OSR_DEFAULT));
if (ret)
return ret;
@@ -672,7 +675,6 @@ static int fsl_micfil_probe(struct platform_device *pdev)
micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
-
platform_set_drvdata(pdev, micfil);
pm_runtime_enable(&pdev->dev);
diff --git a/sound/soc/fsl/fsl_micfil.h b/sound/soc/fsl/fsl_micfil.h
index 5cecae2519795..08901827047db 100644
--- a/sound/soc/fsl/fsl_micfil.h
+++ b/sound/soc/fsl/fsl_micfil.h
@@ -58,7 +58,6 @@
#define MICFIL_QSEL_VLOW2_QUALITY 4
#define MICFIL_CTRL2_CICOSR GENMASK(19, 16)
-#define MICFIL_CTRL2_CICOSR_DEFAULT 0
#define MICFIL_CTRL2_CLKDIV GENMASK(7, 0)
/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 12/19] ASoC: fsl_micfil: use define for OSR default value
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
The OSR (OverSampling Rate) setting is set once to the default value
and never changed throughout the driver. Nevertheless the value is
read back from the register for further calculations. Just use the
default value because we know what we have written.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 10 ++++++----
sound/soc/fsl/fsl_micfil.h | 1 -
2 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 7795fc59d7d1a..48054b9bd4bb2 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -28,6 +28,8 @@
#define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
#define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
+#define MICFIL_OSR_DEFAULT 16
+
struct fsl_micfil {
struct platform_device *pdev;
struct regmap *regmap;
@@ -40,6 +42,7 @@ struct fsl_micfil {
char name[32];
int irq[MICFIL_IRQ_LINES];
int quality; /*QUALITY 2-0 bits */
+ unsigned int osr;
};
struct fsl_micfil_soc_data {
@@ -111,11 +114,11 @@ static inline int get_pdm_clk(struct fsl_micfil *micfil,
unsigned int rate)
{
u32 ctrl2_reg;
- int qsel, osr;
+ int qsel;
int bclk;
+ int osr = MICFIL_OSR_DEFAULT;
regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
- osr = 16 - FIELD_GET(MICFIL_CTRL2_CICOSR, ctrl2_reg);
qsel = FIELD_GET(MICFIL_CTRL2_QSEL, ctrl2_reg);
switch (qsel) {
@@ -281,7 +284,7 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
/* set CICOSR */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_CICOSR,
- FIELD_PREP(MICFIL_CTRL2_CICOSR, MICFIL_CTRL2_CICOSR_DEFAULT));
+ FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - MICFIL_OSR_DEFAULT));
if (ret)
return ret;
@@ -672,7 +675,6 @@ static int fsl_micfil_probe(struct platform_device *pdev)
micfil->dma_params_rx.addr = res->start + REG_MICFIL_DATACH0;
micfil->dma_params_rx.maxburst = MICFIL_DMA_MAXBURST_RX;
-
platform_set_drvdata(pdev, micfil);
pm_runtime_enable(&pdev->dev);
diff --git a/sound/soc/fsl/fsl_micfil.h b/sound/soc/fsl/fsl_micfil.h
index 5cecae2519795..08901827047db 100644
--- a/sound/soc/fsl/fsl_micfil.h
+++ b/sound/soc/fsl/fsl_micfil.h
@@ -58,7 +58,6 @@
#define MICFIL_QSEL_VLOW2_QUALITY 4
#define MICFIL_CTRL2_CICOSR GENMASK(19, 16)
-#define MICFIL_CTRL2_CICOSR_DEFAULT 0
#define MICFIL_CTRL2_CLKDIV GENMASK(7, 0)
/* MICFIL Status Register -- REG_MICFIL_STAT 0x08 */
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 13/19] ASoC: fsl_micfil: Drop get_pdm_clk()
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
get_pdm_clk() calculates the PDM clock based on the quality setting,
but really the PDM clock is independent of the quality, it's always
rate * 4 * micfil->osr. Just drop the function and do the calculation
in the caller.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 38 +-------------------------------------
1 file changed, 1 insertion(+), 37 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 48054b9bd4bb2..8dadb824a94ff 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -110,42 +110,6 @@ static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
snd_soc_get_enum_double, snd_soc_put_enum_double),
};
-static inline int get_pdm_clk(struct fsl_micfil *micfil,
- unsigned int rate)
-{
- u32 ctrl2_reg;
- int qsel;
- int bclk;
- int osr = MICFIL_OSR_DEFAULT;
-
- regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
- qsel = FIELD_GET(MICFIL_CTRL2_QSEL, ctrl2_reg);
-
- switch (qsel) {
- case MICFIL_QSEL_HIGH_QUALITY:
- bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
- break;
- case MICFIL_QSEL_MEDIUM_QUALITY:
- case MICFIL_QSEL_VLOW0_QUALITY:
- bclk = rate * 4 * osr * 1; /* kfactor = 1 */
- break;
- case MICFIL_QSEL_LOW_QUALITY:
- case MICFIL_QSEL_VLOW1_QUALITY:
- bclk = rate * 2 * osr * 2; /* kfactor = 2 */
- break;
- case MICFIL_QSEL_VLOW2_QUALITY:
- bclk = rate * osr * 4; /* kfactor = 4 */
- break;
- default:
- dev_err(&micfil->pdev->dev,
- "Please make sure you select a valid quality.\n");
- bclk = -1;
- break;
- }
-
- return bclk;
-}
-
static inline int get_clk_div(struct fsl_micfil *micfil,
unsigned int rate)
{
@@ -154,7 +118,7 @@ static inline int get_clk_div(struct fsl_micfil *micfil,
mclk_rate = clk_get_rate(micfil->mclk);
- clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
+ clk_div = mclk_rate / (rate * micfil->osr * 8);
return clk_div;
}
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 13/19] ASoC: fsl_micfil: Drop get_pdm_clk()
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
get_pdm_clk() calculates the PDM clock based on the quality setting,
but really the PDM clock is independent of the quality, it's always
rate * 4 * micfil->osr. Just drop the function and do the calculation
in the caller.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 38 +-------------------------------------
1 file changed, 1 insertion(+), 37 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 48054b9bd4bb2..8dadb824a94ff 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -110,42 +110,6 @@ static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
snd_soc_get_enum_double, snd_soc_put_enum_double),
};
-static inline int get_pdm_clk(struct fsl_micfil *micfil,
- unsigned int rate)
-{
- u32 ctrl2_reg;
- int qsel;
- int bclk;
- int osr = MICFIL_OSR_DEFAULT;
-
- regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
- qsel = FIELD_GET(MICFIL_CTRL2_QSEL, ctrl2_reg);
-
- switch (qsel) {
- case MICFIL_QSEL_HIGH_QUALITY:
- bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
- break;
- case MICFIL_QSEL_MEDIUM_QUALITY:
- case MICFIL_QSEL_VLOW0_QUALITY:
- bclk = rate * 4 * osr * 1; /* kfactor = 1 */
- break;
- case MICFIL_QSEL_LOW_QUALITY:
- case MICFIL_QSEL_VLOW1_QUALITY:
- bclk = rate * 2 * osr * 2; /* kfactor = 2 */
- break;
- case MICFIL_QSEL_VLOW2_QUALITY:
- bclk = rate * osr * 4; /* kfactor = 4 */
- break;
- default:
- dev_err(&micfil->pdev->dev,
- "Please make sure you select a valid quality.\n");
- bclk = -1;
- break;
- }
-
- return bclk;
-}
-
static inline int get_clk_div(struct fsl_micfil *micfil,
unsigned int rate)
{
@@ -154,7 +118,7 @@ static inline int get_clk_div(struct fsl_micfil *micfil,
mclk_rate = clk_get_rate(micfil->mclk);
- clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
+ clk_div = mclk_rate / (rate * micfil->osr * 8);
return clk_div;
}
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 14/19] ASoC: fsl_micfil: simplify clock setting
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
The reference manual has this for calculating the micfil internal clock
divider:
MICFIL Clock rate
clkdiv = -----------------
8 * OSR * outrate
(with OSR == Oversampling Rate, outrate == output sample rate)
The driver first sets the MICFIL Clock rate to (outrate * 1024) and then
calculates back the clkdiv value from the above calculation.
Simplify this by using a fixed clkdiv value of 8 and set the MICFIL
Clock rate to (outrate * clkdiv * OSR * 8).
While at it drop disabling the clock before setting its rate. The MICFIL
module is disabled when the rate is changed and it is also resetted
before it is started again, so I doubt it's necessary to disable the
clock.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 45 ++++----------------------------------
1 file changed, 4 insertions(+), 41 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 8dadb824a94ff..7975ae6f3fb4f 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -110,19 +110,6 @@ static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
snd_soc_get_enum_double, snd_soc_put_enum_double),
};
-static inline int get_clk_div(struct fsl_micfil *micfil,
- unsigned int rate)
-{
- long mclk_rate;
- int clk_div;
-
- mclk_rate = clk_get_rate(micfil->mclk);
-
- clk_div = mclk_rate / (rate * micfil->osr * 8);
-
- return clk_div;
-}
-
/* The SRES is a self-negated bit which provides the CPU with the
* capability to initialize the PDM Interface module through the
* slave-bus interface. This bit always reads as zero, and this
@@ -146,24 +133,6 @@ static int fsl_micfil_reset(struct device *dev)
return 0;
}
-static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
- unsigned int freq)
-{
- struct device *dev = &micfil->pdev->dev;
- int ret;
-
- clk_disable_unprepare(micfil->mclk);
-
- ret = clk_set_rate(micfil->mclk, freq * 1024);
- if (ret)
- dev_warn(dev, "failed to set rate (%u): %d\n",
- freq * 1024, ret);
-
- clk_prepare_enable(micfil->mclk);
-
- return ret;
-}
-
static int fsl_micfil_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
@@ -237,13 +206,12 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
static int fsl_set_clock_params(struct device *dev, unsigned int rate)
{
struct fsl_micfil *micfil = dev_get_drvdata(dev);
- int clk_div;
+ int clk_div = 8;
int ret;
- ret = fsl_micfil_set_mclk_rate(micfil, rate);
- if (ret < 0)
- dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
- clk_get_rate(micfil->mclk), rate);
+ ret = clk_set_rate(micfil->mclk, rate * clk_div * micfil->osr * 8);
+ if (ret)
+ return ret;
/* set CICOSR */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
@@ -252,11 +220,6 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
if (ret)
return ret;
- /* set CLK_DIV */
- clk_div = get_clk_div(micfil, rate);
- if (clk_div < 0)
- ret = -EINVAL;
-
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_CLKDIV,
FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div));
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 14/19] ASoC: fsl_micfil: simplify clock setting
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
The reference manual has this for calculating the micfil internal clock
divider:
MICFIL Clock rate
clkdiv = -----------------
8 * OSR * outrate
(with OSR == Oversampling Rate, outrate == output sample rate)
The driver first sets the MICFIL Clock rate to (outrate * 1024) and then
calculates back the clkdiv value from the above calculation.
Simplify this by using a fixed clkdiv value of 8 and set the MICFIL
Clock rate to (outrate * clkdiv * OSR * 8).
While at it drop disabling the clock before setting its rate. The MICFIL
module is disabled when the rate is changed and it is also resetted
before it is started again, so I doubt it's necessary to disable the
clock.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 45 ++++----------------------------------
1 file changed, 4 insertions(+), 41 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 8dadb824a94ff..7975ae6f3fb4f 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -110,19 +110,6 @@ static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
snd_soc_get_enum_double, snd_soc_put_enum_double),
};
-static inline int get_clk_div(struct fsl_micfil *micfil,
- unsigned int rate)
-{
- long mclk_rate;
- int clk_div;
-
- mclk_rate = clk_get_rate(micfil->mclk);
-
- clk_div = mclk_rate / (rate * micfil->osr * 8);
-
- return clk_div;
-}
-
/* The SRES is a self-negated bit which provides the CPU with the
* capability to initialize the PDM Interface module through the
* slave-bus interface. This bit always reads as zero, and this
@@ -146,24 +133,6 @@ static int fsl_micfil_reset(struct device *dev)
return 0;
}
-static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
- unsigned int freq)
-{
- struct device *dev = &micfil->pdev->dev;
- int ret;
-
- clk_disable_unprepare(micfil->mclk);
-
- ret = clk_set_rate(micfil->mclk, freq * 1024);
- if (ret)
- dev_warn(dev, "failed to set rate (%u): %d\n",
- freq * 1024, ret);
-
- clk_prepare_enable(micfil->mclk);
-
- return ret;
-}
-
static int fsl_micfil_startup(struct snd_pcm_substream *substream,
struct snd_soc_dai *dai)
{
@@ -237,13 +206,12 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
static int fsl_set_clock_params(struct device *dev, unsigned int rate)
{
struct fsl_micfil *micfil = dev_get_drvdata(dev);
- int clk_div;
+ int clk_div = 8;
int ret;
- ret = fsl_micfil_set_mclk_rate(micfil, rate);
- if (ret < 0)
- dev_err(dev, "failed to set mclk[%lu] to rate %u\n",
- clk_get_rate(micfil->mclk), rate);
+ ret = clk_set_rate(micfil->mclk, rate * clk_div * micfil->osr * 8);
+ if (ret)
+ return ret;
/* set CICOSR */
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
@@ -252,11 +220,6 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
if (ret)
return ret;
- /* set CLK_DIV */
- clk_div = get_clk_div(micfil, rate);
- if (clk_div < 0)
- ret = -EINVAL;
-
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
MICFIL_CTRL2_CLKDIV,
FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div));
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 15/19] ASoC: fsl_micfil: rework quality setting
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
For the quality setting the quality setting register values are directly
exposed to the kcontrol and thus to userspace. This is unfortunate
because the register settings contains invalid bit combinations marked
as "N/A". For userspace it doesn't make much sense to be able to set
these just to see that the driver responds with "Please make sure you
select a valid quality." in the kernel log.
Work around this by adding get/set functions for the quality setting.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 109 ++++++++++++++++++++++++++-----------
1 file changed, 77 insertions(+), 32 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 7975ae6f3fb4f..3c0a0ccd0e5fe 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -30,6 +30,15 @@
#define MICFIL_OSR_DEFAULT 16
+enum quality {
+ QUALITY_HIGH,
+ QUALITY_MEDIUM,
+ QUALITY_LOW,
+ QUALITY_VLOW0,
+ QUALITY_VLOW1,
+ QUALITY_VLOW2,
+};
+
struct fsl_micfil {
struct platform_device *pdev;
struct regmap *regmap;
@@ -41,7 +50,7 @@ struct fsl_micfil {
unsigned int dataline;
char name[32];
int irq[MICFIL_IRQ_LINES];
- int quality; /*QUALITY 2-0 bits */
+ enum quality quality;
unsigned int osr;
};
@@ -65,29 +74,73 @@ static const struct of_device_id fsl_micfil_dt_ids[] = {
};
MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
-/* Table 5. Quality Modes
- * Medium 0 0 0
- * High 0 0 1
- * Very Low 2 1 0 0
- * Very Low 1 1 0 1
- * Very Low 0 1 1 0
- * Low 1 1 1
- */
static const char * const micfil_quality_select_texts[] = {
- "Medium", "High",
- "N/A", "N/A",
- "VLow2", "VLow1",
- "VLow0", "Low",
+ [QUALITY_HIGH] = "High",
+ [QUALITY_MEDIUM] = "Medium",
+ [QUALITY_LOW] = "Low",
+ [QUALITY_VLOW0] = "VLow0",
+ [QUALITY_VLOW1] = "Vlow1",
+ [QUALITY_VLOW2] = "Vlow2",
};
static const struct soc_enum fsl_micfil_quality_enum =
- SOC_ENUM_SINGLE(REG_MICFIL_CTRL2,
- MICFIL_CTRL2_QSEL_SHIFT,
- ARRAY_SIZE(micfil_quality_select_texts),
- micfil_quality_select_texts);
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
+ micfil_quality_select_texts);
static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
+static int micfil_set_quality(struct fsl_micfil *micfil)
+{
+ u32 qsel;
+
+ switch (micfil->quality) {
+ case QUALITY_HIGH:
+ qsel = MICFIL_QSEL_HIGH_QUALITY;
+ break;
+ case QUALITY_MEDIUM:
+ qsel = MICFIL_QSEL_MEDIUM_QUALITY;
+ break;
+ case QUALITY_LOW:
+ qsel = MICFIL_QSEL_LOW_QUALITY;
+ break;
+ case QUALITY_VLOW0:
+ qsel = MICFIL_QSEL_VLOW0_QUALITY;
+ break;
+ case QUALITY_VLOW1:
+ qsel = MICFIL_QSEL_VLOW1_QUALITY;
+ break;
+ case QUALITY_VLOW2:
+ qsel = MICFIL_QSEL_VLOW2_QUALITY;
+ break;
+ }
+
+ return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
+ MICFIL_CTRL2_QSEL,
+ FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
+}
+
+static int micfil_quality_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
+ struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
+
+ ucontrol->value.integer.value[0] = micfil->quality;
+
+ return 0;
+}
+
+static int micfil_quality_set(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
+ struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
+
+ micfil->quality = ucontrol->value.integer.value[0];
+
+ return micfil_set_quality(micfil);
+}
+
static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv),
@@ -107,7 +160,7 @@ static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv),
SOC_ENUM_EXT("MICFIL Quality Select",
fsl_micfil_quality_enum,
- snd_soc_get_enum_double, snd_soc_put_enum_double),
+ micfil_quality_get, micfil_quality_set),
};
/* The SRES is a self-negated bit which provides the CPU with the
@@ -207,22 +260,21 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
{
struct fsl_micfil *micfil = dev_get_drvdata(dev);
int clk_div = 8;
+ int osr = MICFIL_OSR_DEFAULT;
int ret;
- ret = clk_set_rate(micfil->mclk, rate * clk_div * micfil->osr * 8);
+ ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
if (ret)
return ret;
- /* set CICOSR */
- ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
- MICFIL_CTRL2_CICOSR,
- FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - MICFIL_OSR_DEFAULT));
+ ret = micfil_set_quality(micfil);
if (ret)
return ret;
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
- MICFIL_CTRL2_CLKDIV,
- FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div));
+ MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
+ FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
+ FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
return ret;
}
@@ -275,13 +327,6 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
int ret;
- /* set qsel to medium */
- ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
- MICFIL_CTRL2_QSEL,
- FIELD_PREP(MICFIL_CTRL2_QSEL, MICFIL_QSEL_MEDIUM_QUALITY));
- if (ret)
- return ret;
-
/* set default gain to max_gain */
regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 15/19] ASoC: fsl_micfil: rework quality setting
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
For the quality setting the quality setting register values are directly
exposed to the kcontrol and thus to userspace. This is unfortunate
because the register settings contains invalid bit combinations marked
as "N/A". For userspace it doesn't make much sense to be able to set
these just to see that the driver responds with "Please make sure you
select a valid quality." in the kernel log.
Work around this by adding get/set functions for the quality setting.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 109 ++++++++++++++++++++++++++-----------
1 file changed, 77 insertions(+), 32 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 7975ae6f3fb4f..3c0a0ccd0e5fe 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -30,6 +30,15 @@
#define MICFIL_OSR_DEFAULT 16
+enum quality {
+ QUALITY_HIGH,
+ QUALITY_MEDIUM,
+ QUALITY_LOW,
+ QUALITY_VLOW0,
+ QUALITY_VLOW1,
+ QUALITY_VLOW2,
+};
+
struct fsl_micfil {
struct platform_device *pdev;
struct regmap *regmap;
@@ -41,7 +50,7 @@ struct fsl_micfil {
unsigned int dataline;
char name[32];
int irq[MICFIL_IRQ_LINES];
- int quality; /*QUALITY 2-0 bits */
+ enum quality quality;
unsigned int osr;
};
@@ -65,29 +74,73 @@ static const struct of_device_id fsl_micfil_dt_ids[] = {
};
MODULE_DEVICE_TABLE(of, fsl_micfil_dt_ids);
-/* Table 5. Quality Modes
- * Medium 0 0 0
- * High 0 0 1
- * Very Low 2 1 0 0
- * Very Low 1 1 0 1
- * Very Low 0 1 1 0
- * Low 1 1 1
- */
static const char * const micfil_quality_select_texts[] = {
- "Medium", "High",
- "N/A", "N/A",
- "VLow2", "VLow1",
- "VLow0", "Low",
+ [QUALITY_HIGH] = "High",
+ [QUALITY_MEDIUM] = "Medium",
+ [QUALITY_LOW] = "Low",
+ [QUALITY_VLOW0] = "VLow0",
+ [QUALITY_VLOW1] = "Vlow1",
+ [QUALITY_VLOW2] = "Vlow2",
};
static const struct soc_enum fsl_micfil_quality_enum =
- SOC_ENUM_SINGLE(REG_MICFIL_CTRL2,
- MICFIL_CTRL2_QSEL_SHIFT,
- ARRAY_SIZE(micfil_quality_select_texts),
- micfil_quality_select_texts);
+ SOC_ENUM_SINGLE_EXT(ARRAY_SIZE(micfil_quality_select_texts),
+ micfil_quality_select_texts);
static DECLARE_TLV_DB_SCALE(gain_tlv, 0, 100, 0);
+static int micfil_set_quality(struct fsl_micfil *micfil)
+{
+ u32 qsel;
+
+ switch (micfil->quality) {
+ case QUALITY_HIGH:
+ qsel = MICFIL_QSEL_HIGH_QUALITY;
+ break;
+ case QUALITY_MEDIUM:
+ qsel = MICFIL_QSEL_MEDIUM_QUALITY;
+ break;
+ case QUALITY_LOW:
+ qsel = MICFIL_QSEL_LOW_QUALITY;
+ break;
+ case QUALITY_VLOW0:
+ qsel = MICFIL_QSEL_VLOW0_QUALITY;
+ break;
+ case QUALITY_VLOW1:
+ qsel = MICFIL_QSEL_VLOW1_QUALITY;
+ break;
+ case QUALITY_VLOW2:
+ qsel = MICFIL_QSEL_VLOW2_QUALITY;
+ break;
+ }
+
+ return regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
+ MICFIL_CTRL2_QSEL,
+ FIELD_PREP(MICFIL_CTRL2_QSEL, qsel));
+}
+
+static int micfil_quality_get(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
+ struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
+
+ ucontrol->value.integer.value[0] = micfil->quality;
+
+ return 0;
+}
+
+static int micfil_quality_set(struct snd_kcontrol *kcontrol,
+ struct snd_ctl_elem_value *ucontrol)
+{
+ struct snd_soc_component *cmpnt = snd_soc_kcontrol_component(kcontrol);
+ struct fsl_micfil *micfil = snd_soc_component_get_drvdata(cmpnt);
+
+ micfil->quality = ucontrol->value.integer.value[0];
+
+ return micfil_set_quality(micfil);
+}
+
static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
SOC_SINGLE_SX_TLV("CH0 Volume", REG_MICFIL_OUT_CTRL,
MICFIL_OUTGAIN_CHX_SHIFT(0), 0xF, 0x7, gain_tlv),
@@ -107,7 +160,7 @@ static const struct snd_kcontrol_new fsl_micfil_snd_controls[] = {
MICFIL_OUTGAIN_CHX_SHIFT(7), 0xF, 0x7, gain_tlv),
SOC_ENUM_EXT("MICFIL Quality Select",
fsl_micfil_quality_enum,
- snd_soc_get_enum_double, snd_soc_put_enum_double),
+ micfil_quality_get, micfil_quality_set),
};
/* The SRES is a self-negated bit which provides the CPU with the
@@ -207,22 +260,21 @@ static int fsl_set_clock_params(struct device *dev, unsigned int rate)
{
struct fsl_micfil *micfil = dev_get_drvdata(dev);
int clk_div = 8;
+ int osr = MICFIL_OSR_DEFAULT;
int ret;
- ret = clk_set_rate(micfil->mclk, rate * clk_div * micfil->osr * 8);
+ ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
if (ret)
return ret;
- /* set CICOSR */
- ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
- MICFIL_CTRL2_CICOSR,
- FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - MICFIL_OSR_DEFAULT));
+ ret = micfil_set_quality(micfil);
if (ret)
return ret;
ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
- MICFIL_CTRL2_CLKDIV,
- FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div));
+ MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
+ FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
+ FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
return ret;
}
@@ -275,13 +327,6 @@ static int fsl_micfil_dai_probe(struct snd_soc_dai *cpu_dai)
struct fsl_micfil *micfil = dev_get_drvdata(cpu_dai->dev);
int ret;
- /* set qsel to medium */
- ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
- MICFIL_CTRL2_QSEL,
- FIELD_PREP(MICFIL_CTRL2_QSEL, MICFIL_QSEL_MEDIUM_QUALITY));
- if (ret)
- return ret;
-
/* set default gain to max_gain */
regmap_write(micfil->regmap, REG_MICFIL_OUT_CTRL, 0x77777777);
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 16/19] ASoC: fsl_micfil: drop unused include
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
The micfil driver doesn't use anything from imx-pcm.h. Drop its
inclusion.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 3c0a0ccd0e5fe..9e10de5f4fcd9 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -23,7 +23,6 @@
#include <sound/core.h>
#include "fsl_micfil.h"
-#include "imx-pcm.h"
#define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
#define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 16/19] ASoC: fsl_micfil: drop unused include
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
The micfil driver doesn't use anything from imx-pcm.h. Drop its
inclusion.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 1 -
1 file changed, 1 deletion(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 3c0a0ccd0e5fe..9e10de5f4fcd9 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -23,7 +23,6 @@
#include <sound/core.h>
#include "fsl_micfil.h"
-#include "imx-pcm.h"
#define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
#define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 17/19] ASoC: fsl_micfil: drop only once used defines
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
FSL_MICFIL_RATES and FSL_MICFIL_FORMATS is only used once. Drop
the unnecesary indirection and use SNDRV_PCM_RATE_8000_48000 and
SNDRV_PCM_FMTBIT_S16_LE directly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 9e10de5f4fcd9..7a2af7d34dadc 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -24,9 +24,6 @@
#include "fsl_micfil.h"
-#define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
-#define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
-
#define MICFIL_OSR_DEFAULT 16
enum quality {
@@ -348,8 +345,8 @@ static struct snd_soc_dai_driver fsl_micfil_dai = {
.stream_name = "CPU-Capture",
.channels_min = 1,
.channels_max = 8,
- .rates = FSL_MICFIL_RATES,
- .formats = FSL_MICFIL_FORMATS,
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &fsl_micfil_dai_ops,
};
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 17/19] ASoC: fsl_micfil: drop only once used defines
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
FSL_MICFIL_RATES and FSL_MICFIL_FORMATS is only used once. Drop
the unnecesary indirection and use SNDRV_PCM_RATE_8000_48000 and
SNDRV_PCM_FMTBIT_S16_LE directly.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 7 ++-----
1 file changed, 2 insertions(+), 5 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 9e10de5f4fcd9..7a2af7d34dadc 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -24,9 +24,6 @@
#include "fsl_micfil.h"
-#define FSL_MICFIL_RATES SNDRV_PCM_RATE_8000_48000
-#define FSL_MICFIL_FORMATS (SNDRV_PCM_FMTBIT_S16_LE)
-
#define MICFIL_OSR_DEFAULT 16
enum quality {
@@ -348,8 +345,8 @@ static struct snd_soc_dai_driver fsl_micfil_dai = {
.stream_name = "CPU-Capture",
.channels_min = 1,
.channels_max = 8,
- .rates = FSL_MICFIL_RATES,
- .formats = FSL_MICFIL_FORMATS,
+ .rates = SNDRV_PCM_RATE_8000_48000,
+ .formats = SNDRV_PCM_FMTBIT_S16_LE,
},
.ops = &fsl_micfil_dai_ops,
};
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 18/19] ASoC: fsl_micfil: drop support for undocumented property
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
The "fsl,shared-interrupt" property is undocumented and unnecessary.
Just pass IRQF_SHARED unconditionally.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 7a2af7d34dadc..99e25761008b1 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -552,7 +552,6 @@ static int fsl_micfil_probe(struct platform_device *pdev)
struct resource *res;
void __iomem *regs;
int ret, i;
- unsigned long irqflag = 0;
micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
if (!micfil)
@@ -616,12 +615,9 @@ static int fsl_micfil_probe(struct platform_device *pdev)
return micfil->irq[i];
}
- if (of_property_read_bool(np, "fsl,shared-interrupt"))
- irqflag = IRQF_SHARED;
-
/* Digital Microphone interface interrupt */
ret = devm_request_irq(&pdev->dev, micfil->irq[0],
- micfil_isr, irqflag,
+ micfil_isr, IRQF_SHARED,
micfil->name, micfil);
if (ret) {
dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
@@ -631,7 +627,7 @@ static int fsl_micfil_probe(struct platform_device *pdev)
/* Digital Microphone interface error interrupt */
ret = devm_request_irq(&pdev->dev, micfil->irq[1],
- micfil_err_isr, irqflag,
+ micfil_err_isr, IRQF_SHARED,
micfil->name, micfil);
if (ret) {
dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 18/19] ASoC: fsl_micfil: drop support for undocumented property
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
The "fsl,shared-interrupt" property is undocumented and unnecessary.
Just pass IRQF_SHARED unconditionally.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 8 ++------
1 file changed, 2 insertions(+), 6 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 7a2af7d34dadc..99e25761008b1 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -552,7 +552,6 @@ static int fsl_micfil_probe(struct platform_device *pdev)
struct resource *res;
void __iomem *regs;
int ret, i;
- unsigned long irqflag = 0;
micfil = devm_kzalloc(&pdev->dev, sizeof(*micfil), GFP_KERNEL);
if (!micfil)
@@ -616,12 +615,9 @@ static int fsl_micfil_probe(struct platform_device *pdev)
return micfil->irq[i];
}
- if (of_property_read_bool(np, "fsl,shared-interrupt"))
- irqflag = IRQF_SHARED;
-
/* Digital Microphone interface interrupt */
ret = devm_request_irq(&pdev->dev, micfil->irq[0],
- micfil_isr, irqflag,
+ micfil_isr, IRQF_SHARED,
micfil->name, micfil);
if (ret) {
dev_err(&pdev->dev, "failed to claim mic interface irq %u\n",
@@ -631,7 +627,7 @@ static int fsl_micfil_probe(struct platform_device *pdev)
/* Digital Microphone interface error interrupt */
ret = devm_request_irq(&pdev->dev, micfil->irq[1],
- micfil_err_isr, irqflag,
+ micfil_err_isr, IRQF_SHARED,
micfil->name, micfil);
if (ret) {
dev_err(&pdev->dev, "failed to claim mic interface error irq %u\n",
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 19/19] ASoC: fsl_micfil: fold fsl_set_clock_params() into its only user
2022-03-17 8:27 ` Sascha Hauer
@ 2022-03-17 8:28 ` Sascha Hauer
-1 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel, Vinod Koul,
NXP Linux Team, dmaengine, Sascha Hauer
fsl_set_clock_params() is used only once and easily be folded into its
caller, do so.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 41 ++++++++++++--------------------------
1 file changed, 13 insertions(+), 28 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 99e25761008b1..79f6deb2ba821 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -252,29 +252,6 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
return 0;
}
-static int fsl_set_clock_params(struct device *dev, unsigned int rate)
-{
- struct fsl_micfil *micfil = dev_get_drvdata(dev);
- int clk_div = 8;
- int osr = MICFIL_OSR_DEFAULT;
- int ret;
-
- ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
- if (ret)
- return ret;
-
- ret = micfil_set_quality(micfil);
- if (ret)
- return ret;
-
- ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
- MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
- FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
- FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
-
- return ret;
-}
-
static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
@@ -282,7 +259,8 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
unsigned int channels = params_channels(params);
unsigned int rate = params_rate(params);
- struct device *dev = &micfil->pdev->dev;
+ int clk_div = 8;
+ int osr = MICFIL_OSR_DEFAULT;
int ret;
/* 1. Disable the module */
@@ -297,11 +275,18 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
if (ret)
return ret;
- ret = fsl_set_clock_params(dev, rate);
- if (ret < 0) {
- dev_err(dev, "Failed to set clock parameters [%d]\n", ret);
+ ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
+ if (ret)
return ret;
- }
+
+ ret = micfil_set_quality(micfil);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
+ MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
+ FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
+ FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* [PATCH 19/19] ASoC: fsl_micfil: fold fsl_set_clock_params() into its only user
@ 2022-03-17 8:28 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 8:28 UTC (permalink / raw)
To: alsa-devel
Cc: Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Shengjiu Wang
fsl_set_clock_params() is used only once and easily be folded into its
caller, do so.
Signed-off-by: Sascha Hauer <s.hauer@pengutronix.de>
---
sound/soc/fsl/fsl_micfil.c | 41 ++++++++++++--------------------------
1 file changed, 13 insertions(+), 28 deletions(-)
diff --git a/sound/soc/fsl/fsl_micfil.c b/sound/soc/fsl/fsl_micfil.c
index 99e25761008b1..79f6deb2ba821 100644
--- a/sound/soc/fsl/fsl_micfil.c
+++ b/sound/soc/fsl/fsl_micfil.c
@@ -252,29 +252,6 @@ static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
return 0;
}
-static int fsl_set_clock_params(struct device *dev, unsigned int rate)
-{
- struct fsl_micfil *micfil = dev_get_drvdata(dev);
- int clk_div = 8;
- int osr = MICFIL_OSR_DEFAULT;
- int ret;
-
- ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
- if (ret)
- return ret;
-
- ret = micfil_set_quality(micfil);
- if (ret)
- return ret;
-
- ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
- MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
- FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
- FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
-
- return ret;
-}
-
static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
struct snd_pcm_hw_params *params,
struct snd_soc_dai *dai)
@@ -282,7 +259,8 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
unsigned int channels = params_channels(params);
unsigned int rate = params_rate(params);
- struct device *dev = &micfil->pdev->dev;
+ int clk_div = 8;
+ int osr = MICFIL_OSR_DEFAULT;
int ret;
/* 1. Disable the module */
@@ -297,11 +275,18 @@ static int fsl_micfil_hw_params(struct snd_pcm_substream *substream,
if (ret)
return ret;
- ret = fsl_set_clock_params(dev, rate);
- if (ret < 0) {
- dev_err(dev, "Failed to set clock parameters [%d]\n", ret);
+ ret = clk_set_rate(micfil->mclk, rate * clk_div * osr * 8);
+ if (ret)
return ret;
- }
+
+ ret = micfil_set_quality(micfil);
+ if (ret)
+ return ret;
+
+ ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL2,
+ MICFIL_CTRL2_CLKDIV | MICFIL_CTRL2_CICOSR,
+ FIELD_PREP(MICFIL_CTRL2_CLKDIV, clk_div) |
+ FIELD_PREP(MICFIL_CTRL2_CICOSR, 16 - osr));
micfil->dma_params_rx.peripheral_config = &micfil->sdmacfg;
micfil->dma_params_rx.peripheral_size = sizeof(micfil->sdmacfg);
--
2.30.2
^ permalink raw reply related [flat|nested] 48+ messages in thread
* Re: [PATCH 10/19] dma: imx-sdma: Add multi fifo support
[not found] ` <CAA+D8APw-OHdz4s=oy9bWZOw6kj8mD8nss3OKXsYQty52=tb2Q@mail.gmail.com>
@ 2022-03-17 10:19 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 10:19 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, dmaengine, joy.zou
On Thu, Mar 17, 2022 at 05:08:55PM +0800, Shengjiu Wang wrote:
> On Thu, Mar 17, 2022 at 4:28 PM Sascha Hauer <[1]s.hauer@pengutronix.de>
> wrote:
>
> +struct sdma_peripheral_config {
> + int n_fifos_src;
> + int n_fifos_dst;
> + bool sw_done;
> +};
> +
> #endif
>
> Hi Sascha
> This is our internal definition for this sdma_peripheral_config.
> Could you please adopt this?
This structure is completely internal to the kernel and can be adjusted
when we need it. I don't see a reason to add unused fields to it just to
be compatible with a downstream kernel.
Sascha
> /**
> * struct sdma_audio_config - special sdma config for audio case
> * @src_fifo_num: source fifo number for mcu_2_sai/sai_2_mcu script
> * For example, if there are 4 fifos, sdma will fetch
> * fifos one by one and roll back to the first fifo after
> * the 4th fifo fetch.
> * @dst_fifo_num: similar as src_fifo_num, but dest fifo instead.
> * @src_fifo_off: source fifo offset, 0 means all fifos are continuous, 1
> * means 1 word offset between fifos. All offset between
> * fifos should be same.
> * @dst_fifo_off: dst fifo offset, similar as @src_fifo_off.
> * @words_per_fifo: numbers of words per fifo fetch/fill, 0 means
> * one channel per fifo, 1 means 2 channels per fifo..
> * If 'src_fifo_num = 4' and 'chans_per_fifo = 1', it
> * means the first two words(channels) fetch from fifo1
> * and then jump to fifo2 for next two words, and so on
> * after the last fifo4 fetched, roll back to fifo1.
> * @sw_done_sel: software done selector, PDM need enable software done
> feature
> * in mcu_2_sai/sai_2_mcu script.
> * Bit31: sw_done eanbled or not
> * Bit16~Bit0: selector
> * For example: 0x80000000 means sw_done enabled for done0
> * sector which is for PDM on i.mx8mm.
> */
> struct sdma_audio_config {
> u8 src_fifo_num;
> u8 dst_fifo_num;
> u8 src_fifo_off;
> u8 dst_fifo_off;
> u8 words_per_fifo;
> u32 sw_done_sel;
> };
> best regards
> wang shengjiu
>
>
> References
>
> Visible links
> 1. mailto:s.hauer@pengutronix.de
> 2. mailto:s.hauer@pengutronix.de
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 10/19] dma: imx-sdma: Add multi fifo support
@ 2022-03-17 10:19 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 10:19 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, Xiubo Li, Vinod Koul, NXP Linux Team, Sascha Hauer,
dmaengine, Fabio Estevam, joy.zou
On Thu, Mar 17, 2022 at 05:08:55PM +0800, Shengjiu Wang wrote:
> On Thu, Mar 17, 2022 at 4:28 PM Sascha Hauer <[1]s.hauer@pengutronix.de>
> wrote:
>
> +struct sdma_peripheral_config {
> + int n_fifos_src;
> + int n_fifos_dst;
> + bool sw_done;
> +};
> +
> #endif
>
> Hi Sascha
> This is our internal definition for this sdma_peripheral_config.
> Could you please adopt this?
This structure is completely internal to the kernel and can be adjusted
when we need it. I don't see a reason to add unused fields to it just to
be compatible with a downstream kernel.
Sascha
> /**
> * struct sdma_audio_config - special sdma config for audio case
> * @src_fifo_num: source fifo number for mcu_2_sai/sai_2_mcu script
> * For example, if there are 4 fifos, sdma will fetch
> * fifos one by one and roll back to the first fifo after
> * the 4th fifo fetch.
> * @dst_fifo_num: similar as src_fifo_num, but dest fifo instead.
> * @src_fifo_off: source fifo offset, 0 means all fifos are continuous, 1
> * means 1 word offset between fifos. All offset between
> * fifos should be same.
> * @dst_fifo_off: dst fifo offset, similar as @src_fifo_off.
> * @words_per_fifo: numbers of words per fifo fetch/fill, 0 means
> * one channel per fifo, 1 means 2 channels per fifo..
> * If 'src_fifo_num = 4' and 'chans_per_fifo = 1', it
> * means the first two words(channels) fetch from fifo1
> * and then jump to fifo2 for next two words, and so on
> * after the last fifo4 fetched, roll back to fifo1.
> * @sw_done_sel: software done selector, PDM need enable software done
> feature
> * in mcu_2_sai/sai_2_mcu script.
> * Bit31: sw_done eanbled or not
> * Bit16~Bit0: selector
> * For example: 0x80000000 means sw_done enabled for done0
> * sector which is for PDM on i.mx8mm.
> */
> struct sdma_audio_config {
> u8 src_fifo_num;
> u8 dst_fifo_num;
> u8 src_fifo_off;
> u8 dst_fifo_off;
> u8 words_per_fifo;
> u32 sw_done_sel;
> };
> best regards
> wang shengjiu
>
>
> References
>
> Visible links
> 1. mailto:s.hauer@pengutronix.de
> 2. mailto:s.hauer@pengutronix.de
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 10/19] dma: imx-sdma: Add multi fifo support
[not found] ` <CAA+D8AMdTzqfEQCH4pcQE3K1P-4oo71ctiGW1DD7XJPQDcVbTg@mail.gmail.com>
@ 2022-03-17 14:41 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 14:41 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, dmaengine, joy.zou
On Thu, Mar 17, 2022 at 08:20:22PM +0800, Shengjiu Wang wrote:
> Hi
> On Thu, Mar 17, 2022 at 6:19 PM Sascha Hauer <[1]s.hauer@pengutronix.de>
> wrote:
>
> On Thu, Mar 17, 2022 at 05:08:55PM +0800, Shengjiu Wang wrote:
> > On Thu, Mar 17, 2022 at 4:28 PM Sascha Hauer
> <[1][2]s.hauer@pengutronix.de>
> > wrote:
> >
> > +struct sdma_peripheral_config {
> > + int n_fifos_src;
> > + int n_fifos_dst;
> > + bool sw_done;
> > +};
> > +
> > #endif
> >
> > Hi Sascha
> > This is our internal definition for this sdma_peripheral_config.
> > Could you please adopt this?
>
> This structure is completely internal to the kernel and can be adjusted
> when we need it. I don't see a reason to add unused fields to it just to
> be compatible with a downstream kernel.
>
> Yes, it is not used by micfil. But the fifo_offset and words_per_fifo
> is part the multi fifo script support scope, if only add fifo_num, it
> looks
> like this feature is not complete.
No, it's not. I only added the parts that I am interested in and that I
can test. I have some multichannel audio stuff in my pipeline, I might add
more pieces later.
> By the way, which multi fifo script version are you using? seems it is
> not the latest compared with our release, right?
I am using the latest firmware from linux-firmware.git.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 10/19] dma: imx-sdma: Add multi fifo support
@ 2022-03-17 14:41 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-17 14:41 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, Xiubo Li, Vinod Koul, NXP Linux Team, Sascha Hauer,
dmaengine, Fabio Estevam, joy.zou
On Thu, Mar 17, 2022 at 08:20:22PM +0800, Shengjiu Wang wrote:
> Hi
> On Thu, Mar 17, 2022 at 6:19 PM Sascha Hauer <[1]s.hauer@pengutronix.de>
> wrote:
>
> On Thu, Mar 17, 2022 at 05:08:55PM +0800, Shengjiu Wang wrote:
> > On Thu, Mar 17, 2022 at 4:28 PM Sascha Hauer
> <[1][2]s.hauer@pengutronix.de>
> > wrote:
> >
> > +struct sdma_peripheral_config {
> > + int n_fifos_src;
> > + int n_fifos_dst;
> > + bool sw_done;
> > +};
> > +
> > #endif
> >
> > Hi Sascha
> > This is our internal definition for this sdma_peripheral_config.
> > Could you please adopt this?
>
> This structure is completely internal to the kernel and can be adjusted
> when we need it. I don't see a reason to add unused fields to it just to
> be compatible with a downstream kernel.
>
> Yes, it is not used by micfil. But the fifo_offset and words_per_fifo
> is part the multi fifo script support scope, if only add fifo_num, it
> looks
> like this feature is not complete.
No, it's not. I only added the parts that I am interested in and that I
can test. I have some multichannel audio stuff in my pipeline, I might add
more pieces later.
> By the way, which multi fifo script version are you using? seems it is
> not the latest compared with our release, right?
I am using the latest firmware from linux-firmware.git.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 05/19] ASoC: fsl_micfil: use GENMASK to define register bit fields
2022-03-17 8:28 ` Sascha Hauer
@ 2022-03-17 17:06 ` kernel test robot
-1 siblings, 0 replies; 48+ messages in thread
From: kernel test robot @ 2022-03-17 17:06 UTC (permalink / raw)
To: Sascha Hauer, alsa-devel
Cc: kbuild-all, Xiubo Li, Fabio Estevam, Shengjiu Wang, kernel,
Vinod Koul, NXP Linux Team, dmaengine, Sascha Hauer
Hi Sascha,
I love your patch! Yet something to improve:
[auto build test ERROR on broonie-sound/for-next]
[also build test ERROR on shawnguo/for-next vkoul-dmaengine/next v5.17-rc8]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Sascha-Hauer/ASoC-fsl_micfil-Driver-updates/20220317-163034
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
config: nds32-randconfig-r026-20220317 (https://download.01.org/0day-ci/archive/20220318/202203180058.UK8cEQvk-lkp@intel.com/config)
compiler: nds32le-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/efbc0b5535c7612d0e3ac5473c86e66c7d0bd7a6
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Sascha-Hauer/ASoC-fsl_micfil-Driver-updates/20220317-163034
git checkout efbc0b5535c7612d0e3ac5473c86e66c7d0bd7a6
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=nds32 SHELL=/bin/bash sound/soc/fsl/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
sound/soc/fsl/fsl_micfil.c: In function 'get_pdm_clk':
>> sound/soc/fsl/fsl_micfil.c:119:20: error: implicit declaration of function 'FIELD_GET'; did you mean 'FOLL_GET'? [-Werror=implicit-function-declaration]
119 | osr = 16 - FIELD_GET(MICFIL_CTRL2_CICOSR, ctrl2_reg);
| ^~~~~~~~~
| FOLL_GET
sound/soc/fsl/fsl_micfil.c: In function 'fsl_micfil_trigger':
>> sound/soc/fsl/fsl_micfil.c:247:33: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
247 | FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
| ^~~~~~~~~~
cc1: some warnings being treated as errors
vim +119 sound/soc/fsl/fsl_micfil.c
110
111 static inline int get_pdm_clk(struct fsl_micfil *micfil,
112 unsigned int rate)
113 {
114 u32 ctrl2_reg;
115 int qsel, osr;
116 int bclk;
117
118 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
> 119 osr = 16 - FIELD_GET(MICFIL_CTRL2_CICOSR, ctrl2_reg);
120 qsel = FIELD_GET(MICFIL_CTRL2_QSEL, ctrl2_reg);
121
122 switch (qsel) {
123 case MICFIL_QSEL_HIGH_QUALITY:
124 bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
125 break;
126 case MICFIL_QSEL_MEDIUM_QUALITY:
127 case MICFIL_QSEL_VLOW0_QUALITY:
128 bclk = rate * 4 * osr * 1; /* kfactor = 1 */
129 break;
130 case MICFIL_QSEL_LOW_QUALITY:
131 case MICFIL_QSEL_VLOW1_QUALITY:
132 bclk = rate * 2 * osr * 2; /* kfactor = 2 */
133 break;
134 case MICFIL_QSEL_VLOW2_QUALITY:
135 bclk = rate * osr * 4; /* kfactor = 4 */
136 break;
137 default:
138 dev_err(&micfil->pdev->dev,
139 "Please make sure you select a valid quality.\n");
140 bclk = -1;
141 break;
142 }
143
144 return bclk;
145 }
146
147 static inline int get_clk_div(struct fsl_micfil *micfil,
148 unsigned int rate)
149 {
150 long mclk_rate;
151 int clk_div;
152
153 mclk_rate = clk_get_rate(micfil->mclk);
154
155 clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
156
157 return clk_div;
158 }
159
160 /* The SRES is a self-negated bit which provides the CPU with the
161 * capability to initialize the PDM Interface module through the
162 * slave-bus interface. This bit always reads as zero, and this
163 * bit is only effective when MDIS is cleared
164 */
165 static int fsl_micfil_reset(struct device *dev)
166 {
167 struct fsl_micfil *micfil = dev_get_drvdata(dev);
168 int ret;
169
170 ret = regmap_update_bits(micfil->regmap,
171 REG_MICFIL_CTRL1,
172 MICFIL_CTRL1_MDIS,
173 0);
174 if (ret) {
175 dev_err(dev, "failed to clear MDIS bit %d\n", ret);
176 return ret;
177 }
178
179 ret = regmap_update_bits(micfil->regmap,
180 REG_MICFIL_CTRL1,
181 MICFIL_CTRL1_SRES,
182 MICFIL_CTRL1_SRES);
183 if (ret) {
184 dev_err(dev, "failed to reset MICFIL: %d\n", ret);
185 return ret;
186 }
187
188 return 0;
189 }
190
191 static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
192 unsigned int freq)
193 {
194 struct device *dev = &micfil->pdev->dev;
195 int ret;
196
197 clk_disable_unprepare(micfil->mclk);
198
199 ret = clk_set_rate(micfil->mclk, freq * 1024);
200 if (ret)
201 dev_warn(dev, "failed to set rate (%u): %d\n",
202 freq * 1024, ret);
203
204 clk_prepare_enable(micfil->mclk);
205
206 return ret;
207 }
208
209 static int fsl_micfil_startup(struct snd_pcm_substream *substream,
210 struct snd_soc_dai *dai)
211 {
212 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
213
214 if (!micfil) {
215 dev_err(dai->dev, "micfil dai priv_data not set\n");
216 return -EINVAL;
217 }
218
219 return 0;
220 }
221
222 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
223 struct snd_soc_dai *dai)
224 {
225 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
226 struct device *dev = &micfil->pdev->dev;
227 int ret;
228
229 switch (cmd) {
230 case SNDRV_PCM_TRIGGER_START:
231 case SNDRV_PCM_TRIGGER_RESUME:
232 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
233 ret = fsl_micfil_reset(dev);
234 if (ret) {
235 dev_err(dev, "failed to soft reset\n");
236 return ret;
237 }
238
239 /* DMA Interrupt Selection - DISEL bits
240 * 00 - DMA and IRQ disabled
241 * 01 - DMA req enabled
242 * 10 - IRQ enabled
243 * 11 - reserved
244 */
245 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
246 MICFIL_CTRL1_DISEL,
> 247 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
248 if (ret) {
249 dev_err(dev, "failed to update DISEL bits\n");
250 return ret;
251 }
252
253 /* Enable the module */
254 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
255 MICFIL_CTRL1_PDMIEN,
256 MICFIL_CTRL1_PDMIEN);
257 if (ret) {
258 dev_err(dev, "failed to enable the module\n");
259 return ret;
260 }
261
262 break;
263 case SNDRV_PCM_TRIGGER_STOP:
264 case SNDRV_PCM_TRIGGER_SUSPEND:
265 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
266 /* Disable the module */
267 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
268 MICFIL_CTRL1_PDMIEN,
269 0);
270 if (ret) {
271 dev_err(dev, "failed to enable the module\n");
272 return ret;
273 }
274
275 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
276 MICFIL_CTRL1_DISEL,
277 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
278 if (ret) {
279 dev_err(dev, "failed to update DISEL bits\n");
280 return ret;
281 }
282 break;
283 default:
284 return -EINVAL;
285 }
286 return 0;
287 }
288
---
0-DAY CI Kernel Test Service
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 05/19] ASoC: fsl_micfil: use GENMASK to define register bit fields
@ 2022-03-17 17:06 ` kernel test robot
0 siblings, 0 replies; 48+ messages in thread
From: kernel test robot @ 2022-03-17 17:06 UTC (permalink / raw)
To: Sascha Hauer, alsa-devel
Cc: kbuild-all, Xiubo Li, Shengjiu Wang, Sascha Hauer, Vinod Koul,
NXP Linux Team, kernel, dmaengine, Fabio Estevam
Hi Sascha,
I love your patch! Yet something to improve:
[auto build test ERROR on broonie-sound/for-next]
[also build test ERROR on shawnguo/for-next vkoul-dmaengine/next v5.17-rc8]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/0day-ci/linux/commits/Sascha-Hauer/ASoC-fsl_micfil-Driver-updates/20220317-163034
base: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/sound.git for-next
config: nds32-randconfig-r026-20220317 (https://download.01.org/0day-ci/archive/20220318/202203180058.UK8cEQvk-lkp@intel.com/config)
compiler: nds32le-linux-gcc (GCC) 11.2.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/0day-ci/linux/commit/efbc0b5535c7612d0e3ac5473c86e66c7d0bd7a6
git remote add linux-review https://github.com/0day-ci/linux
git fetch --no-tags linux-review Sascha-Hauer/ASoC-fsl_micfil-Driver-updates/20220317-163034
git checkout efbc0b5535c7612d0e3ac5473c86e66c7d0bd7a6
# save the config file to linux build tree
mkdir build_dir
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.2.0 make.cross O=build_dir ARCH=nds32 SHELL=/bin/bash sound/soc/fsl/
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
sound/soc/fsl/fsl_micfil.c: In function 'get_pdm_clk':
>> sound/soc/fsl/fsl_micfil.c:119:20: error: implicit declaration of function 'FIELD_GET'; did you mean 'FOLL_GET'? [-Werror=implicit-function-declaration]
119 | osr = 16 - FIELD_GET(MICFIL_CTRL2_CICOSR, ctrl2_reg);
| ^~~~~~~~~
| FOLL_GET
sound/soc/fsl/fsl_micfil.c: In function 'fsl_micfil_trigger':
>> sound/soc/fsl/fsl_micfil.c:247:33: error: implicit declaration of function 'FIELD_PREP' [-Werror=implicit-function-declaration]
247 | FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
| ^~~~~~~~~~
cc1: some warnings being treated as errors
vim +119 sound/soc/fsl/fsl_micfil.c
110
111 static inline int get_pdm_clk(struct fsl_micfil *micfil,
112 unsigned int rate)
113 {
114 u32 ctrl2_reg;
115 int qsel, osr;
116 int bclk;
117
118 regmap_read(micfil->regmap, REG_MICFIL_CTRL2, &ctrl2_reg);
> 119 osr = 16 - FIELD_GET(MICFIL_CTRL2_CICOSR, ctrl2_reg);
120 qsel = FIELD_GET(MICFIL_CTRL2_QSEL, ctrl2_reg);
121
122 switch (qsel) {
123 case MICFIL_QSEL_HIGH_QUALITY:
124 bclk = rate * 8 * osr / 2; /* kfactor = 0.5 */
125 break;
126 case MICFIL_QSEL_MEDIUM_QUALITY:
127 case MICFIL_QSEL_VLOW0_QUALITY:
128 bclk = rate * 4 * osr * 1; /* kfactor = 1 */
129 break;
130 case MICFIL_QSEL_LOW_QUALITY:
131 case MICFIL_QSEL_VLOW1_QUALITY:
132 bclk = rate * 2 * osr * 2; /* kfactor = 2 */
133 break;
134 case MICFIL_QSEL_VLOW2_QUALITY:
135 bclk = rate * osr * 4; /* kfactor = 4 */
136 break;
137 default:
138 dev_err(&micfil->pdev->dev,
139 "Please make sure you select a valid quality.\n");
140 bclk = -1;
141 break;
142 }
143
144 return bclk;
145 }
146
147 static inline int get_clk_div(struct fsl_micfil *micfil,
148 unsigned int rate)
149 {
150 long mclk_rate;
151 int clk_div;
152
153 mclk_rate = clk_get_rate(micfil->mclk);
154
155 clk_div = mclk_rate / (get_pdm_clk(micfil, rate) * 2);
156
157 return clk_div;
158 }
159
160 /* The SRES is a self-negated bit which provides the CPU with the
161 * capability to initialize the PDM Interface module through the
162 * slave-bus interface. This bit always reads as zero, and this
163 * bit is only effective when MDIS is cleared
164 */
165 static int fsl_micfil_reset(struct device *dev)
166 {
167 struct fsl_micfil *micfil = dev_get_drvdata(dev);
168 int ret;
169
170 ret = regmap_update_bits(micfil->regmap,
171 REG_MICFIL_CTRL1,
172 MICFIL_CTRL1_MDIS,
173 0);
174 if (ret) {
175 dev_err(dev, "failed to clear MDIS bit %d\n", ret);
176 return ret;
177 }
178
179 ret = regmap_update_bits(micfil->regmap,
180 REG_MICFIL_CTRL1,
181 MICFIL_CTRL1_SRES,
182 MICFIL_CTRL1_SRES);
183 if (ret) {
184 dev_err(dev, "failed to reset MICFIL: %d\n", ret);
185 return ret;
186 }
187
188 return 0;
189 }
190
191 static int fsl_micfil_set_mclk_rate(struct fsl_micfil *micfil,
192 unsigned int freq)
193 {
194 struct device *dev = &micfil->pdev->dev;
195 int ret;
196
197 clk_disable_unprepare(micfil->mclk);
198
199 ret = clk_set_rate(micfil->mclk, freq * 1024);
200 if (ret)
201 dev_warn(dev, "failed to set rate (%u): %d\n",
202 freq * 1024, ret);
203
204 clk_prepare_enable(micfil->mclk);
205
206 return ret;
207 }
208
209 static int fsl_micfil_startup(struct snd_pcm_substream *substream,
210 struct snd_soc_dai *dai)
211 {
212 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
213
214 if (!micfil) {
215 dev_err(dai->dev, "micfil dai priv_data not set\n");
216 return -EINVAL;
217 }
218
219 return 0;
220 }
221
222 static int fsl_micfil_trigger(struct snd_pcm_substream *substream, int cmd,
223 struct snd_soc_dai *dai)
224 {
225 struct fsl_micfil *micfil = snd_soc_dai_get_drvdata(dai);
226 struct device *dev = &micfil->pdev->dev;
227 int ret;
228
229 switch (cmd) {
230 case SNDRV_PCM_TRIGGER_START:
231 case SNDRV_PCM_TRIGGER_RESUME:
232 case SNDRV_PCM_TRIGGER_PAUSE_RELEASE:
233 ret = fsl_micfil_reset(dev);
234 if (ret) {
235 dev_err(dev, "failed to soft reset\n");
236 return ret;
237 }
238
239 /* DMA Interrupt Selection - DISEL bits
240 * 00 - DMA and IRQ disabled
241 * 01 - DMA req enabled
242 * 10 - IRQ enabled
243 * 11 - reserved
244 */
245 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
246 MICFIL_CTRL1_DISEL,
> 247 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DMA));
248 if (ret) {
249 dev_err(dev, "failed to update DISEL bits\n");
250 return ret;
251 }
252
253 /* Enable the module */
254 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
255 MICFIL_CTRL1_PDMIEN,
256 MICFIL_CTRL1_PDMIEN);
257 if (ret) {
258 dev_err(dev, "failed to enable the module\n");
259 return ret;
260 }
261
262 break;
263 case SNDRV_PCM_TRIGGER_STOP:
264 case SNDRV_PCM_TRIGGER_SUSPEND:
265 case SNDRV_PCM_TRIGGER_PAUSE_PUSH:
266 /* Disable the module */
267 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
268 MICFIL_CTRL1_PDMIEN,
269 0);
270 if (ret) {
271 dev_err(dev, "failed to enable the module\n");
272 return ret;
273 }
274
275 ret = regmap_update_bits(micfil->regmap, REG_MICFIL_CTRL1,
276 MICFIL_CTRL1_DISEL,
277 FIELD_PREP(MICFIL_CTRL1_DISEL, MICFIL_CTRL1_DISEL_DISABLE));
278 if (ret) {
279 dev_err(dev, "failed to update DISEL bits\n");
280 return ret;
281 }
282 break;
283 default:
284 return -EINVAL;
285 }
286 return 0;
287 }
288
---
0-DAY CI Kernel Test Service
https://lists.01.org/hyperkitty/list/kbuild-all@lists.01.org
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 10/19] dma: imx-sdma: Add multi fifo support
[not found] ` <CAA+D8AM5bm3Hncrf0=xdPNpC_rz_yMbokN6J-8z4tHi7-==jgA@mail.gmail.com>
@ 2022-03-18 8:04 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-18 8:04 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, Xiubo Li, Fabio Estevam, Sascha Hauer, Vinod Koul,
NXP Linux Team, dmaengine
On Fri, Mar 18, 2022 at 01:42:51PM +0800, Shengjiu Wang wrote:
> Hi
> On Thu, Mar 17, 2022 at 4:28 PM Sascha Hauer <[1]s.hauer@pengutronix.de>
> wrote:
>
> Signed-off-by: Sascha Hauer <[2]s.hauer@pengutronix.de>
> ---
> drivers/dma/imx-sdma.c | 54 +++++++++++++++++++++++++++
> include/linux/platform_data/dma-imx.h | 7 ++++
> 2 files changed, 61 insertions(+)
>
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index 1038f6bc7f846..21e1cec2ffde9 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -14,6 +14,7 @@
> #include <linux/iopoll.h>
> #include <linux/module.h>
> #include <linux/types.h>
> +#include <linux/bitfield.h>
> #include <linux/bitops.h>
> #include <linux/mm.h>
> #include <linux/interrupt.h>
> @@ -73,6 +74,7 @@
> #define SDMA_CHNENBL0_IMX35 0x200
> #define SDMA_CHNENBL0_IMX31 0x080
> #define SDMA_CHNPRI_0 0x100
> +#define SDMA_DONE0_CONFIG 0x1000
>
> /*
> * Buffer descriptor status values.
> @@ -180,6 +182,12 @@
> BIT(DMA_MEM_TO_DEV) | \
> BIT(DMA_DEV_TO_DEV))
>
> +#define SDMA_WATERMARK_LEVEL_N_FIFOS GENMASK(15, 12)
> +#define SDMA_WATERMARK_LEVEL_SW_DONE BIT(23)
> +
> +#define SDMA_DONE0_CONFIG_DONE_SEL BIT(7)
> +#define SDMA_DONE0_CONFIG_DONE_DIS BIT(6)
> +
> /**
> * struct sdma_script_start_addrs - SDMA script start pointers
> *
> @@ -441,6 +449,11 @@ struct sdma_channel {
> struct work_struct terminate_worker;
> struct list_head terminated;
> bool is_ram_script;
> + unsigned int n_fifos;
> + unsigned int n_fifos_src;
> + unsigned int n_fifos_dst;
> + bool sw_done;
> + u32 sw_done_sel;
>
> "sw_done_sel" is not used, and may not be needed.
Ok, will drop.
> And can we just add 'struct sdma_peripheral_config *pconfig'
> to replace each item here ('n_fifos_src', 'n_fifos_dst',
> 'sw_done')?
I rather do not access the pointer to the peripheral_config outside of
sdma_config because I know nothing about the lifetime of that structure.
> the pconfig can point to the struct in dma_slave_config.
> And 'n_fifos' can be moved to locally function in
> sdma_set_watermarklevel_for_sais(), then use sdmac->direction
> to select 'n_fifos_dst' or 'n_fifos_src'.
Ok.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 48+ messages in thread
* Re: [PATCH 10/19] dma: imx-sdma: Add multi fifo support
@ 2022-03-18 8:04 ` Sascha Hauer
0 siblings, 0 replies; 48+ messages in thread
From: Sascha Hauer @ 2022-03-18 8:04 UTC (permalink / raw)
To: Shengjiu Wang
Cc: alsa-devel, Xiubo Li, Vinod Koul, NXP Linux Team, Sascha Hauer,
dmaengine, Fabio Estevam
On Fri, Mar 18, 2022 at 01:42:51PM +0800, Shengjiu Wang wrote:
> Hi
> On Thu, Mar 17, 2022 at 4:28 PM Sascha Hauer <[1]s.hauer@pengutronix.de>
> wrote:
>
> Signed-off-by: Sascha Hauer <[2]s.hauer@pengutronix.de>
> ---
> drivers/dma/imx-sdma.c | 54 +++++++++++++++++++++++++++
> include/linux/platform_data/dma-imx.h | 7 ++++
> 2 files changed, 61 insertions(+)
>
> diff --git a/drivers/dma/imx-sdma.c b/drivers/dma/imx-sdma.c
> index 1038f6bc7f846..21e1cec2ffde9 100644
> --- a/drivers/dma/imx-sdma.c
> +++ b/drivers/dma/imx-sdma.c
> @@ -14,6 +14,7 @@
> #include <linux/iopoll.h>
> #include <linux/module.h>
> #include <linux/types.h>
> +#include <linux/bitfield.h>
> #include <linux/bitops.h>
> #include <linux/mm.h>
> #include <linux/interrupt.h>
> @@ -73,6 +74,7 @@
> #define SDMA_CHNENBL0_IMX35 0x200
> #define SDMA_CHNENBL0_IMX31 0x080
> #define SDMA_CHNPRI_0 0x100
> +#define SDMA_DONE0_CONFIG 0x1000
>
> /*
> * Buffer descriptor status values.
> @@ -180,6 +182,12 @@
> BIT(DMA_MEM_TO_DEV) | \
> BIT(DMA_DEV_TO_DEV))
>
> +#define SDMA_WATERMARK_LEVEL_N_FIFOS GENMASK(15, 12)
> +#define SDMA_WATERMARK_LEVEL_SW_DONE BIT(23)
> +
> +#define SDMA_DONE0_CONFIG_DONE_SEL BIT(7)
> +#define SDMA_DONE0_CONFIG_DONE_DIS BIT(6)
> +
> /**
> * struct sdma_script_start_addrs - SDMA script start pointers
> *
> @@ -441,6 +449,11 @@ struct sdma_channel {
> struct work_struct terminate_worker;
> struct list_head terminated;
> bool is_ram_script;
> + unsigned int n_fifos;
> + unsigned int n_fifos_src;
> + unsigned int n_fifos_dst;
> + bool sw_done;
> + u32 sw_done_sel;
>
> "sw_done_sel" is not used, and may not be needed.
Ok, will drop.
> And can we just add 'struct sdma_peripheral_config *pconfig'
> to replace each item here ('n_fifos_src', 'n_fifos_dst',
> 'sw_done')?
I rather do not access the pointer to the peripheral_config outside of
sdma_config because I know nothing about the lifetime of that structure.
> the pconfig can point to the struct in dma_slave_config.
> And 'n_fifos' can be moved to locally function in
> sdma_set_watermarklevel_for_sais(), then use sdmac->direction
> to select 'n_fifos_dst' or 'n_fifos_src'.
Ok.
Sascha
--
Pengutronix e.K. | |
Steuerwalder Str. 21 | http://www.pengutronix.de/ |
31137 Hildesheim, Germany | Phone: +49-5121-206917-0 |
Amtsgericht Hildesheim, HRA 2686 | Fax: +49-5121-206917-5555 |
^ permalink raw reply [flat|nested] 48+ messages in thread
end of thread, other threads:[~2022-03-18 8:05 UTC | newest]
Thread overview: 48+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-17 8:27 [PATCH 00/19] ASoC: fsl_micfil: Driver updates Sascha Hauer
2022-03-17 8:27 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 01/19] ASoC: fsl_micfil: Drop unnecessary register read Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 02/19] ASoC: fsl_micfil: Drop unused " Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 03/19] ASoC: fsl_micfil: drop fsl_micfil_set_mclk_rate() Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 04/19] ASoC: fsl_micfil: do not define SHIFT/MASK for single bits Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 05/19] ASoC: fsl_micfil: use GENMASK to define register bit fields Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 17:06 ` kernel test robot
2022-03-17 17:06 ` kernel test robot
2022-03-17 8:28 ` [PATCH 06/19] ASoC: fsl_micfil: use clear/set bits Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 07/19] ASoC: fsl_micfil: drop error messages from failed register accesses Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 08/19] ASoC: fsl_micfil: drop unused variables Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 09/19] dma: imx-sdma: error out on unsupported transfer types Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 10/19] dma: imx-sdma: Add multi fifo support Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
[not found] ` <CAA+D8APw-OHdz4s=oy9bWZOw6kj8mD8nss3OKXsYQty52=tb2Q@mail.gmail.com>
2022-03-17 10:19 ` Sascha Hauer
2022-03-17 10:19 ` Sascha Hauer
[not found] ` <CAA+D8AMdTzqfEQCH4pcQE3K1P-4oo71ctiGW1DD7XJPQDcVbTg@mail.gmail.com>
2022-03-17 14:41 ` Sascha Hauer
2022-03-17 14:41 ` Sascha Hauer
[not found] ` <CAA+D8AM5bm3Hncrf0=xdPNpC_rz_yMbokN6J-8z4tHi7-==jgA@mail.gmail.com>
2022-03-18 8:04 ` Sascha Hauer
2022-03-18 8:04 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 11/19] ASoC: fsl_micfil: add " Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 12/19] ASoC: fsl_micfil: use define for OSR default value Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 13/19] ASoC: fsl_micfil: Drop get_pdm_clk() Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 14/19] ASoC: fsl_micfil: simplify clock setting Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 15/19] ASoC: fsl_micfil: rework quality setting Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 16/19] ASoC: fsl_micfil: drop unused include Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 17/19] ASoC: fsl_micfil: drop only once used defines Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 18/19] ASoC: fsl_micfil: drop support for undocumented property Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
2022-03-17 8:28 ` [PATCH 19/19] ASoC: fsl_micfil: fold fsl_set_clock_params() into its only user Sascha Hauer
2022-03-17 8:28 ` Sascha Hauer
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