* [PATCH v4 0/2] check feature type for DFL irq parsing
@ 2022-03-18 3:16 Tianfei Zhang
2022-03-18 3:16 ` [PATCH v4 1/2] fpga: dfl: check feature type before parse irq info Tianfei Zhang
2022-03-18 3:16 ` [PATCH v4 2/2] Documentation: fpga: dfl: add description of Feature ID Tianfei Zhang
0 siblings, 2 replies; 5+ messages in thread
From: Tianfei Zhang @ 2022-03-18 3:16 UTC (permalink / raw)
To: hao.wu, trix, mdf, yilun.xu, linux-fpga, linux-doc, rdunlap
Cc: corbet, Tianfei Zhang
This patch set adds an extended usage of Feature ID for DFL.
Previously the feature IDs defined are unique, no matter
which feature type. But currently we want to extend its
usage to have a per-type feature ID space.
Patch 1 adds feature type checking before parse the irq info.
Patch 2 adds description about the Feature ID.
v4:
- Fix the git commit from Hao's comments.
- Split documentation into another patch.
v3:
- Remove "Fixes" in commit log with Hao's comment, this is a
extension not a bug fix.
v2:
- add DFL Feature ID Registry in documentation.
Tianfei zhang (2):
fpga: dfl: check feature type before parse irq info
Documentation: fpga: dfl: add description of Feature ID
Documentation/fpga/dfl.rst | 10 ++++++++++
drivers/fpga/dfl.c | 38 ++++++++++++++++++++++----------------
2 files changed, 32 insertions(+), 16 deletions(-)
--
2.26.2
^ permalink raw reply [flat|nested] 5+ messages in thread* [PATCH v4 1/2] fpga: dfl: check feature type before parse irq info 2022-03-18 3:16 [PATCH v4 0/2] check feature type for DFL irq parsing Tianfei Zhang @ 2022-03-18 3:16 ` Tianfei Zhang 2022-03-18 3:16 ` [PATCH v4 2/2] Documentation: fpga: dfl: add description of Feature ID Tianfei Zhang 1 sibling, 0 replies; 5+ messages in thread From: Tianfei Zhang @ 2022-03-18 3:16 UTC (permalink / raw) To: hao.wu, trix, mdf, yilun.xu, linux-fpga, linux-doc, rdunlap Cc: corbet, Tianfei zhang From: Tianfei zhang <tianfei.zhang@intel.com> Previously the feature IDs defined are unique, no matter which feature type. But currently we want to extend its usage to have a per-type feature ID space, so this patch adds feature type checking as well just before look into feature ID for different features which have irq info. Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com> --- v4: - Fix the git commit from Hao's comments. - Split documentation into another patch. v3: - Remove "Fixes" in commit log with Hao's comment, this is a extension not a bug fix. v2: - add DFL Feature ID Registry in documentation. --- drivers/fpga/dfl.c | 38 ++++++++++++++++++++++---------------- 1 file changed, 22 insertions(+), 16 deletions(-) diff --git a/drivers/fpga/dfl.c b/drivers/fpga/dfl.c index 599bb21d86af..6bff39ff21a0 100644 --- a/drivers/fpga/dfl.c +++ b/drivers/fpga/dfl.c @@ -940,9 +940,12 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, { void __iomem *base = binfo->ioaddr + ofst; unsigned int i, ibase, inr = 0; + enum dfl_id_type type; int virq; u64 v; + type = feature_dev_id_type(binfo->feature_dev); + /* * Ideally DFL framework should only read info from DFL header, but * current version DFL only provides mmio resources information for @@ -957,22 +960,25 @@ static int parse_feature_irqs(struct build_feature_devs_info *binfo, * code will be added. But in order to be compatible to old version * DFL, the driver may still fall back to these quirks. */ - switch (fid) { - case PORT_FEATURE_ID_UINT: - v = readq(base + PORT_UINT_CAP); - ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); - inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); - break; - case PORT_FEATURE_ID_ERROR: - v = readq(base + PORT_ERROR_CAP); - ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); - break; - case FME_FEATURE_ID_GLOBAL_ERR: - v = readq(base + FME_ERROR_CAP); - ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); - inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); - break; + if (type == PORT_ID) { + switch (fid) { + case PORT_FEATURE_ID_UINT: + v = readq(base + PORT_UINT_CAP); + ibase = FIELD_GET(PORT_UINT_CAP_FST_VECT, v); + inr = FIELD_GET(PORT_UINT_CAP_INT_NUM, v); + break; + case PORT_FEATURE_ID_ERROR: + v = readq(base + PORT_ERROR_CAP); + ibase = FIELD_GET(PORT_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(PORT_ERROR_CAP_SUPP_INT, v); + break; + } + } else if (type == FME_ID) { + if (fid == FME_FEATURE_ID_GLOBAL_ERR) { + v = readq(base + FME_ERROR_CAP); + ibase = FIELD_GET(FME_ERROR_CAP_INT_VECT, v); + inr = FIELD_GET(FME_ERROR_CAP_SUPP_INT, v); + } } if (!inr) { -- 2.26.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* [PATCH v4 2/2] Documentation: fpga: dfl: add description of Feature ID 2022-03-18 3:16 [PATCH v4 0/2] check feature type for DFL irq parsing Tianfei Zhang 2022-03-18 3:16 ` [PATCH v4 1/2] fpga: dfl: check feature type before parse irq info Tianfei Zhang @ 2022-03-18 3:16 ` Tianfei Zhang 2022-03-21 23:05 ` matthew.gerlach 1 sibling, 1 reply; 5+ messages in thread From: Tianfei Zhang @ 2022-03-18 3:16 UTC (permalink / raw) To: hao.wu, trix, mdf, yilun.xu, linux-fpga, linux-doc, rdunlap Cc: corbet, Tianfei zhang From: Tianfei zhang <tianfei.zhang@intel.com> This patch adds the description and registration of Feature ID in documentation. Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com> --- Documentation/fpga/dfl.rst | 10 ++++++++++ 1 file changed, 10 insertions(+) diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst index ef9eec71f6f3..260cac3b7215 100644 --- a/Documentation/fpga/dfl.rst +++ b/Documentation/fpga/dfl.rst @@ -502,6 +502,16 @@ Developer only needs to provide a sub feature driver with matched feature id. FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) could be a reference. +Individual DFL drivers are bound DFL devices based on Feature Type and Feature ID. +The definition of Feature Type and Feature ID can be found: + +https://github.com/OPAE/linux-dfl-feature-id/blob/master/dfl-feature-ids.rst + +If you want to add a new feature ID for FPGA DFL feature device, you must use a pull +request to register a feature ID for DFL. Here is the DFL Feature ID Registry: + +https://github.com/OPAE/linux-dfl-feature-id + Location of DFLs on a PCI Device ================================ The original method for finding a DFL on a PCI device assumed the start of the -- 2.26.2 ^ permalink raw reply related [flat|nested] 5+ messages in thread
* Re: [PATCH v4 2/2] Documentation: fpga: dfl: add description of Feature ID 2022-03-18 3:16 ` [PATCH v4 2/2] Documentation: fpga: dfl: add description of Feature ID Tianfei Zhang @ 2022-03-21 23:05 ` matthew.gerlach 2022-03-22 7:45 ` Zhang, Tianfei 0 siblings, 1 reply; 5+ messages in thread From: matthew.gerlach @ 2022-03-21 23:05 UTC (permalink / raw) To: Tianfei Zhang Cc: hao.wu, trix, mdf, yilun.xu, linux-fpga, linux-doc, rdunlap, corbet On Thu, 17 Mar 2022, Tianfei Zhang wrote: > From: Tianfei zhang <tianfei.zhang@intel.com> > > This patch adds the description and registration of Feature ID > in documentation. > > Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com> > --- > Documentation/fpga/dfl.rst | 10 ++++++++++ > 1 file changed, 10 insertions(+) > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > index ef9eec71f6f3..260cac3b7215 100644 > --- a/Documentation/fpga/dfl.rst > +++ b/Documentation/fpga/dfl.rst > @@ -502,6 +502,16 @@ Developer only needs to provide a sub feature driver with matched feature id. > FME Partial Reconfiguration Sub Feature driver (see drivers/fpga/dfl-fme-pr.c) > could be a reference. > > +Individual DFL drivers are bound DFL devices based on Feature Type and Feature ID. > +The definition of Feature Type and Feature ID can be found: > + > +https://github.com/OPAE/linux-dfl-feature-id/blob/master/dfl-feature-ids.rst > + > +If you want to add a new feature ID for FPGA DFL feature device, you must use a pull s/you muse use/submit/ > +request to register a feature ID for DFL. Here is the DFL Feature ID Registry: > + > +https://github.com/OPAE/linux-dfl-feature-id > + > Location of DFLs on a PCI Device > ================================ > The original method for finding a DFL on a PCI device assumed the start of the > -- > 2.26.2 > > ^ permalink raw reply [flat|nested] 5+ messages in thread
* RE: [PATCH v4 2/2] Documentation: fpga: dfl: add description of Feature ID 2022-03-21 23:05 ` matthew.gerlach @ 2022-03-22 7:45 ` Zhang, Tianfei 0 siblings, 0 replies; 5+ messages in thread From: Zhang, Tianfei @ 2022-03-22 7:45 UTC (permalink / raw) To: matthew.gerlach Cc: Wu, Hao, trix, mdf, Xu, Yilun, linux-fpga, linux-doc, rdunlap, corbet > -----Original Message----- > From: matthew.gerlach@linux.intel.com <matthew.gerlach@linux.intel.com> > Sent: Tuesday, March 22, 2022 7:05 AM > To: Zhang, Tianfei <tianfei.zhang@intel.com> > Cc: Wu, Hao <hao.wu@intel.com>; trix@redhat.com; mdf@kernel.org; Xu, Yilun > <yilun.xu@intel.com>; linux-fpga@vger.kernel.org; linux-doc@vger.kernel.org; > rdunlap@infradead.org; corbet@lwn.net > Subject: Re: [PATCH v4 2/2] Documentation: fpga: dfl: add description of > Feature ID > > > > On Thu, 17 Mar 2022, Tianfei Zhang wrote: > > > From: Tianfei zhang <tianfei.zhang@intel.com> > > > > This patch adds the description and registration of Feature ID in > > documentation. > > > > Signed-off-by: Tianfei zhang <tianfei.zhang@intel.com> > > --- > > Documentation/fpga/dfl.rst | 10 ++++++++++ > > 1 file changed, 10 insertions(+) > > > > diff --git a/Documentation/fpga/dfl.rst b/Documentation/fpga/dfl.rst > > index ef9eec71f6f3..260cac3b7215 100644 > > --- a/Documentation/fpga/dfl.rst > > +++ b/Documentation/fpga/dfl.rst > > @@ -502,6 +502,16 @@ Developer only needs to provide a sub feature driver > with matched feature id. > > FME Partial Reconfiguration Sub Feature driver (see > > drivers/fpga/dfl-fme-pr.c) could be a reference. > > > > +Individual DFL drivers are bound DFL devices based on Feature Type and > Feature ID. > > +The definition of Feature Type and Feature ID can be found: > > + > > +https://github.com/OPAE/linux-dfl-feature-id/blob/master/dfl-feature- > > +ids.rst > > + > > +If you want to add a new feature ID for FPGA DFL feature device, you > > +must use a pull > > s/you muse use/submit/ Thanks, I will change to: you must submit a pull request ... > > > +request to register a feature ID for DFL. Here is the DFL Feature ID Registry: > > + > > +https://github.com/OPAE/linux-dfl-feature-id > > + > > Location of DFLs on a PCI Device > > ================================ > > The original method for finding a DFL on a PCI device assumed the > > start of the > > -- > > 2.26.2 > > > > ^ permalink raw reply [flat|nested] 5+ messages in thread
end of thread, other threads:[~2022-03-22 7:46 UTC | newest] Thread overview: 5+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-03-18 3:16 [PATCH v4 0/2] check feature type for DFL irq parsing Tianfei Zhang 2022-03-18 3:16 ` [PATCH v4 1/2] fpga: dfl: check feature type before parse irq info Tianfei Zhang 2022-03-18 3:16 ` [PATCH v4 2/2] Documentation: fpga: dfl: add description of Feature ID Tianfei Zhang 2022-03-21 23:05 ` matthew.gerlach 2022-03-22 7:45 ` Zhang, Tianfei
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