All of lore.kernel.org
 help / color / mirror / Atom feed
From: Jonathan Cameron <Jonathan.Cameron@huawei.com>
To: linuxarm@huawei.com, qemu-devel@nongnu.org,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Marcel Apfelbaum" <marcel@redhat.com>,
	"Michael S . Tsirkin" <mst@redhat.com>,
	"Igor Mammedov" <imammedo@redhat.com>,
	"Markus Armbruster" <armbru@redhat.com>
Cc: linux-cxl@vger.kernel.org,
	"Ben Widawsky" <ben.widawsky@intel.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Shameerali Kolothum Thodi"
	<shameerali.kolothum.thodi@huawei.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Peter Xu" <peterx@redhat.com>,
	"David Hildenbrand" <david@redhat.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Saransh Gupta1" <saransh@ibm.com>,
	"Shreyas Shah" <shreyas.shah@elastics.cloud>,
	"Chris Browy" <cbrowy@avery-design.com>,
	"Samarth Saxena" <samarths@cadence.com>,
	"Dan Williams" <dan.j.williams@intel.com>,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>
Subject: [PATCH v8 20/46] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing
Date: Fri, 18 Mar 2022 15:06:09 +0000	[thread overview]
Message-ID: <20220318150635.24600-21-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20220318150635.24600-1-Jonathan.Cameron@huawei.com>

From: Ben Widawsky <ben.widawsky@intel.com>

This should introduce no change. Subsequent work will make use of this
new class member.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 hw/cxl/cxl-mailbox-utils.c  |  3 +++
 hw/mem/cxl_type3.c          |  9 +++++++++
 include/hw/cxl/cxl_device.h | 10 ++++++++++
 3 files changed, 22 insertions(+)

diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index fcd41d9a9d..771b1cfe90 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -277,6 +277,8 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd,
     } QEMU_PACKED *id;
     QEMU_BUILD_BUG_ON(sizeof(*id) != 0x43);
 
+    CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
+    CXLType3Class *cvc = CXL_TYPE3_DEV_GET_CLASS(ct3d);
     uint64_t size = cxl_dstate->pmem_size;
 
     if (!QEMU_IS_ALIGNED(size, 256 << 20)) {
@@ -291,6 +293,7 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd,
 
     id->total_capacity = size / (256 << 20);
     id->persistent_capacity = size / (256 << 20);
+    id->lsa_size = cvc->get_lsa_size(ct3d);
 
     *len = sizeof(*id);
     return CXL_MBOX_SUCCESS;
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 16b113d5ed..7cd3041eb3 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -170,10 +170,16 @@ static Property ct3_props[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+static uint64_t get_lsa_size(CXLType3Dev *ct3d)
+{
+    return 0;
+}
+
 static void ct3_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
     PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
+    CXLType3Class *cvc = CXL_TYPE3_DEV_CLASS(oc);
 
     pc->realize = ct3_realize;
     pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
@@ -185,11 +191,14 @@ static void ct3_class_init(ObjectClass *oc, void *data)
     dc->desc = "CXL PMEM Device (Type 3)";
     dc->reset = ct3d_reset;
     device_class_set_props(dc, ct3_props);
+
+    cvc->get_lsa_size = get_lsa_size;
 }
 
 static const TypeInfo ct3d_info = {
     .name = TYPE_CXL_TYPE3_DEV,
     .parent = TYPE_PCI_DEVICE,
+    .class_size = sizeof(struct CXLType3Class),
     .class_init = ct3_class_init,
     .instance_size = sizeof(CXLType3Dev),
     .instance_finalize = ct3_finalize,
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 72da811c52..cf4c110f7e 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -237,6 +237,7 @@ typedef struct cxl_type3_dev {
     /* Properties */
     uint64_t size;
     HostMemoryBackend *hostmem;
+    HostMemoryBackend *lsa;
 
     /* State */
     CXLComponentState cxl_cstate;
@@ -246,5 +247,14 @@ typedef struct cxl_type3_dev {
 #define TYPE_CXL_TYPE3_DEV "cxl-type3"
 
 #define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV)
+OBJECT_DECLARE_TYPE(CXLType3Device, CXLType3Class, CXL_TYPE3_DEV)
+
+struct CXLType3Class {
+    /* Private */
+    PCIDeviceClass parent_class;
+
+    /* public */
+    uint64_t (*get_lsa_size)(CXLType3Dev *ct3d);
+};
 
 #endif
-- 
2.32.0


WARNING: multiple messages have this Message-ID (diff)
From: Jonathan Cameron via <qemu-devel@nongnu.org>
To: linuxarm@huawei.com, qemu-devel@nongnu.org,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Marcel Apfelbaum" <marcel@redhat.com>,
	"Michael S . Tsirkin" <mst@redhat.com>,
	"Igor Mammedov" <imammedo@redhat.com>,
	"Markus Armbruster" <armbru@redhat.com>
Cc: linux-cxl@vger.kernel.org,
	"Ben Widawsky" <ben.widawsky@intel.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Shameerali Kolothum Thodi"
	<shameerali.kolothum.thodi@huawei.com>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Peter Xu" <peterx@redhat.com>,
	"David Hildenbrand" <david@redhat.com>,
	"Paolo Bonzini" <pbonzini@redhat.com>,
	"Saransh Gupta1" <saransh@ibm.com>,
	"Shreyas Shah" <shreyas.shah@elastics.cloud>,
	"Chris Browy" <cbrowy@avery-design.com>,
	"Samarth Saxena" <samarths@cadence.com>,
	"Dan Williams" <dan.j.williams@intel.com>,
	"Mark Cave-Ayland" <mark.cave-ayland@ilande.co.uk>
Subject: [PATCH v8 20/46] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing
Date: Fri, 18 Mar 2022 15:06:09 +0000	[thread overview]
Message-ID: <20220318150635.24600-21-Jonathan.Cameron@huawei.com> (raw)
In-Reply-To: <20220318150635.24600-1-Jonathan.Cameron@huawei.com>

From: Ben Widawsky <ben.widawsky@intel.com>

This should introduce no change. Subsequent work will make use of this
new class member.

Signed-off-by: Ben Widawsky <ben.widawsky@intel.com>
Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com>
---
 hw/cxl/cxl-mailbox-utils.c  |  3 +++
 hw/mem/cxl_type3.c          |  9 +++++++++
 include/hw/cxl/cxl_device.h | 10 ++++++++++
 3 files changed, 22 insertions(+)

diff --git a/hw/cxl/cxl-mailbox-utils.c b/hw/cxl/cxl-mailbox-utils.c
index fcd41d9a9d..771b1cfe90 100644
--- a/hw/cxl/cxl-mailbox-utils.c
+++ b/hw/cxl/cxl-mailbox-utils.c
@@ -277,6 +277,8 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd,
     } QEMU_PACKED *id;
     QEMU_BUILD_BUG_ON(sizeof(*id) != 0x43);
 
+    CXLType3Dev *ct3d = container_of(cxl_dstate, CXLType3Dev, cxl_dstate);
+    CXLType3Class *cvc = CXL_TYPE3_DEV_GET_CLASS(ct3d);
     uint64_t size = cxl_dstate->pmem_size;
 
     if (!QEMU_IS_ALIGNED(size, 256 << 20)) {
@@ -291,6 +293,7 @@ static ret_code cmd_identify_memory_device(struct cxl_cmd *cmd,
 
     id->total_capacity = size / (256 << 20);
     id->persistent_capacity = size / (256 << 20);
+    id->lsa_size = cvc->get_lsa_size(ct3d);
 
     *len = sizeof(*id);
     return CXL_MBOX_SUCCESS;
diff --git a/hw/mem/cxl_type3.c b/hw/mem/cxl_type3.c
index 16b113d5ed..7cd3041eb3 100644
--- a/hw/mem/cxl_type3.c
+++ b/hw/mem/cxl_type3.c
@@ -170,10 +170,16 @@ static Property ct3_props[] = {
     DEFINE_PROP_END_OF_LIST(),
 };
 
+static uint64_t get_lsa_size(CXLType3Dev *ct3d)
+{
+    return 0;
+}
+
 static void ct3_class_init(ObjectClass *oc, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(oc);
     PCIDeviceClass *pc = PCI_DEVICE_CLASS(oc);
+    CXLType3Class *cvc = CXL_TYPE3_DEV_CLASS(oc);
 
     pc->realize = ct3_realize;
     pc->class_id = PCI_CLASS_STORAGE_EXPRESS;
@@ -185,11 +191,14 @@ static void ct3_class_init(ObjectClass *oc, void *data)
     dc->desc = "CXL PMEM Device (Type 3)";
     dc->reset = ct3d_reset;
     device_class_set_props(dc, ct3_props);
+
+    cvc->get_lsa_size = get_lsa_size;
 }
 
 static const TypeInfo ct3d_info = {
     .name = TYPE_CXL_TYPE3_DEV,
     .parent = TYPE_PCI_DEVICE,
+    .class_size = sizeof(struct CXLType3Class),
     .class_init = ct3_class_init,
     .instance_size = sizeof(CXLType3Dev),
     .instance_finalize = ct3_finalize,
diff --git a/include/hw/cxl/cxl_device.h b/include/hw/cxl/cxl_device.h
index 72da811c52..cf4c110f7e 100644
--- a/include/hw/cxl/cxl_device.h
+++ b/include/hw/cxl/cxl_device.h
@@ -237,6 +237,7 @@ typedef struct cxl_type3_dev {
     /* Properties */
     uint64_t size;
     HostMemoryBackend *hostmem;
+    HostMemoryBackend *lsa;
 
     /* State */
     CXLComponentState cxl_cstate;
@@ -246,5 +247,14 @@ typedef struct cxl_type3_dev {
 #define TYPE_CXL_TYPE3_DEV "cxl-type3"
 
 #define CT3(obj) OBJECT_CHECK(CXLType3Dev, (obj), TYPE_CXL_TYPE3_DEV)
+OBJECT_DECLARE_TYPE(CXLType3Device, CXLType3Class, CXL_TYPE3_DEV)
+
+struct CXLType3Class {
+    /* Private */
+    PCIDeviceClass parent_class;
+
+    /* public */
+    uint64_t (*get_lsa_size)(CXLType3Dev *ct3d);
+};
 
 #endif
-- 
2.32.0



  parent reply	other threads:[~2022-03-18 15:16 UTC|newest]

Thread overview: 142+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-18 15:05 [PATCH v8 00/46] CXl 2.0 emulation Support Jonathan Cameron
2022-03-18 15:05 ` Jonathan Cameron via
2022-03-18 15:05 ` [PATCH v8 01/46] hw/pci/cxl: Add a CXL component type (interface) Jonathan Cameron
2022-03-18 15:05   ` Jonathan Cameron via
     [not found]   ` <CGME20220327133216uscas1p13b9248b075f1736542e40654b498b5ff@uscas1p1.samsung.com>
2022-03-27 13:32     ` Adam Manzanares
2022-03-27 13:32       ` Adam Manzanares
2022-03-18 15:05 ` [PATCH v8 02/46] hw/cxl/component: Introduce CXL components (8.1.x, 8.2.5) Jonathan Cameron
2022-03-18 15:05   ` Jonathan Cameron via
2022-03-25 13:45   ` Jonathan Cameron
2022-03-25 13:45     ` Jonathan Cameron via
     [not found]   ` <CGME20220328142843uscas1p231d68ea82ce825a0366392def9906500@uscas1p2.samsung.com>
2022-03-28 14:28     ` Adam Manzanares
2022-03-28 14:28       ` Adam Manzanares
2022-03-30 16:55       ` Jonathan Cameron
2022-03-30 16:55         ` Jonathan Cameron via
2022-03-31 12:20   ` Jonathan Cameron
2022-03-31 12:20     ` Jonathan Cameron via
2022-03-18 15:05 ` [PATCH v8 03/46] MAINTAINERS: Add entry for Compute Express Link Emulation Jonathan Cameron
2022-03-18 15:05   ` Jonathan Cameron via
2022-03-18 15:05 ` [PATCH v8 04/46] hw/cxl/device: Introduce a CXL device (8.2.8) Jonathan Cameron
2022-03-18 15:05   ` Jonathan Cameron via
     [not found]   ` <CGME20220329181401uscas1p2b229afdbb479a012e140f84367c35ccd@uscas1p2.samsung.com>
2022-03-29 18:13     ` Adam Manzanares
2022-03-29 18:13       ` Adam Manzanares
2022-03-29 19:53       ` Davidlohr Bueso
2022-03-29 19:53         ` Davidlohr Bueso
2022-03-30 12:15         ` Jonathan Cameron via
2022-03-30 12:15           ` Jonathan Cameron
2022-03-31 21:42           ` Adam Manzanares
2022-03-31 21:42             ` Adam Manzanares
2022-03-30 17:48       ` Jonathan Cameron
2022-03-30 17:48         ` Jonathan Cameron via
2022-03-31 22:13         ` Adam Manzanares
2022-03-31 22:13           ` Adam Manzanares
2022-04-01 13:30           ` Jonathan Cameron
2022-04-01 13:30             ` Jonathan Cameron via
2022-04-04 15:15             ` Adam Manzanares
2022-04-04 15:15               ` Adam Manzanares
2022-04-05  9:10               ` Jonathan Cameron via
2022-04-05  9:10                 ` Jonathan Cameron
2022-03-18 15:05 ` [PATCH v8 05/46] hw/cxl/device: Implement the CAP array (8.2.8.1-2) Jonathan Cameron
2022-03-18 15:05   ` Jonathan Cameron via
2022-03-18 15:05 ` [PATCH v8 06/46] hw/cxl/device: Implement basic mailbox (8.2.8.4) Jonathan Cameron
2022-03-18 15:05   ` Jonathan Cameron via
2022-03-18 15:05 ` [PATCH v8 07/46] hw/cxl/device: Add memory device utilities Jonathan Cameron
2022-03-18 15:05   ` Jonathan Cameron via
2022-03-18 15:05 ` [PATCH v8 08/46] hw/cxl/device: Add cheap EVENTS implementation (8.2.9.1) Jonathan Cameron
2022-03-18 15:05   ` Jonathan Cameron via
2022-03-18 15:05 ` [PATCH v8 09/46] hw/cxl/device: Timestamp implementation (8.2.9.3) Jonathan Cameron
2022-03-18 15:05   ` Jonathan Cameron via
2022-03-18 15:05 ` [PATCH v8 10/46] hw/cxl/device: Add log commands (8.2.9.4) + CEL Jonathan Cameron
2022-03-18 15:05   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 11/46] hw/pxb: Use a type for realizing expanders Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 12/46] hw/pci/cxl: Create a CXL bus type Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 13/46] cxl: Machine level control on whether CXL support is enabled Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 14/46] hw/pxb: Allow creation of a CXL PXB (host bridge) Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 15/46] qtest/cxl: Introduce initial test for pxb-cxl only Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 16/46] hw/cxl/rp: Add a root port Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 17/46] hw/cxl/device: Add a memory device (8.2.8.5) Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-19  8:32   ` Mark Cave-Ayland
2022-03-19  8:32     ` Mark Cave-Ayland
2022-03-23 18:18     ` Jonathan Cameron
2022-03-23 18:18       ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 18/46] hw/cxl/device: Implement MMIO HDM decoding (8.2.5.12) Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 19/46] hw/cxl/device: Add some trivial commands Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 16:56   ` Alison Schofield
2022-03-18 16:56     ` Alison Schofield
2022-03-23 15:57     ` Jonathan Cameron
2022-03-23 15:57       ` Jonathan Cameron via
2022-03-18 15:06 ` Jonathan Cameron [this message]
2022-03-18 15:06   ` [PATCH v8 20/46] hw/cxl/device: Plumb real Label Storage Area (LSA) sizing Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 21/46] hw/cxl/device: Implement get/set Label Storage Area (LSA) Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 22/46] qtests/cxl: Add initial root port and CXL type3 tests Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 23/46] hw/cxl/component: Implement host bridge MMIO (8.2.5, table 142) Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-19  8:35   ` Mark Cave-Ayland
2022-03-19  8:35     ` Mark Cave-Ayland
2022-03-23 18:37     ` Jonathan Cameron
2022-03-23 18:37       ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 24/46] acpi/cxl: Add _OSC implementation (9.14.2) Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 25/46] acpi/cxl: Create the CEDT (9.14.1) Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 26/46] hw/cxl/component: Add utils for interleave parameter encoding/decoding Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 27/46] hw/cxl/host: Add support for CXL Fixed Memory Windows Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-28 12:50   ` Markus Armbruster
2022-03-28 12:50     ` Markus Armbruster
2022-03-31 12:12     ` Jonathan Cameron
2022-03-31 12:12       ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 28/46] acpi/cxl: Introduce CFMWS structures in CEDT Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 29/46] hw/pci-host/gpex-acpi: Add support for dsdt construction for pxb-cxl Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 30/46] pci/pcie_port: Add pci_find_port_by_pn() Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 31/46] CXL/cxl_component: Add cxl_get_hb_cstate() Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 32/46] mem/cxl_type3: Add read and write functions for associated hostmem Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-19  8:53   ` Mark Cave-Ayland
2022-03-19  8:53     ` Mark Cave-Ayland
2022-03-23 15:43     ` Jonathan Cameron
2022-03-23 15:43       ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 33/46] cxl/cxl-host: Add memops for CFMWS region Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 34/46] hw/cxl/component Add a dumb HDM decoder handler Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 35/46] i386/pc: Enable CXL fixed memory windows Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 36/46] tests/acpi: q35: Allow addition of a CXL test Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 37/46] qtests/bios-tables-test: Add a test for CXL emulation Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 38/46] tests/acpi: Add tables " Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 39/46] qtest/cxl: Add more complex test cases with CFMWs Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 40/46] hw/arm/virt: Basic CXL enablement on pci_expander_bridge instances pxb-cxl Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 41/46] qtest/cxl: Add aarch64 virt test for CXL Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 42/46] docs/cxl: Add initial Compute eXpress Link (CXL) documentation Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 43/46] pci-bridge/cxl_upstream: Add a CXL switch upstream port Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 44/46] pci-bridge/cxl_downstream: Add a CXL switch downstream port Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 45/46] cxl/cxl-host: Support interleave decoding with one level of switches Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via
2022-03-18 15:06 ` [PATCH v8 46/46] docs/cxl: Add switch documentation Jonathan Cameron
2022-03-18 15:06   ` Jonathan Cameron via

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220318150635.24600-21-Jonathan.Cameron@huawei.com \
    --to=jonathan.cameron@huawei.com \
    --cc=alex.bennee@linaro.org \
    --cc=armbru@redhat.com \
    --cc=ben.widawsky@intel.com \
    --cc=cbrowy@avery-design.com \
    --cc=dan.j.williams@intel.com \
    --cc=david@redhat.com \
    --cc=f4bug@amsat.org \
    --cc=imammedo@redhat.com \
    --cc=linux-cxl@vger.kernel.org \
    --cc=linuxarm@huawei.com \
    --cc=marcel@redhat.com \
    --cc=mark.cave-ayland@ilande.co.uk \
    --cc=mst@redhat.com \
    --cc=pbonzini@redhat.com \
    --cc=peter.maydell@linaro.org \
    --cc=peterx@redhat.com \
    --cc=qemu-devel@nongnu.org \
    --cc=samarths@cadence.com \
    --cc=saransh@ibm.com \
    --cc=shameerali.kolothum.thodi@huawei.com \
    --cc=shreyas.shah@elastics.cloud \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body.
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.