* [PATCH 0/9] Add RZ/G2L Display clock support
@ 2022-03-18 17:51 Biju Das
2022-03-18 17:51 ` [PATCH 1/9] clk: renesas: rzg2l: Add FOUTPOSTDIV clk support Biju Das
` (8 more replies)
0 siblings, 9 replies; 18+ messages in thread
From: Biju Das @ 2022-03-18 17:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
This patch series aims to add display clock support on RZ/G2L SMARC
EVK platform. The output from DSI is connected to ADV7535.
Implementation details:-
PLL5 generates 2 clock sources, FOUTPOSTDIV and FOUT1PH0 and vclk is
sourced through DSI divider which is connected to a mux with the above
clock sources.
Pll5-->Mux->DSI divider--> vclk.
DSI mode and DPI mode needs different set of PLL5 parameters for
generating the video clock. Currently we support only DSI mode.
later plan to extend this support to DPI mode.
RFC->V1:
* Replaced LUT with an equation for computing pll5 parameters for generating vclk.
* Replaced magic numbers with macros.
* Added Rb tag from Geert.
RFC:
* https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-2-biju.das.jz@bp.renesas.com/
* https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-3-biju.das.jz@bp.renesas.com/
Logs:-
Clock tree output with monitor connected at 1080p@60Hz:
root@smarc-rzg2l:~# cat /sys/kernel/debug/clk/clk_summary
enable prepare protect duty hardware
clock count count count rate accuracy phase cycle enable
-------------------------------------------------------------------------------------------------------
audio_mclock 0 0 0 11289600 0 0 50000 Y
extal 5 5 0 24000000 0 0 50000 Y
.pll5_foutpostdiv 2 2 0 888000000 0 0 50000 Y
M1 1 1 0 888000000 0 0 50000 Y
dsi_pll_clk 1 1 0 888000000 0 0 50000 Y
.pll5_fout1ph0 1 1 0 444000000 0 0 50000 Y
.sel_pll5_4 1 1 0 444000000 0 0 50000 Y
DSI_DIV 1 1 0 148500000 0 0 50000 Y
M3 2 2 0 148500000 0 0 50000 Y
lcdc_clk_d 3 4 0 148500000 0 0 50000 Y
dsi_vclk 1 1 0 148500000 0 0 50000 Y
.pll6 2 2 0 500000000 0 0 50000 Y
.sel_gpu2 1 1 0 500000000 0 0 50000 Y
G 1 1 0 62500000 0 0 50000 Y
gpu_clk 1 2 0 62500000 0 0 50000 Y
.pll6_250 1 1 0 250000000 0 0 50000 Y
HP 2 2 0 250000000 0 0 50000 Y
.pll5 0 0 0 3000000000 0 0 50000 Y
.pll5_fout3 0 0 0 500000000 0 0 50000 Y
.pll5_250 0 0 0 250000000 0 0 50000 Y
.pll3 2 2 0 1600000000 0 0 50000 Y
.pll3_div2 1 1 0 800000000 0 0 50000 Y
.pll3_div2_4 3 3 0 200000000 0 0 50000 Y
M0 3 3 0 200000000 0 0 50000 Y
eth1_axi 1 1 0 200000000 0 0 50000 Y
eth0_axi 1 1 0 200000000 0 0 50000 Y
lcdc_a 3 4 0 200000000 0 0 50000 Y
P1 12 13 0 200000000 0 0 50000 Y
usb_pclk 8 12 0 200000000 0 0 50000 Y
usb0_func 1 1 0 200000000 0 0 50000 Y
usb1_host 3 5 0 200000000 0 0 50000 Y
usb0_host 3 5 0 200000000 0 0 50000 Y
dsi_aclk 1 1 0 200000000 0 0 50000 Y
gpu_ace_clk 0 1 0 200000000 0 0 50000 N
gpu_axi_clk 1 2 0 200000000 0 0 50000 Y
sdhi1_aclk 1 1 0 200000000 0 0 50000 Y
sdhi0_aclk 1 1 0 200000000 0 0 50000 Y
dmac_aclk 2 2 0 200000000 0 0 50000 Y
ia55_clk 1 1 0 200000000 0 0 50000 Y
gic 1 1 0 200000000 0 0 50000 Y
P1_DIV2 1 1 0 100000000 0 0 50000 Y
dmac_pclk 1 1 0 100000000 0 0 50000 Y
.pll3_div2_4_2 2 2 0 100000000 0 0 50000 Y
ZT 3 3 0 100000000 0 0 50000 Y
eth1_chi 1 1 0 100000000 0 0 50000 Y
eth0_chi 1 1 0 100000000 0 0 50000 Y
lcdc_p 2 3 0 100000000 0 0 50000 Y
P2 1 1 0 100000000 0 0 50000 Y
dsi_pclk 1 1 0 100000000 0 0 50000 Y
ia55_pclk 0 0 0 100000000 0 0 50000 N
.pll3_div2_2 0 0 0 400000000 0 0 50000 Y
.pll3_533 1 2 0 533333333 0 0 50000 Y
M2 1 1 0 266666666 0 0 50000 Y
M2_DIV2 1 1 0 133333333 0 0 50000 Y
dsi_sys_clk 1 1 0 133333333 0 0 50000 Y
.sel_pll3_3 0 1 0 533333333 0 0 50000 Y
divpl3c 0 2 0 266666667 0 0 50000 Y
SPI1 0 1 0 66666666 0 0 50000 Y
spi_clk2 0 1 0 66666666 0 0 50000 N
SPI0 0 1 0 133333333 0 0 50000 Y
spi_clk 0 1 0 133333333 0 0 50000 N
.pll3_400 0 0 0 400000000 0 0 50000 Y
.pll2 3 3 0 1600000000 0 0 50000 Y
.clk_533 0 0 0 533333333 0 0 50000 Y
.clk_266 0 0 0 266666666 0 0 50000 Y
.clk_800 1 1 0 800000000 0 0 50000 Y
.clk_400 2 2 0 400000000 0 0 50000 Y
sd1 2 2 0 400000000 0 0 50000 Y
sdhi1_clk_hs 1 1 0 400000000 0 0 50000 Y
SD1_DIV4 2 2 0 100000000 0 0 50000 Y
sdhi1_imclk2 2 2 0 100000000 0 0 50000 Y
sdhi1_imclk 1 1 0 100000000 0 0 50000 Y
sd0 2 2 0 400000000 0 0 50000 Y
sdhi0_clk_hs 1 1 0 400000000 0 0 50000 Y
SD0_DIV4 2 2 0 100000000 0 0 50000 Y
sdhi0_imclk2 2 2 0 100000000 0 0 50000 Y
sdhi0_imclk 1 1 0 100000000 0 0 50000 Y
.pll2_div2 2 2 0 800000000 0 0 50000 Y
.pll2_div2_10 1 1 0 80000000 0 0 50000 Y
TSU 1 2 0 80000000 0 0 50000 Y
tsu_pclk 1 1 0 80000000 0 0 50000 Y
adc_adclk 0 1 0 80000000 0 0 50000 N
.pll2_div2_8 1 1 0 100000000 0 0 50000 Y
P0 6 15 0 100000000 0 0 50000 Y
adc_pclk 0 1 0 100000000 0 0 50000 N
canfd 1 2 0 100000000 0 0 50000 Y
rspi2 0 0 0 100000000 0 0 50000 N
rspi1 0 1 0 100000000 0 0 50000 N
rspi0 0 0 0 100000000 0 0 50000 N
sci1 0 0 0 100000000 0 0 50000 N
sci0 0 0 0 100000000 0 0 50000 N
scif4 0 0 0 100000000 0 0 50000 N
scif3 0 0 0 100000000 0 0 50000 N
scif2 0 1 0 100000000 0 0 50000 N
scif1 0 0 0 100000000 0 0 50000 N
scif0 2 2 0 100000000 0 0 50000 Y
i2c3 0 1 0 100000000 0 0 50000 N
i2c2 0 0 0 100000000 0 0 50000 N
i2c1 0 1 0 100000000 0 0 50000 N
i2c0 0 1 0 100000000 0 0 50000 N
ssi3_sfr 0 0 0 100000000 0 0 50000 N
ssi3_pclk 0 0 0 100000000 0 0 50000 N
ssi2_sfr 0 0 0 100000000 0 0 50000 N
ssi2_pclk 0 0 0 100000000 0 0 50000 N
ssi1_sfr 0 0 0 100000000 0 0 50000 N
ssi1_pclk 0 0 0 100000000 0 0 50000 N
ssi0_sfr 1 1 0 100000000 0 0 50000 Y
ssi0_pclk 1 1 0 100000000 0 0 50000 Y
wdt2_pclk 0 1 0 100000000 0 0 50000 N
wdt1_pclk 0 1 0 100000000 0 0 50000 N
wdt0_pclk 0 1 0 100000000 0 0 50000 N
ostm2_pclk 1 2 0 100000000 0 0 50000 Y
ostm1_clk 1 2 0 100000000 0 0 50000 Y
ostm0_pclk 0 0 0 100000000 0 0 50000 N
P0_DIV2 0 0 0 50000000 0 0 50000 Y
.pll2_533 1 1 0 533333333 0 0 50000 Y
.pll2_533_div2 1 1 0 266666666 0 0 50000 Y
.div_dsi_lpclk 1 1 0 16666667 0 0 50000 Y
M4 1 1 0 16666667 0 0 50000 Y
dsi_lpclk 1 1 0 16666667 0 0 50000 Y
.pll1 0 0 0 1200000000 0 0 50000 Y
I 0 0 0 1200000000 0 0 50000 Y
.osc_div1000 0 0 0 24000 0 0 50000 Y
.osc 1 4 0 24000000 0 0 50000 Y
gpio 1 2 0 24000000 0 0 50000 Y
wdt2_clk 0 1 0 24000000 0 0 50000 N
wdt1_clk 0 1 0 24000000 0 0 50000 N
wdt0_clk 0 1 0 24000000 0 0 50000 N
can 0 0 0 0 0 0 50000 Y
audio_clk2 0 0 0 12288000 0 0 50000 Y
audio_clk1 0 0 0 11289600 0 0 50000 Y
root@smarc-rzg2l:~#
Biju Das (9):
clk: renesas: rzg2l: Add FOUTPOSTDIV clk support
clk: renesas: rzg2l: Add PLL5_4 clk mux support
clk: renesas: rzg2l: Add DSI divider clk support
clk: renesas: r9a07g044: Add M1 clock support
clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support
clk: renesas: r9a07g044: Add M3 Clock support
clk: renesas: r9a07g044: Add M4 Clock support
clk: renesas: r9a07g044: Add LCDC clock and reset entries
clk: renesas: r9a07g044: Add DSI clock and reset entries
drivers/clk/renesas/r9a07g044-cpg.c | 58 ++++-
drivers/clk/renesas/rzg2l-cpg.c | 338 ++++++++++++++++++++++++++++
drivers/clk/renesas/rzg2l-cpg.h | 43 ++++
3 files changed, 437 insertions(+), 2 deletions(-)
--
2.17.1
^ permalink raw reply [flat|nested] 18+ messages in thread
* [PATCH 1/9] clk: renesas: rzg2l: Add FOUTPOSTDIV clk support
2022-03-18 17:51 [PATCH 0/9] Add RZ/G2L Display clock support Biju Das
@ 2022-03-18 17:51 ` Biju Das
2022-04-21 7:44 ` Geert Uytterhoeven
2022-03-18 17:51 ` [PATCH 2/9] clk: renesas: rzg2l: Add PLL5_4 clk mux support Biju Das
` (7 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2022-03-18 17:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules.
The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced
from DSI divider which is connected to PLL5_4 MUX.
This patch adds support for generating FOUTPOSTDIV clk.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
RFC->V1:
* Removed LUT.
* Replaced magic numbers with macros.
RFC:
*https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-2-biju.das.jz@bp.renesas.com/
---
drivers/clk/renesas/rzg2l-cpg.c | 140 ++++++++++++++++++++++++++++++++
drivers/clk/renesas/rzg2l-cpg.h | 20 +++++
2 files changed, 160 insertions(+)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 486d0656c58a..4d18699852fb 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -64,6 +64,15 @@ struct sd_hw_data {
#define to_sd_hw_data(_hw) container_of(_hw, struct sd_hw_data, hw)
+struct rzg2l_pll5_param {
+ u32 frequency;
+ u32 pl5_fracin;
+ u8 pl5_refdiv;
+ u8 pl5_intin;
+ u8 pl5_postdiv1;
+ u8 pl5_postdiv2;
+};
+
/**
* struct rzg2l_cpg_priv - Clock Pulse Generator Private Data
*
@@ -78,6 +87,7 @@ struct sd_hw_data {
* @last_dt_core_clk: ID of the last Core Clock exported to DT
* @notifiers: Notifier chain to save/restore clock state for system resume
* @info: Pointer to platform data
+ * @pll5_params: pll5 parameters
*/
struct rzg2l_cpg_priv {
struct reset_controller_dev rcdev;
@@ -93,6 +103,8 @@ struct rzg2l_cpg_priv {
struct raw_notifier_head notifiers;
const struct rzg2l_cpg_info *info;
+
+ struct rzg2l_pll5_param pll5_params;
};
static void rzg2l_cpg_del_clk_provider(void *data)
@@ -266,6 +278,131 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
return clk_hw->clk;
}
+struct sipll5 {
+ struct clk_hw hw;
+ u32 conf;
+ struct rzg2l_cpg_priv *priv;
+};
+
+#define to_sipll5(_hw) container_of(_hw, struct sipll5, hw)
+
+static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct sipll5 *sipll5 = to_sipll5(hw);
+ struct rzg2l_cpg_priv *priv = sipll5->priv;
+
+ return priv->pll5_params.frequency;
+}
+
+static long rzg2l_cpg_sipll5_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
+{
+ struct sipll5 *sipll5 = to_sipll5(hw);
+ struct rzg2l_cpg_priv *priv = sipll5->priv;
+
+ return priv->pll5_params.frequency;
+}
+
+static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct sipll5 *sipll5 = to_sipll5(hw);
+ struct rzg2l_cpg_priv *priv = sipll5->priv;
+ int ret;
+ u32 val;
+
+ /* Put PLL5 into standby mode */
+ writel(CPG_SIPLL5_STBY_RESETB_WEN, priv->base + CPG_SIPLL5_STBY);
+ ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val,
+ !(val & CPG_SIPLL5_MON_PLL5_LOCK), 100, 250000);
+ if (ret) {
+ dev_err(priv->dev, "failed to release pll5 lock");
+ return ret;
+ }
+
+ /* Output clock setting 1 */
+ writel(CPG_SIPLL5_CLK1_POSTDIV1_WEN | CPG_SIPLL5_CLK1_REFDIV_WEN |
+ CPG_SIPLL5_CLK1_REFDIV_WEN |
+ (priv->pll5_params.pl5_postdiv1 << 0) |
+ (priv->pll5_params.pl5_postdiv2 << 4) |
+ (priv->pll5_params.pl5_refdiv << 8),
+ priv->base + CPG_SIPLL5_CLK1);
+
+ /* Output clock setting, SSCG modulation value setting 3 */
+ writel((priv->pll5_params.pl5_fracin << 8), priv->base + CPG_SIPLL5_CLK3);
+
+ /* Output clock setting 4 */
+ writel(CPG_SIPLL5_CLK4_RESV_LSB | (priv->pll5_params.pl5_intin << 16),
+ priv->base + CPG_SIPLL5_CLK4);
+
+ /* PLL normal mode setting */
+ writel(CPG_SIPLL5_STBY_SSCG_EN_WEN | CPG_SIPLL5_STBY_RESETB_WEN |
+ CPG_SIPLL5_STBY_RESETB, priv->base + CPG_SIPLL5_STBY);
+
+ /* PLL normal mode transition, output clock stability check */
+ ret = readl_poll_timeout(priv->base + CPG_SIPLL5_MON, val,
+ (val & CPG_SIPLL5_MON_PLL5_LOCK), 100, 250000);
+ if (ret) {
+ dev_err(priv->dev, "failed to lock pll5");
+ return ret;
+ }
+
+ return 0;
+}
+
+static const struct clk_ops rzg2l_cpg_sipll5_ops = {
+ .recalc_rate = rzg2l_cpg_sipll5_recalc_rate,
+ .round_rate = rzg2l_cpg_sipll5_round_rate,
+ .set_rate = rzg2l_cpg_sipll5_set_rate,
+};
+
+static struct clk * __init
+rzg2l_cpg_sipll5_register(const struct cpg_core_clk *core,
+ struct clk **clks,
+ struct rzg2l_cpg_priv *priv)
+{
+ const struct clk *parent;
+ struct clk_init_data init;
+ const char *parent_name;
+ struct sipll5 *sipll5;
+ struct clk_hw *clk_hw;
+ int ret;
+
+ parent = clks[core->parent & 0xffff];
+ if (IS_ERR(parent))
+ return ERR_CAST(parent);
+
+ sipll5 = devm_kzalloc(priv->dev, sizeof(*sipll5), GFP_KERNEL);
+ if (!sipll5)
+ return ERR_PTR(-ENOMEM);
+
+ init.name = core->name;
+ parent_name = __clk_get_name(parent);
+ init.ops = &rzg2l_cpg_sipll5_ops;
+ init.flags = 0;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ sipll5->hw.init = &init;
+ sipll5->conf = core->conf;
+ sipll5->priv = priv;
+
+ writel(CPG_SIPLL5_STBY_SSCG_EN_WEN | CPG_SIPLL5_STBY_RESETB_WEN |
+ CPG_SIPLL5_STBY_RESETB, priv->base + CPG_SIPLL5_STBY);
+
+ clk_hw = &sipll5->hw;
+ clk_hw->init = &init;
+
+ ret = devm_clk_hw_register(priv->dev, clk_hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return clk_hw->clk;
+}
+
struct pll_clk {
struct clk_hw hw;
unsigned int conf;
@@ -420,6 +557,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
clk = rzg2l_cpg_pll_clk_register(core, priv->clks,
priv->base, priv);
break;
+ case CLK_TYPE_SIPLL5:
+ clk = rzg2l_cpg_sipll5_register(core, priv->clks, priv);
+ break;
case CLK_TYPE_DIV:
clk = rzg2l_cpg_div_clk_register(core, priv->clks,
priv->base, priv);
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index ce657beaf160..40f61db902b2 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -9,6 +9,12 @@
#ifndef __RENESAS_RZG2L_CPG_H__
#define __RENESAS_RZG2L_CPG_H__
+#define CPG_SIPLL5_STBY (0x140)
+#define CPG_SIPLL5_CLK1 (0x144)
+#define CPG_SIPLL5_CLK3 (0x14C)
+#define CPG_SIPLL5_CLK4 (0x150)
+#define CPG_SIPLL5_CLK5 (0x154)
+#define CPG_SIPLL5_MON (0x15C)
#define CPG_PL1_DDIV (0x200)
#define CPG_PL2_DDIV (0x204)
#define CPG_PL3A_DDIV (0x208)
@@ -19,6 +25,15 @@
#define CPG_PL6_SSEL (0x414)
#define CPG_PL6_ETH_SSEL (0x418)
+#define CPG_SIPLL5_STBY_RESETB BIT(0)
+#define CPG_SIPLL5_STBY_RESETB_WEN BIT(16)
+#define CPG_SIPLL5_STBY_SSCG_EN_WEN BIT(18)
+#define CPG_SIPLL5_CLK1_POSTDIV1_WEN BIT(16)
+#define CPG_SIPLL5_CLK1_POSTDIV2_WEN BIT(20)
+#define CPG_SIPLL5_CLK1_REFDIV_WEN BIT(24)
+#define CPG_SIPLL5_CLK4_RESV_LSB (0xFF)
+#define CPG_SIPLL5_MON_PLL5_LOCK BIT(4)
+
#define CPG_CLKSTATUS_SELSDHI0_STS BIT(28)
#define CPG_CLKSTATUS_SELSDHI1_STS BIT(29)
@@ -86,6 +101,9 @@ enum clk_types {
/* Clock with SD clock source selector */
CLK_TYPE_SD_MUX,
+
+ /* Clock for SIPLL5 */
+ CLK_TYPE_SIPLL5,
};
#define DEF_TYPE(_name, _id, _type...) \
@@ -109,6 +127,8 @@ enum clk_types {
#define DEF_SD_MUX(_name, _id, _conf, _parent_names, _num_parents) \
DEF_TYPE(_name, _id, CLK_TYPE_SD_MUX, .conf = _conf, \
.parent_names = _parent_names, .num_parents = _num_parents)
+#define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \
+ DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent)
/**
* struct rzg2l_mod_clk - Module Clocks definitions
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/9] clk: renesas: rzg2l: Add PLL5_4 clk mux support
2022-03-18 17:51 [PATCH 0/9] Add RZ/G2L Display clock support Biju Das
2022-03-18 17:51 ` [PATCH 1/9] clk: renesas: rzg2l: Add FOUTPOSTDIV clk support Biju Das
@ 2022-03-18 17:51 ` Biju Das
2022-04-21 7:47 ` Geert Uytterhoeven
2022-03-18 17:51 ` [PATCH 3/9] clk: renesas: rzg2l: Add DSI divider clk support Biju Das
` (6 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2022-03-18 17:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add PLL5_4 clk mux support to select clock from clock
sources FOUTPOSTDIV and FOUT1PH0.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
RFC->V1:
* Removed LUT.
RFC:
* https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220112174612.10773-3-biju.das.jz@bp.renesas.com/
---
drivers/clk/renesas/rzg2l-cpg.c | 84 +++++++++++++++++++++++++++++++++
drivers/clk/renesas/rzg2l-cpg.h | 10 ++++
2 files changed, 94 insertions(+)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index 4d18699852fb..f8e177ef3f93 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -71,6 +71,7 @@ struct rzg2l_pll5_param {
u8 pl5_intin;
u8 pl5_postdiv1;
u8 pl5_postdiv2;
+ u8 clksrc;
};
/**
@@ -278,6 +279,86 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
return clk_hw->clk;
}
+struct pll5_mux_hw_data {
+ struct clk_hw hw;
+ u32 conf;
+ unsigned long rate;
+ struct rzg2l_cpg_priv *priv;
+};
+
+#define to_pll5_mux_hw_data(_hw) container_of(_hw, struct pll5_mux_hw_data, hw)
+
+static int rzg2l_cpg_pll5_4_clk_mux_determine_rate(struct clk_hw *hw,
+ struct clk_rate_request *req)
+{
+ struct clk_hw *parent;
+ struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);
+ struct rzg2l_cpg_priv *priv = hwdata->priv;
+
+ parent = clk_hw_get_parent_by_index(hw, priv->pll5_params.clksrc);
+ req->best_parent_hw = parent;
+ req->best_parent_rate = req->rate;
+
+ return 0;
+}
+
+static int rzg2l_cpg_pll5_4_clk_mux_set_parent(struct clk_hw *hw, u8 index)
+{
+ struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);
+ struct rzg2l_cpg_priv *priv = hwdata->priv;
+
+ writel(CPG_OTHERFUNC1_REG_RES0_ON_WEN | index,
+ priv->base + CPG_OTHERFUNC1_REG);
+
+ return 0;
+}
+
+static u8 rzg2l_cpg_pll5_4_clk_mux_get_parent(struct clk_hw *hw)
+{
+ struct pll5_mux_hw_data *hwdata = to_pll5_mux_hw_data(hw);
+ struct rzg2l_cpg_priv *priv = hwdata->priv;
+
+ return readl(priv->base + GET_REG_OFFSET(hwdata->conf));
+}
+
+static const struct clk_ops rzg2l_cpg_pll5_4_clk_mux_ops = {
+ .determine_rate = rzg2l_cpg_pll5_4_clk_mux_determine_rate,
+ .set_parent = rzg2l_cpg_pll5_4_clk_mux_set_parent,
+ .get_parent = rzg2l_cpg_pll5_4_clk_mux_get_parent,
+};
+
+static struct clk * __init
+rzg2l_cpg_pll5_4_mux_clk_register(const struct cpg_core_clk *core,
+ struct rzg2l_cpg_priv *priv)
+{
+ struct pll5_mux_hw_data *clk_hw_data;
+ struct clk_init_data init;
+ struct clk_hw *clk_hw;
+ int ret;
+
+ clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
+ if (!clk_hw_data)
+ return ERR_PTR(-ENOMEM);
+
+ clk_hw_data->priv = priv;
+ clk_hw_data->conf = core->conf;
+
+ init.name = core->name;
+ init.ops = &rzg2l_cpg_pll5_4_clk_mux_ops;
+ init.flags = CLK_SET_RATE_PARENT;
+ init.num_parents = core->num_parents;
+ init.parent_names = core->parent_names;
+
+ clk_hw = &clk_hw_data->hw;
+ clk_hw->init = &init;
+
+ ret = devm_clk_hw_register(priv->dev, clk_hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return clk_hw->clk;
+}
+
struct sipll5 {
struct clk_hw hw;
u32 conf;
@@ -570,6 +651,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
case CLK_TYPE_SD_MUX:
clk = rzg2l_cpg_sd_mux_clk_register(core, priv->base, priv);
break;
+ case CLK_TYPE_PLL5_4_MUX:
+ clk = rzg2l_cpg_pll5_4_mux_clk_register(core, priv);
+ break;
default:
goto fail;
}
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index 40f61db902b2..a4bdc1d7b5aa 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -24,6 +24,7 @@
#define CPG_PL3_SSEL (0x408)
#define CPG_PL6_SSEL (0x414)
#define CPG_PL6_ETH_SSEL (0x418)
+#define CPG_OTHERFUNC1_REG (0xBE8)
#define CPG_SIPLL5_STBY_RESETB BIT(0)
#define CPG_SIPLL5_STBY_RESETB_WEN BIT(16)
@@ -34,6 +35,8 @@
#define CPG_SIPLL5_CLK4_RESV_LSB (0xFF)
#define CPG_SIPLL5_MON_PLL5_LOCK BIT(4)
+#define CPG_OTHERFUNC1_REG_RES0_ON_WEN BIT(16)
+
#define CPG_CLKSTATUS_SELSDHI0_STS BIT(28)
#define CPG_CLKSTATUS_SELSDHI1_STS BIT(29)
@@ -58,6 +61,7 @@
(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
#define SEL_PLL3_3 SEL_PLL_PACK(CPG_PL3_SSEL, 8, 1)
+#define SEL_PLL5_4 SEL_PLL_PACK(CPG_OTHERFUNC1_REG, 0, 1)
#define SEL_PLL6_2 SEL_PLL_PACK(CPG_PL6_ETH_SSEL, 0, 1)
#define SEL_GPU2 SEL_PLL_PACK(CPG_PL6_SSEL, 12, 1)
@@ -104,6 +108,9 @@ enum clk_types {
/* Clock for SIPLL5 */
CLK_TYPE_SIPLL5,
+
+ /* Clock for PLL5_4 clock source selector */
+ CLK_TYPE_PLL5_4_MUX,
};
#define DEF_TYPE(_name, _id, _type...) \
@@ -129,6 +136,9 @@ enum clk_types {
.parent_names = _parent_names, .num_parents = _num_parents)
#define DEF_PLL5_FOUTPOSTDIV(_name, _id, _parent) \
DEF_TYPE(_name, _id, CLK_TYPE_SIPLL5, .parent = _parent)
+#define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names, _num_parents) \
+ DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \
+ .parent_names = _parent_names, .num_parents = _num_parents)
/**
* struct rzg2l_mod_clk - Module Clocks definitions
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 3/9] clk: renesas: rzg2l: Add DSI divider clk support
2022-03-18 17:51 [PATCH 0/9] Add RZ/G2L Display clock support Biju Das
2022-03-18 17:51 ` [PATCH 1/9] clk: renesas: rzg2l: Add FOUTPOSTDIV clk support Biju Das
2022-03-18 17:51 ` [PATCH 2/9] clk: renesas: rzg2l: Add PLL5_4 clk mux support Biju Das
@ 2022-03-18 17:51 ` Biju Das
2022-04-21 8:02 ` Geert Uytterhoeven
2022-03-18 17:51 ` [PATCH 4/9] clk: renesas: r9a07g044: Add M1 clock support Biju Das
` (5 subsequent siblings)
8 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2022-03-18 17:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB)
This patch add support for DSI divider clk by combaining
DSIDIVA and DSIDIVB .
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
RFC->V1
* Removed LUT and added an equation for computing VCLK.
---
drivers/clk/renesas/rzg2l-cpg.c | 114 ++++++++++++++++++++++++++++++++
drivers/clk/renesas/rzg2l-cpg.h | 13 ++++
2 files changed, 127 insertions(+)
diff --git a/drivers/clk/renesas/rzg2l-cpg.c b/drivers/clk/renesas/rzg2l-cpg.c
index f8e177ef3f93..6e52cdd1cffe 100644
--- a/drivers/clk/renesas/rzg2l-cpg.c
+++ b/drivers/clk/renesas/rzg2l-cpg.c
@@ -27,6 +27,7 @@
#include <linux/pm_domain.h>
#include <linux/reset-controller.h>
#include <linux/slab.h>
+#include <linux/units.h>
#include <dt-bindings/clock/renesas-cpg-mssr.h>
@@ -72,6 +73,8 @@ struct rzg2l_pll5_param {
u8 pl5_postdiv1;
u8 pl5_postdiv2;
u8 clksrc;
+ u8 dsi_div_a;
+ u8 dsi_div_b;
};
/**
@@ -279,6 +282,114 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
return clk_hw->clk;
}
+struct dsi_div_hw_data {
+ struct clk_hw hw;
+ u32 conf;
+ unsigned long rate;
+ struct rzg2l_cpg_priv *priv;
+};
+
+#define to_dsi_div_hw_data(_hw) container_of(_hw, struct dsi_div_hw_data, hw)
+
+static unsigned long rzg2l_cpg_dsi_div_recalc_rate(struct clk_hw *hw,
+ unsigned long parent_rate)
+{
+ struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
+
+ return dsi_div->rate;
+}
+
+static long rzg2l_cpg_dsi_div_round_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long *parent_rate)
+
+{
+ struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
+ struct rzg2l_cpg_priv *priv = dsi_div->priv;
+
+ dsi_div->rate = rate;
+
+ priv->pll5_params.pl5_intin = rate / MEGA;
+ priv->pll5_params.pl5_fracin = ((rate % MEGA) << 24) / MEGA;
+ priv->pll5_params.pl5_refdiv = 2;
+ priv->pll5_params.pl5_postdiv1 = 1;
+ priv->pll5_params.pl5_postdiv2 = 1;
+ priv->pll5_params.clksrc = 1;
+ priv->pll5_params.dsi_div_a = 1;
+ priv->pll5_params.dsi_div_b = 2;
+
+ priv->pll5_params.frequency =
+ EXTAL_FREQ_IN_MEGA_HZ * MEGA / priv->pll5_params.pl5_refdiv *
+ ((((priv->pll5_params.pl5_intin << 24) + priv->pll5_params.pl5_fracin)) >> 24) /
+ (priv->pll5_params.pl5_postdiv1 * priv->pll5_params.pl5_postdiv2);
+
+ if (priv->pll5_params.clksrc)
+ priv->pll5_params.frequency /= 2;
+
+ *parent_rate = priv->pll5_params.frequency;
+
+ return dsi_div->rate;
+}
+
+static int rzg2l_cpg_dsi_div_set_rate(struct clk_hw *hw,
+ unsigned long rate,
+ unsigned long parent_rate)
+{
+ struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
+ struct rzg2l_cpg_priv *priv = dsi_div->priv;
+
+ writel(CPG_PL5_SDIV_DIV_DSI_A_WEN | CPG_PL5_SDIV_DIV_DSI_B_WEN |
+ (priv->pll5_params.dsi_div_a << 0) | (priv->pll5_params.dsi_div_b << 8),
+ priv->base + CPG_PL5_SDIV);
+
+ return 0;
+}
+
+static const struct clk_ops rzg2l_cpg_dsi_div_ops = {
+ .recalc_rate = rzg2l_cpg_dsi_div_recalc_rate,
+ .round_rate = rzg2l_cpg_dsi_div_round_rate,
+ .set_rate = rzg2l_cpg_dsi_div_set_rate,
+};
+
+static struct clk * __init
+rzg2l_cpg_dsi_div_clk_register(const struct cpg_core_clk *core,
+ struct clk **clks,
+ struct rzg2l_cpg_priv *priv)
+{
+ struct dsi_div_hw_data *clk_hw_data;
+ const struct clk *parent;
+ const char *parent_name;
+ struct clk_init_data init;
+ struct clk_hw *clk_hw;
+ int ret;
+
+ parent = clks[core->parent & 0xffff];
+ if (IS_ERR(parent))
+ return ERR_CAST(parent);
+
+ clk_hw_data = devm_kzalloc(priv->dev, sizeof(*clk_hw_data), GFP_KERNEL);
+ if (!clk_hw_data)
+ return ERR_PTR(-ENOMEM);
+
+ clk_hw_data->priv = priv;
+
+ parent_name = __clk_get_name(parent);
+ init.name = core->name;
+ init.ops = &rzg2l_cpg_dsi_div_ops;
+ init.flags = CLK_SET_RATE_PARENT;
+ init.parent_names = &parent_name;
+ init.num_parents = 1;
+
+ clk_hw = &clk_hw_data->hw;
+ clk_hw->init = &init;
+
+ ret = devm_clk_hw_register(priv->dev, clk_hw);
+ if (ret)
+ return ERR_PTR(ret);
+
+ return clk_hw->clk;
+}
+
struct pll5_mux_hw_data {
struct clk_hw hw;
u32 conf;
@@ -654,6 +765,9 @@ rzg2l_cpg_register_core_clk(const struct cpg_core_clk *core,
case CLK_TYPE_PLL5_4_MUX:
clk = rzg2l_cpg_pll5_4_mux_clk_register(core, priv);
break;
+ case CLK_TYPE_DSI_DIV:
+ clk = rzg2l_cpg_dsi_div_clk_register(core, priv->clks, priv);
+ break;
default:
goto fail;
}
diff --git a/drivers/clk/renesas/rzg2l-cpg.h b/drivers/clk/renesas/rzg2l-cpg.h
index a4bdc1d7b5aa..c75db039b444 100644
--- a/drivers/clk/renesas/rzg2l-cpg.h
+++ b/drivers/clk/renesas/rzg2l-cpg.h
@@ -24,6 +24,7 @@
#define CPG_PL3_SSEL (0x408)
#define CPG_PL6_SSEL (0x414)
#define CPG_PL6_ETH_SSEL (0x418)
+#define CPG_PL5_SDIV (0x420)
#define CPG_OTHERFUNC1_REG (0xBE8)
#define CPG_SIPLL5_STBY_RESETB BIT(0)
@@ -37,6 +38,11 @@
#define CPG_OTHERFUNC1_REG_RES0_ON_WEN BIT(16)
+#define CPG_PL5_SDIV_DIV_DSI_A_WEN BIT(16)
+#define CPG_PL5_SDIV_DIV_DSI_B_WEN BIT(24)
+
+#define EXTAL_FREQ_IN_MEGA_HZ (24)
+
#define CPG_CLKSTATUS_SELSDHI0_STS BIT(28)
#define CPG_CLKSTATUS_SELSDHI1_STS BIT(29)
@@ -52,6 +58,7 @@
(((offset) << 20) | ((bitpos) << 12) | ((size) << 8))
#define DIVPL1A DDIV_PACK(CPG_PL1_DDIV, 0, 2)
#define DIVPL2A DDIV_PACK(CPG_PL2_DDIV, 0, 3)
+#define DIVDSILPCLK DDIV_PACK(CPG_PL2_DDIV, 12, 2)
#define DIVPL3A DDIV_PACK(CPG_PL3A_DDIV, 0, 3)
#define DIVPL3B DDIV_PACK(CPG_PL3A_DDIV, 4, 3)
#define DIVPL3C DDIV_PACK(CPG_PL3A_DDIV, 8, 3)
@@ -111,6 +118,10 @@ enum clk_types {
/* Clock for PLL5_4 clock source selector */
CLK_TYPE_PLL5_4_MUX,
+
+ /* Clock for DSI divider */
+ CLK_TYPE_DSI_DIV,
+
};
#define DEF_TYPE(_name, _id, _type...) \
@@ -139,6 +150,8 @@ enum clk_types {
#define DEF_PLL5_4_MUX(_name, _id, _conf, _parent_names, _num_parents) \
DEF_TYPE(_name, _id, CLK_TYPE_PLL5_4_MUX, .conf = _conf, \
.parent_names = _parent_names, .num_parents = _num_parents)
+#define DEF_DSI_DIV(_name, _id, _parent, _flag) \
+ DEF_TYPE(_name, _id, CLK_TYPE_DSI_DIV, .parent = _parent, .flag = _flag)
/**
* struct rzg2l_mod_clk - Module Clocks definitions
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 4/9] clk: renesas: r9a07g044: Add M1 clock support
2022-03-18 17:51 [PATCH 0/9] Add RZ/G2L Display clock support Biju Das
` (2 preceding siblings ...)
2022-03-18 17:51 ` [PATCH 3/9] clk: renesas: rzg2l: Add DSI divider clk support Biju Das
@ 2022-03-18 17:51 ` Biju Das
2022-03-18 17:51 ` [PATCH 5/9] clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support Biju Das
` (4 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2022-03-18 17:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add support for M1 clock which is sourced from FOUTPOSTDIV.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
RFC->V1:
* Added Rb tag from Geert
---
drivers/clk/renesas/r9a07g044-cpg.c | 11 ++++++++++-
1 file changed, 10 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index bdfabb992a20..0c9fa1f705af 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -40,6 +40,8 @@ enum clk_ids {
CLK_DIV_PLL3_C,
CLK_PLL4,
CLK_PLL5,
+ CLK_PLL5_FOUTPOSTDIV,
+ CLK_PLL5_FOUT1PH0,
CLK_PLL5_FOUT3,
CLK_PLL5_250,
CLK_PLL6,
@@ -52,6 +54,7 @@ enum clk_ids {
CLK_SD0_DIV4,
CLK_SD1_DIV4,
CLK_SEL_GPU2,
+ CLK_SEL_PLL5_4,
/* Module Clocks */
MOD_CLK_BASE,
@@ -77,12 +80,13 @@ static const struct clk_div_table dtable_1_32[] = {
/* Mux clock tables */
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
+static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };
static const char * const sel_pll6_2[] = { ".pll6_250", ".pll5_250" };
static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
static const struct {
- struct cpg_core_clk common[44];
+ struct cpg_core_clk common[48];
#ifdef CONFIG_CLK_R9A07G054
struct cpg_core_clk drp[0];
#endif
@@ -127,6 +131,10 @@ static const struct {
DEF_FIXED(".pll6_250", CLK_PLL6_250, CLK_PLL6, 1, 2),
DEF_MUX(".sel_gpu2", CLK_SEL_GPU2, SEL_GPU2,
sel_gpu2, ARRAY_SIZE(sel_gpu2), 0, CLK_MUX_READ_ONLY),
+ DEF_PLL5_FOUTPOSTDIV(".pll5_foutpostdiv", CLK_PLL5_FOUTPOSTDIV, CLK_EXTAL),
+ DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2),
+ DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4,
+ sel_pll5_4, ARRAY_SIZE(sel_pll5_4)),
/* Core output clk */
DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
@@ -154,6 +162,7 @@ static const struct {
DEF_FIXED("SD1_DIV4", CLK_SD1_DIV4, R9A07G044_CLK_SD1, 1, 4),
DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
CLK_DIVIDER_HIWORD_MASK),
+ DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1),
},
#ifdef CONFIG_CLK_R9A07G054
.drp = {
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 5/9] clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support
2022-03-18 17:51 [PATCH 0/9] Add RZ/G2L Display clock support Biju Das
` (3 preceding siblings ...)
2022-03-18 17:51 ` [PATCH 4/9] clk: renesas: r9a07g044: Add M1 clock support Biju Das
@ 2022-03-18 17:51 ` Biju Das
2022-03-18 17:51 ` [PATCH 6/9] clk: renesas: r9a07g044: Add M3 Clock support Biju Das
` (3 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2022-03-18 17:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add support for {M2, M2_DIV2} clocks which is sourced from pll3_533.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
RFC->V1:
* Added Rb tag from Geert
---
drivers/clk/renesas/r9a07g044-cpg.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 0c9fa1f705af..d350d6dce4b1 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -32,6 +32,7 @@ enum clk_ids {
CLK_PLL3,
CLK_PLL3_400,
CLK_PLL3_533,
+ CLK_M2_DIV2,
CLK_PLL3_DIV2,
CLK_PLL3_DIV2_2,
CLK_PLL3_DIV2_4,
@@ -86,7 +87,7 @@ static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
static const struct {
- struct cpg_core_clk common[48];
+ struct cpg_core_clk common[50];
#ifdef CONFIG_CLK_R9A07G054
struct cpg_core_clk drp[0];
#endif
@@ -163,6 +164,8 @@ static const struct {
DEF_DIV("G", R9A07G044_CLK_G, CLK_SEL_GPU2, DIVGPU, dtable_1_8,
CLK_DIVIDER_HIWORD_MASK),
DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1),
+ DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2),
+ DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2),
},
#ifdef CONFIG_CLK_R9A07G054
.drp = {
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 6/9] clk: renesas: r9a07g044: Add M3 Clock support
2022-03-18 17:51 [PATCH 0/9] Add RZ/G2L Display clock support Biju Das
` (4 preceding siblings ...)
2022-03-18 17:51 ` [PATCH 5/9] clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support Biju Das
@ 2022-03-18 17:51 ` Biju Das
2022-03-18 17:51 ` [PATCH 7/9] clk: renesas: r9a07g044: Add M4 " Biju Das
` (2 subsequent siblings)
8 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2022-03-18 17:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add support for M3 clock which is sourced from DSI divider connected
to PLL5_4 mux.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
RFC->V1:
* Added Rb tag from Geert
---
drivers/clk/renesas/r9a07g044-cpg.c | 5 ++++-
1 file changed, 4 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index d350d6dce4b1..cee552bdf3cc 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -56,6 +56,7 @@ enum clk_ids {
CLK_SD1_DIV4,
CLK_SEL_GPU2,
CLK_SEL_PLL5_4,
+ CLK_DSI_DIV,
/* Module Clocks */
MOD_CLK_BASE,
@@ -87,7 +88,7 @@ static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
static const struct {
- struct cpg_core_clk common[50];
+ struct cpg_core_clk common[52];
#ifdef CONFIG_CLK_R9A07G054
struct cpg_core_clk drp[0];
#endif
@@ -166,6 +167,8 @@ static const struct {
DEF_FIXED("M1", R9A07G044_CLK_M1, CLK_PLL5_FOUTPOSTDIV, 1, 1),
DEF_FIXED("M2", R9A07G044_CLK_M2, CLK_PLL3_533, 1, 2),
DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2),
+ DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT),
+ DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1),
},
#ifdef CONFIG_CLK_R9A07G054
.drp = {
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 7/9] clk: renesas: r9a07g044: Add M4 Clock support
2022-03-18 17:51 [PATCH 0/9] Add RZ/G2L Display clock support Biju Das
` (5 preceding siblings ...)
2022-03-18 17:51 ` [PATCH 6/9] clk: renesas: r9a07g044: Add M3 Clock support Biju Das
@ 2022-03-18 17:51 ` Biju Das
2022-03-18 17:51 ` [PATCH 8/9] clk: renesas: r9a07g044: Add LCDC clock and reset entries Biju Das
2022-03-18 17:51 ` [PATCH 9/9] clk: renesas: r9a07g044: Add DSI " Biju Das
8 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2022-03-18 17:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add support for M4 clock which is sourced from pll2_533_div2.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
RFC->V1:
* Added Rb tag from Geert
---
drivers/clk/renesas/r9a07g044-cpg.c | 19 ++++++++++++++++++-
1 file changed, 18 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index cee552bdf3cc..66608696d2e2 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -57,6 +57,9 @@ enum clk_ids {
CLK_SEL_GPU2,
CLK_SEL_PLL5_4,
CLK_DSI_DIV,
+ CLK_PLL2_533,
+ CLK_PLL2_533_DIV2,
+ CLK_DIV_DSI_LPCLK,
/* Module Clocks */
MOD_CLK_BASE,
@@ -80,6 +83,14 @@ static const struct clk_div_table dtable_1_32[] = {
{0, 0},
};
+static const struct clk_div_table dtable_16_128[] = {
+ {0, 16},
+ {1, 32},
+ {2, 64},
+ {3, 128},
+ {0, 0},
+};
+
/* Mux clock tables */
static const char * const sel_pll3_3[] = { ".pll3_533", ".pll3_400" };
static const char * const sel_pll5_4[] = { ".pll5_foutpostdiv", ".pll5_fout1ph0" };
@@ -88,7 +99,7 @@ static const char * const sel_shdi[] = { ".clk_533", ".clk_400", ".clk_266" };
static const char * const sel_gpu2[] = { ".pll6", ".pll3_div2_2" };
static const struct {
- struct cpg_core_clk common[52];
+ struct cpg_core_clk common[56];
#ifdef CONFIG_CLK_R9A07G054
struct cpg_core_clk drp[0];
#endif
@@ -102,6 +113,7 @@ static const struct {
DEF_FIXED(".osc_div1000", CLK_OSC_DIV1000, CLK_EXTAL, 1, 1000),
DEF_SAMPLL(".pll1", CLK_PLL1, CLK_EXTAL, PLL146_CONF(0)),
DEF_FIXED(".pll2", CLK_PLL2, CLK_EXTAL, 200, 3),
+ DEF_FIXED(".pll2_533", CLK_PLL2_533, CLK_PLL2, 1, 3),
DEF_FIXED(".pll3", CLK_PLL3, CLK_EXTAL, 200, 3),
DEF_FIXED(".pll3_400", CLK_PLL3_400, CLK_PLL3, 1, 4),
DEF_FIXED(".pll3_533", CLK_PLL3_533, CLK_PLL3, 1, 3),
@@ -120,6 +132,8 @@ static const struct {
DEF_FIXED(".pll2_div2_8", CLK_PLL2_DIV2_8, CLK_PLL2_DIV2, 1, 8),
DEF_FIXED(".pll2_div2_10", CLK_PLL2_DIV2_10, CLK_PLL2_DIV2, 1, 10),
+ DEF_FIXED(".pll2_533_div2", CLK_PLL2_533_DIV2, CLK_PLL2_533, 1, 2),
+
DEF_FIXED(".pll3_div2", CLK_PLL3_DIV2, CLK_PLL3, 1, 2),
DEF_FIXED(".pll3_div2_2", CLK_PLL3_DIV2_2, CLK_PLL3_DIV2, 1, 2),
DEF_FIXED(".pll3_div2_4", CLK_PLL3_DIV2_4, CLK_PLL3_DIV2, 1, 4),
@@ -137,6 +151,8 @@ static const struct {
DEF_FIXED(".pll5_fout1ph0", CLK_PLL5_FOUT1PH0, CLK_PLL5_FOUTPOSTDIV, 1, 2),
DEF_PLL5_4_MUX(".sel_pll5_4", CLK_SEL_PLL5_4, SEL_PLL5_4,
sel_pll5_4, ARRAY_SIZE(sel_pll5_4)),
+ DEF_DIV(".div_dsi_lpclk", CLK_DIV_DSI_LPCLK, CLK_PLL2_533_DIV2,
+ DIVDSILPCLK, dtable_16_128, CLK_DIVIDER_HIWORD_MASK),
/* Core output clk */
DEF_DIV("I", R9A07G044_CLK_I, CLK_PLL1, DIVPL1A, dtable_1_8,
@@ -169,6 +185,7 @@ static const struct {
DEF_FIXED("M2_DIV2", CLK_M2_DIV2, R9A07G044_CLK_M2, 1, 2),
DEF_DSI_DIV("DSI_DIV", CLK_DSI_DIV, CLK_SEL_PLL5_4, CLK_SET_RATE_PARENT),
DEF_FIXED("M3", R9A07G044_CLK_M3, CLK_DSI_DIV, 1, 1),
+ DEF_FIXED("M4", R9A07G044_CLK_M4, CLK_DIV_DSI_LPCLK, 1, 1),
},
#ifdef CONFIG_CLK_R9A07G054
.drp = {
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 8/9] clk: renesas: r9a07g044: Add LCDC clock and reset entries
2022-03-18 17:51 [PATCH 0/9] Add RZ/G2L Display clock support Biju Das
` (6 preceding siblings ...)
2022-03-18 17:51 ` [PATCH 7/9] clk: renesas: r9a07g044: Add M4 " Biju Das
@ 2022-03-18 17:51 ` Biju Das
2022-03-18 17:51 ` [PATCH 9/9] clk: renesas: r9a07g044: Add DSI " Biju Das
8 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2022-03-18 17:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add LCDC clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
RFC->V1:
* Added Rb tag from Geert
---
drivers/clk/renesas/r9a07g044-cpg.c | 9 ++++++++-
1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index 66608696d2e2..b5ddc5058670 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -194,7 +194,7 @@ static const struct {
};
static const struct {
- struct rzg2l_mod_clk common[62];
+ struct rzg2l_mod_clk common[65];
#ifdef CONFIG_CLK_R9A07G054
struct rzg2l_mod_clk drp[0];
#endif
@@ -254,6 +254,12 @@ static const struct {
0x558, 1),
DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
0x558, 2),
+ DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0,
+ 0x56c, 0),
+ DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT,
+ 0x56c, 0),
+ DEF_MOD("lcdc_clk_d", R9A07G044_LCDC_CLK_D, R9A07G044_CLK_M3,
+ 0x56c, 1),
DEF_MOD("ssi0_pclk", R9A07G044_SSI0_PCLK2, R9A07G044_CLK_P0,
0x570, 0),
DEF_MOD("ssi0_sfr", R9A07G044_SSI0_PCLK_SFR, R9A07G044_CLK_P0,
@@ -349,6 +355,7 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
+ DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0),
DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
DEF_RST(R9A07G044_SSI2_RST_M2_REG, 0x870, 2),
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 9/9] clk: renesas: r9a07g044: Add DSI clock and reset entries
2022-03-18 17:51 [PATCH 0/9] Add RZ/G2L Display clock support Biju Das
` (7 preceding siblings ...)
2022-03-18 17:51 ` [PATCH 8/9] clk: renesas: r9a07g044: Add LCDC clock and reset entries Biju Das
@ 2022-03-18 17:51 ` Biju Das
8 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2022-03-18 17:51 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add DSI clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
---
RFC->V1:
* Added Rb tag from Geert
---
drivers/clk/renesas/r9a07g044-cpg.c | 17 ++++++++++++++++-
1 file changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/clk/renesas/r9a07g044-cpg.c b/drivers/clk/renesas/r9a07g044-cpg.c
index b5ddc5058670..57ec50659bb3 100644
--- a/drivers/clk/renesas/r9a07g044-cpg.c
+++ b/drivers/clk/renesas/r9a07g044-cpg.c
@@ -194,7 +194,7 @@ static const struct {
};
static const struct {
- struct rzg2l_mod_clk common[65];
+ struct rzg2l_mod_clk common[71];
#ifdef CONFIG_CLK_R9A07G054
struct rzg2l_mod_clk drp[0];
#endif
@@ -254,6 +254,18 @@ static const struct {
0x558, 1),
DEF_MOD("gpu_ace_clk", R9A07G044_GPU_ACE_CLK, R9A07G044_CLK_P1,
0x558, 2),
+ DEF_MOD("dsi_pll_clk", R9A07G044_MIPI_DSI_PLLCLK, R9A07G044_CLK_M1,
+ 0x568, 0),
+ DEF_MOD("dsi_sys_clk", R9A07G044_MIPI_DSI_SYSCLK, CLK_M2_DIV2,
+ 0x568, 1),
+ DEF_MOD("dsi_aclk", R9A07G044_MIPI_DSI_ACLK, R9A07G044_CLK_P1,
+ 0x568, 2),
+ DEF_MOD("dsi_pclk", R9A07G044_MIPI_DSI_PCLK, R9A07G044_CLK_P2,
+ 0x568, 3),
+ DEF_MOD("dsi_vclk", R9A07G044_MIPI_DSI_VCLK, R9A07G044_CLK_M3,
+ 0x568, 4),
+ DEF_MOD("dsi_lpclk", R9A07G044_MIPI_DSI_LPCLK, R9A07G044_CLK_M4,
+ 0x568, 5),
DEF_COUPLED("lcdc_a", R9A07G044_LCDC_CLK_A, R9A07G044_CLK_M0,
0x56c, 0),
DEF_COUPLED("lcdc_p", R9A07G044_LCDC_CLK_P, R9A07G044_CLK_ZT,
@@ -355,6 +367,9 @@ static struct rzg2l_reset r9a07g044_resets[] = {
DEF_RST(R9A07G044_GPU_RESETN, 0x858, 0),
DEF_RST(R9A07G044_GPU_AXI_RESETN, 0x858, 1),
DEF_RST(R9A07G044_GPU_ACE_RESETN, 0x858, 2),
+ DEF_RST(R9A07G044_MIPI_DSI_CMN_RSTB, 0x868, 0),
+ DEF_RST(R9A07G044_MIPI_DSI_ARESET_N, 0x868, 1),
+ DEF_RST(R9A07G044_MIPI_DSI_PRESET_N, 0x868, 2),
DEF_RST(R9A07G044_LCDC_RESET_N, 0x86c, 0),
DEF_RST(R9A07G044_SSI0_RST_M2_REG, 0x870, 0),
DEF_RST(R9A07G044_SSI1_RST_M2_REG, 0x870, 1),
--
2.17.1
^ permalink raw reply related [flat|nested] 18+ messages in thread
* Re: [PATCH 1/9] clk: renesas: rzg2l: Add FOUTPOSTDIV clk support
2022-03-18 17:51 ` [PATCH 1/9] clk: renesas: rzg2l: Add FOUTPOSTDIV clk support Biju Das
@ 2022-04-21 7:44 ` Geert Uytterhoeven
2022-04-22 11:04 ` Biju Das
0 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2022-04-21 7:44 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Biju,
On Fri, Mar 18, 2022 at 6:51 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules.
> The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced
> from DSI divider which is connected to PLL5_4 MUX.
>
> This patch adds support for generating FOUTPOSTDIV clk.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> RFC->V1:
> * Removed LUT.
> * Replaced magic numbers with macros.
Thanks for the update!
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -266,6 +278,131 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
> return clk_hw->clk;
> }
>
> +struct sipll5 {
> + struct clk_hw hw;
> + u32 conf;
> + struct rzg2l_cpg_priv *priv;
> +};
> +
> +#define to_sipll5(_hw) container_of(_hw, struct sipll5, hw)
> +
> +static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct sipll5 *sipll5 = to_sipll5(hw);
> + struct rzg2l_cpg_priv *priv = sipll5->priv;
> +
> + return priv->pll5_params.frequency;
> +}
> +
> +static long rzg2l_cpg_sipll5_round_rate(struct clk_hw *hw,
> + unsigned long rate,
> + unsigned long *parent_rate)
> +{
> + struct sipll5 *sipll5 = to_sipll5(hw);
> + struct rzg2l_cpg_priv *priv = sipll5->priv;
> +
> + return priv->pll5_params.frequency;
> +}
> +
> +static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
> + unsigned long rate,
> + unsigned long parent_rate)
> +{
The above 3 functions all ignore their input rates and parent_rates,
as you rely on setting up pll5_params in the DSI divider (patch 3),
and the clock core propagating up to all parents (PLL5_4 in patch 2,
and FOUTPOSDIV here), right?
I think it would help to document that somewhere.
The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/9] clk: renesas: rzg2l: Add PLL5_4 clk mux support
2022-03-18 17:51 ` [PATCH 2/9] clk: renesas: rzg2l: Add PLL5_4 clk mux support Biju Das
@ 2022-04-21 7:47 ` Geert Uytterhoeven
2022-04-22 11:11 ` Biju Das
0 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2022-04-21 7:47 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Biju,
On Fri, Mar 18, 2022 at 6:51 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add PLL5_4 clk mux support to select clock from clock
> sources FOUTPOSTDIV and FOUT1PH0.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> RFC->V1:
> * Removed LUT.
Thanks for the update!
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -71,6 +71,7 @@ struct rzg2l_pll5_param {
> u8 pl5_intin;
> u8 pl5_postdiv1;
> u8 pl5_postdiv2;
> + u8 clksrc;
> };
I understand you cannot use the plain DEF_MUX() here, as "clksrc"
is set up in pll5_params in the DSI divider (patch 3), and you rely
on parent propagation again to program the mux according to that?
I think it would help to document that somewhere.
The rest LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/9] clk: renesas: rzg2l: Add DSI divider clk support
2022-03-18 17:51 ` [PATCH 3/9] clk: renesas: rzg2l: Add DSI divider clk support Biju Das
@ 2022-04-21 8:02 ` Geert Uytterhoeven
2022-04-22 11:15 ` Biju Das
0 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2022-04-21 8:02 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Biju,
On Fri, Mar 18, 2022 at 6:51 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB)
>
> This patch add support for DSI divider clk by combaining
> DSIDIVA and DSIDIVB .
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> ---
> RFC->V1
> * Removed LUT and added an equation for computing VCLK.
Thanks for the update!
> --- a/drivers/clk/renesas/rzg2l-cpg.c
> +++ b/drivers/clk/renesas/rzg2l-cpg.c
> @@ -279,6 +282,114 @@ rzg2l_cpg_sd_mux_clk_register(const struct cpg_core_clk *core,
> return clk_hw->clk;
> }
>
> +struct dsi_div_hw_data {
> + struct clk_hw hw;
> + u32 conf;
> + unsigned long rate;
> + struct rzg2l_cpg_priv *priv;
> +};
> +
> +#define to_dsi_div_hw_data(_hw) container_of(_hw, struct dsi_div_hw_data, hw)
> +
> +static unsigned long rzg2l_cpg_dsi_div_recalc_rate(struct clk_hw *hw,
> + unsigned long parent_rate)
> +{
> + struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
> +
> + return dsi_div->rate;
> +}
> +
> +static long rzg2l_cpg_dsi_div_round_rate(struct clk_hw *hw,
> + unsigned long rate,
> + unsigned long *parent_rate)
Please implement the determine_rate() instead.
> +
Please drop the blank line.
> +{
> + struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
> + struct rzg2l_cpg_priv *priv = dsi_div->priv;
> +
> + dsi_div->rate = rate;
> +
> + priv->pll5_params.pl5_intin = rate / MEGA;
.round_rate() (and .determine_rate()) is used to check if a rate
is supported, without actually changing the clock rate. Hence this
should not operate on priv->pll5_params, but on a local variable.
> + priv->pll5_params.pl5_fracin = ((rate % MEGA) << 24) / MEGA;
While this works fine on 64-bit (RZ/G2L is arm64, so that's OK),
"(rate % MEGA) << 24" will overflow when compile-testing on 32-bit.
Taking into account the 64-by-32 division, I think this should be:
div_u64(((u64)rate % MEGA) << 24, MEGA);
> + priv->pll5_params.pl5_refdiv = 2;
> + priv->pll5_params.pl5_postdiv1 = 1;
> + priv->pll5_params.pl5_postdiv2 = 1;
> + priv->pll5_params.clksrc = 1;
> + priv->pll5_params.dsi_div_a = 1;
> + priv->pll5_params.dsi_div_b = 2;
> +
> + priv->pll5_params.frequency =
> + EXTAL_FREQ_IN_MEGA_HZ * MEGA / priv->pll5_params.pl5_refdiv *
> + ((((priv->pll5_params.pl5_intin << 24) + priv->pll5_params.pl5_fracin)) >> 24) /
> + (priv->pll5_params.pl5_postdiv1 * priv->pll5_params.pl5_postdiv2);
> +
> + if (priv->pll5_params.clksrc)
> + priv->pll5_params.frequency /= 2;
> +
> + *parent_rate = priv->pll5_params.frequency;
> +
> + return dsi_div->rate;
> +}
> +
> +static int rzg2l_cpg_dsi_div_set_rate(struct clk_hw *hw,
> + unsigned long rate,
> + unsigned long parent_rate)
> +{
> + struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
> + struct rzg2l_cpg_priv *priv = dsi_div->priv;
> +
You should update priv->pll5_params here, instead of in your
.round_rate() callback.
> + writel(CPG_PL5_SDIV_DIV_DSI_A_WEN | CPG_PL5_SDIV_DIV_DSI_B_WEN |
> + (priv->pll5_params.dsi_div_a << 0) | (priv->pll5_params.dsi_div_b << 8),
> + priv->base + CPG_PL5_SDIV);
> +
> + return 0;
> +}
The rest LGTM.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 1/9] clk: renesas: rzg2l: Add FOUTPOSTDIV clk support
2022-04-21 7:44 ` Geert Uytterhoeven
@ 2022-04-22 11:04 ` Biju Das
0 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2022-04-22 11:04 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 1/9] clk: renesas: rzg2l: Add FOUTPOSTDIV clk support
>
> Hi Biju,
>
> On Fri, Mar 18, 2022 at 6:51 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > PLL5 generates FOUTPOSTDIV clk and is sourced by LCDC/DSI modules.
> > The FOUTPOSTDIV is connected to PLL5_4 MUX. Video clock is sourced
> > from DSI divider which is connected to PLL5_4 MUX.
> >
> > This patch adds support for generating FOUTPOSTDIV clk.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > RFC->V1:
> > * Removed LUT.
> > * Replaced magic numbers with macros.
>
> Thanks for the update!
>
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
>
> > @@ -266,6 +278,131 @@ rzg2l_cpg_sd_mux_clk_register(const struct
> cpg_core_clk *core,
> > return clk_hw->clk;
> > }
> >
> > +struct sipll5 {
> > + struct clk_hw hw;
> > + u32 conf;
> > + struct rzg2l_cpg_priv *priv;
> > +};
> > +
> > +#define to_sipll5(_hw) container_of(_hw, struct sipll5, hw)
> > +
> > +static unsigned long rzg2l_cpg_sipll5_recalc_rate(struct clk_hw *hw,
> > + unsigned long
> > +parent_rate) {
> > + struct sipll5 *sipll5 = to_sipll5(hw);
> > + struct rzg2l_cpg_priv *priv = sipll5->priv;
> > +
> > + return priv->pll5_params.frequency; }
> > +
> > +static long rzg2l_cpg_sipll5_round_rate(struct clk_hw *hw,
> > + unsigned long rate,
> > + unsigned long *parent_rate) {
> > + struct sipll5 *sipll5 = to_sipll5(hw);
> > + struct rzg2l_cpg_priv *priv = sipll5->priv;
> > +
> > + return priv->pll5_params.frequency; }
> > +
> > +static int rzg2l_cpg_sipll5_set_rate(struct clk_hw *hw,
> > + unsigned long rate,
> > + unsigned long parent_rate) {
>
> The above 3 functions all ignore their input rates and parent_rates, as you
> rely on setting up pll5_params in the DSI divider (patch 3), and the clock
> core propagating up to all parents (PLL5_4 in patch 2, and FOUTPOSDIV
> here), right?
Yes, that is correct, PLL5 parameters are calculated based on video clock in DSI divider(patch3)
And propagating up to here and setting parent's clkrates based on that.
>
> I think it would help to document that somewhere.
OK Will Document this
Cheers,
Biju
>
> The rest LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 2/9] clk: renesas: rzg2l: Add PLL5_4 clk mux support
2022-04-21 7:47 ` Geert Uytterhoeven
@ 2022-04-22 11:11 ` Biju Das
0 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2022-04-22 11:11 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 2/9] clk: renesas: rzg2l: Add PLL5_4 clk mux support
>
> Hi Biju,
>
> On Fri, Mar 18, 2022 at 6:51 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Add PLL5_4 clk mux support to select clock from clock sources
> > FOUTPOSTDIV and FOUT1PH0.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > RFC->V1:
> > * Removed LUT.
>
> Thanks for the update!
>
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > @@ -71,6 +71,7 @@ struct rzg2l_pll5_param {
> > u8 pl5_intin;
> > u8 pl5_postdiv1;
> > u8 pl5_postdiv2;
> > + u8 clksrc;
> > };
>
> I understand you cannot use the plain DEF_MUX() here, as "clksrc"
> is set up in pll5_params in the DSI divider (patch 3), and you rely on
> parent propagation again to program the mux according to that?
Yes, That is correct. Clk src for Display Parallel interface always need to be "0"
and for DSI it can be 0 or 1. Currently for DSI, through generic equation we can
generate PLL5 frequencies for various resolutions using clk src "1".
This needs to be extended for parallel interface when we add support for it.
>
> I think it would help to document that somewhere.
OK will Document this.
Regards,
Biju
>
> The rest LGTM, so
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 3/9] clk: renesas: rzg2l: Add DSI divider clk support
2022-04-21 8:02 ` Geert Uytterhoeven
@ 2022-04-22 11:15 ` Biju Das
2022-04-22 15:10 ` Geert Uytterhoeven
0 siblings, 1 reply; 18+ messages in thread
From: Biju Das @ 2022-04-22 11:15 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 3/9] clk: renesas: rzg2l: Add DSI divider clk support
>
> Hi Biju,
>
> On Fri, Mar 18, 2022 at 6:51 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB)
> >
> > This patch add support for DSI divider clk by combaining DSIDIVA and
> > DSIDIVB .
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > ---
> > RFC->V1
> > * Removed LUT and added an equation for computing VCLK.
>
> Thanks for the update!
>
> > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > @@ -279,6 +282,114 @@ rzg2l_cpg_sd_mux_clk_register(const struct
> cpg_core_clk *core,
> > return clk_hw->clk;
> > }
> >
> > +struct dsi_div_hw_data {
> > + struct clk_hw hw;
> > + u32 conf;
> > + unsigned long rate;
> > + struct rzg2l_cpg_priv *priv;
> > +};
> > +
> > +#define to_dsi_div_hw_data(_hw) container_of(_hw, struct
> dsi_div_hw_data, hw)
> > +
> > +static unsigned long rzg2l_cpg_dsi_div_recalc_rate(struct clk_hw *hw,
> > + unsigned long
> > +parent_rate) {
> > + struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
> > +
> > + return dsi_div->rate;
> > +}
> > +
> > +static long rzg2l_cpg_dsi_div_round_rate(struct clk_hw *hw,
> > + unsigned long rate,
> > + unsigned long *parent_rate)
>
> Please implement the determine_rate() instead.
OK.
>
> > +
>
> Please drop the blank line.
OK.
>
> > +{
> > + struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
> > + struct rzg2l_cpg_priv *priv = dsi_div->priv;
> > +
> > + dsi_div->rate = rate;
> > +
> > + priv->pll5_params.pl5_intin = rate / MEGA;
>
> .round_rate() (and .determine_rate()) is used to check if a rate is
> supported, without actually changing the clock rate. Hence this should not
> operate on priv->pll5_params, but on a local variable.
>
> > + priv->pll5_params.pl5_fracin = ((rate % MEGA) << 24) / MEGA;
>
> While this works fine on 64-bit (RZ/G2L is arm64, so that's OK), "(rate %
> MEGA) << 24" will overflow when compile-testing on 32-bit.
> Taking into account the 64-by-32 division, I think this should be:
>
> div_u64(((u64)rate % MEGA) << 24, MEGA);
OK.
>
> > + priv->pll5_params.pl5_refdiv = 2;
> > + priv->pll5_params.pl5_postdiv1 = 1;
> > + priv->pll5_params.pl5_postdiv2 = 1;
> > + priv->pll5_params.clksrc = 1;
> > + priv->pll5_params.dsi_div_a = 1;
> > + priv->pll5_params.dsi_div_b = 2;
> > +
> > + priv->pll5_params.frequency =
> > + EXTAL_FREQ_IN_MEGA_HZ * MEGA / priv-
> >pll5_params.pl5_refdiv *
> > + ((((priv->pll5_params.pl5_intin << 24) + priv-
> >pll5_params.pl5_fracin)) >> 24) /
> > + (priv->pll5_params.pl5_postdiv1 *
> > + priv->pll5_params.pl5_postdiv2);
> > +
> > + if (priv->pll5_params.clksrc)
> > + priv->pll5_params.frequency /= 2;
> > +
> > + *parent_rate = priv->pll5_params.frequency;
> > +
> > + return dsi_div->rate;
> > +}
> > +
> > +static int rzg2l_cpg_dsi_div_set_rate(struct clk_hw *hw,
> > + unsigned long rate,
> > + unsigned long parent_rate) {
> > + struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
> > + struct rzg2l_cpg_priv *priv = dsi_div->priv;
> > +
>
> You should update priv->pll5_params here, instead of in your
> .round_rate() callback.
I need to find parent_rate based on video clock during {determine,round rate}
I have added there to avoid duplication.
I agree, the following to be set here instead of round_rate() callback.
dsi_div->rate = rate;
Cheers,
Biju
>
> > + writel(CPG_PL5_SDIV_DIV_DSI_A_WEN | CPG_PL5_SDIV_DIV_DSI_B_WEN |
> > + (priv->pll5_params.dsi_div_a << 0) | (priv-
> >pll5_params.dsi_div_b << 8),
> > + priv->base + CPG_PL5_SDIV);
> > +
> > + return 0;
> > +}
>
> The rest LGTM.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 3/9] clk: renesas: rzg2l: Add DSI divider clk support
2022-04-22 11:15 ` Biju Das
@ 2022-04-22 15:10 ` Geert Uytterhoeven
2022-04-26 17:04 ` Biju Das
0 siblings, 1 reply; 18+ messages in thread
From: Geert Uytterhoeven @ 2022-04-22 15:10 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Biju,
On Fri, Apr 22, 2022 at 1:15 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Subject: Re: [PATCH 3/9] clk: renesas: rzg2l: Add DSI divider clk support
> > On Fri, Mar 18, 2022 at 6:51 PM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > > M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB)
> > >
> > > This patch add support for DSI divider clk by combaining DSIDIVA and
> > > DSIDIVB .
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > > +static long rzg2l_cpg_dsi_div_round_rate(struct clk_hw *hw,
> > > + unsigned long rate,
> > > + unsigned long *parent_rate)
> > > +{
> > > + struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
> > > + struct rzg2l_cpg_priv *priv = dsi_div->priv;
> > > +
> > > + dsi_div->rate = rate;
> > > +
> > > + priv->pll5_params.pl5_intin = rate / MEGA;
> >
> > .round_rate() (and .determine_rate()) is used to check if a rate is
> > supported, without actually changing the clock rate. Hence this should not
> > operate on priv->pll5_params, but on a local variable.
> >
> > > + priv->pll5_params.pl5_fracin = ((rate % MEGA) << 24) / MEGA;
> > > + priv->pll5_params.pl5_refdiv = 2;
> > > + priv->pll5_params.pl5_postdiv1 = 1;
> > > + priv->pll5_params.pl5_postdiv2 = 1;
> > > + priv->pll5_params.clksrc = 1;
> > > + priv->pll5_params.dsi_div_a = 1;
> > > + priv->pll5_params.dsi_div_b = 2;
> > > +
> > > + priv->pll5_params.frequency =
> > > + EXTAL_FREQ_IN_MEGA_HZ * MEGA / priv-
> > >pll5_params.pl5_refdiv *
> > > + ((((priv->pll5_params.pl5_intin << 24) + priv-
> > >pll5_params.pl5_fracin)) >> 24) /
> > > + (priv->pll5_params.pl5_postdiv1 *
> > > + priv->pll5_params.pl5_postdiv2);
> > > +
> > > + if (priv->pll5_params.clksrc)
> > > + priv->pll5_params.frequency /= 2;
> > > +
> > > + *parent_rate = priv->pll5_params.frequency;
> > > +
> > > + return dsi_div->rate;
> > > +}
> > > +
> > > +static int rzg2l_cpg_dsi_div_set_rate(struct clk_hw *hw,
> > > + unsigned long rate,
> > > + unsigned long parent_rate) {
> > > + struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
> > > + struct rzg2l_cpg_priv *priv = dsi_div->priv;
> > > +
> >
> > You should update priv->pll5_params here, instead of in your
> > .round_rate() callback.
>
> I need to find parent_rate based on video clock during {determine,round rate}
There is no guarantee that .set_rate() is called right after
.determine_rate() with the exact same parameters, or that it is called
at all. Modifying priv->pll5_params prematurely may affect the other
clocks in hard to debug ways. So please modify priv->pll5_params
only when actually setting the clock rate.
> I have added there to avoid duplication.
You can use a helper that takes a pointer to a struct rzg2l_pll5_param,
calculates the values, and fills them in.
.{determine,round rate}() would call it with a pointer to a local variable.
.set_rate() would call it with a pointer to &priv->pll5_params.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 18+ messages in thread
* RE: [PATCH 3/9] clk: renesas: rzg2l: Add DSI divider clk support
2022-04-22 15:10 ` Geert Uytterhoeven
@ 2022-04-26 17:04 ` Biju Das
0 siblings, 0 replies; 18+ messages in thread
From: Biju Das @ 2022-04-26 17:04 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 3/9] clk: renesas: rzg2l: Add DSI divider clk support
>
> Hi Biju,
>
> On Fri, Apr 22, 2022 at 1:15 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > > Subject: Re: [PATCH 3/9] clk: renesas: rzg2l: Add DSI divider clk
> > > support On Fri, Mar 18, 2022 at 6:51 PM Biju Das
> > > <biju.das.jz@bp.renesas.com>
> > > wrote:
> > > > M3 clock is sourced from DSI Divider (DSIDIVA * DSIDIVB)
> > > >
> > > > This patch add support for DSI divider clk by combaining DSIDIVA
> > > > and DSIDIVB .
> > > >
> > > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> > > > --- a/drivers/clk/renesas/rzg2l-cpg.c
> > > > +++ b/drivers/clk/renesas/rzg2l-cpg.c
> > > > +static long rzg2l_cpg_dsi_div_round_rate(struct clk_hw *hw,
> > > > + unsigned long rate,
> > > > + unsigned long
> > > > +*parent_rate) {
> > > > + struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
> > > > + struct rzg2l_cpg_priv *priv = dsi_div->priv;
> > > > +
> > > > + dsi_div->rate = rate;
> > > > +
> > > > + priv->pll5_params.pl5_intin = rate / MEGA;
> > >
> > > .round_rate() (and .determine_rate()) is used to check if a rate is
> > > supported, without actually changing the clock rate. Hence this
> > > should not operate on priv->pll5_params, but on a local variable.
> > >
> > > > + priv->pll5_params.pl5_fracin = ((rate % MEGA) << 24) / MEGA;
> > > > + priv->pll5_params.pl5_refdiv = 2;
> > > > + priv->pll5_params.pl5_postdiv1 = 1;
> > > > + priv->pll5_params.pl5_postdiv2 = 1;
> > > > + priv->pll5_params.clksrc = 1;
> > > > + priv->pll5_params.dsi_div_a = 1;
> > > > + priv->pll5_params.dsi_div_b = 2;
> > > > +
> > > > + priv->pll5_params.frequency =
> > > > + EXTAL_FREQ_IN_MEGA_HZ * MEGA / priv-
> > > >pll5_params.pl5_refdiv *
> > > > + ((((priv->pll5_params.pl5_intin << 24) + priv-
> > > >pll5_params.pl5_fracin)) >> 24) /
> > > > + (priv->pll5_params.pl5_postdiv1 *
> > > > + priv->pll5_params.pl5_postdiv2);
> > > > +
> > > > + if (priv->pll5_params.clksrc)
> > > > + priv->pll5_params.frequency /= 2;
> > > > +
> > > > + *parent_rate = priv->pll5_params.frequency;
> > > > +
> > > > + return dsi_div->rate;
> > > > +}
> > > > +
> > > > +static int rzg2l_cpg_dsi_div_set_rate(struct clk_hw *hw,
> > > > + unsigned long rate,
> > > > + unsigned long parent_rate) {
> > > > + struct dsi_div_hw_data *dsi_div = to_dsi_div_hw_data(hw);
> > > > + struct rzg2l_cpg_priv *priv = dsi_div->priv;
> > > > +
> > >
> > > You should update priv->pll5_params here, instead of in your
> > > .round_rate() callback.
> >
> > I need to find parent_rate based on video clock during
> > {determine,round rate}
>
> There is no guarantee that .set_rate() is called right after
> .determine_rate() with the exact same parameters, or that it is called at
> all. Modifying priv->pll5_params prematurely may affect the other clocks
> in hard to debug ways. So please modify priv->pll5_params only when
> actually setting the clock rate.
OK will do this change in next version.
>
> > I have added there to avoid duplication.
>
> You can use a helper that takes a pointer to a struct rzg2l_pll5_param,
> calculates the values, and fills them in.
> .{determine,round rate}() would call it with a pointer to a local
> variable.
> .set_rate() would call it with a pointer to &priv->pll5_params.
OK. Will send these changes in next version
Cheers,
Biju
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2022-04-26 17:04 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-18 17:51 [PATCH 0/9] Add RZ/G2L Display clock support Biju Das
2022-03-18 17:51 ` [PATCH 1/9] clk: renesas: rzg2l: Add FOUTPOSTDIV clk support Biju Das
2022-04-21 7:44 ` Geert Uytterhoeven
2022-04-22 11:04 ` Biju Das
2022-03-18 17:51 ` [PATCH 2/9] clk: renesas: rzg2l: Add PLL5_4 clk mux support Biju Das
2022-04-21 7:47 ` Geert Uytterhoeven
2022-04-22 11:11 ` Biju Das
2022-03-18 17:51 ` [PATCH 3/9] clk: renesas: rzg2l: Add DSI divider clk support Biju Das
2022-04-21 8:02 ` Geert Uytterhoeven
2022-04-22 11:15 ` Biju Das
2022-04-22 15:10 ` Geert Uytterhoeven
2022-04-26 17:04 ` Biju Das
2022-03-18 17:51 ` [PATCH 4/9] clk: renesas: r9a07g044: Add M1 clock support Biju Das
2022-03-18 17:51 ` [PATCH 5/9] clk: renesas: r9a07g044: Add {M2, M2_DIV2} Clocks support Biju Das
2022-03-18 17:51 ` [PATCH 6/9] clk: renesas: r9a07g044: Add M3 Clock support Biju Das
2022-03-18 17:51 ` [PATCH 7/9] clk: renesas: r9a07g044: Add M4 " Biju Das
2022-03-18 17:51 ` [PATCH 8/9] clk: renesas: r9a07g044: Add LCDC clock and reset entries Biju Das
2022-03-18 17:51 ` [PATCH 9/9] clk: renesas: r9a07g044: Add DSI " Biju Das
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