From: Ramalingam C <ramalingam.c@intel.com> To: intel-gfx <intel-gfx@lists.freedesktop.org>, dri-devel <dri-devel@lists.freedesktop.org> Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>, "Hellstrom Thomas" <thomas.hellstrom@intel.com>, "Matthew Auld" <matthew.auld@intel.com>, "Christian Koenig" <christian.koenig@amd.com> Subject: [PATCH v4 7/8] drm/i915/gem: Add extra pages in ttm_tt for ccs data Date: Sun, 20 Mar 2022 02:12:28 +0530 [thread overview] Message-ID: <20220319204229.9846-8-ramalingam.c@intel.com> (raw) In-Reply-To: <20220319204229.9846-1-ramalingam.c@intel.com> On Xe-HP and later devices, dedicated compression control state (CCS) stored in local memory is used for each surface, to support the 3D and media compression formats. The memory required for the CCS of the entire local memory is 1/256 of the local memory size. So before the kernel boot, the required memory is reserved for the CCS data and a secure register will be programmed with the CCS base address So when an object is allocated in local memory, dont need to explicitly allocate the space for ccs data. But when the obj is evicted into the smem, to hold the compression related data along with the obj extra space is needed in smem. i.e obj_size + (obj_size/256). Hence when a smem pages are allocated for an obj with lmem placement possibility we create with the extra pages required for the ccs data for the obj size. v2: Used imperative wording [Thomas] v3: Inflate the pages only when obj's placement is lmem only Signed-off-by: Ramalingam C <ramalingam.c@intel.com> cc: Christian Koenig <christian.koenig@amd.com> cc: Hellstrom Thomas <thomas.hellstrom@intel.com> Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 29 ++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c index 3b9f99c765c4..0305a150b9d4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c @@ -20,6 +20,7 @@ #include "gem/i915_gem_ttm.h" #include "gem/i915_gem_ttm_move.h" #include "gem/i915_gem_ttm_pm.h" +#include "gt/intel_gpu_commands.h" #define I915_TTM_PRIO_PURGE 0 #define I915_TTM_PRIO_NO_PAGES 1 @@ -262,12 +263,33 @@ static const struct i915_refct_sgt_ops tt_rsgt_ops = { .release = i915_ttm_tt_release }; +static inline bool +i915_gem_object_needs_ccs_pages(struct drm_i915_gem_object *obj) +{ + bool lmem_placement = false; + int i; + + for (i = 0; i < obj->mm.n_placements; i++) { + /* Compression is not allowed for the objects with smem placement */ + if (obj->mm.placements[i]->type == INTEL_MEMORY_SYSTEM) + return false; + if (!lmem_placement && + obj->mm.placements[i]->type == INTEL_MEMORY_LOCAL) + lmem_placement = true; + } + + return lmem_placement; +} + static struct ttm_tt *i915_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags) { + struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915), + bdev); struct ttm_resource_manager *man = ttm_manager_type(bo->bdev, bo->resource->mem_type); struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo); + unsigned long ccs_pages = 0; enum ttm_caching caching; struct i915_ttm_tt *i915_tt; int ret; @@ -290,7 +312,12 @@ static struct ttm_tt *i915_ttm_tt_create(struct ttm_buffer_object *bo, i915_tt->is_shmem = true; } - ret = ttm_tt_init(&i915_tt->ttm, bo, page_flags, caching, 0); + if (HAS_FLAT_CCS(i915) && i915_gem_object_needs_ccs_pages(obj)) + ccs_pages = DIV_ROUND_UP(DIV_ROUND_UP(bo->base.size, + NUM_BYTES_PER_CCS_BYTE), + PAGE_SIZE); + + ret = ttm_tt_init(&i915_tt->ttm, bo, page_flags, caching, ccs_pages); if (ret) goto err_free; -- 2.20.1
WARNING: multiple messages have this Message-ID (diff)
From: Ramalingam C <ramalingam.c@intel.com> To: intel-gfx <intel-gfx@lists.freedesktop.org>, dri-devel <dri-devel@lists.freedesktop.org> Cc: "Thomas Hellström" <thomas.hellstrom@linux.intel.com>, "Hellstrom Thomas" <thomas.hellstrom@intel.com>, "Matthew Auld" <matthew.auld@intel.com>, "Christian Koenig" <christian.koenig@amd.com> Subject: [Intel-gfx] [PATCH v4 7/8] drm/i915/gem: Add extra pages in ttm_tt for ccs data Date: Sun, 20 Mar 2022 02:12:28 +0530 [thread overview] Message-ID: <20220319204229.9846-8-ramalingam.c@intel.com> (raw) In-Reply-To: <20220319204229.9846-1-ramalingam.c@intel.com> On Xe-HP and later devices, dedicated compression control state (CCS) stored in local memory is used for each surface, to support the 3D and media compression formats. The memory required for the CCS of the entire local memory is 1/256 of the local memory size. So before the kernel boot, the required memory is reserved for the CCS data and a secure register will be programmed with the CCS base address So when an object is allocated in local memory, dont need to explicitly allocate the space for ccs data. But when the obj is evicted into the smem, to hold the compression related data along with the obj extra space is needed in smem. i.e obj_size + (obj_size/256). Hence when a smem pages are allocated for an obj with lmem placement possibility we create with the extra pages required for the ccs data for the obj size. v2: Used imperative wording [Thomas] v3: Inflate the pages only when obj's placement is lmem only Signed-off-by: Ramalingam C <ramalingam.c@intel.com> cc: Christian Koenig <christian.koenig@amd.com> cc: Hellstrom Thomas <thomas.hellstrom@intel.com> Reviewed-by: Thomas Hellström <thomas.hellstrom@linux.intel.com> --- drivers/gpu/drm/i915/gem/i915_gem_ttm.c | 29 ++++++++++++++++++++++++- 1 file changed, 28 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c index 3b9f99c765c4..0305a150b9d4 100644 --- a/drivers/gpu/drm/i915/gem/i915_gem_ttm.c +++ b/drivers/gpu/drm/i915/gem/i915_gem_ttm.c @@ -20,6 +20,7 @@ #include "gem/i915_gem_ttm.h" #include "gem/i915_gem_ttm_move.h" #include "gem/i915_gem_ttm_pm.h" +#include "gt/intel_gpu_commands.h" #define I915_TTM_PRIO_PURGE 0 #define I915_TTM_PRIO_NO_PAGES 1 @@ -262,12 +263,33 @@ static const struct i915_refct_sgt_ops tt_rsgt_ops = { .release = i915_ttm_tt_release }; +static inline bool +i915_gem_object_needs_ccs_pages(struct drm_i915_gem_object *obj) +{ + bool lmem_placement = false; + int i; + + for (i = 0; i < obj->mm.n_placements; i++) { + /* Compression is not allowed for the objects with smem placement */ + if (obj->mm.placements[i]->type == INTEL_MEMORY_SYSTEM) + return false; + if (!lmem_placement && + obj->mm.placements[i]->type == INTEL_MEMORY_LOCAL) + lmem_placement = true; + } + + return lmem_placement; +} + static struct ttm_tt *i915_ttm_tt_create(struct ttm_buffer_object *bo, uint32_t page_flags) { + struct drm_i915_private *i915 = container_of(bo->bdev, typeof(*i915), + bdev); struct ttm_resource_manager *man = ttm_manager_type(bo->bdev, bo->resource->mem_type); struct drm_i915_gem_object *obj = i915_ttm_to_gem(bo); + unsigned long ccs_pages = 0; enum ttm_caching caching; struct i915_ttm_tt *i915_tt; int ret; @@ -290,7 +312,12 @@ static struct ttm_tt *i915_ttm_tt_create(struct ttm_buffer_object *bo, i915_tt->is_shmem = true; } - ret = ttm_tt_init(&i915_tt->ttm, bo, page_flags, caching, 0); + if (HAS_FLAT_CCS(i915) && i915_gem_object_needs_ccs_pages(obj)) + ccs_pages = DIV_ROUND_UP(DIV_ROUND_UP(bo->base.size, + NUM_BYTES_PER_CCS_BYTE), + PAGE_SIZE); + + ret = ttm_tt_init(&i915_tt->ttm, bo, page_flags, caching, ccs_pages); if (ret) goto err_free; -- 2.20.1
next prev parent reply other threads:[~2022-03-19 20:42 UTC|newest] Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-03-19 20:42 [PATCH v4 0/8] drm/i915/ttm: Evict and restore of compressed object Ramalingam C 2022-03-19 20:42 ` [Intel-gfx] " Ramalingam C 2022-03-19 20:42 ` [PATCH v4 1/8] drm/i915/gt: Use XY_FASR_COLOR_BLT to clear obj on graphics ver 12+ Ramalingam C 2022-03-19 20:42 ` [Intel-gfx] " Ramalingam C 2022-03-21 8:49 ` Hellstrom, Thomas 2022-03-21 8:49 ` [Intel-gfx] " Hellstrom, Thomas 2022-03-21 23:07 ` Ramalingam C 2022-03-21 23:07 ` [Intel-gfx] " Ramalingam C 2022-03-19 20:42 ` [PATCH v4 2/8] drm/i915/gt: Clear compress metadata for Flat-ccs objects Ramalingam C 2022-03-19 20:42 ` [Intel-gfx] " Ramalingam C 2022-03-19 20:42 ` [PATCH v4 3/8] drm/i915/selftest_migrate: Consider the possible roundup of size Ramalingam C 2022-03-19 20:42 ` [Intel-gfx] " Ramalingam C 2022-03-19 20:42 ` [PATCH v4 4/8] drm/i915/selftest_migrate: Check CCS meta data clear Ramalingam C 2022-03-19 20:42 ` [Intel-gfx] " Ramalingam C 2022-03-20 1:39 ` kernel test robot 2022-03-21 10:39 ` Hellstrom, Thomas 2022-03-21 10:39 ` Hellstrom, Thomas 2022-03-21 23:05 ` Ramalingam C 2022-03-21 23:05 ` [Intel-gfx] " Ramalingam C 2022-03-19 20:42 ` [PATCH v4 5/8] drm/i915/gt: Optimize the migration loop Ramalingam C 2022-03-19 20:42 ` [Intel-gfx] " Ramalingam C 2022-03-19 20:42 ` [PATCH v4 6/8] drm/ttm: Add a parameter to add extra pages into ttm_tt Ramalingam C 2022-03-19 20:42 ` [Intel-gfx] " Ramalingam C 2022-03-21 10:11 ` Das, Nirmoy 2022-03-21 23:06 ` Ramalingam C 2022-03-19 20:42 ` Ramalingam C [this message] 2022-03-19 20:42 ` [Intel-gfx] [PATCH v4 7/8] drm/i915/gem: Add extra pages in ttm_tt for ccs data Ramalingam C 2022-03-19 20:42 ` [PATCH v4 8/8] drm/i915/migrate: Evict and restore the flatccs capable lmem obj Ramalingam C 2022-03-19 20:42 ` [Intel-gfx] " Ramalingam C 2022-03-19 20:50 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915/ttm: Evict and restore of compressed object (rev2) Patchwork 2022-03-19 20:52 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-03-19 21:26 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2022-03-19 21:26 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
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