* [PATCH] drm/amdgpu/vcn: Correct the register setting for vcn1
@ 2022-03-21 8:26 Emily Deng
2022-03-21 12:48 ` James Zhu
2022-03-21 13:02 ` Paul Menzel
0 siblings, 2 replies; 3+ messages in thread
From: Emily Deng @ 2022-03-21 8:26 UTC (permalink / raw)
To: amd-gfx; +Cc: Emily Deng
Correct the code error for setting register UVD_GFX10_ADDR_CONFIG.
Need to use inst_idx, or it only will set VCN0.
Signed-off-by: Emily Deng <Emily.Deng@amd.com>
---
drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
index c87263ed20ec..b16c56aa2d22 100644
--- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
@@ -575,8 +575,8 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
/* VCN global tiling registers */
- WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
- UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
+ WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
+ UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
}
static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
--
2.34.1
^ permalink raw reply related [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/amdgpu/vcn: Correct the register setting for vcn1
2022-03-21 8:26 [PATCH] drm/amdgpu/vcn: Correct the register setting for vcn1 Emily Deng
@ 2022-03-21 12:48 ` James Zhu
2022-03-21 13:02 ` Paul Menzel
1 sibling, 0 replies; 3+ messages in thread
From: James Zhu @ 2022-03-21 12:48 UTC (permalink / raw)
To: amd-gfx
[-- Attachment #1: Type: text/plain, Size: 1217 bytes --]
ThispatchisReviewed-by:JamesZhu<James.Zhu@amd.com>
On 2022-03-21 4:26 a.m., Emily Deng wrote:
> Correct the code error for setting register UVD_GFX10_ADDR_CONFIG.
> Need to use inst_idx, or it only will set VCN0.
>
> Signed-off-by: Emily Deng<Emily.Deng@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index c87263ed20ec..b16c56aa2d22 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -575,8 +575,8 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
> AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
>
> /* VCN global tiling registers */
> - WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
> - UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
> + WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
> + UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
> }
>
> static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
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^ permalink raw reply [flat|nested] 3+ messages in thread
* Re: [PATCH] drm/amdgpu/vcn: Correct the register setting for vcn1
2022-03-21 8:26 [PATCH] drm/amdgpu/vcn: Correct the register setting for vcn1 Emily Deng
2022-03-21 12:48 ` James Zhu
@ 2022-03-21 13:02 ` Paul Menzel
1 sibling, 0 replies; 3+ messages in thread
From: Paul Menzel @ 2022-03-21 13:02 UTC (permalink / raw)
To: Emily Deng; +Cc: amd-gfx
Dear Emily,
Am 21.03.22 um 09:26 schrieb Emily Deng:
> Correct the code error for setting register UVD_GFX10_ADDR_CONFIG.
> Need to use inst_idx, or it only will set VCN0.
Please add a Fixes tag.
> Signed-off-by: Emily Deng <Emily.Deng@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c | 4 ++--
> 1 file changed, 2 insertions(+), 2 deletions(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> index c87263ed20ec..b16c56aa2d22 100644
> --- a/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/vcn_v3_0.c
> @@ -575,8 +575,8 @@ static void vcn_v3_0_mc_resume_dpg_mode(struct amdgpu_device *adev, int inst_idx
> AMDGPU_GPU_PAGE_ALIGN(sizeof(struct amdgpu_fw_shared)), 0, indirect);
>
> /* VCN global tiling registers */
> - WREG32_SOC15_DPG_MODE(0, SOC15_DPG_MODE_OFFSET(
> - UVD, 0, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
> + WREG32_SOC15_DPG_MODE(inst_idx, SOC15_DPG_MODE_OFFSET(
> + UVD, inst_idx, mmUVD_GFX10_ADDR_CONFIG), adev->gfx.config.gb_addr_config, 0, indirect);
> }
>
> static void vcn_v3_0_disable_static_power_gating(struct amdgpu_device *adev, int inst)
Kind regards,
Paul
^ permalink raw reply [flat|nested] 3+ messages in thread
end of thread, other threads:[~2022-03-21 13:02 UTC | newest]
Thread overview: 3+ messages (download: mbox.gz / follow: Atom feed)
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2022-03-21 8:26 [PATCH] drm/amdgpu/vcn: Correct the register setting for vcn1 Emily Deng
2022-03-21 12:48 ` James Zhu
2022-03-21 13:02 ` Paul Menzel
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