* [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-03-21 9:10 ` Stanislav Lisovskiy 0 siblings, 0 replies; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-03-21 9:10 UTC (permalink / raw) To: intel-gfx; +Cc: Stanislav.Lisovskiy, jani.saarinen, dri-devel Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/dp/drm_dp.c | 25 ++++ drivers/gpu/drm/i915/display/intel_dp.c | 75 +++++----- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 143 ++++++++++++++++++++ include/drm/dp/drm_dp_helper.h | 11 +- 5 files changed, 226 insertions(+), 45 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-03-21 9:10 ` Stanislav Lisovskiy 0 siblings, 0 replies; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-03-21 9:10 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/dp/drm_dp.c | 25 ++++ drivers/gpu/drm/i915/display/intel_dp.c | 75 +++++----- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 143 ++++++++++++++++++++ include/drm/dp/drm_dp_helper.h | 11 +- 5 files changed, 226 insertions(+), 45 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] drm: Add missing DP DSC extended capability definitions. 2022-03-21 9:10 ` [Intel-gfx] " Stanislav Lisovskiy @ 2022-03-21 9:10 ` Stanislav Lisovskiy -1 siblings, 0 replies; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-03-21 9:10 UTC (permalink / raw) To: intel-gfx; +Cc: Stanislav.Lisovskiy, jani.saarinen, dri-devel Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/dp/drm_dp.c | 25 +++++++++++++++++++++++++ include/drm/dp/drm_dp_helper.h | 11 ++++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c index 703972ae14c6..45815745ba7b 100644 --- a/drivers/gpu/drm/dp/drm_dp.c +++ b/drivers/gpu/drm/dp/drm_dp.c @@ -2312,6 +2312,31 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], } EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); +/** + * drm_dp_dsc_sink_bpp_increment_div - Get the bits per pixel precision + * which DP DSC sink device supports. + */ +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; + + switch (bpp_increment_dpcd) { + case DP_DSC_BITS_PER_PIXEL_1_16: + return 16; + case DP_DSC_BITS_PER_PIXEL_1_8: + return 8; + case DP_DSC_BITS_PER_PIXEL_1_4: + return 4; + case DP_DSC_BITS_PER_PIXEL_1_2: + return 2; + case DP_DSC_BITS_PER_PIXEL_1_1: + return 1; + } + + return 0; +} + + /** * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits * @dsc_dpcd: DSC capabilities from DPCD diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h index 51e02cf75277..e4c9f4438ccb 100644 --- a/include/drm/dp/drm_dp_helper.h +++ b/include/drm/dp/drm_dp_helper.h @@ -246,6 +246,9 @@ struct drm_panel; #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -284,12 +287,15 @@ struct drm_panel; #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -351,11 +357,13 @@ struct drm_panel; # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 @@ -1825,6 +1833,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], u8 dsc_bpc[3]); +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); static inline bool drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm: Add missing DP DSC extended capability definitions. @ 2022-03-21 9:10 ` Stanislav Lisovskiy 0 siblings, 0 replies; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-03-21 9:10 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/dp/drm_dp.c | 25 +++++++++++++++++++++++++ include/drm/dp/drm_dp_helper.h | 11 ++++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c index 703972ae14c6..45815745ba7b 100644 --- a/drivers/gpu/drm/dp/drm_dp.c +++ b/drivers/gpu/drm/dp/drm_dp.c @@ -2312,6 +2312,31 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], } EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); +/** + * drm_dp_dsc_sink_bpp_increment_div - Get the bits per pixel precision + * which DP DSC sink device supports. + */ +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; + + switch (bpp_increment_dpcd) { + case DP_DSC_BITS_PER_PIXEL_1_16: + return 16; + case DP_DSC_BITS_PER_PIXEL_1_8: + return 8; + case DP_DSC_BITS_PER_PIXEL_1_4: + return 4; + case DP_DSC_BITS_PER_PIXEL_1_2: + return 2; + case DP_DSC_BITS_PER_PIXEL_1_1: + return 1; + } + + return 0; +} + + /** * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits * @dsc_dpcd: DSC capabilities from DPCD diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h index 51e02cf75277..e4c9f4438ccb 100644 --- a/include/drm/dp/drm_dp_helper.h +++ b/include/drm/dp/drm_dp_helper.h @@ -246,6 +246,9 @@ struct drm_panel; #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -284,12 +287,15 @@ struct drm_panel; #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -351,11 +357,13 @@ struct drm_panel; # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 @@ -1825,6 +1833,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], u8 dsc_bpc[3]); +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); static inline bool drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/2] drm/i915: Add DSC support to MST path 2022-03-21 9:10 ` [Intel-gfx] " Stanislav Lisovskiy @ 2022-03-21 9:10 ` Stanislav Lisovskiy -1 siblings, 0 replies; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-03-21 9:10 UTC (permalink / raw) To: intel-gfx; +Cc: Stanislav.Lisovskiy, jani.saarinen, dri-devel Whenever we are not able to get enough timeslots for required PBN, let's try to allocate those using DSC, just same way as we do for SST. v2: Add DSC checks to intel_dp_mst_mode_valid_ctx, similar to ones we have in intel_dp_mode_valid(Manasi Navare) v3: Removed redundant edp condition logic from MST DSC handling(Manasi Navare) v4: - Fixed forgotten force_dsc_en condition which was always enabled for testing purposes(Manasi Navare) - Properly process ret == EDEADLK, thus fixing the regression caused by WARN triggered with modeset_lock. v5: - Removed redundant check(Imre Deak) v6: Removed intel_dp_mst_dsc_compute_config and refactored intel_dp_dsc_compute_config to support timeslots as a parameter(Ville Syrjälä) Acked-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 75 +++++----- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 143 ++++++++++++++++++++ 3 files changed, 191 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9e19165fd175..b8e1561b5eca 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -115,7 +115,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) } static void intel_dp_unset_edid(struct intel_dp *intel_dp); -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); /* Is link rate UHBR and thus 128b/132b? */ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) @@ -667,11 +666,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915) return 6144 * 8; } -static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, - u32 link_clock, u32 lane_count, - u32 mode_clock, u32 mode_hdisplay, - bool bigjoiner, - u32 pipe_bpp) +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + u32 pipe_bpp, + u32 timeslots) { u32 bits_per_pixel, max_bpp_small_joiner_ram; int i; @@ -683,7 +683,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, * for MST -> TimeSlotsPerMTP has to be calculated */ bits_per_pixel = (link_clock * lane_count * 8) / - intel_dp_mode_to_fec_clock(mode_clock); + (intel_dp_mode_to_fec_clock(mode_clock) * timeslots); drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel); /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ @@ -737,9 +737,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, return bits_per_pixel << 4; } -static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, - int mode_clock, int mode_hdisplay, - bool bigjoiner) +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, + int mode_clock, int mode_hdisplay, + bool bigjoiner) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); u8 min_slice_count, i; @@ -902,8 +902,8 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, return MODE_OK; } -static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, - int hdisplay, int clock) +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, + int hdisplay, int clock) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -990,7 +990,7 @@ intel_dp_mode_valid(struct drm_connector *connector, target_clock, mode->hdisplay, bigjoiner, - pipe_bpp) >> 4; + pipe_bpp, 1) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -1285,7 +1285,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, return -EINVAL; } -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int i, num_bpc; @@ -1375,10 +1375,11 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, return drm_dsc_compute_rc_parameters(vdsc_cfg); } -static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state, - struct link_config_limits *limits) +int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int timeslots) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); @@ -1429,7 +1430,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay, pipe_config->bigjoiner_pipes, - pipe_bpp); + pipe_bpp, + timeslots); dsc_dp_slice_count = intel_dp_dsc_get_slice_count(intel_dp, adjusted_mode->crtc_clock, @@ -1441,41 +1443,26 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return -EINVAL; } pipe_config->dsc.compressed_bpp = min_t(u16, - dsc_max_output_bpp >> 4, - pipe_config->pipe_bpp); + dsc_max_output_bpp >> 4, + pipe_config->pipe_bpp); pipe_config->dsc.slice_count = dsc_dp_slice_count; + drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n", + pipe_config->dsc.compressed_bpp, + pipe_config->dsc.slice_count); } - - /* As of today we support DSC for only RGB */ - if (intel_dp->force_dsc_bpp) { - if (intel_dp->force_dsc_bpp >= 8 && - intel_dp->force_dsc_bpp < pipe_bpp) { - drm_dbg_kms(&dev_priv->drm, - "DSC BPP forced to %d", - intel_dp->force_dsc_bpp); - pipe_config->dsc.compressed_bpp = - intel_dp->force_dsc_bpp; - } else { - drm_dbg_kms(&dev_priv->drm, - "Invalid DSC BPP %d", - intel_dp->force_dsc_bpp); - } - } - /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate * is greater than the maximum Cdclock and if slice count is even * then we need to use 2 VDSC instances. */ - if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq || - pipe_config->bigjoiner_pipes) { - if (pipe_config->dsc.slice_count < 2) { + if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { + if (pipe_config->dsc.slice_count > 1) { + pipe_config->dsc.dsc_split = true; + } else { drm_dbg_kms(&dev_priv->drm, "Cannot split stream to use 2 VDSC instances\n"); return -EINVAL; } - - pipe_config->dsc.dsc_split = true; } ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); @@ -1558,7 +1545,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, if (ret || intel_dp->force_dsc_en || (DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes)) { ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, - conn_state, &limits); + conn_state, &limits, 1); if (ret < 0) return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index d457e17bdc57..4c0ad3158ee7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -55,6 +55,11 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder); int intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); +int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int timeslots); bool intel_dp_is_edp(struct intel_dp *intel_dp); bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); @@ -94,6 +99,18 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + u32 pipe_bpp, + u32 timeslots); +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, + int mode_clock, int mode_hdisplay, + bool bigjoiner); +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, + int hdisplay, int clock); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index e30e698aa684..778ca6283b8e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -99,6 +99,82 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, return 0; } +static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + struct link_config_limits *limits) +{ + struct drm_atomic_state *state = crtc_state->uapi.state; + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); + struct intel_dp *intel_dp = &intel_mst->primary->dp; + struct intel_connector *connector = + to_intel_connector(conn_state->connector); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + bool constant_n = drm_dp_has_quirk(&intel_dp->desc, + DP_DPCD_QUIRK_CONSTANT_N); + int bpp, slots = -EINVAL; + int i, num_bpc; + u8 dsc_bpc[3] = {0}; + int min_bpp, max_bpp; + u8 dsc_max_bpc; + + crtc_state->lane_count = limits->max_lane_count; + crtc_state->port_clock = limits->max_rate; + + /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ + if (DISPLAY_VER(i915) >= 12) + dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc); + else + dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc); + + max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp); + min_bpp = limits->min_bpp; + + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, + dsc_bpc); + for (i = 0; i < num_bpc; i++) { + if (max_bpp >= dsc_bpc[i] * 3) + if (min_bpp > dsc_bpc[i] * 3) + min_bpp = dsc_bpc[i] * 3; + } + drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n", + min_bpp, max_bpp); + for (bpp = max_bpp; bpp >= min_bpp; bpp -= 2 * 3) { + crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, + bpp << 4, + true); + + slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, + connector->port, + crtc_state->pbn, 0); + + drm_dbg_kms(&i915->drm, "Trying bpp %d got %d pbn %d slots\n", + bpp, crtc_state->pbn, slots); + + if (slots == -EDEADLK) + return slots; + if (slots >= 0) + break; + } + + if (slots < 0) { + drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n", + slots); + return slots; + } + + intel_link_compute_m_n(crtc_state->pipe_bpp, + crtc_state->lane_count, + adjusted_mode->crtc_clock, + crtc_state->port_clock, + &crtc_state->dp_m_n, + constant_n, crtc_state->fec_enable); + crtc_state->dp_m_n.tu = slots; + + return 0; +} static int intel_dp_mst_update_slots(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -175,6 +251,27 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, ret = intel_dp_mst_compute_link_config(encoder, pipe_config, conn_state, &limits); + + if (ret == -EDEADLK) + return ret; + + /* enable compression if the mode doesn't fit available BW */ + drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); + if (ret || intel_dp->force_dsc_en) { + /* + * Try to get at least some timeslots and then see, if + * we can fit there with DSC. + */ + ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config, + conn_state, &limits); + if (ret < 0) + return ret; + + ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, + conn_state, &limits, + pipe_config->dp_m_n.tu); + } + if (ret) return ret; @@ -715,6 +812,10 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; int max_rate, mode_rate, max_lanes, max_link_clock; int ret; + bool dsc = false, bigjoiner = false; + u16 dsc_max_output_bpp = 0; + u8 dsc_slice_count = 0; + int target_clock = mode->clock; if (drm_connector_is_unregistered(connector)) { *status = MODE_ERROR; @@ -752,6 +853,48 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, return 0; } + if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) { + bigjoiner = true; + max_dotclk *= 2; + } + + if (DISPLAY_VER(dev_priv) >= 10 && + drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { + /* + * TBD pass the connector BPC, + * for now U8_MAX so that max BPC on that platform would be picked + */ + int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + + if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { + dsc_max_output_bpp = + intel_dp_dsc_get_output_bpp(dev_priv, + max_link_clock, + max_lanes, + target_clock, + mode->hdisplay, + bigjoiner, + pipe_bpp, 1) >> 4; + dsc_slice_count = + intel_dp_dsc_get_slice_count(intel_dp, + target_clock, + mode->hdisplay, + bigjoiner); + } + + dsc = dsc_max_output_bpp && dsc_slice_count; + } + + /* + * Big joiner configuration needs DSC for TGL which is not true for + * XE_LPD where uncompressed joiner is supported. + */ + if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) + return MODE_CLOCK_HIGH; + + if (mode_rate > max_rate && !dsc) + return MODE_CLOCK_HIGH; + *status = intel_mode_valid_max_plane_size(dev_priv, mode, false); return 0; } -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915: Add DSC support to MST path @ 2022-03-21 9:10 ` Stanislav Lisovskiy 0 siblings, 0 replies; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-03-21 9:10 UTC (permalink / raw) To: intel-gfx; +Cc: dri-devel Whenever we are not able to get enough timeslots for required PBN, let's try to allocate those using DSC, just same way as we do for SST. v2: Add DSC checks to intel_dp_mst_mode_valid_ctx, similar to ones we have in intel_dp_mode_valid(Manasi Navare) v3: Removed redundant edp condition logic from MST DSC handling(Manasi Navare) v4: - Fixed forgotten force_dsc_en condition which was always enabled for testing purposes(Manasi Navare) - Properly process ret == EDEADLK, thus fixing the regression caused by WARN triggered with modeset_lock. v5: - Removed redundant check(Imre Deak) v6: Removed intel_dp_mst_dsc_compute_config and refactored intel_dp_dsc_compute_config to support timeslots as a parameter(Ville Syrjälä) Acked-by: Imre Deak <imre.deak@intel.com> Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/display/intel_dp.c | 75 +++++----- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 143 ++++++++++++++++++++ 3 files changed, 191 insertions(+), 44 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_dp.c b/drivers/gpu/drm/i915/display/intel_dp.c index 9e19165fd175..b8e1561b5eca 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.c +++ b/drivers/gpu/drm/i915/display/intel_dp.c @@ -115,7 +115,6 @@ bool intel_dp_is_edp(struct intel_dp *intel_dp) } static void intel_dp_unset_edid(struct intel_dp *intel_dp); -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); /* Is link rate UHBR and thus 128b/132b? */ bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state) @@ -667,11 +666,12 @@ small_joiner_ram_size_bits(struct drm_i915_private *i915) return 6144 * 8; } -static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, - u32 link_clock, u32 lane_count, - u32 mode_clock, u32 mode_hdisplay, - bool bigjoiner, - u32 pipe_bpp) +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + u32 pipe_bpp, + u32 timeslots) { u32 bits_per_pixel, max_bpp_small_joiner_ram; int i; @@ -683,7 +683,7 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, * for MST -> TimeSlotsPerMTP has to be calculated */ bits_per_pixel = (link_clock * lane_count * 8) / - intel_dp_mode_to_fec_clock(mode_clock); + (intel_dp_mode_to_fec_clock(mode_clock) * timeslots); drm_dbg_kms(&i915->drm, "Max link bpp: %u\n", bits_per_pixel); /* Small Joiner Check: output bpp <= joiner RAM (bits) / Horiz. width */ @@ -737,9 +737,9 @@ static u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, return bits_per_pixel << 4; } -static u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, - int mode_clock, int mode_hdisplay, - bool bigjoiner) +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, + int mode_clock, int mode_hdisplay, + bool bigjoiner) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); u8 min_slice_count, i; @@ -902,8 +902,8 @@ intel_dp_mode_valid_downstream(struct intel_connector *connector, return MODE_OK; } -static bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, - int hdisplay, int clock) +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, + int hdisplay, int clock) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); @@ -990,7 +990,7 @@ intel_dp_mode_valid(struct drm_connector *connector, target_clock, mode->hdisplay, bigjoiner, - pipe_bpp) >> 4; + pipe_bpp, 1) >> 4; dsc_slice_count = intel_dp_dsc_get_slice_count(intel_dp, target_clock, @@ -1285,7 +1285,7 @@ intel_dp_compute_link_config_wide(struct intel_dp *intel_dp, return -EINVAL; } -static int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 max_req_bpc) { struct drm_i915_private *i915 = dp_to_i915(intel_dp); int i, num_bpc; @@ -1375,10 +1375,11 @@ static int intel_dp_dsc_compute_params(struct intel_encoder *encoder, return drm_dsc_compute_rc_parameters(vdsc_cfg); } -static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, - struct intel_crtc_state *pipe_config, - struct drm_connector_state *conn_state, - struct link_config_limits *limits) +int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int timeslots) { struct intel_digital_port *dig_port = dp_to_dig_port(intel_dp); struct drm_i915_private *dev_priv = to_i915(dig_port->base.base.dev); @@ -1429,7 +1430,8 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, adjusted_mode->crtc_clock, adjusted_mode->crtc_hdisplay, pipe_config->bigjoiner_pipes, - pipe_bpp); + pipe_bpp, + timeslots); dsc_dp_slice_count = intel_dp_dsc_get_slice_count(intel_dp, adjusted_mode->crtc_clock, @@ -1441,41 +1443,26 @@ static int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, return -EINVAL; } pipe_config->dsc.compressed_bpp = min_t(u16, - dsc_max_output_bpp >> 4, - pipe_config->pipe_bpp); + dsc_max_output_bpp >> 4, + pipe_config->pipe_bpp); pipe_config->dsc.slice_count = dsc_dp_slice_count; + drm_dbg_kms(&dev_priv->drm, "DSC: compressed bpp %d slice count %d\n", + pipe_config->dsc.compressed_bpp, + pipe_config->dsc.slice_count); } - - /* As of today we support DSC for only RGB */ - if (intel_dp->force_dsc_bpp) { - if (intel_dp->force_dsc_bpp >= 8 && - intel_dp->force_dsc_bpp < pipe_bpp) { - drm_dbg_kms(&dev_priv->drm, - "DSC BPP forced to %d", - intel_dp->force_dsc_bpp); - pipe_config->dsc.compressed_bpp = - intel_dp->force_dsc_bpp; - } else { - drm_dbg_kms(&dev_priv->drm, - "Invalid DSC BPP %d", - intel_dp->force_dsc_bpp); - } - } - /* * VDSC engine operates at 1 Pixel per clock, so if peak pixel rate * is greater than the maximum Cdclock and if slice count is even * then we need to use 2 VDSC instances. */ - if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq || - pipe_config->bigjoiner_pipes) { - if (pipe_config->dsc.slice_count < 2) { + if (adjusted_mode->crtc_clock > dev_priv->max_cdclk_freq) { + if (pipe_config->dsc.slice_count > 1) { + pipe_config->dsc.dsc_split = true; + } else { drm_dbg_kms(&dev_priv->drm, "Cannot split stream to use 2 VDSC instances\n"); return -EINVAL; } - - pipe_config->dsc.dsc_split = true; } ret = intel_dp_dsc_compute_params(&dig_port->base, pipe_config); @@ -1558,7 +1545,7 @@ intel_dp_compute_link_config(struct intel_encoder *encoder, if (ret || intel_dp->force_dsc_en || (DISPLAY_VER(i915) < 13 && pipe_config->bigjoiner_pipes)) { ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, - conn_state, &limits); + conn_state, &limits, 1); if (ret < 0) return ret; } diff --git a/drivers/gpu/drm/i915/display/intel_dp.h b/drivers/gpu/drm/i915/display/intel_dp.h index d457e17bdc57..4c0ad3158ee7 100644 --- a/drivers/gpu/drm/i915/display/intel_dp.h +++ b/drivers/gpu/drm/i915/display/intel_dp.h @@ -55,6 +55,11 @@ void intel_dp_encoder_flush_work(struct drm_encoder *encoder); int intel_dp_compute_config(struct intel_encoder *encoder, struct intel_crtc_state *pipe_config, struct drm_connector_state *conn_state); +int intel_dp_dsc_compute_config(struct intel_dp *intel_dp, + struct intel_crtc_state *pipe_config, + struct drm_connector_state *conn_state, + struct link_config_limits *limits, + int timeslots); bool intel_dp_is_edp(struct intel_dp *intel_dp); bool intel_dp_is_uhbr(const struct intel_crtc_state *crtc_state); bool intel_dp_is_port_edp(struct drm_i915_private *dev_priv, enum port port); @@ -94,6 +99,18 @@ void intel_read_dp_sdp(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, unsigned int type); bool intel_digital_port_connected(struct intel_encoder *encoder); +int intel_dp_dsc_compute_bpp(struct intel_dp *intel_dp, u8 dsc_max_bpc); +u16 intel_dp_dsc_get_output_bpp(struct drm_i915_private *i915, + u32 link_clock, u32 lane_count, + u32 mode_clock, u32 mode_hdisplay, + bool bigjoiner, + u32 pipe_bpp, + u32 timeslots); +u8 intel_dp_dsc_get_slice_count(struct intel_dp *intel_dp, + int mode_clock, int mode_hdisplay, + bool bigjoiner); +bool intel_dp_need_bigjoiner(struct intel_dp *intel_dp, + int hdisplay, int clock); static inline unsigned int intel_dp_unused_lane_mask(int lane_count) { diff --git a/drivers/gpu/drm/i915/display/intel_dp_mst.c b/drivers/gpu/drm/i915/display/intel_dp_mst.c index e30e698aa684..778ca6283b8e 100644 --- a/drivers/gpu/drm/i915/display/intel_dp_mst.c +++ b/drivers/gpu/drm/i915/display/intel_dp_mst.c @@ -99,6 +99,82 @@ static int intel_dp_mst_compute_link_config(struct intel_encoder *encoder, return 0; } +static int intel_dp_dsc_mst_compute_link_config(struct intel_encoder *encoder, + struct intel_crtc_state *crtc_state, + struct drm_connector_state *conn_state, + struct link_config_limits *limits) +{ + struct drm_atomic_state *state = crtc_state->uapi.state; + struct intel_dp_mst_encoder *intel_mst = enc_to_mst(encoder); + struct intel_dp *intel_dp = &intel_mst->primary->dp; + struct intel_connector *connector = + to_intel_connector(conn_state->connector); + struct drm_i915_private *i915 = to_i915(connector->base.dev); + const struct drm_display_mode *adjusted_mode = + &crtc_state->hw.adjusted_mode; + bool constant_n = drm_dp_has_quirk(&intel_dp->desc, + DP_DPCD_QUIRK_CONSTANT_N); + int bpp, slots = -EINVAL; + int i, num_bpc; + u8 dsc_bpc[3] = {0}; + int min_bpp, max_bpp; + u8 dsc_max_bpc; + + crtc_state->lane_count = limits->max_lane_count; + crtc_state->port_clock = limits->max_rate; + + /* Max DSC Input BPC for ICL is 10 and for TGL+ is 12 */ + if (DISPLAY_VER(i915) >= 12) + dsc_max_bpc = min_t(u8, 12, conn_state->max_requested_bpc); + else + dsc_max_bpc = min_t(u8, 10, conn_state->max_requested_bpc); + + max_bpp = min_t(u8, dsc_max_bpc * 3, limits->max_bpp); + min_bpp = limits->min_bpp; + + num_bpc = drm_dp_dsc_sink_supported_input_bpcs(intel_dp->dsc_dpcd, + dsc_bpc); + for (i = 0; i < num_bpc; i++) { + if (max_bpp >= dsc_bpc[i] * 3) + if (min_bpp > dsc_bpc[i] * 3) + min_bpp = dsc_bpc[i] * 3; + } + drm_dbg_kms(&i915->drm, "DSC Sink supported min bpp %d max bpp %d\n", + min_bpp, max_bpp); + for (bpp = max_bpp; bpp >= min_bpp; bpp -= 2 * 3) { + crtc_state->pbn = drm_dp_calc_pbn_mode(adjusted_mode->crtc_clock, + bpp << 4, + true); + + slots = drm_dp_atomic_find_vcpi_slots(state, &intel_dp->mst_mgr, + connector->port, + crtc_state->pbn, 0); + + drm_dbg_kms(&i915->drm, "Trying bpp %d got %d pbn %d slots\n", + bpp, crtc_state->pbn, slots); + + if (slots == -EDEADLK) + return slots; + if (slots >= 0) + break; + } + + if (slots < 0) { + drm_dbg_kms(&i915->drm, "failed finding vcpi slots:%d\n", + slots); + return slots; + } + + intel_link_compute_m_n(crtc_state->pipe_bpp, + crtc_state->lane_count, + adjusted_mode->crtc_clock, + crtc_state->port_clock, + &crtc_state->dp_m_n, + constant_n, crtc_state->fec_enable); + crtc_state->dp_m_n.tu = slots; + + return 0; +} static int intel_dp_mst_update_slots(struct intel_encoder *encoder, struct intel_crtc_state *crtc_state, struct drm_connector_state *conn_state) @@ -175,6 +251,27 @@ static int intel_dp_mst_compute_config(struct intel_encoder *encoder, ret = intel_dp_mst_compute_link_config(encoder, pipe_config, conn_state, &limits); + + if (ret == -EDEADLK) + return ret; + + /* enable compression if the mode doesn't fit available BW */ + drm_dbg_kms(&dev_priv->drm, "Force DSC en = %d\n", intel_dp->force_dsc_en); + if (ret || intel_dp->force_dsc_en) { + /* + * Try to get at least some timeslots and then see, if + * we can fit there with DSC. + */ + ret = intel_dp_dsc_mst_compute_link_config(encoder, pipe_config, + conn_state, &limits); + if (ret < 0) + return ret; + + ret = intel_dp_dsc_compute_config(intel_dp, pipe_config, + conn_state, &limits, + pipe_config->dp_m_n.tu); + } + if (ret) return ret; @@ -715,6 +812,10 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, int max_dotclk = to_i915(connector->dev)->max_dotclk_freq; int max_rate, mode_rate, max_lanes, max_link_clock; int ret; + bool dsc = false, bigjoiner = false; + u16 dsc_max_output_bpp = 0; + u8 dsc_slice_count = 0; + int target_clock = mode->clock; if (drm_connector_is_unregistered(connector)) { *status = MODE_ERROR; @@ -752,6 +853,48 @@ intel_dp_mst_mode_valid_ctx(struct drm_connector *connector, return 0; } + if (intel_dp_need_bigjoiner(intel_dp, mode->hdisplay, target_clock)) { + bigjoiner = true; + max_dotclk *= 2; + } + + if (DISPLAY_VER(dev_priv) >= 10 && + drm_dp_sink_supports_dsc(intel_dp->dsc_dpcd)) { + /* + * TBD pass the connector BPC, + * for now U8_MAX so that max BPC on that platform would be picked + */ + int pipe_bpp = intel_dp_dsc_compute_bpp(intel_dp, U8_MAX); + + if (drm_dp_sink_supports_fec(intel_dp->fec_capable)) { + dsc_max_output_bpp = + intel_dp_dsc_get_output_bpp(dev_priv, + max_link_clock, + max_lanes, + target_clock, + mode->hdisplay, + bigjoiner, + pipe_bpp, 1) >> 4; + dsc_slice_count = + intel_dp_dsc_get_slice_count(intel_dp, + target_clock, + mode->hdisplay, + bigjoiner); + } + + dsc = dsc_max_output_bpp && dsc_slice_count; + } + + /* + * Big joiner configuration needs DSC for TGL which is not true for + * XE_LPD where uncompressed joiner is supported. + */ + if (DISPLAY_VER(dev_priv) < 13 && bigjoiner && !dsc) + return MODE_CLOCK_HIGH; + + if (mode_rate > max_rate && !dsc) + return MODE_CLOCK_HIGH; + *status = intel_mode_valid_max_plane_size(dev_priv, mode, false); return 0; } -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DP MST DSC support to i915 (rev2) 2022-03-21 9:10 ` [Intel-gfx] " Stanislav Lisovskiy ` (2 preceding siblings ...) (?) @ 2022-03-21 9:25 ` Patchwork -1 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-03-21 9:25 UTC (permalink / raw) To: Stanislav Lisovskiy; +Cc: intel-gfx == Series Details == Series: Add DP MST DSC support to i915 (rev2) URL : https://patchwork.freedesktop.org/series/101492/ State : warning == Summary == $ dim checkpatch origin/drm-tip 9b8bc9218f7e drm: Add missing DP DSC extended capability definitions. -:45: CHECK:LINE_SPACING: Please don't use multiple blank lines #45: FILE: drivers/gpu/drm/dp/drm_dp.c:2339: + + total: 0 errors, 0 warnings, 1 checks, 76 lines checked 3508503c9690 drm/i915: Add DSC support to MST path ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for Add DP MST DSC support to i915 (rev2) 2022-03-21 9:10 ` [Intel-gfx] " Stanislav Lisovskiy ` (3 preceding siblings ...) (?) @ 2022-03-21 9:28 ` Patchwork -1 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-03-21 9:28 UTC (permalink / raw) To: Stanislav Lisovskiy; +Cc: intel-gfx == Series Details == Series: Add DP MST DSC support to i915 (rev2) URL : https://patchwork.freedesktop.org/series/101492/ State : warning == Summary == $ dim sparse --fast origin/drm-tip Sparse version: v0.6.2 Fast mode used, each commit won't be checked separately. - +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1444:25: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1444:25: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1444:25: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1445:17: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1445:17: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1445:17: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1504:17: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1504:17: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1504:17: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:353:16: error: incompatible types in comparison expression (different type sizes): +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:353:16: unsigned long * +drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:353:16: unsigned long long * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:345:17: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:345:17: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:345:17: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:596:23: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:596:23: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:596:23: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:598:25: error: incompatible types in comparison expression (different address spaces): +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:598:25: struct dma_fence * +drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:598:25: struct dma_fence [noderef] __rcu * +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB" +drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for Add DP MST DSC support to i915 (rev2) 2022-03-21 9:10 ` [Intel-gfx] " Stanislav Lisovskiy ` (4 preceding siblings ...) (?) @ 2022-03-21 10:04 ` Patchwork -1 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-03-21 10:04 UTC (permalink / raw) To: Stanislav Lisovskiy; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 10775 bytes --] == Series Details == Series: Add DP MST DSC support to i915 (rev2) URL : https://patchwork.freedesktop.org/series/101492/ State : success == Summary == CI Bug Log - changes from CI_DRM_11387 -> Patchwork_22624 ==================================================== Summary ------- **SUCCESS** No regressions found. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/index.html Participating hosts (43 -> 42) ------------------------------ Additional (4): bat-rpls-1 bat-rpls-2 bat-adlm-1 bat-dg1-6 Missing (5): shard-tglu fi-bsw-cyan fi-pnv-d510 shard-rkl shard-dg1 Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_22624: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@kms_flip@basic-flip-vs-modeset@c-dp1: - {bat-adlm-1}: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-adlm-1/igt@kms_flip@basic-flip-vs-modeset@c-dp1.html Known issues ------------ Here are the changes found in Patchwork_22624 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@fbdev@nullptr: - bat-dg1-6: NOTRUN -> [SKIP][2] ([i915#2582]) +4 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@fbdev@nullptr.html * igt@gem_exec_gttfill@basic: - bat-dg1-6: NOTRUN -> [SKIP][3] ([i915#4086]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@gem_exec_gttfill@basic.html * igt@gem_mmap@basic: - bat-dg1-6: NOTRUN -> [SKIP][4] ([i915#4083]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@gem_mmap@basic.html * igt@gem_tiled_blits@basic: - bat-dg1-6: NOTRUN -> [SKIP][5] ([i915#4077]) +2 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@gem_tiled_blits@basic.html * igt@gem_tiled_pread_basic: - bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4079]) +1 similar issue [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@gem_tiled_pread_basic.html * igt@i915_pm_backlight@basic-brightness: - bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#1155]) [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@i915_pm_backlight@basic-brightness.html * igt@i915_selftest@live@hangcheck: - bat-dg1-6: NOTRUN -> [DMESG-FAIL][8] ([i915#4494] / [i915#4957]) [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@i915_selftest@live@hangcheck.html - fi-hsw-4770: [PASS][9] -> [INCOMPLETE][10] ([i915#3303]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html * igt@kms_addfb_basic@addfb25-x-tiled-legacy: - bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#4212]) +7 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html * igt@kms_addfb_basic@basic-y-tiled-legacy: - bat-dg1-6: NOTRUN -> [SKIP][12] ([i915#4215]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html * igt@kms_busy@basic: - bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4303]) [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@kms_busy@basic.html * igt@kms_chamelium@hdmi-edid-read: - bat-dg1-6: NOTRUN -> [SKIP][14] ([fdo#111827]) +8 similar issues [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@kms_chamelium@hdmi-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - bat-dg1-6: NOTRUN -> [SKIP][15] ([i915#4103] / [i915#4213]) +1 similar issue [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt@kms_cursor_legacy@basic-flip-after-cursor-legacy: - bat-dg1-6: NOTRUN -> [SKIP][16] ([i915#4078]) +23 similar issues [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@kms_cursor_legacy@basic-flip-after-cursor-legacy.html * igt@kms_force_connector_basic@force-load-detect: - bat-dg1-6: NOTRUN -> [SKIP][17] ([fdo#109285]) [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c: - bat-dg1-6: NOTRUN -> [SKIP][18] ([i915#4078] / [i915#5341]) [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html * igt@kms_psr@cursor_plane_move: - bat-dg1-6: NOTRUN -> [SKIP][19] ([i915#1072] / [i915#4078]) +3 similar issues [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@kms_psr@cursor_plane_move.html * igt@kms_setmode@basic-clone-single-crtc: - bat-dg1-6: NOTRUN -> [SKIP][20] ([i915#3555]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@kms_setmode@basic-clone-single-crtc.html * igt@prime_vgem@basic-fence-flip: - bat-dg1-6: NOTRUN -> [SKIP][21] ([i915#3708]) +3 similar issues [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@prime_vgem@basic-fence-flip.html * igt@prime_vgem@basic-gtt: - bat-dg1-6: NOTRUN -> [SKIP][22] ([i915#3708] / [i915#4077]) +1 similar issue [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@prime_vgem@basic-gtt.html * igt@prime_vgem@basic-userptr: - bat-dg1-6: NOTRUN -> [SKIP][23] ([i915#3708] / [i915#4873]) [23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg1-6/igt@prime_vgem@basic-userptr.html * igt@runner@aborted: - fi-hsw-4770: NOTRUN -> [FAIL][24] ([fdo#109271] / [i915#1436] / [i915#4312]) [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/fi-hsw-4770/igt@runner@aborted.html #### Possible fixes #### * igt@gem_busy@busy@all: - {bat-dg2-9}: [DMESG-WARN][25] ([i915#5195]) -> [PASS][26] [25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/bat-dg2-9/igt@gem_busy@busy@all.html [26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/bat-dg2-9/igt@gem_busy@busy@all.html * igt@i915_selftest@live@perf: - {fi-tgl-dsi}: [DMESG-WARN][27] ([i915#2867]) -> [PASS][28] [27]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/fi-tgl-dsi/igt@i915_selftest@live@perf.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/fi-tgl-dsi/igt@i915_selftest@live@perf.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308 [fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155 [i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436 [i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845 [i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849 [i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582 [i915#2867]: https://gitlab.freedesktop.org/drm/intel/issues/2867 [i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282 [i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576 [i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595 [i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637 [i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708 [i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077 [i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078 [i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079 [i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083 [i915#4086]: https://gitlab.freedesktop.org/drm/intel/issues/4086 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212 [i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213 [i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215 [i915#4303]: https://gitlab.freedesktop.org/drm/intel/issues/4303 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391 [i915#4494]: https://gitlab.freedesktop.org/drm/intel/issues/4494 [i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613 [i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873 [i915#4957]: https://gitlab.freedesktop.org/drm/intel/issues/4957 [i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190 [i915#5192]: https://gitlab.freedesktop.org/drm/intel/issues/5192 [i915#5193]: https://gitlab.freedesktop.org/drm/intel/issues/5193 [i915#5195]: https://gitlab.freedesktop.org/drm/intel/issues/5195 [i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274 [i915#5337]: https://gitlab.freedesktop.org/drm/intel/issues/5337 [i915#5339]: https://gitlab.freedesktop.org/drm/intel/issues/5339 [i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341 Build changes ------------- * Linux: CI_DRM_11387 -> Patchwork_22624 CI-20190529: 20190529 CI_DRM_11387: 028e1cf1266d3cd2bc46952c6003fd3253a1cc4e @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6386: 0fcd59ad25b2960c0b654f90dfe4dd9e7c7b874d @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22624: 3508503c9690503761e729457e27de21bf797cde @ git://anongit.freedesktop.org/gfx-ci/linux == Linux commits == 3508503c9690 drm/i915: Add DSC support to MST path 9b8bc9218f7e drm: Add missing DP DSC extended capability definitions. == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/index.html [-- Attachment #2: Type: text/html, Size: 11263 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for Add DP MST DSC support to i915 (rev2) 2022-03-21 9:10 ` [Intel-gfx] " Stanislav Lisovskiy ` (5 preceding siblings ...) (?) @ 2022-03-21 11:40 ` Patchwork -1 siblings, 0 replies; 16+ messages in thread From: Patchwork @ 2022-03-21 11:40 UTC (permalink / raw) To: Stanislav Lisovskiy; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 30261 bytes --] == Series Details == Series: Add DP MST DSC support to i915 (rev2) URL : https://patchwork.freedesktop.org/series/101492/ State : success == Summary == CI Bug Log - changes from CI_DRM_11387_full -> Patchwork_22624_full ==================================================== Summary ------- **SUCCESS** No regressions found. Participating hosts (13 -> 13) ------------------------------ No changes in participating hosts Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_22624_full: ### IGT changes ### #### Suppressed #### The following results come from untrusted machines, tests, or statuses. They do not affect the overall result. * igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen: - {shard-rkl}: NOTRUN -> ([SKIP][1], [SKIP][2]) ([fdo#112022] / [i915#4070]) +1 similar issue [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen.html [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen.html * igt@kms_cursor_crc@pipe-a-cursor-512x512-random: - {shard-rkl}: NOTRUN -> ([SKIP][3], [SKIP][4]) ([fdo#112022]) [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-5/igt@kms_cursor_crc@pipe-a-cursor-512x512-random.html [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_cursor_crc@pipe-a-cursor-512x512-random.html * igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding: - {shard-rkl}: [SKIP][5] ([fdo#109279] / [i915#3359] / [i915#4070]) -> ([SKIP][6], [SKIP][7]) ([fdo#112022] / [i915#4070]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-512x512-sliding.html * igt@kms_cursor_crc@pipe-a-cursor-64x64-rapid-movement: - {shard-rkl}: [SKIP][8] ([fdo#112022] / [i915#4070]) -> [SKIP][9] +2 similar issues [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-2/igt@kms_cursor_crc@pipe-a-cursor-64x64-rapid-movement.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_cursor_crc@pipe-a-cursor-64x64-rapid-movement.html * igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen: - {shard-rkl}: [SKIP][10] ([fdo#112022]) -> ([SKIP][11], [SKIP][12]) ([fdo#112022] / [i915#4070]) +2 similar issues [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-5/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-1/igt@kms_cursor_crc@pipe-b-cursor-256x256-offscreen.html * igt@kms_cursor_crc@pipe-b-cursor-512x170-sliding: - {shard-rkl}: [SKIP][13] ([fdo#112022]) -> [SKIP][14] +1 similar issue [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-4/igt@kms_cursor_crc@pipe-b-cursor-512x170-sliding.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_cursor_crc@pipe-b-cursor-512x170-sliding.html * igt@kms_cursor_crc@pipe-b-cursor-64x21-rapid-movement: - {shard-rkl}: [SKIP][15] ([fdo#112022] / [i915#4070]) -> ([SKIP][16], [PASS][17]) [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-1/igt@kms_cursor_crc@pipe-b-cursor-64x21-rapid-movement.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_cursor_crc@pipe-b-cursor-64x21-rapid-movement.html [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-64x21-rapid-movement.html * igt@kms_cursor_crc@pipe-b-cursor-64x64-random: - {shard-rkl}: [PASS][18] -> [SKIP][19] +3 similar issues [18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html * igt@kms_cursor_edge_walk@pipe-c-128x128-top-edge: - {shard-rkl}: [SKIP][20] ([i915#1849] / [i915#4098]) -> ([SKIP][21], [SKIP][22]) ([i915#4070]) [20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-5/igt@kms_cursor_edge_walk@pipe-c-128x128-top-edge.html [21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_cursor_edge_walk@pipe-c-128x128-top-edge.html [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-1/igt@kms_cursor_edge_walk@pipe-c-128x128-top-edge.html * igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge: - {shard-rkl}: ([SKIP][23], [SKIP][24]) ([i915#1849] / [i915#4098]) -> [SKIP][25] [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-5/igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge.html [24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-4/igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge.html [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_cursor_edge_walk@pipe-c-64x64-left-edge.html * igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen: - {shard-rkl}: [SKIP][26] ([i915#1849]) -> ([SKIP][27], [PASS][28]) [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-1p-primscrn-spr-indfb-fullscreen.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt: - {shard-rkl}: [SKIP][29] ([fdo#111825] / [i915#1825]) -> ([SKIP][30], [SKIP][31]) ([i915#1849]) [29]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-pri-shrfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt: - {shard-rkl}: [SKIP][32] ([fdo#111825] / [i915#1825]) -> [SKIP][33] +1 similar issue [32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt.html [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-spr-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render: - {shard-rkl}: [PASS][34] -> ([SKIP][35], [SKIP][36]) ([i915#1849]) +1 similar issue [34]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-6/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-1/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_frontbuffer_tracking@fbc-rgb565-draw-render.html * igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc: - {shard-rkl}: NOTRUN -> ([SKIP][37], [SKIP][38]) ([i915#1849]) +9 similar issues [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-5/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-1p-primscrn-spr-indfb-draw-mmap-wc.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite: - {shard-rkl}: NOTRUN -> [SKIP][39] +27 similar issues [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-primscrn-pri-indfb-draw-pwrite.html * igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-cpu: - {shard-rkl}: [SKIP][40] ([i915#1849]) -> ([SKIP][41], [SKIP][42]) ([fdo#111825] / [i915#1825]) [40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-cpu.html [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-cpu.html [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-cpu.html * igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-gtt: - {shard-rkl}: [SKIP][43] ([i915#1849]) -> [SKIP][44] +9 similar issues [43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-5/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-gtt.html [44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-2p-primscrn-pri-indfb-draw-mmap-gtt.html * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-pwrite: - {shard-rkl}: [SKIP][45] ([i915#4098]) -> [SKIP][46] +3 similar issues [45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-4/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-pwrite.html [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-pwrite.html * igt@kms_pipe_crc_basic@read-crc-pipe-c: - {shard-rkl}: [SKIP][47] ([i915#1849] / [i915#4098]) -> [SKIP][48] +1 similar issue [47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-5/igt@kms_pipe_crc_basic@read-crc-pipe-c.html [48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_pipe_crc_basic@read-crc-pipe-c.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max: - {shard-rkl}: NOTRUN -> ([SKIP][49], [SKIP][50]) ([i915#1849] / [i915#4070] / [i915#4098]) +1 similar issue [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-2/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html [50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html * igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min: - {shard-rkl}: NOTRUN -> ([SKIP][51], [SKIP][52]) ([i915#1849] / [i915#4098]) [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-5/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-min.html * igt@kms_plane_alpha_blend@pipe-b-alpha-basic: - {shard-rkl}: [SKIP][53] ([i915#1849] / [i915#4098]) -> ([SKIP][54], [SKIP][55]) ([i915#1849] / [i915#4070] / [i915#4098]) [53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-5/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-1/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_plane_alpha_blend@pipe-b-alpha-basic.html * igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min: - {shard-rkl}: [SKIP][56] ([i915#4070]) -> ([SKIP][57], [SKIP][58]) ([i915#1849] / [i915#4098]) [56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-5/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-min.html * igt@kms_plane_multiple@atomic-pipe-c-tiling-4: - {shard-rkl}: NOTRUN -> ([SKIP][59], [SKIP][60]) ([i915#4070]) [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-2/igt@kms_plane_multiple@atomic-pipe-c-tiling-4.html [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-4/igt@kms_plane_multiple@atomic-pipe-c-tiling-4.html * igt@kms_properties@plane-properties-legacy: - {shard-rkl}: ([SKIP][61], [SKIP][62]) ([i915#1849] / [i915#4098]) -> ([SKIP][63], [SKIP][64]) ([i915#1849]) +1 similar issue [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-4/igt@kms_properties@plane-properties-legacy.html [62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-rkl-5/igt@kms_properties@plane-properties-legacy.html [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-1/igt@kms_properties@plane-properties-legacy.html [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-rkl-3/igt@kms_properties@plane-properties-legacy.html Known issues ------------ Here are the changes found in Patchwork_22624_full that come from known issues: ### IGT changes ### #### Issues hit #### * igt@gem_exec_fair@basic-none@vcs1: - shard-iclb: NOTRUN -> [FAIL][65] ([i915#2842]) [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb1/igt@gem_exec_fair@basic-none@vcs1.html * igt@gem_exec_fair@basic-pace@vcs1: - shard-kbl: NOTRUN -> [FAIL][66] ([i915#2842]) [66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-kbl4/igt@gem_exec_fair@basic-pace@vcs1.html * igt@gem_exec_fair@basic-throttle@rcs0: - shard-iclb: NOTRUN -> [FAIL][67] ([i915#2849]) [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html * igt@gem_exec_params@no-blt: - shard-tglb: NOTRUN -> [SKIP][68] ([fdo#109283]) [68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-tglb8/igt@gem_exec_params@no-blt.html * igt@gem_exec_whisper@basic-fds-forked-all: - shard-iclb: [PASS][69] -> [INCOMPLETE][70] ([i915#1895]) [69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-iclb2/igt@gem_exec_whisper@basic-fds-forked-all.html [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb5/igt@gem_exec_whisper@basic-fds-forked-all.html * igt@gem_exec_whisper@basic-fds-priority-all: - shard-skl: [PASS][71] -> [INCOMPLETE][72] ([i915#5268]) [71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-skl4/igt@gem_exec_whisper@basic-fds-priority-all.html [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-skl6/igt@gem_exec_whisper@basic-fds-priority-all.html * igt@gem_lmem_swapping@heavy-verify-multi: - shard-kbl: NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#4613]) +1 similar issue [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-kbl1/igt@gem_lmem_swapping@heavy-verify-multi.html * igt@gem_lmem_swapping@random-engines: - shard-apl: NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#4613]) [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-apl6/igt@gem_lmem_swapping@random-engines.html * igt@gem_lmem_swapping@smem-oom: - shard-skl: NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#4613]) [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-skl1/igt@gem_lmem_swapping@smem-oom.html * igt@gem_pread@exhaustion: - shard-skl: NOTRUN -> [WARN][76] ([i915#2658]) [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-skl1/igt@gem_pread@exhaustion.html * igt@gem_pxp@create-valid-protected-context: - shard-iclb: NOTRUN -> [SKIP][77] ([i915#4270]) [77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb5/igt@gem_pxp@create-valid-protected-context.html * igt@gem_render_copy@yf-tiled-to-vebox-x-tiled: - shard-iclb: NOTRUN -> [SKIP][78] ([i915#768]) [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb5/igt@gem_render_copy@yf-tiled-to-vebox-x-tiled.html * igt@gem_softpin@evict-snoop-interruptible: - shard-iclb: NOTRUN -> [SKIP][79] ([fdo#109312]) [79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb3/igt@gem_softpin@evict-snoop-interruptible.html * igt@gem_workarounds@suspend-resume-fd: - shard-kbl: [PASS][80] -> [DMESG-WARN][81] ([i915#180]) +1 similar issue [80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-kbl6/igt@gem_workarounds@suspend-resume-fd.html [81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-kbl4/igt@gem_workarounds@suspend-resume-fd.html * igt@gen7_exec_parse@oacontrol-tracking: - shard-iclb: NOTRUN -> [SKIP][82] ([fdo#109289]) [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb5/igt@gen7_exec_parse@oacontrol-tracking.html * igt@gen9_exec_parse@allowed-all: - shard-iclb: NOTRUN -> [SKIP][83] ([i915#2856]) [83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb5/igt@gen9_exec_parse@allowed-all.html - shard-apl: [PASS][84] -> [DMESG-WARN][85] ([i915#1436] / [i915#716]) [84]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-apl7/igt@gen9_exec_parse@allowed-all.html [85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-apl8/igt@gen9_exec_parse@allowed-all.html * igt@gen9_exec_parse@allowed-single: - shard-skl: [PASS][86] -> [DMESG-WARN][87] ([i915#1436] / [i915#716]) [86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-skl10/igt@gen9_exec_parse@allowed-single.html [87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-skl9/igt@gen9_exec_parse@allowed-single.html * igt@i915_module_load@reload: - shard-iclb: [PASS][88] -> [DMESG-WARN][89] ([i915#2867]) [88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-iclb4/igt@i915_module_load@reload.html [89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb3/igt@i915_module_load@reload.html * igt@i915_pm_dc@dc6-dpms: - shard-skl: NOTRUN -> [FAIL][90] ([i915#454]) [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-skl1/igt@i915_pm_dc@dc6-dpms.html * igt@i915_pm_dc@dc9-dpms: - shard-iclb: [PASS][91] -> [SKIP][92] ([i915#4281]) [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-iclb8/igt@i915_pm_dc@dc9-dpms.html [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html * igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp: - shard-apl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#1937]) [93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-apl6/igt@i915_pm_lpsp@kms-lpsp@kms-lpsp-dp.html * igt@i915_pm_rpm@modeset-non-lpsp-stress: - shard-iclb: NOTRUN -> [SKIP][94] ([fdo#110892]) [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb3/igt@i915_pm_rpm@modeset-non-lpsp-stress.html * igt@i915_suspend@forcewake: - shard-apl: [PASS][95] -> [DMESG-WARN][96] ([i915#180]) +1 similar issue [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-apl4/igt@i915_suspend@forcewake.html [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-apl6/igt@i915_suspend@forcewake.html * igt@kms_async_flips@crc: - shard-skl: NOTRUN -> [FAIL][97] ([i915#4272]) [97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-skl7/igt@kms_async_flips@crc.html * igt@kms_big_fb@4-tiled-32bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][98] ([i915#5286]) +1 similar issue [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb5/igt@kms_big_fb@4-tiled-32bpp-rotate-90.html * igt@kms_big_fb@linear-8bpp-rotate-90: - shard-iclb: NOTRUN -> [SKIP][99] ([fdo#110725] / [fdo#111614]) +1 similar issue [99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb8/igt@kms_big_fb@linear-8bpp-rotate-90.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip: - shard-skl: NOTRUN -> [FAIL][100] ([i915#3743]) [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-skl1/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-async-flip.html * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip: - shard-kbl: NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#3777]) [101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-kbl3/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip: - shard-skl: NOTRUN -> [FAIL][102] ([i915#3763]) [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-skl7/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html * igt@kms_big_fb@yf-tiled-64bpp-rotate-270: - shard-iclb: NOTRUN -> [SKIP][103] ([fdo#110723]) [103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb8/igt@kms_big_fb@yf-tiled-64bpp-rotate-270.html * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip: - shard-skl: NOTRUN -> [SKIP][104] ([fdo#109271] / [i915#3777]) +1 similar issue [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-skl1/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html * igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs: - shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109278] / [i915#3886]) +1 similar issue [105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb5/igt@kms_ccs@pipe-a-bad-rotation-90-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs: - shard-kbl: NOTRUN -> [SKIP][106] ([fdo#109271] / [i915#3886]) +4 similar issues [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-kbl4/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc: - shard-skl: NOTRUN -> [SKIP][107] ([fdo#109271] / [i915#3886]) +6 similar issues [107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-skl7/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html * igt@kms_ccs@pipe-d-ccs-on-another-bo-yf_tiled_ccs: - shard-iclb: NOTRUN -> [SKIP][108] ([fdo#109278]) +13 similar issues [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb3/igt@kms_ccs@pipe-d-ccs-on-another-bo-yf_tiled_ccs.html * igt@kms_chamelium@dp-hpd-with-enabled-mode: - shard-iclb: NOTRUN -> [SKIP][109] ([fdo#109284] / [fdo#111827]) +6 similar issues [109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb5/igt@kms_chamelium@dp-hpd-with-enabled-mode.html * igt@kms_chamelium@hdmi-audio-edid: - shard-skl: NOTRUN -> [SKIP][110] ([fdo#109271] / [fdo#111827]) +5 similar issues [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-skl7/igt@kms_chamelium@hdmi-audio-edid.html * igt@kms_chamelium@hdmi-hpd-with-enabled-mode: - shard-kbl: NOTRUN -> [SKIP][111] ([fdo#109271] / [fdo#111827]) +7 similar issues [111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-kbl1/igt@kms_chamelium@hdmi-hpd-with-enabled-mode.html * igt@kms_chamelium@hdmi-mode-timings: - shard-apl: NOTRUN -> [SKIP][112] ([fdo#109271] / [fdo#111827]) +1 similar issue [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-apl6/igt@kms_chamelium@hdmi-mode-timings.html * igt@kms_color_chamelium@pipe-b-ctm-max: - shard-tglb: NOTRUN -> [SKIP][113] ([fdo#109284] / [fdo#111827]) [113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-tglb8/igt@kms_color_chamelium@pipe-b-ctm-max.html * igt@kms_color_chamelium@pipe-d-ctm-negative: - shard-iclb: NOTRUN -> [SKIP][114] ([fdo#109278] / [fdo#109284] / [fdo#111827]) +1 similar issue [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb8/igt@kms_color_chamelium@pipe-d-ctm-negative.html * igt@kms_content_protection@atomic: - shard-apl: NOTRUN -> [TIMEOUT][115] ([i915#1319]) [115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-apl6/igt@kms_content_protection@atomic.html * igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding: - shard-kbl: NOTRUN -> [SKIP][116] ([fdo#109271]) +132 similar issues [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-kbl4/igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding.html - shard-tglb: NOTRUN -> [SKIP][117] ([fdo#109279] / [i915#3359]) [117]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-tglb8/igt@kms_cursor_crc@pipe-a-cursor-512x170-sliding.html * igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen: - shard-iclb: NOTRUN -> [SKIP][118] ([fdo#109278] / [fdo#109279]) +3 similar issues [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb8/igt@kms_cursor_crc@pipe-a-cursor-512x512-offscreen.html * igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge: - shard-snb: [PASS][119] -> [SKIP][120] ([fdo#109271]) [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-snb7/igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge.html [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-snb2/igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge.html * igt@kms_cursor_legacy@cursorb-vs-flipb-toggle: - shard-iclb: NOTRUN -> [SKIP][121] ([fdo#109274] / [fdo#109278]) +2 similar issues [121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb5/igt@kms_cursor_legacy@cursorb-vs-flipb-toggle.html * igt@kms_cursor_legacy@flip-vs-cursor-toggle: - shard-iclb: [PASS][122] -> [FAIL][123] ([i915#2346]) [122]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-iclb3/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html [123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html * igt@kms_cursor_legacy@pipe-d-single-bo: - shard-apl: NOTRUN -> [SKIP][124] ([fdo#109271] / [i915#533]) [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-apl6/igt@kms_cursor_legacy@pipe-d-single-bo.html * igt@kms_draw_crc@draw-method-xrgb2101010-render-4tiled: - shard-iclb: NOTRUN -> [SKIP][125] ([i915#5287]) [125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb5/igt@kms_draw_crc@draw-method-xrgb2101010-render-4tiled.html * igt@kms_fbcon_fbt@fbc-suspend: - shard-kbl: [PASS][126] -> [INCOMPLETE][127] ([i915#180] / [i915#636]) [126]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-kbl1/igt@kms_fbcon_fbt@fbc-suspend.html [127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-kbl6/igt@kms_fbcon_fbt@fbc-suspend.html * igt@kms_flip@2x-absolute-wf_vblank-interruptible: - shard-iclb: NOTRUN -> [SKIP][128] ([fdo#109274]) +2 similar issues [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb5/igt@kms_flip@2x-absolute-wf_vblank-interruptible.html * igt@kms_flip@2x-flip-vs-panning: - shard-apl: NOTRUN -> [SKIP][129] ([fdo#109271]) +23 similar issues [129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-apl6/igt@kms_flip@2x-flip-vs-panning.html * igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1: - shard-glk: [PASS][130] -> [FAIL][131] ([i915#79]) [130]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-glk8/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html [131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-glk2/igt@kms_flip@flip-vs-expired-vblank-interruptible@b-hdmi-a1.html * igt@kms_flip@flip-vs-expired-vblank@b-edp1: - shard-skl: [PASS][132] -> [FAIL][133] ([i915#79]) [132]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html [133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@b-edp1.html * igt@kms_flip@flip-vs-suspend-interruptible@b-edp1: - shard-skl: [PASS][134] -> [INCOMPLETE][135] ([i915#4839]) [134]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11387/shard-skl6/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html [135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-skl9/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html * igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling: - shard-iclb: NOTRUN -> [SKIP][136] ([i915#2587]) [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-iclb5/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-32bpp-ytilercccs-downscaling.html * igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt: - shard-skl: NOTRUN -> [SKIP][137] ([fdo#109271]) +133 similar issues [137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/shard-skl1/igt@kms_frontbuffer_tracking@fbc-1p-shrfb-fliptrack-mmap-gtt.html * igt@kms_frontbuffer_trackin == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22624/index.html [-- Attachment #2: Type: text/html, Size: 33151 bytes --] ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-08-22 9:40 Stanislav Lisovskiy 2022-08-22 9:40 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 0 siblings, 1 reply; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-08-22 9:40 UTC (permalink / raw) To: intel-gfx Cc: Stanislav.Lisovskiy, jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/i915/display/intel_dp.c | 73 ++++----- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 157 ++++++++++++++++++++ include/drm/display/drm_dp.h | 10 +- 4 files changed, 214 insertions(+), 43 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] drm: Add missing DP DSC extended capability definitions. 2022-08-22 9:40 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy @ 2022-08-22 9:40 ` Stanislav Lisovskiy 0 siblings, 0 replies; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-08-22 9:40 UTC (permalink / raw) To: intel-gfx Cc: Stanislav.Lisovskiy, jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning v3: - Removed function which is not yet used(Jani Nikula) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- include/drm/display/drm_dp.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 9e3aff7e68bb..0d05e3172f96 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -239,6 +239,9 @@ #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -277,12 +280,15 @@ #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -344,11 +350,13 @@ # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-08-15 17:35 Stanislav Lisovskiy 2022-08-15 17:35 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 0 siblings, 1 reply; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-08-15 17:35 UTC (permalink / raw) To: intel-gfx Cc: Stanislav.Lisovskiy, jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/i915/display/intel_dp.c | 76 ++++------ drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 157 ++++++++++++++++++++ include/drm/display/drm_dp.h | 10 +- 4 files changed, 215 insertions(+), 45 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] drm: Add missing DP DSC extended capability definitions. 2022-08-15 17:35 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy @ 2022-08-15 17:35 ` Stanislav Lisovskiy 0 siblings, 0 replies; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-08-15 17:35 UTC (permalink / raw) To: intel-gfx Cc: Stanislav.Lisovskiy, jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning v3: - Removed function which is not yet used(Jani Nikula) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- include/drm/display/drm_dp.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 9e3aff7e68bb..0d05e3172f96 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -239,6 +239,9 @@ #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -277,12 +280,15 @@ #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -344,11 +350,13 @@ # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-08-10 8:17 Stanislav Lisovskiy 2022-08-10 8:17 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 0 siblings, 1 reply; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-08-10 8:17 UTC (permalink / raw) To: intel-gfx Cc: Stanislav.Lisovskiy, jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/i915/display/intel_dp.c | 76 +++++----- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 145 ++++++++++++++++++++ include/drm/display/drm_dp.h | 10 +- 4 files changed, 203 insertions(+), 45 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] drm: Add missing DP DSC extended capability definitions. 2022-08-10 8:17 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy @ 2022-08-10 8:17 ` Stanislav Lisovskiy 0 siblings, 0 replies; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-08-10 8:17 UTC (permalink / raw) To: intel-gfx Cc: Stanislav.Lisovskiy, jani.nikula, manasi.d.navare, jani.saarinen, dri-devel Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning v3: - Removed function which is not yet used(Jani Nikula) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- include/drm/display/drm_dp.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/include/drm/display/drm_dp.h b/include/drm/display/drm_dp.h index 9e3aff7e68bb..0d05e3172f96 100644 --- a/include/drm/display/drm_dp.h +++ b/include/drm/display/drm_dp.h @@ -239,6 +239,9 @@ #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -277,12 +280,15 @@ #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -344,11 +350,13 @@ # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-04-11 16:25 Stanislav Lisovskiy 2022-04-11 16:25 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 0 siblings, 1 reply; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-04-11 16:25 UTC (permalink / raw) To: intel-gfx; +Cc: Stanislav.Lisovskiy, jani.nikula, dri-devel, jani.saarinen Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/i915/display/intel_dp.c | 75 +++++----- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 143 ++++++++++++++++++++ include/drm/dp/drm_dp_helper.h | 10 +- 4 files changed, 200 insertions(+), 45 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] drm: Add missing DP DSC extended capability definitions. 2022-04-11 16:25 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy @ 2022-04-11 16:25 ` Stanislav Lisovskiy 0 siblings, 0 replies; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-04-11 16:25 UTC (permalink / raw) To: intel-gfx; +Cc: Stanislav.Lisovskiy, jani.nikula, dri-devel, jani.saarinen Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. v2: - Fixed checkpatch comment warning v3: - Removed function which is not yet used(Jani Nikula) Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- include/drm/dp/drm_dp_helper.h | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h index 1eccd9741943..272e687ae25f 100644 --- a/include/drm/dp/drm_dp_helper.h +++ b/include/drm/dp/drm_dp_helper.h @@ -246,6 +246,9 @@ struct drm_panel; #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -284,12 +287,15 @@ struct drm_panel; #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -351,11 +357,13 @@ struct drm_panel; # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 0/2] Add DP MST DSC support to i915 @ 2022-03-17 16:33 Stanislav Lisovskiy 2022-03-17 16:33 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 0 siblings, 1 reply; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-03-17 16:33 UTC (permalink / raw) To: intel-gfx; +Cc: manasi.d.navare, Stanislav.Lisovskiy, jani.saarinen, dri-devel Currently we have only DSC support for DP SST. Stanislav Lisovskiy (2): drm: Add missing DP DSC extended capability definitions. drm/i915: Add DSC support to MST path drivers/gpu/drm/dp/drm_dp.c | 25 ++++ drivers/gpu/drm/i915/display/intel_dp.c | 138 ++++++++++++++++-- drivers/gpu/drm/i915/display/intel_dp.h | 17 +++ drivers/gpu/drm/i915/display/intel_dp_mst.c | 146 +++++++++++++++++++- include/drm/dp/drm_dp_helper.h | 11 +- 5 files changed, 320 insertions(+), 17 deletions(-) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/2] drm: Add missing DP DSC extended capability definitions. 2022-03-17 16:33 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy @ 2022-03-17 16:33 ` Stanislav Lisovskiy 0 siblings, 0 replies; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-03-17 16:33 UTC (permalink / raw) To: intel-gfx; +Cc: manasi.d.navare, Stanislav.Lisovskiy, jani.saarinen, dri-devel Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/dp/drm_dp.c | 25 +++++++++++++++++++++++++ include/drm/dp/drm_dp_helper.h | 11 ++++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c index 703972ae14c6..fe9c72055638 100644 --- a/drivers/gpu/drm/dp/drm_dp.c +++ b/drivers/gpu/drm/dp/drm_dp.c @@ -2312,6 +2312,31 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], } EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); +/** + * drm_dp_dsc_sink_bpp_increment_div - Get the bits per pixel precision + * which DP DSC sink device supports. + */ +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; + + switch (bpp_increment_dpcd) { + case DP_DSC_BITS_PER_PIXEL_1_16: + return 16; + case DP_DSC_BITS_PER_PIXEL_1_8: + return 8; + case DP_DSC_BITS_PER_PIXEL_1_4: + return 4; + case DP_DSC_BITS_PER_PIXEL_1_2: + return 2; + case DP_DSC_BITS_PER_PIXEL_1_1: + return 1; + } + + return 0; +} + + /** * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits * @dsc_dpcd: DSC capabilities from DPCD diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h index 51e02cf75277..e4c9f4438ccb 100644 --- a/include/drm/dp/drm_dp_helper.h +++ b/include/drm/dp/drm_dp_helper.h @@ -246,6 +246,9 @@ struct drm_panel; #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -284,12 +287,15 @@ struct drm_panel; #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -351,11 +357,13 @@ struct drm_panel; # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 @@ -1825,6 +1833,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], u8 dsc_bpc[3]); +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); static inline bool drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 1/2] drm: Add missing DP DSC extended capability definitions. @ 2022-03-17 16:25 Stanislav Lisovskiy 0 siblings, 0 replies; 16+ messages in thread From: Stanislav Lisovskiy @ 2022-03-17 16:25 UTC (permalink / raw) To: dri-devel; +Cc: manasi.d.navare, Stanislav.Lisovskiy, intel-gfx, jani.saarinen Adding DP DSC register definitions, we might need for further DSC implementation, supporting MST and DP branch pass-through mode. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/dp/drm_dp.c | 25 +++++++++++++++++++++++++ include/drm/dp/drm_dp_helper.h | 11 ++++++++++- 2 files changed, 35 insertions(+), 1 deletion(-) diff --git a/drivers/gpu/drm/dp/drm_dp.c b/drivers/gpu/drm/dp/drm_dp.c index 703972ae14c6..fe9c72055638 100644 --- a/drivers/gpu/drm/dp/drm_dp.c +++ b/drivers/gpu/drm/dp/drm_dp.c @@ -2312,6 +2312,31 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], } EXPORT_SYMBOL(drm_dp_dsc_sink_max_slice_count); +/** + * drm_dp_dsc_sink_bpp_increment_div - Get the bits per pixel precision + * which DP DSC sink device supports. + */ +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) +{ + u8 bpp_increment_dpcd = dsc_dpcd[DP_DSC_BITS_PER_PIXEL_INC - DP_DSC_SUPPORT]; + + switch (bpp_increment_dpcd) { + case DP_DSC_BITS_PER_PIXEL_1_16: + return 16; + case DP_DSC_BITS_PER_PIXEL_1_8: + return 8; + case DP_DSC_BITS_PER_PIXEL_1_4: + return 4; + case DP_DSC_BITS_PER_PIXEL_1_2: + return 2; + case DP_DSC_BITS_PER_PIXEL_1_1: + return 1; + } + + return 0; +} + + /** * drm_dp_dsc_sink_line_buf_depth() - Get the line buffer depth in bits * @dsc_dpcd: DSC capabilities from DPCD diff --git a/include/drm/dp/drm_dp_helper.h b/include/drm/dp/drm_dp_helper.h index 51e02cf75277..e4c9f4438ccb 100644 --- a/include/drm/dp/drm_dp_helper.h +++ b/include/drm/dp/drm_dp_helper.h @@ -246,6 +246,9 @@ struct drm_panel; #define DP_DSC_SUPPORT 0x060 /* DP 1.4 */ # define DP_DSC_DECOMPRESSION_IS_SUPPORTED (1 << 0) +# define DP_DSC_PASS_THROUGH_IS_SUPPORTED (1 << 1) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_COMP_TO_COMP (1 << 2) +# define DP_DSC_DYNAMIC_PPS_UPDATE_SUPPORT_UNCOMP_TO_COMP (1 << 3) #define DP_DSC_REV 0x061 # define DP_DSC_MAJOR_MASK (0xf << 0) @@ -284,12 +287,15 @@ struct drm_panel; #define DP_DSC_BLK_PREDICTION_SUPPORT 0x066 # define DP_DSC_BLK_PREDICTION_IS_SUPPORTED (1 << 0) +# define DP_DSC_RGB_COLOR_CONV_BYPASS_SUPPORT (1 << 1) #define DP_DSC_MAX_BITS_PER_PIXEL_LOW 0x067 /* eDP 1.4 */ #define DP_DSC_MAX_BITS_PER_PIXEL_HI 0x068 /* eDP 1.4 */ # define DP_DSC_MAX_BITS_PER_PIXEL_HI_MASK (0x3 << 0) # define DP_DSC_MAX_BITS_PER_PIXEL_HI_SHIFT 8 +# define DP_DSC_MAX_BPP_DELTA_VERSION_MASK 0x06 +# define DP_DSC_MAX_BPP_DELTA_AVAILABILITY 0x08 #define DP_DSC_DEC_COLOR_FORMAT_CAP 0x069 # define DP_DSC_RGB (1 << 0) @@ -351,11 +357,13 @@ struct drm_panel; # define DP_DSC_24_PER_DP_DSC_SINK (1 << 2) #define DP_DSC_BITS_PER_PIXEL_INC 0x06F +# define DP_DSC_RGB_YCbCr444_MAX_BPP_DELTA_MASK 0x1f +# define DP_DSC_RGB_YCbCr420_MAX_BPP_DELTA_MASK 0xe0 # define DP_DSC_BITS_PER_PIXEL_1_16 0x0 # define DP_DSC_BITS_PER_PIXEL_1_8 0x1 # define DP_DSC_BITS_PER_PIXEL_1_4 0x2 # define DP_DSC_BITS_PER_PIXEL_1_2 0x3 -# define DP_DSC_BITS_PER_PIXEL_1 0x4 +# define DP_DSC_BITS_PER_PIXEL_1_1 0x4 #define DP_PSR_SUPPORT 0x070 /* XXX 1.2? */ # define DP_PSR_IS_SUPPORTED 1 @@ -1825,6 +1833,7 @@ u8 drm_dp_dsc_sink_max_slice_count(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE], u8 drm_dp_dsc_sink_line_buf_depth(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); int drm_dp_dsc_sink_supported_input_bpcs(const u8 dsc_dpc[DP_DSC_RECEIVER_CAP_SIZE], u8 dsc_bpc[3]); +u8 drm_dp_dsc_sink_bpp_increment_div(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]); static inline bool drm_dp_sink_supports_dsc(const u8 dsc_dpcd[DP_DSC_RECEIVER_CAP_SIZE]) -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-08-22 9:41 UTC | newest] Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-03-21 9:10 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy 2022-03-21 9:10 ` [Intel-gfx] " Stanislav Lisovskiy 2022-03-21 9:10 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 2022-03-21 9:10 ` [Intel-gfx] " Stanislav Lisovskiy 2022-03-21 9:10 ` [PATCH 2/2] drm/i915: Add DSC support to MST path Stanislav Lisovskiy 2022-03-21 9:10 ` [Intel-gfx] " Stanislav Lisovskiy 2022-03-21 9:25 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for Add DP MST DSC support to i915 (rev2) Patchwork 2022-03-21 9:28 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork 2022-03-21 10:04 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork 2022-03-21 11:40 ` [Intel-gfx] ✓ Fi.CI.IGT: " Patchwork -- strict thread matches above, loose matches on Subject: below -- 2022-08-22 9:40 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy 2022-08-22 9:40 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 2022-08-15 17:35 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy 2022-08-15 17:35 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 2022-08-10 8:17 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy 2022-08-10 8:17 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 2022-04-11 16:25 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy 2022-04-11 16:25 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 2022-03-17 16:33 [PATCH 0/2] Add DP MST DSC support to i915 Stanislav Lisovskiy 2022-03-17 16:33 ` [PATCH 1/2] drm: Add missing DP DSC extended capability definitions Stanislav Lisovskiy 2022-03-17 16:25 Stanislav Lisovskiy
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