[PATCH 1/2] gdbstub: Set current_cpu for memory read write

* [PATCH 1/2] gdbstub: Set current_cpu for memory read write
@ 2022-03-22 15:42 Bin Meng
  2022-03-22 15:42 ` [PATCH 2/2] monitor/misc: Set current_cpu for memory dump Bin Meng
  2022-03-22 15:56 ` [PATCH 1/2] gdbstub: Set current_cpu for memory read write Peter Maydell
  0 siblings, 2 replies; 15+ messages in thread
From: Bin Meng @ 2022-03-22 15:42 UTC (permalink / raw)
  To: Alex Bennée, Philippe Mathieu-Daudé, qemu-devel

When accessing the per-CPU register bank of some devices (e.g.: GIC)
from the GDB stub context, a segfault occurs. This is due to current_cpu
is not set, as the contect is not a guest CPU.

Let's set current_cpu before doing the acutal memory read write.

Resolves: https://gitlab.com/qemu-project/qemu/-/issues/124
Signed-off-by: Bin Meng <bmeng.cn@gmail.com>
---

 gdbstub.c | 15 ++++++++++++---
 1 file changed, 12 insertions(+), 3 deletions(-)

diff --git a/gdbstub.c b/gdbstub.c
index 3c14c6a038..0b12b98fbc 100644
--- a/gdbstub.c
+++ b/gdbstub.c
@@ -66,6 +66,9 @@ static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr,
                                          uint8_t *buf, int len, bool is_write)
 {
     CPUClass *cc;
+    int ret;
+
+    current_cpu = cpu;
 
 #ifndef CONFIG_USER_ONLY
     if (phy_memory_mode) {
@@ -74,15 +77,21 @@ static inline int target_memory_rw_debug(CPUState *cpu, target_ulong addr,
         } else {
             cpu_physical_memory_read(addr, buf, len);
         }
-        return 0;
+        ret = 0;
+        goto done;
     }
 #endif
 
     cc = CPU_GET_CLASS(cpu);
     if (cc->memory_rw_debug) {
-        return cc->memory_rw_debug(cpu, addr, buf, len, is_write);
+        ret = cc->memory_rw_debug(cpu, addr, buf, len, is_write);
+        goto done;
     }
-    return cpu_memory_rw_debug(cpu, addr, buf, len, is_write);
+    ret = cpu_memory_rw_debug(cpu, addr, buf, len, is_write);
+
+done:
+    current_cpu = NULL;
+    return ret;
 }
 
 /* Return the GDB index for a given vCPU state.
-- 
2.25.1



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