* [RFC PATCH v3 0/2] HEVC enhancements
@ 2022-03-27 8:43 ` Sebastian Fricke
0 siblings, 0 replies; 12+ messages in thread
From: Sebastian Fricke @ 2022-03-27 8:43 UTC (permalink / raw)
To: linux-media
Cc: acourbot, tfiga, hverkuil-cisco, Sebastian Fricke, Maxime Ripard,
Paul Kocialkowski, Mauro Carvalho Chehab, Greg Kroah-Hartman,
Chen-Yu Tsai, Jernej Skrabec, open list:STAGING SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support,
open list:ARM/Allwinner sunXi SoC support, open list
While reading the definitions for codecs, I felt that the definition
list could be appended with the term used in HEVC. This makes the list
more complete from my point of view, but I see that this is a slippery
slope as we surely don't want to add every term from every codec (Thus
the RFC).
Secondly, I renamed the H265 identifier found in the cedrus driver to
HEVC. The idea here is mainly to align it with the other drivers like
Hantro and RkVDEC, but also with the goal of using one identifier within
the source tree (to simply searching for the term and also for less
confusion).
Changes since V1:
- Kernel test robot reported some variables that had not replaced, I
changed those.
Changes since V2:
- A few more missed replacements
Sebastian Fricke (2):
media: docs-rst: Append HEVC specific term
staging: media: cedrus: Rename H265 to HEVC
.../userspace-api/media/v4l/dev-decoder.rst | 8 +-
drivers/staging/media/sunxi/cedrus/Makefile | 2 +-
drivers/staging/media/sunxi/cedrus/cedrus.c | 30 +-
drivers/staging/media/sunxi/cedrus/cedrus.h | 14 +-
.../staging/media/sunxi/cedrus/cedrus_dec.c | 10 +-
.../cedrus/{cedrus_h265.c => cedrus_hevc.c} | 438 +++++++++---------
.../staging/media/sunxi/cedrus/cedrus_hw.c | 4 +-
.../staging/media/sunxi/cedrus/cedrus_regs.h | 394 ++++++++--------
.../staging/media/sunxi/cedrus/cedrus_video.c | 4 +-
9 files changed, 455 insertions(+), 449 deletions(-)
rename drivers/staging/media/sunxi/cedrus/{cedrus_h265.c => cedrus_hevc.c} (53%)
--
2.25.1
^ permalink raw reply [flat|nested] 12+ messages in thread
* [RFC PATCH v3 0/2] HEVC enhancements
@ 2022-03-27 8:43 ` Sebastian Fricke
0 siblings, 0 replies; 12+ messages in thread
From: Sebastian Fricke @ 2022-03-27 8:43 UTC (permalink / raw)
To: linux-media
Cc: acourbot, tfiga, hverkuil-cisco, Sebastian Fricke, Maxime Ripard,
Paul Kocialkowski, Mauro Carvalho Chehab, Greg Kroah-Hartman,
Chen-Yu Tsai, Jernej Skrabec, open list:STAGING SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support,
open list:ARM/Allwinner sunXi SoC support, open list
While reading the definitions for codecs, I felt that the definition
list could be appended with the term used in HEVC. This makes the list
more complete from my point of view, but I see that this is a slippery
slope as we surely don't want to add every term from every codec (Thus
the RFC).
Secondly, I renamed the H265 identifier found in the cedrus driver to
HEVC. The idea here is mainly to align it with the other drivers like
Hantro and RkVDEC, but also with the goal of using one identifier within
the source tree (to simply searching for the term and also for less
confusion).
Changes since V1:
- Kernel test robot reported some variables that had not replaced, I
changed those.
Changes since V2:
- A few more missed replacements
Sebastian Fricke (2):
media: docs-rst: Append HEVC specific term
staging: media: cedrus: Rename H265 to HEVC
.../userspace-api/media/v4l/dev-decoder.rst | 8 +-
drivers/staging/media/sunxi/cedrus/Makefile | 2 +-
drivers/staging/media/sunxi/cedrus/cedrus.c | 30 +-
drivers/staging/media/sunxi/cedrus/cedrus.h | 14 +-
.../staging/media/sunxi/cedrus/cedrus_dec.c | 10 +-
.../cedrus/{cedrus_h265.c => cedrus_hevc.c} | 438 +++++++++---------
.../staging/media/sunxi/cedrus/cedrus_hw.c | 4 +-
.../staging/media/sunxi/cedrus/cedrus_regs.h | 394 ++++++++--------
.../staging/media/sunxi/cedrus/cedrus_video.c | 4 +-
9 files changed, 455 insertions(+), 449 deletions(-)
rename drivers/staging/media/sunxi/cedrus/{cedrus_h265.c => cedrus_hevc.c} (53%)
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
* [RFC PATCH v3 1/2] media: docs-rst: Append HEVC specific term
2022-03-27 8:43 ` Sebastian Fricke
@ 2022-03-27 8:43 ` Sebastian Fricke
-1 siblings, 0 replies; 12+ messages in thread
From: Sebastian Fricke @ 2022-03-27 8:43 UTC (permalink / raw)
To: linux-media
Cc: acourbot, tfiga, hverkuil-cisco, Sebastian Fricke,
Mauro Carvalho Chehab, Maxime Ripard, Paul Kocialkowski,
Greg Kroah-Hartman, Chen-Yu Tsai, Jernej Skrabec, open list,
open list:STAGING SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support,
open list:ARM/Allwinner sunXi SoC support
Describe the coding tree unit as replacement for the macroblock in the
HEVC codec. Highlight a key difference of the HEVC codec to predecessors
like AVC(H.264) to give a better overview of the differences between the
coding standards.
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
---
Documentation/userspace-api/media/v4l/dev-decoder.rst | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/userspace-api/media/v4l/dev-decoder.rst b/Documentation/userspace-api/media/v4l/dev-decoder.rst
index 3cf2b496f2d0..eb5b1b1e3a51 100644
--- a/Documentation/userspace-api/media/v4l/dev-decoder.rst
+++ b/Documentation/userspace-api/media/v4l/dev-decoder.rst
@@ -72,6 +72,11 @@ coded resolution
coded width
width for given coded resolution.
+coding tree unit
+ processing unit of the HEVC codec (≘ macroblock units in H.264, VP8, VP9);
+ can use block structures of up to 64×64 pixels;
+ Good at sub-partitioning the picture into variable sized structures.
+
decode order
the order in which frames are decoded; may differ from display order if the
coded format includes a feature of frame reordering; for decoders,
@@ -104,7 +109,8 @@ keyframe
macroblock
a processing unit in image and video compression formats based on linear
block transforms (e.g. H.264, VP8, VP9); codec-specific, but for most of
- popular codecs the size is 16x16 samples (pixels).
+ popular codecs the size is 16x16 samples (pixels). The HEVC codec uses a
+ slightly more flexible processing unit called coding tree unit (CTU).
OUTPUT
the source buffer queue; for decoders, the queue of buffers containing
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [RFC PATCH v3 1/2] media: docs-rst: Append HEVC specific term
@ 2022-03-27 8:43 ` Sebastian Fricke
0 siblings, 0 replies; 12+ messages in thread
From: Sebastian Fricke @ 2022-03-27 8:43 UTC (permalink / raw)
To: linux-media
Cc: acourbot, tfiga, hverkuil-cisco, Sebastian Fricke,
Mauro Carvalho Chehab, Maxime Ripard, Paul Kocialkowski,
Greg Kroah-Hartman, Chen-Yu Tsai, Jernej Skrabec, open list,
open list:STAGING SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support,
open list:ARM/Allwinner sunXi SoC support
Describe the coding tree unit as replacement for the macroblock in the
HEVC codec. Highlight a key difference of the HEVC codec to predecessors
like AVC(H.264) to give a better overview of the differences between the
coding standards.
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
---
Documentation/userspace-api/media/v4l/dev-decoder.rst | 8 +++++++-
1 file changed, 7 insertions(+), 1 deletion(-)
diff --git a/Documentation/userspace-api/media/v4l/dev-decoder.rst b/Documentation/userspace-api/media/v4l/dev-decoder.rst
index 3cf2b496f2d0..eb5b1b1e3a51 100644
--- a/Documentation/userspace-api/media/v4l/dev-decoder.rst
+++ b/Documentation/userspace-api/media/v4l/dev-decoder.rst
@@ -72,6 +72,11 @@ coded resolution
coded width
width for given coded resolution.
+coding tree unit
+ processing unit of the HEVC codec (≘ macroblock units in H.264, VP8, VP9);
+ can use block structures of up to 64×64 pixels;
+ Good at sub-partitioning the picture into variable sized structures.
+
decode order
the order in which frames are decoded; may differ from display order if the
coded format includes a feature of frame reordering; for decoders,
@@ -104,7 +109,8 @@ keyframe
macroblock
a processing unit in image and video compression formats based on linear
block transforms (e.g. H.264, VP8, VP9); codec-specific, but for most of
- popular codecs the size is 16x16 samples (pixels).
+ popular codecs the size is 16x16 samples (pixels). The HEVC codec uses a
+ slightly more flexible processing unit called coding tree unit (CTU).
OUTPUT
the source buffer queue; for decoders, the queue of buffers containing
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [RFC PATCH v3 2/2] staging: media: cedrus: Rename H265 to HEVC
2022-03-27 8:43 ` Sebastian Fricke
@ 2022-03-27 8:43 ` Sebastian Fricke
-1 siblings, 0 replies; 12+ messages in thread
From: Sebastian Fricke @ 2022-03-27 8:43 UTC (permalink / raw)
To: linux-media
Cc: acourbot, tfiga, hverkuil-cisco, Sebastian Fricke, Maxime Ripard,
Paul Kocialkowski, Mauro Carvalho Chehab, Greg Kroah-Hartman,
Chen-Yu Tsai, Jernej Skrabec, open list:STAGING SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support,
open list:ARM/Allwinner sunXi SoC support, open list
Rename all instances where the identifier H265 is used with HEVC.
The codec has multiple identifiers H.265 (ITU-T), MPEG-H Part 2 (ISO),
but the actual name of the codec is HEVC (High Efficiency Video Coding).
Also nearly all other related drivers use the term HEVC instead of H265.
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
---
drivers/staging/media/sunxi/cedrus/Makefile | 2 +-
drivers/staging/media/sunxi/cedrus/cedrus.c | 30 +-
drivers/staging/media/sunxi/cedrus/cedrus.h | 14 +-
.../staging/media/sunxi/cedrus/cedrus_dec.c | 10 +-
.../cedrus/{cedrus_h265.c => cedrus_hevc.c} | 438 +++++++++---------
.../staging/media/sunxi/cedrus/cedrus_hw.c | 4 +-
.../staging/media/sunxi/cedrus/cedrus_regs.h | 394 ++++++++--------
.../staging/media/sunxi/cedrus/cedrus_video.c | 4 +-
8 files changed, 448 insertions(+), 448 deletions(-)
rename drivers/staging/media/sunxi/cedrus/{cedrus_h265.c => cedrus_hevc.c} (53%)
diff --git a/drivers/staging/media/sunxi/cedrus/Makefile b/drivers/staging/media/sunxi/cedrus/Makefile
index a647b3690bf8..84b1b5db3128 100644
--- a/drivers/staging/media/sunxi/cedrus/Makefile
+++ b/drivers/staging/media/sunxi/cedrus/Makefile
@@ -2,5 +2,5 @@
obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o
sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o \
- cedrus_mpeg2.o cedrus_h264.o cedrus_h265.o \
+ cedrus_mpeg2.o cedrus_h264.o cedrus_hevc.o \
cedrus_vp8.o
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
index 68b3dcdb5df3..f27cb8036a72 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
@@ -54,7 +54,7 @@ static int cedrus_try_ctrl(struct v4l2_ctrl *ctrl)
/* Luma and chroma bit depth mismatch */
return -EINVAL;
- if (ctx->dev->capabilities & CEDRUS_CAPABILITY_H265_10_DEC) {
+ if (ctx->dev->capabilities & CEDRUS_CAPABILITY_HEVC_10_DEC) {
if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
/* Only 8-bit and 10-bit are supported */
return -EINVAL;
@@ -167,25 +167,25 @@ static const struct cedrus_control cedrus_controls[] = {
.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS,
.ops = &cedrus_ctrl_ops,
},
- .codec = CEDRUS_CODEC_H265,
+ .codec = CEDRUS_CODEC_HEVC,
},
{
.cfg = {
.id = V4L2_CID_MPEG_VIDEO_HEVC_PPS,
},
- .codec = CEDRUS_CODEC_H265,
+ .codec = CEDRUS_CODEC_HEVC,
},
{
.cfg = {
.id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS,
},
- .codec = CEDRUS_CODEC_H265,
+ .codec = CEDRUS_CODEC_HEVC,
},
{
.cfg = {
.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX,
},
- .codec = CEDRUS_CODEC_H265,
+ .codec = CEDRUS_CODEC_HEVC,
},
{
.cfg = {
@@ -193,7 +193,7 @@ static const struct cedrus_control cedrus_controls[] = {
.max = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,
.def = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,
},
- .codec = CEDRUS_CODEC_H265,
+ .codec = CEDRUS_CODEC_HEVC,
},
{
.cfg = {
@@ -201,7 +201,7 @@ static const struct cedrus_control cedrus_controls[] = {
.max = V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE,
.def = V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE,
},
- .codec = CEDRUS_CODEC_H265,
+ .codec = CEDRUS_CODEC_HEVC,
},
{
.cfg = {
@@ -213,7 +213,7 @@ static const struct cedrus_control cedrus_controls[] = {
.cfg = {
.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS,
},
- .codec = CEDRUS_CODEC_H265,
+ .codec = CEDRUS_CODEC_HEVC,
},
};
@@ -434,7 +434,7 @@ static int cedrus_probe(struct platform_device *pdev)
dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2;
dev->dec_ops[CEDRUS_CODEC_H264] = &cedrus_dec_ops_h264;
- dev->dec_ops[CEDRUS_CODEC_H265] = &cedrus_dec_ops_h265;
+ dev->dec_ops[CEDRUS_CODEC_HEVC] = &cedrus_dec_ops_hevc;
dev->dec_ops[CEDRUS_CODEC_VP8] = &cedrus_dec_ops_vp8;
mutex_init(&dev->dev_mutex);
@@ -563,7 +563,7 @@ static const struct cedrus_variant sun8i_h3_cedrus_variant = {
.capabilities = CEDRUS_CAPABILITY_UNTILED |
CEDRUS_CAPABILITY_MPEG2_DEC |
CEDRUS_CAPABILITY_H264_DEC |
- CEDRUS_CAPABILITY_H265_DEC |
+ CEDRUS_CAPABILITY_HEVC_DEC |
CEDRUS_CAPABILITY_VP8_DEC,
.mod_rate = 402000000,
};
@@ -586,7 +586,7 @@ static const struct cedrus_variant sun20i_d1_cedrus_variant = {
.capabilities = CEDRUS_CAPABILITY_UNTILED |
CEDRUS_CAPABILITY_MPEG2_DEC |
CEDRUS_CAPABILITY_H264_DEC |
- CEDRUS_CAPABILITY_H265_DEC,
+ CEDRUS_CAPABILITY_HEVC_DEC,
.mod_rate = 432000000,
};
@@ -594,7 +594,7 @@ static const struct cedrus_variant sun50i_a64_cedrus_variant = {
.capabilities = CEDRUS_CAPABILITY_UNTILED |
CEDRUS_CAPABILITY_MPEG2_DEC |
CEDRUS_CAPABILITY_H264_DEC |
- CEDRUS_CAPABILITY_H265_DEC |
+ CEDRUS_CAPABILITY_HEVC_DEC |
CEDRUS_CAPABILITY_VP8_DEC,
.mod_rate = 402000000,
};
@@ -603,7 +603,7 @@ static const struct cedrus_variant sun50i_h5_cedrus_variant = {
.capabilities = CEDRUS_CAPABILITY_UNTILED |
CEDRUS_CAPABILITY_MPEG2_DEC |
CEDRUS_CAPABILITY_H264_DEC |
- CEDRUS_CAPABILITY_H265_DEC |
+ CEDRUS_CAPABILITY_HEVC_DEC |
CEDRUS_CAPABILITY_VP8_DEC,
.mod_rate = 402000000,
};
@@ -612,8 +612,8 @@ static const struct cedrus_variant sun50i_h6_cedrus_variant = {
.capabilities = CEDRUS_CAPABILITY_UNTILED |
CEDRUS_CAPABILITY_MPEG2_DEC |
CEDRUS_CAPABILITY_H264_DEC |
- CEDRUS_CAPABILITY_H265_DEC |
- CEDRUS_CAPABILITY_H265_10_DEC |
+ CEDRUS_CAPABILITY_HEVC_DEC |
+ CEDRUS_CAPABILITY_HEVC_10_DEC |
CEDRUS_CAPABILITY_VP8_DEC,
.mod_rate = 600000000,
};
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h
index 3bc094eb497f..2c260fe27325 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
@@ -29,16 +29,16 @@
#define CEDRUS_NAME "cedrus"
#define CEDRUS_CAPABILITY_UNTILED BIT(0)
-#define CEDRUS_CAPABILITY_H265_DEC BIT(1)
+#define CEDRUS_CAPABILITY_HEVC_DEC BIT(1)
#define CEDRUS_CAPABILITY_H264_DEC BIT(2)
#define CEDRUS_CAPABILITY_MPEG2_DEC BIT(3)
#define CEDRUS_CAPABILITY_VP8_DEC BIT(4)
-#define CEDRUS_CAPABILITY_H265_10_DEC BIT(5)
+#define CEDRUS_CAPABILITY_HEVC_10_DEC BIT(5)
enum cedrus_codec {
CEDRUS_CODEC_MPEG2,
CEDRUS_CODEC_H264,
- CEDRUS_CODEC_H265,
+ CEDRUS_CODEC_HEVC,
CEDRUS_CODEC_VP8,
CEDRUS_CODEC_LAST,
};
@@ -75,7 +75,7 @@ struct cedrus_mpeg2_run {
const struct v4l2_ctrl_mpeg2_quantisation *quantisation;
};
-struct cedrus_h265_run {
+struct cedrus_hevc_run {
const struct v4l2_ctrl_hevc_sps *sps;
const struct v4l2_ctrl_hevc_pps *pps;
const struct v4l2_ctrl_hevc_slice_params *slice_params;
@@ -94,7 +94,7 @@ struct cedrus_run {
union {
struct cedrus_h264_run h264;
struct cedrus_mpeg2_run mpeg2;
- struct cedrus_h265_run h265;
+ struct cedrus_hevc_run hevc;
struct cedrus_vp8_run vp8;
};
};
@@ -146,7 +146,7 @@ struct cedrus_ctx {
ssize_t mv_col_buf_unit_size;
void *neighbor_info_buf;
dma_addr_t neighbor_info_buf_addr;
- } h265;
+ } hevc;
struct {
unsigned int last_frame_p_type;
unsigned int last_filter_type;
@@ -201,7 +201,7 @@ struct cedrus_dev {
extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2;
extern struct cedrus_dec_ops cedrus_dec_ops_h264;
-extern struct cedrus_dec_ops cedrus_dec_ops_h265;
+extern struct cedrus_dec_ops cedrus_dec_ops_hevc;
extern struct cedrus_dec_ops cedrus_dec_ops_vp8;
static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c
index 9c7200299465..95f192127a50 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c
@@ -64,15 +64,15 @@ void cedrus_device_run(void *priv)
break;
case V4L2_PIX_FMT_HEVC_SLICE:
- run.h265.sps = cedrus_find_control_data(ctx,
+ run.hevc.sps = cedrus_find_control_data(ctx,
V4L2_CID_MPEG_VIDEO_HEVC_SPS);
- run.h265.pps = cedrus_find_control_data(ctx,
+ run.hevc.pps = cedrus_find_control_data(ctx,
V4L2_CID_MPEG_VIDEO_HEVC_PPS);
- run.h265.slice_params = cedrus_find_control_data(ctx,
+ run.hevc.slice_params = cedrus_find_control_data(ctx,
V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS);
- run.h265.decode_params = cedrus_find_control_data(ctx,
+ run.hevc.decode_params = cedrus_find_control_data(ctx,
V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS);
- run.h265.scaling_matrix = cedrus_find_control_data(ctx,
+ run.hevc.scaling_matrix = cedrus_find_control_data(ctx,
V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX);
break;
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_hevc.c
similarity index 53%
rename from drivers/staging/media/sunxi/cedrus/cedrus_h265.c
rename to drivers/staging/media/sunxi/cedrus/cedrus_hevc.c
index 44f385be9f6c..211410214d84 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hevc.c
@@ -21,13 +21,13 @@
* internal decoding metadata. They match the values used by the early BSP
* implementations, that were initially exposed in libvdpau-sunxi.
* Subsequent BSP implementations seem to double the neighbor info buffer size
- * for the H6 SoC, which may be related to 10 bit H265 support.
+ * for the H6 SoC, which may be related to 10 bit HEVC support.
*/
-#define CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE (794 * SZ_1K)
-#define CEDRUS_H265_ENTRY_POINTS_BUF_SIZE (4 * SZ_1K)
-#define CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE 160
+#define CEDRUS_HEVC_NEIGHBOR_INFO_BUF_SIZE (794 * SZ_1K)
+#define CEDRUS_HEVC_ENTRY_POINTS_BUF_SIZE (4 * SZ_1K)
+#define CEDRUS_HEVC_MV_COL_BUF_UNIT_CTB_SIZE 160
-struct cedrus_h265_sram_frame_info {
+struct cedrus_hevc_sram_frame_info {
__le32 top_pic_order_cnt;
__le32 bottom_pic_order_cnt;
__le32 top_mv_col_buf_addr;
@@ -36,69 +36,69 @@ struct cedrus_h265_sram_frame_info {
__le32 chroma_addr;
} __packed;
-struct cedrus_h265_sram_pred_weight {
+struct cedrus_hevc_sram_pred_weight {
__s8 delta_weight;
__s8 offset;
} __packed;
-static enum cedrus_irq_status cedrus_h265_irq_status(struct cedrus_ctx *ctx)
+static enum cedrus_irq_status cedrus_hevc_irq_status(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
u32 reg;
- reg = cedrus_read(dev, VE_DEC_H265_STATUS);
- reg &= VE_DEC_H265_STATUS_CHECK_MASK;
+ reg = cedrus_read(dev, VE_DEC_HEVC_STATUS);
+ reg &= VE_DEC_HEVC_STATUS_CHECK_MASK;
- if (reg & VE_DEC_H265_STATUS_CHECK_ERROR ||
- !(reg & VE_DEC_H265_STATUS_SUCCESS))
+ if (reg & VE_DEC_HEVC_STATUS_CHECK_ERROR ||
+ !(reg & VE_DEC_HEVC_STATUS_SUCCESS))
return CEDRUS_IRQ_ERROR;
return CEDRUS_IRQ_OK;
}
-static void cedrus_h265_irq_clear(struct cedrus_ctx *ctx)
+static void cedrus_hevc_irq_clear(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
- cedrus_write(dev, VE_DEC_H265_STATUS, VE_DEC_H265_STATUS_CHECK_MASK);
+ cedrus_write(dev, VE_DEC_HEVC_STATUS, VE_DEC_HEVC_STATUS_CHECK_MASK);
}
-static void cedrus_h265_irq_disable(struct cedrus_ctx *ctx)
+static void cedrus_hevc_irq_disable(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
- u32 reg = cedrus_read(dev, VE_DEC_H265_CTRL);
+ u32 reg = cedrus_read(dev, VE_DEC_HEVC_CTRL);
- reg &= ~VE_DEC_H265_CTRL_IRQ_MASK;
+ reg &= ~VE_DEC_HEVC_CTRL_IRQ_MASK;
- cedrus_write(dev, VE_DEC_H265_CTRL, reg);
+ cedrus_write(dev, VE_DEC_HEVC_CTRL, reg);
}
-static void cedrus_h265_sram_write_offset(struct cedrus_dev *dev, u32 offset)
+static void cedrus_hevc_sram_write_offset(struct cedrus_dev *dev, u32 offset)
{
- cedrus_write(dev, VE_DEC_H265_SRAM_OFFSET, offset);
+ cedrus_write(dev, VE_DEC_HEVC_SRAM_OFFSET, offset);
}
-static void cedrus_h265_sram_write_data(struct cedrus_dev *dev, void *data,
+static void cedrus_hevc_sram_write_data(struct cedrus_dev *dev, void *data,
unsigned int size)
{
u32 *word = data;
while (size >= sizeof(u32)) {
- cedrus_write(dev, VE_DEC_H265_SRAM_DATA, *word++);
+ cedrus_write(dev, VE_DEC_HEVC_SRAM_DATA, *word++);
size -= sizeof(u32);
}
}
static inline dma_addr_t
-cedrus_h265_frame_info_mv_col_buf_addr(struct cedrus_ctx *ctx,
+cedrus_hevc_frame_info_mv_col_buf_addr(struct cedrus_ctx *ctx,
unsigned int index, unsigned int field)
{
- return ctx->codec.h265.mv_col_buf_addr + index *
- ctx->codec.h265.mv_col_buf_unit_size +
- field * ctx->codec.h265.mv_col_buf_unit_size / 2;
+ return ctx->codec.hevc.mv_col_buf_addr + index *
+ ctx->codec.hevc.mv_col_buf_unit_size +
+ field * ctx->codec.hevc.mv_col_buf_unit_size / 2;
}
-static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx,
+static void cedrus_hevc_frame_info_write_single(struct cedrus_ctx *ctx,
unsigned int index,
bool field_pic,
u32 pic_order_cnt[],
@@ -108,31 +108,31 @@ static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx,
dma_addr_t dst_luma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 0);
dma_addr_t dst_chroma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 1);
dma_addr_t mv_col_buf_addr[2] = {
- cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, 0),
- cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index,
+ cedrus_hevc_frame_info_mv_col_buf_addr(ctx, buffer_index, 0),
+ cedrus_hevc_frame_info_mv_col_buf_addr(ctx, buffer_index,
field_pic ? 1 : 0)
};
- u32 offset = VE_DEC_H265_SRAM_OFFSET_FRAME_INFO +
- VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT * index;
- struct cedrus_h265_sram_frame_info frame_info = {
+ u32 offset = VE_DEC_HEVC_SRAM_OFFSET_FRAME_INFO +
+ VE_DEC_HEVC_SRAM_OFFSET_FRAME_INFO_UNIT * index;
+ struct cedrus_hevc_sram_frame_info frame_info = {
.top_pic_order_cnt = cpu_to_le32(pic_order_cnt[0]),
.bottom_pic_order_cnt = cpu_to_le32(field_pic ?
pic_order_cnt[1] :
pic_order_cnt[0]),
.top_mv_col_buf_addr =
- cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])),
+ cpu_to_le32(VE_DEC_HEVC_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])),
.bottom_mv_col_buf_addr = cpu_to_le32(field_pic ?
- VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[1]) :
- VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])),
- .luma_addr = cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_luma_addr)),
- .chroma_addr = cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_chroma_addr)),
+ VE_DEC_HEVC_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[1]) :
+ VE_DEC_HEVC_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])),
+ .luma_addr = cpu_to_le32(VE_DEC_HEVC_SRAM_DATA_ADDR_BASE(dst_luma_addr)),
+ .chroma_addr = cpu_to_le32(VE_DEC_HEVC_SRAM_DATA_ADDR_BASE(dst_chroma_addr)),
};
- cedrus_h265_sram_write_offset(dev, offset);
- cedrus_h265_sram_write_data(dev, &frame_info, sizeof(frame_info));
+ cedrus_hevc_sram_write_offset(dev, offset);
+ cedrus_hevc_sram_write_data(dev, &frame_info, sizeof(frame_info));
}
-static void cedrus_h265_frame_info_write_dpb(struct cedrus_ctx *ctx,
+static void cedrus_hevc_frame_info_write_dpb(struct cedrus_ctx *ctx,
const struct v4l2_hevc_dpb_entry *dpb,
u8 num_active_dpb_entries)
{
@@ -147,13 +147,13 @@ static void cedrus_h265_frame_info_write_dpb(struct cedrus_ctx *ctx,
dpb[i].pic_order_cnt[1]
};
- cedrus_h265_frame_info_write_single(ctx, i, dpb[i].field_pic,
+ cedrus_hevc_frame_info_write_single(ctx, i, dpb[i].field_pic,
pic_order_cnt,
buffer_index);
}
}
-static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev,
+static void cedrus_hevc_ref_pic_list_write(struct cedrus_dev *dev,
const struct v4l2_hevc_dpb_entry *dpb,
const u8 list[],
u8 num_ref_idx_active,
@@ -162,7 +162,7 @@ static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev,
unsigned int i;
u32 word = 0;
- cedrus_h265_sram_write_offset(dev, sram_offset);
+ cedrus_hevc_sram_write_offset(dev, sram_offset);
for (i = 0; i < num_ref_idx_active; i++) {
unsigned int shift = (i % 4) * 8;
@@ -170,20 +170,20 @@ static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev,
u8 value = list[i];
if (dpb[index].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE)
- value |= VE_DEC_H265_SRAM_REF_PIC_LIST_LT_REF;
+ value |= VE_DEC_HEVC_SRAM_REF_PIC_LIST_LT_REF;
/* Each SRAM word gathers up to 4 references. */
word |= value << shift;
/* Write the word to SRAM and clear it for the next batch. */
if ((i % 4) == 3 || i == (num_ref_idx_active - 1)) {
- cedrus_h265_sram_write_data(dev, &word, sizeof(word));
+ cedrus_hevc_sram_write_data(dev, &word, sizeof(word));
word = 0;
}
}
}
-static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev,
+static void cedrus_hevc_pred_weight_write(struct cedrus_dev *dev,
const s8 delta_luma_weight[],
const s8 luma_offset[],
const s8 delta_chroma_weight[][2],
@@ -192,10 +192,10 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev,
u32 sram_luma_offset,
u32 sram_chroma_offset)
{
- struct cedrus_h265_sram_pred_weight pred_weight[2] = { { 0 } };
+ struct cedrus_hevc_sram_pred_weight pred_weight[2] = { { 0 } };
unsigned int i, j;
- cedrus_h265_sram_write_offset(dev, sram_luma_offset);
+ cedrus_hevc_sram_write_offset(dev, sram_luma_offset);
for (i = 0; i < num_ref_idx_active; i++) {
unsigned int index = i % 2;
@@ -204,11 +204,11 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev,
pred_weight[index].offset = luma_offset[i];
if (index == 1 || i == (num_ref_idx_active - 1))
- cedrus_h265_sram_write_data(dev, (u32 *)&pred_weight,
+ cedrus_hevc_sram_write_data(dev, (u32 *)&pred_weight,
sizeof(pred_weight));
}
- cedrus_h265_sram_write_offset(dev, sram_chroma_offset);
+ cedrus_hevc_sram_write_offset(dev, sram_chroma_offset);
for (i = 0; i < num_ref_idx_active; i++) {
for (j = 0; j < 2; j++) {
@@ -216,50 +216,50 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev,
pred_weight[j].offset = chroma_offset[i][j];
}
- cedrus_h265_sram_write_data(dev, &pred_weight,
+ cedrus_hevc_sram_write_data(dev, &pred_weight,
sizeof(pred_weight));
}
}
-static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num)
+static void cedrus_hevc_skip_bits(struct cedrus_dev *dev, int num)
{
int count = 0;
while (count < num) {
int tmp = min(num - count, 32);
- cedrus_write(dev, VE_DEC_H265_TRIGGER,
- VE_DEC_H265_TRIGGER_FLUSH_BITS |
- VE_DEC_H265_TRIGGER_TYPE_N_BITS(tmp));
- while (cedrus_read(dev, VE_DEC_H265_STATUS) & VE_DEC_H265_STATUS_VLD_BUSY)
+ cedrus_write(dev, VE_DEC_HEVC_TRIGGER,
+ VE_DEC_HEVC_TRIGGER_FLUSH_BITS |
+ VE_DEC_HEVC_TRIGGER_TYPE_N_BITS(tmp));
+ while (cedrus_read(dev, VE_DEC_HEVC_STATUS) & VE_DEC_HEVC_STATUS_VLD_BUSY)
udelay(1);
count += tmp;
}
}
-static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
+static void cedrus_hevc_write_scaling_list(struct cedrus_ctx *ctx,
struct cedrus_run *run)
{
const struct v4l2_ctrl_hevc_scaling_matrix *scaling;
struct cedrus_dev *dev = ctx->dev;
u32 i, j, k, val;
- scaling = run->h265.scaling_matrix;
+ scaling = run->hevc.scaling_matrix;
- cedrus_write(dev, VE_DEC_H265_SCALING_LIST_DC_COEF0,
+ cedrus_write(dev, VE_DEC_HEVC_SCALING_LIST_DC_COEF0,
(scaling->scaling_list_dc_coef_32x32[1] << 24) |
(scaling->scaling_list_dc_coef_32x32[0] << 16) |
(scaling->scaling_list_dc_coef_16x16[1] << 8) |
(scaling->scaling_list_dc_coef_16x16[0] << 0));
- cedrus_write(dev, VE_DEC_H265_SCALING_LIST_DC_COEF1,
+ cedrus_write(dev, VE_DEC_HEVC_SCALING_LIST_DC_COEF1,
(scaling->scaling_list_dc_coef_16x16[5] << 24) |
(scaling->scaling_list_dc_coef_16x16[4] << 16) |
(scaling->scaling_list_dc_coef_16x16[3] << 8) |
(scaling->scaling_list_dc_coef_16x16[2] << 0));
- cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS);
+ cedrus_hevc_sram_write_offset(dev, VE_DEC_HEVC_SRAM_OFFSET_SCALING_LISTS);
for (i = 0; i < 6; i++)
for (j = 0; j < 8; j++)
@@ -268,7 +268,7 @@ static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
((u32)scaling->scaling_list_8x8[i][j + (k + 2) * 8] << 16) |
((u32)scaling->scaling_list_8x8[i][j + (k + 1) * 8] << 8) |
scaling->scaling_list_8x8[i][j + k * 8];
- cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val);
+ cedrus_write(dev, VE_DEC_HEVC_SRAM_DATA, val);
}
for (i = 0; i < 2; i++)
@@ -278,7 +278,7 @@ static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
((u32)scaling->scaling_list_32x32[i][j + (k + 2) * 8] << 16) |
((u32)scaling->scaling_list_32x32[i][j + (k + 1) * 8] << 8) |
scaling->scaling_list_32x32[i][j + k * 8];
- cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val);
+ cedrus_write(dev, VE_DEC_HEVC_SRAM_DATA, val);
}
for (i = 0; i < 6; i++)
@@ -288,7 +288,7 @@ static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
((u32)scaling->scaling_list_16x16[i][j + (k + 2) * 8] << 16) |
((u32)scaling->scaling_list_16x16[i][j + (k + 1) * 8] << 8) |
scaling->scaling_list_16x16[i][j + k * 8];
- cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val);
+ cedrus_write(dev, VE_DEC_HEVC_SRAM_DATA, val);
}
for (i = 0; i < 6; i++)
@@ -297,11 +297,11 @@ static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
((u32)scaling->scaling_list_4x4[i][j + 8] << 16) |
((u32)scaling->scaling_list_4x4[i][j + 4] << 8) |
scaling->scaling_list_4x4[i][j];
- cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val);
+ cedrus_write(dev, VE_DEC_HEVC_SRAM_DATA, val);
}
}
-static void cedrus_h265_setup(struct cedrus_ctx *ctx,
+static void cedrus_hevc_setup(struct cedrus_ctx *ctx,
struct cedrus_run *run)
{
struct cedrus_dev *dev = ctx->dev;
@@ -319,10 +319,10 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
u32 pic_order_cnt[2];
u32 reg;
- sps = run->h265.sps;
- pps = run->h265.pps;
- slice_params = run->h265.slice_params;
- decode_params = run->h265.decode_params;
+ sps = run->hevc.sps;
+ pps = run->hevc.pps;
+ slice_params = run->hevc.slice_params;
+ decode_params = run->hevc.decode_params;
pred_weight_table = &slice_params->pred_weight_table;
log2_max_luma_coding_block_size =
@@ -333,7 +333,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma);
/* MV column buffer size and allocation. */
- if (!ctx->codec.h265.mv_col_buf_size) {
+ if (!ctx->codec.hevc.mv_col_buf_size) {
unsigned int num_buffers =
run->dst->vb2_buf.vb2_queue->num_buffers;
@@ -342,269 +342,269 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
* Since the address is given with missing lsb bits, 1 KiB is
* added to each buffer to ensure proper alignment.
*/
- ctx->codec.h265.mv_col_buf_unit_size =
+ ctx->codec.hevc.mv_col_buf_unit_size =
DIV_ROUND_UP(ctx->src_fmt.width, ctb_size_luma) *
DIV_ROUND_UP(ctx->src_fmt.height, ctb_size_luma) *
- CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE + SZ_1K;
+ CEDRUS_HEVC_MV_COL_BUF_UNIT_CTB_SIZE + SZ_1K;
- ctx->codec.h265.mv_col_buf_size = num_buffers *
- ctx->codec.h265.mv_col_buf_unit_size;
+ ctx->codec.hevc.mv_col_buf_size = num_buffers *
+ ctx->codec.hevc.mv_col_buf_unit_size;
/* Buffer is never accessed by CPU, so we can skip kernel mapping. */
- ctx->codec.h265.mv_col_buf =
+ ctx->codec.hevc.mv_col_buf =
dma_alloc_attrs(dev->dev,
- ctx->codec.h265.mv_col_buf_size,
- &ctx->codec.h265.mv_col_buf_addr,
+ ctx->codec.hevc.mv_col_buf_size,
+ &ctx->codec.hevc.mv_col_buf_addr,
GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
- if (!ctx->codec.h265.mv_col_buf) {
- ctx->codec.h265.mv_col_buf_size = 0;
+ if (!ctx->codec.hevc.mv_col_buf) {
+ ctx->codec.hevc.mv_col_buf_size = 0;
// TODO: Abort the process here.
return;
}
}
- /* Activate H265 engine. */
- cedrus_engine_enable(ctx, CEDRUS_CODEC_H265);
+ /* Activate HEVC engine. */
+ cedrus_engine_enable(ctx, CEDRUS_CODEC_HEVC);
/* Source offset and length in bits. */
- cedrus_write(dev, VE_DEC_H265_BITS_OFFSET, 0);
+ cedrus_write(dev, VE_DEC_HEVC_BITS_OFFSET, 0);
reg = slice_params->bit_size;
- cedrus_write(dev, VE_DEC_H265_BITS_LEN, reg);
+ cedrus_write(dev, VE_DEC_HEVC_BITS_LEN, reg);
/* Source beginning and end addresses. */
src_buf_addr = vb2_dma_contig_plane_dma_addr(&run->src->vb2_buf, 0);
- reg = VE_DEC_H265_BITS_ADDR_BASE(src_buf_addr);
- reg |= VE_DEC_H265_BITS_ADDR_VALID_SLICE_DATA;
- reg |= VE_DEC_H265_BITS_ADDR_LAST_SLICE_DATA;
- reg |= VE_DEC_H265_BITS_ADDR_FIRST_SLICE_DATA;
+ reg = VE_DEC_HEVC_BITS_ADDR_BASE(src_buf_addr);
+ reg |= VE_DEC_HEVC_BITS_ADDR_VALID_SLICE_DATA;
+ reg |= VE_DEC_HEVC_BITS_ADDR_LAST_SLICE_DATA;
+ reg |= VE_DEC_HEVC_BITS_ADDR_FIRST_SLICE_DATA;
- cedrus_write(dev, VE_DEC_H265_BITS_ADDR, reg);
+ cedrus_write(dev, VE_DEC_HEVC_BITS_ADDR, reg);
src_buf_end_addr = src_buf_addr +
DIV_ROUND_UP(slice_params->bit_size, 8);
- reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr);
- cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg);
+ reg = VE_DEC_HEVC_BITS_END_ADDR_BASE(src_buf_end_addr);
+ cedrus_write(dev, VE_DEC_HEVC_BITS_END_ADDR, reg);
/* Coding tree block address */
- reg = VE_DEC_H265_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma);
- reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma);
- cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg);
+ reg = VE_DEC_HEVC_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma);
+ reg |= VE_DEC_HEVC_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_CTB_ADDR, reg);
- cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0);
- cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0);
+ cedrus_write(dev, VE_DEC_HEVC_TILE_START_CTB, 0);
+ cedrus_write(dev, VE_DEC_HEVC_TILE_END_CTB, 0);
/* Clear the number of correctly-decoded coding tree blocks. */
if (ctx->fh.m2m_ctx->new_frame)
- cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_CTB_NUM, 0);
/* Initialize bitstream access. */
- cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC);
+ cedrus_write(dev, VE_DEC_HEVC_TRIGGER, VE_DEC_HEVC_TRIGGER_INIT_SWDEC);
- cedrus_h265_skip_bits(dev, slice_params->data_bit_offset);
+ cedrus_hevc_skip_bits(dev, slice_params->data_bit_offset);
/* Bitstream parameters. */
- reg = VE_DEC_H265_DEC_NAL_HDR_NAL_UNIT_TYPE(slice_params->nal_unit_type) |
- VE_DEC_H265_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(slice_params->nuh_temporal_id_plus1);
+ reg = VE_DEC_HEVC_DEC_NAL_HDR_NAL_UNIT_TYPE(slice_params->nal_unit_type) |
+ VE_DEC_HEVC_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(slice_params->nuh_temporal_id_plus1);
- cedrus_write(dev, VE_DEC_H265_DEC_NAL_HDR, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_NAL_HDR, reg);
/* SPS. */
- reg = VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(sps->max_transform_hierarchy_depth_intra) |
- VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(sps->max_transform_hierarchy_depth_inter) |
- VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(sps->log2_diff_max_min_luma_transform_block_size) |
- VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(sps->log2_min_luma_transform_block_size_minus2) |
- VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_luma_coding_block_size) |
- VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_luma_coding_block_size_minus3) |
- VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(sps->bit_depth_chroma_minus8) |
- VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(sps->bit_depth_luma_minus8) |
- VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(sps->chroma_format_idc);
-
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_STRONG_INTRA_SMOOTHING_ENABLE,
+ reg = VE_DEC_HEVC_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(sps->max_transform_hierarchy_depth_intra) |
+ VE_DEC_HEVC_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(sps->max_transform_hierarchy_depth_inter) |
+ VE_DEC_HEVC_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(sps->log2_diff_max_min_luma_transform_block_size) |
+ VE_DEC_HEVC_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(sps->log2_min_luma_transform_block_size_minus2) |
+ VE_DEC_HEVC_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_luma_coding_block_size) |
+ VE_DEC_HEVC_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_luma_coding_block_size_minus3) |
+ VE_DEC_HEVC_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(sps->bit_depth_chroma_minus8) |
+ VE_DEC_HEVC_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(sps->bit_depth_luma_minus8) |
+ VE_DEC_HEVC_DEC_SPS_HDR_CHROMA_FORMAT_IDC(sps->chroma_format_idc);
+
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SPS_HDR_FLAG_STRONG_INTRA_SMOOTHING_ENABLE,
V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED,
sps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SPS_TEMPORAL_MVP_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SPS_HDR_FLAG_SPS_TEMPORAL_MVP_ENABLED,
V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED,
sps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SAMPLE_ADAPTIVE_OFFSET_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SPS_HDR_FLAG_SAMPLE_ADAPTIVE_OFFSET_ENABLED,
V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET,
sps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_AMP_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SPS_HDR_FLAG_AMP_ENABLED,
V4L2_HEVC_SPS_FLAG_AMP_ENABLED, sps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SEPARATE_COLOUR_PLANE,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SPS_HDR_FLAG_SEPARATE_COLOUR_PLANE,
V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE,
sps->flags);
- cedrus_write(dev, VE_DEC_H265_DEC_SPS_HDR, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_SPS_HDR, reg);
- reg = VE_DEC_H265_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_pcm_luma_coding_block_size) |
- VE_DEC_H265_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_pcm_luma_coding_block_size_minus3) |
- VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(sps->pcm_sample_bit_depth_chroma_minus1) |
- VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(sps->pcm_sample_bit_depth_luma_minus1);
+ reg = VE_DEC_HEVC_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_pcm_luma_coding_block_size) |
+ VE_DEC_HEVC_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_pcm_luma_coding_block_size_minus3) |
+ VE_DEC_HEVC_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(sps->pcm_sample_bit_depth_chroma_minus1) |
+ VE_DEC_HEVC_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(sps->pcm_sample_bit_depth_luma_minus1);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PCM_CTRL_FLAG_PCM_ENABLED,
V4L2_HEVC_SPS_FLAG_PCM_ENABLED, sps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_LOOP_FILTER_DISABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PCM_CTRL_FLAG_PCM_LOOP_FILTER_DISABLED,
V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED,
sps->flags);
- cedrus_write(dev, VE_DEC_H265_DEC_PCM_CTRL, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_PCM_CTRL, reg);
/* PPS. */
- reg = VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) |
- VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(pps->pps_cb_qp_offset) |
- VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(pps->init_qp_minus26) |
- VE_DEC_H265_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(pps->diff_cu_qp_delta_depth);
+ reg = VE_DEC_HEVC_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) |
+ VE_DEC_HEVC_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(pps->pps_cb_qp_offset) |
+ VE_DEC_HEVC_DEC_PPS_CTRL0_INIT_QP_MINUS26(pps->init_qp_minus26) |
+ VE_DEC_HEVC_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(pps->diff_cu_qp_delta_depth);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CU_QP_DELTA_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_CU_QP_DELTA_ENABLED,
V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED,
pps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_TRANSFORM_SKIP_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_TRANSFORM_SKIP_ENABLED,
V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED,
pps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CONSTRAINED_INTRA_PRED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_CONSTRAINED_INTRA_PRED,
V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED,
pps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_SIGN_DATA_HIDING_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_SIGN_DATA_HIDING_ENABLED,
V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED,
pps->flags);
- cedrus_write(dev, VE_DEC_H265_DEC_PPS_CTRL0, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_PPS_CTRL0, reg);
- reg = VE_DEC_H265_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(pps->log2_parallel_merge_level_minus2);
+ reg = VE_DEC_HEVC_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(pps->log2_parallel_merge_level_minus2);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED,
V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED,
pps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED,
V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED,
pps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_ENTROPY_CODING_SYNC_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_ENTROPY_CODING_SYNC_ENABLED,
V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED,
pps->flags);
- /* TODO: VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED */
+ /* TODO: VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_TILES_ENABLED */
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED,
V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED,
pps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_BIPRED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_WEIGHTED_BIPRED,
V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED, pps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_PRED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_WEIGHTED_PRED,
V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED, pps->flags);
- cedrus_write(dev, VE_DEC_H265_DEC_PPS_CTRL1, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_PPS_CTRL1, reg);
/* Slice Parameters. */
- reg = VE_DEC_H265_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(slice_params->pic_struct) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(slice_params->five_minus_max_num_merge_cand) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(slice_params->num_ref_idx_l1_active_minus1) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(slice_params->num_ref_idx_l0_active_minus1) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(slice_params->collocated_ref_idx) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(slice_params->colour_plane_id) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(slice_params->slice_type);
+ reg = VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(slice_params->pic_struct) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(slice_params->five_minus_max_num_merge_cand) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(slice_params->num_ref_idx_l1_active_minus1) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(slice_params->num_ref_idx_l0_active_minus1) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(slice_params->collocated_ref_idx) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(slice_params->colour_plane_id) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_SLICE_TYPE(slice_params->slice_type);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_COLLOCATED_FROM_L0,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_COLLOCATED_FROM_L0,
V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0,
slice_params->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_CABAC_INIT,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_CABAC_INIT,
V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT,
slice_params->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_MVD_L1_ZERO,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_MVD_L1_ZERO,
V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO,
slice_params->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_CHROMA,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_CHROMA,
V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA,
slice_params->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_LUMA,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_LUMA,
V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA,
slice_params->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_TEMPORAL_MVP_ENABLE,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_SLICE_TEMPORAL_MVP_ENABLE,
V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED,
slice_params->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT,
V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT,
slice_params->flags);
if (ctx->fh.m2m_ctx->new_frame)
- reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC;
+ reg |= VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC;
- cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO0, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_SLICE_HDR_INFO0, reg);
- reg = VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(slice_params->slice_tc_offset_div2) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(slice_params->slice_beta_offset_div2) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(decode_params->num_poc_st_curr_after == 0) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(slice_params->slice_cr_qp_offset) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(slice_params->slice_cb_qp_offset) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(slice_params->slice_qp_delta);
+ reg = VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(slice_params->slice_tc_offset_div2) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(slice_params->slice_beta_offset_div2) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(decode_params->num_poc_st_curr_after == 0) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(slice_params->slice_cr_qp_offset) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(slice_params->slice_cb_qp_offset) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(slice_params->slice_qp_delta);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED,
V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED,
slice_params->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED,
V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED,
slice_params->flags);
- cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO1, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_SLICE_HDR_INFO1, reg);
chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom +
pred_weight_table->delta_chroma_log2_weight_denom;
- reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(0) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(chroma_log2_weight_denom) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(pred_weight_table->luma_log2_weight_denom);
+ reg = VE_DEC_HEVC_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(0) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(chroma_log2_weight_denom) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(pred_weight_table->luma_log2_weight_denom);
- cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO2, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_SLICE_HDR_INFO2, reg);
/* Decoded picture size. */
- reg = VE_DEC_H265_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) |
- VE_DEC_H265_DEC_PIC_SIZE_HEIGHT(ctx->src_fmt.height);
+ reg = VE_DEC_HEVC_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) |
+ VE_DEC_HEVC_DEC_PIC_SIZE_HEIGHT(ctx->src_fmt.height);
- cedrus_write(dev, VE_DEC_H265_DEC_PIC_SIZE, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_PIC_SIZE, reg);
/* Scaling list. */
if (sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED) {
- cedrus_h265_write_scaling_list(ctx, run);
- reg = VE_DEC_H265_SCALING_LIST_CTRL0_FLAG_ENABLED;
+ cedrus_hevc_write_scaling_list(ctx, run);
+ reg = VE_DEC_HEVC_SCALING_LIST_CTRL0_FLAG_ENABLED;
} else {
- reg = VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT;
+ reg = VE_DEC_HEVC_SCALING_LIST_CTRL0_DEFAULT;
}
- cedrus_write(dev, VE_DEC_H265_SCALING_LIST_CTRL0, reg);
+ cedrus_write(dev, VE_DEC_HEVC_SCALING_LIST_CTRL0, reg);
/* Neightbor information address. */
- reg = VE_DEC_H265_NEIGHBOR_INFO_ADDR_BASE(ctx->codec.h265.neighbor_info_buf_addr);
- cedrus_write(dev, VE_DEC_H265_NEIGHBOR_INFO_ADDR, reg);
+ reg = VE_DEC_HEVC_NEIGHBOR_INFO_ADDR_BASE(ctx->codec.hevc.neighbor_info_buf_addr);
+ cedrus_write(dev, VE_DEC_HEVC_NEIGHBOR_INFO_ADDR, reg);
/* Write decoded picture buffer in pic list. */
- cedrus_h265_frame_info_write_dpb(ctx, decode_params->dpb,
+ cedrus_hevc_frame_info_write_dpb(ctx, decode_params->dpb,
decode_params->num_active_dpb_entries);
/* Output frame. */
@@ -613,104 +613,104 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
pic_order_cnt[0] = slice_params->slice_pic_order_cnt;
pic_order_cnt[1] = slice_params->slice_pic_order_cnt;
- cedrus_h265_frame_info_write_single(ctx, output_pic_list_index,
+ cedrus_hevc_frame_info_write_single(ctx, output_pic_list_index,
slice_params->pic_struct != 0,
pic_order_cnt,
run->dst->vb2_buf.index);
- cedrus_write(dev, VE_DEC_H265_OUTPUT_FRAME_IDX, output_pic_list_index);
+ cedrus_write(dev, VE_DEC_HEVC_OUTPUT_FRAME_IDX, output_pic_list_index);
/* Reference picture list 0 (for P/B frames). */
if (slice_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) {
- cedrus_h265_ref_pic_list_write(dev, decode_params->dpb,
+ cedrus_hevc_ref_pic_list_write(dev, decode_params->dpb,
slice_params->ref_idx_l0,
slice_params->num_ref_idx_l0_active_minus1 + 1,
- VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0);
+ VE_DEC_HEVC_SRAM_OFFSET_REF_PIC_LIST0);
if ((pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED) ||
(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED))
- cedrus_h265_pred_weight_write(dev,
+ cedrus_hevc_pred_weight_write(dev,
pred_weight_table->delta_luma_weight_l0,
pred_weight_table->luma_offset_l0,
pred_weight_table->delta_chroma_weight_l0,
pred_weight_table->chroma_offset_l0,
slice_params->num_ref_idx_l0_active_minus1 + 1,
- VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0,
- VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0);
+ VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0,
+ VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0);
}
/* Reference picture list 1 (for B frames). */
if (slice_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) {
- cedrus_h265_ref_pic_list_write(dev, decode_params->dpb,
+ cedrus_hevc_ref_pic_list_write(dev, decode_params->dpb,
slice_params->ref_idx_l1,
slice_params->num_ref_idx_l1_active_minus1 + 1,
- VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1);
+ VE_DEC_HEVC_SRAM_OFFSET_REF_PIC_LIST1);
if (pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED)
- cedrus_h265_pred_weight_write(dev,
+ cedrus_hevc_pred_weight_write(dev,
pred_weight_table->delta_luma_weight_l1,
pred_weight_table->luma_offset_l1,
pred_weight_table->delta_chroma_weight_l1,
pred_weight_table->chroma_offset_l1,
slice_params->num_ref_idx_l1_active_minus1 + 1,
- VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1,
- VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1);
+ VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1,
+ VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1);
}
/* Enable appropriate interruptions. */
- cedrus_write(dev, VE_DEC_H265_CTRL, VE_DEC_H265_CTRL_IRQ_MASK);
+ cedrus_write(dev, VE_DEC_HEVC_CTRL, VE_DEC_HEVC_CTRL_IRQ_MASK);
}
-static int cedrus_h265_start(struct cedrus_ctx *ctx)
+static int cedrus_hevc_start(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
/* The buffer size is calculated at setup time. */
- ctx->codec.h265.mv_col_buf_size = 0;
+ ctx->codec.hevc.mv_col_buf_size = 0;
/* Buffer is never accessed by CPU, so we can skip kernel mapping. */
- ctx->codec.h265.neighbor_info_buf =
- dma_alloc_attrs(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE,
- &ctx->codec.h265.neighbor_info_buf_addr,
+ ctx->codec.hevc.neighbor_info_buf =
+ dma_alloc_attrs(dev->dev, CEDRUS_HEVC_NEIGHBOR_INFO_BUF_SIZE,
+ &ctx->codec.hevc.neighbor_info_buf_addr,
GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
- if (!ctx->codec.h265.neighbor_info_buf)
+ if (!ctx->codec.hevc.neighbor_info_buf)
return -ENOMEM;
return 0;
}
-static void cedrus_h265_stop(struct cedrus_ctx *ctx)
+static void cedrus_hevc_stop(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
- if (ctx->codec.h265.mv_col_buf_size > 0) {
- dma_free_attrs(dev->dev, ctx->codec.h265.mv_col_buf_size,
- ctx->codec.h265.mv_col_buf,
- ctx->codec.h265.mv_col_buf_addr,
+ if (ctx->codec.hevc.mv_col_buf_size > 0) {
+ dma_free_attrs(dev->dev, ctx->codec.hevc.mv_col_buf_size,
+ ctx->codec.hevc.mv_col_buf,
+ ctx->codec.hevc.mv_col_buf_addr,
DMA_ATTR_NO_KERNEL_MAPPING);
- ctx->codec.h265.mv_col_buf_size = 0;
+ ctx->codec.hevc.mv_col_buf_size = 0;
}
- dma_free_attrs(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE,
- ctx->codec.h265.neighbor_info_buf,
- ctx->codec.h265.neighbor_info_buf_addr,
+ dma_free_attrs(dev->dev, CEDRUS_HEVC_NEIGHBOR_INFO_BUF_SIZE,
+ ctx->codec.hevc.neighbor_info_buf,
+ ctx->codec.hevc.neighbor_info_buf_addr,
DMA_ATTR_NO_KERNEL_MAPPING);
}
-static void cedrus_h265_trigger(struct cedrus_ctx *ctx)
+static void cedrus_hevc_trigger(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
- cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_DEC_SLICE);
+ cedrus_write(dev, VE_DEC_HEVC_TRIGGER, VE_DEC_HEVC_TRIGGER_DEC_SLICE);
}
-struct cedrus_dec_ops cedrus_dec_ops_h265 = {
- .irq_clear = cedrus_h265_irq_clear,
- .irq_disable = cedrus_h265_irq_disable,
- .irq_status = cedrus_h265_irq_status,
- .setup = cedrus_h265_setup,
- .start = cedrus_h265_start,
- .stop = cedrus_h265_stop,
- .trigger = cedrus_h265_trigger,
+struct cedrus_dec_ops cedrus_dec_ops_hevc = {
+ .irq_clear = cedrus_hevc_irq_clear,
+ .irq_disable = cedrus_hevc_irq_disable,
+ .irq_status = cedrus_hevc_irq_status,
+ .setup = cedrus_hevc_setup,
+ .start = cedrus_hevc_start,
+ .stop = cedrus_hevc_stop,
+ .trigger = cedrus_hevc_trigger,
};
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
index a6470a89851e..4697a1ec4592 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
@@ -53,8 +53,8 @@ int cedrus_engine_enable(struct cedrus_ctx *ctx, enum cedrus_codec codec)
reg |= VE_MODE_DEC_H264;
break;
- case CEDRUS_CODEC_H265:
- reg |= VE_MODE_DEC_H265;
+ case CEDRUS_CODEC_HEVC:
+ reg |= VE_MODE_DEC_HEVC;
break;
default:
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
index bdb062ad8682..402d5f7af3c1 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
@@ -31,7 +31,7 @@
#define VE_ENGINE_DEC_MPEG 0x100
#define VE_ENGINE_DEC_H264 0x200
-#define VE_ENGINE_DEC_H265 0x500
+#define VE_ENGINE_DEC_HEVC 0x500
#define VE_MODE 0x00
@@ -42,7 +42,7 @@
#define VE_MODE_DDR_MODE_BW_128 (0x03 << 16)
#define VE_MODE_DDR_MODE_BW_256 (0x02 << 16)
#define VE_MODE_DISABLED (0x07 << 0)
-#define VE_MODE_DEC_H265 (0x04 << 0)
+#define VE_MODE_DEC_HEVC (0x04 << 0)
#define VE_MODE_DEC_H264 (0x01 << 0)
#define VE_MODE_DEC_MPEG (0x00 << 0)
@@ -255,273 +255,273 @@
#define VE_DEC_MPEG_ROT_LUMA (VE_ENGINE_DEC_MPEG + 0xcc)
#define VE_DEC_MPEG_ROT_CHROMA (VE_ENGINE_DEC_MPEG + 0xd0)
-#define VE_DEC_H265_DEC_NAL_HDR (VE_ENGINE_DEC_H265 + 0x00)
+#define VE_DEC_HEVC_DEC_NAL_HDR (VE_ENGINE_DEC_HEVC + 0x00)
-#define VE_DEC_H265_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(v) \
+#define VE_DEC_HEVC_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(v) \
SHIFT_AND_MASK_BITS(v, 8, 6)
-#define VE_DEC_H265_DEC_NAL_HDR_NAL_UNIT_TYPE(v) \
+#define VE_DEC_HEVC_DEC_NAL_HDR_NAL_UNIT_TYPE(v) \
SHIFT_AND_MASK_BITS(v, 5, 0)
-#define VE_DEC_H265_FLAG(reg_flag, ctrl_flag, flags) \
+#define VE_DEC_HEVC_FLAG(reg_flag, ctrl_flag, flags) \
(((flags) & (ctrl_flag)) ? reg_flag : 0)
-#define VE_DEC_H265_DEC_SPS_HDR (VE_ENGINE_DEC_H265 + 0x04)
+#define VE_DEC_HEVC_DEC_SPS_HDR (VE_ENGINE_DEC_HEVC + 0x04)
-#define VE_DEC_H265_DEC_SPS_HDR_FLAG_STRONG_INTRA_SMOOTHING_ENABLE BIT(26)
-#define VE_DEC_H265_DEC_SPS_HDR_FLAG_SPS_TEMPORAL_MVP_ENABLED BIT(25)
-#define VE_DEC_H265_DEC_SPS_HDR_FLAG_SAMPLE_ADAPTIVE_OFFSET_ENABLED BIT(24)
-#define VE_DEC_H265_DEC_SPS_HDR_FLAG_AMP_ENABLED BIT(23)
-#define VE_DEC_H265_DEC_SPS_HDR_FLAG_SEPARATE_COLOUR_PLANE BIT(2)
+#define VE_DEC_HEVC_DEC_SPS_HDR_FLAG_STRONG_INTRA_SMOOTHING_ENABLE BIT(26)
+#define VE_DEC_HEVC_DEC_SPS_HDR_FLAG_SPS_TEMPORAL_MVP_ENABLED BIT(25)
+#define VE_DEC_HEVC_DEC_SPS_HDR_FLAG_SAMPLE_ADAPTIVE_OFFSET_ENABLED BIT(24)
+#define VE_DEC_HEVC_DEC_SPS_HDR_FLAG_AMP_ENABLED BIT(23)
+#define VE_DEC_HEVC_DEC_SPS_HDR_FLAG_SEPARATE_COLOUR_PLANE BIT(2)
-#define VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(v) \
SHIFT_AND_MASK_BITS(v, 22, 20)
-#define VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(v) \
SHIFT_AND_MASK_BITS(v, 19, 17)
-#define VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(v) \
SHIFT_AND_MASK_BITS(v, 16, 15)
-#define VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(v) \
SHIFT_AND_MASK_BITS(v, 14, 13)
-#define VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(v) \
SHIFT_AND_MASK_BITS(v, 12, 11)
-#define VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \
SHIFT_AND_MASK_BITS(v, 10, 9)
-#define VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(v) \
SHIFT_AND_MASK_BITS(v, 8, 6)
-#define VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(v) \
SHIFT_AND_MASK_BITS(v, 5, 3)
-#define VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_CHROMA_FORMAT_IDC(v) \
SHIFT_AND_MASK_BITS(v, 1, 0)
-#define VE_DEC_H265_DEC_PIC_SIZE (VE_ENGINE_DEC_H265 + 0x08)
+#define VE_DEC_HEVC_DEC_PIC_SIZE (VE_ENGINE_DEC_HEVC + 0x08)
-#define VE_DEC_H265_DEC_PIC_SIZE_WIDTH(w) (((w) << 0) & GENMASK(13, 0))
-#define VE_DEC_H265_DEC_PIC_SIZE_HEIGHT(h) (((h) << 16) & GENMASK(29, 16))
+#define VE_DEC_HEVC_DEC_PIC_SIZE_WIDTH(w) (((w) << 0) & GENMASK(13, 0))
+#define VE_DEC_HEVC_DEC_PIC_SIZE_HEIGHT(h) (((h) << 16) & GENMASK(29, 16))
-#define VE_DEC_H265_DEC_PCM_CTRL (VE_ENGINE_DEC_H265 + 0x0c)
+#define VE_DEC_HEVC_DEC_PCM_CTRL (VE_ENGINE_DEC_HEVC + 0x0c)
-#define VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_ENABLED BIT(15)
-#define VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_LOOP_FILTER_DISABLED BIT(14)
+#define VE_DEC_HEVC_DEC_PCM_CTRL_FLAG_PCM_ENABLED BIT(15)
+#define VE_DEC_HEVC_DEC_PCM_CTRL_FLAG_PCM_LOOP_FILTER_DISABLED BIT(14)
-#define VE_DEC_H265_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(v) \
+#define VE_DEC_HEVC_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(v) \
SHIFT_AND_MASK_BITS(v, 11, 10)
-#define VE_DEC_H265_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \
+#define VE_DEC_HEVC_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \
SHIFT_AND_MASK_BITS(v, 9, 8)
-#define VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(v) \
+#define VE_DEC_HEVC_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(v) \
SHIFT_AND_MASK_BITS(v, 7, 4)
-#define VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(v) \
+#define VE_DEC_HEVC_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(v) \
SHIFT_AND_MASK_BITS(v, 3, 0)
-#define VE_DEC_H265_DEC_PPS_CTRL0 (VE_ENGINE_DEC_H265 + 0x10)
+#define VE_DEC_HEVC_DEC_PPS_CTRL0 (VE_ENGINE_DEC_HEVC + 0x10)
-#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CU_QP_DELTA_ENABLED BIT(3)
-#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_TRANSFORM_SKIP_ENABLED BIT(2)
-#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CONSTRAINED_INTRA_PRED BIT(1)
-#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_SIGN_DATA_HIDING_ENABLED BIT(0)
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_CU_QP_DELTA_ENABLED BIT(3)
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_TRANSFORM_SKIP_ENABLED BIT(2)
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_CONSTRAINED_INTRA_PRED BIT(1)
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_SIGN_DATA_HIDING_ENABLED BIT(0)
-#define VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(v) \
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(v) \
SHIFT_AND_MASK_BITS(v, 29, 24)
-#define VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(v) \
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(v) \
SHIFT_AND_MASK_BITS(v, 21, 16)
-#define VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(v) \
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_INIT_QP_MINUS26(v) \
SHIFT_AND_MASK_BITS(v, 14, 8)
-#define VE_DEC_H265_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(v) \
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(v) \
SHIFT_AND_MASK_BITS(v, 5, 4)
-#define VE_DEC_H265_DEC_PPS_CTRL1 (VE_ENGINE_DEC_H265 + 0x14)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1 (VE_ENGINE_DEC_HEVC + 0x14)
-#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED BIT(6)
-#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED BIT(5)
-#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_ENTROPY_CODING_SYNC_ENABLED BIT(4)
-#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED BIT(3)
-#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED BIT(2)
-#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_BIPRED BIT(1)
-#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_PRED BIT(0)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED BIT(6)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED BIT(5)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_ENTROPY_CODING_SYNC_ENABLED BIT(4)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_TILES_ENABLED BIT(3)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED BIT(2)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_WEIGHTED_BIPRED BIT(1)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_WEIGHTED_PRED BIT(0)
-#define VE_DEC_H265_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(v) \
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(v) \
SHIFT_AND_MASK_BITS(v, 10, 8)
-#define VE_DEC_H265_SCALING_LIST_CTRL0 (VE_ENGINE_DEC_H265 + 0x18)
+#define VE_DEC_HEVC_SCALING_LIST_CTRL0 (VE_ENGINE_DEC_HEVC + 0x18)
-#define VE_DEC_H265_SCALING_LIST_CTRL0_FLAG_ENABLED BIT(31)
+#define VE_DEC_HEVC_SCALING_LIST_CTRL0_FLAG_ENABLED BIT(31)
-#define VE_DEC_H265_SCALING_LIST_CTRL0_SRAM (0 << 30)
-#define VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT (1 << 30)
+#define VE_DEC_HEVC_SCALING_LIST_CTRL0_SRAM (0 << 30)
+#define VE_DEC_HEVC_SCALING_LIST_CTRL0_DEFAULT (1 << 30)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0 (VE_ENGINE_DEC_H265 + 0x20)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0 (VE_ENGINE_DEC_HEVC + 0x20)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_COLLOCATED_FROM_L0 BIT(11)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_CABAC_INIT BIT(10)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_MVD_L1_ZERO BIT(9)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_CHROMA BIT(8)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_LUMA BIT(7)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_TEMPORAL_MVP_ENABLE BIT(6)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT BIT(1)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC BIT(0)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_COLLOCATED_FROM_L0 BIT(11)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_CABAC_INIT BIT(10)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_MVD_L1_ZERO BIT(9)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_CHROMA BIT(8)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_LUMA BIT(7)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_SLICE_TEMPORAL_MVP_ENABLE BIT(6)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT BIT(1)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC BIT(0)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(v) \
SHIFT_AND_MASK_BITS(v, 29, 28)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(v) \
SHIFT_AND_MASK_BITS(v, 26, 24)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(v) \
SHIFT_AND_MASK_BITS(v, 23, 20)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(v) \
SHIFT_AND_MASK_BITS(v, 19, 16)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(v) \
SHIFT_AND_MASK_BITS(v, 15, 12)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(v) \
SHIFT_AND_MASK_BITS(v, 5, 4)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_SLICE_TYPE(v) \
SHIFT_AND_MASK_BITS(v, 3, 2)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1 (VE_ENGINE_DEC_H265 + 0x24)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1 (VE_ENGINE_DEC_HEVC + 0x24)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED BIT(23)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED BIT(22)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED BIT(23)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED BIT(22)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(v) \
SHIFT_AND_MASK_BITS(v, 31, 28)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(v) \
SHIFT_AND_MASK_BITS(v, 27, 24)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(v) \
((v) ? BIT(21) : 0)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(v) \
SHIFT_AND_MASK_BITS(v, 20, 16)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(v) \
SHIFT_AND_MASK_BITS(v, 12, 8)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(v) \
SHIFT_AND_MASK_BITS(v, 6, 0)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO2 (VE_ENGINE_DEC_H265 + 0x28)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO2 (VE_ENGINE_DEC_HEVC + 0x28)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(v) \
SHIFT_AND_MASK_BITS(v, 21, 8)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(v) \
SHIFT_AND_MASK_BITS(v, 6, 4)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(v) \
SHIFT_AND_MASK_BITS(v, 2, 0)
-#define VE_DEC_H265_DEC_CTB_ADDR (VE_ENGINE_DEC_H265 + 0x2c)
-
-#define VE_DEC_H265_DEC_CTB_ADDR_Y(y) SHIFT_AND_MASK_BITS(y, 25, 16)
-#define VE_DEC_H265_DEC_CTB_ADDR_X(x) SHIFT_AND_MASK_BITS(x, 9, 0)
-
-#define VE_DEC_H265_CTRL (VE_ENGINE_DEC_H265 + 0x30)
-
-#define VE_DEC_H265_CTRL_DDR_CONSISTENCY_EN BIT(31)
-#define VE_DEC_H265_CTRL_STCD_EN BIT(25)
-#define VE_DEC_H265_CTRL_EPTB_DEC_BYPASS_EN BIT(24)
-#define VE_DEC_H265_CTRL_TQ_BYPASS_EN BIT(12)
-#define VE_DEC_H265_CTRL_VLD_BYPASS_EN BIT(11)
-#define VE_DEC_H265_CTRL_NCRI_CACHE_DISABLE BIT(10)
-#define VE_DEC_H265_CTRL_ROTATE_SCALE_OUT_EN BIT(9)
-#define VE_DEC_H265_CTRL_MC_NO_WRITEBACK BIT(8)
-#define VE_DEC_H265_CTRL_VLD_DATA_REQ_IRQ_EN BIT(2)
-#define VE_DEC_H265_CTRL_ERROR_IRQ_EN BIT(1)
-#define VE_DEC_H265_CTRL_FINISH_IRQ_EN BIT(0)
-#define VE_DEC_H265_CTRL_IRQ_MASK \
- (VE_DEC_H265_CTRL_FINISH_IRQ_EN | VE_DEC_H265_CTRL_ERROR_IRQ_EN | \
- VE_DEC_H265_CTRL_VLD_DATA_REQ_IRQ_EN)
-
-#define VE_DEC_H265_TRIGGER (VE_ENGINE_DEC_H265 + 0x34)
-
-#define VE_DEC_H265_TRIGGER_TYPE_N_BITS(x) (((x) & 0x3f) << 8)
-#define VE_DEC_H265_TRIGGER_STCD_VC1 (0x02 << 4)
-#define VE_DEC_H265_TRIGGER_STCD_AVS (0x01 << 4)
-#define VE_DEC_H265_TRIGGER_STCD_HEVC (0x00 << 4)
-#define VE_DEC_H265_TRIGGER_DEC_SLICE (0x08 << 0)
-#define VE_DEC_H265_TRIGGER_INIT_SWDEC (0x07 << 0)
-#define VE_DEC_H265_TRIGGER_BYTE_ALIGN (0x06 << 0)
-#define VE_DEC_H265_TRIGGER_GET_VLCUE (0x05 << 0)
-#define VE_DEC_H265_TRIGGER_GET_VLCSE (0x04 << 0)
-#define VE_DEC_H265_TRIGGER_FLUSH_BITS (0x03 << 0)
-#define VE_DEC_H265_TRIGGER_GET_BITS (0x02 << 0)
-#define VE_DEC_H265_TRIGGER_SHOW_BITS (0x01 << 0)
-
-#define VE_DEC_H265_STATUS (VE_ENGINE_DEC_H265 + 0x38)
-
-#define VE_DEC_H265_STATUS_STCD BIT(24)
-#define VE_DEC_H265_STATUS_STCD_BUSY BIT(21)
-#define VE_DEC_H265_STATUS_WB_BUSY BIT(20)
-#define VE_DEC_H265_STATUS_BS_DMA_BUSY BIT(19)
-#define VE_DEC_H265_STATUS_IT_BUSY BIT(18)
-#define VE_DEC_H265_STATUS_INTER_BUSY BIT(17)
-#define VE_DEC_H265_STATUS_MORE_DATA BIT(16)
-#define VE_DEC_H265_STATUS_DBLK_BUSY BIT(15)
-#define VE_DEC_H265_STATUS_IREC_BUSY BIT(14)
-#define VE_DEC_H265_STATUS_INTRA_BUSY BIT(13)
-#define VE_DEC_H265_STATUS_MCRI_BUSY BIT(12)
-#define VE_DEC_H265_STATUS_IQIT_BUSY BIT(11)
-#define VE_DEC_H265_STATUS_MVP_BUSY BIT(10)
-#define VE_DEC_H265_STATUS_IS_BUSY BIT(9)
-#define VE_DEC_H265_STATUS_VLD_BUSY BIT(8)
-#define VE_DEC_H265_STATUS_OVER_TIME BIT(3)
-#define VE_DEC_H265_STATUS_VLD_DATA_REQ BIT(2)
-#define VE_DEC_H265_STATUS_ERROR BIT(1)
-#define VE_DEC_H265_STATUS_SUCCESS BIT(0)
-#define VE_DEC_H265_STATUS_STCD_TYPE_MASK GENMASK(23, 22)
-#define VE_DEC_H265_STATUS_CHECK_MASK \
- (VE_DEC_H265_STATUS_SUCCESS | VE_DEC_H265_STATUS_ERROR | \
- VE_DEC_H265_STATUS_VLD_DATA_REQ)
-#define VE_DEC_H265_STATUS_CHECK_ERROR \
- (VE_DEC_H265_STATUS_ERROR | VE_DEC_H265_STATUS_VLD_DATA_REQ)
-
-#define VE_DEC_H265_DEC_CTB_NUM (VE_ENGINE_DEC_H265 + 0x3c)
-
-#define VE_DEC_H265_BITS_ADDR (VE_ENGINE_DEC_H265 + 0x40)
-
-#define VE_DEC_H265_BITS_ADDR_FIRST_SLICE_DATA BIT(30)
-#define VE_DEC_H265_BITS_ADDR_LAST_SLICE_DATA BIT(29)
-#define VE_DEC_H265_BITS_ADDR_VALID_SLICE_DATA BIT(28)
-#define VE_DEC_H265_BITS_ADDR_BASE(a) (((a) >> 8) & GENMASK(27, 0))
-
-#define VE_DEC_H265_BITS_OFFSET (VE_ENGINE_DEC_H265 + 0x44)
-#define VE_DEC_H265_BITS_LEN (VE_ENGINE_DEC_H265 + 0x48)
-
-#define VE_DEC_H265_BITS_END_ADDR (VE_ENGINE_DEC_H265 + 0x4c)
-
-#define VE_DEC_H265_BITS_END_ADDR_BASE(a) ((a) >> 8)
-
-#define VE_DEC_H265_SDRT_CTRL (VE_ENGINE_DEC_H265 + 0x50)
-#define VE_DEC_H265_SDRT_LUMA_ADDR (VE_ENGINE_DEC_H265 + 0x54)
-#define VE_DEC_H265_SDRT_CHROMA_ADDR (VE_ENGINE_DEC_H265 + 0x58)
-
-#define VE_DEC_H265_OUTPUT_FRAME_IDX (VE_ENGINE_DEC_H265 + 0x5c)
-
-#define VE_DEC_H265_NEIGHBOR_INFO_ADDR (VE_ENGINE_DEC_H265 + 0x60)
-
-#define VE_DEC_H265_NEIGHBOR_INFO_ADDR_BASE(a) ((a) >> 8)
-
-#define VE_DEC_H265_ENTRY_POINT_OFFSET_ADDR (VE_ENGINE_DEC_H265 + 0x64)
-#define VE_DEC_H265_TILE_START_CTB (VE_ENGINE_DEC_H265 + 0x68)
-#define VE_DEC_H265_TILE_END_CTB (VE_ENGINE_DEC_H265 + 0x6c)
-#define VE_DEC_H265_SCALING_LIST_DC_COEF0 (VE_ENGINE_DEC_H265 + 0x78)
-#define VE_DEC_H265_SCALING_LIST_DC_COEF1 (VE_ENGINE_DEC_H265 + 0x7c)
-
-#define VE_DEC_H265_LOW_ADDR (VE_ENGINE_DEC_H265 + 0x80)
-
-#define VE_DEC_H265_LOW_ADDR_PRIMARY_CHROMA(a) \
+#define VE_DEC_HEVC_DEC_CTB_ADDR (VE_ENGINE_DEC_HEVC + 0x2c)
+
+#define VE_DEC_HEVC_DEC_CTB_ADDR_Y(y) SHIFT_AND_MASK_BITS(y, 25, 16)
+#define VE_DEC_HEVC_DEC_CTB_ADDR_X(x) SHIFT_AND_MASK_BITS(x, 9, 0)
+
+#define VE_DEC_HEVC_CTRL (VE_ENGINE_DEC_HEVC + 0x30)
+
+#define VE_DEC_HEVC_CTRL_DDR_CONSISTENCY_EN BIT(31)
+#define VE_DEC_HEVC_CTRL_STCD_EN BIT(25)
+#define VE_DEC_HEVC_CTRL_EPTB_DEC_BYPASS_EN BIT(24)
+#define VE_DEC_HEVC_CTRL_TQ_BYPASS_EN BIT(12)
+#define VE_DEC_HEVC_CTRL_VLD_BYPASS_EN BIT(11)
+#define VE_DEC_HEVC_CTRL_NCRI_CACHE_DISABLE BIT(10)
+#define VE_DEC_HEVC_CTRL_ROTATE_SCALE_OUT_EN BIT(9)
+#define VE_DEC_HEVC_CTRL_MC_NO_WRITEBACK BIT(8)
+#define VE_DEC_HEVC_CTRL_VLD_DATA_REQ_IRQ_EN BIT(2)
+#define VE_DEC_HEVC_CTRL_ERROR_IRQ_EN BIT(1)
+#define VE_DEC_HEVC_CTRL_FINISH_IRQ_EN BIT(0)
+#define VE_DEC_HEVC_CTRL_IRQ_MASK \
+ (VE_DEC_HEVC_CTRL_FINISH_IRQ_EN | VE_DEC_HEVC_CTRL_ERROR_IRQ_EN | \
+ VE_DEC_HEVC_CTRL_VLD_DATA_REQ_IRQ_EN)
+
+#define VE_DEC_HEVC_TRIGGER (VE_ENGINE_DEC_HEVC + 0x34)
+
+#define VE_DEC_HEVC_TRIGGER_TYPE_N_BITS(x) (((x) & 0x3f) << 8)
+#define VE_DEC_HEVC_TRIGGER_STCD_VC1 (0x02 << 4)
+#define VE_DEC_HEVC_TRIGGER_STCD_AVS (0x01 << 4)
+#define VE_DEC_HEVC_TRIGGER_STCD_HEVC (0x00 << 4)
+#define VE_DEC_HEVC_TRIGGER_DEC_SLICE (0x08 << 0)
+#define VE_DEC_HEVC_TRIGGER_INIT_SWDEC (0x07 << 0)
+#define VE_DEC_HEVC_TRIGGER_BYTE_ALIGN (0x06 << 0)
+#define VE_DEC_HEVC_TRIGGER_GET_VLCUE (0x05 << 0)
+#define VE_DEC_HEVC_TRIGGER_GET_VLCSE (0x04 << 0)
+#define VE_DEC_HEVC_TRIGGER_FLUSH_BITS (0x03 << 0)
+#define VE_DEC_HEVC_TRIGGER_GET_BITS (0x02 << 0)
+#define VE_DEC_HEVC_TRIGGER_SHOW_BITS (0x01 << 0)
+
+#define VE_DEC_HEVC_STATUS (VE_ENGINE_DEC_HEVC + 0x38)
+
+#define VE_DEC_HEVC_STATUS_STCD BIT(24)
+#define VE_DEC_HEVC_STATUS_STCD_BUSY BIT(21)
+#define VE_DEC_HEVC_STATUS_WB_BUSY BIT(20)
+#define VE_DEC_HEVC_STATUS_BS_DMA_BUSY BIT(19)
+#define VE_DEC_HEVC_STATUS_IT_BUSY BIT(18)
+#define VE_DEC_HEVC_STATUS_INTER_BUSY BIT(17)
+#define VE_DEC_HEVC_STATUS_MORE_DATA BIT(16)
+#define VE_DEC_HEVC_STATUS_DBLK_BUSY BIT(15)
+#define VE_DEC_HEVC_STATUS_IREC_BUSY BIT(14)
+#define VE_DEC_HEVC_STATUS_INTRA_BUSY BIT(13)
+#define VE_DEC_HEVC_STATUS_MCRI_BUSY BIT(12)
+#define VE_DEC_HEVC_STATUS_IQIT_BUSY BIT(11)
+#define VE_DEC_HEVC_STATUS_MVP_BUSY BIT(10)
+#define VE_DEC_HEVC_STATUS_IS_BUSY BIT(9)
+#define VE_DEC_HEVC_STATUS_VLD_BUSY BIT(8)
+#define VE_DEC_HEVC_STATUS_OVER_TIME BIT(3)
+#define VE_DEC_HEVC_STATUS_VLD_DATA_REQ BIT(2)
+#define VE_DEC_HEVC_STATUS_ERROR BIT(1)
+#define VE_DEC_HEVC_STATUS_SUCCESS BIT(0)
+#define VE_DEC_HEVC_STATUS_STCD_TYPE_MASK GENMASK(23, 22)
+#define VE_DEC_HEVC_STATUS_CHECK_MASK \
+ (VE_DEC_HEVC_STATUS_SUCCESS | VE_DEC_HEVC_STATUS_ERROR | \
+ VE_DEC_HEVC_STATUS_VLD_DATA_REQ)
+#define VE_DEC_HEVC_STATUS_CHECK_ERROR \
+ (VE_DEC_HEVC_STATUS_ERROR | VE_DEC_HEVC_STATUS_VLD_DATA_REQ)
+
+#define VE_DEC_HEVC_DEC_CTB_NUM (VE_ENGINE_DEC_HEVC + 0x3c)
+
+#define VE_DEC_HEVC_BITS_ADDR (VE_ENGINE_DEC_HEVC + 0x40)
+
+#define VE_DEC_HEVC_BITS_ADDR_FIRST_SLICE_DATA BIT(30)
+#define VE_DEC_HEVC_BITS_ADDR_LAST_SLICE_DATA BIT(29)
+#define VE_DEC_HEVC_BITS_ADDR_VALID_SLICE_DATA BIT(28)
+#define VE_DEC_HEVC_BITS_ADDR_BASE(a) (((a) >> 8) & GENMASK(27, 0))
+
+#define VE_DEC_HEVC_BITS_OFFSET (VE_ENGINE_DEC_HEVC + 0x44)
+#define VE_DEC_HEVC_BITS_LEN (VE_ENGINE_DEC_HEVC + 0x48)
+
+#define VE_DEC_HEVC_BITS_END_ADDR (VE_ENGINE_DEC_HEVC + 0x4c)
+
+#define VE_DEC_HEVC_BITS_END_ADDR_BASE(a) ((a) >> 8)
+
+#define VE_DEC_HEVC_SDRT_CTRL (VE_ENGINE_DEC_HEVC + 0x50)
+#define VE_DEC_HEVC_SDRT_LUMA_ADDR (VE_ENGINE_DEC_HEVC + 0x54)
+#define VE_DEC_HEVC_SDRT_CHROMA_ADDR (VE_ENGINE_DEC_HEVC + 0x58)
+
+#define VE_DEC_HEVC_OUTPUT_FRAME_IDX (VE_ENGINE_DEC_HEVC + 0x5c)
+
+#define VE_DEC_HEVC_NEIGHBOR_INFO_ADDR (VE_ENGINE_DEC_HEVC + 0x60)
+
+#define VE_DEC_HEVC_NEIGHBOR_INFO_ADDR_BASE(a) ((a) >> 8)
+
+#define VE_DEC_HEVC_ENTRY_POINT_OFFSET_ADDR (VE_ENGINE_DEC_HEVC + 0x64)
+#define VE_DEC_HEVC_TILE_START_CTB (VE_ENGINE_DEC_HEVC + 0x68)
+#define VE_DEC_HEVC_TILE_END_CTB (VE_ENGINE_DEC_HEVC + 0x6c)
+#define VE_DEC_HEVC_SCALING_LIST_DC_COEF0 (VE_ENGINE_DEC_HEVC + 0x78)
+#define VE_DEC_HEVC_SCALING_LIST_DC_COEF1 (VE_ENGINE_DEC_HEVC + 0x7c)
+
+#define VE_DEC_HEVC_LOW_ADDR (VE_ENGINE_DEC_HEVC + 0x80)
+
+#define VE_DEC_HEVC_LOW_ADDR_PRIMARY_CHROMA(a) \
SHIFT_AND_MASK_BITS(a, 31, 24)
-#define VE_DEC_H265_LOW_ADDR_SECONDARY_CHROMA(a) \
+#define VE_DEC_HEVC_LOW_ADDR_SECONDARY_CHROMA(a) \
SHIFT_AND_MASK_BITS(a, 23, 16)
-#define VE_DEC_H265_LOW_ADDR_ENTRY_POINTS_BUF(a) \
+#define VE_DEC_HEVC_LOW_ADDR_ENTRY_POINTS_BUF(a) \
SHIFT_AND_MASK_BITS(a, 7, 0)
-#define VE_DEC_H265_SRAM_OFFSET (VE_ENGINE_DEC_H265 + 0xe0)
+#define VE_DEC_HEVC_SRAM_OFFSET (VE_ENGINE_DEC_HEVC + 0xe0)
-#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0 0x00
-#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0 0x20
-#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1 0x60
-#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1 0x80
-#define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO 0x400
-#define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT 0x20
-#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS 0x800
-#define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0 0xc00
-#define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1 0xc10
+#define VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0 0x00
+#define VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0 0x20
+#define VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1 0x60
+#define VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1 0x80
+#define VE_DEC_HEVC_SRAM_OFFSET_FRAME_INFO 0x400
+#define VE_DEC_HEVC_SRAM_OFFSET_FRAME_INFO_UNIT 0x20
+#define VE_DEC_HEVC_SRAM_OFFSET_SCALING_LISTS 0x800
+#define VE_DEC_HEVC_SRAM_OFFSET_REF_PIC_LIST0 0xc00
+#define VE_DEC_HEVC_SRAM_OFFSET_REF_PIC_LIST1 0xc10
-#define VE_DEC_H265_SRAM_DATA (VE_ENGINE_DEC_H265 + 0xe4)
+#define VE_DEC_HEVC_SRAM_DATA (VE_ENGINE_DEC_HEVC + 0xe4)
-#define VE_DEC_H265_SRAM_DATA_ADDR_BASE(a) ((a) >> 8)
-#define VE_DEC_H265_SRAM_REF_PIC_LIST_LT_REF BIT(7)
+#define VE_DEC_HEVC_SRAM_DATA_ADDR_BASE(a) ((a) >> 8)
+#define VE_DEC_HEVC_SRAM_REF_PIC_LIST_LT_REF BIT(7)
#define VE_H264_SPS 0x200
#define VE_H264_SPS_MBS_ONLY BIT(18)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
index 33726175d980..384b9fa08423 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
@@ -48,7 +48,7 @@ static struct cedrus_format cedrus_formats[] = {
{
.pixelformat = V4L2_PIX_FMT_HEVC_SLICE,
.directions = CEDRUS_DECODE_SRC,
- .capabilities = CEDRUS_CAPABILITY_H265_DEC,
+ .capabilities = CEDRUS_CAPABILITY_HEVC_DEC,
},
{
.pixelformat = V4L2_PIX_FMT_VP8_FRAME,
@@ -485,7 +485,7 @@ static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count)
break;
case V4L2_PIX_FMT_HEVC_SLICE:
- ctx->current_codec = CEDRUS_CODEC_H265;
+ ctx->current_codec = CEDRUS_CODEC_HEVC;
break;
case V4L2_PIX_FMT_VP8_FRAME:
--
2.25.1
^ permalink raw reply related [flat|nested] 12+ messages in thread
* [RFC PATCH v3 2/2] staging: media: cedrus: Rename H265 to HEVC
@ 2022-03-27 8:43 ` Sebastian Fricke
0 siblings, 0 replies; 12+ messages in thread
From: Sebastian Fricke @ 2022-03-27 8:43 UTC (permalink / raw)
To: linux-media
Cc: acourbot, tfiga, hverkuil-cisco, Sebastian Fricke, Maxime Ripard,
Paul Kocialkowski, Mauro Carvalho Chehab, Greg Kroah-Hartman,
Chen-Yu Tsai, Jernej Skrabec, open list:STAGING SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support,
open list:ARM/Allwinner sunXi SoC support, open list
Rename all instances where the identifier H265 is used with HEVC.
The codec has multiple identifiers H.265 (ITU-T), MPEG-H Part 2 (ISO),
but the actual name of the codec is HEVC (High Efficiency Video Coding).
Also nearly all other related drivers use the term HEVC instead of H265.
Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
---
drivers/staging/media/sunxi/cedrus/Makefile | 2 +-
drivers/staging/media/sunxi/cedrus/cedrus.c | 30 +-
drivers/staging/media/sunxi/cedrus/cedrus.h | 14 +-
.../staging/media/sunxi/cedrus/cedrus_dec.c | 10 +-
.../cedrus/{cedrus_h265.c => cedrus_hevc.c} | 438 +++++++++---------
.../staging/media/sunxi/cedrus/cedrus_hw.c | 4 +-
.../staging/media/sunxi/cedrus/cedrus_regs.h | 394 ++++++++--------
.../staging/media/sunxi/cedrus/cedrus_video.c | 4 +-
8 files changed, 448 insertions(+), 448 deletions(-)
rename drivers/staging/media/sunxi/cedrus/{cedrus_h265.c => cedrus_hevc.c} (53%)
diff --git a/drivers/staging/media/sunxi/cedrus/Makefile b/drivers/staging/media/sunxi/cedrus/Makefile
index a647b3690bf8..84b1b5db3128 100644
--- a/drivers/staging/media/sunxi/cedrus/Makefile
+++ b/drivers/staging/media/sunxi/cedrus/Makefile
@@ -2,5 +2,5 @@
obj-$(CONFIG_VIDEO_SUNXI_CEDRUS) += sunxi-cedrus.o
sunxi-cedrus-y = cedrus.o cedrus_video.o cedrus_hw.o cedrus_dec.o \
- cedrus_mpeg2.o cedrus_h264.o cedrus_h265.o \
+ cedrus_mpeg2.o cedrus_h264.o cedrus_hevc.o \
cedrus_vp8.o
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.c b/drivers/staging/media/sunxi/cedrus/cedrus.c
index 68b3dcdb5df3..f27cb8036a72 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus.c
@@ -54,7 +54,7 @@ static int cedrus_try_ctrl(struct v4l2_ctrl *ctrl)
/* Luma and chroma bit depth mismatch */
return -EINVAL;
- if (ctx->dev->capabilities & CEDRUS_CAPABILITY_H265_10_DEC) {
+ if (ctx->dev->capabilities & CEDRUS_CAPABILITY_HEVC_10_DEC) {
if (sps->bit_depth_luma_minus8 != 0 && sps->bit_depth_luma_minus8 != 2)
/* Only 8-bit and 10-bit are supported */
return -EINVAL;
@@ -167,25 +167,25 @@ static const struct cedrus_control cedrus_controls[] = {
.id = V4L2_CID_MPEG_VIDEO_HEVC_SPS,
.ops = &cedrus_ctrl_ops,
},
- .codec = CEDRUS_CODEC_H265,
+ .codec = CEDRUS_CODEC_HEVC,
},
{
.cfg = {
.id = V4L2_CID_MPEG_VIDEO_HEVC_PPS,
},
- .codec = CEDRUS_CODEC_H265,
+ .codec = CEDRUS_CODEC_HEVC,
},
{
.cfg = {
.id = V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS,
},
- .codec = CEDRUS_CODEC_H265,
+ .codec = CEDRUS_CODEC_HEVC,
},
{
.cfg = {
.id = V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX,
},
- .codec = CEDRUS_CODEC_H265,
+ .codec = CEDRUS_CODEC_HEVC,
},
{
.cfg = {
@@ -193,7 +193,7 @@ static const struct cedrus_control cedrus_controls[] = {
.max = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,
.def = V4L2_MPEG_VIDEO_HEVC_DECODE_MODE_SLICE_BASED,
},
- .codec = CEDRUS_CODEC_H265,
+ .codec = CEDRUS_CODEC_HEVC,
},
{
.cfg = {
@@ -201,7 +201,7 @@ static const struct cedrus_control cedrus_controls[] = {
.max = V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE,
.def = V4L2_MPEG_VIDEO_HEVC_START_CODE_NONE,
},
- .codec = CEDRUS_CODEC_H265,
+ .codec = CEDRUS_CODEC_HEVC,
},
{
.cfg = {
@@ -213,7 +213,7 @@ static const struct cedrus_control cedrus_controls[] = {
.cfg = {
.id = V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS,
},
- .codec = CEDRUS_CODEC_H265,
+ .codec = CEDRUS_CODEC_HEVC,
},
};
@@ -434,7 +434,7 @@ static int cedrus_probe(struct platform_device *pdev)
dev->dec_ops[CEDRUS_CODEC_MPEG2] = &cedrus_dec_ops_mpeg2;
dev->dec_ops[CEDRUS_CODEC_H264] = &cedrus_dec_ops_h264;
- dev->dec_ops[CEDRUS_CODEC_H265] = &cedrus_dec_ops_h265;
+ dev->dec_ops[CEDRUS_CODEC_HEVC] = &cedrus_dec_ops_hevc;
dev->dec_ops[CEDRUS_CODEC_VP8] = &cedrus_dec_ops_vp8;
mutex_init(&dev->dev_mutex);
@@ -563,7 +563,7 @@ static const struct cedrus_variant sun8i_h3_cedrus_variant = {
.capabilities = CEDRUS_CAPABILITY_UNTILED |
CEDRUS_CAPABILITY_MPEG2_DEC |
CEDRUS_CAPABILITY_H264_DEC |
- CEDRUS_CAPABILITY_H265_DEC |
+ CEDRUS_CAPABILITY_HEVC_DEC |
CEDRUS_CAPABILITY_VP8_DEC,
.mod_rate = 402000000,
};
@@ -586,7 +586,7 @@ static const struct cedrus_variant sun20i_d1_cedrus_variant = {
.capabilities = CEDRUS_CAPABILITY_UNTILED |
CEDRUS_CAPABILITY_MPEG2_DEC |
CEDRUS_CAPABILITY_H264_DEC |
- CEDRUS_CAPABILITY_H265_DEC,
+ CEDRUS_CAPABILITY_HEVC_DEC,
.mod_rate = 432000000,
};
@@ -594,7 +594,7 @@ static const struct cedrus_variant sun50i_a64_cedrus_variant = {
.capabilities = CEDRUS_CAPABILITY_UNTILED |
CEDRUS_CAPABILITY_MPEG2_DEC |
CEDRUS_CAPABILITY_H264_DEC |
- CEDRUS_CAPABILITY_H265_DEC |
+ CEDRUS_CAPABILITY_HEVC_DEC |
CEDRUS_CAPABILITY_VP8_DEC,
.mod_rate = 402000000,
};
@@ -603,7 +603,7 @@ static const struct cedrus_variant sun50i_h5_cedrus_variant = {
.capabilities = CEDRUS_CAPABILITY_UNTILED |
CEDRUS_CAPABILITY_MPEG2_DEC |
CEDRUS_CAPABILITY_H264_DEC |
- CEDRUS_CAPABILITY_H265_DEC |
+ CEDRUS_CAPABILITY_HEVC_DEC |
CEDRUS_CAPABILITY_VP8_DEC,
.mod_rate = 402000000,
};
@@ -612,8 +612,8 @@ static const struct cedrus_variant sun50i_h6_cedrus_variant = {
.capabilities = CEDRUS_CAPABILITY_UNTILED |
CEDRUS_CAPABILITY_MPEG2_DEC |
CEDRUS_CAPABILITY_H264_DEC |
- CEDRUS_CAPABILITY_H265_DEC |
- CEDRUS_CAPABILITY_H265_10_DEC |
+ CEDRUS_CAPABILITY_HEVC_DEC |
+ CEDRUS_CAPABILITY_HEVC_10_DEC |
CEDRUS_CAPABILITY_VP8_DEC,
.mod_rate = 600000000,
};
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus.h b/drivers/staging/media/sunxi/cedrus/cedrus.h
index 3bc094eb497f..2c260fe27325 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus.h
+++ b/drivers/staging/media/sunxi/cedrus/cedrus.h
@@ -29,16 +29,16 @@
#define CEDRUS_NAME "cedrus"
#define CEDRUS_CAPABILITY_UNTILED BIT(0)
-#define CEDRUS_CAPABILITY_H265_DEC BIT(1)
+#define CEDRUS_CAPABILITY_HEVC_DEC BIT(1)
#define CEDRUS_CAPABILITY_H264_DEC BIT(2)
#define CEDRUS_CAPABILITY_MPEG2_DEC BIT(3)
#define CEDRUS_CAPABILITY_VP8_DEC BIT(4)
-#define CEDRUS_CAPABILITY_H265_10_DEC BIT(5)
+#define CEDRUS_CAPABILITY_HEVC_10_DEC BIT(5)
enum cedrus_codec {
CEDRUS_CODEC_MPEG2,
CEDRUS_CODEC_H264,
- CEDRUS_CODEC_H265,
+ CEDRUS_CODEC_HEVC,
CEDRUS_CODEC_VP8,
CEDRUS_CODEC_LAST,
};
@@ -75,7 +75,7 @@ struct cedrus_mpeg2_run {
const struct v4l2_ctrl_mpeg2_quantisation *quantisation;
};
-struct cedrus_h265_run {
+struct cedrus_hevc_run {
const struct v4l2_ctrl_hevc_sps *sps;
const struct v4l2_ctrl_hevc_pps *pps;
const struct v4l2_ctrl_hevc_slice_params *slice_params;
@@ -94,7 +94,7 @@ struct cedrus_run {
union {
struct cedrus_h264_run h264;
struct cedrus_mpeg2_run mpeg2;
- struct cedrus_h265_run h265;
+ struct cedrus_hevc_run hevc;
struct cedrus_vp8_run vp8;
};
};
@@ -146,7 +146,7 @@ struct cedrus_ctx {
ssize_t mv_col_buf_unit_size;
void *neighbor_info_buf;
dma_addr_t neighbor_info_buf_addr;
- } h265;
+ } hevc;
struct {
unsigned int last_frame_p_type;
unsigned int last_filter_type;
@@ -201,7 +201,7 @@ struct cedrus_dev {
extern struct cedrus_dec_ops cedrus_dec_ops_mpeg2;
extern struct cedrus_dec_ops cedrus_dec_ops_h264;
-extern struct cedrus_dec_ops cedrus_dec_ops_h265;
+extern struct cedrus_dec_ops cedrus_dec_ops_hevc;
extern struct cedrus_dec_ops cedrus_dec_ops_vp8;
static inline void cedrus_write(struct cedrus_dev *dev, u32 reg, u32 val)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c
index 9c7200299465..95f192127a50 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_dec.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_dec.c
@@ -64,15 +64,15 @@ void cedrus_device_run(void *priv)
break;
case V4L2_PIX_FMT_HEVC_SLICE:
- run.h265.sps = cedrus_find_control_data(ctx,
+ run.hevc.sps = cedrus_find_control_data(ctx,
V4L2_CID_MPEG_VIDEO_HEVC_SPS);
- run.h265.pps = cedrus_find_control_data(ctx,
+ run.hevc.pps = cedrus_find_control_data(ctx,
V4L2_CID_MPEG_VIDEO_HEVC_PPS);
- run.h265.slice_params = cedrus_find_control_data(ctx,
+ run.hevc.slice_params = cedrus_find_control_data(ctx,
V4L2_CID_MPEG_VIDEO_HEVC_SLICE_PARAMS);
- run.h265.decode_params = cedrus_find_control_data(ctx,
+ run.hevc.decode_params = cedrus_find_control_data(ctx,
V4L2_CID_MPEG_VIDEO_HEVC_DECODE_PARAMS);
- run.h265.scaling_matrix = cedrus_find_control_data(ctx,
+ run.hevc.scaling_matrix = cedrus_find_control_data(ctx,
V4L2_CID_MPEG_VIDEO_HEVC_SCALING_MATRIX);
break;
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c b/drivers/staging/media/sunxi/cedrus/cedrus_hevc.c
similarity index 53%
rename from drivers/staging/media/sunxi/cedrus/cedrus_h265.c
rename to drivers/staging/media/sunxi/cedrus/cedrus_hevc.c
index 44f385be9f6c..211410214d84 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_h265.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hevc.c
@@ -21,13 +21,13 @@
* internal decoding metadata. They match the values used by the early BSP
* implementations, that were initially exposed in libvdpau-sunxi.
* Subsequent BSP implementations seem to double the neighbor info buffer size
- * for the H6 SoC, which may be related to 10 bit H265 support.
+ * for the H6 SoC, which may be related to 10 bit HEVC support.
*/
-#define CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE (794 * SZ_1K)
-#define CEDRUS_H265_ENTRY_POINTS_BUF_SIZE (4 * SZ_1K)
-#define CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE 160
+#define CEDRUS_HEVC_NEIGHBOR_INFO_BUF_SIZE (794 * SZ_1K)
+#define CEDRUS_HEVC_ENTRY_POINTS_BUF_SIZE (4 * SZ_1K)
+#define CEDRUS_HEVC_MV_COL_BUF_UNIT_CTB_SIZE 160
-struct cedrus_h265_sram_frame_info {
+struct cedrus_hevc_sram_frame_info {
__le32 top_pic_order_cnt;
__le32 bottom_pic_order_cnt;
__le32 top_mv_col_buf_addr;
@@ -36,69 +36,69 @@ struct cedrus_h265_sram_frame_info {
__le32 chroma_addr;
} __packed;
-struct cedrus_h265_sram_pred_weight {
+struct cedrus_hevc_sram_pred_weight {
__s8 delta_weight;
__s8 offset;
} __packed;
-static enum cedrus_irq_status cedrus_h265_irq_status(struct cedrus_ctx *ctx)
+static enum cedrus_irq_status cedrus_hevc_irq_status(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
u32 reg;
- reg = cedrus_read(dev, VE_DEC_H265_STATUS);
- reg &= VE_DEC_H265_STATUS_CHECK_MASK;
+ reg = cedrus_read(dev, VE_DEC_HEVC_STATUS);
+ reg &= VE_DEC_HEVC_STATUS_CHECK_MASK;
- if (reg & VE_DEC_H265_STATUS_CHECK_ERROR ||
- !(reg & VE_DEC_H265_STATUS_SUCCESS))
+ if (reg & VE_DEC_HEVC_STATUS_CHECK_ERROR ||
+ !(reg & VE_DEC_HEVC_STATUS_SUCCESS))
return CEDRUS_IRQ_ERROR;
return CEDRUS_IRQ_OK;
}
-static void cedrus_h265_irq_clear(struct cedrus_ctx *ctx)
+static void cedrus_hevc_irq_clear(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
- cedrus_write(dev, VE_DEC_H265_STATUS, VE_DEC_H265_STATUS_CHECK_MASK);
+ cedrus_write(dev, VE_DEC_HEVC_STATUS, VE_DEC_HEVC_STATUS_CHECK_MASK);
}
-static void cedrus_h265_irq_disable(struct cedrus_ctx *ctx)
+static void cedrus_hevc_irq_disable(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
- u32 reg = cedrus_read(dev, VE_DEC_H265_CTRL);
+ u32 reg = cedrus_read(dev, VE_DEC_HEVC_CTRL);
- reg &= ~VE_DEC_H265_CTRL_IRQ_MASK;
+ reg &= ~VE_DEC_HEVC_CTRL_IRQ_MASK;
- cedrus_write(dev, VE_DEC_H265_CTRL, reg);
+ cedrus_write(dev, VE_DEC_HEVC_CTRL, reg);
}
-static void cedrus_h265_sram_write_offset(struct cedrus_dev *dev, u32 offset)
+static void cedrus_hevc_sram_write_offset(struct cedrus_dev *dev, u32 offset)
{
- cedrus_write(dev, VE_DEC_H265_SRAM_OFFSET, offset);
+ cedrus_write(dev, VE_DEC_HEVC_SRAM_OFFSET, offset);
}
-static void cedrus_h265_sram_write_data(struct cedrus_dev *dev, void *data,
+static void cedrus_hevc_sram_write_data(struct cedrus_dev *dev, void *data,
unsigned int size)
{
u32 *word = data;
while (size >= sizeof(u32)) {
- cedrus_write(dev, VE_DEC_H265_SRAM_DATA, *word++);
+ cedrus_write(dev, VE_DEC_HEVC_SRAM_DATA, *word++);
size -= sizeof(u32);
}
}
static inline dma_addr_t
-cedrus_h265_frame_info_mv_col_buf_addr(struct cedrus_ctx *ctx,
+cedrus_hevc_frame_info_mv_col_buf_addr(struct cedrus_ctx *ctx,
unsigned int index, unsigned int field)
{
- return ctx->codec.h265.mv_col_buf_addr + index *
- ctx->codec.h265.mv_col_buf_unit_size +
- field * ctx->codec.h265.mv_col_buf_unit_size / 2;
+ return ctx->codec.hevc.mv_col_buf_addr + index *
+ ctx->codec.hevc.mv_col_buf_unit_size +
+ field * ctx->codec.hevc.mv_col_buf_unit_size / 2;
}
-static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx,
+static void cedrus_hevc_frame_info_write_single(struct cedrus_ctx *ctx,
unsigned int index,
bool field_pic,
u32 pic_order_cnt[],
@@ -108,31 +108,31 @@ static void cedrus_h265_frame_info_write_single(struct cedrus_ctx *ctx,
dma_addr_t dst_luma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 0);
dma_addr_t dst_chroma_addr = cedrus_dst_buf_addr(ctx, buffer_index, 1);
dma_addr_t mv_col_buf_addr[2] = {
- cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index, 0),
- cedrus_h265_frame_info_mv_col_buf_addr(ctx, buffer_index,
+ cedrus_hevc_frame_info_mv_col_buf_addr(ctx, buffer_index, 0),
+ cedrus_hevc_frame_info_mv_col_buf_addr(ctx, buffer_index,
field_pic ? 1 : 0)
};
- u32 offset = VE_DEC_H265_SRAM_OFFSET_FRAME_INFO +
- VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT * index;
- struct cedrus_h265_sram_frame_info frame_info = {
+ u32 offset = VE_DEC_HEVC_SRAM_OFFSET_FRAME_INFO +
+ VE_DEC_HEVC_SRAM_OFFSET_FRAME_INFO_UNIT * index;
+ struct cedrus_hevc_sram_frame_info frame_info = {
.top_pic_order_cnt = cpu_to_le32(pic_order_cnt[0]),
.bottom_pic_order_cnt = cpu_to_le32(field_pic ?
pic_order_cnt[1] :
pic_order_cnt[0]),
.top_mv_col_buf_addr =
- cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])),
+ cpu_to_le32(VE_DEC_HEVC_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])),
.bottom_mv_col_buf_addr = cpu_to_le32(field_pic ?
- VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[1]) :
- VE_DEC_H265_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])),
- .luma_addr = cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_luma_addr)),
- .chroma_addr = cpu_to_le32(VE_DEC_H265_SRAM_DATA_ADDR_BASE(dst_chroma_addr)),
+ VE_DEC_HEVC_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[1]) :
+ VE_DEC_HEVC_SRAM_DATA_ADDR_BASE(mv_col_buf_addr[0])),
+ .luma_addr = cpu_to_le32(VE_DEC_HEVC_SRAM_DATA_ADDR_BASE(dst_luma_addr)),
+ .chroma_addr = cpu_to_le32(VE_DEC_HEVC_SRAM_DATA_ADDR_BASE(dst_chroma_addr)),
};
- cedrus_h265_sram_write_offset(dev, offset);
- cedrus_h265_sram_write_data(dev, &frame_info, sizeof(frame_info));
+ cedrus_hevc_sram_write_offset(dev, offset);
+ cedrus_hevc_sram_write_data(dev, &frame_info, sizeof(frame_info));
}
-static void cedrus_h265_frame_info_write_dpb(struct cedrus_ctx *ctx,
+static void cedrus_hevc_frame_info_write_dpb(struct cedrus_ctx *ctx,
const struct v4l2_hevc_dpb_entry *dpb,
u8 num_active_dpb_entries)
{
@@ -147,13 +147,13 @@ static void cedrus_h265_frame_info_write_dpb(struct cedrus_ctx *ctx,
dpb[i].pic_order_cnt[1]
};
- cedrus_h265_frame_info_write_single(ctx, i, dpb[i].field_pic,
+ cedrus_hevc_frame_info_write_single(ctx, i, dpb[i].field_pic,
pic_order_cnt,
buffer_index);
}
}
-static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev,
+static void cedrus_hevc_ref_pic_list_write(struct cedrus_dev *dev,
const struct v4l2_hevc_dpb_entry *dpb,
const u8 list[],
u8 num_ref_idx_active,
@@ -162,7 +162,7 @@ static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev,
unsigned int i;
u32 word = 0;
- cedrus_h265_sram_write_offset(dev, sram_offset);
+ cedrus_hevc_sram_write_offset(dev, sram_offset);
for (i = 0; i < num_ref_idx_active; i++) {
unsigned int shift = (i % 4) * 8;
@@ -170,20 +170,20 @@ static void cedrus_h265_ref_pic_list_write(struct cedrus_dev *dev,
u8 value = list[i];
if (dpb[index].flags & V4L2_HEVC_DPB_ENTRY_LONG_TERM_REFERENCE)
- value |= VE_DEC_H265_SRAM_REF_PIC_LIST_LT_REF;
+ value |= VE_DEC_HEVC_SRAM_REF_PIC_LIST_LT_REF;
/* Each SRAM word gathers up to 4 references. */
word |= value << shift;
/* Write the word to SRAM and clear it for the next batch. */
if ((i % 4) == 3 || i == (num_ref_idx_active - 1)) {
- cedrus_h265_sram_write_data(dev, &word, sizeof(word));
+ cedrus_hevc_sram_write_data(dev, &word, sizeof(word));
word = 0;
}
}
}
-static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev,
+static void cedrus_hevc_pred_weight_write(struct cedrus_dev *dev,
const s8 delta_luma_weight[],
const s8 luma_offset[],
const s8 delta_chroma_weight[][2],
@@ -192,10 +192,10 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev,
u32 sram_luma_offset,
u32 sram_chroma_offset)
{
- struct cedrus_h265_sram_pred_weight pred_weight[2] = { { 0 } };
+ struct cedrus_hevc_sram_pred_weight pred_weight[2] = { { 0 } };
unsigned int i, j;
- cedrus_h265_sram_write_offset(dev, sram_luma_offset);
+ cedrus_hevc_sram_write_offset(dev, sram_luma_offset);
for (i = 0; i < num_ref_idx_active; i++) {
unsigned int index = i % 2;
@@ -204,11 +204,11 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev,
pred_weight[index].offset = luma_offset[i];
if (index == 1 || i == (num_ref_idx_active - 1))
- cedrus_h265_sram_write_data(dev, (u32 *)&pred_weight,
+ cedrus_hevc_sram_write_data(dev, (u32 *)&pred_weight,
sizeof(pred_weight));
}
- cedrus_h265_sram_write_offset(dev, sram_chroma_offset);
+ cedrus_hevc_sram_write_offset(dev, sram_chroma_offset);
for (i = 0; i < num_ref_idx_active; i++) {
for (j = 0; j < 2; j++) {
@@ -216,50 +216,50 @@ static void cedrus_h265_pred_weight_write(struct cedrus_dev *dev,
pred_weight[j].offset = chroma_offset[i][j];
}
- cedrus_h265_sram_write_data(dev, &pred_weight,
+ cedrus_hevc_sram_write_data(dev, &pred_weight,
sizeof(pred_weight));
}
}
-static void cedrus_h265_skip_bits(struct cedrus_dev *dev, int num)
+static void cedrus_hevc_skip_bits(struct cedrus_dev *dev, int num)
{
int count = 0;
while (count < num) {
int tmp = min(num - count, 32);
- cedrus_write(dev, VE_DEC_H265_TRIGGER,
- VE_DEC_H265_TRIGGER_FLUSH_BITS |
- VE_DEC_H265_TRIGGER_TYPE_N_BITS(tmp));
- while (cedrus_read(dev, VE_DEC_H265_STATUS) & VE_DEC_H265_STATUS_VLD_BUSY)
+ cedrus_write(dev, VE_DEC_HEVC_TRIGGER,
+ VE_DEC_HEVC_TRIGGER_FLUSH_BITS |
+ VE_DEC_HEVC_TRIGGER_TYPE_N_BITS(tmp));
+ while (cedrus_read(dev, VE_DEC_HEVC_STATUS) & VE_DEC_HEVC_STATUS_VLD_BUSY)
udelay(1);
count += tmp;
}
}
-static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
+static void cedrus_hevc_write_scaling_list(struct cedrus_ctx *ctx,
struct cedrus_run *run)
{
const struct v4l2_ctrl_hevc_scaling_matrix *scaling;
struct cedrus_dev *dev = ctx->dev;
u32 i, j, k, val;
- scaling = run->h265.scaling_matrix;
+ scaling = run->hevc.scaling_matrix;
- cedrus_write(dev, VE_DEC_H265_SCALING_LIST_DC_COEF0,
+ cedrus_write(dev, VE_DEC_HEVC_SCALING_LIST_DC_COEF0,
(scaling->scaling_list_dc_coef_32x32[1] << 24) |
(scaling->scaling_list_dc_coef_32x32[0] << 16) |
(scaling->scaling_list_dc_coef_16x16[1] << 8) |
(scaling->scaling_list_dc_coef_16x16[0] << 0));
- cedrus_write(dev, VE_DEC_H265_SCALING_LIST_DC_COEF1,
+ cedrus_write(dev, VE_DEC_HEVC_SCALING_LIST_DC_COEF1,
(scaling->scaling_list_dc_coef_16x16[5] << 24) |
(scaling->scaling_list_dc_coef_16x16[4] << 16) |
(scaling->scaling_list_dc_coef_16x16[3] << 8) |
(scaling->scaling_list_dc_coef_16x16[2] << 0));
- cedrus_h265_sram_write_offset(dev, VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS);
+ cedrus_hevc_sram_write_offset(dev, VE_DEC_HEVC_SRAM_OFFSET_SCALING_LISTS);
for (i = 0; i < 6; i++)
for (j = 0; j < 8; j++)
@@ -268,7 +268,7 @@ static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
((u32)scaling->scaling_list_8x8[i][j + (k + 2) * 8] << 16) |
((u32)scaling->scaling_list_8x8[i][j + (k + 1) * 8] << 8) |
scaling->scaling_list_8x8[i][j + k * 8];
- cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val);
+ cedrus_write(dev, VE_DEC_HEVC_SRAM_DATA, val);
}
for (i = 0; i < 2; i++)
@@ -278,7 +278,7 @@ static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
((u32)scaling->scaling_list_32x32[i][j + (k + 2) * 8] << 16) |
((u32)scaling->scaling_list_32x32[i][j + (k + 1) * 8] << 8) |
scaling->scaling_list_32x32[i][j + k * 8];
- cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val);
+ cedrus_write(dev, VE_DEC_HEVC_SRAM_DATA, val);
}
for (i = 0; i < 6; i++)
@@ -288,7 +288,7 @@ static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
((u32)scaling->scaling_list_16x16[i][j + (k + 2) * 8] << 16) |
((u32)scaling->scaling_list_16x16[i][j + (k + 1) * 8] << 8) |
scaling->scaling_list_16x16[i][j + k * 8];
- cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val);
+ cedrus_write(dev, VE_DEC_HEVC_SRAM_DATA, val);
}
for (i = 0; i < 6; i++)
@@ -297,11 +297,11 @@ static void cedrus_h265_write_scaling_list(struct cedrus_ctx *ctx,
((u32)scaling->scaling_list_4x4[i][j + 8] << 16) |
((u32)scaling->scaling_list_4x4[i][j + 4] << 8) |
scaling->scaling_list_4x4[i][j];
- cedrus_write(dev, VE_DEC_H265_SRAM_DATA, val);
+ cedrus_write(dev, VE_DEC_HEVC_SRAM_DATA, val);
}
}
-static void cedrus_h265_setup(struct cedrus_ctx *ctx,
+static void cedrus_hevc_setup(struct cedrus_ctx *ctx,
struct cedrus_run *run)
{
struct cedrus_dev *dev = ctx->dev;
@@ -319,10 +319,10 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
u32 pic_order_cnt[2];
u32 reg;
- sps = run->h265.sps;
- pps = run->h265.pps;
- slice_params = run->h265.slice_params;
- decode_params = run->h265.decode_params;
+ sps = run->hevc.sps;
+ pps = run->hevc.pps;
+ slice_params = run->hevc.slice_params;
+ decode_params = run->hevc.decode_params;
pred_weight_table = &slice_params->pred_weight_table;
log2_max_luma_coding_block_size =
@@ -333,7 +333,7 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
DIV_ROUND_UP(sps->pic_width_in_luma_samples, ctb_size_luma);
/* MV column buffer size and allocation. */
- if (!ctx->codec.h265.mv_col_buf_size) {
+ if (!ctx->codec.hevc.mv_col_buf_size) {
unsigned int num_buffers =
run->dst->vb2_buf.vb2_queue->num_buffers;
@@ -342,269 +342,269 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
* Since the address is given with missing lsb bits, 1 KiB is
* added to each buffer to ensure proper alignment.
*/
- ctx->codec.h265.mv_col_buf_unit_size =
+ ctx->codec.hevc.mv_col_buf_unit_size =
DIV_ROUND_UP(ctx->src_fmt.width, ctb_size_luma) *
DIV_ROUND_UP(ctx->src_fmt.height, ctb_size_luma) *
- CEDRUS_H265_MV_COL_BUF_UNIT_CTB_SIZE + SZ_1K;
+ CEDRUS_HEVC_MV_COL_BUF_UNIT_CTB_SIZE + SZ_1K;
- ctx->codec.h265.mv_col_buf_size = num_buffers *
- ctx->codec.h265.mv_col_buf_unit_size;
+ ctx->codec.hevc.mv_col_buf_size = num_buffers *
+ ctx->codec.hevc.mv_col_buf_unit_size;
/* Buffer is never accessed by CPU, so we can skip kernel mapping. */
- ctx->codec.h265.mv_col_buf =
+ ctx->codec.hevc.mv_col_buf =
dma_alloc_attrs(dev->dev,
- ctx->codec.h265.mv_col_buf_size,
- &ctx->codec.h265.mv_col_buf_addr,
+ ctx->codec.hevc.mv_col_buf_size,
+ &ctx->codec.hevc.mv_col_buf_addr,
GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
- if (!ctx->codec.h265.mv_col_buf) {
- ctx->codec.h265.mv_col_buf_size = 0;
+ if (!ctx->codec.hevc.mv_col_buf) {
+ ctx->codec.hevc.mv_col_buf_size = 0;
// TODO: Abort the process here.
return;
}
}
- /* Activate H265 engine. */
- cedrus_engine_enable(ctx, CEDRUS_CODEC_H265);
+ /* Activate HEVC engine. */
+ cedrus_engine_enable(ctx, CEDRUS_CODEC_HEVC);
/* Source offset and length in bits. */
- cedrus_write(dev, VE_DEC_H265_BITS_OFFSET, 0);
+ cedrus_write(dev, VE_DEC_HEVC_BITS_OFFSET, 0);
reg = slice_params->bit_size;
- cedrus_write(dev, VE_DEC_H265_BITS_LEN, reg);
+ cedrus_write(dev, VE_DEC_HEVC_BITS_LEN, reg);
/* Source beginning and end addresses. */
src_buf_addr = vb2_dma_contig_plane_dma_addr(&run->src->vb2_buf, 0);
- reg = VE_DEC_H265_BITS_ADDR_BASE(src_buf_addr);
- reg |= VE_DEC_H265_BITS_ADDR_VALID_SLICE_DATA;
- reg |= VE_DEC_H265_BITS_ADDR_LAST_SLICE_DATA;
- reg |= VE_DEC_H265_BITS_ADDR_FIRST_SLICE_DATA;
+ reg = VE_DEC_HEVC_BITS_ADDR_BASE(src_buf_addr);
+ reg |= VE_DEC_HEVC_BITS_ADDR_VALID_SLICE_DATA;
+ reg |= VE_DEC_HEVC_BITS_ADDR_LAST_SLICE_DATA;
+ reg |= VE_DEC_HEVC_BITS_ADDR_FIRST_SLICE_DATA;
- cedrus_write(dev, VE_DEC_H265_BITS_ADDR, reg);
+ cedrus_write(dev, VE_DEC_HEVC_BITS_ADDR, reg);
src_buf_end_addr = src_buf_addr +
DIV_ROUND_UP(slice_params->bit_size, 8);
- reg = VE_DEC_H265_BITS_END_ADDR_BASE(src_buf_end_addr);
- cedrus_write(dev, VE_DEC_H265_BITS_END_ADDR, reg);
+ reg = VE_DEC_HEVC_BITS_END_ADDR_BASE(src_buf_end_addr);
+ cedrus_write(dev, VE_DEC_HEVC_BITS_END_ADDR, reg);
/* Coding tree block address */
- reg = VE_DEC_H265_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma);
- reg |= VE_DEC_H265_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma);
- cedrus_write(dev, VE_DEC_H265_DEC_CTB_ADDR, reg);
+ reg = VE_DEC_HEVC_DEC_CTB_ADDR_X(slice_params->slice_segment_addr % width_in_ctb_luma);
+ reg |= VE_DEC_HEVC_DEC_CTB_ADDR_Y(slice_params->slice_segment_addr / width_in_ctb_luma);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_CTB_ADDR, reg);
- cedrus_write(dev, VE_DEC_H265_TILE_START_CTB, 0);
- cedrus_write(dev, VE_DEC_H265_TILE_END_CTB, 0);
+ cedrus_write(dev, VE_DEC_HEVC_TILE_START_CTB, 0);
+ cedrus_write(dev, VE_DEC_HEVC_TILE_END_CTB, 0);
/* Clear the number of correctly-decoded coding tree blocks. */
if (ctx->fh.m2m_ctx->new_frame)
- cedrus_write(dev, VE_DEC_H265_DEC_CTB_NUM, 0);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_CTB_NUM, 0);
/* Initialize bitstream access. */
- cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_INIT_SWDEC);
+ cedrus_write(dev, VE_DEC_HEVC_TRIGGER, VE_DEC_HEVC_TRIGGER_INIT_SWDEC);
- cedrus_h265_skip_bits(dev, slice_params->data_bit_offset);
+ cedrus_hevc_skip_bits(dev, slice_params->data_bit_offset);
/* Bitstream parameters. */
- reg = VE_DEC_H265_DEC_NAL_HDR_NAL_UNIT_TYPE(slice_params->nal_unit_type) |
- VE_DEC_H265_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(slice_params->nuh_temporal_id_plus1);
+ reg = VE_DEC_HEVC_DEC_NAL_HDR_NAL_UNIT_TYPE(slice_params->nal_unit_type) |
+ VE_DEC_HEVC_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(slice_params->nuh_temporal_id_plus1);
- cedrus_write(dev, VE_DEC_H265_DEC_NAL_HDR, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_NAL_HDR, reg);
/* SPS. */
- reg = VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(sps->max_transform_hierarchy_depth_intra) |
- VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(sps->max_transform_hierarchy_depth_inter) |
- VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(sps->log2_diff_max_min_luma_transform_block_size) |
- VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(sps->log2_min_luma_transform_block_size_minus2) |
- VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_luma_coding_block_size) |
- VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_luma_coding_block_size_minus3) |
- VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(sps->bit_depth_chroma_minus8) |
- VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(sps->bit_depth_luma_minus8) |
- VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(sps->chroma_format_idc);
-
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_STRONG_INTRA_SMOOTHING_ENABLE,
+ reg = VE_DEC_HEVC_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(sps->max_transform_hierarchy_depth_intra) |
+ VE_DEC_HEVC_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(sps->max_transform_hierarchy_depth_inter) |
+ VE_DEC_HEVC_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(sps->log2_diff_max_min_luma_transform_block_size) |
+ VE_DEC_HEVC_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(sps->log2_min_luma_transform_block_size_minus2) |
+ VE_DEC_HEVC_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_luma_coding_block_size) |
+ VE_DEC_HEVC_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_luma_coding_block_size_minus3) |
+ VE_DEC_HEVC_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(sps->bit_depth_chroma_minus8) |
+ VE_DEC_HEVC_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(sps->bit_depth_luma_minus8) |
+ VE_DEC_HEVC_DEC_SPS_HDR_CHROMA_FORMAT_IDC(sps->chroma_format_idc);
+
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SPS_HDR_FLAG_STRONG_INTRA_SMOOTHING_ENABLE,
V4L2_HEVC_SPS_FLAG_STRONG_INTRA_SMOOTHING_ENABLED,
sps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SPS_TEMPORAL_MVP_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SPS_HDR_FLAG_SPS_TEMPORAL_MVP_ENABLED,
V4L2_HEVC_SPS_FLAG_SPS_TEMPORAL_MVP_ENABLED,
sps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SAMPLE_ADAPTIVE_OFFSET_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SPS_HDR_FLAG_SAMPLE_ADAPTIVE_OFFSET_ENABLED,
V4L2_HEVC_SPS_FLAG_SAMPLE_ADAPTIVE_OFFSET,
sps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_AMP_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SPS_HDR_FLAG_AMP_ENABLED,
V4L2_HEVC_SPS_FLAG_AMP_ENABLED, sps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SPS_HDR_FLAG_SEPARATE_COLOUR_PLANE,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SPS_HDR_FLAG_SEPARATE_COLOUR_PLANE,
V4L2_HEVC_SPS_FLAG_SEPARATE_COLOUR_PLANE,
sps->flags);
- cedrus_write(dev, VE_DEC_H265_DEC_SPS_HDR, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_SPS_HDR, reg);
- reg = VE_DEC_H265_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_pcm_luma_coding_block_size) |
- VE_DEC_H265_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_pcm_luma_coding_block_size_minus3) |
- VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(sps->pcm_sample_bit_depth_chroma_minus1) |
- VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(sps->pcm_sample_bit_depth_luma_minus1);
+ reg = VE_DEC_HEVC_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(sps->log2_diff_max_min_pcm_luma_coding_block_size) |
+ VE_DEC_HEVC_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(sps->log2_min_pcm_luma_coding_block_size_minus3) |
+ VE_DEC_HEVC_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(sps->pcm_sample_bit_depth_chroma_minus1) |
+ VE_DEC_HEVC_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(sps->pcm_sample_bit_depth_luma_minus1);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PCM_CTRL_FLAG_PCM_ENABLED,
V4L2_HEVC_SPS_FLAG_PCM_ENABLED, sps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_LOOP_FILTER_DISABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PCM_CTRL_FLAG_PCM_LOOP_FILTER_DISABLED,
V4L2_HEVC_SPS_FLAG_PCM_LOOP_FILTER_DISABLED,
sps->flags);
- cedrus_write(dev, VE_DEC_H265_DEC_PCM_CTRL, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_PCM_CTRL, reg);
/* PPS. */
- reg = VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) |
- VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(pps->pps_cb_qp_offset) |
- VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(pps->init_qp_minus26) |
- VE_DEC_H265_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(pps->diff_cu_qp_delta_depth);
+ reg = VE_DEC_HEVC_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(pps->pps_cr_qp_offset) |
+ VE_DEC_HEVC_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(pps->pps_cb_qp_offset) |
+ VE_DEC_HEVC_DEC_PPS_CTRL0_INIT_QP_MINUS26(pps->init_qp_minus26) |
+ VE_DEC_HEVC_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(pps->diff_cu_qp_delta_depth);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CU_QP_DELTA_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_CU_QP_DELTA_ENABLED,
V4L2_HEVC_PPS_FLAG_CU_QP_DELTA_ENABLED,
pps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_TRANSFORM_SKIP_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_TRANSFORM_SKIP_ENABLED,
V4L2_HEVC_PPS_FLAG_TRANSFORM_SKIP_ENABLED,
pps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CONSTRAINED_INTRA_PRED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_CONSTRAINED_INTRA_PRED,
V4L2_HEVC_PPS_FLAG_CONSTRAINED_INTRA_PRED,
pps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL0_FLAG_SIGN_DATA_HIDING_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_SIGN_DATA_HIDING_ENABLED,
V4L2_HEVC_PPS_FLAG_SIGN_DATA_HIDING_ENABLED,
pps->flags);
- cedrus_write(dev, VE_DEC_H265_DEC_PPS_CTRL0, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_PPS_CTRL0, reg);
- reg = VE_DEC_H265_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(pps->log2_parallel_merge_level_minus2);
+ reg = VE_DEC_HEVC_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(pps->log2_parallel_merge_level_minus2);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED,
V4L2_HEVC_PPS_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED,
pps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED,
V4L2_HEVC_PPS_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED,
pps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_ENTROPY_CODING_SYNC_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_ENTROPY_CODING_SYNC_ENABLED,
V4L2_HEVC_PPS_FLAG_ENTROPY_CODING_SYNC_ENABLED,
pps->flags);
- /* TODO: VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED */
+ /* TODO: VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_TILES_ENABLED */
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED,
V4L2_HEVC_PPS_FLAG_TRANSQUANT_BYPASS_ENABLED,
pps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_BIPRED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_WEIGHTED_BIPRED,
V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED, pps->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_PRED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_WEIGHTED_PRED,
V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED, pps->flags);
- cedrus_write(dev, VE_DEC_H265_DEC_PPS_CTRL1, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_PPS_CTRL1, reg);
/* Slice Parameters. */
- reg = VE_DEC_H265_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(slice_params->pic_struct) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(slice_params->five_minus_max_num_merge_cand) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(slice_params->num_ref_idx_l1_active_minus1) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(slice_params->num_ref_idx_l0_active_minus1) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(slice_params->collocated_ref_idx) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(slice_params->colour_plane_id) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(slice_params->slice_type);
+ reg = VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(slice_params->pic_struct) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(slice_params->five_minus_max_num_merge_cand) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(slice_params->num_ref_idx_l1_active_minus1) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(slice_params->num_ref_idx_l0_active_minus1) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(slice_params->collocated_ref_idx) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(slice_params->colour_plane_id) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_SLICE_TYPE(slice_params->slice_type);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_COLLOCATED_FROM_L0,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_COLLOCATED_FROM_L0,
V4L2_HEVC_SLICE_PARAMS_FLAG_COLLOCATED_FROM_L0,
slice_params->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_CABAC_INIT,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_CABAC_INIT,
V4L2_HEVC_SLICE_PARAMS_FLAG_CABAC_INIT,
slice_params->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_MVD_L1_ZERO,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_MVD_L1_ZERO,
V4L2_HEVC_SLICE_PARAMS_FLAG_MVD_L1_ZERO,
slice_params->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_CHROMA,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_CHROMA,
V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_CHROMA,
slice_params->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_LUMA,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_LUMA,
V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_SAO_LUMA,
slice_params->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_TEMPORAL_MVP_ENABLE,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_SLICE_TEMPORAL_MVP_ENABLE,
V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_TEMPORAL_MVP_ENABLED,
slice_params->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT,
V4L2_HEVC_SLICE_PARAMS_FLAG_DEPENDENT_SLICE_SEGMENT,
slice_params->flags);
if (ctx->fh.m2m_ctx->new_frame)
- reg |= VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC;
+ reg |= VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC;
- cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO0, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_SLICE_HDR_INFO0, reg);
- reg = VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(slice_params->slice_tc_offset_div2) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(slice_params->slice_beta_offset_div2) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(decode_params->num_poc_st_curr_after == 0) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(slice_params->slice_cr_qp_offset) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(slice_params->slice_cb_qp_offset) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(slice_params->slice_qp_delta);
+ reg = VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(slice_params->slice_tc_offset_div2) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(slice_params->slice_beta_offset_div2) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(decode_params->num_poc_st_curr_after == 0) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(slice_params->slice_cr_qp_offset) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(slice_params->slice_cb_qp_offset) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(slice_params->slice_qp_delta);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED,
V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED,
slice_params->flags);
- reg |= VE_DEC_H265_FLAG(VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED,
+ reg |= VE_DEC_HEVC_FLAG(VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED,
V4L2_HEVC_SLICE_PARAMS_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED,
slice_params->flags);
- cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO1, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_SLICE_HDR_INFO1, reg);
chroma_log2_weight_denom = pred_weight_table->luma_log2_weight_denom +
pred_weight_table->delta_chroma_log2_weight_denom;
- reg = VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(0) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(chroma_log2_weight_denom) |
- VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(pred_weight_table->luma_log2_weight_denom);
+ reg = VE_DEC_HEVC_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(0) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(chroma_log2_weight_denom) |
+ VE_DEC_HEVC_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(pred_weight_table->luma_log2_weight_denom);
- cedrus_write(dev, VE_DEC_H265_DEC_SLICE_HDR_INFO2, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_SLICE_HDR_INFO2, reg);
/* Decoded picture size. */
- reg = VE_DEC_H265_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) |
- VE_DEC_H265_DEC_PIC_SIZE_HEIGHT(ctx->src_fmt.height);
+ reg = VE_DEC_HEVC_DEC_PIC_SIZE_WIDTH(ctx->src_fmt.width) |
+ VE_DEC_HEVC_DEC_PIC_SIZE_HEIGHT(ctx->src_fmt.height);
- cedrus_write(dev, VE_DEC_H265_DEC_PIC_SIZE, reg);
+ cedrus_write(dev, VE_DEC_HEVC_DEC_PIC_SIZE, reg);
/* Scaling list. */
if (sps->flags & V4L2_HEVC_SPS_FLAG_SCALING_LIST_ENABLED) {
- cedrus_h265_write_scaling_list(ctx, run);
- reg = VE_DEC_H265_SCALING_LIST_CTRL0_FLAG_ENABLED;
+ cedrus_hevc_write_scaling_list(ctx, run);
+ reg = VE_DEC_HEVC_SCALING_LIST_CTRL0_FLAG_ENABLED;
} else {
- reg = VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT;
+ reg = VE_DEC_HEVC_SCALING_LIST_CTRL0_DEFAULT;
}
- cedrus_write(dev, VE_DEC_H265_SCALING_LIST_CTRL0, reg);
+ cedrus_write(dev, VE_DEC_HEVC_SCALING_LIST_CTRL0, reg);
/* Neightbor information address. */
- reg = VE_DEC_H265_NEIGHBOR_INFO_ADDR_BASE(ctx->codec.h265.neighbor_info_buf_addr);
- cedrus_write(dev, VE_DEC_H265_NEIGHBOR_INFO_ADDR, reg);
+ reg = VE_DEC_HEVC_NEIGHBOR_INFO_ADDR_BASE(ctx->codec.hevc.neighbor_info_buf_addr);
+ cedrus_write(dev, VE_DEC_HEVC_NEIGHBOR_INFO_ADDR, reg);
/* Write decoded picture buffer in pic list. */
- cedrus_h265_frame_info_write_dpb(ctx, decode_params->dpb,
+ cedrus_hevc_frame_info_write_dpb(ctx, decode_params->dpb,
decode_params->num_active_dpb_entries);
/* Output frame. */
@@ -613,104 +613,104 @@ static void cedrus_h265_setup(struct cedrus_ctx *ctx,
pic_order_cnt[0] = slice_params->slice_pic_order_cnt;
pic_order_cnt[1] = slice_params->slice_pic_order_cnt;
- cedrus_h265_frame_info_write_single(ctx, output_pic_list_index,
+ cedrus_hevc_frame_info_write_single(ctx, output_pic_list_index,
slice_params->pic_struct != 0,
pic_order_cnt,
run->dst->vb2_buf.index);
- cedrus_write(dev, VE_DEC_H265_OUTPUT_FRAME_IDX, output_pic_list_index);
+ cedrus_write(dev, VE_DEC_HEVC_OUTPUT_FRAME_IDX, output_pic_list_index);
/* Reference picture list 0 (for P/B frames). */
if (slice_params->slice_type != V4L2_HEVC_SLICE_TYPE_I) {
- cedrus_h265_ref_pic_list_write(dev, decode_params->dpb,
+ cedrus_hevc_ref_pic_list_write(dev, decode_params->dpb,
slice_params->ref_idx_l0,
slice_params->num_ref_idx_l0_active_minus1 + 1,
- VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0);
+ VE_DEC_HEVC_SRAM_OFFSET_REF_PIC_LIST0);
if ((pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_PRED) ||
(pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED))
- cedrus_h265_pred_weight_write(dev,
+ cedrus_hevc_pred_weight_write(dev,
pred_weight_table->delta_luma_weight_l0,
pred_weight_table->luma_offset_l0,
pred_weight_table->delta_chroma_weight_l0,
pred_weight_table->chroma_offset_l0,
slice_params->num_ref_idx_l0_active_minus1 + 1,
- VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0,
- VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0);
+ VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0,
+ VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0);
}
/* Reference picture list 1 (for B frames). */
if (slice_params->slice_type == V4L2_HEVC_SLICE_TYPE_B) {
- cedrus_h265_ref_pic_list_write(dev, decode_params->dpb,
+ cedrus_hevc_ref_pic_list_write(dev, decode_params->dpb,
slice_params->ref_idx_l1,
slice_params->num_ref_idx_l1_active_minus1 + 1,
- VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1);
+ VE_DEC_HEVC_SRAM_OFFSET_REF_PIC_LIST1);
if (pps->flags & V4L2_HEVC_PPS_FLAG_WEIGHTED_BIPRED)
- cedrus_h265_pred_weight_write(dev,
+ cedrus_hevc_pred_weight_write(dev,
pred_weight_table->delta_luma_weight_l1,
pred_weight_table->luma_offset_l1,
pred_weight_table->delta_chroma_weight_l1,
pred_weight_table->chroma_offset_l1,
slice_params->num_ref_idx_l1_active_minus1 + 1,
- VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1,
- VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1);
+ VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1,
+ VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1);
}
/* Enable appropriate interruptions. */
- cedrus_write(dev, VE_DEC_H265_CTRL, VE_DEC_H265_CTRL_IRQ_MASK);
+ cedrus_write(dev, VE_DEC_HEVC_CTRL, VE_DEC_HEVC_CTRL_IRQ_MASK);
}
-static int cedrus_h265_start(struct cedrus_ctx *ctx)
+static int cedrus_hevc_start(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
/* The buffer size is calculated at setup time. */
- ctx->codec.h265.mv_col_buf_size = 0;
+ ctx->codec.hevc.mv_col_buf_size = 0;
/* Buffer is never accessed by CPU, so we can skip kernel mapping. */
- ctx->codec.h265.neighbor_info_buf =
- dma_alloc_attrs(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE,
- &ctx->codec.h265.neighbor_info_buf_addr,
+ ctx->codec.hevc.neighbor_info_buf =
+ dma_alloc_attrs(dev->dev, CEDRUS_HEVC_NEIGHBOR_INFO_BUF_SIZE,
+ &ctx->codec.hevc.neighbor_info_buf_addr,
GFP_KERNEL, DMA_ATTR_NO_KERNEL_MAPPING);
- if (!ctx->codec.h265.neighbor_info_buf)
+ if (!ctx->codec.hevc.neighbor_info_buf)
return -ENOMEM;
return 0;
}
-static void cedrus_h265_stop(struct cedrus_ctx *ctx)
+static void cedrus_hevc_stop(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
- if (ctx->codec.h265.mv_col_buf_size > 0) {
- dma_free_attrs(dev->dev, ctx->codec.h265.mv_col_buf_size,
- ctx->codec.h265.mv_col_buf,
- ctx->codec.h265.mv_col_buf_addr,
+ if (ctx->codec.hevc.mv_col_buf_size > 0) {
+ dma_free_attrs(dev->dev, ctx->codec.hevc.mv_col_buf_size,
+ ctx->codec.hevc.mv_col_buf,
+ ctx->codec.hevc.mv_col_buf_addr,
DMA_ATTR_NO_KERNEL_MAPPING);
- ctx->codec.h265.mv_col_buf_size = 0;
+ ctx->codec.hevc.mv_col_buf_size = 0;
}
- dma_free_attrs(dev->dev, CEDRUS_H265_NEIGHBOR_INFO_BUF_SIZE,
- ctx->codec.h265.neighbor_info_buf,
- ctx->codec.h265.neighbor_info_buf_addr,
+ dma_free_attrs(dev->dev, CEDRUS_HEVC_NEIGHBOR_INFO_BUF_SIZE,
+ ctx->codec.hevc.neighbor_info_buf,
+ ctx->codec.hevc.neighbor_info_buf_addr,
DMA_ATTR_NO_KERNEL_MAPPING);
}
-static void cedrus_h265_trigger(struct cedrus_ctx *ctx)
+static void cedrus_hevc_trigger(struct cedrus_ctx *ctx)
{
struct cedrus_dev *dev = ctx->dev;
- cedrus_write(dev, VE_DEC_H265_TRIGGER, VE_DEC_H265_TRIGGER_DEC_SLICE);
+ cedrus_write(dev, VE_DEC_HEVC_TRIGGER, VE_DEC_HEVC_TRIGGER_DEC_SLICE);
}
-struct cedrus_dec_ops cedrus_dec_ops_h265 = {
- .irq_clear = cedrus_h265_irq_clear,
- .irq_disable = cedrus_h265_irq_disable,
- .irq_status = cedrus_h265_irq_status,
- .setup = cedrus_h265_setup,
- .start = cedrus_h265_start,
- .stop = cedrus_h265_stop,
- .trigger = cedrus_h265_trigger,
+struct cedrus_dec_ops cedrus_dec_ops_hevc = {
+ .irq_clear = cedrus_hevc_irq_clear,
+ .irq_disable = cedrus_hevc_irq_disable,
+ .irq_status = cedrus_hevc_irq_status,
+ .setup = cedrus_hevc_setup,
+ .start = cedrus_hevc_start,
+ .stop = cedrus_hevc_stop,
+ .trigger = cedrus_hevc_trigger,
};
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
index a6470a89851e..4697a1ec4592 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_hw.c
@@ -53,8 +53,8 @@ int cedrus_engine_enable(struct cedrus_ctx *ctx, enum cedrus_codec codec)
reg |= VE_MODE_DEC_H264;
break;
- case CEDRUS_CODEC_H265:
- reg |= VE_MODE_DEC_H265;
+ case CEDRUS_CODEC_HEVC:
+ reg |= VE_MODE_DEC_HEVC;
break;
default:
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
index bdb062ad8682..402d5f7af3c1 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_regs.h
@@ -31,7 +31,7 @@
#define VE_ENGINE_DEC_MPEG 0x100
#define VE_ENGINE_DEC_H264 0x200
-#define VE_ENGINE_DEC_H265 0x500
+#define VE_ENGINE_DEC_HEVC 0x500
#define VE_MODE 0x00
@@ -42,7 +42,7 @@
#define VE_MODE_DDR_MODE_BW_128 (0x03 << 16)
#define VE_MODE_DDR_MODE_BW_256 (0x02 << 16)
#define VE_MODE_DISABLED (0x07 << 0)
-#define VE_MODE_DEC_H265 (0x04 << 0)
+#define VE_MODE_DEC_HEVC (0x04 << 0)
#define VE_MODE_DEC_H264 (0x01 << 0)
#define VE_MODE_DEC_MPEG (0x00 << 0)
@@ -255,273 +255,273 @@
#define VE_DEC_MPEG_ROT_LUMA (VE_ENGINE_DEC_MPEG + 0xcc)
#define VE_DEC_MPEG_ROT_CHROMA (VE_ENGINE_DEC_MPEG + 0xd0)
-#define VE_DEC_H265_DEC_NAL_HDR (VE_ENGINE_DEC_H265 + 0x00)
+#define VE_DEC_HEVC_DEC_NAL_HDR (VE_ENGINE_DEC_HEVC + 0x00)
-#define VE_DEC_H265_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(v) \
+#define VE_DEC_HEVC_DEC_NAL_HDR_NUH_TEMPORAL_ID_PLUS1(v) \
SHIFT_AND_MASK_BITS(v, 8, 6)
-#define VE_DEC_H265_DEC_NAL_HDR_NAL_UNIT_TYPE(v) \
+#define VE_DEC_HEVC_DEC_NAL_HDR_NAL_UNIT_TYPE(v) \
SHIFT_AND_MASK_BITS(v, 5, 0)
-#define VE_DEC_H265_FLAG(reg_flag, ctrl_flag, flags) \
+#define VE_DEC_HEVC_FLAG(reg_flag, ctrl_flag, flags) \
(((flags) & (ctrl_flag)) ? reg_flag : 0)
-#define VE_DEC_H265_DEC_SPS_HDR (VE_ENGINE_DEC_H265 + 0x04)
+#define VE_DEC_HEVC_DEC_SPS_HDR (VE_ENGINE_DEC_HEVC + 0x04)
-#define VE_DEC_H265_DEC_SPS_HDR_FLAG_STRONG_INTRA_SMOOTHING_ENABLE BIT(26)
-#define VE_DEC_H265_DEC_SPS_HDR_FLAG_SPS_TEMPORAL_MVP_ENABLED BIT(25)
-#define VE_DEC_H265_DEC_SPS_HDR_FLAG_SAMPLE_ADAPTIVE_OFFSET_ENABLED BIT(24)
-#define VE_DEC_H265_DEC_SPS_HDR_FLAG_AMP_ENABLED BIT(23)
-#define VE_DEC_H265_DEC_SPS_HDR_FLAG_SEPARATE_COLOUR_PLANE BIT(2)
+#define VE_DEC_HEVC_DEC_SPS_HDR_FLAG_STRONG_INTRA_SMOOTHING_ENABLE BIT(26)
+#define VE_DEC_HEVC_DEC_SPS_HDR_FLAG_SPS_TEMPORAL_MVP_ENABLED BIT(25)
+#define VE_DEC_HEVC_DEC_SPS_HDR_FLAG_SAMPLE_ADAPTIVE_OFFSET_ENABLED BIT(24)
+#define VE_DEC_HEVC_DEC_SPS_HDR_FLAG_AMP_ENABLED BIT(23)
+#define VE_DEC_HEVC_DEC_SPS_HDR_FLAG_SEPARATE_COLOUR_PLANE BIT(2)
-#define VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTRA(v) \
SHIFT_AND_MASK_BITS(v, 22, 20)
-#define VE_DEC_H265_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_MAX_TRANSFORM_HIERARCHY_DEPTH_INTER(v) \
SHIFT_AND_MASK_BITS(v, 19, 17)
-#define VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_TRANSFORM_BLOCK_SIZE(v) \
SHIFT_AND_MASK_BITS(v, 16, 15)
-#define VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_LOG2_MIN_TRANSFORM_BLOCK_SIZE_MINUS2(v) \
SHIFT_AND_MASK_BITS(v, 14, 13)
-#define VE_DEC_H265_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_LOG2_DIFF_MAX_MIN_LUMA_CODING_BLOCK_SIZE(v) \
SHIFT_AND_MASK_BITS(v, 12, 11)
-#define VE_DEC_H265_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_LOG2_MIN_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \
SHIFT_AND_MASK_BITS(v, 10, 9)
-#define VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_BIT_DEPTH_CHROMA_MINUS8(v) \
SHIFT_AND_MASK_BITS(v, 8, 6)
-#define VE_DEC_H265_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_BIT_DEPTH_LUMA_MINUS8(v) \
SHIFT_AND_MASK_BITS(v, 5, 3)
-#define VE_DEC_H265_DEC_SPS_HDR_CHROMA_FORMAT_IDC(v) \
+#define VE_DEC_HEVC_DEC_SPS_HDR_CHROMA_FORMAT_IDC(v) \
SHIFT_AND_MASK_BITS(v, 1, 0)
-#define VE_DEC_H265_DEC_PIC_SIZE (VE_ENGINE_DEC_H265 + 0x08)
+#define VE_DEC_HEVC_DEC_PIC_SIZE (VE_ENGINE_DEC_HEVC + 0x08)
-#define VE_DEC_H265_DEC_PIC_SIZE_WIDTH(w) (((w) << 0) & GENMASK(13, 0))
-#define VE_DEC_H265_DEC_PIC_SIZE_HEIGHT(h) (((h) << 16) & GENMASK(29, 16))
+#define VE_DEC_HEVC_DEC_PIC_SIZE_WIDTH(w) (((w) << 0) & GENMASK(13, 0))
+#define VE_DEC_HEVC_DEC_PIC_SIZE_HEIGHT(h) (((h) << 16) & GENMASK(29, 16))
-#define VE_DEC_H265_DEC_PCM_CTRL (VE_ENGINE_DEC_H265 + 0x0c)
+#define VE_DEC_HEVC_DEC_PCM_CTRL (VE_ENGINE_DEC_HEVC + 0x0c)
-#define VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_ENABLED BIT(15)
-#define VE_DEC_H265_DEC_PCM_CTRL_FLAG_PCM_LOOP_FILTER_DISABLED BIT(14)
+#define VE_DEC_HEVC_DEC_PCM_CTRL_FLAG_PCM_ENABLED BIT(15)
+#define VE_DEC_HEVC_DEC_PCM_CTRL_FLAG_PCM_LOOP_FILTER_DISABLED BIT(14)
-#define VE_DEC_H265_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(v) \
+#define VE_DEC_HEVC_DEC_PCM_CTRL_LOG2_DIFF_MAX_MIN_PCM_LUMA_CODING_BLOCK_SIZE(v) \
SHIFT_AND_MASK_BITS(v, 11, 10)
-#define VE_DEC_H265_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \
+#define VE_DEC_HEVC_DEC_PCM_CTRL_LOG2_MIN_PCM_LUMA_CODING_BLOCK_SIZE_MINUS3(v) \
SHIFT_AND_MASK_BITS(v, 9, 8)
-#define VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(v) \
+#define VE_DEC_HEVC_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_CHROMA_MINUS1(v) \
SHIFT_AND_MASK_BITS(v, 7, 4)
-#define VE_DEC_H265_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(v) \
+#define VE_DEC_HEVC_DEC_PCM_CTRL_PCM_SAMPLE_BIT_DEPTH_LUMA_MINUS1(v) \
SHIFT_AND_MASK_BITS(v, 3, 0)
-#define VE_DEC_H265_DEC_PPS_CTRL0 (VE_ENGINE_DEC_H265 + 0x10)
+#define VE_DEC_HEVC_DEC_PPS_CTRL0 (VE_ENGINE_DEC_HEVC + 0x10)
-#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CU_QP_DELTA_ENABLED BIT(3)
-#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_TRANSFORM_SKIP_ENABLED BIT(2)
-#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_CONSTRAINED_INTRA_PRED BIT(1)
-#define VE_DEC_H265_DEC_PPS_CTRL0_FLAG_SIGN_DATA_HIDING_ENABLED BIT(0)
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_CU_QP_DELTA_ENABLED BIT(3)
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_TRANSFORM_SKIP_ENABLED BIT(2)
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_CONSTRAINED_INTRA_PRED BIT(1)
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_FLAG_SIGN_DATA_HIDING_ENABLED BIT(0)
-#define VE_DEC_H265_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(v) \
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_PPS_CR_QP_OFFSET(v) \
SHIFT_AND_MASK_BITS(v, 29, 24)
-#define VE_DEC_H265_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(v) \
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_PPS_CB_QP_OFFSET(v) \
SHIFT_AND_MASK_BITS(v, 21, 16)
-#define VE_DEC_H265_DEC_PPS_CTRL0_INIT_QP_MINUS26(v) \
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_INIT_QP_MINUS26(v) \
SHIFT_AND_MASK_BITS(v, 14, 8)
-#define VE_DEC_H265_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(v) \
+#define VE_DEC_HEVC_DEC_PPS_CTRL0_DIFF_CU_QP_DELTA_DEPTH(v) \
SHIFT_AND_MASK_BITS(v, 5, 4)
-#define VE_DEC_H265_DEC_PPS_CTRL1 (VE_ENGINE_DEC_H265 + 0x14)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1 (VE_ENGINE_DEC_HEVC + 0x14)
-#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED BIT(6)
-#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED BIT(5)
-#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_ENTROPY_CODING_SYNC_ENABLED BIT(4)
-#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TILES_ENABLED BIT(3)
-#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED BIT(2)
-#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_BIPRED BIT(1)
-#define VE_DEC_H265_DEC_PPS_CTRL1_FLAG_WEIGHTED_PRED BIT(0)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_PPS_LOOP_FILTER_ACROSS_SLICES_ENABLED BIT(6)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_LOOP_FILTER_ACROSS_TILES_ENABLED BIT(5)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_ENTROPY_CODING_SYNC_ENABLED BIT(4)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_TILES_ENABLED BIT(3)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_TRANSQUANT_BYPASS_ENABLED BIT(2)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_WEIGHTED_BIPRED BIT(1)
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_FLAG_WEIGHTED_PRED BIT(0)
-#define VE_DEC_H265_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(v) \
+#define VE_DEC_HEVC_DEC_PPS_CTRL1_LOG2_PARALLEL_MERGE_LEVEL_MINUS2(v) \
SHIFT_AND_MASK_BITS(v, 10, 8)
-#define VE_DEC_H265_SCALING_LIST_CTRL0 (VE_ENGINE_DEC_H265 + 0x18)
+#define VE_DEC_HEVC_SCALING_LIST_CTRL0 (VE_ENGINE_DEC_HEVC + 0x18)
-#define VE_DEC_H265_SCALING_LIST_CTRL0_FLAG_ENABLED BIT(31)
+#define VE_DEC_HEVC_SCALING_LIST_CTRL0_FLAG_ENABLED BIT(31)
-#define VE_DEC_H265_SCALING_LIST_CTRL0_SRAM (0 << 30)
-#define VE_DEC_H265_SCALING_LIST_CTRL0_DEFAULT (1 << 30)
+#define VE_DEC_HEVC_SCALING_LIST_CTRL0_SRAM (0 << 30)
+#define VE_DEC_HEVC_SCALING_LIST_CTRL0_DEFAULT (1 << 30)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0 (VE_ENGINE_DEC_H265 + 0x20)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0 (VE_ENGINE_DEC_HEVC + 0x20)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_COLLOCATED_FROM_L0 BIT(11)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_CABAC_INIT BIT(10)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_MVD_L1_ZERO BIT(9)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_CHROMA BIT(8)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_LUMA BIT(7)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_SLICE_TEMPORAL_MVP_ENABLE BIT(6)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT BIT(1)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC BIT(0)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_COLLOCATED_FROM_L0 BIT(11)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_CABAC_INIT BIT(10)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_MVD_L1_ZERO BIT(9)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_CHROMA BIT(8)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_SLICE_SAO_LUMA BIT(7)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_SLICE_TEMPORAL_MVP_ENABLE BIT(6)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_DEPENDENT_SLICE_SEGMENT BIT(1)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FLAG_FIRST_SLICE_SEGMENT_IN_PIC BIT(0)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_PICTURE_TYPE(v) \
SHIFT_AND_MASK_BITS(v, 29, 28)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_FIVE_MINUS_MAX_NUM_MERGE_CAND(v) \
SHIFT_AND_MASK_BITS(v, 26, 24)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L1_ACTIVE_MINUS1(v) \
SHIFT_AND_MASK_BITS(v, 23, 20)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_NUM_REF_IDX_L0_ACTIVE_MINUS1(v) \
SHIFT_AND_MASK_BITS(v, 19, 16)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_COLLOCATED_REF_IDX(v) \
SHIFT_AND_MASK_BITS(v, 15, 12)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_COLOUR_PLANE_ID(v) \
SHIFT_AND_MASK_BITS(v, 5, 4)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO0_SLICE_TYPE(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO0_SLICE_TYPE(v) \
SHIFT_AND_MASK_BITS(v, 3, 2)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1 (VE_ENGINE_DEC_H265 + 0x24)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1 (VE_ENGINE_DEC_HEVC + 0x24)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED BIT(23)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED BIT(22)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_FLAG_SLICE_DEBLOCKING_FILTER_DISABLED BIT(23)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_FLAG_SLICE_LOOP_FILTER_ACROSS_SLICES_ENABLED BIT(22)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_TC_OFFSET_DIV2(v) \
SHIFT_AND_MASK_BITS(v, 31, 28)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_BETA_OFFSET_DIV2(v) \
SHIFT_AND_MASK_BITS(v, 27, 24)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_POC_BIGEST_IN_RPS_ST(v) \
((v) ? BIT(21) : 0)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_CR_QP_OFFSET(v) \
SHIFT_AND_MASK_BITS(v, 20, 16)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_CB_QP_OFFSET(v) \
SHIFT_AND_MASK_BITS(v, 12, 8)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO1_SLICE_QP_DELTA(v) \
SHIFT_AND_MASK_BITS(v, 6, 0)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO2 (VE_ENGINE_DEC_H265 + 0x28)
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO2 (VE_ENGINE_DEC_HEVC + 0x28)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO2_NUM_ENTRY_POINT_OFFSETS(v) \
SHIFT_AND_MASK_BITS(v, 21, 8)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO2_CHROMA_LOG2_WEIGHT_DENOM(v) \
SHIFT_AND_MASK_BITS(v, 6, 4)
-#define VE_DEC_H265_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(v) \
+#define VE_DEC_HEVC_DEC_SLICE_HDR_INFO2_LUMA_LOG2_WEIGHT_DENOM(v) \
SHIFT_AND_MASK_BITS(v, 2, 0)
-#define VE_DEC_H265_DEC_CTB_ADDR (VE_ENGINE_DEC_H265 + 0x2c)
-
-#define VE_DEC_H265_DEC_CTB_ADDR_Y(y) SHIFT_AND_MASK_BITS(y, 25, 16)
-#define VE_DEC_H265_DEC_CTB_ADDR_X(x) SHIFT_AND_MASK_BITS(x, 9, 0)
-
-#define VE_DEC_H265_CTRL (VE_ENGINE_DEC_H265 + 0x30)
-
-#define VE_DEC_H265_CTRL_DDR_CONSISTENCY_EN BIT(31)
-#define VE_DEC_H265_CTRL_STCD_EN BIT(25)
-#define VE_DEC_H265_CTRL_EPTB_DEC_BYPASS_EN BIT(24)
-#define VE_DEC_H265_CTRL_TQ_BYPASS_EN BIT(12)
-#define VE_DEC_H265_CTRL_VLD_BYPASS_EN BIT(11)
-#define VE_DEC_H265_CTRL_NCRI_CACHE_DISABLE BIT(10)
-#define VE_DEC_H265_CTRL_ROTATE_SCALE_OUT_EN BIT(9)
-#define VE_DEC_H265_CTRL_MC_NO_WRITEBACK BIT(8)
-#define VE_DEC_H265_CTRL_VLD_DATA_REQ_IRQ_EN BIT(2)
-#define VE_DEC_H265_CTRL_ERROR_IRQ_EN BIT(1)
-#define VE_DEC_H265_CTRL_FINISH_IRQ_EN BIT(0)
-#define VE_DEC_H265_CTRL_IRQ_MASK \
- (VE_DEC_H265_CTRL_FINISH_IRQ_EN | VE_DEC_H265_CTRL_ERROR_IRQ_EN | \
- VE_DEC_H265_CTRL_VLD_DATA_REQ_IRQ_EN)
-
-#define VE_DEC_H265_TRIGGER (VE_ENGINE_DEC_H265 + 0x34)
-
-#define VE_DEC_H265_TRIGGER_TYPE_N_BITS(x) (((x) & 0x3f) << 8)
-#define VE_DEC_H265_TRIGGER_STCD_VC1 (0x02 << 4)
-#define VE_DEC_H265_TRIGGER_STCD_AVS (0x01 << 4)
-#define VE_DEC_H265_TRIGGER_STCD_HEVC (0x00 << 4)
-#define VE_DEC_H265_TRIGGER_DEC_SLICE (0x08 << 0)
-#define VE_DEC_H265_TRIGGER_INIT_SWDEC (0x07 << 0)
-#define VE_DEC_H265_TRIGGER_BYTE_ALIGN (0x06 << 0)
-#define VE_DEC_H265_TRIGGER_GET_VLCUE (0x05 << 0)
-#define VE_DEC_H265_TRIGGER_GET_VLCSE (0x04 << 0)
-#define VE_DEC_H265_TRIGGER_FLUSH_BITS (0x03 << 0)
-#define VE_DEC_H265_TRIGGER_GET_BITS (0x02 << 0)
-#define VE_DEC_H265_TRIGGER_SHOW_BITS (0x01 << 0)
-
-#define VE_DEC_H265_STATUS (VE_ENGINE_DEC_H265 + 0x38)
-
-#define VE_DEC_H265_STATUS_STCD BIT(24)
-#define VE_DEC_H265_STATUS_STCD_BUSY BIT(21)
-#define VE_DEC_H265_STATUS_WB_BUSY BIT(20)
-#define VE_DEC_H265_STATUS_BS_DMA_BUSY BIT(19)
-#define VE_DEC_H265_STATUS_IT_BUSY BIT(18)
-#define VE_DEC_H265_STATUS_INTER_BUSY BIT(17)
-#define VE_DEC_H265_STATUS_MORE_DATA BIT(16)
-#define VE_DEC_H265_STATUS_DBLK_BUSY BIT(15)
-#define VE_DEC_H265_STATUS_IREC_BUSY BIT(14)
-#define VE_DEC_H265_STATUS_INTRA_BUSY BIT(13)
-#define VE_DEC_H265_STATUS_MCRI_BUSY BIT(12)
-#define VE_DEC_H265_STATUS_IQIT_BUSY BIT(11)
-#define VE_DEC_H265_STATUS_MVP_BUSY BIT(10)
-#define VE_DEC_H265_STATUS_IS_BUSY BIT(9)
-#define VE_DEC_H265_STATUS_VLD_BUSY BIT(8)
-#define VE_DEC_H265_STATUS_OVER_TIME BIT(3)
-#define VE_DEC_H265_STATUS_VLD_DATA_REQ BIT(2)
-#define VE_DEC_H265_STATUS_ERROR BIT(1)
-#define VE_DEC_H265_STATUS_SUCCESS BIT(0)
-#define VE_DEC_H265_STATUS_STCD_TYPE_MASK GENMASK(23, 22)
-#define VE_DEC_H265_STATUS_CHECK_MASK \
- (VE_DEC_H265_STATUS_SUCCESS | VE_DEC_H265_STATUS_ERROR | \
- VE_DEC_H265_STATUS_VLD_DATA_REQ)
-#define VE_DEC_H265_STATUS_CHECK_ERROR \
- (VE_DEC_H265_STATUS_ERROR | VE_DEC_H265_STATUS_VLD_DATA_REQ)
-
-#define VE_DEC_H265_DEC_CTB_NUM (VE_ENGINE_DEC_H265 + 0x3c)
-
-#define VE_DEC_H265_BITS_ADDR (VE_ENGINE_DEC_H265 + 0x40)
-
-#define VE_DEC_H265_BITS_ADDR_FIRST_SLICE_DATA BIT(30)
-#define VE_DEC_H265_BITS_ADDR_LAST_SLICE_DATA BIT(29)
-#define VE_DEC_H265_BITS_ADDR_VALID_SLICE_DATA BIT(28)
-#define VE_DEC_H265_BITS_ADDR_BASE(a) (((a) >> 8) & GENMASK(27, 0))
-
-#define VE_DEC_H265_BITS_OFFSET (VE_ENGINE_DEC_H265 + 0x44)
-#define VE_DEC_H265_BITS_LEN (VE_ENGINE_DEC_H265 + 0x48)
-
-#define VE_DEC_H265_BITS_END_ADDR (VE_ENGINE_DEC_H265 + 0x4c)
-
-#define VE_DEC_H265_BITS_END_ADDR_BASE(a) ((a) >> 8)
-
-#define VE_DEC_H265_SDRT_CTRL (VE_ENGINE_DEC_H265 + 0x50)
-#define VE_DEC_H265_SDRT_LUMA_ADDR (VE_ENGINE_DEC_H265 + 0x54)
-#define VE_DEC_H265_SDRT_CHROMA_ADDR (VE_ENGINE_DEC_H265 + 0x58)
-
-#define VE_DEC_H265_OUTPUT_FRAME_IDX (VE_ENGINE_DEC_H265 + 0x5c)
-
-#define VE_DEC_H265_NEIGHBOR_INFO_ADDR (VE_ENGINE_DEC_H265 + 0x60)
-
-#define VE_DEC_H265_NEIGHBOR_INFO_ADDR_BASE(a) ((a) >> 8)
-
-#define VE_DEC_H265_ENTRY_POINT_OFFSET_ADDR (VE_ENGINE_DEC_H265 + 0x64)
-#define VE_DEC_H265_TILE_START_CTB (VE_ENGINE_DEC_H265 + 0x68)
-#define VE_DEC_H265_TILE_END_CTB (VE_ENGINE_DEC_H265 + 0x6c)
-#define VE_DEC_H265_SCALING_LIST_DC_COEF0 (VE_ENGINE_DEC_H265 + 0x78)
-#define VE_DEC_H265_SCALING_LIST_DC_COEF1 (VE_ENGINE_DEC_H265 + 0x7c)
-
-#define VE_DEC_H265_LOW_ADDR (VE_ENGINE_DEC_H265 + 0x80)
-
-#define VE_DEC_H265_LOW_ADDR_PRIMARY_CHROMA(a) \
+#define VE_DEC_HEVC_DEC_CTB_ADDR (VE_ENGINE_DEC_HEVC + 0x2c)
+
+#define VE_DEC_HEVC_DEC_CTB_ADDR_Y(y) SHIFT_AND_MASK_BITS(y, 25, 16)
+#define VE_DEC_HEVC_DEC_CTB_ADDR_X(x) SHIFT_AND_MASK_BITS(x, 9, 0)
+
+#define VE_DEC_HEVC_CTRL (VE_ENGINE_DEC_HEVC + 0x30)
+
+#define VE_DEC_HEVC_CTRL_DDR_CONSISTENCY_EN BIT(31)
+#define VE_DEC_HEVC_CTRL_STCD_EN BIT(25)
+#define VE_DEC_HEVC_CTRL_EPTB_DEC_BYPASS_EN BIT(24)
+#define VE_DEC_HEVC_CTRL_TQ_BYPASS_EN BIT(12)
+#define VE_DEC_HEVC_CTRL_VLD_BYPASS_EN BIT(11)
+#define VE_DEC_HEVC_CTRL_NCRI_CACHE_DISABLE BIT(10)
+#define VE_DEC_HEVC_CTRL_ROTATE_SCALE_OUT_EN BIT(9)
+#define VE_DEC_HEVC_CTRL_MC_NO_WRITEBACK BIT(8)
+#define VE_DEC_HEVC_CTRL_VLD_DATA_REQ_IRQ_EN BIT(2)
+#define VE_DEC_HEVC_CTRL_ERROR_IRQ_EN BIT(1)
+#define VE_DEC_HEVC_CTRL_FINISH_IRQ_EN BIT(0)
+#define VE_DEC_HEVC_CTRL_IRQ_MASK \
+ (VE_DEC_HEVC_CTRL_FINISH_IRQ_EN | VE_DEC_HEVC_CTRL_ERROR_IRQ_EN | \
+ VE_DEC_HEVC_CTRL_VLD_DATA_REQ_IRQ_EN)
+
+#define VE_DEC_HEVC_TRIGGER (VE_ENGINE_DEC_HEVC + 0x34)
+
+#define VE_DEC_HEVC_TRIGGER_TYPE_N_BITS(x) (((x) & 0x3f) << 8)
+#define VE_DEC_HEVC_TRIGGER_STCD_VC1 (0x02 << 4)
+#define VE_DEC_HEVC_TRIGGER_STCD_AVS (0x01 << 4)
+#define VE_DEC_HEVC_TRIGGER_STCD_HEVC (0x00 << 4)
+#define VE_DEC_HEVC_TRIGGER_DEC_SLICE (0x08 << 0)
+#define VE_DEC_HEVC_TRIGGER_INIT_SWDEC (0x07 << 0)
+#define VE_DEC_HEVC_TRIGGER_BYTE_ALIGN (0x06 << 0)
+#define VE_DEC_HEVC_TRIGGER_GET_VLCUE (0x05 << 0)
+#define VE_DEC_HEVC_TRIGGER_GET_VLCSE (0x04 << 0)
+#define VE_DEC_HEVC_TRIGGER_FLUSH_BITS (0x03 << 0)
+#define VE_DEC_HEVC_TRIGGER_GET_BITS (0x02 << 0)
+#define VE_DEC_HEVC_TRIGGER_SHOW_BITS (0x01 << 0)
+
+#define VE_DEC_HEVC_STATUS (VE_ENGINE_DEC_HEVC + 0x38)
+
+#define VE_DEC_HEVC_STATUS_STCD BIT(24)
+#define VE_DEC_HEVC_STATUS_STCD_BUSY BIT(21)
+#define VE_DEC_HEVC_STATUS_WB_BUSY BIT(20)
+#define VE_DEC_HEVC_STATUS_BS_DMA_BUSY BIT(19)
+#define VE_DEC_HEVC_STATUS_IT_BUSY BIT(18)
+#define VE_DEC_HEVC_STATUS_INTER_BUSY BIT(17)
+#define VE_DEC_HEVC_STATUS_MORE_DATA BIT(16)
+#define VE_DEC_HEVC_STATUS_DBLK_BUSY BIT(15)
+#define VE_DEC_HEVC_STATUS_IREC_BUSY BIT(14)
+#define VE_DEC_HEVC_STATUS_INTRA_BUSY BIT(13)
+#define VE_DEC_HEVC_STATUS_MCRI_BUSY BIT(12)
+#define VE_DEC_HEVC_STATUS_IQIT_BUSY BIT(11)
+#define VE_DEC_HEVC_STATUS_MVP_BUSY BIT(10)
+#define VE_DEC_HEVC_STATUS_IS_BUSY BIT(9)
+#define VE_DEC_HEVC_STATUS_VLD_BUSY BIT(8)
+#define VE_DEC_HEVC_STATUS_OVER_TIME BIT(3)
+#define VE_DEC_HEVC_STATUS_VLD_DATA_REQ BIT(2)
+#define VE_DEC_HEVC_STATUS_ERROR BIT(1)
+#define VE_DEC_HEVC_STATUS_SUCCESS BIT(0)
+#define VE_DEC_HEVC_STATUS_STCD_TYPE_MASK GENMASK(23, 22)
+#define VE_DEC_HEVC_STATUS_CHECK_MASK \
+ (VE_DEC_HEVC_STATUS_SUCCESS | VE_DEC_HEVC_STATUS_ERROR | \
+ VE_DEC_HEVC_STATUS_VLD_DATA_REQ)
+#define VE_DEC_HEVC_STATUS_CHECK_ERROR \
+ (VE_DEC_HEVC_STATUS_ERROR | VE_DEC_HEVC_STATUS_VLD_DATA_REQ)
+
+#define VE_DEC_HEVC_DEC_CTB_NUM (VE_ENGINE_DEC_HEVC + 0x3c)
+
+#define VE_DEC_HEVC_BITS_ADDR (VE_ENGINE_DEC_HEVC + 0x40)
+
+#define VE_DEC_HEVC_BITS_ADDR_FIRST_SLICE_DATA BIT(30)
+#define VE_DEC_HEVC_BITS_ADDR_LAST_SLICE_DATA BIT(29)
+#define VE_DEC_HEVC_BITS_ADDR_VALID_SLICE_DATA BIT(28)
+#define VE_DEC_HEVC_BITS_ADDR_BASE(a) (((a) >> 8) & GENMASK(27, 0))
+
+#define VE_DEC_HEVC_BITS_OFFSET (VE_ENGINE_DEC_HEVC + 0x44)
+#define VE_DEC_HEVC_BITS_LEN (VE_ENGINE_DEC_HEVC + 0x48)
+
+#define VE_DEC_HEVC_BITS_END_ADDR (VE_ENGINE_DEC_HEVC + 0x4c)
+
+#define VE_DEC_HEVC_BITS_END_ADDR_BASE(a) ((a) >> 8)
+
+#define VE_DEC_HEVC_SDRT_CTRL (VE_ENGINE_DEC_HEVC + 0x50)
+#define VE_DEC_HEVC_SDRT_LUMA_ADDR (VE_ENGINE_DEC_HEVC + 0x54)
+#define VE_DEC_HEVC_SDRT_CHROMA_ADDR (VE_ENGINE_DEC_HEVC + 0x58)
+
+#define VE_DEC_HEVC_OUTPUT_FRAME_IDX (VE_ENGINE_DEC_HEVC + 0x5c)
+
+#define VE_DEC_HEVC_NEIGHBOR_INFO_ADDR (VE_ENGINE_DEC_HEVC + 0x60)
+
+#define VE_DEC_HEVC_NEIGHBOR_INFO_ADDR_BASE(a) ((a) >> 8)
+
+#define VE_DEC_HEVC_ENTRY_POINT_OFFSET_ADDR (VE_ENGINE_DEC_HEVC + 0x64)
+#define VE_DEC_HEVC_TILE_START_CTB (VE_ENGINE_DEC_HEVC + 0x68)
+#define VE_DEC_HEVC_TILE_END_CTB (VE_ENGINE_DEC_HEVC + 0x6c)
+#define VE_DEC_HEVC_SCALING_LIST_DC_COEF0 (VE_ENGINE_DEC_HEVC + 0x78)
+#define VE_DEC_HEVC_SCALING_LIST_DC_COEF1 (VE_ENGINE_DEC_HEVC + 0x7c)
+
+#define VE_DEC_HEVC_LOW_ADDR (VE_ENGINE_DEC_HEVC + 0x80)
+
+#define VE_DEC_HEVC_LOW_ADDR_PRIMARY_CHROMA(a) \
SHIFT_AND_MASK_BITS(a, 31, 24)
-#define VE_DEC_H265_LOW_ADDR_SECONDARY_CHROMA(a) \
+#define VE_DEC_HEVC_LOW_ADDR_SECONDARY_CHROMA(a) \
SHIFT_AND_MASK_BITS(a, 23, 16)
-#define VE_DEC_H265_LOW_ADDR_ENTRY_POINTS_BUF(a) \
+#define VE_DEC_HEVC_LOW_ADDR_ENTRY_POINTS_BUF(a) \
SHIFT_AND_MASK_BITS(a, 7, 0)
-#define VE_DEC_H265_SRAM_OFFSET (VE_ENGINE_DEC_H265 + 0xe0)
+#define VE_DEC_HEVC_SRAM_OFFSET (VE_ENGINE_DEC_HEVC + 0xe0)
-#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0 0x00
-#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0 0x20
-#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1 0x60
-#define VE_DEC_H265_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1 0x80
-#define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO 0x400
-#define VE_DEC_H265_SRAM_OFFSET_FRAME_INFO_UNIT 0x20
-#define VE_DEC_H265_SRAM_OFFSET_SCALING_LISTS 0x800
-#define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST0 0xc00
-#define VE_DEC_H265_SRAM_OFFSET_REF_PIC_LIST1 0xc10
+#define VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_LUMA_L0 0x00
+#define VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L0 0x20
+#define VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_LUMA_L1 0x60
+#define VE_DEC_HEVC_SRAM_OFFSET_PRED_WEIGHT_CHROMA_L1 0x80
+#define VE_DEC_HEVC_SRAM_OFFSET_FRAME_INFO 0x400
+#define VE_DEC_HEVC_SRAM_OFFSET_FRAME_INFO_UNIT 0x20
+#define VE_DEC_HEVC_SRAM_OFFSET_SCALING_LISTS 0x800
+#define VE_DEC_HEVC_SRAM_OFFSET_REF_PIC_LIST0 0xc00
+#define VE_DEC_HEVC_SRAM_OFFSET_REF_PIC_LIST1 0xc10
-#define VE_DEC_H265_SRAM_DATA (VE_ENGINE_DEC_H265 + 0xe4)
+#define VE_DEC_HEVC_SRAM_DATA (VE_ENGINE_DEC_HEVC + 0xe4)
-#define VE_DEC_H265_SRAM_DATA_ADDR_BASE(a) ((a) >> 8)
-#define VE_DEC_H265_SRAM_REF_PIC_LIST_LT_REF BIT(7)
+#define VE_DEC_HEVC_SRAM_DATA_ADDR_BASE(a) ((a) >> 8)
+#define VE_DEC_HEVC_SRAM_REF_PIC_LIST_LT_REF BIT(7)
#define VE_H264_SPS 0x200
#define VE_H264_SPS_MBS_ONLY BIT(18)
diff --git a/drivers/staging/media/sunxi/cedrus/cedrus_video.c b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
index 33726175d980..384b9fa08423 100644
--- a/drivers/staging/media/sunxi/cedrus/cedrus_video.c
+++ b/drivers/staging/media/sunxi/cedrus/cedrus_video.c
@@ -48,7 +48,7 @@ static struct cedrus_format cedrus_formats[] = {
{
.pixelformat = V4L2_PIX_FMT_HEVC_SLICE,
.directions = CEDRUS_DECODE_SRC,
- .capabilities = CEDRUS_CAPABILITY_H265_DEC,
+ .capabilities = CEDRUS_CAPABILITY_HEVC_DEC,
},
{
.pixelformat = V4L2_PIX_FMT_VP8_FRAME,
@@ -485,7 +485,7 @@ static int cedrus_start_streaming(struct vb2_queue *vq, unsigned int count)
break;
case V4L2_PIX_FMT_HEVC_SLICE:
- ctx->current_codec = CEDRUS_CODEC_H265;
+ ctx->current_codec = CEDRUS_CODEC_HEVC;
break;
case V4L2_PIX_FMT_VP8_FRAME:
--
2.25.1
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^ permalink raw reply related [flat|nested] 12+ messages in thread
* Re: [RFC PATCH v3 2/2] staging: media: cedrus: Rename H265 to HEVC
2022-03-27 8:43 ` Sebastian Fricke
@ 2022-03-28 17:09 ` Jernej Škrabec
-1 siblings, 0 replies; 12+ messages in thread
From: Jernej Škrabec @ 2022-03-28 17:09 UTC (permalink / raw)
To: linux-media, Sebastian Fricke
Cc: acourbot, tfiga, hverkuil-cisco, Sebastian Fricke, Maxime Ripard,
Paul Kocialkowski, Mauro Carvalho Chehab, Greg Kroah-Hartman,
Chen-Yu Tsai, open list:STAGING SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support,
open list:ARM/Allwinner sunXi SoC support, open list
Hi Sebastian!
Dne nedelja, 27. marec 2022 ob 10:43:10 CEST je Sebastian Fricke napisal(a):
> Rename all instances where the identifier H265 is used with HEVC.
> The codec has multiple identifiers H.265 (ITU-T), MPEG-H Part 2 (ISO),
> but the actual name of the codec is HEVC (High Efficiency Video Coding).
> Also nearly all other related drivers use the term HEVC instead of H265.
>
> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
This patch is not constructive. I admit, it's unfortunate it's not using same
name as other drivers, but anyone dealing with HEVC will know H265 is synonym
for it. This patch doesn't improve anything and actually makes any fix harder
to backport, if something cames up. According to diffstat, this rewrites more
than 50% of cedrus_h265.c, including renaming the file. Additionally, it's easy
to miss something to rename and we could play this game in the future too, for
no real benefit.
So NAK.
Best regard,
Jernej
P.S. Please wait at least few days before resending patches, even if you find
something. After all, RFC patches are meant to get some response, it's not
expected they will be perfect.
> ---
> drivers/staging/media/sunxi/cedrus/Makefile | 2 +-
> drivers/staging/media/sunxi/cedrus/cedrus.c | 30 +-
> drivers/staging/media/sunxi/cedrus/cedrus.h | 14 +-
> .../staging/media/sunxi/cedrus/cedrus_dec.c | 10 +-
> .../cedrus/{cedrus_h265.c => cedrus_hevc.c} | 438 +++++++++---------
> .../staging/media/sunxi/cedrus/cedrus_hw.c | 4 +-
> .../staging/media/sunxi/cedrus/cedrus_regs.h | 394 ++++++++--------
> .../staging/media/sunxi/cedrus/cedrus_video.c | 4 +-
> 8 files changed, 448 insertions(+), 448 deletions(-)
> rename drivers/staging/media/sunxi/cedrus/{cedrus_h265.c => cedrus_hevc.c}
> (53%)
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC PATCH v3 2/2] staging: media: cedrus: Rename H265 to HEVC
@ 2022-03-28 17:09 ` Jernej Škrabec
0 siblings, 0 replies; 12+ messages in thread
From: Jernej Škrabec @ 2022-03-28 17:09 UTC (permalink / raw)
To: linux-media, Sebastian Fricke
Cc: acourbot, tfiga, hverkuil-cisco, Sebastian Fricke, Maxime Ripard,
Paul Kocialkowski, Mauro Carvalho Chehab, Greg Kroah-Hartman,
Chen-Yu Tsai, open list:STAGING SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support,
open list:ARM/Allwinner sunXi SoC support, open list
Hi Sebastian!
Dne nedelja, 27. marec 2022 ob 10:43:10 CEST je Sebastian Fricke napisal(a):
> Rename all instances where the identifier H265 is used with HEVC.
> The codec has multiple identifiers H.265 (ITU-T), MPEG-H Part 2 (ISO),
> but the actual name of the codec is HEVC (High Efficiency Video Coding).
> Also nearly all other related drivers use the term HEVC instead of H265.
>
> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
This patch is not constructive. I admit, it's unfortunate it's not using same
name as other drivers, but anyone dealing with HEVC will know H265 is synonym
for it. This patch doesn't improve anything and actually makes any fix harder
to backport, if something cames up. According to diffstat, this rewrites more
than 50% of cedrus_h265.c, including renaming the file. Additionally, it's easy
to miss something to rename and we could play this game in the future too, for
no real benefit.
So NAK.
Best regard,
Jernej
P.S. Please wait at least few days before resending patches, even if you find
something. After all, RFC patches are meant to get some response, it's not
expected they will be perfect.
> ---
> drivers/staging/media/sunxi/cedrus/Makefile | 2 +-
> drivers/staging/media/sunxi/cedrus/cedrus.c | 30 +-
> drivers/staging/media/sunxi/cedrus/cedrus.h | 14 +-
> .../staging/media/sunxi/cedrus/cedrus_dec.c | 10 +-
> .../cedrus/{cedrus_h265.c => cedrus_hevc.c} | 438 +++++++++---------
> .../staging/media/sunxi/cedrus/cedrus_hw.c | 4 +-
> .../staging/media/sunxi/cedrus/cedrus_regs.h | 394 ++++++++--------
> .../staging/media/sunxi/cedrus/cedrus_video.c | 4 +-
> 8 files changed, 448 insertions(+), 448 deletions(-)
> rename drivers/staging/media/sunxi/cedrus/{cedrus_h265.c => cedrus_hevc.c}
> (53%)
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC PATCH v3 1/2] media: docs-rst: Append HEVC specific term
2022-03-27 8:43 ` Sebastian Fricke
@ 2022-03-28 17:10 ` Jernej Škrabec
-1 siblings, 0 replies; 12+ messages in thread
From: Jernej Škrabec @ 2022-03-28 17:10 UTC (permalink / raw)
To: linux-media, Sebastian Fricke
Cc: acourbot, tfiga, hverkuil-cisco, Sebastian Fricke,
Mauro Carvalho Chehab, Maxime Ripard, Paul Kocialkowski,
Greg Kroah-Hartman, Chen-Yu Tsai, open list,
open list:STAGING SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support,
open list:ARM/Allwinner sunXi SoC support
Dne nedelja, 27. marec 2022 ob 10:43:08 CEST je Sebastian Fricke napisal(a):
> Describe the coding tree unit as replacement for the macroblock in the
> HEVC codec. Highlight a key difference of the HEVC codec to predecessors
> like AVC(H.264) to give a better overview of the differences between the
> coding standards.
>
Looks good to me.
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
> ---
> Documentation/userspace-api/media/v4l/dev-decoder.rst | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/userspace-api/media/v4l/dev-decoder.rst
> b/Documentation/userspace-api/media/v4l/dev-decoder.rst index
> 3cf2b496f2d0..eb5b1b1e3a51 100644
> --- a/Documentation/userspace-api/media/v4l/dev-decoder.rst
> +++ b/Documentation/userspace-api/media/v4l/dev-decoder.rst
> @@ -72,6 +72,11 @@ coded resolution
> coded width
> width for given coded resolution.
>
> +coding tree unit
> + processing unit of the HEVC codec (≘ macroblock units in H.264, VP8,
> VP9); + can use block structures of up to 64×64 pixels;
> + Good at sub-partitioning the picture into variable sized structures.
> +
> decode order
> the order in which frames are decoded; may differ from display order if
> the coded format includes a feature of frame reordering; for decoders, @@
> -104,7 +109,8 @@ keyframe
> macroblock
> a processing unit in image and video compression formats based on linear
> block transforms (e.g. H.264, VP8, VP9); codec-specific, but for most of -
> popular codecs the size is 16x16 samples (pixels).
> + popular codecs the size is 16x16 samples (pixels). The HEVC codec uses a
> + slightly more flexible processing unit called coding tree unit (CTU).
>
> OUTPUT
> the source buffer queue; for decoders, the queue of buffers containing
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC PATCH v3 1/2] media: docs-rst: Append HEVC specific term
@ 2022-03-28 17:10 ` Jernej Škrabec
0 siblings, 0 replies; 12+ messages in thread
From: Jernej Škrabec @ 2022-03-28 17:10 UTC (permalink / raw)
To: linux-media, Sebastian Fricke
Cc: acourbot, tfiga, hverkuil-cisco, Sebastian Fricke,
Mauro Carvalho Chehab, Maxime Ripard, Paul Kocialkowski,
Greg Kroah-Hartman, Chen-Yu Tsai, open list,
open list:STAGING SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support,
open list:ARM/Allwinner sunXi SoC support
Dne nedelja, 27. marec 2022 ob 10:43:08 CEST je Sebastian Fricke napisal(a):
> Describe the coding tree unit as replacement for the macroblock in the
> HEVC codec. Highlight a key difference of the HEVC codec to predecessors
> like AVC(H.264) to give a better overview of the differences between the
> coding standards.
>
Looks good to me.
Acked-by: Jernej Skrabec <jernej.skrabec@gmail.com>
Best regards,
Jernej
> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
> ---
> Documentation/userspace-api/media/v4l/dev-decoder.rst | 8 +++++++-
> 1 file changed, 7 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/userspace-api/media/v4l/dev-decoder.rst
> b/Documentation/userspace-api/media/v4l/dev-decoder.rst index
> 3cf2b496f2d0..eb5b1b1e3a51 100644
> --- a/Documentation/userspace-api/media/v4l/dev-decoder.rst
> +++ b/Documentation/userspace-api/media/v4l/dev-decoder.rst
> @@ -72,6 +72,11 @@ coded resolution
> coded width
> width for given coded resolution.
>
> +coding tree unit
> + processing unit of the HEVC codec (≘ macroblock units in H.264, VP8,
> VP9); + can use block structures of up to 64×64 pixels;
> + Good at sub-partitioning the picture into variable sized structures.
> +
> decode order
> the order in which frames are decoded; may differ from display order if
> the coded format includes a feature of frame reordering; for decoders, @@
> -104,7 +109,8 @@ keyframe
> macroblock
> a processing unit in image and video compression formats based on linear
> block transforms (e.g. H.264, VP8, VP9); codec-specific, but for most of -
> popular codecs the size is 16x16 samples (pixels).
> + popular codecs the size is 16x16 samples (pixels). The HEVC codec uses a
> + slightly more flexible processing unit called coding tree unit (CTU).
>
> OUTPUT
> the source buffer queue; for decoders, the queue of buffers containing
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC PATCH v3 2/2] staging: media: cedrus: Rename H265 to HEVC
2022-03-28 17:09 ` Jernej Škrabec
@ 2022-03-29 6:53 ` Sebastian Fricke
-1 siblings, 0 replies; 12+ messages in thread
From: Sebastian Fricke @ 2022-03-29 6:53 UTC (permalink / raw)
To: Jernej Škrabec
Cc: linux-media, acourbot, tfiga, hverkuil-cisco, Maxime Ripard,
Paul Kocialkowski, Mauro Carvalho Chehab, Greg Kroah-Hartman,
Chen-Yu Tsai, open list:STAGING SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support,
open list:ARM/Allwinner sunXi SoC support, open list
Hey Jernej,
On 28.03.2022 19:09, Jernej Škrabec wrote:
>Hi Sebastian!
>
>Dne nedelja, 27. marec 2022 ob 10:43:10 CEST je Sebastian Fricke napisal(a):
>> Rename all instances where the identifier H265 is used with HEVC.
>> The codec has multiple identifiers H.265 (ITU-T), MPEG-H Part 2 (ISO),
>> but the actual name of the codec is HEVC (High Efficiency Video Coding).
>> Also nearly all other related drivers use the term HEVC instead of H265.
>>
>> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
>
>This patch is not constructive. I admit, it's unfortunate it's not using same
>name as other drivers, but anyone dealing with HEVC will know H265 is synonym
>for it. This patch doesn't improve anything and actually makes any fix harder
>to backport, if something cames up. According to diffstat, this rewrites more
>than 50% of cedrus_h265.c, including renaming the file. Additionally, it's easy
>to miss something to rename and we could play this game in the future too, for
>no real benefit.
>
>So NAK.
Alright, thank you for presenting your view on that topic. I'll drop this patch.
>
>Best regard,
>Jernej
>
>P.S. Please wait at least few days before resending patches, even if you find
>something. After all, RFC patches are meant to get some response, it's not
>expected they will be perfect.
Thanks for the tip, I'll be honest, I was bascically just ashamed that I
missed those variables even after extensive grepping that I thought I
better fix this up quickly instead of dumping trash on the mailing list.
Greetings,
Sebastian
>
>> ---
>> drivers/staging/media/sunxi/cedrus/Makefile | 2 +-
>> drivers/staging/media/sunxi/cedrus/cedrus.c | 30 +-
>> drivers/staging/media/sunxi/cedrus/cedrus.h | 14 +-
>> .../staging/media/sunxi/cedrus/cedrus_dec.c | 10 +-
>> .../cedrus/{cedrus_h265.c => cedrus_hevc.c} | 438 +++++++++---------
>> .../staging/media/sunxi/cedrus/cedrus_hw.c | 4 +-
>> .../staging/media/sunxi/cedrus/cedrus_regs.h | 394 ++++++++--------
>> .../staging/media/sunxi/cedrus/cedrus_video.c | 4 +-
>> 8 files changed, 448 insertions(+), 448 deletions(-)
>> rename drivers/staging/media/sunxi/cedrus/{cedrus_h265.c => cedrus_hevc.c}
>> (53%)
>
>
>
^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [RFC PATCH v3 2/2] staging: media: cedrus: Rename H265 to HEVC
@ 2022-03-29 6:53 ` Sebastian Fricke
0 siblings, 0 replies; 12+ messages in thread
From: Sebastian Fricke @ 2022-03-29 6:53 UTC (permalink / raw)
To: Jernej Škrabec
Cc: linux-media, acourbot, tfiga, hverkuil-cisco, Maxime Ripard,
Paul Kocialkowski, Mauro Carvalho Chehab, Greg Kroah-Hartman,
Chen-Yu Tsai, open list:STAGING SUBSYSTEM,
moderated list:ARM/Allwinner sunXi SoC support,
open list:ARM/Allwinner sunXi SoC support, open list
Hey Jernej,
On 28.03.2022 19:09, Jernej Škrabec wrote:
>Hi Sebastian!
>
>Dne nedelja, 27. marec 2022 ob 10:43:10 CEST je Sebastian Fricke napisal(a):
>> Rename all instances where the identifier H265 is used with HEVC.
>> The codec has multiple identifiers H.265 (ITU-T), MPEG-H Part 2 (ISO),
>> but the actual name of the codec is HEVC (High Efficiency Video Coding).
>> Also nearly all other related drivers use the term HEVC instead of H265.
>>
>> Signed-off-by: Sebastian Fricke <sebastian.fricke@collabora.com>
>
>This patch is not constructive. I admit, it's unfortunate it's not using same
>name as other drivers, but anyone dealing with HEVC will know H265 is synonym
>for it. This patch doesn't improve anything and actually makes any fix harder
>to backport, if something cames up. According to diffstat, this rewrites more
>than 50% of cedrus_h265.c, including renaming the file. Additionally, it's easy
>to miss something to rename and we could play this game in the future too, for
>no real benefit.
>
>So NAK.
Alright, thank you for presenting your view on that topic. I'll drop this patch.
>
>Best regard,
>Jernej
>
>P.S. Please wait at least few days before resending patches, even if you find
>something. After all, RFC patches are meant to get some response, it's not
>expected they will be perfect.
Thanks for the tip, I'll be honest, I was bascically just ashamed that I
missed those variables even after extensive grepping that I thought I
better fix this up quickly instead of dumping trash on the mailing list.
Greetings,
Sebastian
>
>> ---
>> drivers/staging/media/sunxi/cedrus/Makefile | 2 +-
>> drivers/staging/media/sunxi/cedrus/cedrus.c | 30 +-
>> drivers/staging/media/sunxi/cedrus/cedrus.h | 14 +-
>> .../staging/media/sunxi/cedrus/cedrus_dec.c | 10 +-
>> .../cedrus/{cedrus_h265.c => cedrus_hevc.c} | 438 +++++++++---------
>> .../staging/media/sunxi/cedrus/cedrus_hw.c | 4 +-
>> .../staging/media/sunxi/cedrus/cedrus_regs.h | 394 ++++++++--------
>> .../staging/media/sunxi/cedrus/cedrus_video.c | 4 +-
>> 8 files changed, 448 insertions(+), 448 deletions(-)
>> rename drivers/staging/media/sunxi/cedrus/{cedrus_h265.c => cedrus_hevc.c}
>> (53%)
>
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-03-29 6:55 UTC | newest]
Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-27 8:43 [RFC PATCH v3 0/2] HEVC enhancements Sebastian Fricke
2022-03-27 8:43 ` Sebastian Fricke
2022-03-27 8:43 ` [RFC PATCH v3 1/2] media: docs-rst: Append HEVC specific term Sebastian Fricke
2022-03-27 8:43 ` Sebastian Fricke
2022-03-28 17:10 ` Jernej Škrabec
2022-03-28 17:10 ` Jernej Škrabec
2022-03-27 8:43 ` [RFC PATCH v3 2/2] staging: media: cedrus: Rename H265 to HEVC Sebastian Fricke
2022-03-27 8:43 ` Sebastian Fricke
2022-03-28 17:09 ` Jernej Škrabec
2022-03-28 17:09 ` Jernej Škrabec
2022-03-29 6:53 ` Sebastian Fricke
2022-03-29 6:53 ` Sebastian Fricke
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