* [PATCH v12 0/3] Add basic SoC support for mediatek mt8195
@ 2022-03-29 11:45 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-29 11:45 UTC (permalink / raw)
To: Chaotian Jing, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun, Tinghan Shen
This series adds basic SoC support for Mediatek's SoC MT8195.
---
Changes in v12:
- update mtk-sd.yaml to extend reg property and fix yamllint error
- add xhci nodes and move xhci3 property (usb2-lpm-disable) to evb.dts
Changes in v11:
- rebase on 5.17-rc4
Changes in v10:
- clean CC list
Changes in v9:
- remove duplicated cpus dt-bindings patch in v8
Changes in v8:
- v7 mediatek,spi-mtk-nor.yaml patch is applied in branch for-5.17 at
kernel/git/broonie/spi.git
- v7 pinctrl-mt8195.yaml patch is applied in branch for-next at
kernel/git/linusw/linux-pinctrl.git
- add cortex-a78 compatible to cpus dt-bindings
- add mediatek,drive-strength-adv property to pinctrl dt-bindings
- fix evb dts
- remove i2c nodes with disabled status from dts
- fix pin properties not match pinctrl dt-bindings
- remove unnecessary u3port*
- fix dtsi
- fix node format
- reorder oscillator* nodes
- fix node name of cpu idle nodes
- remove clock-frequency property in the timer node
- reorder clock and clock names in usb nodes
Changes in v7:
- refine title of spi-nor dt-bindings patch
- refine commit message of pinctrl dt-bindings patch
- update pinctrl-mt8195.yaml
- change property pattern from 'pins' to '^pins'
- update examples with new property in descriptions
- add new example
- drop '_' from node names of pinctrl subnodes in mt8195-evb.dts
Changes in v6:
- rebase on 5.16-rc1
- add new clock name to spi-nor dt-bindings
- add "pins" property in pinctrl dt-bindings
- fix fails of dtbs_checks
- remove "arm,armv8" not matched in yaml from cpu compatile
- fix node name of xhci
- remvoe xhci upstreaming wakeup properties
- remove xhci unused properties address-cells and size-cells
- fix node name of ufs-phy
- fix node name of spi-nor
- fix node name and sub-nodes of pinctrl
- fix mmc compatible
Changes in v5:
- enable basic nodes in mt8195-evb.dts
- remove dedicated clock nodes
- add mmc2 node
- fix interrupt number of pinctrl node
- update clock nodes to apply internal fixes
- add dt-bindings for perficfg node
v4 thread:
https://lore.kernel.org/all/20210922093303.23720-2-seiya.wang@mediatek.com/
v3 thread:
https://lore.kernel.org/all/20210601075350.31515-2-seiya.wang@mediatek.com/
v2 thread:
https://lore.kernel.org/all/20210319023427.16711-10-seiya.wang@mediatek.com/
v1 thread:
https://lore.kernel.org/all/20210316111443.3332-11-seiya.wang@mediatek.com/
---
Tinghan Shen (3):
dt-bindings: mmc: mtk-sd: fix yamllint error
dt-bindings: mmc: mtk-sd: increase reg maxItems
arm64: dts: Add mediatek SoC mt8195 and evaluation board
.../devicetree/bindings/mmc/mtk-sd.yaml | 6 +-
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 173 +++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1045 +++++++++++++++++
4 files changed, 1223 insertions(+), 2 deletions(-)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi
--
2.18.0
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v12 0/3] Add basic SoC support for mediatek mt8195
@ 2022-03-29 11:45 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-29 11:45 UTC (permalink / raw)
To: Chaotian Jing, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun, Tinghan Shen
This series adds basic SoC support for Mediatek's SoC MT8195.
---
Changes in v12:
- update mtk-sd.yaml to extend reg property and fix yamllint error
- add xhci nodes and move xhci3 property (usb2-lpm-disable) to evb.dts
Changes in v11:
- rebase on 5.17-rc4
Changes in v10:
- clean CC list
Changes in v9:
- remove duplicated cpus dt-bindings patch in v8
Changes in v8:
- v7 mediatek,spi-mtk-nor.yaml patch is applied in branch for-5.17 at
kernel/git/broonie/spi.git
- v7 pinctrl-mt8195.yaml patch is applied in branch for-next at
kernel/git/linusw/linux-pinctrl.git
- add cortex-a78 compatible to cpus dt-bindings
- add mediatek,drive-strength-adv property to pinctrl dt-bindings
- fix evb dts
- remove i2c nodes with disabled status from dts
- fix pin properties not match pinctrl dt-bindings
- remove unnecessary u3port*
- fix dtsi
- fix node format
- reorder oscillator* nodes
- fix node name of cpu idle nodes
- remove clock-frequency property in the timer node
- reorder clock and clock names in usb nodes
Changes in v7:
- refine title of spi-nor dt-bindings patch
- refine commit message of pinctrl dt-bindings patch
- update pinctrl-mt8195.yaml
- change property pattern from 'pins' to '^pins'
- update examples with new property in descriptions
- add new example
- drop '_' from node names of pinctrl subnodes in mt8195-evb.dts
Changes in v6:
- rebase on 5.16-rc1
- add new clock name to spi-nor dt-bindings
- add "pins" property in pinctrl dt-bindings
- fix fails of dtbs_checks
- remove "arm,armv8" not matched in yaml from cpu compatile
- fix node name of xhci
- remvoe xhci upstreaming wakeup properties
- remove xhci unused properties address-cells and size-cells
- fix node name of ufs-phy
- fix node name of spi-nor
- fix node name and sub-nodes of pinctrl
- fix mmc compatible
Changes in v5:
- enable basic nodes in mt8195-evb.dts
- remove dedicated clock nodes
- add mmc2 node
- fix interrupt number of pinctrl node
- update clock nodes to apply internal fixes
- add dt-bindings for perficfg node
v4 thread:
https://lore.kernel.org/all/20210922093303.23720-2-seiya.wang@mediatek.com/
v3 thread:
https://lore.kernel.org/all/20210601075350.31515-2-seiya.wang@mediatek.com/
v2 thread:
https://lore.kernel.org/all/20210319023427.16711-10-seiya.wang@mediatek.com/
v1 thread:
https://lore.kernel.org/all/20210316111443.3332-11-seiya.wang@mediatek.com/
---
Tinghan Shen (3):
dt-bindings: mmc: mtk-sd: fix yamllint error
dt-bindings: mmc: mtk-sd: increase reg maxItems
arm64: dts: Add mediatek SoC mt8195 and evaluation board
.../devicetree/bindings/mmc/mtk-sd.yaml | 6 +-
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 173 +++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1045 +++++++++++++++++
4 files changed, 1223 insertions(+), 2 deletions(-)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v12 0/3] Add basic SoC support for mediatek mt8195
@ 2022-03-29 11:45 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-29 11:45 UTC (permalink / raw)
To: Chaotian Jing, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun, Tinghan Shen
This series adds basic SoC support for Mediatek's SoC MT8195.
---
Changes in v12:
- update mtk-sd.yaml to extend reg property and fix yamllint error
- add xhci nodes and move xhci3 property (usb2-lpm-disable) to evb.dts
Changes in v11:
- rebase on 5.17-rc4
Changes in v10:
- clean CC list
Changes in v9:
- remove duplicated cpus dt-bindings patch in v8
Changes in v8:
- v7 mediatek,spi-mtk-nor.yaml patch is applied in branch for-5.17 at
kernel/git/broonie/spi.git
- v7 pinctrl-mt8195.yaml patch is applied in branch for-next at
kernel/git/linusw/linux-pinctrl.git
- add cortex-a78 compatible to cpus dt-bindings
- add mediatek,drive-strength-adv property to pinctrl dt-bindings
- fix evb dts
- remove i2c nodes with disabled status from dts
- fix pin properties not match pinctrl dt-bindings
- remove unnecessary u3port*
- fix dtsi
- fix node format
- reorder oscillator* nodes
- fix node name of cpu idle nodes
- remove clock-frequency property in the timer node
- reorder clock and clock names in usb nodes
Changes in v7:
- refine title of spi-nor dt-bindings patch
- refine commit message of pinctrl dt-bindings patch
- update pinctrl-mt8195.yaml
- change property pattern from 'pins' to '^pins'
- update examples with new property in descriptions
- add new example
- drop '_' from node names of pinctrl subnodes in mt8195-evb.dts
Changes in v6:
- rebase on 5.16-rc1
- add new clock name to spi-nor dt-bindings
- add "pins" property in pinctrl dt-bindings
- fix fails of dtbs_checks
- remove "arm,armv8" not matched in yaml from cpu compatile
- fix node name of xhci
- remvoe xhci upstreaming wakeup properties
- remove xhci unused properties address-cells and size-cells
- fix node name of ufs-phy
- fix node name of spi-nor
- fix node name and sub-nodes of pinctrl
- fix mmc compatible
Changes in v5:
- enable basic nodes in mt8195-evb.dts
- remove dedicated clock nodes
- add mmc2 node
- fix interrupt number of pinctrl node
- update clock nodes to apply internal fixes
- add dt-bindings for perficfg node
v4 thread:
https://lore.kernel.org/all/20210922093303.23720-2-seiya.wang@mediatek.com/
v3 thread:
https://lore.kernel.org/all/20210601075350.31515-2-seiya.wang@mediatek.com/
v2 thread:
https://lore.kernel.org/all/20210319023427.16711-10-seiya.wang@mediatek.com/
v1 thread:
https://lore.kernel.org/all/20210316111443.3332-11-seiya.wang@mediatek.com/
---
Tinghan Shen (3):
dt-bindings: mmc: mtk-sd: fix yamllint error
dt-bindings: mmc: mtk-sd: increase reg maxItems
arm64: dts: Add mediatek SoC mt8195 and evaluation board
.../devicetree/bindings/mmc/mtk-sd.yaml | 6 +-
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 173 +++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1045 +++++++++++++++++
4 files changed, 1223 insertions(+), 2 deletions(-)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* [PATCH v12 1/3] dt-bindings: mmc: mtk-sd: fix yamllint error
2022-03-29 11:45 ` Tinghan Shen
(?)
@ 2022-03-29 11:45 ` Tinghan Shen
-1 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-29 11:45 UTC (permalink / raw)
To: Chaotian Jing, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun, Tinghan Shen
Documentation/devicetree/bindings/mmc/mtk-sd.yaml
54:81 error line too long (95 > 80 characters) (line-length)
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 297ada03e3de..7032f7adf3ca 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -50,7 +50,8 @@ properties:
- description: source clock (required).
- description: HCLK which used for host (required).
- description: independent source clock gate (required for MT2712).
- - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
+ - description: bus clock used for internal register access
+ (required for MT2712 MSDC0/3).
- description: msdc subsys clock gate (required for MT8192).
- description: peripheral bus clock gate (required for MT8192).
- description: AXI bus clock gate (required for MT8192).
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v12 1/3] dt-bindings: mmc: mtk-sd: fix yamllint error
@ 2022-03-29 11:45 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-29 11:45 UTC (permalink / raw)
To: Chaotian Jing, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun, Tinghan Shen
Documentation/devicetree/bindings/mmc/mtk-sd.yaml
54:81 error line too long (95 > 80 characters) (line-length)
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 297ada03e3de..7032f7adf3ca 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -50,7 +50,8 @@ properties:
- description: source clock (required).
- description: HCLK which used for host (required).
- description: independent source clock gate (required for MT2712).
- - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
+ - description: bus clock used for internal register access
+ (required for MT2712 MSDC0/3).
- description: msdc subsys clock gate (required for MT8192).
- description: peripheral bus clock gate (required for MT8192).
- description: AXI bus clock gate (required for MT8192).
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v12 1/3] dt-bindings: mmc: mtk-sd: fix yamllint error
@ 2022-03-29 11:45 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-29 11:45 UTC (permalink / raw)
To: Chaotian Jing, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun, Tinghan Shen
Documentation/devicetree/bindings/mmc/mtk-sd.yaml
54:81 error line too long (95 > 80 characters) (line-length)
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 297ada03e3de..7032f7adf3ca 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -50,7 +50,8 @@ properties:
- description: source clock (required).
- description: HCLK which used for host (required).
- description: independent source clock gate (required for MT2712).
- - description: bus clock used for internal register access (required for MT2712 MSDC0/3).
+ - description: bus clock used for internal register access
+ (required for MT2712 MSDC0/3).
- description: msdc subsys clock gate (required for MT8192).
- description: peripheral bus clock gate (required for MT8192).
- description: AXI bus clock gate (required for MT8192).
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
2022-03-29 11:45 ` Tinghan Shen
(?)
@ 2022-03-29 11:45 ` Tinghan Shen
-1 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-29 11:45 UTC (permalink / raw)
To: Chaotian Jing, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun, Tinghan Shen
Add optional host top register base for the reg binding description.
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 7032f7adf3ca..6d41bcec900f 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -40,7 +40,8 @@ properties:
- const: mediatek,mt8183-mmc
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
clocks:
description:
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-29 11:45 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-29 11:45 UTC (permalink / raw)
To: Chaotian Jing, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun, Tinghan Shen
Add optional host top register base for the reg binding description.
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 7032f7adf3ca..6d41bcec900f 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -40,7 +40,8 @@ properties:
- const: mediatek,mt8183-mmc
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
clocks:
description:
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-29 11:45 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-29 11:45 UTC (permalink / raw)
To: Chaotian Jing, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun, Tinghan Shen
Add optional host top register base for the reg binding description.
Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
---
Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
index 7032f7adf3ca..6d41bcec900f 100644
--- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
+++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
@@ -40,7 +40,8 @@ properties:
- const: mediatek,mt8183-mmc
reg:
- maxItems: 1
+ minItems: 1
+ maxItems: 2
clocks:
description:
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v12 3/3] arm64: dts: Add mediatek SoC mt8195 and evaluation board
2022-03-29 11:45 ` Tinghan Shen
(?)
@ 2022-03-29 11:45 ` Tinghan Shen
-1 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-29 11:45 UTC (permalink / raw)
To: Chaotian Jing, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun, Tinghan Shen, Seiya Wang
Add basic chip support for mediatek mt8195.
Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 173 +++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1045 +++++++++++++++++++
3 files changed, 1219 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 8c1e18032f9f..5da29e7223e4 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -38,4 +38,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
new file mode 100644
index 000000000000..76b5aaad7263
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Seiya Wang <seiya.wang@mediatek.com>
+ */
+/dts-v1/;
+#include "mt8195.dtsi"
+
+/ {
+ model = "MediaTek MT8195 evaluation board";
+ compatible = "mediatek,mt8195-evb", "mediatek,mt8195";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+};
+
+&auxadc {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pin>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pin>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pin>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pin>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&nor_flash {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nor_pins_default>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&pio {
+ i2c0_pin: i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
+ <PINMUX_GPIO9__FUNC_SCL0>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ mediatek,drive-strength-adv = <0>;
+ drive-strength = <6>;
+ };
+ };
+
+ i2c1_pin: i2c1-pins {
+ pins {
+ pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
+ <PINMUX_GPIO11__FUNC_SCL1>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ mediatek,drive-strength-adv = <0>;
+ drive-strength = <6>;
+ };
+ };
+
+ i2c4_pin: i2c4-pins {
+ pins {
+ pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
+ <PINMUX_GPIO17__FUNC_SCL4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ mediatek,drive-strength-adv = <7>;
+ };
+ };
+
+ i2c6_pin: i2c6-pins {
+ pins {
+ pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
+ <PINMUX_GPIO26__FUNC_SCL6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ i2c7_pin: i2c7-pins {
+ pins {
+ pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
+ <PINMUX_GPIO28__FUNC_SDA7>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ nor_pins_default: nor-pins {
+ pins0 {
+ pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
+ <PINMUX_GPIO141__FUNC_SPINOR_CK>,
+ <PINMUX_GPIO143__FUNC_SPINOR_IO1>;
+ bias-pull-down;
+ };
+
+ pins1 {
+ pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>,
+ <PINMUX_GPIO130__FUNC_SPINOR_IO2>,
+ <PINMUX_GPIO131__FUNC_SPINOR_IO3>;
+ bias-pull-up;
+ };
+ };
+
+ uart0_pin: uart0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
+ <PINMUX_GPIO99__FUNC_URXD0>;
+ };
+ };
+};
+
+&u3phy0 {
+ status="okay";
+};
+
+&u3phy1 {
+ status="okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pin>;
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&xhci1 {
+ status = "okay";
+};
+
+&xhci2 {
+ status = "okay";
+};
+
+&xhci3 {
+ /* This controller is connected with a BT device.
+ * Disable usb2 lpm to prevent known issues.
+ */
+ usb2-lpm-disable;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
new file mode 100644
index 000000000000..b57e620c2c72
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -0,0 +1,1045 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Seiya Wang <seiya.wang@mediatek.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
+#include <dt-bindings/reset/ti-syscon.h>
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x000>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x400>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x500>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x600>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x700>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+
+ core1 {
+ cpu = <&cpu5>;
+ };
+
+ core2 {
+ cpu = <&cpu6>;
+ };
+
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_off_l: cpu-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <95>;
+ min-residency-us = <580>;
+ };
+
+ cpu_off_b: cpu-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <45>;
+ exit-latency-us = <140>;
+ min-residency-us = <740>;
+ };
+
+ cluster_off_l: cluster-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010002>;
+ local-timer-stop;
+ entry-latency-us = <55>;
+ exit-latency-us = <155>;
+ min-residency-us = <840>;
+ };
+
+ cluster_off_b: cluster-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010002>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <200>;
+ min-residency-us = <1000>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+
+ dsu-pmu {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
+ cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
+ <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ };
+
+ clk26m: oscillator-26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "clk32k";
+ };
+
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
+ };
+
+ pmu-a78 {
+ compatible = "arm,cortex-a78-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ #redistributor-regions = <1>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>,
+ <0 0x0c040000 0 0x200000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+ };
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8195-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg_ao: syscon@10001000 {
+ compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+
+ infracfg_rst: reset-controller {
+ compatible = "ti,syscon-reset";
+ #reset-cells = <1>;
+ ti,reset-bits = <
+ 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */
+ 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
+ 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
+ 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */
+ >;
+ };
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8195-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt8195-pinctrl";
+ reg = <0 0x10005000 0 0x1000>,
+ <0 0x11d10000 0 0x1000>,
+ <0 0x11d30000 0 0x1000>,
+ <0 0x11d40000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11eb0000 0 0x1000>,
+ <0 0x11f40000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
+ "iocfg_br", "iocfg_lm", "iocfg_rb",
+ "iocfg_tl", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 144>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
+ #interrupt-cells = <2>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8195-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8195-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ systimer: timer@10017000 {
+ compatible = "mediatek,mt8195-timer",
+ "mediatek,mt6765-timer";
+ reg = <0 0x10017000 0 0x1000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_CLK26M_D2>;
+ };
+
+ pwrap: pwrap@10024000 {
+ compatible = "mediatek,mt8195-pwrap", "syscon";
+ reg = <0 0x10024000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+ <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
+ clock-names = "spi", "wrap";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
+ };
+
+ scp_adsp: clock-controller@10720000 {
+ compatible = "mediatek,mt8195-scp_adsp";
+ reg = <0 0x10720000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@11001100 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001100 0 0x100>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11001200 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001200 0 0x100>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11001300 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001300 0 0x100>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart3: serial@11001400 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001400 0 0x100>;
+ interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart4: serial@11001500 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001500 0 0x100>;
+ interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart5: serial@11001600 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001600 0 0x100>;
+ interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ auxadc: auxadc@11002000 {
+ compatible = "mediatek,mt8195-auxadc",
+ "mediatek,mt8173-auxadc";
+ reg = <0 0x11002000 0 0x1000>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ pericfg_ao: syscon@11003000 {
+ compatible = "mediatek,mt8195-pericfg_ao", "syscon";
+ reg = <0 0x11003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ spi0: spi@1100a000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100a000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi1: spi@11010000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11010000 0 0x1000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI1>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi2: spi@11012000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11012000 0 0x1000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI2>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi3: spi@11013000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11013000 0 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI3>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi4: spi@11018000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI4>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi5: spi@11019000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11019000 0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI5>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spis0: spi@1101d000 {
+ compatible = "mediatek,mt8195-spi-slave";
+ reg = <0 0x1101d000 0 0x1000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
+ clock-names = "spi";
+ assigned-clocks = <&topckgen CLK_TOP_SPIS>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+ status = "disabled";
+ };
+
+ spis1: spi@1101e000 {
+ compatible = "mediatek,mt8195-spi-slave";
+ reg = <0 0x1101e000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
+ clock-names = "spi";
+ assigned-clocks = <&topckgen CLK_TOP_SPIS>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+ status = "disabled";
+ };
+
+ xhci0: usb@11200000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&topckgen CLK_TOP_SSUSB_XHCI>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
+ <&topckgen CLK_TOP_SSUSB_REF>,
+ <&apmixedsys CLK_APMIXED_USB1PLL>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x10000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC0>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c70000 0 0x1000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC1>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@11250000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11250000 0 0x1000>,
+ <0 0x11e60000 0 0x1000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_2>,
+ <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
+ <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
+ clock-names = "source", "hclk", "source_cg";
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ status = "disabled";
+ };
+
+ xhci1: usb@11290000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11290000 0 0x1000>,
+ <0 0x11293e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port1 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_P1_REF>,
+ <&apmixedsys CLK_APMIXED_USB1PLL>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck";
+ status = "disabled";
+ };
+
+ xhci2: usb@112a0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112a0000 0 0x1000>,
+ <0 0x112a3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_P2_REF>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "xhci_ck";
+ status = "disabled";
+ };
+
+ xhci3: usb@112b0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112b0000 0 0x1000>,
+ <0 0x112b3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port3 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_P3_REF>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "xhci_ck";
+ status = "disabled";
+ };
+
+ nor_flash: spi@1132c000 {
+ compatible = "mediatek,mt8195-nor",
+ "mediatek,mt8173-nor";
+ reg = <0 0x1132c000 0 0x1000>;
+ interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_SPINOR>,
+ <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
+ <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
+ clock-names = "spi", "sf", "axi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ u3phy2: t-phy@11c40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c40000 0x700>;
+ status = "disabled";
+
+ u2port2: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy3: t-phy@11c50000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c50000 0x700>;
+ status = "disabled";
+
+ u2port3: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ i2c5: i2c@11d00000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11d00000 0 0x1000>,
+ <0 0x10220580 0 0x80>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@11d01000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11d01000 0 0x1000>,
+ <0 0x10220600 0 0x80>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@11d02000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11d02000 0 0x1000>,
+ <0 0x10220680 0 0x80>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ imp_iic_wrap_s: clock-controller@11d03000 {
+ compatible = "mediatek,mt8195-imp_iic_wrap_s";
+ reg = <0 0x11d03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ i2c0: i2c@11e00000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e00000 0 0x1000>,
+ <0 0x10220080 0 0x80>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ };
+
+ i2c1: i2c@11e01000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e01000 0 0x1000>,
+ <0 0x10220200 0 0x80>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11e02000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e02000 0 0x1000>,
+ <0 0x10220380 0 0x80>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@11e03000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e03000 0 0x1000>,
+ <0 0x10220480 0 0x80>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@11e04000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e04000 0 0x1000>,
+ <0 0x10220500 0 0x80>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ imp_iic_wrap_w: clock-controller@11e05000 {
+ compatible = "mediatek,mt8195-imp_iic_wrap_w";
+ reg = <0 0x11e05000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ u3phy1: t-phy@11e30000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e30000 0xe00>;
+ status = "disabled";
+
+ u2port1: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
+ <&clk26m>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u3port1: usb-phy@700 {
+ reg = <0x700 0x700>;
+ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
+ <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy0: t-phy@11e40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e40000 0xe00>;
+ status = "disabled";
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
+ <&clk26m>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x700>;
+ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
+ <&topckgen CLK_TOP_SSUSB_PHY_REF>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ ufsphy: ufs-phy@11fa0000 {
+ compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
+ reg = <0 0x11fa0000 0 0xc000>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "unipro", "mp";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ mfgcfg: clock-controller@13fbf000 {
+ compatible = "mediatek,mt8195-mfgcfg";
+ reg = <0 0x13fbf000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys: clock-controller@14e00000 {
+ compatible = "mediatek,mt8195-wpesys";
+ reg = <0 0x14e00000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys_vpp0: clock-controller@14e02000 {
+ compatible = "mediatek,mt8195-wpesys_vpp0";
+ reg = <0 0x14e02000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys_vpp1: clock-controller@14e03000 {
+ compatible = "mediatek,mt8195-wpesys_vpp1";
+ reg = <0 0x14e03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: clock-controller@15000000 {
+ compatible = "mediatek,mt8195-imgsys";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_dip_top: clock-controller@15110000 {
+ compatible = "mediatek,mt8195-imgsys1_dip_top";
+ reg = <0 0x15110000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_dip_nr: clock-controller@15130000 {
+ compatible = "mediatek,mt8195-imgsys1_dip_nr";
+ reg = <0 0x15130000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_wpe: clock-controller@15220000 {
+ compatible = "mediatek,mt8195-imgsys1_wpe";
+ reg = <0 0x15220000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipesys: clock-controller@15330000 {
+ compatible = "mediatek,mt8195-ipesys";
+ reg = <0 0x15330000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: clock-controller@16000000 {
+ compatible = "mediatek,mt8195-camsys";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawa: clock-controller@1604f000 {
+ compatible = "mediatek,mt8195-camsys_rawa";
+ reg = <0 0x1604f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_yuva: clock-controller@1606f000 {
+ compatible = "mediatek,mt8195-camsys_yuva";
+ reg = <0 0x1606f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawb: clock-controller@1608f000 {
+ compatible = "mediatek,mt8195-camsys_rawb";
+ reg = <0 0x1608f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_yuvb: clock-controller@160af000 {
+ compatible = "mediatek,mt8195-camsys_yuvb";
+ reg = <0 0x160af000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_mraw: clock-controller@16140000 {
+ compatible = "mediatek,mt8195-camsys_mraw";
+ reg = <0 0x16140000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ccusys: clock-controller@17200000 {
+ compatible = "mediatek,mt8195-ccusys";
+ reg = <0 0x17200000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_soc: clock-controller@1800f000 {
+ compatible = "mediatek,mt8195-vdecsys_soc";
+ reg = <0 0x1800f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: clock-controller@1802f000 {
+ compatible = "mediatek,mt8195-vdecsys";
+ reg = <0 0x1802f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_core1: clock-controller@1803f000 {
+ compatible = "mediatek,mt8195-vdecsys_core1";
+ reg = <0 0x1803f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apusys_pll: clock-controller@190f3000 {
+ compatible = "mediatek,mt8195-apusys_pll";
+ reg = <0 0x190f3000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: clock-controller@1a000000 {
+ compatible = "mediatek,mt8195-vencsys";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys_core1: clock-controller@1b000000 {
+ compatible = "mediatek,mt8195-vencsys_core1";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+};
--
2.18.0
^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v12 3/3] arm64: dts: Add mediatek SoC mt8195 and evaluation board
@ 2022-03-29 11:45 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-29 11:45 UTC (permalink / raw)
To: Chaotian Jing, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun, Tinghan Shen, Seiya Wang
Add basic chip support for mediatek mt8195.
Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 173 +++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1045 +++++++++++++++++++
3 files changed, 1219 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 8c1e18032f9f..5da29e7223e4 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -38,4 +38,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
new file mode 100644
index 000000000000..76b5aaad7263
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Seiya Wang <seiya.wang@mediatek.com>
+ */
+/dts-v1/;
+#include "mt8195.dtsi"
+
+/ {
+ model = "MediaTek MT8195 evaluation board";
+ compatible = "mediatek,mt8195-evb", "mediatek,mt8195";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+};
+
+&auxadc {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pin>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pin>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pin>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pin>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&nor_flash {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nor_pins_default>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&pio {
+ i2c0_pin: i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
+ <PINMUX_GPIO9__FUNC_SCL0>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ mediatek,drive-strength-adv = <0>;
+ drive-strength = <6>;
+ };
+ };
+
+ i2c1_pin: i2c1-pins {
+ pins {
+ pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
+ <PINMUX_GPIO11__FUNC_SCL1>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ mediatek,drive-strength-adv = <0>;
+ drive-strength = <6>;
+ };
+ };
+
+ i2c4_pin: i2c4-pins {
+ pins {
+ pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
+ <PINMUX_GPIO17__FUNC_SCL4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ mediatek,drive-strength-adv = <7>;
+ };
+ };
+
+ i2c6_pin: i2c6-pins {
+ pins {
+ pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
+ <PINMUX_GPIO26__FUNC_SCL6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ i2c7_pin: i2c7-pins {
+ pins {
+ pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
+ <PINMUX_GPIO28__FUNC_SDA7>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ nor_pins_default: nor-pins {
+ pins0 {
+ pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
+ <PINMUX_GPIO141__FUNC_SPINOR_CK>,
+ <PINMUX_GPIO143__FUNC_SPINOR_IO1>;
+ bias-pull-down;
+ };
+
+ pins1 {
+ pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>,
+ <PINMUX_GPIO130__FUNC_SPINOR_IO2>,
+ <PINMUX_GPIO131__FUNC_SPINOR_IO3>;
+ bias-pull-up;
+ };
+ };
+
+ uart0_pin: uart0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
+ <PINMUX_GPIO99__FUNC_URXD0>;
+ };
+ };
+};
+
+&u3phy0 {
+ status="okay";
+};
+
+&u3phy1 {
+ status="okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pin>;
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&xhci1 {
+ status = "okay";
+};
+
+&xhci2 {
+ status = "okay";
+};
+
+&xhci3 {
+ /* This controller is connected with a BT device.
+ * Disable usb2 lpm to prevent known issues.
+ */
+ usb2-lpm-disable;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
new file mode 100644
index 000000000000..b57e620c2c72
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -0,0 +1,1045 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Seiya Wang <seiya.wang@mediatek.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
+#include <dt-bindings/reset/ti-syscon.h>
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x000>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x400>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x500>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x600>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x700>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+
+ core1 {
+ cpu = <&cpu5>;
+ };
+
+ core2 {
+ cpu = <&cpu6>;
+ };
+
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_off_l: cpu-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <95>;
+ min-residency-us = <580>;
+ };
+
+ cpu_off_b: cpu-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <45>;
+ exit-latency-us = <140>;
+ min-residency-us = <740>;
+ };
+
+ cluster_off_l: cluster-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010002>;
+ local-timer-stop;
+ entry-latency-us = <55>;
+ exit-latency-us = <155>;
+ min-residency-us = <840>;
+ };
+
+ cluster_off_b: cluster-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010002>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <200>;
+ min-residency-us = <1000>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+
+ dsu-pmu {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
+ cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
+ <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ };
+
+ clk26m: oscillator-26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "clk32k";
+ };
+
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
+ };
+
+ pmu-a78 {
+ compatible = "arm,cortex-a78-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ #redistributor-regions = <1>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>,
+ <0 0x0c040000 0 0x200000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+ };
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8195-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg_ao: syscon@10001000 {
+ compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+
+ infracfg_rst: reset-controller {
+ compatible = "ti,syscon-reset";
+ #reset-cells = <1>;
+ ti,reset-bits = <
+ 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */
+ 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
+ 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
+ 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */
+ >;
+ };
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8195-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt8195-pinctrl";
+ reg = <0 0x10005000 0 0x1000>,
+ <0 0x11d10000 0 0x1000>,
+ <0 0x11d30000 0 0x1000>,
+ <0 0x11d40000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11eb0000 0 0x1000>,
+ <0 0x11f40000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
+ "iocfg_br", "iocfg_lm", "iocfg_rb",
+ "iocfg_tl", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 144>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
+ #interrupt-cells = <2>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8195-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8195-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ systimer: timer@10017000 {
+ compatible = "mediatek,mt8195-timer",
+ "mediatek,mt6765-timer";
+ reg = <0 0x10017000 0 0x1000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_CLK26M_D2>;
+ };
+
+ pwrap: pwrap@10024000 {
+ compatible = "mediatek,mt8195-pwrap", "syscon";
+ reg = <0 0x10024000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+ <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
+ clock-names = "spi", "wrap";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
+ };
+
+ scp_adsp: clock-controller@10720000 {
+ compatible = "mediatek,mt8195-scp_adsp";
+ reg = <0 0x10720000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@11001100 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001100 0 0x100>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11001200 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001200 0 0x100>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11001300 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001300 0 0x100>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart3: serial@11001400 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001400 0 0x100>;
+ interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart4: serial@11001500 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001500 0 0x100>;
+ interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart5: serial@11001600 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001600 0 0x100>;
+ interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ auxadc: auxadc@11002000 {
+ compatible = "mediatek,mt8195-auxadc",
+ "mediatek,mt8173-auxadc";
+ reg = <0 0x11002000 0 0x1000>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ pericfg_ao: syscon@11003000 {
+ compatible = "mediatek,mt8195-pericfg_ao", "syscon";
+ reg = <0 0x11003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ spi0: spi@1100a000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100a000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi1: spi@11010000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11010000 0 0x1000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI1>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi2: spi@11012000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11012000 0 0x1000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI2>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi3: spi@11013000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11013000 0 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI3>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi4: spi@11018000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI4>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi5: spi@11019000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11019000 0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI5>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spis0: spi@1101d000 {
+ compatible = "mediatek,mt8195-spi-slave";
+ reg = <0 0x1101d000 0 0x1000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
+ clock-names = "spi";
+ assigned-clocks = <&topckgen CLK_TOP_SPIS>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+ status = "disabled";
+ };
+
+ spis1: spi@1101e000 {
+ compatible = "mediatek,mt8195-spi-slave";
+ reg = <0 0x1101e000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
+ clock-names = "spi";
+ assigned-clocks = <&topckgen CLK_TOP_SPIS>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+ status = "disabled";
+ };
+
+ xhci0: usb@11200000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&topckgen CLK_TOP_SSUSB_XHCI>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
+ <&topckgen CLK_TOP_SSUSB_REF>,
+ <&apmixedsys CLK_APMIXED_USB1PLL>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x10000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC0>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c70000 0 0x1000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC1>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@11250000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11250000 0 0x1000>,
+ <0 0x11e60000 0 0x1000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_2>,
+ <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
+ <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
+ clock-names = "source", "hclk", "source_cg";
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ status = "disabled";
+ };
+
+ xhci1: usb@11290000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11290000 0 0x1000>,
+ <0 0x11293e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port1 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_P1_REF>,
+ <&apmixedsys CLK_APMIXED_USB1PLL>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck";
+ status = "disabled";
+ };
+
+ xhci2: usb@112a0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112a0000 0 0x1000>,
+ <0 0x112a3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_P2_REF>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "xhci_ck";
+ status = "disabled";
+ };
+
+ xhci3: usb@112b0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112b0000 0 0x1000>,
+ <0 0x112b3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port3 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_P3_REF>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "xhci_ck";
+ status = "disabled";
+ };
+
+ nor_flash: spi@1132c000 {
+ compatible = "mediatek,mt8195-nor",
+ "mediatek,mt8173-nor";
+ reg = <0 0x1132c000 0 0x1000>;
+ interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_SPINOR>,
+ <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
+ <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
+ clock-names = "spi", "sf", "axi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ u3phy2: t-phy@11c40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c40000 0x700>;
+ status = "disabled";
+
+ u2port2: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy3: t-phy@11c50000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c50000 0x700>;
+ status = "disabled";
+
+ u2port3: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ i2c5: i2c@11d00000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11d00000 0 0x1000>,
+ <0 0x10220580 0 0x80>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@11d01000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11d01000 0 0x1000>,
+ <0 0x10220600 0 0x80>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@11d02000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11d02000 0 0x1000>,
+ <0 0x10220680 0 0x80>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ imp_iic_wrap_s: clock-controller@11d03000 {
+ compatible = "mediatek,mt8195-imp_iic_wrap_s";
+ reg = <0 0x11d03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ i2c0: i2c@11e00000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e00000 0 0x1000>,
+ <0 0x10220080 0 0x80>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ };
+
+ i2c1: i2c@11e01000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e01000 0 0x1000>,
+ <0 0x10220200 0 0x80>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11e02000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e02000 0 0x1000>,
+ <0 0x10220380 0 0x80>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@11e03000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e03000 0 0x1000>,
+ <0 0x10220480 0 0x80>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@11e04000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e04000 0 0x1000>,
+ <0 0x10220500 0 0x80>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ imp_iic_wrap_w: clock-controller@11e05000 {
+ compatible = "mediatek,mt8195-imp_iic_wrap_w";
+ reg = <0 0x11e05000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ u3phy1: t-phy@11e30000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e30000 0xe00>;
+ status = "disabled";
+
+ u2port1: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
+ <&clk26m>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u3port1: usb-phy@700 {
+ reg = <0x700 0x700>;
+ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
+ <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy0: t-phy@11e40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e40000 0xe00>;
+ status = "disabled";
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
+ <&clk26m>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x700>;
+ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
+ <&topckgen CLK_TOP_SSUSB_PHY_REF>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ ufsphy: ufs-phy@11fa0000 {
+ compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
+ reg = <0 0x11fa0000 0 0xc000>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "unipro", "mp";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ mfgcfg: clock-controller@13fbf000 {
+ compatible = "mediatek,mt8195-mfgcfg";
+ reg = <0 0x13fbf000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys: clock-controller@14e00000 {
+ compatible = "mediatek,mt8195-wpesys";
+ reg = <0 0x14e00000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys_vpp0: clock-controller@14e02000 {
+ compatible = "mediatek,mt8195-wpesys_vpp0";
+ reg = <0 0x14e02000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys_vpp1: clock-controller@14e03000 {
+ compatible = "mediatek,mt8195-wpesys_vpp1";
+ reg = <0 0x14e03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: clock-controller@15000000 {
+ compatible = "mediatek,mt8195-imgsys";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_dip_top: clock-controller@15110000 {
+ compatible = "mediatek,mt8195-imgsys1_dip_top";
+ reg = <0 0x15110000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_dip_nr: clock-controller@15130000 {
+ compatible = "mediatek,mt8195-imgsys1_dip_nr";
+ reg = <0 0x15130000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_wpe: clock-controller@15220000 {
+ compatible = "mediatek,mt8195-imgsys1_wpe";
+ reg = <0 0x15220000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipesys: clock-controller@15330000 {
+ compatible = "mediatek,mt8195-ipesys";
+ reg = <0 0x15330000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: clock-controller@16000000 {
+ compatible = "mediatek,mt8195-camsys";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawa: clock-controller@1604f000 {
+ compatible = "mediatek,mt8195-camsys_rawa";
+ reg = <0 0x1604f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_yuva: clock-controller@1606f000 {
+ compatible = "mediatek,mt8195-camsys_yuva";
+ reg = <0 0x1606f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawb: clock-controller@1608f000 {
+ compatible = "mediatek,mt8195-camsys_rawb";
+ reg = <0 0x1608f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_yuvb: clock-controller@160af000 {
+ compatible = "mediatek,mt8195-camsys_yuvb";
+ reg = <0 0x160af000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_mraw: clock-controller@16140000 {
+ compatible = "mediatek,mt8195-camsys_mraw";
+ reg = <0 0x16140000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ccusys: clock-controller@17200000 {
+ compatible = "mediatek,mt8195-ccusys";
+ reg = <0 0x17200000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_soc: clock-controller@1800f000 {
+ compatible = "mediatek,mt8195-vdecsys_soc";
+ reg = <0 0x1800f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: clock-controller@1802f000 {
+ compatible = "mediatek,mt8195-vdecsys";
+ reg = <0 0x1802f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_core1: clock-controller@1803f000 {
+ compatible = "mediatek,mt8195-vdecsys_core1";
+ reg = <0 0x1803f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apusys_pll: clock-controller@190f3000 {
+ compatible = "mediatek,mt8195-apusys_pll";
+ reg = <0 0x190f3000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: clock-controller@1a000000 {
+ compatible = "mediatek,mt8195-vencsys";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys_core1: clock-controller@1b000000 {
+ compatible = "mediatek,mt8195-vencsys_core1";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+};
--
2.18.0
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^ permalink raw reply related [flat|nested] 39+ messages in thread
* [PATCH v12 3/3] arm64: dts: Add mediatek SoC mt8195 and evaluation board
@ 2022-03-29 11:45 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-29 11:45 UTC (permalink / raw)
To: Chaotian Jing, Ulf Hansson, Rob Herring, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun, Tinghan Shen, Seiya Wang
Add basic chip support for mediatek mt8195.
Signed-off-by: Seiya Wang <seiya.wang@mediatek.com>
Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/Makefile | 1 +
arch/arm64/boot/dts/mediatek/mt8195-evb.dts | 173 +++
arch/arm64/boot/dts/mediatek/mt8195.dtsi | 1045 +++++++++++++++++++
3 files changed, 1219 insertions(+)
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-evb.dts
create mode 100644 arch/arm64/boot/dts/mediatek/mt8195.dtsi
diff --git a/arch/arm64/boot/dts/mediatek/Makefile b/arch/arm64/boot/dts/mediatek/Makefile
index 8c1e18032f9f..5da29e7223e4 100644
--- a/arch/arm64/boot/dts/mediatek/Makefile
+++ b/arch/arm64/boot/dts/mediatek/Makefile
@@ -38,4 +38,5 @@ dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku0.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-kukui-krane-sku176.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8183-pumpkin.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8192-evb.dtb
+dtb-$(CONFIG_ARCH_MEDIATEK) += mt8195-evb.dtb
dtb-$(CONFIG_ARCH_MEDIATEK) += mt8516-pumpkin.dtb
diff --git a/arch/arm64/boot/dts/mediatek/mt8195-evb.dts b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
new file mode 100644
index 000000000000..76b5aaad7263
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8195-evb.dts
@@ -0,0 +1,173 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (C) 2021 MediaTek Inc.
+ * Author: Seiya Wang <seiya.wang@mediatek.com>
+ */
+/dts-v1/;
+#include "mt8195.dtsi"
+
+/ {
+ model = "MediaTek MT8195 evaluation board";
+ compatible = "mediatek,mt8195-evb", "mediatek,mt8195";
+
+ aliases {
+ serial0 = &uart0;
+ };
+
+ chosen {
+ stdout-path = "serial0:921600n8";
+ };
+
+ memory@40000000 {
+ device_type = "memory";
+ reg = <0 0x40000000 0 0x80000000>;
+ };
+};
+
+&auxadc {
+ status = "okay";
+};
+
+&i2c0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c0_pin>;
+ clock-frequency = <100000>;
+ status = "okay";
+};
+
+&i2c1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c1_pin>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4_pin>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&i2c6 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c6_pin>;
+ clock-frequency = <400000>;
+ status = "okay";
+};
+
+&nor_flash {
+ status = "okay";
+ pinctrl-names = "default";
+ pinctrl-0 = <&nor_pins_default>;
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <50000000>;
+ };
+};
+
+&pio {
+ i2c0_pin: i2c0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO8__FUNC_SDA0>,
+ <PINMUX_GPIO9__FUNC_SCL0>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ mediatek,drive-strength-adv = <0>;
+ drive-strength = <6>;
+ };
+ };
+
+ i2c1_pin: i2c1-pins {
+ pins {
+ pinmux = <PINMUX_GPIO10__FUNC_SDA1>,
+ <PINMUX_GPIO11__FUNC_SCL1>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ mediatek,drive-strength-adv = <0>;
+ drive-strength = <6>;
+ };
+ };
+
+ i2c4_pin: i2c4-pins {
+ pins {
+ pinmux = <PINMUX_GPIO16__FUNC_SDA4>,
+ <PINMUX_GPIO17__FUNC_SCL4>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ mediatek,drive-strength-adv = <7>;
+ };
+ };
+
+ i2c6_pin: i2c6-pins {
+ pins {
+ pinmux = <PINMUX_GPIO25__FUNC_SDA6>,
+ <PINMUX_GPIO26__FUNC_SCL6>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ i2c7_pin: i2c7-pins {
+ pins {
+ pinmux = <PINMUX_GPIO27__FUNC_SCL7>,
+ <PINMUX_GPIO28__FUNC_SDA7>;
+ bias-pull-up = <MTK_PUPD_SET_R1R0_01>;
+ };
+ };
+
+ nor_pins_default: nor-pins {
+ pins0 {
+ pinmux = <PINMUX_GPIO142__FUNC_SPINOR_IO0>,
+ <PINMUX_GPIO141__FUNC_SPINOR_CK>,
+ <PINMUX_GPIO143__FUNC_SPINOR_IO1>;
+ bias-pull-down;
+ };
+
+ pins1 {
+ pinmux = <PINMUX_GPIO140__FUNC_SPINOR_CS>,
+ <PINMUX_GPIO130__FUNC_SPINOR_IO2>,
+ <PINMUX_GPIO131__FUNC_SPINOR_IO3>;
+ bias-pull-up;
+ };
+ };
+
+ uart0_pin: uart0-pins {
+ pins {
+ pinmux = <PINMUX_GPIO98__FUNC_UTXD0>,
+ <PINMUX_GPIO99__FUNC_URXD0>;
+ };
+ };
+};
+
+&u3phy0 {
+ status="okay";
+};
+
+&u3phy1 {
+ status="okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_pin>;
+ status = "okay";
+};
+
+&xhci0 {
+ status = "okay";
+};
+
+&xhci1 {
+ status = "okay";
+};
+
+&xhci2 {
+ status = "okay";
+};
+
+&xhci3 {
+ /* This controller is connected with a BT device.
+ * Disable usb2 lpm to prevent known issues.
+ */
+ usb2-lpm-disable;
+ status = "okay";
+};
diff --git a/arch/arm64/boot/dts/mediatek/mt8195.dtsi b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
new file mode 100644
index 000000000000..b57e620c2c72
--- /dev/null
+++ b/arch/arm64/boot/dts/mediatek/mt8195.dtsi
@@ -0,0 +1,1045 @@
+// SPDX-License-Identifier: (GPL-2.0 OR MIT)
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ * Author: Seiya Wang <seiya.wang@mediatek.com>
+ */
+
+/dts-v1/;
+#include <dt-bindings/clock/mt8195-clk.h>
+#include <dt-bindings/interrupt-controller/arm-gic.h>
+#include <dt-bindings/interrupt-controller/irq.h>
+#include <dt-bindings/phy/phy.h>
+#include <dt-bindings/pinctrl/mt8195-pinfunc.h>
+#include <dt-bindings/reset/ti-syscon.h>
+
+/ {
+ compatible = "mediatek,mt8195";
+ interrupt-parent = <&gic>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+
+ cpus {
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ cpu0: cpu@0 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x000>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu1: cpu@100 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x100>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu2: cpu@200 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x200>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu3: cpu@300 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a55";
+ reg = <0x300>;
+ enable-method = "psci";
+ clock-frequency = <1701000000>;
+ capacity-dmips-mhz = <578>;
+ cpu-idle-states = <&cpu_off_l &cluster_off_l>;
+ next-level-cache = <&l2_0>;
+ #cooling-cells = <2>;
+ };
+
+ cpu4: cpu@400 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x400>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu5: cpu@500 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x500>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu6: cpu@600 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x600>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu7: cpu@700 {
+ device_type = "cpu";
+ compatible = "arm,cortex-a78";
+ reg = <0x700>;
+ enable-method = "psci";
+ clock-frequency = <2171000000>;
+ capacity-dmips-mhz = <1024>;
+ cpu-idle-states = <&cpu_off_b &cluster_off_b>;
+ next-level-cache = <&l2_1>;
+ #cooling-cells = <2>;
+ };
+
+ cpu-map {
+ cluster0 {
+ core0 {
+ cpu = <&cpu0>;
+ };
+
+ core1 {
+ cpu = <&cpu1>;
+ };
+
+ core2 {
+ cpu = <&cpu2>;
+ };
+
+ core3 {
+ cpu = <&cpu3>;
+ };
+ };
+
+ cluster1 {
+ core0 {
+ cpu = <&cpu4>;
+ };
+
+ core1 {
+ cpu = <&cpu5>;
+ };
+
+ core2 {
+ cpu = <&cpu6>;
+ };
+
+ core3 {
+ cpu = <&cpu7>;
+ };
+ };
+ };
+
+ idle-states {
+ entry-method = "psci";
+
+ cpu_off_l: cpu-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <95>;
+ min-residency-us = <580>;
+ };
+
+ cpu_off_b: cpu-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x00010001>;
+ local-timer-stop;
+ entry-latency-us = <45>;
+ exit-latency-us = <140>;
+ min-residency-us = <740>;
+ };
+
+ cluster_off_l: cluster-off-l {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010002>;
+ local-timer-stop;
+ entry-latency-us = <55>;
+ exit-latency-us = <155>;
+ min-residency-us = <840>;
+ };
+
+ cluster_off_b: cluster-off-b {
+ compatible = "arm,idle-state";
+ arm,psci-suspend-param = <0x01010002>;
+ local-timer-stop;
+ entry-latency-us = <50>;
+ exit-latency-us = <200>;
+ min-residency-us = <1000>;
+ };
+ };
+
+ l2_0: l2-cache0 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l2_1: l2-cache1 {
+ compatible = "cache";
+ next-level-cache = <&l3_0>;
+ };
+
+ l3_0: l3-cache {
+ compatible = "cache";
+ };
+ };
+
+ dsu-pmu {
+ compatible = "arm,dsu-pmu";
+ interrupts = <GIC_SPI 18 IRQ_TYPE_LEVEL_HIGH 0>;
+ cpus = <&cpu0>, <&cpu1>, <&cpu2>, <&cpu3>,
+ <&cpu4>, <&cpu5>, <&cpu6>, <&cpu7>;
+ };
+
+ clk26m: oscillator-26m {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <26000000>;
+ clock-output-names = "clk26m";
+ };
+
+ clk32k: oscillator-32k {
+ compatible = "fixed-clock";
+ #clock-cells = <0>;
+ clock-frequency = <32768>;
+ clock-output-names = "clk32k";
+ };
+
+ pmu-a55 {
+ compatible = "arm,cortex-a55-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster0>;
+ };
+
+ pmu-a78 {
+ compatible = "arm,cortex-a78-pmu";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 7 IRQ_TYPE_LEVEL_HIGH &ppi_cluster1>;
+ };
+
+ psci {
+ compatible = "arm,psci-1.0";
+ method = "smc";
+ };
+
+ timer: timer {
+ compatible = "arm,armv8-timer";
+ interrupt-parent = <&gic>;
+ interrupts = <GIC_PPI 13 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 14 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 11 IRQ_TYPE_LEVEL_HIGH 0>,
+ <GIC_PPI 10 IRQ_TYPE_LEVEL_HIGH 0>;
+ };
+
+ soc {
+ #address-cells = <2>;
+ #size-cells = <2>;
+ compatible = "simple-bus";
+ ranges;
+
+ gic: interrupt-controller@c000000 {
+ compatible = "arm,gic-v3";
+ #interrupt-cells = <4>;
+ #redistributor-regions = <1>;
+ interrupt-parent = <&gic>;
+ interrupt-controller;
+ reg = <0 0x0c000000 0 0x40000>,
+ <0 0x0c040000 0 0x200000>;
+ interrupts = <GIC_PPI 9 IRQ_TYPE_LEVEL_HIGH 0>;
+
+ ppi-partitions {
+ ppi_cluster0: interrupt-partition-0 {
+ affinity = <&cpu0 &cpu1 &cpu2 &cpu3>;
+ };
+
+ ppi_cluster1: interrupt-partition-1 {
+ affinity = <&cpu4 &cpu5 &cpu6 &cpu7>;
+ };
+ };
+ };
+
+ topckgen: syscon@10000000 {
+ compatible = "mediatek,mt8195-topckgen", "syscon";
+ reg = <0 0x10000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ infracfg_ao: syscon@10001000 {
+ compatible = "mediatek,mt8195-infracfg_ao", "syscon", "simple-mfd";
+ reg = <0 0x10001000 0 0x1000>;
+ #clock-cells = <1>;
+
+ infracfg_rst: reset-controller {
+ compatible = "ti,syscon-reset";
+ #reset-cells = <1>;
+ ti,reset-bits = <
+ 0x140 18 0x144 18 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* pcie */
+ 0x120 0 0x124 0 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
+ 0x730 10 0x734 10 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* thermal */
+ 0x150 5 0x154 5 0 0 (ASSERT_SET | DEASSERT_SET | STATUS_NONE) /* svs gpu */
+ >;
+ };
+ };
+
+ pericfg: syscon@10003000 {
+ compatible = "mediatek,mt8195-pericfg", "syscon";
+ reg = <0 0x10003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ pio: pinctrl@10005000 {
+ compatible = "mediatek,mt8195-pinctrl";
+ reg = <0 0x10005000 0 0x1000>,
+ <0 0x11d10000 0 0x1000>,
+ <0 0x11d30000 0 0x1000>,
+ <0 0x11d40000 0 0x1000>,
+ <0 0x11e20000 0 0x1000>,
+ <0 0x11eb0000 0 0x1000>,
+ <0 0x11f40000 0 0x1000>,
+ <0 0x1000b000 0 0x1000>;
+ reg-names = "iocfg0", "iocfg_bm", "iocfg_bl",
+ "iocfg_br", "iocfg_lm", "iocfg_rb",
+ "iocfg_tl", "eint";
+ gpio-controller;
+ #gpio-cells = <2>;
+ gpio-ranges = <&pio 0 0 144>;
+ interrupt-controller;
+ interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH 0>;
+ #interrupt-cells = <2>;
+ };
+
+ watchdog: watchdog@10007000 {
+ compatible = "mediatek,mt8195-wdt",
+ "mediatek,mt6589-wdt";
+ reg = <0 0x10007000 0 0x100>;
+ };
+
+ apmixedsys: syscon@1000c000 {
+ compatible = "mediatek,mt8195-apmixedsys", "syscon";
+ reg = <0 0x1000c000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ systimer: timer@10017000 {
+ compatible = "mediatek,mt8195-timer",
+ "mediatek,mt6765-timer";
+ reg = <0 0x10017000 0 0x1000>;
+ interrupts = <GIC_SPI 265 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_CLK26M_D2>;
+ };
+
+ pwrap: pwrap@10024000 {
+ compatible = "mediatek,mt8195-pwrap", "syscon";
+ reg = <0 0x10024000 0 0x1000>;
+ reg-names = "pwrap";
+ interrupts = <GIC_SPI 243 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_PMIC_AP>,
+ <&infracfg_ao CLK_INFRA_AO_PMIC_TMR>;
+ clock-names = "spi", "wrap";
+ assigned-clocks = <&topckgen CLK_TOP_PWRAP_ULPOSC>;
+ assigned-clock-parents = <&topckgen CLK_TOP_ULPOSC1_D10>;
+ };
+
+ scp_adsp: clock-controller@10720000 {
+ compatible = "mediatek,mt8195-scp_adsp";
+ reg = <0 0x10720000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ uart0: serial@11001100 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001100 0 0x100>;
+ interrupts = <GIC_SPI 141 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART0>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart1: serial@11001200 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001200 0 0x100>;
+ interrupts = <GIC_SPI 142 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART1>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart2: serial@11001300 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001300 0 0x100>;
+ interrupts = <GIC_SPI 143 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART2>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart3: serial@11001400 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001400 0 0x100>;
+ interrupts = <GIC_SPI 723 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART3>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart4: serial@11001500 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001500 0 0x100>;
+ interrupts = <GIC_SPI 724 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART4>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ uart5: serial@11001600 {
+ compatible = "mediatek,mt8195-uart",
+ "mediatek,mt6577-uart";
+ reg = <0 0x11001600 0 0x100>;
+ interrupts = <GIC_SPI 725 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&clk26m>, <&infracfg_ao CLK_INFRA_AO_UART5>;
+ clock-names = "baud", "bus";
+ status = "disabled";
+ };
+
+ auxadc: auxadc@11002000 {
+ compatible = "mediatek,mt8195-auxadc",
+ "mediatek,mt8173-auxadc";
+ reg = <0 0x11002000 0 0x1000>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_AUXADC>;
+ clock-names = "main";
+ #io-channel-cells = <1>;
+ status = "disabled";
+ };
+
+ pericfg_ao: syscon@11003000 {
+ compatible = "mediatek,mt8195-pericfg_ao", "syscon";
+ reg = <0 0x11003000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ spi0: spi@1100a000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x1100a000 0 0x1000>;
+ interrupts = <GIC_SPI 191 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI0>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi1: spi@11010000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11010000 0 0x1000>;
+ interrupts = <GIC_SPI 192 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI1>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi2: spi@11012000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11012000 0 0x1000>;
+ interrupts = <GIC_SPI 193 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI2>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi3: spi@11013000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11013000 0 0x1000>;
+ interrupts = <GIC_SPI 194 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI3>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi4: spi@11018000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11018000 0 0x1000>;
+ interrupts = <GIC_SPI 195 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI4>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spi5: spi@11019000 {
+ compatible = "mediatek,mt8195-spi",
+ "mediatek,mt6765-spi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ reg = <0 0x11019000 0 0x1000>;
+ interrupts = <GIC_SPI 196 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_UNIVPLL_D6_D2>,
+ <&topckgen CLK_TOP_SPI>,
+ <&infracfg_ao CLK_INFRA_AO_SPI5>;
+ clock-names = "parent-clk", "sel-clk", "spi-clk";
+ status = "disabled";
+ };
+
+ spis0: spi@1101d000 {
+ compatible = "mediatek,mt8195-spi-slave";
+ reg = <0 0x1101d000 0 0x1000>;
+ interrupts = <GIC_SPI 197 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SPIS0>;
+ clock-names = "spi";
+ assigned-clocks = <&topckgen CLK_TOP_SPIS>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+ status = "disabled";
+ };
+
+ spis1: spi@1101e000 {
+ compatible = "mediatek,mt8195-spi-slave";
+ reg = <0 0x1101e000 0 0x1000>;
+ interrupts = <GIC_SPI 198 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SPIS1>;
+ clock-names = "spi";
+ assigned-clocks = <&topckgen CLK_TOP_SPIS>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D6>;
+ status = "disabled";
+ };
+
+ xhci0: usb@11200000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11200000 0 0x1000>,
+ <0 0x11203e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port0 PHY_TYPE_USB2>,
+ <&u3port0 PHY_TYPE_USB3>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
+ <&topckgen CLK_TOP_SSUSB_XHCI>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
+ <&topckgen CLK_TOP_SSUSB_REF>,
+ <&apmixedsys CLK_APMIXED_USB1PLL>,
+ <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck", "xhci_ck";
+ status = "disabled";
+ };
+
+ mmc0: mmc@11230000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11230000 0 0x10000>,
+ <0 0x11f50000 0 0x1000>;
+ interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC50_0>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC0>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC0_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ status = "disabled";
+ };
+
+ mmc1: mmc@11240000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11240000 0 0x1000>,
+ <0 0x11c70000 0 0x1000>;
+ interrupts = <GIC_SPI 135 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_1>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC1>,
+ <&infracfg_ao CLK_INFRA_AO_MSDC1_SRC>;
+ clock-names = "source", "hclk", "source_cg";
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_1>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ status = "disabled";
+ };
+
+ mmc2: mmc@11250000 {
+ compatible = "mediatek,mt8195-mmc",
+ "mediatek,mt8183-mmc";
+ reg = <0 0x11250000 0 0x1000>,
+ <0 0x11e60000 0 0x1000>;
+ interrupts = <GIC_SPI 136 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_MSDC30_2>,
+ <&infracfg_ao CLK_INFRA_AO_CG1_MSDC2>,
+ <&infracfg_ao CLK_INFRA_AO_CG3_MSDC2>;
+ clock-names = "source", "hclk", "source_cg";
+ assigned-clocks = <&topckgen CLK_TOP_MSDC30_2>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MSDCPLL_D2>;
+ status = "disabled";
+ };
+
+ xhci1: usb@11290000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x11290000 0 0x1000>,
+ <0 0x11293e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port1 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_P1_REF>,
+ <&apmixedsys CLK_APMIXED_USB1PLL>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "mcu_ck","xhci_ck";
+ status = "disabled";
+ };
+
+ xhci2: usb@112a0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112a0000 0 0x1000>,
+ <0 0x112a3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port2 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_P2_REF>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "xhci_ck";
+ status = "disabled";
+ };
+
+ xhci3: usb@112b0000 {
+ compatible = "mediatek,mt8195-xhci",
+ "mediatek,mtk-xhci";
+ reg = <0 0x112b0000 0 0x1000>,
+ <0 0x112b3e00 0 0x0100>;
+ reg-names = "mac", "ippc";
+ interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
+ phys = <&u2port3 PHY_TYPE_USB2>;
+ assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
+ <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
+ assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
+ <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
+ clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
+ <&topckgen CLK_TOP_SSUSB_P3_REF>,
+ <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>;
+ clock-names = "sys_ck", "ref_ck", "xhci_ck";
+ status = "disabled";
+ };
+
+ nor_flash: spi@1132c000 {
+ compatible = "mediatek,mt8195-nor",
+ "mediatek,mt8173-nor";
+ reg = <0 0x1132c000 0 0x1000>;
+ interrupts = <GIC_SPI 825 IRQ_TYPE_LEVEL_HIGH 0>;
+ clocks = <&topckgen CLK_TOP_SPINOR>,
+ <&pericfg_ao CLK_PERI_AO_FLASHIF_FLASH>,
+ <&pericfg_ao CLK_PERI_AO_FLASHIF_BUS>;
+ clock-names = "spi", "sf", "axi";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ u3phy2: t-phy@11c40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c40000 0x700>;
+ status = "disabled";
+
+ u2port2: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P2_REF>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy3: t-phy@11c50000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11c50000 0x700>;
+ status = "disabled";
+
+ u2port3: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P3_REF>;
+ clock-names = "ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ i2c5: i2c@11d00000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11d00000 0 0x1000>,
+ <0 0x10220580 0 0x80>;
+ interrupts = <GIC_SPI 154 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C5>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c6: i2c@11d01000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11d01000 0 0x1000>,
+ <0 0x10220600 0 0x80>;
+ interrupts = <GIC_SPI 155 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C6>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c7: i2c@11d02000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11d02000 0 0x1000>,
+ <0 0x10220680 0 0x80>;
+ interrupts = <GIC_SPI 156 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_s CLK_IMP_IIC_WRAP_S_I2C7>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ imp_iic_wrap_s: clock-controller@11d03000 {
+ compatible = "mediatek,mt8195-imp_iic_wrap_s";
+ reg = <0 0x11d03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ i2c0: i2c@11e00000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e00000 0 0x1000>,
+ <0 0x10220080 0 0x80>;
+ interrupts = <GIC_SPI 144 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C0>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+ };
+
+ i2c1: i2c@11e01000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e01000 0 0x1000>,
+ <0 0x10220200 0 0x80>;
+ interrupts = <GIC_SPI 147 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C1>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c2: i2c@11e02000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e02000 0 0x1000>,
+ <0 0x10220380 0 0x80>;
+ interrupts = <GIC_SPI 150 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C2>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c3: i2c@11e03000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e03000 0 0x1000>,
+ <0 0x10220480 0 0x80>;
+ interrupts = <GIC_SPI 152 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C3>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ i2c4: i2c@11e04000 {
+ compatible = "mediatek,mt8195-i2c",
+ "mediatek,mt8192-i2c";
+ reg = <0 0x11e04000 0 0x1000>,
+ <0 0x10220500 0 0x80>;
+ interrupts = <GIC_SPI 153 IRQ_TYPE_LEVEL_HIGH 0>;
+ clock-div = <1>;
+ clocks = <&imp_iic_wrap_w CLK_IMP_IIC_WRAP_W_I2C4>,
+ <&infracfg_ao CLK_INFRA_AO_APDMA_B>;
+ clock-names = "main", "dma";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
+ imp_iic_wrap_w: clock-controller@11e05000 {
+ compatible = "mediatek,mt8195-imp_iic_wrap_w";
+ reg = <0 0x11e05000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ u3phy1: t-phy@11e30000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e30000 0xe00>;
+ status = "disabled";
+
+ u2port1: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>,
+ <&clk26m>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u3port1: usb-phy@700 {
+ reg = <0x700 0x700>;
+ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
+ <&topckgen CLK_TOP_SSUSB_PHY_P1_REF>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ u3phy0: t-phy@11e40000 {
+ compatible = "mediatek,mt8195-tphy", "mediatek,generic-tphy-v3";
+ #address-cells = <1>;
+ #size-cells = <1>;
+ ranges = <0 0 0x11e40000 0xe00>;
+ status = "disabled";
+
+ u2port0: usb-phy@0 {
+ reg = <0x0 0x700>;
+ clocks = <&topckgen CLK_TOP_SSUSB_PHY_REF>,
+ <&clk26m>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+
+ u3port0: usb-phy@700 {
+ reg = <0x700 0x700>;
+ clocks = <&apmixedsys CLK_APMIXED_PLL_SSUSB26M>,
+ <&topckgen CLK_TOP_SSUSB_PHY_REF>;
+ clock-names = "ref", "da_ref";
+ #phy-cells = <1>;
+ };
+ };
+
+ ufsphy: ufs-phy@11fa0000 {
+ compatible = "mediatek,mt8195-ufsphy", "mediatek,mt8183-ufsphy";
+ reg = <0 0x11fa0000 0 0xc000>;
+ clocks = <&clk26m>, <&clk26m>;
+ clock-names = "unipro", "mp";
+ #phy-cells = <0>;
+ status = "disabled";
+ };
+
+ mfgcfg: clock-controller@13fbf000 {
+ compatible = "mediatek,mt8195-mfgcfg";
+ reg = <0 0x13fbf000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys: clock-controller@14e00000 {
+ compatible = "mediatek,mt8195-wpesys";
+ reg = <0 0x14e00000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys_vpp0: clock-controller@14e02000 {
+ compatible = "mediatek,mt8195-wpesys_vpp0";
+ reg = <0 0x14e02000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ wpesys_vpp1: clock-controller@14e03000 {
+ compatible = "mediatek,mt8195-wpesys_vpp1";
+ reg = <0 0x14e03000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys: clock-controller@15000000 {
+ compatible = "mediatek,mt8195-imgsys";
+ reg = <0 0x15000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_dip_top: clock-controller@15110000 {
+ compatible = "mediatek,mt8195-imgsys1_dip_top";
+ reg = <0 0x15110000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_dip_nr: clock-controller@15130000 {
+ compatible = "mediatek,mt8195-imgsys1_dip_nr";
+ reg = <0 0x15130000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ imgsys1_wpe: clock-controller@15220000 {
+ compatible = "mediatek,mt8195-imgsys1_wpe";
+ reg = <0 0x15220000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ipesys: clock-controller@15330000 {
+ compatible = "mediatek,mt8195-ipesys";
+ reg = <0 0x15330000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys: clock-controller@16000000 {
+ compatible = "mediatek,mt8195-camsys";
+ reg = <0 0x16000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawa: clock-controller@1604f000 {
+ compatible = "mediatek,mt8195-camsys_rawa";
+ reg = <0 0x1604f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_yuva: clock-controller@1606f000 {
+ compatible = "mediatek,mt8195-camsys_yuva";
+ reg = <0 0x1606f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_rawb: clock-controller@1608f000 {
+ compatible = "mediatek,mt8195-camsys_rawb";
+ reg = <0 0x1608f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_yuvb: clock-controller@160af000 {
+ compatible = "mediatek,mt8195-camsys_yuvb";
+ reg = <0 0x160af000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ camsys_mraw: clock-controller@16140000 {
+ compatible = "mediatek,mt8195-camsys_mraw";
+ reg = <0 0x16140000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ ccusys: clock-controller@17200000 {
+ compatible = "mediatek,mt8195-ccusys";
+ reg = <0 0x17200000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_soc: clock-controller@1800f000 {
+ compatible = "mediatek,mt8195-vdecsys_soc";
+ reg = <0 0x1800f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys: clock-controller@1802f000 {
+ compatible = "mediatek,mt8195-vdecsys";
+ reg = <0 0x1802f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vdecsys_core1: clock-controller@1803f000 {
+ compatible = "mediatek,mt8195-vdecsys_core1";
+ reg = <0 0x1803f000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ apusys_pll: clock-controller@190f3000 {
+ compatible = "mediatek,mt8195-apusys_pll";
+ reg = <0 0x190f3000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys: clock-controller@1a000000 {
+ compatible = "mediatek,mt8195-vencsys";
+ reg = <0 0x1a000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+
+ vencsys_core1: clock-controller@1b000000 {
+ compatible = "mediatek,mt8195-vencsys_core1";
+ reg = <0 0x1b000000 0 0x1000>;
+ #clock-cells = <1>;
+ };
+ };
+};
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
2022-03-29 11:45 ` Tinghan Shen
(?)
@ 2022-03-29 12:43 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-29 12:43 UTC (permalink / raw)
To: Tinghan Shen, Chaotian Jing, Ulf Hansson, Rob Herring,
Krzysztof Kozlowski, Matthias Brugger, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Il 29/03/22 13:45, Tinghan Shen ha scritto:
> Add optional host top register base for the reg binding description.
>
> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> index 7032f7adf3ca..6d41bcec900f 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -40,7 +40,8 @@ properties:
> - const: mediatek,mt8183-mmc
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
it's just maxItems... adding minItems: 1 is not required.
>
> clocks:
> description:
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-29 12:43 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-29 12:43 UTC (permalink / raw)
To: Tinghan Shen, Chaotian Jing, Ulf Hansson, Rob Herring,
Krzysztof Kozlowski, Matthias Brugger, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Il 29/03/22 13:45, Tinghan Shen ha scritto:
> Add optional host top register base for the reg binding description.
>
> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> index 7032f7adf3ca..6d41bcec900f 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -40,7 +40,8 @@ properties:
> - const: mediatek,mt8183-mmc
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
it's just maxItems... adding minItems: 1 is not required.
>
> clocks:
> description:
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-29 12:43 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-29 12:43 UTC (permalink / raw)
To: Tinghan Shen, Chaotian Jing, Ulf Hansson, Rob Herring,
Krzysztof Kozlowski, Matthias Brugger, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Il 29/03/22 13:45, Tinghan Shen ha scritto:
> Add optional host top register base for the reg binding description.
>
> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> index 7032f7adf3ca..6d41bcec900f 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -40,7 +40,8 @@ properties:
> - const: mediatek,mt8183-mmc
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
it's just maxItems... adding minItems: 1 is not required.
>
> clocks:
> description:
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 1/3] dt-bindings: mmc: mtk-sd: fix yamllint error
2022-03-29 11:45 ` Tinghan Shen
(?)
@ 2022-03-29 12:47 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-29 12:47 UTC (permalink / raw)
To: Tinghan Shen, Chaotian Jing, Ulf Hansson, Rob Herring,
Krzysztof Kozlowski, Matthias Brugger, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Il 29/03/22 13:45, Tinghan Shen ha scritto:
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> 54:81 error line too long (95 > 80 characters) (line-length)
>
I can't reproduce this error that you're getting... this commit is not
necessary, as the .yamllint file in the kernel allows a maximum line-length
of 110 characters.
rules:
line-length:
# 80 chars should be enough, but don't fail if a line is longer
max: 110
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/.yamllint?h=next-20220329
Please drop this commit.
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 1/3] dt-bindings: mmc: mtk-sd: fix yamllint error
@ 2022-03-29 12:47 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-29 12:47 UTC (permalink / raw)
To: Tinghan Shen, Chaotian Jing, Ulf Hansson, Rob Herring,
Krzysztof Kozlowski, Matthias Brugger, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Il 29/03/22 13:45, Tinghan Shen ha scritto:
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> 54:81 error line too long (95 > 80 characters) (line-length)
>
I can't reproduce this error that you're getting... this commit is not
necessary, as the .yamllint file in the kernel allows a maximum line-length
of 110 characters.
rules:
line-length:
# 80 chars should be enough, but don't fail if a line is longer
max: 110
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/.yamllint?h=next-20220329
Please drop this commit.
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 1/3] dt-bindings: mmc: mtk-sd: fix yamllint error
@ 2022-03-29 12:47 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-29 12:47 UTC (permalink / raw)
To: Tinghan Shen, Chaotian Jing, Ulf Hansson, Rob Herring,
Krzysztof Kozlowski, Matthias Brugger, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Il 29/03/22 13:45, Tinghan Shen ha scritto:
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> 54:81 error line too long (95 > 80 characters) (line-length)
>
I can't reproduce this error that you're getting... this commit is not
necessary, as the .yamllint file in the kernel allows a maximum line-length
of 110 characters.
rules:
line-length:
# 80 chars should be enough, but don't fail if a line is longer
max: 110
https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/.yamllint?h=next-20220329
Please drop this commit.
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
2022-03-29 11:45 ` Tinghan Shen
(?)
@ 2022-03-29 14:27 ` Matthias Brugger
-1 siblings, 0 replies; 39+ messages in thread
From: Matthias Brugger @ 2022-03-29 14:27 UTC (permalink / raw)
To: Tinghan Shen, Chaotian Jing, Ulf Hansson, Rob Herring,
Krzysztof Kozlowski, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
On 29/03/2022 13:45, Tinghan Shen wrote:
> Add optional host top register base for the reg binding description.
>
Is this based a on a new version of the IP? Shall we make the second reg
mandatory for the new HW? If I remember correctly the reg needs to be restored
after power save event. So I suppose mmc won't work if that's not done. So
optional wouldn't be the right approach.
Can you please clarify if that's the case.
Thanks,
Matthias
> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> index 7032f7adf3ca..6d41bcec900f 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -40,7 +40,8 @@ properties:
> - const: mediatek,mt8183-mmc
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
>
> clocks:
> description:
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-29 14:27 ` Matthias Brugger
0 siblings, 0 replies; 39+ messages in thread
From: Matthias Brugger @ 2022-03-29 14:27 UTC (permalink / raw)
To: Tinghan Shen, Chaotian Jing, Ulf Hansson, Rob Herring,
Krzysztof Kozlowski, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
On 29/03/2022 13:45, Tinghan Shen wrote:
> Add optional host top register base for the reg binding description.
>
Is this based a on a new version of the IP? Shall we make the second reg
mandatory for the new HW? If I remember correctly the reg needs to be restored
after power save event. So I suppose mmc won't work if that's not done. So
optional wouldn't be the right approach.
Can you please clarify if that's the case.
Thanks,
Matthias
> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> index 7032f7adf3ca..6d41bcec900f 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -40,7 +40,8 @@ properties:
> - const: mediatek,mt8183-mmc
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
>
> clocks:
> description:
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-29 14:27 ` Matthias Brugger
0 siblings, 0 replies; 39+ messages in thread
From: Matthias Brugger @ 2022-03-29 14:27 UTC (permalink / raw)
To: Tinghan Shen, Chaotian Jing, Ulf Hansson, Rob Herring,
Krzysztof Kozlowski, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
On 29/03/2022 13:45, Tinghan Shen wrote:
> Add optional host top register base for the reg binding description.
>
Is this based a on a new version of the IP? Shall we make the second reg
mandatory for the new HW? If I remember correctly the reg needs to be restored
after power save event. So I suppose mmc won't work if that's not done. So
optional wouldn't be the right approach.
Can you please clarify if that's the case.
Thanks,
Matthias
> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> index 7032f7adf3ca..6d41bcec900f 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -40,7 +40,8 @@ properties:
> - const: mediatek,mt8183-mmc
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
>
> clocks:
> description:
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
2022-03-29 12:43 ` AngeloGioacchino Del Regno
(?)
@ 2022-03-29 19:10 ` Rob Herring
-1 siblings, 0 replies; 39+ messages in thread
From: Rob Herring @ 2022-03-29 19:10 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: Tinghan Shen, Chaotian Jing, Ulf Hansson, Krzysztof Kozlowski,
Matthias Brugger, Wenbin Mei, linux-mmc, devicetree,
linux-kernel, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support,
Project_Global_Chrome_Upstream_Group, Ryder Lee, Chen-Yu Tsai,
Chunfeng Yun
On Tue, Mar 29, 2022 at 7:43 AM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 29/03/22 13:45, Tinghan Shen ha scritto:
> > Add optional host top register base for the reg binding description.
> >
> > Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > index 7032f7adf3ca..6d41bcec900f 100644
> > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > @@ -40,7 +40,8 @@ properties:
> > - const: mediatek,mt8183-mmc
> >
> > reg:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 2
>
> it's just maxItems... adding minItems: 1 is not required.
If 1 entry is still valid, then minItems is required. If not, then
it's an ABI break.
Rob
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-29 19:10 ` Rob Herring
0 siblings, 0 replies; 39+ messages in thread
From: Rob Herring @ 2022-03-29 19:10 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: Tinghan Shen, Chaotian Jing, Ulf Hansson, Krzysztof Kozlowski,
Matthias Brugger, Wenbin Mei, linux-mmc, devicetree,
linux-kernel, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support,
Project_Global_Chrome_Upstream_Group, Ryder Lee, Chen-Yu Tsai,
Chunfeng Yun
On Tue, Mar 29, 2022 at 7:43 AM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 29/03/22 13:45, Tinghan Shen ha scritto:
> > Add optional host top register base for the reg binding description.
> >
> > Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > index 7032f7adf3ca..6d41bcec900f 100644
> > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > @@ -40,7 +40,8 @@ properties:
> > - const: mediatek,mt8183-mmc
> >
> > reg:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 2
>
> it's just maxItems... adding minItems: 1 is not required.
If 1 entry is still valid, then minItems is required. If not, then
it's an ABI break.
Rob
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-29 19:10 ` Rob Herring
0 siblings, 0 replies; 39+ messages in thread
From: Rob Herring @ 2022-03-29 19:10 UTC (permalink / raw)
To: AngeloGioacchino Del Regno
Cc: Tinghan Shen, Chaotian Jing, Ulf Hansson, Krzysztof Kozlowski,
Matthias Brugger, Wenbin Mei, linux-mmc, devicetree,
linux-kernel, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support,
Project_Global_Chrome_Upstream_Group, Ryder Lee, Chen-Yu Tsai,
Chunfeng Yun
On Tue, Mar 29, 2022 at 7:43 AM AngeloGioacchino Del Regno
<angelogioacchino.delregno@collabora.com> wrote:
>
> Il 29/03/22 13:45, Tinghan Shen ha scritto:
> > Add optional host top register base for the reg binding description.
> >
> > Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > index 7032f7adf3ca..6d41bcec900f 100644
> > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > @@ -40,7 +40,8 @@ properties:
> > - const: mediatek,mt8183-mmc
> >
> > reg:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 2
>
> it's just maxItems... adding minItems: 1 is not required.
If 1 entry is still valid, then minItems is required. If not, then
it's an ABI break.
Rob
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
2022-03-29 11:45 ` Tinghan Shen
(?)
@ 2022-03-29 20:38 ` Rob Herring
-1 siblings, 0 replies; 39+ messages in thread
From: Rob Herring @ 2022-03-29 20:38 UTC (permalink / raw)
To: Tinghan Shen
Cc: Chaotian Jing, Ulf Hansson, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei,
linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
On Tue, Mar 29, 2022 at 07:45:39PM +0800, Tinghan Shen wrote:
> Add optional host top register base for the reg binding description.
>
> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> index 7032f7adf3ca..6d41bcec900f 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -40,7 +40,8 @@ properties:
> - const: mediatek,mt8183-mmc
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
If more than 1 entry, then you need to define what each one is.
>
> clocks:
> description:
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-29 20:38 ` Rob Herring
0 siblings, 0 replies; 39+ messages in thread
From: Rob Herring @ 2022-03-29 20:38 UTC (permalink / raw)
To: Tinghan Shen
Cc: Chaotian Jing, Ulf Hansson, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei,
linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
On Tue, Mar 29, 2022 at 07:45:39PM +0800, Tinghan Shen wrote:
> Add optional host top register base for the reg binding description.
>
> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> index 7032f7adf3ca..6d41bcec900f 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -40,7 +40,8 @@ properties:
> - const: mediatek,mt8183-mmc
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
If more than 1 entry, then you need to define what each one is.
>
> clocks:
> description:
> --
> 2.18.0
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-29 20:38 ` Rob Herring
0 siblings, 0 replies; 39+ messages in thread
From: Rob Herring @ 2022-03-29 20:38 UTC (permalink / raw)
To: Tinghan Shen
Cc: Chaotian Jing, Ulf Hansson, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei,
linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
On Tue, Mar 29, 2022 at 07:45:39PM +0800, Tinghan Shen wrote:
> Add optional host top register base for the reg binding description.
>
> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> ---
> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> 1 file changed, 2 insertions(+), 1 deletion(-)
>
> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> index 7032f7adf3ca..6d41bcec900f 100644
> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> @@ -40,7 +40,8 @@ properties:
> - const: mediatek,mt8183-mmc
>
> reg:
> - maxItems: 1
> + minItems: 1
> + maxItems: 2
If more than 1 entry, then you need to define what each one is.
>
> clocks:
> description:
> --
> 2.18.0
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 1/3] dt-bindings: mmc: mtk-sd: fix yamllint error
2022-03-29 12:47 ` AngeloGioacchino Del Regno
(?)
@ 2022-03-30 2:55 ` Tinghan Shen
-1 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-30 2:55 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chaotian Jing, Ulf Hansson,
Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Hi Angelo,
On Tue, 2022-03-29 at 14:47 +0200, AngeloGioacchino Del Regno wrote:
> Il 29/03/22 13:45, Tinghan Shen ha scritto:
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > 54:81 error line too long (95 > 80 characters) (line-length)
> >
>
> I can't reproduce this error that you're getting... this commit is not
> necessary, as the .yamllint file in the kernel allows a maximum line-length
> of 110 characters.
>
> rules:
> line-length:
> # 80 chars should be enough, but don't fail if a line is longer
> max: 110
>
>
https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/.yamllint?h=next-20220329__;!!CTRNKA9wMg0ARbw!1L9icT80FdI9EYV81qRGpzbEvV1NFP_pwk8YABV0eIiRf2ppttnPlRfu5aXEUsxODiE$
>
>
> Please drop this commit.
Thank you for your feedback.
I figured out why I have this error...
It's because I do the yamllint outside of the bindings folder and not specify the yamllint config
file.
I'll drop this at next version.
Best regards,
Tinghan
>
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 1/3] dt-bindings: mmc: mtk-sd: fix yamllint error
@ 2022-03-30 2:55 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-30 2:55 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chaotian Jing, Ulf Hansson,
Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Hi Angelo,
On Tue, 2022-03-29 at 14:47 +0200, AngeloGioacchino Del Regno wrote:
> Il 29/03/22 13:45, Tinghan Shen ha scritto:
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > 54:81 error line too long (95 > 80 characters) (line-length)
> >
>
> I can't reproduce this error that you're getting... this commit is not
> necessary, as the .yamllint file in the kernel allows a maximum line-length
> of 110 characters.
>
> rules:
> line-length:
> # 80 chars should be enough, but don't fail if a line is longer
> max: 110
>
>
https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/.yamllint?h=next-20220329__;!!CTRNKA9wMg0ARbw!1L9icT80FdI9EYV81qRGpzbEvV1NFP_pwk8YABV0eIiRf2ppttnPlRfu5aXEUsxODiE$
>
>
> Please drop this commit.
Thank you for your feedback.
I figured out why I have this error...
It's because I do the yamllint outside of the bindings folder and not specify the yamllint config
file.
I'll drop this at next version.
Best regards,
Tinghan
>
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 1/3] dt-bindings: mmc: mtk-sd: fix yamllint error
@ 2022-03-30 2:55 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-30 2:55 UTC (permalink / raw)
To: AngeloGioacchino Del Regno, Chaotian Jing, Ulf Hansson,
Rob Herring, Krzysztof Kozlowski, Matthias Brugger, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Hi Angelo,
On Tue, 2022-03-29 at 14:47 +0200, AngeloGioacchino Del Regno wrote:
> Il 29/03/22 13:45, Tinghan Shen ha scritto:
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > 54:81 error line too long (95 > 80 characters) (line-length)
> >
>
> I can't reproduce this error that you're getting... this commit is not
> necessary, as the .yamllint file in the kernel allows a maximum line-length
> of 110 characters.
>
> rules:
> line-length:
> # 80 chars should be enough, but don't fail if a line is longer
> max: 110
>
>
https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/next/linux-next.git/tree/Documentation/devicetree/bindings/.yamllint?h=next-20220329__;!!CTRNKA9wMg0ARbw!1L9icT80FdI9EYV81qRGpzbEvV1NFP_pwk8YABV0eIiRf2ppttnPlRfu5aXEUsxODiE$
>
>
> Please drop this commit.
Thank you for your feedback.
I figured out why I have this error...
It's because I do the yamllint outside of the bindings folder and not specify the yamllint config
file.
I'll drop this at next version.
Best regards,
Tinghan
>
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
2022-03-29 20:38 ` Rob Herring
(?)
@ 2022-03-30 7:25 ` Tinghan Shen
-1 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-30 7:25 UTC (permalink / raw)
To: Rob Herring
Cc: Chaotian Jing, Ulf Hansson, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei,
linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Hi Rob,
On Tue, 2022-03-29 at 15:38 -0500, Rob Herring wrote:
> On Tue, Mar 29, 2022 at 07:45:39PM +0800, Tinghan Shen wrote:
> > Add optional host top register base for the reg binding description.
> >
> > Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > index 7032f7adf3ca..6d41bcec900f 100644
> > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > @@ -40,7 +40,8 @@ properties:
> > - const: mediatek,mt8183-mmc
> >
> > reg:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 2
>
> If more than 1 entry, then you need to define what each one is.
Ok. I'll add definitions at next version.
Thank you.
Best regards,
Tinghan
>
> >
> > clocks:
> > description:
> > --
> > 2.18.0
> >
> >
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-30 7:25 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-30 7:25 UTC (permalink / raw)
To: Rob Herring
Cc: Chaotian Jing, Ulf Hansson, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei,
linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Hi Rob,
On Tue, 2022-03-29 at 15:38 -0500, Rob Herring wrote:
> On Tue, Mar 29, 2022 at 07:45:39PM +0800, Tinghan Shen wrote:
> > Add optional host top register base for the reg binding description.
> >
> > Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > index 7032f7adf3ca..6d41bcec900f 100644
> > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > @@ -40,7 +40,8 @@ properties:
> > - const: mediatek,mt8183-mmc
> >
> > reg:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 2
>
> If more than 1 entry, then you need to define what each one is.
Ok. I'll add definitions at next version.
Thank you.
Best regards,
Tinghan
>
> >
> > clocks:
> > description:
> > --
> > 2.18.0
> >
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-30 7:25 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-30 7:25 UTC (permalink / raw)
To: Rob Herring
Cc: Chaotian Jing, Ulf Hansson, Krzysztof Kozlowski,
Matthias Brugger, AngeloGioacchino Del Regno, Wenbin Mei,
linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Hi Rob,
On Tue, 2022-03-29 at 15:38 -0500, Rob Herring wrote:
> On Tue, Mar 29, 2022 at 07:45:39PM +0800, Tinghan Shen wrote:
> > Add optional host top register base for the reg binding description.
> >
> > Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > index 7032f7adf3ca..6d41bcec900f 100644
> > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > @@ -40,7 +40,8 @@ properties:
> > - const: mediatek,mt8183-mmc
> >
> > reg:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 2
>
> If more than 1 entry, then you need to define what each one is.
Ok. I'll add definitions at next version.
Thank you.
Best regards,
Tinghan
>
> >
> > clocks:
> > description:
> > --
> > 2.18.0
> >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
2022-03-29 14:27 ` Matthias Brugger
(?)
@ 2022-03-30 7:33 ` Tinghan Shen
-1 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-30 7:33 UTC (permalink / raw)
To: Matthias Brugger, Chaotian Jing, Ulf Hansson, Rob Herring,
Krzysztof Kozlowski, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Hi Matthias,
On Tue, 2022-03-29 at 16:27 +0200, Matthias Brugger wrote:
>
> On 29/03/2022 13:45, Tinghan Shen wrote:
> > Add optional host top register base for the reg binding description.
> >
>
> Is this based a on a new version of the IP? Shall we make the second reg
> mandatory for the new HW? If I remember correctly the reg needs to be restored
> after power save event. So I suppose mmc won't work if that's not done. So
> optional wouldn't be the right approach.
>
> Can you please clarify if that's the case.
Yes. This change is introduced since mt8183, and the host top register
is required for mt8183.
We'll try to describe this change clearly in bindings in next version.
Best regards,
Tinghan
>
> Thanks,
> Matthias
>
> > Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > index 7032f7adf3ca..6d41bcec900f 100644
> > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > @@ -40,7 +40,8 @@ properties:
> > - const: mediatek,mt8183-mmc
> >
> > reg:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 2
> >
> > clocks:
> > description:
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-30 7:33 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-30 7:33 UTC (permalink / raw)
To: Matthias Brugger, Chaotian Jing, Ulf Hansson, Rob Herring,
Krzysztof Kozlowski, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Hi Matthias,
On Tue, 2022-03-29 at 16:27 +0200, Matthias Brugger wrote:
>
> On 29/03/2022 13:45, Tinghan Shen wrote:
> > Add optional host top register base for the reg binding description.
> >
>
> Is this based a on a new version of the IP? Shall we make the second reg
> mandatory for the new HW? If I remember correctly the reg needs to be restored
> after power save event. So I suppose mmc won't work if that's not done. So
> optional wouldn't be the right approach.
>
> Can you please clarify if that's the case.
Yes. This change is introduced since mt8183, and the host top register
is required for mt8183.
We'll try to describe this change clearly in bindings in next version.
Best regards,
Tinghan
>
> Thanks,
> Matthias
>
> > Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > index 7032f7adf3ca..6d41bcec900f 100644
> > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > @@ -40,7 +40,8 @@ properties:
> > - const: mediatek,mt8183-mmc
> >
> > reg:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 2
> >
> > clocks:
> > description:
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-30 7:33 ` Tinghan Shen
0 siblings, 0 replies; 39+ messages in thread
From: Tinghan Shen @ 2022-03-30 7:33 UTC (permalink / raw)
To: Matthias Brugger, Chaotian Jing, Ulf Hansson, Rob Herring,
Krzysztof Kozlowski, AngeloGioacchino Del Regno, Wenbin Mei
Cc: linux-mmc, devicetree, linux-kernel, linux-arm-kernel,
linux-mediatek, Project_Global_Chrome_Upstream_Group, ryder.lee,
wenst, chunfeng.yun
Hi Matthias,
On Tue, 2022-03-29 at 16:27 +0200, Matthias Brugger wrote:
>
> On 29/03/2022 13:45, Tinghan Shen wrote:
> > Add optional host top register base for the reg binding description.
> >
>
> Is this based a on a new version of the IP? Shall we make the second reg
> mandatory for the new HW? If I remember correctly the reg needs to be restored
> after power save event. So I suppose mmc won't work if that's not done. So
> optional wouldn't be the right approach.
>
> Can you please clarify if that's the case.
Yes. This change is introduced since mt8183, and the host top register
is required for mt8183.
We'll try to describe this change clearly in bindings in next version.
Best regards,
Tinghan
>
> Thanks,
> Matthias
>
> > Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
> > Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
> > ---
> > Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
> > 1 file changed, 2 insertions(+), 1 deletion(-)
> >
> > diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > index 7032f7adf3ca..6d41bcec900f 100644
> > --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
> > @@ -40,7 +40,8 @@ properties:
> > - const: mediatek,mt8183-mmc
> >
> > reg:
> > - maxItems: 1
> > + minItems: 1
> > + maxItems: 2
> >
> > clocks:
> > description:
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^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
2022-03-29 19:10 ` Rob Herring
(?)
@ 2022-03-30 8:20 ` AngeloGioacchino Del Regno
-1 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-30 8:20 UTC (permalink / raw)
To: Rob Herring
Cc: Tinghan Shen, Chaotian Jing, Ulf Hansson, Krzysztof Kozlowski,
Matthias Brugger, Wenbin Mei, linux-mmc, devicetree,
linux-kernel, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support,
Project_Global_Chrome_Upstream_Group, Ryder Lee, Chen-Yu Tsai,
Chunfeng Yun
Il 29/03/22 21:10, Rob Herring ha scritto:
> On Tue, Mar 29, 2022 at 7:43 AM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Il 29/03/22 13:45, Tinghan Shen ha scritto:
>>> Add optional host top register base for the reg binding description.
>>>
>>> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
>>> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
>>> ---
>>> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
>>> index 7032f7adf3ca..6d41bcec900f 100644
>>> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
>>> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
>>> @@ -40,7 +40,8 @@ properties:
>>> - const: mediatek,mt8183-mmc
>>>
>>> reg:
>>> - maxItems: 1
>>> + minItems: 1
>>> + maxItems: 2
>>
>> it's just maxItems... adding minItems: 1 is not required.
>
> If 1 entry is still valid, then minItems is required. If not, then
> it's an ABI break.
>
> Rob
Right. Sorry for that and thanks for the explaination, Rob.
Cheers,
Angelo
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-30 8:20 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-30 8:20 UTC (permalink / raw)
To: Rob Herring
Cc: Tinghan Shen, Chaotian Jing, Ulf Hansson, Krzysztof Kozlowski,
Matthias Brugger, Wenbin Mei, linux-mmc, devicetree,
linux-kernel, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support,
Project_Global_Chrome_Upstream_Group, Ryder Lee, Chen-Yu Tsai,
Chunfeng Yun
Il 29/03/22 21:10, Rob Herring ha scritto:
> On Tue, Mar 29, 2022 at 7:43 AM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Il 29/03/22 13:45, Tinghan Shen ha scritto:
>>> Add optional host top register base for the reg binding description.
>>>
>>> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
>>> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
>>> ---
>>> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
>>> index 7032f7adf3ca..6d41bcec900f 100644
>>> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
>>> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
>>> @@ -40,7 +40,8 @@ properties:
>>> - const: mediatek,mt8183-mmc
>>>
>>> reg:
>>> - maxItems: 1
>>> + minItems: 1
>>> + maxItems: 2
>>
>> it's just maxItems... adding minItems: 1 is not required.
>
> If 1 entry is still valid, then minItems is required. If not, then
> it's an ABI break.
>
> Rob
Right. Sorry for that and thanks for the explaination, Rob.
Cheers,
Angelo
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 39+ messages in thread
* Re: [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems
@ 2022-03-30 8:20 ` AngeloGioacchino Del Regno
0 siblings, 0 replies; 39+ messages in thread
From: AngeloGioacchino Del Regno @ 2022-03-30 8:20 UTC (permalink / raw)
To: Rob Herring
Cc: Tinghan Shen, Chaotian Jing, Ulf Hansson, Krzysztof Kozlowski,
Matthias Brugger, Wenbin Mei, linux-mmc, devicetree,
linux-kernel, linux-arm-kernel,
moderated list:ARM/Mediatek SoC support,
Project_Global_Chrome_Upstream_Group, Ryder Lee, Chen-Yu Tsai,
Chunfeng Yun
Il 29/03/22 21:10, Rob Herring ha scritto:
> On Tue, Mar 29, 2022 at 7:43 AM AngeloGioacchino Del Regno
> <angelogioacchino.delregno@collabora.com> wrote:
>>
>> Il 29/03/22 13:45, Tinghan Shen ha scritto:
>>> Add optional host top register base for the reg binding description.
>>>
>>> Signed-off-by: Wenbin Mei <wenbin.mei@mediatek.com>
>>> Signed-off-by: Tinghan Shen <tinghan.shen@mediatek.com>
>>> ---
>>> Documentation/devicetree/bindings/mmc/mtk-sd.yaml | 3 ++-
>>> 1 file changed, 2 insertions(+), 1 deletion(-)
>>>
>>> diff --git a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
>>> index 7032f7adf3ca..6d41bcec900f 100644
>>> --- a/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
>>> +++ b/Documentation/devicetree/bindings/mmc/mtk-sd.yaml
>>> @@ -40,7 +40,8 @@ properties:
>>> - const: mediatek,mt8183-mmc
>>>
>>> reg:
>>> - maxItems: 1
>>> + minItems: 1
>>> + maxItems: 2
>>
>> it's just maxItems... adding minItems: 1 is not required.
>
> If 1 entry is still valid, then minItems is required. If not, then
> it's an ABI break.
>
> Rob
Right. Sorry for that and thanks for the explaination, Rob.
Cheers,
Angelo
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 39+ messages in thread
end of thread, other threads:[~2022-03-30 8:23 UTC | newest]
Thread overview: 39+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-29 11:45 [PATCH v12 0/3] Add basic SoC support for mediatek mt8195 Tinghan Shen
2022-03-29 11:45 ` Tinghan Shen
2022-03-29 11:45 ` Tinghan Shen
2022-03-29 11:45 ` [PATCH v12 1/3] dt-bindings: mmc: mtk-sd: fix yamllint error Tinghan Shen
2022-03-29 11:45 ` Tinghan Shen
2022-03-29 11:45 ` Tinghan Shen
2022-03-29 12:47 ` AngeloGioacchino Del Regno
2022-03-29 12:47 ` AngeloGioacchino Del Regno
2022-03-29 12:47 ` AngeloGioacchino Del Regno
2022-03-30 2:55 ` Tinghan Shen
2022-03-30 2:55 ` Tinghan Shen
2022-03-30 2:55 ` Tinghan Shen
2022-03-29 11:45 ` [PATCH v12 2/3] dt-bindings: mmc: mtk-sd: increase reg maxItems Tinghan Shen
2022-03-29 11:45 ` Tinghan Shen
2022-03-29 11:45 ` Tinghan Shen
2022-03-29 12:43 ` AngeloGioacchino Del Regno
2022-03-29 12:43 ` AngeloGioacchino Del Regno
2022-03-29 12:43 ` AngeloGioacchino Del Regno
2022-03-29 19:10 ` Rob Herring
2022-03-29 19:10 ` Rob Herring
2022-03-29 19:10 ` Rob Herring
2022-03-30 8:20 ` AngeloGioacchino Del Regno
2022-03-30 8:20 ` AngeloGioacchino Del Regno
2022-03-30 8:20 ` AngeloGioacchino Del Regno
2022-03-29 14:27 ` Matthias Brugger
2022-03-29 14:27 ` Matthias Brugger
2022-03-29 14:27 ` Matthias Brugger
2022-03-30 7:33 ` Tinghan Shen
2022-03-30 7:33 ` Tinghan Shen
2022-03-30 7:33 ` Tinghan Shen
2022-03-29 20:38 ` Rob Herring
2022-03-29 20:38 ` Rob Herring
2022-03-29 20:38 ` Rob Herring
2022-03-30 7:25 ` Tinghan Shen
2022-03-30 7:25 ` Tinghan Shen
2022-03-30 7:25 ` Tinghan Shen
2022-03-29 11:45 ` [PATCH v12 3/3] arm64: dts: Add mediatek SoC mt8195 and evaluation board Tinghan Shen
2022-03-29 11:45 ` Tinghan Shen
2022-03-29 11:45 ` Tinghan Shen
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