* [Intel-gfx] [PATCH v3 01/18] drm/i915: Move per-platform power well hooks to intel_display_power_well.c
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-31 7:13 ` Hogander, Jouni
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 02/18] drm/i915: Unexport the for_each_power_well() macros Imre Deak
` (24 subsequent siblings)
25 siblings, 1 reply; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
Move the implementation of platform specific power well hooks to
intel_display_power_well.c, to reduce the clutter in
intel_display_power.c.
The locking of all the power domain/power well state is handled in the
power domain functions in intel_display_power.c using
i915_power_domains::lock. This patch also moves the
chy_phy_powergate_ch/lanes() functions to intel_display_power_well.c
which borrow the same lock to protect the DISPLAY_PHY_CONTROL register
state, which the HW uses both for toggling power wells and power gating
PHY lanes.
No functional change.
v2:
- Clarify in the commit log why CHV functions using the
i915_power_domains::lock were moved, while others locking the power
domain/well state were kept in intel_display_power.c . (Jouni)
- Move forward declaration of chv_phy_powergate_ch/lanes() to
intel_display_power_well.h .
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
.../drm/i915/display/intel_display_power.c | 1759 ----------------
.../drm/i915/display/intel_display_power.h | 5 -
.../i915/display/intel_display_power_well.c | 1817 +++++++++++++++++
.../i915/display/intel_display_power_well.h | 62 +-
drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 +
drivers/gpu/drm/i915/display/intel_pps.c | 1 +
6 files changed, 1846 insertions(+), 1799 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 3dc859032bac7..35a5e36df8206 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -9,24 +9,16 @@
#include "i915_irq.h"
#include "intel_cdclk.h"
#include "intel_combo_phy.h"
-#include "intel_combo_phy_regs.h"
-#include "intel_crt.h"
#include "intel_de.h"
#include "intel_display_power.h"
#include "intel_display_power_well.h"
#include "intel_display_types.h"
#include "intel_dmc.h"
-#include "intel_dpio_phy.h"
-#include "intel_dpll.h"
-#include "intel_hotplug.h"
#include "intel_mchbar_regs.h"
#include "intel_pch_refclk.h"
#include "intel_pcode.h"
#include "intel_pm.h"
-#include "intel_pps.h"
#include "intel_snps_phy.h"
-#include "intel_tc.h"
-#include "intel_vga.h"
#include "vlv_sideband.h"
const char *
@@ -235,604 +227,6 @@ bool intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
return ret;
}
-/*
- * Starting with Haswell, we have a "Power Down Well" that can be turned off
- * when not needed anymore. We have 4 registers that can request the power well
- * to be enabled, and it will only be disabled if none of the registers is
- * requesting it to be enabled.
- */
-static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
- u8 irq_pipe_mask, bool has_vga)
-{
- if (has_vga)
- intel_vga_reset_io_mem(dev_priv);
-
- if (irq_pipe_mask)
- gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
-}
-
-static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
- u8 irq_pipe_mask)
-{
- if (irq_pipe_mask)
- gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
-}
-
-#define ICL_AUX_PW_TO_CH(pw_idx) \
- ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
-
-#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
- ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
-
-static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well)
-{
- int pw_idx = power_well->desc->hsw.idx;
-
- return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
- ICL_AUX_PW_TO_CH(pw_idx);
-}
-
-static struct intel_digital_port *
-aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
- enum aux_ch aux_ch)
-{
- struct intel_digital_port *dig_port = NULL;
- struct intel_encoder *encoder;
-
- for_each_intel_encoder(&dev_priv->drm, encoder) {
- /* We'll check the MST primary port */
- if (encoder->type == INTEL_OUTPUT_DP_MST)
- continue;
-
- dig_port = enc_to_dig_port(encoder);
- if (!dig_port)
- continue;
-
- if (dig_port->aux_ch != aux_ch) {
- dig_port = NULL;
- continue;
- }
-
- break;
- }
-
- return dig_port;
-}
-
-static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915,
- const struct i915_power_well *power_well)
-{
- enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
- struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch);
-
- return intel_port_to_phy(i915, dig_port->base.port);
-}
-
-static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well,
- bool timeout_expected)
-{
- const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
- int enable_delay = power_well->desc->hsw.fixed_enable_delay;
-
- /*
- * For some power wells we're not supposed to watch the status bit for
- * an ack, but rather just wait a fixed amount of time and then
- * proceed. This is only used on DG2.
- */
- if (IS_DG2(dev_priv) && enable_delay) {
- usleep_range(enable_delay, 2 * enable_delay);
- return;
- }
-
- /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
- if (intel_de_wait_for_set(dev_priv, regs->driver,
- HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {
- drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n",
- intel_power_well_name(power_well));
-
- drm_WARN_ON(&dev_priv->drm, !timeout_expected);
-
- }
-}
-
-static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
- const struct i915_power_well_regs *regs,
- int pw_idx)
-{
- u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
- u32 ret;
-
- ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0;
- ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0;
- if (regs->kvmr.reg)
- ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0;
- ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0;
-
- return ret;
-}
-
-static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
- bool disabled;
- u32 reqs;
-
- /*
- * Bspec doesn't require waiting for PWs to get disabled, but still do
- * this for paranoia. The known cases where a PW will be forced on:
- * - a KVMR request on any power well via the KVMR request register
- * - a DMC request on PW1 and MISC_IO power wells via the BIOS and
- * DEBUG request registers
- * Skip the wait in case any of the request bits are set and print a
- * diagnostic message.
- */
- wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) &
- HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
- (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1);
- if (disabled)
- return;
-
- drm_dbg_kms(&dev_priv->drm,
- "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
- intel_power_well_name(power_well),
- !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
-}
-
-static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
- enum skl_power_gate pg)
-{
- /* Timeout 5us for PG#0, for other PGs 1us */
- drm_WARN_ON(&dev_priv->drm,
- intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS,
- SKL_FUSE_PG_DIST_STATUS(pg), 1));
-}
-
-static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
- u32 val;
-
- if (power_well->desc->hsw.has_fuses) {
- enum skl_power_gate pg;
-
- pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
- SKL_PW_CTL_IDX_TO_PG(pw_idx);
-
- /* Wa_16013190616:adlp */
- if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1)
- intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC);
-
- /*
- * For PW1 we have to wait both for the PW0/PG0 fuse state
- * before enabling the power well and PW1/PG1's own fuse
- * state after the enabling. For all other power wells with
- * fuses we only have to wait for that PW/PG's fuse state
- * after the enabling.
- */
- if (pg == SKL_PG1)
- gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
- }
-
- val = intel_de_read(dev_priv, regs->driver);
- intel_de_write(dev_priv, regs->driver,
- val | HSW_PWR_WELL_CTL_REQ(pw_idx));
-
- hsw_wait_for_power_well_enable(dev_priv, power_well, false);
-
- if (power_well->desc->hsw.has_fuses) {
- enum skl_power_gate pg;
-
- pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
- SKL_PW_CTL_IDX_TO_PG(pw_idx);
- gen9_wait_for_power_well_fuses(dev_priv, pg);
- }
-
- hsw_power_well_post_enable(dev_priv,
- power_well->desc->hsw.irq_pipe_mask,
- power_well->desc->hsw.has_vga);
-}
-
-static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
- u32 val;
-
- hsw_power_well_pre_disable(dev_priv,
- power_well->desc->hsw.irq_pipe_mask);
-
- val = intel_de_read(dev_priv, regs->driver);
- intel_de_write(dev_priv, regs->driver,
- val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
- hsw_wait_for_power_well_disable(dev_priv, power_well);
-}
-
-static void
-icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
- enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
- u32 val;
-
- drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
-
- val = intel_de_read(dev_priv, regs->driver);
- intel_de_write(dev_priv, regs->driver,
- val | HSW_PWR_WELL_CTL_REQ(pw_idx));
-
- if (DISPLAY_VER(dev_priv) < 12) {
- val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
- intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
- val | ICL_LANE_ENABLE_AUX);
- }
-
- hsw_wait_for_power_well_enable(dev_priv, power_well, false);
-
- /* Display WA #1178: icl */
- if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
- !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
- val = intel_de_read(dev_priv, ICL_AUX_ANAOVRD1(pw_idx));
- val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
- intel_de_write(dev_priv, ICL_AUX_ANAOVRD1(pw_idx), val);
- }
-}
-
-static void
-icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
- enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
- u32 val;
-
- drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
-
- val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
- intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
- val & ~ICL_LANE_ENABLE_AUX);
-
- val = intel_de_read(dev_priv, regs->driver);
- intel_de_write(dev_priv, regs->driver,
- val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
-
- hsw_wait_for_power_well_disable(dev_priv, power_well);
-}
-
-#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
-
-static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well,
- struct intel_digital_port *dig_port)
-{
- if (drm_WARN_ON(&dev_priv->drm, !dig_port))
- return;
-
- if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
- return;
-
- drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
-}
-
-#else
-
-static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well,
- struct intel_digital_port *dig_port)
-{
-}
-
-#endif
-
-#define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1)
-
-static void icl_tc_cold_exit(struct drm_i915_private *i915)
-{
- int ret, tries = 0;
-
- while (1) {
- ret = snb_pcode_write_timeout(i915, ICL_PCODE_EXIT_TCCOLD, 0,
- 250, 1);
- if (ret != -EAGAIN || ++tries == 3)
- break;
- msleep(1);
- }
-
- /* Spec states that TC cold exit can take up to 1ms to complete */
- if (!ret)
- msleep(1);
-
- /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */
- drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" :
- "succeeded");
-}
-
-static void
-icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
- struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
- const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- bool is_tbt = power_well->desc->hsw.is_tc_tbt;
- bool timeout_expected;
- u32 val;
-
- icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
-
- val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch));
- val &= ~DP_AUX_CH_CTL_TBT_IO;
- if (is_tbt)
- val |= DP_AUX_CH_CTL_TBT_IO;
- intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val);
-
- val = intel_de_read(dev_priv, regs->driver);
- intel_de_write(dev_priv, regs->driver,
- val | HSW_PWR_WELL_CTL_REQ(power_well->desc->hsw.idx));
-
- /*
- * An AUX timeout is expected if the TBT DP tunnel is down,
- * or need to enable AUX on a legacy TypeC port as part of the TC-cold
- * exit sequence.
- */
- timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port);
- if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
- icl_tc_cold_exit(dev_priv);
-
- hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected);
-
- if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) {
- enum tc_port tc_port;
-
- tc_port = TGL_AUX_PW_TO_TC_PORT(power_well->desc->hsw.idx);
- intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
- HIP_INDEX_VAL(tc_port, 0x2));
-
- if (intel_de_wait_for_set(dev_priv, DKL_CMN_UC_DW_27(tc_port),
- DKL_CMN_UC_DW27_UC_HEALTH, 1))
- drm_warn(&dev_priv->drm,
- "Timeout waiting TC uC health\n");
- }
-}
-
-static void
-icl_aux_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
-
- if (intel_phy_is_tc(dev_priv, phy))
- return icl_tc_phy_aux_power_well_enable(dev_priv, power_well);
- else if (IS_ICELAKE(dev_priv))
- return icl_combo_phy_aux_power_well_enable(dev_priv,
- power_well);
- else
- return hsw_power_well_enable(dev_priv, power_well);
-}
-
-static void
-icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
-
- if (intel_phy_is_tc(dev_priv, phy))
- return hsw_power_well_disable(dev_priv, power_well);
- else if (IS_ICELAKE(dev_priv))
- return icl_combo_phy_aux_power_well_disable(dev_priv,
- power_well);
- else
- return hsw_power_well_disable(dev_priv, power_well);
-}
-
-/*
- * We should only use the power well if we explicitly asked the hardware to
- * enable it, so check if it's enabled and also check if we've requested it to
- * be enabled.
- */
-static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- enum i915_power_well_id id = power_well->desc->id;
- int pw_idx = power_well->desc->hsw.idx;
- u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
- HSW_PWR_WELL_CTL_STATE(pw_idx);
- u32 val;
-
- val = intel_de_read(dev_priv, regs->driver);
-
- /*
- * On GEN9 big core due to a DMC bug the driver's request bits for PW1
- * and the MISC_IO PW will be not restored, so check instead for the
- * BIOS's own request bits, which are forced-on for these power wells
- * when exiting DC5/6.
- */
- if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
- (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
- val |= intel_de_read(dev_priv, regs->bios);
-
- return (val & mask) == mask;
-}
-
-static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
-{
- drm_WARN_ONCE(&dev_priv->drm,
- (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9),
- "DC9 already programmed to be enabled.\n");
- drm_WARN_ONCE(&dev_priv->drm,
- intel_de_read(dev_priv, DC_STATE_EN) &
- DC_STATE_EN_UPTO_DC5,
- "DC5 still not disabled to enable DC9.\n");
- drm_WARN_ONCE(&dev_priv->drm,
- intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) &
- HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
- "Power well 2 on.\n");
- drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
- "Interrupts not disabled yet.\n");
-
- /*
- * TODO: check for the following to verify the conditions to enter DC9
- * state are satisfied:
- * 1] Check relevant display engine registers to verify if mode set
- * disable sequence was followed.
- * 2] Check if display uninitialize sequence is initialized.
- */
-}
-
-static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
-{
- drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
- "Interrupts not disabled yet.\n");
- drm_WARN_ONCE(&dev_priv->drm,
- intel_de_read(dev_priv, DC_STATE_EN) &
- DC_STATE_EN_UPTO_DC5,
- "DC5 still not disabled.\n");
-
- /*
- * TODO: check for the following to verify DC9 state was indeed
- * entered before programming to disable it:
- * 1] Check relevant display engine registers to verify if mode
- * set disable sequence was followed.
- * 2] Check if display uninitialize sequence is initialized.
- */
-}
-
-static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
- u32 state)
-{
- int rewrites = 0;
- int rereads = 0;
- u32 v;
-
- intel_de_write(dev_priv, DC_STATE_EN, state);
-
- /* It has been observed that disabling the dc6 state sometimes
- * doesn't stick and dmc keeps returning old value. Make sure
- * the write really sticks enough times and also force rewrite until
- * we are confident that state is exactly what we want.
- */
- do {
- v = intel_de_read(dev_priv, DC_STATE_EN);
-
- if (v != state) {
- intel_de_write(dev_priv, DC_STATE_EN, state);
- rewrites++;
- rereads = 0;
- } else if (rereads++ > 5) {
- break;
- }
-
- } while (rewrites < 100);
-
- if (v != state)
- drm_err(&dev_priv->drm,
- "Writing dc state to 0x%x failed, now 0x%x\n",
- state, v);
-
- /* Most of the times we need one retry, avoid spam */
- if (rewrites > 1)
- drm_dbg_kms(&dev_priv->drm,
- "Rewrote dc state to 0x%x %d times\n",
- state, rewrites);
-}
-
-static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
-{
- u32 mask;
-
- mask = DC_STATE_EN_UPTO_DC5;
-
- if (DISPLAY_VER(dev_priv) >= 12)
- mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
- | DC_STATE_EN_DC9;
- else if (DISPLAY_VER(dev_priv) == 11)
- mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
- else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- mask |= DC_STATE_EN_DC9;
- else
- mask |= DC_STATE_EN_UPTO_DC6;
-
- return mask;
-}
-
-static void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
-{
- u32 val;
-
- if (!HAS_DISPLAY(dev_priv))
- return;
-
- val = intel_de_read(dev_priv, DC_STATE_EN) & gen9_dc_mask(dev_priv);
-
- drm_dbg_kms(&dev_priv->drm,
- "Resetting DC state tracking from %02x to %02x\n",
- dev_priv->dmc.dc_state, val);
- dev_priv->dmc.dc_state = val;
-}
-
-/**
- * gen9_set_dc_state - set target display C power state
- * @dev_priv: i915 device instance
- * @state: target DC power state
- * - DC_STATE_DISABLE
- * - DC_STATE_EN_UPTO_DC5
- * - DC_STATE_EN_UPTO_DC6
- * - DC_STATE_EN_DC9
- *
- * Signal to DMC firmware/HW the target DC power state passed in @state.
- * DMC/HW can turn off individual display clocks and power rails when entering
- * a deeper DC power state (higher in number) and turns these back when exiting
- * that state to a shallower power state (lower in number). The HW will decide
- * when to actually enter a given state on an on-demand basis, for instance
- * depending on the active state of display pipes. The state of display
- * registers backed by affected power rails are saved/restored as needed.
- *
- * Based on the above enabling a deeper DC power state is asynchronous wrt.
- * enabling it. Disabling a deeper power state is synchronous: for instance
- * setting %DC_STATE_DISABLE won't complete until all HW resources are turned
- * back on and register state is restored. This is guaranteed by the MMIO write
- * to DC_STATE_EN blocking until the state is restored.
- */
-static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
-{
- u32 val;
- u32 mask;
-
- if (!HAS_DISPLAY(dev_priv))
- return;
-
- if (drm_WARN_ON_ONCE(&dev_priv->drm,
- state & ~dev_priv->dmc.allowed_dc_mask))
- state &= dev_priv->dmc.allowed_dc_mask;
-
- val = intel_de_read(dev_priv, DC_STATE_EN);
- mask = gen9_dc_mask(dev_priv);
- drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n",
- val & mask, state);
-
- /* Check if DMC is ignoring our DC state requests */
- if ((val & mask) != dev_priv->dmc.dc_state)
- drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
- dev_priv->dmc.dc_state, val & mask);
-
- val &= ~mask;
- val |= state;
-
- gen9_write_dc_state(dev_priv, val);
-
- dev_priv->dmc.dc_state = val & mask;
-}
-
static u32
sanitize_target_dc_state(struct drm_i915_private *dev_priv,
u32 target_dc_state)
@@ -858,65 +252,6 @@ sanitize_target_dc_state(struct drm_i915_private *dev_priv,
return target_dc_state;
}
-static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
-{
- drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n");
- gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
-}
-
-static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
-{
- u32 val;
-
- drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n");
- val = intel_de_read(dev_priv, DC_STATE_EN);
- val &= ~DC_STATE_DC3CO_STATUS;
- intel_de_write(dev_priv, DC_STATE_EN, val);
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
- /*
- * Delay of 200us DC3CO Exit time B.Spec 49196
- */
- usleep_range(200, 210);
-}
-
-static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
-{
- assert_can_enable_dc9(dev_priv);
-
- drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n");
- /*
- * Power sequencer reset is not needed on
- * platforms with South Display Engine on PCH,
- * because PPS registers are always on.
- */
- if (!HAS_PCH_SPLIT(dev_priv))
- intel_pps_reset_all(dev_priv);
- gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
-}
-
-static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
-{
- assert_can_disable_dc9(dev_priv);
-
- drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n");
-
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
-
- intel_pps_unlock_regs_wa(dev_priv);
-}
-
-static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
-{
- drm_WARN_ONCE(&dev_priv->drm,
- !intel_de_read(dev_priv,
- DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
- "DMC program storage start is NULL\n");
- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
- "DMC SSP Base Not fine\n");
- drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
- "DMC HTP Not fine\n");
-}
-
/**
* intel_display_power_set_target_dc_state - Set target dc state.
* @dev_priv: i915 device
@@ -961,912 +296,8 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
mutex_unlock(&power_domains->lock);
}
-static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
-{
- enum i915_power_well_id high_pg;
-
- /* Power wells at this level and above must be disabled for DC5 entry */
- if (DISPLAY_VER(dev_priv) == 12)
- high_pg = ICL_DISP_PW_3;
- else
- high_pg = SKL_DISP_PW_2;
-
- drm_WARN_ONCE(&dev_priv->drm,
- intel_display_power_well_is_enabled(dev_priv, high_pg),
- "Power wells above platform's DC5 limit still enabled.\n");
-
- drm_WARN_ONCE(&dev_priv->drm,
- (intel_de_read(dev_priv, DC_STATE_EN) &
- DC_STATE_EN_UPTO_DC5),
- "DC5 already programmed to be enabled.\n");
- assert_rpm_wakelock_held(&dev_priv->runtime_pm);
-
- assert_dmc_loaded(dev_priv);
-}
-
-static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
-{
- assert_can_enable_dc5(dev_priv);
-
- drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n");
-
- /* Wa Display #1183: skl,kbl,cfl */
- if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
- intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
- intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
-
- gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
-}
-
-static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
-{
- drm_WARN_ONCE(&dev_priv->drm,
- intel_de_read(dev_priv, UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
- "Backlight is not disabled.\n");
- drm_WARN_ONCE(&dev_priv->drm,
- (intel_de_read(dev_priv, DC_STATE_EN) &
- DC_STATE_EN_UPTO_DC6),
- "DC6 already programmed to be enabled.\n");
-
- assert_dmc_loaded(dev_priv);
-}
-
-static void skl_enable_dc6(struct drm_i915_private *dev_priv)
-{
- assert_can_enable_dc6(dev_priv);
-
- drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n");
-
- /* Wa Display #1183: skl,kbl,cfl */
- if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
- intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
- intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
-
- gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
-}
-
-static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
- u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
- u32 bios_req = intel_de_read(dev_priv, regs->bios);
-
- /* Take over the request bit if set by BIOS. */
- if (bios_req & mask) {
- u32 drv_req = intel_de_read(dev_priv, regs->driver);
-
- if (!(drv_req & mask))
- intel_de_write(dev_priv, regs->driver, drv_req | mask);
- intel_de_write(dev_priv, regs->bios, bios_req & ~mask);
- }
-}
-
-static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy);
-}
-
-static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy);
-}
-
-static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc->bxt.phy);
-}
-
-static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
-{
- struct i915_power_well *power_well;
-
- power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
- if (intel_power_well_refcount(power_well) > 0)
- bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
-
- power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
- if (intel_power_well_refcount(power_well) > 0)
- bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
-
- if (IS_GEMINILAKE(dev_priv)) {
- power_well = lookup_power_well(dev_priv,
- GLK_DISP_PW_DPIO_CMN_C);
- if (intel_power_well_refcount(power_well) > 0)
- bxt_ddi_phy_verify_state(dev_priv,
- power_well->desc->bxt.phy);
- }
-}
-
-static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- return ((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
- (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
-}
-
-static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
-{
- u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv);
- u8 enabled_dbuf_slices = dev_priv->dbuf.enabled_slices;
-
- drm_WARN(&dev_priv->drm,
- hw_enabled_dbuf_slices != enabled_dbuf_slices,
- "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n",
- hw_enabled_dbuf_slices,
- enabled_dbuf_slices);
-}
-
-static void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
-{
- struct intel_cdclk_config cdclk_config = {};
-
- if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) {
- tgl_disable_dc3co(dev_priv);
- return;
- }
-
- gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
-
- if (!HAS_DISPLAY(dev_priv))
- return;
-
- intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
- /* Can't read out voltage_level so can't use intel_cdclk_changed() */
- drm_WARN_ON(&dev_priv->drm,
- intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
- &cdclk_config));
-
- gen9_assert_dbuf_enabled(dev_priv);
-
- if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
- bxt_verify_ddi_phy_power_wells(dev_priv);
-
- if (DISPLAY_VER(dev_priv) >= 11)
- /*
- * DMC retains HW context only for port A, the other combo
- * PHY's HW context for port B is lost after DC transitions,
- * so we need to restore it manually.
- */
- intel_combo_phy_init(dev_priv);
-}
-
-static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- gen9_disable_dc_states(dev_priv);
-}
-
-static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- if (!intel_dmc_has_payload(dev_priv))
- return;
-
- switch (dev_priv->dmc.target_dc_state) {
- case DC_STATE_EN_DC3CO:
- tgl_enable_dc3co(dev_priv);
- break;
- case DC_STATE_EN_UPTO_DC6:
- skl_enable_dc6(dev_priv);
- break;
- case DC_STATE_EN_UPTO_DC5:
- gen9_enable_dc5(dev_priv);
- break;
- }
-}
-
-static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
-}
-
-static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
-}
-
-static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- return true;
-}
-
-static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
- i830_enable_pipe(dev_priv, PIPE_A);
- if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
- i830_enable_pipe(dev_priv, PIPE_B);
-}
-
-static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- i830_disable_pipe(dev_priv, PIPE_B);
- i830_disable_pipe(dev_priv, PIPE_A);
-}
-
-static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
- intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
-}
-
-static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- if (intel_power_well_refcount(power_well) > 0)
- i830_pipes_power_well_enable(dev_priv, power_well);
- else
- i830_pipes_power_well_disable(dev_priv, power_well);
-}
-
-static void vlv_set_power_well(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well, bool enable)
-{
- int pw_idx = power_well->desc->vlv.idx;
- u32 mask;
- u32 state;
- u32 ctrl;
-
- mask = PUNIT_PWRGT_MASK(pw_idx);
- state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
- PUNIT_PWRGT_PWR_GATE(pw_idx);
-
- vlv_punit_get(dev_priv);
-
-#define COND \
- ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
-
- if (COND)
- goto out;
-
- ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
- ctrl &= ~mask;
- ctrl |= state;
- vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
-
- if (wait_for(COND, 100))
- drm_err(&dev_priv->drm,
- "timeout setting power well state %08x (%08x)\n",
- state,
- vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
-
-#undef COND
-
-out:
- vlv_punit_put(dev_priv);
-}
-
-static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- vlv_set_power_well(dev_priv, power_well, true);
-}
-
-static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- vlv_set_power_well(dev_priv, power_well, false);
-}
-
-static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- int pw_idx = power_well->desc->vlv.idx;
- bool enabled = false;
- u32 mask;
- u32 state;
- u32 ctrl;
-
- mask = PUNIT_PWRGT_MASK(pw_idx);
- ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
-
- vlv_punit_get(dev_priv);
-
- state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
- /*
- * We only ever set the power-on and power-gate states, anything
- * else is unexpected.
- */
- drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) &&
- state != PUNIT_PWRGT_PWR_GATE(pw_idx));
- if (state == ctrl)
- enabled = true;
-
- /*
- * A transient state at this point would mean some unexpected party
- * is poking at the power controls too.
- */
- ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
- drm_WARN_ON(&dev_priv->drm, ctrl != state);
-
- vlv_punit_put(dev_priv);
-
- return enabled;
-}
-
-static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
-{
- u32 val;
-
- /*
- * On driver load, a pipe may be active and driving a DSI display.
- * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
- * (and never recovering) in this case. intel_dsi_post_disable() will
- * clear it when we turn off the display.
- */
- val = intel_de_read(dev_priv, DSPCLK_GATE_D);
- val &= DPOUNIT_CLOCK_GATE_DISABLE;
- val |= VRHUNIT_CLOCK_GATE_DISABLE;
- intel_de_write(dev_priv, DSPCLK_GATE_D, val);
-
- /*
- * Disable trickle feed and enable pnd deadline calculation
- */
- intel_de_write(dev_priv, MI_ARB_VLV,
- MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
- intel_de_write(dev_priv, CBR1_VLV, 0);
-
- drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
- intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
- DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq,
- 1000));
-}
-
-static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
-{
- struct intel_encoder *encoder;
- enum pipe pipe;
-
- /*
- * Enable the CRI clock source so we can get at the
- * display and the reference clock for VGA
- * hotplug / manual detection. Supposedly DSI also
- * needs the ref clock up and running.
- *
- * CHV DPLL B/C have some issues if VGA mode is enabled.
- */
- for_each_pipe(dev_priv, pipe) {
- u32 val = intel_de_read(dev_priv, DPLL(pipe));
-
- val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
- if (pipe != PIPE_A)
- val |= DPLL_INTEGRATED_CRI_CLK_VLV;
-
- intel_de_write(dev_priv, DPLL(pipe), val);
- }
-
- vlv_init_display_clock_gating(dev_priv);
-
- spin_lock_irq(&dev_priv->irq_lock);
- valleyview_enable_display_irqs(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
-
- /*
- * During driver initialization/resume we can avoid restoring the
- * part of the HW/SW state that will be inited anyway explicitly.
- */
- if (dev_priv->power_domains.initializing)
- return;
-
- intel_hpd_init(dev_priv);
- intel_hpd_poll_disable(dev_priv);
-
- /* Re-enable the ADPA, if we have one */
- for_each_intel_encoder(&dev_priv->drm, encoder) {
- if (encoder->type == INTEL_OUTPUT_ANALOG)
- intel_crt_reset(&encoder->base);
- }
-
- intel_vga_redisable_power_on(dev_priv);
-
- intel_pps_unlock_regs_wa(dev_priv);
-}
-
-static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
-{
- spin_lock_irq(&dev_priv->irq_lock);
- valleyview_disable_display_irqs(dev_priv);
- spin_unlock_irq(&dev_priv->irq_lock);
-
- /* make sure we're done processing display irqs */
- intel_synchronize_irq(dev_priv);
-
- intel_pps_reset_all(dev_priv);
-
- /* Prevent us from re-enabling polling on accident in late suspend */
- if (!dev_priv->drm.dev->power.is_suspended)
- intel_hpd_poll_enable(dev_priv);
-}
-
-static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- vlv_set_power_well(dev_priv, power_well, true);
-
- vlv_display_power_well_init(dev_priv);
-}
-
-static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- vlv_display_power_well_deinit(dev_priv);
-
- vlv_set_power_well(dev_priv, power_well, false);
-}
-
-static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- /* since ref/cri clock was enabled */
- udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
-
- vlv_set_power_well(dev_priv, power_well, true);
-
- /*
- * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
- * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
- * a. GUnit 0x2110 bit[0] set to 1 (def 0)
- * b. The other bits such as sfr settings / modesel may all
- * be set to 0.
- *
- * This should only be done on init and resume from S3 with
- * both PLLs disabled, or we risk losing DPIO and PLL
- * synchronization.
- */
- intel_de_write(dev_priv, DPIO_CTL,
- intel_de_read(dev_priv, DPIO_CTL) | DPIO_CMNRST);
-}
-
-static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- enum pipe pipe;
-
- for_each_pipe(dev_priv, pipe)
- assert_pll_disabled(dev_priv, pipe);
-
- /* Assert common reset */
- intel_de_write(dev_priv, DPIO_CTL,
- intel_de_read(dev_priv, DPIO_CTL) & ~DPIO_CMNRST);
-
- vlv_set_power_well(dev_priv, power_well, false);
-}
-
#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
-#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
-
-static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
-{
- struct i915_power_well *cmn_bc =
- lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
- struct i915_power_well *cmn_d =
- lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
- u32 phy_control = dev_priv->chv_phy_control;
- u32 phy_status = 0;
- u32 phy_status_mask = 0xffffffff;
-
- /*
- * The BIOS can leave the PHY is some weird state
- * where it doesn't fully power down some parts.
- * Disable the asserts until the PHY has been fully
- * reset (ie. the power well has been disabled at
- * least once).
- */
- if (!dev_priv->chv_phy_assert[DPIO_PHY0])
- phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
- PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
- PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
- PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
- PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
- PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
-
- if (!dev_priv->chv_phy_assert[DPIO_PHY1])
- phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
- PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
- PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
-
- if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
- phy_status |= PHY_POWERGOOD(DPIO_PHY0);
-
- /* this assumes override is only used to enable lanes */
- if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
- phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
-
- if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
- phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
-
- /* CL1 is on whenever anything is on in either channel */
- if (BITS_SET(phy_control,
- PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
- PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
- phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
-
- /*
- * The DPLLB check accounts for the pipe B + port A usage
- * with CL2 powered up but all the lanes in the second channel
- * powered down.
- */
- if (BITS_SET(phy_control,
- PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
- (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
- phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
-
- if (BITS_SET(phy_control,
- PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
- phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
- if (BITS_SET(phy_control,
- PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
- phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
-
- if (BITS_SET(phy_control,
- PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
- phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
- if (BITS_SET(phy_control,
- PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
- phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
- }
-
- if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
- phy_status |= PHY_POWERGOOD(DPIO_PHY1);
-
- /* this assumes override is only used to enable lanes */
- if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
- phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
-
- if (BITS_SET(phy_control,
- PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
- phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
-
- if (BITS_SET(phy_control,
- PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
- phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
- if (BITS_SET(phy_control,
- PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
- phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
- }
-
- phy_status &= phy_status_mask;
-
- /*
- * The PHY may be busy with some initial calibration and whatnot,
- * so the power state can take a while to actually change.
- */
- if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS,
- phy_status_mask, phy_status, 10))
- drm_err(&dev_priv->drm,
- "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
- intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
- phy_status, dev_priv->chv_phy_control);
-}
-
-#undef BITS_SET
-
-static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- enum dpio_phy phy;
- enum pipe pipe;
- u32 tmp;
-
- drm_WARN_ON_ONCE(&dev_priv->drm,
- power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
- power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
-
- if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
- pipe = PIPE_A;
- phy = DPIO_PHY0;
- } else {
- pipe = PIPE_C;
- phy = DPIO_PHY1;
- }
-
- /* since ref/cri clock was enabled */
- udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
- vlv_set_power_well(dev_priv, power_well, true);
-
- /* Poll for phypwrgood signal */
- if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
- PHY_POWERGOOD(phy), 1))
- drm_err(&dev_priv->drm, "Display PHY %d is not power up\n",
- phy);
-
- vlv_dpio_get(dev_priv);
-
- /* Enable dynamic power down */
- tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
- tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
- DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
- vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
-
- if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
- tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
- tmp |= DPIO_DYNPWRDOWNEN_CH1;
- vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
- } else {
- /*
- * Force the non-existing CL2 off. BXT does this
- * too, so maybe it saves some power even though
- * CL2 doesn't exist?
- */
- tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
- tmp |= DPIO_CL2_LDOFUSE_PWRENB;
- vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
- }
-
- vlv_dpio_put(dev_priv);
-
- dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
- intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
-
- drm_dbg_kms(&dev_priv->drm,
- "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
- phy, dev_priv->chv_phy_control);
-
- assert_chv_phy_status(dev_priv);
-}
-
-static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- enum dpio_phy phy;
-
- drm_WARN_ON_ONCE(&dev_priv->drm,
- power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
- power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
-
- if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
- phy = DPIO_PHY0;
- assert_pll_disabled(dev_priv, PIPE_A);
- assert_pll_disabled(dev_priv, PIPE_B);
- } else {
- phy = DPIO_PHY1;
- assert_pll_disabled(dev_priv, PIPE_C);
- }
-
- dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
- intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
-
- vlv_set_power_well(dev_priv, power_well, false);
-
- drm_dbg_kms(&dev_priv->drm,
- "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
- phy, dev_priv->chv_phy_control);
-
- /* PHY is fully reset now, so we can enable the PHY state asserts */
- dev_priv->chv_phy_assert[phy] = true;
-
- assert_chv_phy_status(dev_priv);
-}
-
-static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
- enum dpio_channel ch, bool override, unsigned int mask)
-{
- enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
- u32 reg, val, expected, actual;
-
- /*
- * The BIOS can leave the PHY is some weird state
- * where it doesn't fully power down some parts.
- * Disable the asserts until the PHY has been fully
- * reset (ie. the power well has been disabled at
- * least once).
- */
- if (!dev_priv->chv_phy_assert[phy])
- return;
-
- if (ch == DPIO_CH0)
- reg = _CHV_CMN_DW0_CH0;
- else
- reg = _CHV_CMN_DW6_CH1;
-
- vlv_dpio_get(dev_priv);
- val = vlv_dpio_read(dev_priv, pipe, reg);
- vlv_dpio_put(dev_priv);
-
- /*
- * This assumes !override is only used when the port is disabled.
- * All lanes should power down even without the override when
- * the port is disabled.
- */
- if (!override || mask == 0xf) {
- expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
- /*
- * If CH1 common lane is not active anymore
- * (eg. for pipe B DPLL) the entire channel will
- * shut down, which causes the common lane registers
- * to read as 0. That means we can't actually check
- * the lane power down status bits, but as the entire
- * register reads as 0 it's a good indication that the
- * channel is indeed entirely powered down.
- */
- if (ch == DPIO_CH1 && val == 0)
- expected = 0;
- } else if (mask != 0x0) {
- expected = DPIO_ANYDL_POWERDOWN;
- } else {
- expected = 0;
- }
-
- if (ch == DPIO_CH0)
- actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
- else
- actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
- actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
-
- drm_WARN(&dev_priv->drm, actual != expected,
- "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
- !!(actual & DPIO_ALLDL_POWERDOWN),
- !!(actual & DPIO_ANYDL_POWERDOWN),
- !!(expected & DPIO_ALLDL_POWERDOWN),
- !!(expected & DPIO_ANYDL_POWERDOWN),
- reg, val);
-}
-
-bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
- enum dpio_channel ch, bool override)
-{
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
- bool was_override;
-
- mutex_lock(&power_domains->lock);
-
- was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
-
- if (override == was_override)
- goto out;
-
- if (override)
- dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
- else
- dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
-
- intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
-
- drm_dbg_kms(&dev_priv->drm,
- "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
- phy, ch, dev_priv->chv_phy_control);
-
- assert_chv_phy_status(dev_priv);
-
-out:
- mutex_unlock(&power_domains->lock);
-
- return was_override;
-}
-
-void chv_phy_powergate_lanes(struct intel_encoder *encoder,
- bool override, unsigned int mask)
-{
- struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
- struct i915_power_domains *power_domains = &dev_priv->power_domains;
- enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
- enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
-
- mutex_lock(&power_domains->lock);
-
- dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
- dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
-
- if (override)
- dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
- else
- dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
-
- intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
-
- drm_dbg_kms(&dev_priv->drm,
- "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
- phy, ch, mask, dev_priv->chv_phy_control);
-
- assert_chv_phy_status(dev_priv);
-
- assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
-
- mutex_unlock(&power_domains->lock);
-}
-
-static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- enum pipe pipe = PIPE_A;
- bool enabled;
- u32 state, ctrl;
-
- vlv_punit_get(dev_priv);
-
- state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);
- /*
- * We only ever set the power-on and power-gate states, anything
- * else is unexpected.
- */
- drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) &&
- state != DP_SSS_PWR_GATE(pipe));
- enabled = state == DP_SSS_PWR_ON(pipe);
-
- /*
- * A transient state at this point would mean some unexpected party
- * is poking at the power controls too.
- */
- ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);
- drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state);
-
- vlv_punit_put(dev_priv);
-
- return enabled;
-}
-
-static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well,
- bool enable)
-{
- enum pipe pipe = PIPE_A;
- u32 state;
- u32 ctrl;
-
- state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
-
- vlv_punit_get(dev_priv);
-
-#define COND \
- ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state)
-
- if (COND)
- goto out;
-
- ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
- ctrl &= ~DP_SSC_MASK(pipe);
- ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
- vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl);
-
- if (wait_for(COND, 100))
- drm_err(&dev_priv->drm,
- "timeout setting power well state %08x (%08x)\n",
- state,
- vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM));
-
-#undef COND
-
-out:
- vlv_punit_put(dev_priv);
-}
-
-static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
- dev_priv->chv_phy_control);
-}
-
-static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- chv_set_pipe_power_well(dev_priv, power_well, true);
-
- vlv_display_power_well_init(dev_priv);
-}
-
-static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- vlv_display_power_well_deinit(dev_priv);
-
- chv_set_pipe_power_well(dev_priv, power_well, false);
-}
-
static u64 __async_put_domains_mask(struct i915_power_domains *power_domains)
{
return power_domains->async_put_domains[0] |
@@ -3046,27 +1477,6 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
#define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
#define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
-static const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
- .sync_hw = i9xx_power_well_sync_hw_noop,
- .enable = i9xx_always_on_power_well_noop,
- .disable = i9xx_always_on_power_well_noop,
- .is_enabled = i9xx_always_on_power_well_enabled,
-};
-
-static const struct i915_power_well_ops chv_pipe_power_well_ops = {
- .sync_hw = chv_pipe_power_well_sync_hw,
- .enable = chv_pipe_power_well_enable,
- .disable = chv_pipe_power_well_disable,
- .is_enabled = chv_pipe_power_well_enabled,
-};
-
-static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
- .sync_hw = i9xx_power_well_sync_hw_noop,
- .enable = chv_dpio_cmn_power_well_enable,
- .disable = chv_dpio_cmn_power_well_disable,
- .is_enabled = vlv_power_well_enabled,
-};
-
static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
{
.name = "always-on",
@@ -3077,13 +1487,6 @@ static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
},
};
-static const struct i915_power_well_ops i830_pipes_power_well_ops = {
- .sync_hw = i830_pipes_power_well_sync_hw,
- .enable = i830_pipes_power_well_enable,
- .disable = i830_pipes_power_well_disable,
- .is_enabled = i830_pipes_power_well_enabled,
-};
-
static const struct i915_power_well_desc i830_power_wells[] = {
{
.name = "always-on",
@@ -3100,35 +1503,6 @@ static const struct i915_power_well_desc i830_power_wells[] = {
},
};
-static const struct i915_power_well_regs hsw_power_well_regs = {
- .bios = HSW_PWR_WELL_CTL1,
- .driver = HSW_PWR_WELL_CTL2,
- .kvmr = HSW_PWR_WELL_CTL3,
- .debug = HSW_PWR_WELL_CTL4,
-};
-
-static const struct i915_power_well_ops hsw_power_well_ops = {
- .regs = &hsw_power_well_regs,
- .sync_hw = hsw_power_well_sync_hw,
- .enable = hsw_power_well_enable,
- .disable = hsw_power_well_disable,
- .is_enabled = hsw_power_well_enabled,
-};
-
-static const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
- .sync_hw = i9xx_power_well_sync_hw_noop,
- .enable = gen9_dc_off_power_well_enable,
- .disable = gen9_dc_off_power_well_disable,
- .is_enabled = gen9_dc_off_power_well_enabled,
-};
-
-static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
- .sync_hw = i9xx_power_well_sync_hw_noop,
- .enable = bxt_dpio_cmn_power_well_enable,
- .disable = bxt_dpio_cmn_power_well_disable,
- .is_enabled = bxt_dpio_cmn_power_well_enabled,
-};
-
static const struct i915_power_well_desc hsw_power_wells[] = {
{
.name = "always-on",
@@ -3170,27 +1544,6 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
},
};
-static const struct i915_power_well_ops vlv_display_power_well_ops = {
- .sync_hw = i9xx_power_well_sync_hw_noop,
- .enable = vlv_display_power_well_enable,
- .disable = vlv_display_power_well_disable,
- .is_enabled = vlv_power_well_enabled,
-};
-
-static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
- .sync_hw = i9xx_power_well_sync_hw_noop,
- .enable = vlv_dpio_cmn_power_well_enable,
- .disable = vlv_dpio_cmn_power_well_disable,
- .is_enabled = vlv_power_well_enabled,
-};
-
-static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
- .sync_hw = i9xx_power_well_sync_hw_noop,
- .enable = vlv_power_well_enable,
- .disable = vlv_power_well_disable,
- .is_enabled = vlv_power_well_enabled,
-};
-
static const struct i915_power_well_desc vlv_power_wells[] = {
{
.name = "always-on",
@@ -3572,34 +1925,6 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
};
-static const struct i915_power_well_regs icl_aux_power_well_regs = {
- .bios = ICL_PWR_WELL_CTL_AUX1,
- .driver = ICL_PWR_WELL_CTL_AUX2,
- .debug = ICL_PWR_WELL_CTL_AUX4,
-};
-
-static const struct i915_power_well_ops icl_aux_power_well_ops = {
- .regs = &icl_aux_power_well_regs,
- .sync_hw = hsw_power_well_sync_hw,
- .enable = icl_aux_power_well_enable,
- .disable = icl_aux_power_well_disable,
- .is_enabled = hsw_power_well_enabled,
-};
-
-static const struct i915_power_well_regs icl_ddi_power_well_regs = {
- .bios = ICL_PWR_WELL_CTL_DDI1,
- .driver = ICL_PWR_WELL_CTL_DDI2,
- .debug = ICL_PWR_WELL_CTL_DDI4,
-};
-
-static const struct i915_power_well_ops icl_ddi_power_well_ops = {
- .regs = &icl_ddi_power_well_regs,
- .sync_hw = hsw_power_well_sync_hw,
- .enable = hsw_power_well_enable,
- .disable = hsw_power_well_disable,
- .is_enabled = hsw_power_well_enabled,
-};
-
static const struct i915_power_well_desc icl_power_wells[] = {
{
.name = "always-on",
@@ -3813,90 +2138,6 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
};
-static void
-tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
-{
- u8 tries = 0;
- int ret;
-
- while (1) {
- u32 low_val;
- u32 high_val = 0;
-
- if (block)
- low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ;
- else
- low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ;
-
- /*
- * Spec states that we should timeout the request after 200us
- * but the function below will timeout after 500us
- */
- ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, &high_val);
- if (ret == 0) {
- if (block &&
- (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
- ret = -EIO;
- else
- break;
- }
-
- if (++tries == 3)
- break;
-
- msleep(1);
- }
-
- if (ret)
- drm_err(&i915->drm, "TC cold %sblock failed\n",
- block ? "" : "un");
- else
- drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n",
- block ? "" : "un");
-}
-
-static void
-tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915,
- struct i915_power_well *power_well)
-{
- tgl_tc_cold_request(i915, true);
-}
-
-static void
-tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915,
- struct i915_power_well *power_well)
-{
- tgl_tc_cold_request(i915, false);
-}
-
-static void
-tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
- struct i915_power_well *power_well)
-{
- if (intel_power_well_refcount(power_well) > 0)
- tgl_tc_cold_off_power_well_enable(i915, power_well);
- else
- tgl_tc_cold_off_power_well_disable(i915, power_well);
-}
-
-static bool
-tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
- struct i915_power_well *power_well)
-{
- /*
- * Not the correctly implementation but there is no way to just read it
- * from PCODE, so returning count to avoid state mismatch errors
- */
- return intel_power_well_refcount(power_well);
-}
-
-static const struct i915_power_well_ops tgl_tc_cold_off_ops = {
- .sync_hw = tgl_tc_cold_off_power_well_sync_hw,
- .enable = tgl_tc_cold_off_power_well_enable,
- .disable = tgl_tc_cold_off_power_well_disable,
- .is_enabled = tgl_tc_cold_off_power_well_is_enabled,
-};
-
static const struct i915_power_well_desc tgl_power_wells[] = {
{
.name = "always-on",
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index ced384b0a1658..95b9391499109 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -305,9 +305,4 @@ void gen9_dbuf_slices_update(struct drm_i915_private *dev_priv,
for ((wf) = intel_display_power_get_if_enabled((i915), (domain)); (wf); \
intel_display_power_put_async((i915), (domain), (wf)), (wf) = 0)
-void chv_phy_powergate_lanes(struct intel_encoder *encoder,
- bool override, unsigned int mask);
-bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
- enum dpio_channel ch, bool override);
-
#endif /* __INTEL_DISPLAY_POWER_H__ */
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 2a0fb9d9c60f2..a92bb807f1972 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -4,7 +4,58 @@
*/
#include "i915_drv.h"
+#include "i915_irq.h"
+#include "intel_combo_phy.h"
+#include "intel_combo_phy_regs.h"
+#include "intel_crt.h"
+#include "intel_de.h"
#include "intel_display_power_well.h"
+#include "intel_display_types.h"
+#include "intel_dpio_phy.h"
+#include "intel_dpll.h"
+#include "intel_hotplug.h"
+#include "intel_pcode.h"
+#include "intel_pm.h"
+#include "intel_pps.h"
+#include "intel_vga.h"
+#include "intel_tc.h"
+#include "vlv_sideband.h"
+#include "vlv_sideband_reg.h"
+
+struct i915_power_well_regs {
+ i915_reg_t bios;
+ i915_reg_t driver;
+ i915_reg_t kvmr;
+ i915_reg_t debug;
+};
+
+struct i915_power_well_ops {
+ const struct i915_power_well_regs *regs;
+ /*
+ * Synchronize the well's hw state to match the current sw state, for
+ * example enable/disable it based on the current refcount. Called
+ * during driver init and resume time, possibly after first calling
+ * the enable/disable handlers.
+ */
+ void (*sync_hw)(struct drm_i915_private *i915,
+ struct i915_power_well *power_well);
+ /*
+ * Enable the well and resources that depend on it (for example
+ * interrupts located on the well). Called after the 0->1 refcount
+ * transition.
+ */
+ void (*enable)(struct drm_i915_private *i915,
+ struct i915_power_well *power_well);
+ /*
+ * Disable the well and resources that depend on it. Called after
+ * the 1->0 refcount transition.
+ */
+ void (*disable)(struct drm_i915_private *i915,
+ struct i915_power_well *power_well);
+ /* Returns the hw enabled state. */
+ bool (*is_enabled)(struct drm_i915_private *i915,
+ struct i915_power_well *power_well);
+};
struct i915_power_well *
lookup_power_well(struct drm_i915_private *i915,
@@ -111,3 +162,1769 @@ int intel_power_well_refcount(struct i915_power_well *power_well)
{
return power_well->count;
}
+
+/*
+ * Starting with Haswell, we have a "Power Down Well" that can be turned off
+ * when not needed anymore. We have 4 registers that can request the power well
+ * to be enabled, and it will only be disabled if none of the registers is
+ * requesting it to be enabled.
+ */
+static void hsw_power_well_post_enable(struct drm_i915_private *dev_priv,
+ u8 irq_pipe_mask, bool has_vga)
+{
+ if (has_vga)
+ intel_vga_reset_io_mem(dev_priv);
+
+ if (irq_pipe_mask)
+ gen8_irq_power_well_post_enable(dev_priv, irq_pipe_mask);
+}
+
+static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
+ u8 irq_pipe_mask)
+{
+ if (irq_pipe_mask)
+ gen8_irq_power_well_pre_disable(dev_priv, irq_pipe_mask);
+}
+
+#define ICL_AUX_PW_TO_CH(pw_idx) \
+ ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
+
+#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
+ ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
+
+static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well)
+{
+ int pw_idx = power_well->desc->hsw.idx;
+
+ return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
+ ICL_AUX_PW_TO_CH(pw_idx);
+}
+
+static struct intel_digital_port *
+aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
+ enum aux_ch aux_ch)
+{
+ struct intel_digital_port *dig_port = NULL;
+ struct intel_encoder *encoder;
+
+ for_each_intel_encoder(&dev_priv->drm, encoder) {
+ /* We'll check the MST primary port */
+ if (encoder->type == INTEL_OUTPUT_DP_MST)
+ continue;
+
+ dig_port = enc_to_dig_port(encoder);
+ if (!dig_port)
+ continue;
+
+ if (dig_port->aux_ch != aux_ch) {
+ dig_port = NULL;
+ continue;
+ }
+
+ break;
+ }
+
+ return dig_port;
+}
+
+static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915,
+ const struct i915_power_well *power_well)
+{
+ enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
+ struct intel_digital_port *dig_port = aux_ch_to_digital_port(i915, aux_ch);
+
+ return intel_port_to_phy(i915, dig_port->base.port);
+}
+
+static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well,
+ bool timeout_expected)
+{
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
+ int pw_idx = power_well->desc->hsw.idx;
+ int enable_delay = power_well->desc->hsw.fixed_enable_delay;
+
+ /*
+ * For some power wells we're not supposed to watch the status bit for
+ * an ack, but rather just wait a fixed amount of time and then
+ * proceed. This is only used on DG2.
+ */
+ if (IS_DG2(dev_priv) && enable_delay) {
+ usleep_range(enable_delay, 2 * enable_delay);
+ return;
+ }
+
+ /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us. */
+ if (intel_de_wait_for_set(dev_priv, regs->driver,
+ HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {
+ drm_dbg_kms(&dev_priv->drm, "%s power well enable timeout\n",
+ intel_power_well_name(power_well));
+
+ drm_WARN_ON(&dev_priv->drm, !timeout_expected);
+
+ }
+}
+
+static u32 hsw_power_well_requesters(struct drm_i915_private *dev_priv,
+ const struct i915_power_well_regs *regs,
+ int pw_idx)
+{
+ u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
+ u32 ret;
+
+ ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0;
+ ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 : 0;
+ if (regs->kvmr.reg)
+ ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ? 4 : 0;
+ ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0;
+
+ return ret;
+}
+
+static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
+ int pw_idx = power_well->desc->hsw.idx;
+ bool disabled;
+ u32 reqs;
+
+ /*
+ * Bspec doesn't require waiting for PWs to get disabled, but still do
+ * this for paranoia. The known cases where a PW will be forced on:
+ * - a KVMR request on any power well via the KVMR request register
+ * - a DMC request on PW1 and MISC_IO power wells via the BIOS and
+ * DEBUG request registers
+ * Skip the wait in case any of the request bits are set and print a
+ * diagnostic message.
+ */
+ wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) &
+ HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
+ (reqs = hsw_power_well_requesters(dev_priv, regs, pw_idx)), 1);
+ if (disabled)
+ return;
+
+ drm_dbg_kms(&dev_priv->drm,
+ "%s forced on (bios:%d driver:%d kvmr:%d debug:%d)\n",
+ intel_power_well_name(power_well),
+ !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs & 8));
+}
+
+static void gen9_wait_for_power_well_fuses(struct drm_i915_private *dev_priv,
+ enum skl_power_gate pg)
+{
+ /* Timeout 5us for PG#0, for other PGs 1us */
+ drm_WARN_ON(&dev_priv->drm,
+ intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS,
+ SKL_FUSE_PG_DIST_STATUS(pg), 1));
+}
+
+static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
+ int pw_idx = power_well->desc->hsw.idx;
+ u32 val;
+
+ if (power_well->desc->hsw.has_fuses) {
+ enum skl_power_gate pg;
+
+ pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
+ SKL_PW_CTL_IDX_TO_PG(pw_idx);
+
+ /* Wa_16013190616:adlp */
+ if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1)
+ intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0, DISABLE_FLR_SRC);
+
+ /*
+ * For PW1 we have to wait both for the PW0/PG0 fuse state
+ * before enabling the power well and PW1/PG1's own fuse
+ * state after the enabling. For all other power wells with
+ * fuses we only have to wait for that PW/PG's fuse state
+ * after the enabling.
+ */
+ if (pg == SKL_PG1)
+ gen9_wait_for_power_well_fuses(dev_priv, SKL_PG0);
+ }
+
+ val = intel_de_read(dev_priv, regs->driver);
+ intel_de_write(dev_priv, regs->driver,
+ val | HSW_PWR_WELL_CTL_REQ(pw_idx));
+
+ hsw_wait_for_power_well_enable(dev_priv, power_well, false);
+
+ if (power_well->desc->hsw.has_fuses) {
+ enum skl_power_gate pg;
+
+ pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
+ SKL_PW_CTL_IDX_TO_PG(pw_idx);
+ gen9_wait_for_power_well_fuses(dev_priv, pg);
+ }
+
+ hsw_power_well_post_enable(dev_priv,
+ power_well->desc->hsw.irq_pipe_mask,
+ power_well->desc->hsw.has_vga);
+}
+
+static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
+ int pw_idx = power_well->desc->hsw.idx;
+ u32 val;
+
+ hsw_power_well_pre_disable(dev_priv,
+ power_well->desc->hsw.irq_pipe_mask);
+
+ val = intel_de_read(dev_priv, regs->driver);
+ intel_de_write(dev_priv, regs->driver,
+ val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
+ hsw_wait_for_power_well_disable(dev_priv, power_well);
+}
+
+static void
+icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
+ int pw_idx = power_well->desc->hsw.idx;
+ enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
+ u32 val;
+
+ drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
+
+ val = intel_de_read(dev_priv, regs->driver);
+ intel_de_write(dev_priv, regs->driver,
+ val | HSW_PWR_WELL_CTL_REQ(pw_idx));
+
+ if (DISPLAY_VER(dev_priv) < 12) {
+ val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
+ intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
+ val | ICL_LANE_ENABLE_AUX);
+ }
+
+ hsw_wait_for_power_well_enable(dev_priv, power_well, false);
+
+ /* Display WA #1178: icl */
+ if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <= ICL_PW_CTL_IDX_AUX_B &&
+ !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
+ val = intel_de_read(dev_priv, ICL_AUX_ANAOVRD1(pw_idx));
+ val |= ICL_AUX_ANAOVRD1_ENABLE | ICL_AUX_ANAOVRD1_LDO_BYPASS;
+ intel_de_write(dev_priv, ICL_AUX_ANAOVRD1(pw_idx), val);
+ }
+}
+
+static void
+icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
+ int pw_idx = power_well->desc->hsw.idx;
+ enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
+ u32 val;
+
+ drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
+
+ val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
+ intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
+ val & ~ICL_LANE_ENABLE_AUX);
+
+ val = intel_de_read(dev_priv, regs->driver);
+ intel_de_write(dev_priv, regs->driver,
+ val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
+
+ hsw_wait_for_power_well_disable(dev_priv, power_well);
+}
+
+#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
+
+static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well,
+ struct intel_digital_port *dig_port)
+{
+ if (drm_WARN_ON(&dev_priv->drm, !dig_port))
+ return;
+
+ if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
+ return;
+
+ drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
+}
+
+#else
+
+static void icl_tc_port_assert_ref_held(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well,
+ struct intel_digital_port *dig_port)
+{
+}
+
+#endif
+
+#define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) - TGL_PW_CTL_IDX_AUX_TC1)
+
+static void icl_tc_cold_exit(struct drm_i915_private *i915)
+{
+ int ret, tries = 0;
+
+ while (1) {
+ ret = snb_pcode_write_timeout(i915, ICL_PCODE_EXIT_TCCOLD, 0,
+ 250, 1);
+ if (ret != -EAGAIN || ++tries == 3)
+ break;
+ msleep(1);
+ }
+
+ /* Spec states that TC cold exit can take up to 1ms to complete */
+ if (!ret)
+ msleep(1);
+
+ /* TODO: turn failure into a error as soon i915 CI updates ICL IFWI */
+ drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" :
+ "succeeded");
+}
+
+static void
+icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
+ struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
+ bool is_tbt = power_well->desc->hsw.is_tc_tbt;
+ bool timeout_expected;
+ u32 val;
+
+ icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
+
+ val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch));
+ val &= ~DP_AUX_CH_CTL_TBT_IO;
+ if (is_tbt)
+ val |= DP_AUX_CH_CTL_TBT_IO;
+ intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val);
+
+ val = intel_de_read(dev_priv, regs->driver);
+ intel_de_write(dev_priv, regs->driver,
+ val | HSW_PWR_WELL_CTL_REQ(power_well->desc->hsw.idx));
+
+ /*
+ * An AUX timeout is expected if the TBT DP tunnel is down,
+ * or need to enable AUX on a legacy TypeC port as part of the TC-cold
+ * exit sequence.
+ */
+ timeout_expected = is_tbt || intel_tc_cold_requires_aux_pw(dig_port);
+ if (DISPLAY_VER(dev_priv) == 11 && intel_tc_cold_requires_aux_pw(dig_port))
+ icl_tc_cold_exit(dev_priv);
+
+ hsw_wait_for_power_well_enable(dev_priv, power_well, timeout_expected);
+
+ if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) {
+ enum tc_port tc_port;
+
+ tc_port = TGL_AUX_PW_TO_TC_PORT(power_well->desc->hsw.idx);
+ intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
+ HIP_INDEX_VAL(tc_port, 0x2));
+
+ if (intel_de_wait_for_set(dev_priv, DKL_CMN_UC_DW_27(tc_port),
+ DKL_CMN_UC_DW27_UC_HEALTH, 1))
+ drm_warn(&dev_priv->drm,
+ "Timeout waiting TC uC health\n");
+ }
+}
+
+static void
+icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
+ struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
+
+ icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
+
+ hsw_power_well_disable(dev_priv, power_well);
+}
+
+static void
+icl_aux_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
+
+ if (intel_phy_is_tc(dev_priv, phy))
+ return icl_tc_phy_aux_power_well_enable(dev_priv, power_well);
+ else if (IS_ICELAKE(dev_priv))
+ return icl_combo_phy_aux_power_well_enable(dev_priv,
+ power_well);
+ else
+ return hsw_power_well_enable(dev_priv, power_well);
+}
+
+static void
+icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
+
+ if (intel_phy_is_tc(dev_priv, phy))
+ return icl_tc_phy_aux_power_well_disable(dev_priv, power_well);
+ else if (IS_ICELAKE(dev_priv))
+ return icl_combo_phy_aux_power_well_disable(dev_priv,
+ power_well);
+ else
+ return hsw_power_well_disable(dev_priv, power_well);
+}
+
+/*
+ * We should only use the power well if we explicitly asked the hardware to
+ * enable it, so check if it's enabled and also check if we've requested it to
+ * be enabled.
+ */
+static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
+ enum i915_power_well_id id = power_well->desc->id;
+ int pw_idx = power_well->desc->hsw.idx;
+ u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
+ HSW_PWR_WELL_CTL_STATE(pw_idx);
+ u32 val;
+
+ val = intel_de_read(dev_priv, regs->driver);
+
+ /*
+ * On GEN9 big core due to a DMC bug the driver's request bits for PW1
+ * and the MISC_IO PW will be not restored, so check instead for the
+ * BIOS's own request bits, which are forced-on for these power wells
+ * when exiting DC5/6.
+ */
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
+ (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
+ val |= intel_de_read(dev_priv, regs->bios);
+
+ return (val & mask) == mask;
+}
+
+static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
+{
+ drm_WARN_ONCE(&dev_priv->drm,
+ (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC9),
+ "DC9 already programmed to be enabled.\n");
+ drm_WARN_ONCE(&dev_priv->drm,
+ intel_de_read(dev_priv, DC_STATE_EN) &
+ DC_STATE_EN_UPTO_DC5,
+ "DC5 still not disabled to enable DC9.\n");
+ drm_WARN_ONCE(&dev_priv->drm,
+ intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) &
+ HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
+ "Power well 2 on.\n");
+ drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
+ "Interrupts not disabled yet.\n");
+
+ /*
+ * TODO: check for the following to verify the conditions to enter DC9
+ * state are satisfied:
+ * 1] Check relevant display engine registers to verify if mode set
+ * disable sequence was followed.
+ * 2] Check if display uninitialize sequence is initialized.
+ */
+}
+
+static void assert_can_disable_dc9(struct drm_i915_private *dev_priv)
+{
+ drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
+ "Interrupts not disabled yet.\n");
+ drm_WARN_ONCE(&dev_priv->drm,
+ intel_de_read(dev_priv, DC_STATE_EN) &
+ DC_STATE_EN_UPTO_DC5,
+ "DC5 still not disabled.\n");
+
+ /*
+ * TODO: check for the following to verify DC9 state was indeed
+ * entered before programming to disable it:
+ * 1] Check relevant display engine registers to verify if mode
+ * set disable sequence was followed.
+ * 2] Check if display uninitialize sequence is initialized.
+ */
+}
+
+static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
+ u32 state)
+{
+ int rewrites = 0;
+ int rereads = 0;
+ u32 v;
+
+ intel_de_write(dev_priv, DC_STATE_EN, state);
+
+ /* It has been observed that disabling the dc6 state sometimes
+ * doesn't stick and dmc keeps returning old value. Make sure
+ * the write really sticks enough times and also force rewrite until
+ * we are confident that state is exactly what we want.
+ */
+ do {
+ v = intel_de_read(dev_priv, DC_STATE_EN);
+
+ if (v != state) {
+ intel_de_write(dev_priv, DC_STATE_EN, state);
+ rewrites++;
+ rereads = 0;
+ } else if (rereads++ > 5) {
+ break;
+ }
+
+ } while (rewrites < 100);
+
+ if (v != state)
+ drm_err(&dev_priv->drm,
+ "Writing dc state to 0x%x failed, now 0x%x\n",
+ state, v);
+
+ /* Most of the times we need one retry, avoid spam */
+ if (rewrites > 1)
+ drm_dbg_kms(&dev_priv->drm,
+ "Rewrote dc state to 0x%x %d times\n",
+ state, rewrites);
+}
+
+static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
+{
+ u32 mask;
+
+ mask = DC_STATE_EN_UPTO_DC5;
+
+ if (DISPLAY_VER(dev_priv) >= 12)
+ mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
+ | DC_STATE_EN_DC9;
+ else if (DISPLAY_VER(dev_priv) == 11)
+ mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
+ else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
+ mask |= DC_STATE_EN_DC9;
+ else
+ mask |= DC_STATE_EN_UPTO_DC6;
+
+ return mask;
+}
+
+void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ if (!HAS_DISPLAY(dev_priv))
+ return;
+
+ val = intel_de_read(dev_priv, DC_STATE_EN) & gen9_dc_mask(dev_priv);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "Resetting DC state tracking from %02x to %02x\n",
+ dev_priv->dmc.dc_state, val);
+ dev_priv->dmc.dc_state = val;
+}
+
+/**
+ * gen9_set_dc_state - set target display C power state
+ * @dev_priv: i915 device instance
+ * @state: target DC power state
+ * - DC_STATE_DISABLE
+ * - DC_STATE_EN_UPTO_DC5
+ * - DC_STATE_EN_UPTO_DC6
+ * - DC_STATE_EN_DC9
+ *
+ * Signal to DMC firmware/HW the target DC power state passed in @state.
+ * DMC/HW can turn off individual display clocks and power rails when entering
+ * a deeper DC power state (higher in number) and turns these back when exiting
+ * that state to a shallower power state (lower in number). The HW will decide
+ * when to actually enter a given state on an on-demand basis, for instance
+ * depending on the active state of display pipes. The state of display
+ * registers backed by affected power rails are saved/restored as needed.
+ *
+ * Based on the above enabling a deeper DC power state is asynchronous wrt.
+ * enabling it. Disabling a deeper power state is synchronous: for instance
+ * setting %DC_STATE_DISABLE won't complete until all HW resources are turned
+ * back on and register state is restored. This is guaranteed by the MMIO write
+ * to DC_STATE_EN blocking until the state is restored.
+ */
+void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
+{
+ u32 val;
+ u32 mask;
+
+ if (!HAS_DISPLAY(dev_priv))
+ return;
+
+ if (drm_WARN_ON_ONCE(&dev_priv->drm,
+ state & ~dev_priv->dmc.allowed_dc_mask))
+ state &= dev_priv->dmc.allowed_dc_mask;
+
+ val = intel_de_read(dev_priv, DC_STATE_EN);
+ mask = gen9_dc_mask(dev_priv);
+ drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to %02x\n",
+ val & mask, state);
+
+ /* Check if DMC is ignoring our DC state requests */
+ if ((val & mask) != dev_priv->dmc.dc_state)
+ drm_err(&dev_priv->drm, "DC state mismatch (0x%x -> 0x%x)\n",
+ dev_priv->dmc.dc_state, val & mask);
+
+ val &= ~mask;
+ val |= state;
+
+ gen9_write_dc_state(dev_priv, val);
+
+ dev_priv->dmc.dc_state = val & mask;
+}
+
+static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
+{
+ drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n");
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
+}
+
+static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n");
+ val = intel_de_read(dev_priv, DC_STATE_EN);
+ val &= ~DC_STATE_DC3CO_STATUS;
+ intel_de_write(dev_priv, DC_STATE_EN, val);
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+ /*
+ * Delay of 200us DC3CO Exit time B.Spec 49196
+ */
+ usleep_range(200, 210);
+}
+
+static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
+{
+ drm_WARN_ONCE(&dev_priv->drm,
+ !intel_de_read(dev_priv,
+ DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
+ "DMC program storage start is NULL\n");
+ drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_SSP_BASE),
+ "DMC SSP Base Not fine\n");
+ drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv, DMC_HTP_SKL),
+ "DMC HTP Not fine\n");
+}
+
+static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
+{
+ enum i915_power_well_id high_pg;
+
+ /* Power wells at this level and above must be disabled for DC5 entry */
+ if (DISPLAY_VER(dev_priv) == 12)
+ high_pg = ICL_DISP_PW_3;
+ else
+ high_pg = SKL_DISP_PW_2;
+
+ drm_WARN_ONCE(&dev_priv->drm,
+ intel_display_power_well_is_enabled(dev_priv, high_pg),
+ "Power wells above platform's DC5 limit still enabled.\n");
+
+ drm_WARN_ONCE(&dev_priv->drm,
+ (intel_de_read(dev_priv, DC_STATE_EN) &
+ DC_STATE_EN_UPTO_DC5),
+ "DC5 already programmed to be enabled.\n");
+ assert_rpm_wakelock_held(&dev_priv->runtime_pm);
+
+ assert_dmc_loaded(dev_priv);
+}
+
+void gen9_enable_dc5(struct drm_i915_private *dev_priv)
+{
+ assert_can_enable_dc5(dev_priv);
+
+ drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n");
+
+ /* Wa Display #1183: skl,kbl,cfl */
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
+ intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
+ intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
+
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
+}
+
+static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
+{
+ drm_WARN_ONCE(&dev_priv->drm,
+ intel_de_read(dev_priv, UTIL_PIN_CTL) & UTIL_PIN_ENABLE,
+ "Backlight is not disabled.\n");
+ drm_WARN_ONCE(&dev_priv->drm,
+ (intel_de_read(dev_priv, DC_STATE_EN) &
+ DC_STATE_EN_UPTO_DC6),
+ "DC6 already programmed to be enabled.\n");
+
+ assert_dmc_loaded(dev_priv);
+}
+
+void skl_enable_dc6(struct drm_i915_private *dev_priv)
+{
+ assert_can_enable_dc6(dev_priv);
+
+ drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n");
+
+ /* Wa Display #1183: skl,kbl,cfl */
+ if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
+ intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
+ intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
+
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
+}
+
+void bxt_enable_dc9(struct drm_i915_private *dev_priv)
+{
+ assert_can_enable_dc9(dev_priv);
+
+ drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n");
+ /*
+ * Power sequencer reset is not needed on
+ * platforms with South Display Engine on PCH,
+ * because PPS registers are always on.
+ */
+ if (!HAS_PCH_SPLIT(dev_priv))
+ intel_pps_reset_all(dev_priv);
+ gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
+}
+
+void bxt_disable_dc9(struct drm_i915_private *dev_priv)
+{
+ assert_can_disable_dc9(dev_priv);
+
+ drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n");
+
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+ intel_pps_unlock_regs_wa(dev_priv);
+}
+
+static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
+ int pw_idx = power_well->desc->hsw.idx;
+ u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
+ u32 bios_req = intel_de_read(dev_priv, regs->bios);
+
+ /* Take over the request bit if set by BIOS. */
+ if (bios_req & mask) {
+ u32 drv_req = intel_de_read(dev_priv, regs->driver);
+
+ if (!(drv_req & mask))
+ intel_de_write(dev_priv, regs->driver, drv_req | mask);
+ intel_de_write(dev_priv, regs->bios, bios_req & ~mask);
+ }
+}
+
+static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy);
+}
+
+static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy);
+}
+
+static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc->bxt.phy);
+}
+
+static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
+{
+ struct i915_power_well *power_well;
+
+ power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
+ if (intel_power_well_refcount(power_well) > 0)
+ bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
+
+ power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
+ if (intel_power_well_refcount(power_well) > 0)
+ bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
+
+ if (IS_GEMINILAKE(dev_priv)) {
+ power_well = lookup_power_well(dev_priv,
+ GLK_DISP_PW_DPIO_CMN_C);
+ if (intel_power_well_refcount(power_well) > 0)
+ bxt_ddi_phy_verify_state(dev_priv,
+ power_well->desc->bxt.phy);
+ }
+}
+
+static bool gen9_dc_off_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ return ((intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_DC3CO) == 0 &&
+ (intel_de_read(dev_priv, DC_STATE_EN) & DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
+}
+
+static void gen9_assert_dbuf_enabled(struct drm_i915_private *dev_priv)
+{
+ u8 hw_enabled_dbuf_slices = intel_enabled_dbuf_slices_mask(dev_priv);
+ u8 enabled_dbuf_slices = dev_priv->dbuf.enabled_slices;
+
+ drm_WARN(&dev_priv->drm,
+ hw_enabled_dbuf_slices != enabled_dbuf_slices,
+ "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n",
+ hw_enabled_dbuf_slices,
+ enabled_dbuf_slices);
+}
+
+void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
+{
+ struct intel_cdclk_config cdclk_config = {};
+
+ if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) {
+ tgl_disable_dc3co(dev_priv);
+ return;
+ }
+
+ gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
+
+ if (!HAS_DISPLAY(dev_priv))
+ return;
+
+ intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
+ /* Can't read out voltage_level so can't use intel_cdclk_changed() */
+ drm_WARN_ON(&dev_priv->drm,
+ intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
+ &cdclk_config));
+
+ gen9_assert_dbuf_enabled(dev_priv);
+
+ if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
+ bxt_verify_ddi_phy_power_wells(dev_priv);
+
+ if (DISPLAY_VER(dev_priv) >= 11)
+ /*
+ * DMC retains HW context only for port A, the other combo
+ * PHY's HW context for port B is lost after DC transitions,
+ * so we need to restore it manually.
+ */
+ intel_combo_phy_init(dev_priv);
+}
+
+static void gen9_dc_off_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ gen9_disable_dc_states(dev_priv);
+}
+
+static void gen9_dc_off_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ if (!intel_dmc_has_payload(dev_priv))
+ return;
+
+ switch (dev_priv->dmc.target_dc_state) {
+ case DC_STATE_EN_DC3CO:
+ tgl_enable_dc3co(dev_priv);
+ break;
+ case DC_STATE_EN_UPTO_DC6:
+ skl_enable_dc6(dev_priv);
+ break;
+ case DC_STATE_EN_UPTO_DC5:
+ gen9_enable_dc5(dev_priv);
+ break;
+ }
+}
+
+static void i9xx_power_well_sync_hw_noop(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+}
+
+static void i9xx_always_on_power_well_noop(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+}
+
+static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ return true;
+}
+
+static void i830_pipes_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE) == 0)
+ i830_enable_pipe(dev_priv, PIPE_A);
+ if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE) == 0)
+ i830_enable_pipe(dev_priv, PIPE_B);
+}
+
+static void i830_pipes_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ i830_disable_pipe(dev_priv, PIPE_B);
+ i830_disable_pipe(dev_priv, PIPE_A);
+}
+
+static bool i830_pipes_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ return intel_de_read(dev_priv, PIPECONF(PIPE_A)) & PIPECONF_ENABLE &&
+ intel_de_read(dev_priv, PIPECONF(PIPE_B)) & PIPECONF_ENABLE;
+}
+
+static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ if (intel_power_well_refcount(power_well) > 0)
+ i830_pipes_power_well_enable(dev_priv, power_well);
+ else
+ i830_pipes_power_well_disable(dev_priv, power_well);
+}
+
+static void vlv_set_power_well(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well, bool enable)
+{
+ int pw_idx = power_well->desc->vlv.idx;
+ u32 mask;
+ u32 state;
+ u32 ctrl;
+
+ mask = PUNIT_PWRGT_MASK(pw_idx);
+ state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
+ PUNIT_PWRGT_PWR_GATE(pw_idx);
+
+ vlv_punit_get(dev_priv);
+
+#define COND \
+ ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) == state)
+
+ if (COND)
+ goto out;
+
+ ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
+ ctrl &= ~mask;
+ ctrl |= state;
+ vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
+
+ if (wait_for(COND, 100))
+ drm_err(&dev_priv->drm,
+ "timeout setting power well state %08x (%08x)\n",
+ state,
+ vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL));
+
+#undef COND
+
+out:
+ vlv_punit_put(dev_priv);
+}
+
+static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ vlv_set_power_well(dev_priv, power_well, true);
+}
+
+static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ vlv_set_power_well(dev_priv, power_well, false);
+}
+
+static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ int pw_idx = power_well->desc->vlv.idx;
+ bool enabled = false;
+ u32 mask;
+ u32 state;
+ u32 ctrl;
+
+ mask = PUNIT_PWRGT_MASK(pw_idx);
+ ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
+
+ vlv_punit_get(dev_priv);
+
+ state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask;
+ /*
+ * We only ever set the power-on and power-gate states, anything
+ * else is unexpected.
+ */
+ drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx) &&
+ state != PUNIT_PWRGT_PWR_GATE(pw_idx));
+ if (state == ctrl)
+ enabled = true;
+
+ /*
+ * A transient state at this point would mean some unexpected party
+ * is poking at the power controls too.
+ */
+ ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
+ drm_WARN_ON(&dev_priv->drm, ctrl != state);
+
+ vlv_punit_put(dev_priv);
+
+ return enabled;
+}
+
+static void vlv_init_display_clock_gating(struct drm_i915_private *dev_priv)
+{
+ u32 val;
+
+ /*
+ * On driver load, a pipe may be active and driving a DSI display.
+ * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe getting stuck
+ * (and never recovering) in this case. intel_dsi_post_disable() will
+ * clear it when we turn off the display.
+ */
+ val = intel_de_read(dev_priv, DSPCLK_GATE_D);
+ val &= DPOUNIT_CLOCK_GATE_DISABLE;
+ val |= VRHUNIT_CLOCK_GATE_DISABLE;
+ intel_de_write(dev_priv, DSPCLK_GATE_D, val);
+
+ /*
+ * Disable trickle feed and enable pnd deadline calculation
+ */
+ intel_de_write(dev_priv, MI_ARB_VLV,
+ MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
+ intel_de_write(dev_priv, CBR1_VLV, 0);
+
+ drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq == 0);
+ intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
+ DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)->rawclk_freq,
+ 1000));
+}
+
+static void vlv_display_power_well_init(struct drm_i915_private *dev_priv)
+{
+ struct intel_encoder *encoder;
+ enum pipe pipe;
+
+ /*
+ * Enable the CRI clock source so we can get at the
+ * display and the reference clock for VGA
+ * hotplug / manual detection. Supposedly DSI also
+ * needs the ref clock up and running.
+ *
+ * CHV DPLL B/C have some issues if VGA mode is enabled.
+ */
+ for_each_pipe(dev_priv, pipe) {
+ u32 val = intel_de_read(dev_priv, DPLL(pipe));
+
+ val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
+ if (pipe != PIPE_A)
+ val |= DPLL_INTEGRATED_CRI_CLK_VLV;
+
+ intel_de_write(dev_priv, DPLL(pipe), val);
+ }
+
+ vlv_init_display_clock_gating(dev_priv);
+
+ spin_lock_irq(&dev_priv->irq_lock);
+ valleyview_enable_display_irqs(dev_priv);
+ spin_unlock_irq(&dev_priv->irq_lock);
+
+ /*
+ * During driver initialization/resume we can avoid restoring the
+ * part of the HW/SW state that will be inited anyway explicitly.
+ */
+ if (dev_priv->power_domains.initializing)
+ return;
+
+ intel_hpd_init(dev_priv);
+ intel_hpd_poll_disable(dev_priv);
+
+ /* Re-enable the ADPA, if we have one */
+ for_each_intel_encoder(&dev_priv->drm, encoder) {
+ if (encoder->type == INTEL_OUTPUT_ANALOG)
+ intel_crt_reset(&encoder->base);
+ }
+
+ intel_vga_redisable_power_on(dev_priv);
+
+ intel_pps_unlock_regs_wa(dev_priv);
+}
+
+static void vlv_display_power_well_deinit(struct drm_i915_private *dev_priv)
+{
+ spin_lock_irq(&dev_priv->irq_lock);
+ valleyview_disable_display_irqs(dev_priv);
+ spin_unlock_irq(&dev_priv->irq_lock);
+
+ /* make sure we're done processing display irqs */
+ intel_synchronize_irq(dev_priv);
+
+ intel_pps_reset_all(dev_priv);
+
+ /* Prevent us from re-enabling polling on accident in late suspend */
+ if (!dev_priv->drm.dev->power.is_suspended)
+ intel_hpd_poll_enable(dev_priv);
+}
+
+static void vlv_display_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ vlv_set_power_well(dev_priv, power_well, true);
+
+ vlv_display_power_well_init(dev_priv);
+}
+
+static void vlv_display_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ vlv_display_power_well_deinit(dev_priv);
+
+ vlv_set_power_well(dev_priv, power_well, false);
+}
+
+static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ /* since ref/cri clock was enabled */
+ udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
+
+ vlv_set_power_well(dev_priv, power_well, true);
+
+ /*
+ * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
+ * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
+ * a. GUnit 0x2110 bit[0] set to 1 (def 0)
+ * b. The other bits such as sfr settings / modesel may all
+ * be set to 0.
+ *
+ * This should only be done on init and resume from S3 with
+ * both PLLs disabled, or we risk losing DPIO and PLL
+ * synchronization.
+ */
+ intel_de_write(dev_priv, DPIO_CTL,
+ intel_de_read(dev_priv, DPIO_CTL) | DPIO_CMNRST);
+}
+
+static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum pipe pipe;
+
+ for_each_pipe(dev_priv, pipe)
+ assert_pll_disabled(dev_priv, pipe);
+
+ /* Assert common reset */
+ intel_de_write(dev_priv, DPIO_CTL,
+ intel_de_read(dev_priv, DPIO_CTL) & ~DPIO_CMNRST);
+
+ vlv_set_power_well(dev_priv, power_well, false);
+}
+
+#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
+
+#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
+
+static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
+{
+ struct i915_power_well *cmn_bc =
+ lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
+ struct i915_power_well *cmn_d =
+ lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
+ u32 phy_control = dev_priv->chv_phy_control;
+ u32 phy_status = 0;
+ u32 phy_status_mask = 0xffffffff;
+
+ /*
+ * The BIOS can leave the PHY is some weird state
+ * where it doesn't fully power down some parts.
+ * Disable the asserts until the PHY has been fully
+ * reset (ie. the power well has been disabled at
+ * least once).
+ */
+ if (!dev_priv->chv_phy_assert[DPIO_PHY0])
+ phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0) |
+ PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0) |
+ PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1) |
+ PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1) |
+ PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0) |
+ PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1));
+
+ if (!dev_priv->chv_phy_assert[DPIO_PHY1])
+ phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0) |
+ PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0) |
+ PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1));
+
+ if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
+ phy_status |= PHY_POWERGOOD(DPIO_PHY0);
+
+ /* this assumes override is only used to enable lanes */
+ if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH0)) == 0)
+ phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0);
+
+ if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0, DPIO_CH1)) == 0)
+ phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1);
+
+ /* CL1 is on whenever anything is on in either channel */
+ if (BITS_SET(phy_control,
+ PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH0) |
+ PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)))
+ phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH0);
+
+ /*
+ * The DPLLB check accounts for the pipe B + port A usage
+ * with CL2 powered up but all the lanes in the second channel
+ * powered down.
+ */
+ if (BITS_SET(phy_control,
+ PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0, DPIO_CH1)) &&
+ (intel_de_read(dev_priv, DPLL(PIPE_B)) & DPLL_VCO_ENABLE) == 0)
+ phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0, DPIO_CH1);
+
+ if (BITS_SET(phy_control,
+ PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH0)))
+ phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 0);
+ if (BITS_SET(phy_control,
+ PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH0)))
+ phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH0, 1);
+
+ if (BITS_SET(phy_control,
+ PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0, DPIO_CH1)))
+ phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 0);
+ if (BITS_SET(phy_control,
+ PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0, DPIO_CH1)))
+ phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0, DPIO_CH1, 1);
+ }
+
+ if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
+ phy_status |= PHY_POWERGOOD(DPIO_PHY1);
+
+ /* this assumes override is only used to enable lanes */
+ if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1, DPIO_CH0)) == 0)
+ phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0);
+
+ if (BITS_SET(phy_control,
+ PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1, DPIO_CH0)))
+ phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1, DPIO_CH0);
+
+ if (BITS_SET(phy_control,
+ PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1, DPIO_CH0)))
+ phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 0);
+ if (BITS_SET(phy_control,
+ PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1, DPIO_CH0)))
+ phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1, DPIO_CH0, 1);
+ }
+
+ phy_status &= phy_status_mask;
+
+ /*
+ * The PHY may be busy with some initial calibration and whatnot,
+ * so the power state can take a while to actually change.
+ */
+ if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS,
+ phy_status_mask, phy_status, 10))
+ drm_err(&dev_priv->drm,
+ "Unexpected PHY_STATUS 0x%08x, expected 0x%08x (PHY_CONTROL=0x%08x)\n",
+ intel_de_read(dev_priv, DISPLAY_PHY_STATUS) & phy_status_mask,
+ phy_status, dev_priv->chv_phy_control);
+}
+
+#undef BITS_SET
+
+static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum dpio_phy phy;
+ enum pipe pipe;
+ u32 tmp;
+
+ drm_WARN_ON_ONCE(&dev_priv->drm,
+ power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
+ power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
+
+ if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
+ pipe = PIPE_A;
+ phy = DPIO_PHY0;
+ } else {
+ pipe = PIPE_C;
+ phy = DPIO_PHY1;
+ }
+
+ /* since ref/cri clock was enabled */
+ udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
+ vlv_set_power_well(dev_priv, power_well, true);
+
+ /* Poll for phypwrgood signal */
+ if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
+ PHY_POWERGOOD(phy), 1))
+ drm_err(&dev_priv->drm, "Display PHY %d is not power up\n",
+ phy);
+
+ vlv_dpio_get(dev_priv);
+
+ /* Enable dynamic power down */
+ tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
+ tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
+ DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
+ vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
+
+ if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
+ tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
+ tmp |= DPIO_DYNPWRDOWNEN_CH1;
+ vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
+ } else {
+ /*
+ * Force the non-existing CL2 off. BXT does this
+ * too, so maybe it saves some power even though
+ * CL2 doesn't exist?
+ */
+ tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
+ tmp |= DPIO_CL2_LDOFUSE_PWRENB;
+ vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
+ }
+
+ vlv_dpio_put(dev_priv);
+
+ dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
+ intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
+ dev_priv->chv_phy_control);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
+ phy, dev_priv->chv_phy_control);
+
+ assert_chv_phy_status(dev_priv);
+}
+
+static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum dpio_phy phy;
+
+ drm_WARN_ON_ONCE(&dev_priv->drm,
+ power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
+ power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
+
+ if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
+ phy = DPIO_PHY0;
+ assert_pll_disabled(dev_priv, PIPE_A);
+ assert_pll_disabled(dev_priv, PIPE_B);
+ } else {
+ phy = DPIO_PHY1;
+ assert_pll_disabled(dev_priv, PIPE_C);
+ }
+
+ dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
+ intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
+ dev_priv->chv_phy_control);
+
+ vlv_set_power_well(dev_priv, power_well, false);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
+ phy, dev_priv->chv_phy_control);
+
+ /* PHY is fully reset now, so we can enable the PHY state asserts */
+ dev_priv->chv_phy_assert[phy] = true;
+
+ assert_chv_phy_status(dev_priv);
+}
+
+static void assert_chv_phy_powergate(struct drm_i915_private *dev_priv, enum dpio_phy phy,
+ enum dpio_channel ch, bool override, unsigned int mask)
+{
+ enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
+ u32 reg, val, expected, actual;
+
+ /*
+ * The BIOS can leave the PHY is some weird state
+ * where it doesn't fully power down some parts.
+ * Disable the asserts until the PHY has been fully
+ * reset (ie. the power well has been disabled at
+ * least once).
+ */
+ if (!dev_priv->chv_phy_assert[phy])
+ return;
+
+ if (ch == DPIO_CH0)
+ reg = _CHV_CMN_DW0_CH0;
+ else
+ reg = _CHV_CMN_DW6_CH1;
+
+ vlv_dpio_get(dev_priv);
+ val = vlv_dpio_read(dev_priv, pipe, reg);
+ vlv_dpio_put(dev_priv);
+
+ /*
+ * This assumes !override is only used when the port is disabled.
+ * All lanes should power down even without the override when
+ * the port is disabled.
+ */
+ if (!override || mask == 0xf) {
+ expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
+ /*
+ * If CH1 common lane is not active anymore
+ * (eg. for pipe B DPLL) the entire channel will
+ * shut down, which causes the common lane registers
+ * to read as 0. That means we can't actually check
+ * the lane power down status bits, but as the entire
+ * register reads as 0 it's a good indication that the
+ * channel is indeed entirely powered down.
+ */
+ if (ch == DPIO_CH1 && val == 0)
+ expected = 0;
+ } else if (mask != 0x0) {
+ expected = DPIO_ANYDL_POWERDOWN;
+ } else {
+ expected = 0;
+ }
+
+ if (ch == DPIO_CH0)
+ actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
+ else
+ actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
+ actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
+
+ drm_WARN(&dev_priv->drm, actual != expected,
+ "Unexpected DPIO lane power down: all %d, any %d. Expected: all %d, any %d. (0x%x = 0x%08x)\n",
+ !!(actual & DPIO_ALLDL_POWERDOWN),
+ !!(actual & DPIO_ANYDL_POWERDOWN),
+ !!(expected & DPIO_ALLDL_POWERDOWN),
+ !!(expected & DPIO_ANYDL_POWERDOWN),
+ reg, val);
+}
+
+bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
+ enum dpio_channel ch, bool override)
+{
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ bool was_override;
+
+ mutex_lock(&power_domains->lock);
+
+ was_override = dev_priv->chv_phy_control & PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+
+ if (override == was_override)
+ goto out;
+
+ if (override)
+ dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ else
+ dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+
+ intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
+ dev_priv->chv_phy_control);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "Power gating DPIO PHY%d CH%d (DPIO_PHY_CONTROL=0x%08x)\n",
+ phy, ch, dev_priv->chv_phy_control);
+
+ assert_chv_phy_status(dev_priv);
+
+out:
+ mutex_unlock(&power_domains->lock);
+
+ return was_override;
+}
+
+void chv_phy_powergate_lanes(struct intel_encoder *encoder,
+ bool override, unsigned int mask)
+{
+ struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
+ struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ enum dpio_phy phy = vlv_dig_port_to_phy(enc_to_dig_port(encoder));
+ enum dpio_channel ch = vlv_dig_port_to_channel(enc_to_dig_port(encoder));
+
+ mutex_lock(&power_domains->lock);
+
+ dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy, ch);
+ dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy, ch);
+
+ if (override)
+ dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+ else
+ dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
+
+ intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
+ dev_priv->chv_phy_control);
+
+ drm_dbg_kms(&dev_priv->drm,
+ "Power gating DPIO PHY%d CH%d lanes 0x%x (PHY_CONTROL=0x%08x)\n",
+ phy, ch, mask, dev_priv->chv_phy_control);
+
+ assert_chv_phy_status(dev_priv);
+
+ assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
+
+ mutex_unlock(&power_domains->lock);
+}
+
+static bool chv_pipe_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ enum pipe pipe = PIPE_A;
+ bool enabled;
+ u32 state, ctrl;
+
+ vlv_punit_get(dev_priv);
+
+ state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe);
+ /*
+ * We only ever set the power-on and power-gate states, anything
+ * else is unexpected.
+ */
+ drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) &&
+ state != DP_SSS_PWR_GATE(pipe));
+ enabled = state == DP_SSS_PWR_ON(pipe);
+
+ /*
+ * A transient state at this point would mean some unexpected party
+ * is poking at the power controls too.
+ */
+ ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSC_MASK(pipe);
+ drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state);
+
+ vlv_punit_put(dev_priv);
+
+ return enabled;
+}
+
+static void chv_set_pipe_power_well(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well,
+ bool enable)
+{
+ enum pipe pipe = PIPE_A;
+ u32 state;
+ u32 ctrl;
+
+ state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
+
+ vlv_punit_get(dev_priv);
+
+#define COND \
+ ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) & DP_SSS_MASK(pipe)) == state)
+
+ if (COND)
+ goto out;
+
+ ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
+ ctrl &= ~DP_SSC_MASK(pipe);
+ ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
+ vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl);
+
+ if (wait_for(COND, 100))
+ drm_err(&dev_priv->drm,
+ "timeout setting power well state %08x (%08x)\n",
+ state,
+ vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM));
+
+#undef COND
+
+out:
+ vlv_punit_put(dev_priv);
+}
+
+static void chv_pipe_power_well_sync_hw(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
+ dev_priv->chv_phy_control);
+}
+
+static void chv_pipe_power_well_enable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ chv_set_pipe_power_well(dev_priv, power_well, true);
+
+ vlv_display_power_well_init(dev_priv);
+}
+
+static void chv_pipe_power_well_disable(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ vlv_display_power_well_deinit(dev_priv);
+
+ chv_set_pipe_power_well(dev_priv, power_well, false);
+}
+
+static void
+tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
+{
+ u8 tries = 0;
+ int ret;
+
+ while (1) {
+ u32 low_val;
+ u32 high_val = 0;
+
+ if (block)
+ low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ;
+ else
+ low_val = TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ;
+
+ /*
+ * Spec states that we should timeout the request after 200us
+ * but the function below will timeout after 500us
+ */
+ ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val, &high_val);
+ if (ret == 0) {
+ if (block &&
+ (low_val & TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
+ ret = -EIO;
+ else
+ break;
+ }
+
+ if (++tries == 3)
+ break;
+
+ msleep(1);
+ }
+
+ if (ret)
+ drm_err(&i915->drm, "TC cold %sblock failed\n",
+ block ? "" : "un");
+ else
+ drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n",
+ block ? "" : "un");
+}
+
+static void
+tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915,
+ struct i915_power_well *power_well)
+{
+ tgl_tc_cold_request(i915, true);
+}
+
+static void
+tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915,
+ struct i915_power_well *power_well)
+{
+ tgl_tc_cold_request(i915, false);
+}
+
+static void
+tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
+ struct i915_power_well *power_well)
+{
+ if (intel_power_well_refcount(power_well) > 0)
+ tgl_tc_cold_off_power_well_enable(i915, power_well);
+ else
+ tgl_tc_cold_off_power_well_disable(i915, power_well);
+}
+
+static bool
+tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
+{
+ /*
+ * Not the correctly implementation but there is no way to just read it
+ * from PCODE, so returning count to avoid state mismatch errors
+ */
+ return intel_power_well_refcount(power_well);
+}
+
+
+const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = i9xx_always_on_power_well_noop,
+ .disable = i9xx_always_on_power_well_noop,
+ .is_enabled = i9xx_always_on_power_well_enabled,
+};
+
+const struct i915_power_well_ops chv_pipe_power_well_ops = {
+ .sync_hw = chv_pipe_power_well_sync_hw,
+ .enable = chv_pipe_power_well_enable,
+ .disable = chv_pipe_power_well_disable,
+ .is_enabled = chv_pipe_power_well_enabled,
+};
+
+const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = chv_dpio_cmn_power_well_enable,
+ .disable = chv_dpio_cmn_power_well_disable,
+ .is_enabled = vlv_power_well_enabled,
+};
+
+const struct i915_power_well_ops i830_pipes_power_well_ops = {
+ .sync_hw = i830_pipes_power_well_sync_hw,
+ .enable = i830_pipes_power_well_enable,
+ .disable = i830_pipes_power_well_disable,
+ .is_enabled = i830_pipes_power_well_enabled,
+};
+
+static const struct i915_power_well_regs hsw_power_well_regs = {
+ .bios = HSW_PWR_WELL_CTL1,
+ .driver = HSW_PWR_WELL_CTL2,
+ .kvmr = HSW_PWR_WELL_CTL3,
+ .debug = HSW_PWR_WELL_CTL4,
+};
+
+const struct i915_power_well_ops hsw_power_well_ops = {
+ .regs = &hsw_power_well_regs,
+ .sync_hw = hsw_power_well_sync_hw,
+ .enable = hsw_power_well_enable,
+ .disable = hsw_power_well_disable,
+ .is_enabled = hsw_power_well_enabled,
+};
+
+const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = gen9_dc_off_power_well_enable,
+ .disable = gen9_dc_off_power_well_disable,
+ .is_enabled = gen9_dc_off_power_well_enabled,
+};
+
+const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = bxt_dpio_cmn_power_well_enable,
+ .disable = bxt_dpio_cmn_power_well_disable,
+ .is_enabled = bxt_dpio_cmn_power_well_enabled,
+};
+
+const struct i915_power_well_ops vlv_display_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = vlv_display_power_well_enable,
+ .disable = vlv_display_power_well_disable,
+ .is_enabled = vlv_power_well_enabled,
+};
+
+const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = vlv_dpio_cmn_power_well_enable,
+ .disable = vlv_dpio_cmn_power_well_disable,
+ .is_enabled = vlv_power_well_enabled,
+};
+
+const struct i915_power_well_ops vlv_dpio_power_well_ops = {
+ .sync_hw = i9xx_power_well_sync_hw_noop,
+ .enable = vlv_power_well_enable,
+ .disable = vlv_power_well_disable,
+ .is_enabled = vlv_power_well_enabled,
+};
+
+static const struct i915_power_well_regs icl_aux_power_well_regs = {
+ .bios = ICL_PWR_WELL_CTL_AUX1,
+ .driver = ICL_PWR_WELL_CTL_AUX2,
+ .debug = ICL_PWR_WELL_CTL_AUX4,
+};
+
+const struct i915_power_well_ops icl_aux_power_well_ops = {
+ .regs = &icl_aux_power_well_regs,
+ .sync_hw = hsw_power_well_sync_hw,
+ .enable = icl_aux_power_well_enable,
+ .disable = icl_aux_power_well_disable,
+ .is_enabled = hsw_power_well_enabled,
+};
+
+static const struct i915_power_well_regs icl_ddi_power_well_regs = {
+ .bios = ICL_PWR_WELL_CTL_DDI1,
+ .driver = ICL_PWR_WELL_CTL_DDI2,
+ .debug = ICL_PWR_WELL_CTL_DDI4,
+};
+
+const struct i915_power_well_ops icl_ddi_power_well_ops = {
+ .regs = &icl_ddi_power_well_regs,
+ .sync_hw = hsw_power_well_sync_hw,
+ .enable = hsw_power_well_enable,
+ .disable = hsw_power_well_disable,
+ .is_enabled = hsw_power_well_enabled,
+};
+
+const struct i915_power_well_ops tgl_tc_cold_off_ops = {
+ .sync_hw = tgl_tc_cold_off_power_well_sync_hw,
+ .enable = tgl_tc_cold_off_power_well_enable,
+ .disable = tgl_tc_cold_off_power_well_disable,
+ .is_enabled = tgl_tc_cold_off_power_well_is_enabled,
+};
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index 9a3756fdcf7fc..de3ee1bfb06d9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -36,41 +36,6 @@ enum i915_power_well_id {
TGL_DISP_PW_TC_COLD_OFF,
};
-struct i915_power_well_regs {
- i915_reg_t bios;
- i915_reg_t driver;
- i915_reg_t kvmr;
- i915_reg_t debug;
-};
-
-struct i915_power_well_ops {
- const struct i915_power_well_regs *regs;
- /*
- * Synchronize the well's hw state to match the current sw state, for
- * example enable/disable it based on the current refcount. Called
- * during driver init and resume time, possibly after first calling
- * the enable/disable handlers.
- */
- void (*sync_hw)(struct drm_i915_private *i915,
- struct i915_power_well *power_well);
- /*
- * Enable the well and resources that depend on it (for example
- * interrupts located on the well). Called after the 0->1 refcount
- * transition.
- */
- void (*enable)(struct drm_i915_private *i915,
- struct i915_power_well *power_well);
- /*
- * Disable the well and resources that depend on it. Called after
- * the 1->0 refcount transition.
- */
- void (*disable)(struct drm_i915_private *i915,
- struct i915_power_well *power_well);
- /* Returns the hw enabled state. */
- bool (*is_enabled)(struct drm_i915_private *i915,
- struct i915_power_well *power_well);
-};
-
struct i915_power_well_desc {
const char *name;
bool always_on;
@@ -150,4 +115,31 @@ const char *intel_power_well_name(struct i915_power_well *power_well);
u64 intel_power_well_domains(struct i915_power_well *power_well);
int intel_power_well_refcount(struct i915_power_well *power_well);
+void chv_phy_powergate_lanes(struct intel_encoder *encoder,
+ bool override, unsigned int mask);
+bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum dpio_phy phy,
+ enum dpio_channel ch, bool override);
+
+void gen9_enable_dc5(struct drm_i915_private *dev_priv);
+void skl_enable_dc6(struct drm_i915_private *dev_priv);
+void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
+void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state);
+void gen9_disable_dc_states(struct drm_i915_private *dev_priv);
+void bxt_enable_dc9(struct drm_i915_private *dev_priv);
+void bxt_disable_dc9(struct drm_i915_private *dev_priv);
+
+extern const struct i915_power_well_ops i9xx_always_on_power_well_ops;
+extern const struct i915_power_well_ops chv_pipe_power_well_ops;
+extern const struct i915_power_well_ops chv_dpio_cmn_power_well_ops;
+extern const struct i915_power_well_ops i830_pipes_power_well_ops;
+extern const struct i915_power_well_ops hsw_power_well_ops;
+extern const struct i915_power_well_ops gen9_dc_off_power_well_ops;
+extern const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops;
+extern const struct i915_power_well_ops vlv_display_power_well_ops;
+extern const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops;
+extern const struct i915_power_well_ops vlv_dpio_power_well_ops;
+extern const struct i915_power_well_ops icl_aux_power_well_ops;
+extern const struct i915_power_well_ops icl_ddi_power_well_ops;
+extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
+
#endif
diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
index 44edeb2e55c0c..cc6abe761f5e3 100644
--- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
+++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
@@ -24,6 +24,7 @@
#include "intel_ddi.h"
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
+#include "intel_display_power_well.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dpio_phy.h"
diff --git a/drivers/gpu/drm/i915/display/intel_pps.c b/drivers/gpu/drm/i915/display/intel_pps.c
index 64bd4ca0edd47..5a598dd060391 100644
--- a/drivers/gpu/drm/i915/display/intel_pps.c
+++ b/drivers/gpu/drm/i915/display/intel_pps.c
@@ -6,6 +6,7 @@
#include "g4x_dp.h"
#include "i915_drv.h"
#include "intel_de.h"
+#include "intel_display_power_well.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dpll.h"
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Intel-gfx] [PATCH v3 01/18] drm/i915: Move per-platform power well hooks to intel_display_power_well.c
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 01/18] drm/i915: Move per-platform power well hooks to intel_display_power_well.c Imre Deak
@ 2022-03-31 7:13 ` Hogander, Jouni
0 siblings, 0 replies; 29+ messages in thread
From: Hogander, Jouni @ 2022-03-31 7:13 UTC (permalink / raw)
To: intel-gfx, Deak, Imre
On Tue, 2022-03-29 at 19:43 +0300, Imre Deak wrote:
> Move the implementation of platform specific power well hooks to
> intel_display_power_well.c, to reduce the clutter in
> intel_display_power.c.
>
> The locking of all the power domain/power well state is handled in
> the
> power domain functions in intel_display_power.c using
> i915_power_domains::lock. This patch also moves the
> chy_phy_powergate_ch/lanes() functions to intel_display_power_well.c
> which borrow the same lock to protect the DISPLAY_PHY_CONTROL
> register
> state, which the HW uses both for toggling power wells and power
> gating
> PHY lanes.
>
> No functional change.
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
>
> v2:
> - Clarify in the commit log why CHV functions using the
> i915_power_domains::lock were moved, while others locking the power
> domain/well state were kept in intel_display_power.c . (Jouni)
> - Move forward declaration of chv_phy_powergate_ch/lanes() to
> intel_display_power_well.h .
>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
> .../drm/i915/display/intel_display_power.c | 1759 -------------
> ---
> .../drm/i915/display/intel_display_power.h | 5 -
> .../i915/display/intel_display_power_well.c | 1817
> +++++++++++++++++
> .../i915/display/intel_display_power_well.h | 62 +-
> drivers/gpu/drm/i915/display/intel_dpio_phy.c | 1 +
> drivers/gpu/drm/i915/display/intel_pps.c | 1 +
> 6 files changed, 1846 insertions(+), 1799 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 3dc859032bac7..35a5e36df8206 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -9,24 +9,16 @@
> #include "i915_irq.h"
> #include "intel_cdclk.h"
> #include "intel_combo_phy.h"
> -#include "intel_combo_phy_regs.h"
> -#include "intel_crt.h"
> #include "intel_de.h"
> #include "intel_display_power.h"
> #include "intel_display_power_well.h"
> #include "intel_display_types.h"
> #include "intel_dmc.h"
> -#include "intel_dpio_phy.h"
> -#include "intel_dpll.h"
> -#include "intel_hotplug.h"
> #include "intel_mchbar_regs.h"
> #include "intel_pch_refclk.h"
> #include "intel_pcode.h"
> #include "intel_pm.h"
> -#include "intel_pps.h"
> #include "intel_snps_phy.h"
> -#include "intel_tc.h"
> -#include "intel_vga.h"
> #include "vlv_sideband.h"
>
> const char *
> @@ -235,604 +227,6 @@ bool intel_display_power_is_enabled(struct
> drm_i915_private *dev_priv,
> return ret;
> }
>
> -/*
> - * Starting with Haswell, we have a "Power Down Well" that can be
> turned off
> - * when not needed anymore. We have 4 registers that can request the
> power well
> - * to be enabled, and it will only be disabled if none of the
> registers is
> - * requesting it to be enabled.
> - */
> -static void hsw_power_well_post_enable(struct drm_i915_private
> *dev_priv,
> - u8 irq_pipe_mask, bool has_vga)
> -{
> - if (has_vga)
> - intel_vga_reset_io_mem(dev_priv);
> -
> - if (irq_pipe_mask)
> - gen8_irq_power_well_post_enable(dev_priv,
> irq_pipe_mask);
> -}
> -
> -static void hsw_power_well_pre_disable(struct drm_i915_private
> *dev_priv,
> - u8 irq_pipe_mask)
> -{
> - if (irq_pipe_mask)
> - gen8_irq_power_well_pre_disable(dev_priv,
> irq_pipe_mask);
> -}
> -
> -#define ICL_AUX_PW_TO_CH(pw_idx) \
> - ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
> -
> -#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
> - ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
> -
> -static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well
> *power_well)
> -{
> - int pw_idx = power_well->desc->hsw.idx;
> -
> - return power_well->desc->hsw.is_tc_tbt ?
> ICL_TBT_AUX_PW_TO_CH(pw_idx) :
> - ICL_AUX_PW_TO_CH(pw_id
> x);
> -}
> -
> -static struct intel_digital_port *
> -aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
> - enum aux_ch aux_ch)
> -{
> - struct intel_digital_port *dig_port = NULL;
> - struct intel_encoder *encoder;
> -
> - for_each_intel_encoder(&dev_priv->drm, encoder) {
> - /* We'll check the MST primary port */
> - if (encoder->type == INTEL_OUTPUT_DP_MST)
> - continue;
> -
> - dig_port = enc_to_dig_port(encoder);
> - if (!dig_port)
> - continue;
> -
> - if (dig_port->aux_ch != aux_ch) {
> - dig_port = NULL;
> - continue;
> - }
> -
> - break;
> - }
> -
> - return dig_port;
> -}
> -
> -static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915,
> - const struct i915_power_well
> *power_well)
> -{
> - enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
> - struct intel_digital_port *dig_port =
> aux_ch_to_digital_port(i915, aux_ch);
> -
> - return intel_port_to_phy(i915, dig_port->base.port);
> -}
> -
> -static void hsw_wait_for_power_well_enable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well,
> - bool timeout_expected)
> -{
> - const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> - int pw_idx = power_well->desc->hsw.idx;
> - int enable_delay = power_well->desc->hsw.fixed_enable_delay;
> -
> - /*
> - * For some power wells we're not supposed to watch the status
> bit for
> - * an ack, but rather just wait a fixed amount of time and then
> - * proceed. This is only used on DG2.
> - */
> - if (IS_DG2(dev_priv) && enable_delay) {
> - usleep_range(enable_delay, 2 * enable_delay);
> - return;
> - }
> -
> - /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us.
> */
> - if (intel_de_wait_for_set(dev_priv, regs->driver,
> - HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {
> - drm_dbg_kms(&dev_priv->drm, "%s power well enable
> timeout\n",
> - intel_power_well_name(power_well));
> -
> - drm_WARN_ON(&dev_priv->drm, !timeout_expected);
> -
> - }
> -}
> -
> -static u32 hsw_power_well_requesters(struct drm_i915_private
> *dev_priv,
> - const struct i915_power_well_regs
> *regs,
> - int pw_idx)
> -{
> - u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
> - u32 ret;
> -
> - ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0;
> - ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 :
> 0;
> - if (regs->kvmr.reg)
> - ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ?
> 4 : 0;
> - ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0;
> -
> - return ret;
> -}
> -
> -static void hsw_wait_for_power_well_disable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> - int pw_idx = power_well->desc->hsw.idx;
> - bool disabled;
> - u32 reqs;
> -
> - /*
> - * Bspec doesn't require waiting for PWs to get disabled, but
> still do
> - * this for paranoia. The known cases where a PW will be forced
> on:
> - * - a KVMR request on any power well via the KVMR request
> register
> - * - a DMC request on PW1 and MISC_IO power wells via the BIOS
> and
> - * DEBUG request registers
> - * Skip the wait in case any of the request bits are set and
> print a
> - * diagnostic message.
> - */
> - wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) &
> - HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
> - (reqs = hsw_power_well_requesters(dev_priv, regs,
> pw_idx)), 1);
> - if (disabled)
> - return;
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "%s forced on (bios:%d driver:%d kvmr:%d
> debug:%d)\n",
> - intel_power_well_name(power_well),
> - !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs &
> 8));
> -}
> -
> -static void gen9_wait_for_power_well_fuses(struct drm_i915_private
> *dev_priv,
> - enum skl_power_gate pg)
> -{
> - /* Timeout 5us for PG#0, for other PGs 1us */
> - drm_WARN_ON(&dev_priv->drm,
> - intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS,
> - SKL_FUSE_PG_DIST_STATUS(pg),
> 1));
> -}
> -
> -static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> - struct i915_power_well *power_well)
> -{
> - const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> - int pw_idx = power_well->desc->hsw.idx;
> - u32 val;
> -
> - if (power_well->desc->hsw.has_fuses) {
> - enum skl_power_gate pg;
> -
> - pg = DISPLAY_VER(dev_priv) >= 11 ?
> ICL_PW_CTL_IDX_TO_PG(pw_idx) :
> - SKL_PW_CTL_IDX_TO_PG(p
> w_idx);
> -
> - /* Wa_16013190616:adlp */
> - if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1)
> - intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
> DISABLE_FLR_SRC);
> -
> - /*
> - * For PW1 we have to wait both for the PW0/PG0 fuse
> state
> - * before enabling the power well and PW1/PG1's own
> fuse
> - * state after the enabling. For all other power wells
> with
> - * fuses we only have to wait for that PW/PG's fuse
> state
> - * after the enabling.
> - */
> - if (pg == SKL_PG1)
> - gen9_wait_for_power_well_fuses(dev_priv,
> SKL_PG0);
> - }
> -
> - val = intel_de_read(dev_priv, regs->driver);
> - intel_de_write(dev_priv, regs->driver,
> - val | HSW_PWR_WELL_CTL_REQ(pw_idx));
> -
> - hsw_wait_for_power_well_enable(dev_priv, power_well, false);
> -
> - if (power_well->desc->hsw.has_fuses) {
> - enum skl_power_gate pg;
> -
> - pg = DISPLAY_VER(dev_priv) >= 11 ?
> ICL_PW_CTL_IDX_TO_PG(pw_idx) :
> - SKL_PW_CTL_IDX_TO_PG(p
> w_idx);
> - gen9_wait_for_power_well_fuses(dev_priv, pg);
> - }
> -
> - hsw_power_well_post_enable(dev_priv,
> - power_well->desc->hsw.irq_pipe_mask,
> - power_well->desc->hsw.has_vga);
> -}
> -
> -static void hsw_power_well_disable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well *power_well)
> -{
> - const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> - int pw_idx = power_well->desc->hsw.idx;
> - u32 val;
> -
> - hsw_power_well_pre_disable(dev_priv,
> - power_well->desc-
> >hsw.irq_pipe_mask);
> -
> - val = intel_de_read(dev_priv, regs->driver);
> - intel_de_write(dev_priv, regs->driver,
> - val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
> - hsw_wait_for_power_well_disable(dev_priv, power_well);
> -}
> -
> -static void
> -icl_combo_phy_aux_power_well_enable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well *power_well)
> -{
> - const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> - int pw_idx = power_well->desc->hsw.idx;
> - enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
> - u32 val;
> -
> - drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
> -
> - val = intel_de_read(dev_priv, regs->driver);
> - intel_de_write(dev_priv, regs->driver,
> - val | HSW_PWR_WELL_CTL_REQ(pw_idx));
> -
> - if (DISPLAY_VER(dev_priv) < 12) {
> - val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
> - intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
> - val | ICL_LANE_ENABLE_AUX);
> - }
> -
> - hsw_wait_for_power_well_enable(dev_priv, power_well, false);
> -
> - /* Display WA #1178: icl */
> - if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <=
> ICL_PW_CTL_IDX_AUX_B &&
> - !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
> - val = intel_de_read(dev_priv,
> ICL_AUX_ANAOVRD1(pw_idx));
> - val |= ICL_AUX_ANAOVRD1_ENABLE |
> ICL_AUX_ANAOVRD1_LDO_BYPASS;
> - intel_de_write(dev_priv, ICL_AUX_ANAOVRD1(pw_idx),
> val);
> - }
> -}
> -
> -static void
> -icl_combo_phy_aux_power_well_disable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> - int pw_idx = power_well->desc->hsw.idx;
> - enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
> - u32 val;
> -
> - drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
> -
> - val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
> - intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
> - val & ~ICL_LANE_ENABLE_AUX);
> -
> - val = intel_de_read(dev_priv, regs->driver);
> - intel_de_write(dev_priv, regs->driver,
> - val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
> -
> - hsw_wait_for_power_well_disable(dev_priv, power_well);
> -}
> -
> -#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> -
> -static void icl_tc_port_assert_ref_held(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well,
> - struct intel_digital_port
> *dig_port)
> -{
> - if (drm_WARN_ON(&dev_priv->drm, !dig_port))
> - return;
> -
> - if (DISPLAY_VER(dev_priv) == 11 &&
> intel_tc_cold_requires_aux_pw(dig_port))
> - return;
> -
> - drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
> -}
> -
> -#else
> -
> -static void icl_tc_port_assert_ref_held(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well,
> - struct intel_digital_port
> *dig_port)
> -{
> -}
> -
> -#endif
> -
> -#define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) -
> TGL_PW_CTL_IDX_AUX_TC1)
> -
> -static void icl_tc_cold_exit(struct drm_i915_private *i915)
> -{
> - int ret, tries = 0;
> -
> - while (1) {
> - ret = snb_pcode_write_timeout(i915,
> ICL_PCODE_EXIT_TCCOLD, 0,
> - 250, 1);
> - if (ret != -EAGAIN || ++tries == 3)
> - break;
> - msleep(1);
> - }
> -
> - /* Spec states that TC cold exit can take up to 1ms to complete
> */
> - if (!ret)
> - msleep(1);
> -
> - /* TODO: turn failure into a error as soon i915 CI updates ICL
> IFWI */
> - drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" :
> - "succeeded");
> -}
> -
> -static void
> -icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> - struct i915_power_well *power_well)
> -{
> - enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
> - struct intel_digital_port *dig_port =
> aux_ch_to_digital_port(dev_priv, aux_ch);
> - const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> - bool is_tbt = power_well->desc->hsw.is_tc_tbt;
> - bool timeout_expected;
> - u32 val;
> -
> - icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
> -
> - val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch));
> - val &= ~DP_AUX_CH_CTL_TBT_IO;
> - if (is_tbt)
> - val |= DP_AUX_CH_CTL_TBT_IO;
> - intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val);
> -
> - val = intel_de_read(dev_priv, regs->driver);
> - intel_de_write(dev_priv, regs->driver,
> - val | HSW_PWR_WELL_CTL_REQ(power_well->desc-
> >hsw.idx));
> -
> - /*
> - * An AUX timeout is expected if the TBT DP tunnel is down,
> - * or need to enable AUX on a legacy TypeC port as part of the
> TC-cold
> - * exit sequence.
> - */
> - timeout_expected = is_tbt ||
> intel_tc_cold_requires_aux_pw(dig_port);
> - if (DISPLAY_VER(dev_priv) == 11 &&
> intel_tc_cold_requires_aux_pw(dig_port))
> - icl_tc_cold_exit(dev_priv);
> -
> - hsw_wait_for_power_well_enable(dev_priv, power_well,
> timeout_expected);
> -
> - if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) {
> - enum tc_port tc_port;
> -
> - tc_port = TGL_AUX_PW_TO_TC_PORT(power_well->desc-
> >hsw.idx);
> - intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
> - HIP_INDEX_VAL(tc_port, 0x2));
> -
> - if (intel_de_wait_for_set(dev_priv,
> DKL_CMN_UC_DW_27(tc_port),
> - DKL_CMN_UC_DW27_UC_HEALTH,
> 1))
> - drm_warn(&dev_priv->drm,
> - "Timeout waiting TC uC health\n");
> - }
> -}
> -
> -static void
> -icl_aux_power_well_enable(struct drm_i915_private *dev_priv,
> - struct i915_power_well *power_well)
> -{
> - enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
> -
> - if (intel_phy_is_tc(dev_priv, phy))
> - return icl_tc_phy_aux_power_well_enable(dev_priv,
> power_well);
> - else if (IS_ICELAKE(dev_priv))
> - return icl_combo_phy_aux_power_well_enable(dev_priv,
> - power_well);
> - else
> - return hsw_power_well_enable(dev_priv, power_well);
> -}
> -
> -static void
> -icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
> - struct i915_power_well *power_well)
> -{
> - enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
> -
> - if (intel_phy_is_tc(dev_priv, phy))
> - return hsw_power_well_disable(dev_priv, power_well);
> - else if (IS_ICELAKE(dev_priv))
> - return icl_combo_phy_aux_power_well_disable(dev_priv,
> - power_well)
> ;
> - else
> - return hsw_power_well_disable(dev_priv, power_well);
> -}
> -
> -/*
> - * We should only use the power well if we explicitly asked the
> hardware to
> - * enable it, so check if it's enabled and also check if we've
> requested it to
> - * be enabled.
> - */
> -static bool hsw_power_well_enabled(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well *power_well)
> -{
> - const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> - enum i915_power_well_id id = power_well->desc->id;
> - int pw_idx = power_well->desc->hsw.idx;
> - u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
> - HSW_PWR_WELL_CTL_STATE(pw_idx);
> - u32 val;
> -
> - val = intel_de_read(dev_priv, regs->driver);
> -
> - /*
> - * On GEN9 big core due to a DMC bug the driver's request bits
> for PW1
> - * and the MISC_IO PW will be not restored, so check instead
> for the
> - * BIOS's own request bits, which are forced-on for these power
> wells
> - * when exiting DC5/6.
> - */
> - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
> - (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
> - val |= intel_de_read(dev_priv, regs->bios);
> -
> - return (val & mask) == mask;
> -}
> -
> -static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
> -{
> - drm_WARN_ONCE(&dev_priv->drm,
> - (intel_de_read(dev_priv, DC_STATE_EN) &
> DC_STATE_EN_DC9),
> - "DC9 already programmed to be enabled.\n");
> - drm_WARN_ONCE(&dev_priv->drm,
> - intel_de_read(dev_priv, DC_STATE_EN) &
> - DC_STATE_EN_UPTO_DC5,
> - "DC5 still not disabled to enable DC9.\n");
> - drm_WARN_ONCE(&dev_priv->drm,
> - intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) &
> - HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
> - "Power well 2 on.\n");
> - drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
> - "Interrupts not disabled yet.\n");
> -
> - /*
> - * TODO: check for the following to verify the conditions to
> enter DC9
> - * state are satisfied:
> - * 1] Check relevant display engine registers to verify if
> mode set
> - * disable sequence was followed.
> - * 2] Check if display uninitialize sequence is initialized.
> - */
> -}
> -
> -static void assert_can_disable_dc9(struct drm_i915_private
> *dev_priv)
> -{
> - drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
> - "Interrupts not disabled yet.\n");
> - drm_WARN_ONCE(&dev_priv->drm,
> - intel_de_read(dev_priv, DC_STATE_EN) &
> - DC_STATE_EN_UPTO_DC5,
> - "DC5 still not disabled.\n");
> -
> - /*
> - * TODO: check for the following to verify DC9 state was
> indeed
> - * entered before programming to disable it:
> - * 1] Check relevant display engine registers to verify if
> mode
> - * set disable sequence was followed.
> - * 2] Check if display uninitialize sequence is initialized.
> - */
> -}
> -
> -static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
> - u32 state)
> -{
> - int rewrites = 0;
> - int rereads = 0;
> - u32 v;
> -
> - intel_de_write(dev_priv, DC_STATE_EN, state);
> -
> - /* It has been observed that disabling the dc6 state sometimes
> - * doesn't stick and dmc keeps returning old value. Make sure
> - * the write really sticks enough times and also force rewrite
> until
> - * we are confident that state is exactly what we want.
> - */
> - do {
> - v = intel_de_read(dev_priv, DC_STATE_EN);
> -
> - if (v != state) {
> - intel_de_write(dev_priv, DC_STATE_EN, state);
> - rewrites++;
> - rereads = 0;
> - } else if (rereads++ > 5) {
> - break;
> - }
> -
> - } while (rewrites < 100);
> -
> - if (v != state)
> - drm_err(&dev_priv->drm,
> - "Writing dc state to 0x%x failed, now 0x%x\n",
> - state, v);
> -
> - /* Most of the times we need one retry, avoid spam */
> - if (rewrites > 1)
> - drm_dbg_kms(&dev_priv->drm,
> - "Rewrote dc state to 0x%x %d times\n",
> - state, rewrites);
> -}
> -
> -static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
> -{
> - u32 mask;
> -
> - mask = DC_STATE_EN_UPTO_DC5;
> -
> - if (DISPLAY_VER(dev_priv) >= 12)
> - mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
> - | DC_STATE_EN_DC9;
> - else if (DISPLAY_VER(dev_priv) == 11)
> - mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
> - else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> - mask |= DC_STATE_EN_DC9;
> - else
> - mask |= DC_STATE_EN_UPTO_DC6;
> -
> - return mask;
> -}
> -
> -static void gen9_sanitize_dc_state(struct drm_i915_private
> *dev_priv)
> -{
> - u32 val;
> -
> - if (!HAS_DISPLAY(dev_priv))
> - return;
> -
> - val = intel_de_read(dev_priv, DC_STATE_EN) &
> gen9_dc_mask(dev_priv);
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "Resetting DC state tracking from %02x to %02x\n",
> - dev_priv->dmc.dc_state, val);
> - dev_priv->dmc.dc_state = val;
> -}
> -
> -/**
> - * gen9_set_dc_state - set target display C power state
> - * @dev_priv: i915 device instance
> - * @state: target DC power state
> - * - DC_STATE_DISABLE
> - * - DC_STATE_EN_UPTO_DC5
> - * - DC_STATE_EN_UPTO_DC6
> - * - DC_STATE_EN_DC9
> - *
> - * Signal to DMC firmware/HW the target DC power state passed in
> @state.
> - * DMC/HW can turn off individual display clocks and power rails
> when entering
> - * a deeper DC power state (higher in number) and turns these back
> when exiting
> - * that state to a shallower power state (lower in number). The HW
> will decide
> - * when to actually enter a given state on an on-demand basis, for
> instance
> - * depending on the active state of display pipes. The state of
> display
> - * registers backed by affected power rails are saved/restored as
> needed.
> - *
> - * Based on the above enabling a deeper DC power state is
> asynchronous wrt.
> - * enabling it. Disabling a deeper power state is synchronous: for
> instance
> - * setting %DC_STATE_DISABLE won't complete until all HW resources
> are turned
> - * back on and register state is restored. This is guaranteed by the
> MMIO write
> - * to DC_STATE_EN blocking until the state is restored.
> - */
> -static void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32
> state)
> -{
> - u32 val;
> - u32 mask;
> -
> - if (!HAS_DISPLAY(dev_priv))
> - return;
> -
> - if (drm_WARN_ON_ONCE(&dev_priv->drm,
> - state & ~dev_priv->dmc.allowed_dc_mask))
> - state &= dev_priv->dmc.allowed_dc_mask;
> -
> - val = intel_de_read(dev_priv, DC_STATE_EN);
> - mask = gen9_dc_mask(dev_priv);
> - drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to
> %02x\n",
> - val & mask, state);
> -
> - /* Check if DMC is ignoring our DC state requests */
> - if ((val & mask) != dev_priv->dmc.dc_state)
> - drm_err(&dev_priv->drm, "DC state mismatch (0x%x ->
> 0x%x)\n",
> - dev_priv->dmc.dc_state, val & mask);
> -
> - val &= ~mask;
> - val |= state;
> -
> - gen9_write_dc_state(dev_priv, val);
> -
> - dev_priv->dmc.dc_state = val & mask;
> -}
> -
> static u32
> sanitize_target_dc_state(struct drm_i915_private *dev_priv,
> u32 target_dc_state)
> @@ -858,65 +252,6 @@ sanitize_target_dc_state(struct drm_i915_private
> *dev_priv,
> return target_dc_state;
> }
>
> -static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
> -{
> - drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n");
> - gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> -}
> -
> -static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
> -{
> - u32 val;
> -
> - drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n");
> - val = intel_de_read(dev_priv, DC_STATE_EN);
> - val &= ~DC_STATE_DC3CO_STATUS;
> - intel_de_write(dev_priv, DC_STATE_EN, val);
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> - /*
> - * Delay of 200us DC3CO Exit time B.Spec 49196
> - */
> - usleep_range(200, 210);
> -}
> -
> -static void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> -{
> - assert_can_enable_dc9(dev_priv);
> -
> - drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n");
> - /*
> - * Power sequencer reset is not needed on
> - * platforms with South Display Engine on PCH,
> - * because PPS registers are always on.
> - */
> - if (!HAS_PCH_SPLIT(dev_priv))
> - intel_pps_reset_all(dev_priv);
> - gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
> -}
> -
> -static void bxt_disable_dc9(struct drm_i915_private *dev_priv)
> -{
> - assert_can_disable_dc9(dev_priv);
> -
> - drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n");
> -
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> -
> - intel_pps_unlock_regs_wa(dev_priv);
> -}
> -
> -static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
> -{
> - drm_WARN_ONCE(&dev_priv->drm,
> - !intel_de_read(dev_priv,
> - DMC_PROGRAM(dev_priv-
> >dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
> - "DMC program storage start is
> NULL\n");
> - drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv,
> DMC_SSP_BASE),
> - "DMC SSP Base Not fine\n");
> - drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv,
> DMC_HTP_SKL),
> - "DMC HTP Not fine\n");
> -}
> -
> /**
> * intel_display_power_set_target_dc_state - Set target dc state.
> * @dev_priv: i915 device
> @@ -961,912 +296,8 @@ void
> intel_display_power_set_target_dc_state(struct drm_i915_private
> *dev_priv,
> mutex_unlock(&power_domains->lock);
> }
>
> -static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
> -{
> - enum i915_power_well_id high_pg;
> -
> - /* Power wells at this level and above must be disabled for DC5
> entry */
> - if (DISPLAY_VER(dev_priv) == 12)
> - high_pg = ICL_DISP_PW_3;
> - else
> - high_pg = SKL_DISP_PW_2;
> -
> - drm_WARN_ONCE(&dev_priv->drm,
> - intel_display_power_well_is_enabled(dev_priv,
> high_pg),
> - "Power wells above platform's DC5 limit still
> enabled.\n");
> -
> - drm_WARN_ONCE(&dev_priv->drm,
> - (intel_de_read(dev_priv, DC_STATE_EN) &
> - DC_STATE_EN_UPTO_DC5),
> - "DC5 already programmed to be enabled.\n");
> - assert_rpm_wakelock_held(&dev_priv->runtime_pm);
> -
> - assert_dmc_loaded(dev_priv);
> -}
> -
> -static void gen9_enable_dc5(struct drm_i915_private *dev_priv)
> -{
> - assert_can_enable_dc5(dev_priv);
> -
> - drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n");
> -
> - /* Wa Display #1183: skl,kbl,cfl */
> - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
> - intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
> - intel_de_read(dev_priv,
> GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
> -
> - gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> -}
> -
> -static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
> -{
> - drm_WARN_ONCE(&dev_priv->drm,
> - intel_de_read(dev_priv, UTIL_PIN_CTL) &
> UTIL_PIN_ENABLE,
> - "Backlight is not disabled.\n");
> - drm_WARN_ONCE(&dev_priv->drm,
> - (intel_de_read(dev_priv, DC_STATE_EN) &
> - DC_STATE_EN_UPTO_DC6),
> - "DC6 already programmed to be enabled.\n");
> -
> - assert_dmc_loaded(dev_priv);
> -}
> -
> -static void skl_enable_dc6(struct drm_i915_private *dev_priv)
> -{
> - assert_can_enable_dc6(dev_priv);
> -
> - drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n");
> -
> - /* Wa Display #1183: skl,kbl,cfl */
> - if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
> - intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
> - intel_de_read(dev_priv,
> GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
> -
> - gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
> -}
> -
> -static void hsw_power_well_sync_hw(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well *power_well)
> -{
> - const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> - int pw_idx = power_well->desc->hsw.idx;
> - u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
> - u32 bios_req = intel_de_read(dev_priv, regs->bios);
> -
> - /* Take over the request bit if set by BIOS. */
> - if (bios_req & mask) {
> - u32 drv_req = intel_de_read(dev_priv, regs->driver);
> -
> - if (!(drv_req & mask))
> - intel_de_write(dev_priv, regs->driver, drv_req
> | mask);
> - intel_de_write(dev_priv, regs->bios, bios_req & ~mask);
> - }
> -}
> -
> -static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy);
> -}
> -
> -static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy);
> -}
> -
> -static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc-
> >bxt.phy);
> -}
> -
> -static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private
> *dev_priv)
> -{
> - struct i915_power_well *power_well;
> -
> - power_well = lookup_power_well(dev_priv,
> BXT_DISP_PW_DPIO_CMN_A);
> - if (intel_power_well_refcount(power_well) > 0)
> - bxt_ddi_phy_verify_state(dev_priv, power_well->desc-
> >bxt.phy);
> -
> - power_well = lookup_power_well(dev_priv,
> VLV_DISP_PW_DPIO_CMN_BC);
> - if (intel_power_well_refcount(power_well) > 0)
> - bxt_ddi_phy_verify_state(dev_priv, power_well->desc-
> >bxt.phy);
> -
> - if (IS_GEMINILAKE(dev_priv)) {
> - power_well = lookup_power_well(dev_priv,
> - GLK_DISP_PW_DPIO_CMN_C);
> - if (intel_power_well_refcount(power_well) > 0)
> - bxt_ddi_phy_verify_state(dev_priv,
> - power_well->desc-
> >bxt.phy);
> - }
> -}
> -
> -static bool gen9_dc_off_power_well_enabled(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - return ((intel_de_read(dev_priv, DC_STATE_EN) &
> DC_STATE_EN_DC3CO) == 0 &&
> - (intel_de_read(dev_priv, DC_STATE_EN) &
> DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
> -}
> -
> -static void gen9_assert_dbuf_enabled(struct drm_i915_private
> *dev_priv)
> -{
> - u8 hw_enabled_dbuf_slices =
> intel_enabled_dbuf_slices_mask(dev_priv);
> - u8 enabled_dbuf_slices = dev_priv->dbuf.enabled_slices;
> -
> - drm_WARN(&dev_priv->drm,
> - hw_enabled_dbuf_slices != enabled_dbuf_slices,
> - "Unexpected DBuf power power state (0x%08x, expected
> 0x%08x)\n",
> - hw_enabled_dbuf_slices,
> - enabled_dbuf_slices);
> -}
> -
> -static void gen9_disable_dc_states(struct drm_i915_private
> *dev_priv)
> -{
> - struct intel_cdclk_config cdclk_config = {};
> -
> - if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) {
> - tgl_disable_dc3co(dev_priv);
> - return;
> - }
> -
> - gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> -
> - if (!HAS_DISPLAY(dev_priv))
> - return;
> -
> - intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
> - /* Can't read out voltage_level so can't use
> intel_cdclk_changed() */
> - drm_WARN_ON(&dev_priv->drm,
> - intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
> - &cdclk_config));
> -
> - gen9_assert_dbuf_enabled(dev_priv);
> -
> - if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> - bxt_verify_ddi_phy_power_wells(dev_priv);
> -
> - if (DISPLAY_VER(dev_priv) >= 11)
> - /*
> - * DMC retains HW context only for port A, the other
> combo
> - * PHY's HW context for port B is lost after DC
> transitions,
> - * so we need to restore it manually.
> - */
> - intel_combo_phy_init(dev_priv);
> -}
> -
> -static void gen9_dc_off_power_well_enable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - gen9_disable_dc_states(dev_priv);
> -}
> -
> -static void gen9_dc_off_power_well_disable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - if (!intel_dmc_has_payload(dev_priv))
> - return;
> -
> - switch (dev_priv->dmc.target_dc_state) {
> - case DC_STATE_EN_DC3CO:
> - tgl_enable_dc3co(dev_priv);
> - break;
> - case DC_STATE_EN_UPTO_DC6:
> - skl_enable_dc6(dev_priv);
> - break;
> - case DC_STATE_EN_UPTO_DC5:
> - gen9_enable_dc5(dev_priv);
> - break;
> - }
> -}
> -
> -static void i9xx_power_well_sync_hw_noop(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> -}
> -
> -static void i9xx_always_on_power_well_noop(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> -}
> -
> -static bool i9xx_always_on_power_well_enabled(struct
> drm_i915_private *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - return true;
> -}
> -
> -static void i830_pipes_power_well_enable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) &
> PIPECONF_ENABLE) == 0)
> - i830_enable_pipe(dev_priv, PIPE_A);
> - if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) &
> PIPECONF_ENABLE) == 0)
> - i830_enable_pipe(dev_priv, PIPE_B);
> -}
> -
> -static void i830_pipes_power_well_disable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - i830_disable_pipe(dev_priv, PIPE_B);
> - i830_disable_pipe(dev_priv, PIPE_A);
> -}
> -
> -static bool i830_pipes_power_well_enabled(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - return intel_de_read(dev_priv, PIPECONF(PIPE_A)) &
> PIPECONF_ENABLE &&
> - intel_de_read(dev_priv, PIPECONF(PIPE_B)) &
> PIPECONF_ENABLE;
> -}
> -
> -static void i830_pipes_power_well_sync_hw(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - if (intel_power_well_refcount(power_well) > 0)
> - i830_pipes_power_well_enable(dev_priv, power_well);
> - else
> - i830_pipes_power_well_disable(dev_priv, power_well);
> -}
> -
> -static void vlv_set_power_well(struct drm_i915_private *dev_priv,
> - struct i915_power_well *power_well, bool
> enable)
> -{
> - int pw_idx = power_well->desc->vlv.idx;
> - u32 mask;
> - u32 state;
> - u32 ctrl;
> -
> - mask = PUNIT_PWRGT_MASK(pw_idx);
> - state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
> - PUNIT_PWRGT_PWR_GATE(pw_idx);
> -
> - vlv_punit_get(dev_priv);
> -
> -#define COND \
> - ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) ==
> state)
> -
> - if (COND)
> - goto out;
> -
> - ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
> - ctrl &= ~mask;
> - ctrl |= state;
> - vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
> -
> - if (wait_for(COND, 100))
> - drm_err(&dev_priv->drm,
> - "timeout setting power well state %08x
> (%08x)\n",
> - state,
> - vlv_punit_read(dev_priv,
> PUNIT_REG_PWRGT_CTRL));
> -
> -#undef COND
> -
> -out:
> - vlv_punit_put(dev_priv);
> -}
> -
> -static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
> - struct i915_power_well *power_well)
> -{
> - vlv_set_power_well(dev_priv, power_well, true);
> -}
> -
> -static void vlv_power_well_disable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well *power_well)
> -{
> - vlv_set_power_well(dev_priv, power_well, false);
> -}
> -
> -static bool vlv_power_well_enabled(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well *power_well)
> -{
> - int pw_idx = power_well->desc->vlv.idx;
> - bool enabled = false;
> - u32 mask;
> - u32 state;
> - u32 ctrl;
> -
> - mask = PUNIT_PWRGT_MASK(pw_idx);
> - ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
> -
> - vlv_punit_get(dev_priv);
> -
> - state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) &
> mask;
> - /*
> - * We only ever set the power-on and power-gate states,
> anything
> - * else is unexpected.
> - */
> - drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx)
> &&
> - state != PUNIT_PWRGT_PWR_GATE(pw_idx));
> - if (state == ctrl)
> - enabled = true;
> -
> - /*
> - * A transient state at this point would mean some unexpected
> party
> - * is poking at the power controls too.
> - */
> - ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
> - drm_WARN_ON(&dev_priv->drm, ctrl != state);
> -
> - vlv_punit_put(dev_priv);
> -
> - return enabled;
> -}
> -
> -static void vlv_init_display_clock_gating(struct drm_i915_private
> *dev_priv)
> -{
> - u32 val;
> -
> - /*
> - * On driver load, a pipe may be active and driving a DSI
> display.
> - * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe
> getting stuck
> - * (and never recovering) in this case.
> intel_dsi_post_disable() will
> - * clear it when we turn off the display.
> - */
> - val = intel_de_read(dev_priv, DSPCLK_GATE_D);
> - val &= DPOUNIT_CLOCK_GATE_DISABLE;
> - val |= VRHUNIT_CLOCK_GATE_DISABLE;
> - intel_de_write(dev_priv, DSPCLK_GATE_D, val);
> -
> - /*
> - * Disable trickle feed and enable pnd deadline calculation
> - */
> - intel_de_write(dev_priv, MI_ARB_VLV,
> - MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> - intel_de_write(dev_priv, CBR1_VLV, 0);
> -
> - drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq
> == 0);
> - intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
> - DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)-
> >rawclk_freq,
> - 1000));
> -}
> -
> -static void vlv_display_power_well_init(struct drm_i915_private
> *dev_priv)
> -{
> - struct intel_encoder *encoder;
> - enum pipe pipe;
> -
> - /*
> - * Enable the CRI clock source so we can get at the
> - * display and the reference clock for VGA
> - * hotplug / manual detection. Supposedly DSI also
> - * needs the ref clock up and running.
> - *
> - * CHV DPLL B/C have some issues if VGA mode is enabled.
> - */
> - for_each_pipe(dev_priv, pipe) {
> - u32 val = intel_de_read(dev_priv, DPLL(pipe));
> -
> - val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> - if (pipe != PIPE_A)
> - val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> -
> - intel_de_write(dev_priv, DPLL(pipe), val);
> - }
> -
> - vlv_init_display_clock_gating(dev_priv);
> -
> - spin_lock_irq(&dev_priv->irq_lock);
> - valleyview_enable_display_irqs(dev_priv);
> - spin_unlock_irq(&dev_priv->irq_lock);
> -
> - /*
> - * During driver initialization/resume we can avoid restoring
> the
> - * part of the HW/SW state that will be inited anyway
> explicitly.
> - */
> - if (dev_priv->power_domains.initializing)
> - return;
> -
> - intel_hpd_init(dev_priv);
> - intel_hpd_poll_disable(dev_priv);
> -
> - /* Re-enable the ADPA, if we have one */
> - for_each_intel_encoder(&dev_priv->drm, encoder) {
> - if (encoder->type == INTEL_OUTPUT_ANALOG)
> - intel_crt_reset(&encoder->base);
> - }
> -
> - intel_vga_redisable_power_on(dev_priv);
> -
> - intel_pps_unlock_regs_wa(dev_priv);
> -}
> -
> -static void vlv_display_power_well_deinit(struct drm_i915_private
> *dev_priv)
> -{
> - spin_lock_irq(&dev_priv->irq_lock);
> - valleyview_disable_display_irqs(dev_priv);
> - spin_unlock_irq(&dev_priv->irq_lock);
> -
> - /* make sure we're done processing display irqs */
> - intel_synchronize_irq(dev_priv);
> -
> - intel_pps_reset_all(dev_priv);
> -
> - /* Prevent us from re-enabling polling on accident in late
> suspend */
> - if (!dev_priv->drm.dev->power.is_suspended)
> - intel_hpd_poll_enable(dev_priv);
> -}
> -
> -static void vlv_display_power_well_enable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - vlv_set_power_well(dev_priv, power_well, true);
> -
> - vlv_display_power_well_init(dev_priv);
> -}
> -
> -static void vlv_display_power_well_disable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - vlv_display_power_well_deinit(dev_priv);
> -
> - vlv_set_power_well(dev_priv, power_well, false);
> -}
> -
> -static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - /* since ref/cri clock was enabled */
> - udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
> -
> - vlv_set_power_well(dev_priv, power_well, true);
> -
> - /*
> - * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
> - * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
> - * a. GUnit 0x2110 bit[0] set to 1 (def 0)
> - * b. The other bits such as sfr settings / modesel may all
> - * be set to 0.
> - *
> - * This should only be done on init and resume from S3 with
> - * both PLLs disabled, or we risk losing DPIO and PLL
> - * synchronization.
> - */
> - intel_de_write(dev_priv, DPIO_CTL,
> - intel_de_read(dev_priv, DPIO_CTL) |
> DPIO_CMNRST);
> -}
> -
> -static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - enum pipe pipe;
> -
> - for_each_pipe(dev_priv, pipe)
> - assert_pll_disabled(dev_priv, pipe);
> -
> - /* Assert common reset */
> - intel_de_write(dev_priv, DPIO_CTL,
> - intel_de_read(dev_priv, DPIO_CTL) &
> ~DPIO_CMNRST);
> -
> - vlv_set_power_well(dev_priv, power_well, false);
> -}
> -
> #define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
>
> -#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
> -
> -static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
> -{
> - struct i915_power_well *cmn_bc =
> - lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
> - struct i915_power_well *cmn_d =
> - lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
> - u32 phy_control = dev_priv->chv_phy_control;
> - u32 phy_status = 0;
> - u32 phy_status_mask = 0xffffffff;
> -
> - /*
> - * The BIOS can leave the PHY is some weird state
> - * where it doesn't fully power down some parts.
> - * Disable the asserts until the PHY has been fully
> - * reset (ie. the power well has been disabled at
> - * least once).
> - */
> - if (!dev_priv->chv_phy_assert[DPIO_PHY0])
> - phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0,
> DPIO_CH0) |
> - PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH0, 0) |
> - PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH0, 1) |
> - PHY_STATUS_CMN_LDO(DPIO_PHY0,
> DPIO_CH1) |
> - PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH1, 0) |
> - PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH1, 1));
> -
> - if (!dev_priv->chv_phy_assert[DPIO_PHY1])
> - phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1,
> DPIO_CH0) |
> - PHY_STATUS_SPLINE_LDO(DPIO_PHY1,
> DPIO_CH0, 0) |
> - PHY_STATUS_SPLINE_LDO(DPIO_PHY1,
> DPIO_CH0, 1));
> -
> - if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
> - phy_status |= PHY_POWERGOOD(DPIO_PHY0);
> -
> - /* this assumes override is only used to enable lanes
> */
> - if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0,
> DPIO_CH0)) == 0)
> - phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf,
> DPIO_PHY0, DPIO_CH0);
> -
> - if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0,
> DPIO_CH1)) == 0)
> - phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf,
> DPIO_PHY0, DPIO_CH1);
> -
> - /* CL1 is on whenever anything is on in either channel
> */
> - if (BITS_SET(phy_control,
> - PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0,
> DPIO_CH0) |
> - PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0,
> DPIO_CH1)))
> - phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0,
> DPIO_CH0);
> -
> - /*
> - * The DPLLB check accounts for the pipe B + port A
> usage
> - * with CL2 powered up but all the lanes in the second
> channel
> - * powered down.
> - */
> - if (BITS_SET(phy_control,
> - PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0,
> DPIO_CH1)) &&
> - (intel_de_read(dev_priv, DPLL(PIPE_B)) &
> DPLL_VCO_ENABLE) == 0)
> - phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0,
> DPIO_CH1);
> -
> - if (BITS_SET(phy_control,
> - PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0,
> DPIO_CH0)))
> - phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH0, 0);
> - if (BITS_SET(phy_control,
> - PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0,
> DPIO_CH0)))
> - phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH0, 1);
> -
> - if (BITS_SET(phy_control,
> - PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0,
> DPIO_CH1)))
> - phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH1, 0);
> - if (BITS_SET(phy_control,
> - PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0,
> DPIO_CH1)))
> - phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH1, 1);
> - }
> -
> - if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
> - phy_status |= PHY_POWERGOOD(DPIO_PHY1);
> -
> - /* this assumes override is only used to enable lanes
> */
> - if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1,
> DPIO_CH0)) == 0)
> - phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf,
> DPIO_PHY1, DPIO_CH0);
> -
> - if (BITS_SET(phy_control,
> - PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1,
> DPIO_CH0)))
> - phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1,
> DPIO_CH0);
> -
> - if (BITS_SET(phy_control,
> - PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1,
> DPIO_CH0)))
> - phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1,
> DPIO_CH0, 0);
> - if (BITS_SET(phy_control,
> - PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1,
> DPIO_CH0)))
> - phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1,
> DPIO_CH0, 1);
> - }
> -
> - phy_status &= phy_status_mask;
> -
> - /*
> - * The PHY may be busy with some initial calibration and
> whatnot,
> - * so the power state can take a while to actually change.
> - */
> - if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS,
> - phy_status_mask, phy_status,
> 10))
> - drm_err(&dev_priv->drm,
> - "Unexpected PHY_STATUS 0x%08x, expected 0x%08x
> (PHY_CONTROL=0x%08x)\n",
> - intel_de_read(dev_priv, DISPLAY_PHY_STATUS) &
> phy_status_mask,
> - phy_status, dev_priv->chv_phy_control);
> -}
> -
> -#undef BITS_SET
> -
> -static void chv_dpio_cmn_power_well_enable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - enum dpio_phy phy;
> - enum pipe pipe;
> - u32 tmp;
> -
> - drm_WARN_ON_ONCE(&dev_priv->drm,
> - power_well->desc->id !=
> VLV_DISP_PW_DPIO_CMN_BC &&
> - power_well->desc->id !=
> CHV_DISP_PW_DPIO_CMN_D);
> -
> - if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
> - pipe = PIPE_A;
> - phy = DPIO_PHY0;
> - } else {
> - pipe = PIPE_C;
> - phy = DPIO_PHY1;
> - }
> -
> - /* since ref/cri clock was enabled */
> - udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
> - vlv_set_power_well(dev_priv, power_well, true);
> -
> - /* Poll for phypwrgood signal */
> - if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
> - PHY_POWERGOOD(phy), 1))
> - drm_err(&dev_priv->drm, "Display PHY %d is not power
> up\n",
> - phy);
> -
> - vlv_dpio_get(dev_priv);
> -
> - /* Enable dynamic power down */
> - tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
> - tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
> - DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
> - vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
> -
> - if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
> - tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
> - tmp |= DPIO_DYNPWRDOWNEN_CH1;
> - vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
> - } else {
> - /*
> - * Force the non-existing CL2 off. BXT does this
> - * too, so maybe it saves some power even though
> - * CL2 doesn't exist?
> - */
> - tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
> - tmp |= DPIO_CL2_LDOFUSE_PWRENB;
> - vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
> - }
> -
> - vlv_dpio_put(dev_priv);
> -
> - dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
> - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
> - dev_priv->chv_phy_control);
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
> - phy, dev_priv->chv_phy_control);
> -
> - assert_chv_phy_status(dev_priv);
> -}
> -
> -static void chv_dpio_cmn_power_well_disable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - enum dpio_phy phy;
> -
> - drm_WARN_ON_ONCE(&dev_priv->drm,
> - power_well->desc->id !=
> VLV_DISP_PW_DPIO_CMN_BC &&
> - power_well->desc->id !=
> CHV_DISP_PW_DPIO_CMN_D);
> -
> - if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
> - phy = DPIO_PHY0;
> - assert_pll_disabled(dev_priv, PIPE_A);
> - assert_pll_disabled(dev_priv, PIPE_B);
> - } else {
> - phy = DPIO_PHY1;
> - assert_pll_disabled(dev_priv, PIPE_C);
> - }
> -
> - dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
> - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
> - dev_priv->chv_phy_control);
> -
> - vlv_set_power_well(dev_priv, power_well, false);
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
> - phy, dev_priv->chv_phy_control);
> -
> - /* PHY is fully reset now, so we can enable the PHY state
> asserts */
> - dev_priv->chv_phy_assert[phy] = true;
> -
> - assert_chv_phy_status(dev_priv);
> -}
> -
> -static void assert_chv_phy_powergate(struct drm_i915_private
> *dev_priv, enum dpio_phy phy,
> - enum dpio_channel ch, bool
> override, unsigned int mask)
> -{
> - enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
> - u32 reg, val, expected, actual;
> -
> - /*
> - * The BIOS can leave the PHY is some weird state
> - * where it doesn't fully power down some parts.
> - * Disable the asserts until the PHY has been fully
> - * reset (ie. the power well has been disabled at
> - * least once).
> - */
> - if (!dev_priv->chv_phy_assert[phy])
> - return;
> -
> - if (ch == DPIO_CH0)
> - reg = _CHV_CMN_DW0_CH0;
> - else
> - reg = _CHV_CMN_DW6_CH1;
> -
> - vlv_dpio_get(dev_priv);
> - val = vlv_dpio_read(dev_priv, pipe, reg);
> - vlv_dpio_put(dev_priv);
> -
> - /*
> - * This assumes !override is only used when the port is
> disabled.
> - * All lanes should power down even without the override when
> - * the port is disabled.
> - */
> - if (!override || mask == 0xf) {
> - expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
> - /*
> - * If CH1 common lane is not active anymore
> - * (eg. for pipe B DPLL) the entire channel will
> - * shut down, which causes the common lane registers
> - * to read as 0. That means we can't actually check
> - * the lane power down status bits, but as the entire
> - * register reads as 0 it's a good indication that the
> - * channel is indeed entirely powered down.
> - */
> - if (ch == DPIO_CH1 && val == 0)
> - expected = 0;
> - } else if (mask != 0x0) {
> - expected = DPIO_ANYDL_POWERDOWN;
> - } else {
> - expected = 0;
> - }
> -
> - if (ch == DPIO_CH0)
> - actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
> - else
> - actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
> - actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
> -
> - drm_WARN(&dev_priv->drm, actual != expected,
> - "Unexpected DPIO lane power down: all %d, any %d.
> Expected: all %d, any %d. (0x%x = 0x%08x)\n",
> - !!(actual & DPIO_ALLDL_POWERDOWN),
> - !!(actual & DPIO_ANYDL_POWERDOWN),
> - !!(expected & DPIO_ALLDL_POWERDOWN),
> - !!(expected & DPIO_ANYDL_POWERDOWN),
> - reg, val);
> -}
> -
> -bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum
> dpio_phy phy,
> - enum dpio_channel ch, bool override)
> -{
> - struct i915_power_domains *power_domains = &dev_priv-
> >power_domains;
> - bool was_override;
> -
> - mutex_lock(&power_domains->lock);
> -
> - was_override = dev_priv->chv_phy_control &
> PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> -
> - if (override == was_override)
> - goto out;
> -
> - if (override)
> - dev_priv->chv_phy_control |=
> PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> - else
> - dev_priv->chv_phy_control &=
> ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> -
> - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
> - dev_priv->chv_phy_control);
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "Power gating DPIO PHY%d CH%d
> (DPIO_PHY_CONTROL=0x%08x)\n",
> - phy, ch, dev_priv->chv_phy_control);
> -
> - assert_chv_phy_status(dev_priv);
> -
> -out:
> - mutex_unlock(&power_domains->lock);
> -
> - return was_override;
> -}
> -
> -void chv_phy_powergate_lanes(struct intel_encoder *encoder,
> - bool override, unsigned int mask)
> -{
> - struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> - struct i915_power_domains *power_domains = &dev_priv-
> >power_domains;
> - enum dpio_phy phy =
> vlv_dig_port_to_phy(enc_to_dig_port(encoder));
> - enum dpio_channel ch =
> vlv_dig_port_to_channel(enc_to_dig_port(encoder));
> -
> - mutex_lock(&power_domains->lock);
> -
> - dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy,
> ch);
> - dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy,
> ch);
> -
> - if (override)
> - dev_priv->chv_phy_control |=
> PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> - else
> - dev_priv->chv_phy_control &=
> ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> -
> - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
> - dev_priv->chv_phy_control);
> -
> - drm_dbg_kms(&dev_priv->drm,
> - "Power gating DPIO PHY%d CH%d lanes 0x%x
> (PHY_CONTROL=0x%08x)\n",
> - phy, ch, mask, dev_priv->chv_phy_control);
> -
> - assert_chv_phy_status(dev_priv);
> -
> - assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
> -
> - mutex_unlock(&power_domains->lock);
> -}
> -
> -static bool chv_pipe_power_well_enabled(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - enum pipe pipe = PIPE_A;
> - bool enabled;
> - u32 state, ctrl;
> -
> - vlv_punit_get(dev_priv);
> -
> - state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
> DP_SSS_MASK(pipe);
> - /*
> - * We only ever set the power-on and power-gate states,
> anything
> - * else is unexpected.
> - */
> - drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) &&
> - state != DP_SSS_PWR_GATE(pipe));
> - enabled = state == DP_SSS_PWR_ON(pipe);
> -
> - /*
> - * A transient state at this point would mean some unexpected
> party
> - * is poking at the power controls too.
> - */
> - ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
> DP_SSC_MASK(pipe);
> - drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state);
> -
> - vlv_punit_put(dev_priv);
> -
> - return enabled;
> -}
> -
> -static void chv_set_pipe_power_well(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well *power_well,
> - bool enable)
> -{
> - enum pipe pipe = PIPE_A;
> - u32 state;
> - u32 ctrl;
> -
> - state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
> -
> - vlv_punit_get(dev_priv);
> -
> -#define COND \
> - ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
> DP_SSS_MASK(pipe)) == state)
> -
> - if (COND)
> - goto out;
> -
> - ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
> - ctrl &= ~DP_SSC_MASK(pipe);
> - ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
> - vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl);
> -
> - if (wait_for(COND, 100))
> - drm_err(&dev_priv->drm,
> - "timeout setting power well state %08x
> (%08x)\n",
> - state,
> - vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM));
> -
> -#undef COND
> -
> -out:
> - vlv_punit_put(dev_priv);
> -}
> -
> -static void chv_pipe_power_well_sync_hw(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
> - dev_priv->chv_phy_control);
> -}
> -
> -static void chv_pipe_power_well_enable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - chv_set_pipe_power_well(dev_priv, power_well, true);
> -
> - vlv_display_power_well_init(dev_priv);
> -}
> -
> -static void chv_pipe_power_well_disable(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - vlv_display_power_well_deinit(dev_priv);
> -
> - chv_set_pipe_power_well(dev_priv, power_well, false);
> -}
> -
> static u64 __async_put_domains_mask(struct i915_power_domains
> *power_domains)
> {
> return power_domains->async_put_domains[0] |
> @@ -3046,27 +1477,6 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> #define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_PORT_DDI_IO_TC3)
> #define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_PORT_DDI_IO_TC4)
>
> -static const struct i915_power_well_ops
> i9xx_always_on_power_well_ops = {
> - .sync_hw = i9xx_power_well_sync_hw_noop,
> - .enable = i9xx_always_on_power_well_noop,
> - .disable = i9xx_always_on_power_well_noop,
> - .is_enabled = i9xx_always_on_power_well_enabled,
> -};
> -
> -static const struct i915_power_well_ops chv_pipe_power_well_ops = {
> - .sync_hw = chv_pipe_power_well_sync_hw,
> - .enable = chv_pipe_power_well_enable,
> - .disable = chv_pipe_power_well_disable,
> - .is_enabled = chv_pipe_power_well_enabled,
> -};
> -
> -static const struct i915_power_well_ops chv_dpio_cmn_power_well_ops
> = {
> - .sync_hw = i9xx_power_well_sync_hw_noop,
> - .enable = chv_dpio_cmn_power_well_enable,
> - .disable = chv_dpio_cmn_power_well_disable,
> - .is_enabled = vlv_power_well_enabled,
> -};
> -
> static const struct i915_power_well_desc i9xx_always_on_power_well[]
> = {
> {
> .name = "always-on",
> @@ -3077,13 +1487,6 @@ static const struct i915_power_well_desc
> i9xx_always_on_power_well[] = {
> },
> };
>
> -static const struct i915_power_well_ops i830_pipes_power_well_ops =
> {
> - .sync_hw = i830_pipes_power_well_sync_hw,
> - .enable = i830_pipes_power_well_enable,
> - .disable = i830_pipes_power_well_disable,
> - .is_enabled = i830_pipes_power_well_enabled,
> -};
> -
> static const struct i915_power_well_desc i830_power_wells[] = {
> {
> .name = "always-on",
> @@ -3100,35 +1503,6 @@ static const struct i915_power_well_desc
> i830_power_wells[] = {
> },
> };
>
> -static const struct i915_power_well_regs hsw_power_well_regs = {
> - .bios = HSW_PWR_WELL_CTL1,
> - .driver = HSW_PWR_WELL_CTL2,
> - .kvmr = HSW_PWR_WELL_CTL3,
> - .debug = HSW_PWR_WELL_CTL4,
> -};
> -
> -static const struct i915_power_well_ops hsw_power_well_ops = {
> - .regs = &hsw_power_well_regs,
> - .sync_hw = hsw_power_well_sync_hw,
> - .enable = hsw_power_well_enable,
> - .disable = hsw_power_well_disable,
> - .is_enabled = hsw_power_well_enabled,
> -};
> -
> -static const struct i915_power_well_ops gen9_dc_off_power_well_ops =
> {
> - .sync_hw = i9xx_power_well_sync_hw_noop,
> - .enable = gen9_dc_off_power_well_enable,
> - .disable = gen9_dc_off_power_well_disable,
> - .is_enabled = gen9_dc_off_power_well_enabled,
> -};
> -
> -static const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops
> = {
> - .sync_hw = i9xx_power_well_sync_hw_noop,
> - .enable = bxt_dpio_cmn_power_well_enable,
> - .disable = bxt_dpio_cmn_power_well_disable,
> - .is_enabled = bxt_dpio_cmn_power_well_enabled,
> -};
> -
> static const struct i915_power_well_desc hsw_power_wells[] = {
> {
> .name = "always-on",
> @@ -3170,27 +1544,6 @@ static const struct i915_power_well_desc
> bdw_power_wells[] = {
> },
> };
>
> -static const struct i915_power_well_ops vlv_display_power_well_ops =
> {
> - .sync_hw = i9xx_power_well_sync_hw_noop,
> - .enable = vlv_display_power_well_enable,
> - .disable = vlv_display_power_well_disable,
> - .is_enabled = vlv_power_well_enabled,
> -};
> -
> -static const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops
> = {
> - .sync_hw = i9xx_power_well_sync_hw_noop,
> - .enable = vlv_dpio_cmn_power_well_enable,
> - .disable = vlv_dpio_cmn_power_well_disable,
> - .is_enabled = vlv_power_well_enabled,
> -};
> -
> -static const struct i915_power_well_ops vlv_dpio_power_well_ops = {
> - .sync_hw = i9xx_power_well_sync_hw_noop,
> - .enable = vlv_power_well_enable,
> - .disable = vlv_power_well_disable,
> - .is_enabled = vlv_power_well_enabled,
> -};
> -
> static const struct i915_power_well_desc vlv_power_wells[] = {
> {
> .name = "always-on",
> @@ -3572,34 +1925,6 @@ static const struct i915_power_well_desc
> glk_power_wells[] = {
> },
> };
>
> -static const struct i915_power_well_regs icl_aux_power_well_regs = {
> - .bios = ICL_PWR_WELL_CTL_AUX1,
> - .driver = ICL_PWR_WELL_CTL_AUX2,
> - .debug = ICL_PWR_WELL_CTL_AUX4,
> -};
> -
> -static const struct i915_power_well_ops icl_aux_power_well_ops = {
> - .regs = &icl_aux_power_well_regs,
> - .sync_hw = hsw_power_well_sync_hw,
> - .enable = icl_aux_power_well_enable,
> - .disable = icl_aux_power_well_disable,
> - .is_enabled = hsw_power_well_enabled,
> -};
> -
> -static const struct i915_power_well_regs icl_ddi_power_well_regs = {
> - .bios = ICL_PWR_WELL_CTL_DDI1,
> - .driver = ICL_PWR_WELL_CTL_DDI2,
> - .debug = ICL_PWR_WELL_CTL_DDI4,
> -};
> -
> -static const struct i915_power_well_ops icl_ddi_power_well_ops = {
> - .regs = &icl_ddi_power_well_regs,
> - .sync_hw = hsw_power_well_sync_hw,
> - .enable = hsw_power_well_enable,
> - .disable = hsw_power_well_disable,
> - .is_enabled = hsw_power_well_enabled,
> -};
> -
> static const struct i915_power_well_desc icl_power_wells[] = {
> {
> .name = "always-on",
> @@ -3813,90 +2138,6 @@ static const struct i915_power_well_desc
> icl_power_wells[] = {
> },
> };
>
> -static void
> -tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
> -{
> - u8 tries = 0;
> - int ret;
> -
> - while (1) {
> - u32 low_val;
> - u32 high_val = 0;
> -
> - if (block)
> - low_val =
> TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ;
> - else
> - low_val =
> TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ;
> -
> - /*
> - * Spec states that we should timeout the request after
> 200us
> - * but the function below will timeout after 500us
> - */
> - ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val,
> &high_val);
> - if (ret == 0) {
> - if (block &&
> - (low_val &
> TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
> - ret = -EIO;
> - else
> - break;
> - }
> -
> - if (++tries == 3)
> - break;
> -
> - msleep(1);
> - }
> -
> - if (ret)
> - drm_err(&i915->drm, "TC cold %sblock failed\n",
> - block ? "" : "un");
> - else
> - drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n",
> - block ? "" : "un");
> -}
> -
> -static void
> -tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915,
> - struct i915_power_well *power_well)
> -{
> - tgl_tc_cold_request(i915, true);
> -}
> -
> -static void
> -tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915,
> - struct i915_power_well *power_well)
> -{
> - tgl_tc_cold_request(i915, false);
> -}
> -
> -static void
> -tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
> - struct i915_power_well *power_well)
> -{
> - if (intel_power_well_refcount(power_well) > 0)
> - tgl_tc_cold_off_power_well_enable(i915, power_well);
> - else
> - tgl_tc_cold_off_power_well_disable(i915, power_well);
> -}
> -
> -static bool
> -tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private
> *dev_priv,
> - struct i915_power_well
> *power_well)
> -{
> - /*
> - * Not the correctly implementation but there is no way to just
> read it
> - * from PCODE, so returning count to avoid state mismatch
> errors
> - */
> - return intel_power_well_refcount(power_well);
> -}
> -
> -static const struct i915_power_well_ops tgl_tc_cold_off_ops = {
> - .sync_hw = tgl_tc_cold_off_power_well_sync_hw,
> - .enable = tgl_tc_cold_off_power_well_enable,
> - .disable = tgl_tc_cold_off_power_well_disable,
> - .is_enabled = tgl_tc_cold_off_power_well_is_enabled,
> -};
> -
> static const struct i915_power_well_desc tgl_power_wells[] = {
> {
> .name = "always-on",
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h
> b/drivers/gpu/drm/i915/display/intel_display_power.h
> index ced384b0a1658..95b9391499109 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.h
> @@ -305,9 +305,4 @@ void gen9_dbuf_slices_update(struct
> drm_i915_private *dev_priv,
> for ((wf) = intel_display_power_get_if_enabled((i915),
> (domain)); (wf); \
> intel_display_power_put_async((i915), (domain), (wf)),
> (wf) = 0)
>
> -void chv_phy_powergate_lanes(struct intel_encoder *encoder,
> - bool override, unsigned int mask);
> -bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum
> dpio_phy phy,
> - enum dpio_channel ch, bool override);
> -
> #endif /* __INTEL_DISPLAY_POWER_H__ */
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> index 2a0fb9d9c60f2..a92bb807f1972 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
> @@ -4,7 +4,58 @@
> */
>
> #include "i915_drv.h"
> +#include "i915_irq.h"
> +#include "intel_combo_phy.h"
> +#include "intel_combo_phy_regs.h"
> +#include "intel_crt.h"
> +#include "intel_de.h"
> #include "intel_display_power_well.h"
> +#include "intel_display_types.h"
> +#include "intel_dpio_phy.h"
> +#include "intel_dpll.h"
> +#include "intel_hotplug.h"
> +#include "intel_pcode.h"
> +#include "intel_pm.h"
> +#include "intel_pps.h"
> +#include "intel_vga.h"
> +#include "intel_tc.h"
> +#include "vlv_sideband.h"
> +#include "vlv_sideband_reg.h"
> +
> +struct i915_power_well_regs {
> + i915_reg_t bios;
> + i915_reg_t driver;
> + i915_reg_t kvmr;
> + i915_reg_t debug;
> +};
> +
> +struct i915_power_well_ops {
> + const struct i915_power_well_regs *regs;
> + /*
> + * Synchronize the well's hw state to match the current sw
> state, for
> + * example enable/disable it based on the current refcount.
> Called
> + * during driver init and resume time, possibly after first
> calling
> + * the enable/disable handlers.
> + */
> + void (*sync_hw)(struct drm_i915_private *i915,
> + struct i915_power_well *power_well);
> + /*
> + * Enable the well and resources that depend on it (for example
> + * interrupts located on the well). Called after the 0->1
> refcount
> + * transition.
> + */
> + void (*enable)(struct drm_i915_private *i915,
> + struct i915_power_well *power_well);
> + /*
> + * Disable the well and resources that depend on it. Called
> after
> + * the 1->0 refcount transition.
> + */
> + void (*disable)(struct drm_i915_private *i915,
> + struct i915_power_well *power_well);
> + /* Returns the hw enabled state. */
> + bool (*is_enabled)(struct drm_i915_private *i915,
> + struct i915_power_well *power_well);
> +};
>
> struct i915_power_well *
> lookup_power_well(struct drm_i915_private *i915,
> @@ -111,3 +162,1769 @@ int intel_power_well_refcount(struct
> i915_power_well *power_well)
> {
> return power_well->count;
> }
> +
> +/*
> + * Starting with Haswell, we have a "Power Down Well" that can be
> turned off
> + * when not needed anymore. We have 4 registers that can request the
> power well
> + * to be enabled, and it will only be disabled if none of the
> registers is
> + * requesting it to be enabled.
> + */
> +static void hsw_power_well_post_enable(struct drm_i915_private
> *dev_priv,
> + u8 irq_pipe_mask, bool has_vga)
> +{
> + if (has_vga)
> + intel_vga_reset_io_mem(dev_priv);
> +
> + if (irq_pipe_mask)
> + gen8_irq_power_well_post_enable(dev_priv,
> irq_pipe_mask);
> +}
> +
> +static void hsw_power_well_pre_disable(struct drm_i915_private
> *dev_priv,
> + u8 irq_pipe_mask)
> +{
> + if (irq_pipe_mask)
> + gen8_irq_power_well_pre_disable(dev_priv,
> irq_pipe_mask);
> +}
> +
> +#define ICL_AUX_PW_TO_CH(pw_idx) \
> + ((pw_idx) - ICL_PW_CTL_IDX_AUX_A + AUX_CH_A)
> +
> +#define ICL_TBT_AUX_PW_TO_CH(pw_idx) \
> + ((pw_idx) - ICL_PW_CTL_IDX_AUX_TBT1 + AUX_CH_C)
> +
> +static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well
> *power_well)
> +{
> + int pw_idx = power_well->desc->hsw.idx;
> +
> + return power_well->desc->hsw.is_tc_tbt ?
> ICL_TBT_AUX_PW_TO_CH(pw_idx) :
> + ICL_AUX_PW_TO_CH(pw_id
> x);
> +}
> +
> +static struct intel_digital_port *
> +aux_ch_to_digital_port(struct drm_i915_private *dev_priv,
> + enum aux_ch aux_ch)
> +{
> + struct intel_digital_port *dig_port = NULL;
> + struct intel_encoder *encoder;
> +
> + for_each_intel_encoder(&dev_priv->drm, encoder) {
> + /* We'll check the MST primary port */
> + if (encoder->type == INTEL_OUTPUT_DP_MST)
> + continue;
> +
> + dig_port = enc_to_dig_port(encoder);
> + if (!dig_port)
> + continue;
> +
> + if (dig_port->aux_ch != aux_ch) {
> + dig_port = NULL;
> + continue;
> + }
> +
> + break;
> + }
> +
> + return dig_port;
> +}
> +
> +static enum phy icl_aux_pw_to_phy(struct drm_i915_private *i915,
> + const struct i915_power_well
> *power_well)
> +{
> + enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
> + struct intel_digital_port *dig_port =
> aux_ch_to_digital_port(i915, aux_ch);
> +
> + return intel_port_to_phy(i915, dig_port->base.port);
> +}
> +
> +static void hsw_wait_for_power_well_enable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well,
> + bool timeout_expected)
> +{
> + const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> + int pw_idx = power_well->desc->hsw.idx;
> + int enable_delay = power_well->desc->hsw.fixed_enable_delay;
> +
> + /*
> + * For some power wells we're not supposed to watch the status
> bit for
> + * an ack, but rather just wait a fixed amount of time and then
> + * proceed. This is only used on DG2.
> + */
> + if (IS_DG2(dev_priv) && enable_delay) {
> + usleep_range(enable_delay, 2 * enable_delay);
> + return;
> + }
> +
> + /* Timeout for PW1:10 us, AUX:not specified, other PWs:20 us.
> */
> + if (intel_de_wait_for_set(dev_priv, regs->driver,
> + HSW_PWR_WELL_CTL_STATE(pw_idx), 1)) {
> + drm_dbg_kms(&dev_priv->drm, "%s power well enable
> timeout\n",
> + intel_power_well_name(power_well));
> +
> + drm_WARN_ON(&dev_priv->drm, !timeout_expected);
> +
> + }
> +}
> +
> +static u32 hsw_power_well_requesters(struct drm_i915_private
> *dev_priv,
> + const struct i915_power_well_regs
> *regs,
> + int pw_idx)
> +{
> + u32 req_mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
> + u32 ret;
> +
> + ret = intel_de_read(dev_priv, regs->bios) & req_mask ? 1 : 0;
> + ret |= intel_de_read(dev_priv, regs->driver) & req_mask ? 2 :
> 0;
> + if (regs->kvmr.reg)
> + ret |= intel_de_read(dev_priv, regs->kvmr) & req_mask ?
> 4 : 0;
> + ret |= intel_de_read(dev_priv, regs->debug) & req_mask ? 8 : 0;
> +
> + return ret;
> +}
> +
> +static void hsw_wait_for_power_well_disable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> + int pw_idx = power_well->desc->hsw.idx;
> + bool disabled;
> + u32 reqs;
> +
> + /*
> + * Bspec doesn't require waiting for PWs to get disabled, but
> still do
> + * this for paranoia. The known cases where a PW will be forced
> on:
> + * - a KVMR request on any power well via the KVMR request
> register
> + * - a DMC request on PW1 and MISC_IO power wells via the BIOS
> and
> + * DEBUG request registers
> + * Skip the wait in case any of the request bits are set and
> print a
> + * diagnostic message.
> + */
> + wait_for((disabled = !(intel_de_read(dev_priv, regs->driver) &
> + HSW_PWR_WELL_CTL_STATE(pw_idx))) ||
> + (reqs = hsw_power_well_requesters(dev_priv, regs,
> pw_idx)), 1);
> + if (disabled)
> + return;
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "%s forced on (bios:%d driver:%d kvmr:%d
> debug:%d)\n",
> + intel_power_well_name(power_well),
> + !!(reqs & 1), !!(reqs & 2), !!(reqs & 4), !!(reqs &
> 8));
> +}
> +
> +static void gen9_wait_for_power_well_fuses(struct drm_i915_private
> *dev_priv,
> + enum skl_power_gate pg)
> +{
> + /* Timeout 5us for PG#0, for other PGs 1us */
> + drm_WARN_ON(&dev_priv->drm,
> + intel_de_wait_for_set(dev_priv, SKL_FUSE_STATUS,
> + SKL_FUSE_PG_DIST_STATUS(pg),
> 1));
> +}
> +
> +static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> + int pw_idx = power_well->desc->hsw.idx;
> + u32 val;
> +
> + if (power_well->desc->hsw.has_fuses) {
> + enum skl_power_gate pg;
> +
> + pg = DISPLAY_VER(dev_priv) >= 11 ?
> ICL_PW_CTL_IDX_TO_PG(pw_idx) :
> + SKL_PW_CTL_IDX_TO_PG(p
> w_idx);
> +
> + /* Wa_16013190616:adlp */
> + if (IS_ALDERLAKE_P(dev_priv) && pg == SKL_PG1)
> + intel_de_rmw(dev_priv, GEN8_CHICKEN_DCPR_1, 0,
> DISABLE_FLR_SRC);
> +
> + /*
> + * For PW1 we have to wait both for the PW0/PG0 fuse
> state
> + * before enabling the power well and PW1/PG1's own
> fuse
> + * state after the enabling. For all other power wells
> with
> + * fuses we only have to wait for that PW/PG's fuse
> state
> + * after the enabling.
> + */
> + if (pg == SKL_PG1)
> + gen9_wait_for_power_well_fuses(dev_priv,
> SKL_PG0);
> + }
> +
> + val = intel_de_read(dev_priv, regs->driver);
> + intel_de_write(dev_priv, regs->driver,
> + val | HSW_PWR_WELL_CTL_REQ(pw_idx));
> +
> + hsw_wait_for_power_well_enable(dev_priv, power_well, false);
> +
> + if (power_well->desc->hsw.has_fuses) {
> + enum skl_power_gate pg;
> +
> + pg = DISPLAY_VER(dev_priv) >= 11 ?
> ICL_PW_CTL_IDX_TO_PG(pw_idx) :
> + SKL_PW_CTL_IDX_TO_PG(p
> w_idx);
> + gen9_wait_for_power_well_fuses(dev_priv, pg);
> + }
> +
> + hsw_power_well_post_enable(dev_priv,
> + power_well->desc->hsw.irq_pipe_mask,
> + power_well->desc->hsw.has_vga);
> +}
> +
> +static void hsw_power_well_disable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> + int pw_idx = power_well->desc->hsw.idx;
> + u32 val;
> +
> + hsw_power_well_pre_disable(dev_priv,
> + power_well->desc-
> >hsw.irq_pipe_mask);
> +
> + val = intel_de_read(dev_priv, regs->driver);
> + intel_de_write(dev_priv, regs->driver,
> + val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
> + hsw_wait_for_power_well_disable(dev_priv, power_well);
> +}
> +
> +static void
> +icl_combo_phy_aux_power_well_enable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> + int pw_idx = power_well->desc->hsw.idx;
> + enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
> + u32 val;
> +
> + drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
> +
> + val = intel_de_read(dev_priv, regs->driver);
> + intel_de_write(dev_priv, regs->driver,
> + val | HSW_PWR_WELL_CTL_REQ(pw_idx));
> +
> + if (DISPLAY_VER(dev_priv) < 12) {
> + val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
> + intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
> + val | ICL_LANE_ENABLE_AUX);
> + }
> +
> + hsw_wait_for_power_well_enable(dev_priv, power_well, false);
> +
> + /* Display WA #1178: icl */
> + if (pw_idx >= ICL_PW_CTL_IDX_AUX_A && pw_idx <=
> ICL_PW_CTL_IDX_AUX_B &&
> + !intel_bios_is_port_edp(dev_priv, (enum port)phy)) {
> + val = intel_de_read(dev_priv,
> ICL_AUX_ANAOVRD1(pw_idx));
> + val |= ICL_AUX_ANAOVRD1_ENABLE |
> ICL_AUX_ANAOVRD1_LDO_BYPASS;
> + intel_de_write(dev_priv, ICL_AUX_ANAOVRD1(pw_idx),
> val);
> + }
> +}
> +
> +static void
> +icl_combo_phy_aux_power_well_disable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> + int pw_idx = power_well->desc->hsw.idx;
> + enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
> + u32 val;
> +
> + drm_WARN_ON(&dev_priv->drm, !IS_ICELAKE(dev_priv));
> +
> + val = intel_de_read(dev_priv, ICL_PORT_CL_DW12(phy));
> + intel_de_write(dev_priv, ICL_PORT_CL_DW12(phy),
> + val & ~ICL_LANE_ENABLE_AUX);
> +
> + val = intel_de_read(dev_priv, regs->driver);
> + intel_de_write(dev_priv, regs->driver,
> + val & ~HSW_PWR_WELL_CTL_REQ(pw_idx));
> +
> + hsw_wait_for_power_well_disable(dev_priv, power_well);
> +}
> +
> +#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
> +
> +static void icl_tc_port_assert_ref_held(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well,
> + struct intel_digital_port
> *dig_port)
> +{
> + if (drm_WARN_ON(&dev_priv->drm, !dig_port))
> + return;
> +
> + if (DISPLAY_VER(dev_priv) == 11 &&
> intel_tc_cold_requires_aux_pw(dig_port))
> + return;
> +
> + drm_WARN_ON(&dev_priv->drm, !intel_tc_port_ref_held(dig_port));
> +}
> +
> +#else
> +
> +static void icl_tc_port_assert_ref_held(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well,
> + struct intel_digital_port
> *dig_port)
> +{
> +}
> +
> +#endif
> +
> +#define TGL_AUX_PW_TO_TC_PORT(pw_idx) ((pw_idx) -
> TGL_PW_CTL_IDX_AUX_TC1)
> +
> +static void icl_tc_cold_exit(struct drm_i915_private *i915)
> +{
> + int ret, tries = 0;
> +
> + while (1) {
> + ret = snb_pcode_write_timeout(i915,
> ICL_PCODE_EXIT_TCCOLD, 0,
> + 250, 1);
> + if (ret != -EAGAIN || ++tries == 3)
> + break;
> + msleep(1);
> + }
> +
> + /* Spec states that TC cold exit can take up to 1ms to complete
> */
> + if (!ret)
> + msleep(1);
> +
> + /* TODO: turn failure into a error as soon i915 CI updates ICL
> IFWI */
> + drm_dbg_kms(&i915->drm, "TC cold block %s\n", ret ? "failed" :
> + "succeeded");
> +}
> +
> +static void
> +icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
> + struct intel_digital_port *dig_port =
> aux_ch_to_digital_port(dev_priv, aux_ch);
> + const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> + bool is_tbt = power_well->desc->hsw.is_tc_tbt;
> + bool timeout_expected;
> + u32 val;
> +
> + icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
> +
> + val = intel_de_read(dev_priv, DP_AUX_CH_CTL(aux_ch));
> + val &= ~DP_AUX_CH_CTL_TBT_IO;
> + if (is_tbt)
> + val |= DP_AUX_CH_CTL_TBT_IO;
> + intel_de_write(dev_priv, DP_AUX_CH_CTL(aux_ch), val);
> +
> + val = intel_de_read(dev_priv, regs->driver);
> + intel_de_write(dev_priv, regs->driver,
> + val | HSW_PWR_WELL_CTL_REQ(power_well->desc-
> >hsw.idx));
> +
> + /*
> + * An AUX timeout is expected if the TBT DP tunnel is down,
> + * or need to enable AUX on a legacy TypeC port as part of the
> TC-cold
> + * exit sequence.
> + */
> + timeout_expected = is_tbt ||
> intel_tc_cold_requires_aux_pw(dig_port);
> + if (DISPLAY_VER(dev_priv) == 11 &&
> intel_tc_cold_requires_aux_pw(dig_port))
> + icl_tc_cold_exit(dev_priv);
> +
> + hsw_wait_for_power_well_enable(dev_priv, power_well,
> timeout_expected);
> +
> + if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) {
> + enum tc_port tc_port;
> +
> + tc_port = TGL_AUX_PW_TO_TC_PORT(power_well->desc-
> >hsw.idx);
> + intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
> + HIP_INDEX_VAL(tc_port, 0x2));
> +
> + if (intel_de_wait_for_set(dev_priv,
> DKL_CMN_UC_DW_27(tc_port),
> + DKL_CMN_UC_DW27_UC_HEALTH,
> 1))
> + drm_warn(&dev_priv->drm,
> + "Timeout waiting TC uC health\n");
> + }
> +}
> +
> +static void
> +icl_tc_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
> + struct intel_digital_port *dig_port =
> aux_ch_to_digital_port(dev_priv, aux_ch);
> +
> + icl_tc_port_assert_ref_held(dev_priv, power_well, dig_port);
> +
> + hsw_power_well_disable(dev_priv, power_well);
> +}
> +
> +static void
> +icl_aux_power_well_enable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
> +
> + if (intel_phy_is_tc(dev_priv, phy))
> + return icl_tc_phy_aux_power_well_enable(dev_priv,
> power_well);
> + else if (IS_ICELAKE(dev_priv))
> + return icl_combo_phy_aux_power_well_enable(dev_priv,
> + power_well);
> + else
> + return hsw_power_well_enable(dev_priv, power_well);
> +}
> +
> +static void
> +icl_aux_power_well_disable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
> +
> + if (intel_phy_is_tc(dev_priv, phy))
> + return icl_tc_phy_aux_power_well_disable(dev_priv,
> power_well);
> + else if (IS_ICELAKE(dev_priv))
> + return icl_combo_phy_aux_power_well_disable(dev_priv,
> + power_well)
> ;
> + else
> + return hsw_power_well_disable(dev_priv, power_well);
> +}
> +
> +/*
> + * We should only use the power well if we explicitly asked the
> hardware to
> + * enable it, so check if it's enabled and also check if we've
> requested it to
> + * be enabled.
> + */
> +static bool hsw_power_well_enabled(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> + enum i915_power_well_id id = power_well->desc->id;
> + int pw_idx = power_well->desc->hsw.idx;
> + u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
> + HSW_PWR_WELL_CTL_STATE(pw_idx);
> + u32 val;
> +
> + val = intel_de_read(dev_priv, regs->driver);
> +
> + /*
> + * On GEN9 big core due to a DMC bug the driver's request bits
> for PW1
> + * and the MISC_IO PW will be not restored, so check instead
> for the
> + * BIOS's own request bits, which are forced-on for these power
> wells
> + * when exiting DC5/6.
> + */
> + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv) &&
> + (id == SKL_DISP_PW_1 || id == SKL_DISP_PW_MISC_IO))
> + val |= intel_de_read(dev_priv, regs->bios);
> +
> + return (val & mask) == mask;
> +}
> +
> +static void assert_can_enable_dc9(struct drm_i915_private *dev_priv)
> +{
> + drm_WARN_ONCE(&dev_priv->drm,
> + (intel_de_read(dev_priv, DC_STATE_EN) &
> DC_STATE_EN_DC9),
> + "DC9 already programmed to be enabled.\n");
> + drm_WARN_ONCE(&dev_priv->drm,
> + intel_de_read(dev_priv, DC_STATE_EN) &
> + DC_STATE_EN_UPTO_DC5,
> + "DC5 still not disabled to enable DC9.\n");
> + drm_WARN_ONCE(&dev_priv->drm,
> + intel_de_read(dev_priv, HSW_PWR_WELL_CTL2) &
> + HSW_PWR_WELL_CTL_REQ(SKL_PW_CTL_IDX_PW_2),
> + "Power well 2 on.\n");
> + drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
> + "Interrupts not disabled yet.\n");
> +
> + /*
> + * TODO: check for the following to verify the conditions to
> enter DC9
> + * state are satisfied:
> + * 1] Check relevant display engine registers to verify if
> mode set
> + * disable sequence was followed.
> + * 2] Check if display uninitialize sequence is initialized.
> + */
> +}
> +
> +static void assert_can_disable_dc9(struct drm_i915_private
> *dev_priv)
> +{
> + drm_WARN_ONCE(&dev_priv->drm, intel_irqs_enabled(dev_priv),
> + "Interrupts not disabled yet.\n");
> + drm_WARN_ONCE(&dev_priv->drm,
> + intel_de_read(dev_priv, DC_STATE_EN) &
> + DC_STATE_EN_UPTO_DC5,
> + "DC5 still not disabled.\n");
> +
> + /*
> + * TODO: check for the following to verify DC9 state was
> indeed
> + * entered before programming to disable it:
> + * 1] Check relevant display engine registers to verify if
> mode
> + * set disable sequence was followed.
> + * 2] Check if display uninitialize sequence is initialized.
> + */
> +}
> +
> +static void gen9_write_dc_state(struct drm_i915_private *dev_priv,
> + u32 state)
> +{
> + int rewrites = 0;
> + int rereads = 0;
> + u32 v;
> +
> + intel_de_write(dev_priv, DC_STATE_EN, state);
> +
> + /* It has been observed that disabling the dc6 state sometimes
> + * doesn't stick and dmc keeps returning old value. Make sure
> + * the write really sticks enough times and also force rewrite
> until
> + * we are confident that state is exactly what we want.
> + */
> + do {
> + v = intel_de_read(dev_priv, DC_STATE_EN);
> +
> + if (v != state) {
> + intel_de_write(dev_priv, DC_STATE_EN, state);
> + rewrites++;
> + rereads = 0;
> + } else if (rereads++ > 5) {
> + break;
> + }
> +
> + } while (rewrites < 100);
> +
> + if (v != state)
> + drm_err(&dev_priv->drm,
> + "Writing dc state to 0x%x failed, now 0x%x\n",
> + state, v);
> +
> + /* Most of the times we need one retry, avoid spam */
> + if (rewrites > 1)
> + drm_dbg_kms(&dev_priv->drm,
> + "Rewrote dc state to 0x%x %d times\n",
> + state, rewrites);
> +}
> +
> +static u32 gen9_dc_mask(struct drm_i915_private *dev_priv)
> +{
> + u32 mask;
> +
> + mask = DC_STATE_EN_UPTO_DC5;
> +
> + if (DISPLAY_VER(dev_priv) >= 12)
> + mask |= DC_STATE_EN_DC3CO | DC_STATE_EN_UPTO_DC6
> + | DC_STATE_EN_DC9;
> + else if (DISPLAY_VER(dev_priv) == 11)
> + mask |= DC_STATE_EN_UPTO_DC6 | DC_STATE_EN_DC9;
> + else if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> + mask |= DC_STATE_EN_DC9;
> + else
> + mask |= DC_STATE_EN_UPTO_DC6;
> +
> + return mask;
> +}
> +
> +void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv)
> +{
> + u32 val;
> +
> + if (!HAS_DISPLAY(dev_priv))
> + return;
> +
> + val = intel_de_read(dev_priv, DC_STATE_EN) &
> gen9_dc_mask(dev_priv);
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "Resetting DC state tracking from %02x to %02x\n",
> + dev_priv->dmc.dc_state, val);
> + dev_priv->dmc.dc_state = val;
> +}
> +
> +/**
> + * gen9_set_dc_state - set target display C power state
> + * @dev_priv: i915 device instance
> + * @state: target DC power state
> + * - DC_STATE_DISABLE
> + * - DC_STATE_EN_UPTO_DC5
> + * - DC_STATE_EN_UPTO_DC6
> + * - DC_STATE_EN_DC9
> + *
> + * Signal to DMC firmware/HW the target DC power state passed in
> @state.
> + * DMC/HW can turn off individual display clocks and power rails
> when entering
> + * a deeper DC power state (higher in number) and turns these back
> when exiting
> + * that state to a shallower power state (lower in number). The HW
> will decide
> + * when to actually enter a given state on an on-demand basis, for
> instance
> + * depending on the active state of display pipes. The state of
> display
> + * registers backed by affected power rails are saved/restored as
> needed.
> + *
> + * Based on the above enabling a deeper DC power state is
> asynchronous wrt.
> + * enabling it. Disabling a deeper power state is synchronous: for
> instance
> + * setting %DC_STATE_DISABLE won't complete until all HW resources
> are turned
> + * back on and register state is restored. This is guaranteed by the
> MMIO write
> + * to DC_STATE_EN blocking until the state is restored.
> + */
> +void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32 state)
> +{
> + u32 val;
> + u32 mask;
> +
> + if (!HAS_DISPLAY(dev_priv))
> + return;
> +
> + if (drm_WARN_ON_ONCE(&dev_priv->drm,
> + state & ~dev_priv->dmc.allowed_dc_mask))
> + state &= dev_priv->dmc.allowed_dc_mask;
> +
> + val = intel_de_read(dev_priv, DC_STATE_EN);
> + mask = gen9_dc_mask(dev_priv);
> + drm_dbg_kms(&dev_priv->drm, "Setting DC state from %02x to
> %02x\n",
> + val & mask, state);
> +
> + /* Check if DMC is ignoring our DC state requests */
> + if ((val & mask) != dev_priv->dmc.dc_state)
> + drm_err(&dev_priv->drm, "DC state mismatch (0x%x ->
> 0x%x)\n",
> + dev_priv->dmc.dc_state, val & mask);
> +
> + val &= ~mask;
> + val |= state;
> +
> + gen9_write_dc_state(dev_priv, val);
> +
> + dev_priv->dmc.dc_state = val & mask;
> +}
> +
> +static void tgl_enable_dc3co(struct drm_i915_private *dev_priv)
> +{
> + drm_dbg_kms(&dev_priv->drm, "Enabling DC3CO\n");
> + gen9_set_dc_state(dev_priv, DC_STATE_EN_DC3CO);
> +}
> +
> +static void tgl_disable_dc3co(struct drm_i915_private *dev_priv)
> +{
> + u32 val;
> +
> + drm_dbg_kms(&dev_priv->drm, "Disabling DC3CO\n");
> + val = intel_de_read(dev_priv, DC_STATE_EN);
> + val &= ~DC_STATE_DC3CO_STATUS;
> + intel_de_write(dev_priv, DC_STATE_EN, val);
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> + /*
> + * Delay of 200us DC3CO Exit time B.Spec 49196
> + */
> + usleep_range(200, 210);
> +}
> +
> +static void assert_dmc_loaded(struct drm_i915_private *dev_priv)
> +{
> + drm_WARN_ONCE(&dev_priv->drm,
> + !intel_de_read(dev_priv,
> + DMC_PROGRAM(dev_priv-
> >dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
> + "DMC program storage start is
> NULL\n");
> + drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv,
> DMC_SSP_BASE),
> + "DMC SSP Base Not fine\n");
> + drm_WARN_ONCE(&dev_priv->drm, !intel_de_read(dev_priv,
> DMC_HTP_SKL),
> + "DMC HTP Not fine\n");
> +}
> +
> +static void assert_can_enable_dc5(struct drm_i915_private *dev_priv)
> +{
> + enum i915_power_well_id high_pg;
> +
> + /* Power wells at this level and above must be disabled for DC5
> entry */
> + if (DISPLAY_VER(dev_priv) == 12)
> + high_pg = ICL_DISP_PW_3;
> + else
> + high_pg = SKL_DISP_PW_2;
> +
> + drm_WARN_ONCE(&dev_priv->drm,
> + intel_display_power_well_is_enabled(dev_priv,
> high_pg),
> + "Power wells above platform's DC5 limit still
> enabled.\n");
> +
> + drm_WARN_ONCE(&dev_priv->drm,
> + (intel_de_read(dev_priv, DC_STATE_EN) &
> + DC_STATE_EN_UPTO_DC5),
> + "DC5 already programmed to be enabled.\n");
> + assert_rpm_wakelock_held(&dev_priv->runtime_pm);
> +
> + assert_dmc_loaded(dev_priv);
> +}
> +
> +void gen9_enable_dc5(struct drm_i915_private *dev_priv)
> +{
> + assert_can_enable_dc5(dev_priv);
> +
> + drm_dbg_kms(&dev_priv->drm, "Enabling DC5\n");
> +
> + /* Wa Display #1183: skl,kbl,cfl */
> + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
> + intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
> + intel_de_read(dev_priv,
> GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
> +
> + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC5);
> +}
> +
> +static void assert_can_enable_dc6(struct drm_i915_private *dev_priv)
> +{
> + drm_WARN_ONCE(&dev_priv->drm,
> + intel_de_read(dev_priv, UTIL_PIN_CTL) &
> UTIL_PIN_ENABLE,
> + "Backlight is not disabled.\n");
> + drm_WARN_ONCE(&dev_priv->drm,
> + (intel_de_read(dev_priv, DC_STATE_EN) &
> + DC_STATE_EN_UPTO_DC6),
> + "DC6 already programmed to be enabled.\n");
> +
> + assert_dmc_loaded(dev_priv);
> +}
> +
> +void skl_enable_dc6(struct drm_i915_private *dev_priv)
> +{
> + assert_can_enable_dc6(dev_priv);
> +
> + drm_dbg_kms(&dev_priv->drm, "Enabling DC6\n");
> +
> + /* Wa Display #1183: skl,kbl,cfl */
> + if (DISPLAY_VER(dev_priv) == 9 && !IS_BROXTON(dev_priv))
> + intel_de_write(dev_priv, GEN8_CHICKEN_DCPR_1,
> + intel_de_read(dev_priv,
> GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
> +
> + gen9_set_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
> +}
> +
> +void bxt_enable_dc9(struct drm_i915_private *dev_priv)
> +{
> + assert_can_enable_dc9(dev_priv);
> +
> + drm_dbg_kms(&dev_priv->drm, "Enabling DC9\n");
> + /*
> + * Power sequencer reset is not needed on
> + * platforms with South Display Engine on PCH,
> + * because PPS registers are always on.
> + */
> + if (!HAS_PCH_SPLIT(dev_priv))
> + intel_pps_reset_all(dev_priv);
> + gen9_set_dc_state(dev_priv, DC_STATE_EN_DC9);
> +}
> +
> +void bxt_disable_dc9(struct drm_i915_private *dev_priv)
> +{
> + assert_can_disable_dc9(dev_priv);
> +
> + drm_dbg_kms(&dev_priv->drm, "Disabling DC9\n");
> +
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +
> + intel_pps_unlock_regs_wa(dev_priv);
> +}
> +
> +static void hsw_power_well_sync_hw(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + const struct i915_power_well_regs *regs = power_well->desc-
> >ops->regs;
> + int pw_idx = power_well->desc->hsw.idx;
> + u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
> + u32 bios_req = intel_de_read(dev_priv, regs->bios);
> +
> + /* Take over the request bit if set by BIOS. */
> + if (bios_req & mask) {
> + u32 drv_req = intel_de_read(dev_priv, regs->driver);
> +
> + if (!(drv_req & mask))
> + intel_de_write(dev_priv, regs->driver, drv_req
> | mask);
> + intel_de_write(dev_priv, regs->bios, bios_req & ~mask);
> + }
> +}
> +
> +static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy);
> +}
> +
> +static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy);
> +}
> +
> +static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc-
> >bxt.phy);
> +}
> +
> +static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private
> *dev_priv)
> +{
> + struct i915_power_well *power_well;
> +
> + power_well = lookup_power_well(dev_priv,
> BXT_DISP_PW_DPIO_CMN_A);
> + if (intel_power_well_refcount(power_well) > 0)
> + bxt_ddi_phy_verify_state(dev_priv, power_well->desc-
> >bxt.phy);
> +
> + power_well = lookup_power_well(dev_priv,
> VLV_DISP_PW_DPIO_CMN_BC);
> + if (intel_power_well_refcount(power_well) > 0)
> + bxt_ddi_phy_verify_state(dev_priv, power_well->desc-
> >bxt.phy);
> +
> + if (IS_GEMINILAKE(dev_priv)) {
> + power_well = lookup_power_well(dev_priv,
> + GLK_DISP_PW_DPIO_CMN_C);
> + if (intel_power_well_refcount(power_well) > 0)
> + bxt_ddi_phy_verify_state(dev_priv,
> + power_well->desc-
> >bxt.phy);
> + }
> +}
> +
> +static bool gen9_dc_off_power_well_enabled(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + return ((intel_de_read(dev_priv, DC_STATE_EN) &
> DC_STATE_EN_DC3CO) == 0 &&
> + (intel_de_read(dev_priv, DC_STATE_EN) &
> DC_STATE_EN_UPTO_DC5_DC6_MASK) == 0);
> +}
> +
> +static void gen9_assert_dbuf_enabled(struct drm_i915_private
> *dev_priv)
> +{
> + u8 hw_enabled_dbuf_slices =
> intel_enabled_dbuf_slices_mask(dev_priv);
> + u8 enabled_dbuf_slices = dev_priv->dbuf.enabled_slices;
> +
> + drm_WARN(&dev_priv->drm,
> + hw_enabled_dbuf_slices != enabled_dbuf_slices,
> + "Unexpected DBuf power power state (0x%08x, expected
> 0x%08x)\n",
> + hw_enabled_dbuf_slices,
> + enabled_dbuf_slices);
> +}
> +
> +void gen9_disable_dc_states(struct drm_i915_private *dev_priv)
> +{
> + struct intel_cdclk_config cdclk_config = {};
> +
> + if (dev_priv->dmc.target_dc_state == DC_STATE_EN_DC3CO) {
> + tgl_disable_dc3co(dev_priv);
> + return;
> + }
> +
> + gen9_set_dc_state(dev_priv, DC_STATE_DISABLE);
> +
> + if (!HAS_DISPLAY(dev_priv))
> + return;
> +
> + intel_cdclk_get_cdclk(dev_priv, &cdclk_config);
> + /* Can't read out voltage_level so can't use
> intel_cdclk_changed() */
> + drm_WARN_ON(&dev_priv->drm,
> + intel_cdclk_needs_modeset(&dev_priv->cdclk.hw,
> + &cdclk_config));
> +
> + gen9_assert_dbuf_enabled(dev_priv);
> +
> + if (IS_GEMINILAKE(dev_priv) || IS_BROXTON(dev_priv))
> + bxt_verify_ddi_phy_power_wells(dev_priv);
> +
> + if (DISPLAY_VER(dev_priv) >= 11)
> + /*
> + * DMC retains HW context only for port A, the other
> combo
> + * PHY's HW context for port B is lost after DC
> transitions,
> + * so we need to restore it manually.
> + */
> + intel_combo_phy_init(dev_priv);
> +}
> +
> +static void gen9_dc_off_power_well_enable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + gen9_disable_dc_states(dev_priv);
> +}
> +
> +static void gen9_dc_off_power_well_disable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + if (!intel_dmc_has_payload(dev_priv))
> + return;
> +
> + switch (dev_priv->dmc.target_dc_state) {
> + case DC_STATE_EN_DC3CO:
> + tgl_enable_dc3co(dev_priv);
> + break;
> + case DC_STATE_EN_UPTO_DC6:
> + skl_enable_dc6(dev_priv);
> + break;
> + case DC_STATE_EN_UPTO_DC5:
> + gen9_enable_dc5(dev_priv);
> + break;
> + }
> +}
> +
> +static void i9xx_power_well_sync_hw_noop(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> +}
> +
> +static void i9xx_always_on_power_well_noop(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> +}
> +
> +static bool i9xx_always_on_power_well_enabled(struct
> drm_i915_private *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + return true;
> +}
> +
> +static void i830_pipes_power_well_enable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + if ((intel_de_read(dev_priv, PIPECONF(PIPE_A)) &
> PIPECONF_ENABLE) == 0)
> + i830_enable_pipe(dev_priv, PIPE_A);
> + if ((intel_de_read(dev_priv, PIPECONF(PIPE_B)) &
> PIPECONF_ENABLE) == 0)
> + i830_enable_pipe(dev_priv, PIPE_B);
> +}
> +
> +static void i830_pipes_power_well_disable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + i830_disable_pipe(dev_priv, PIPE_B);
> + i830_disable_pipe(dev_priv, PIPE_A);
> +}
> +
> +static bool i830_pipes_power_well_enabled(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + return intel_de_read(dev_priv, PIPECONF(PIPE_A)) &
> PIPECONF_ENABLE &&
> + intel_de_read(dev_priv, PIPECONF(PIPE_B)) &
> PIPECONF_ENABLE;
> +}
> +
> +static void i830_pipes_power_well_sync_hw(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + if (intel_power_well_refcount(power_well) > 0)
> + i830_pipes_power_well_enable(dev_priv, power_well);
> + else
> + i830_pipes_power_well_disable(dev_priv, power_well);
> +}
> +
> +static void vlv_set_power_well(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well, bool
> enable)
> +{
> + int pw_idx = power_well->desc->vlv.idx;
> + u32 mask;
> + u32 state;
> + u32 ctrl;
> +
> + mask = PUNIT_PWRGT_MASK(pw_idx);
> + state = enable ? PUNIT_PWRGT_PWR_ON(pw_idx) :
> + PUNIT_PWRGT_PWR_GATE(pw_idx);
> +
> + vlv_punit_get(dev_priv);
> +
> +#define COND \
> + ((vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) & mask) ==
> state)
> +
> + if (COND)
> + goto out;
> +
> + ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL);
> + ctrl &= ~mask;
> + ctrl |= state;
> + vlv_punit_write(dev_priv, PUNIT_REG_PWRGT_CTRL, ctrl);
> +
> + if (wait_for(COND, 100))
> + drm_err(&dev_priv->drm,
> + "timeout setting power well state %08x
> (%08x)\n",
> + state,
> + vlv_punit_read(dev_priv,
> PUNIT_REG_PWRGT_CTRL));
> +
> +#undef COND
> +
> +out:
> + vlv_punit_put(dev_priv);
> +}
> +
> +static void vlv_power_well_enable(struct drm_i915_private *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + vlv_set_power_well(dev_priv, power_well, true);
> +}
> +
> +static void vlv_power_well_disable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + vlv_set_power_well(dev_priv, power_well, false);
> +}
> +
> +static bool vlv_power_well_enabled(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well *power_well)
> +{
> + int pw_idx = power_well->desc->vlv.idx;
> + bool enabled = false;
> + u32 mask;
> + u32 state;
> + u32 ctrl;
> +
> + mask = PUNIT_PWRGT_MASK(pw_idx);
> + ctrl = PUNIT_PWRGT_PWR_ON(pw_idx);
> +
> + vlv_punit_get(dev_priv);
> +
> + state = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_STATUS) &
> mask;
> + /*
> + * We only ever set the power-on and power-gate states,
> anything
> + * else is unexpected.
> + */
> + drm_WARN_ON(&dev_priv->drm, state != PUNIT_PWRGT_PWR_ON(pw_idx)
> &&
> + state != PUNIT_PWRGT_PWR_GATE(pw_idx));
> + if (state == ctrl)
> + enabled = true;
> +
> + /*
> + * A transient state at this point would mean some unexpected
> party
> + * is poking at the power controls too.
> + */
> + ctrl = vlv_punit_read(dev_priv, PUNIT_REG_PWRGT_CTRL) & mask;
> + drm_WARN_ON(&dev_priv->drm, ctrl != state);
> +
> + vlv_punit_put(dev_priv);
> +
> + return enabled;
> +}
> +
> +static void vlv_init_display_clock_gating(struct drm_i915_private
> *dev_priv)
> +{
> + u32 val;
> +
> + /*
> + * On driver load, a pipe may be active and driving a DSI
> display.
> + * Preserve DPOUNIT_CLOCK_GATE_DISABLE to avoid the pipe
> getting stuck
> + * (and never recovering) in this case.
> intel_dsi_post_disable() will
> + * clear it when we turn off the display.
> + */
> + val = intel_de_read(dev_priv, DSPCLK_GATE_D);
> + val &= DPOUNIT_CLOCK_GATE_DISABLE;
> + val |= VRHUNIT_CLOCK_GATE_DISABLE;
> + intel_de_write(dev_priv, DSPCLK_GATE_D, val);
> +
> + /*
> + * Disable trickle feed and enable pnd deadline calculation
> + */
> + intel_de_write(dev_priv, MI_ARB_VLV,
> + MI_ARB_DISPLAY_TRICKLE_FEED_DISABLE);
> + intel_de_write(dev_priv, CBR1_VLV, 0);
> +
> + drm_WARN_ON(&dev_priv->drm, RUNTIME_INFO(dev_priv)->rawclk_freq
> == 0);
> + intel_de_write(dev_priv, RAWCLK_FREQ_VLV,
> + DIV_ROUND_CLOSEST(RUNTIME_INFO(dev_priv)-
> >rawclk_freq,
> + 1000));
> +}
> +
> +static void vlv_display_power_well_init(struct drm_i915_private
> *dev_priv)
> +{
> + struct intel_encoder *encoder;
> + enum pipe pipe;
> +
> + /*
> + * Enable the CRI clock source so we can get at the
> + * display and the reference clock for VGA
> + * hotplug / manual detection. Supposedly DSI also
> + * needs the ref clock up and running.
> + *
> + * CHV DPLL B/C have some issues if VGA mode is enabled.
> + */
> + for_each_pipe(dev_priv, pipe) {
> + u32 val = intel_de_read(dev_priv, DPLL(pipe));
> +
> + val |= DPLL_REF_CLK_ENABLE_VLV | DPLL_VGA_MODE_DIS;
> + if (pipe != PIPE_A)
> + val |= DPLL_INTEGRATED_CRI_CLK_VLV;
> +
> + intel_de_write(dev_priv, DPLL(pipe), val);
> + }
> +
> + vlv_init_display_clock_gating(dev_priv);
> +
> + spin_lock_irq(&dev_priv->irq_lock);
> + valleyview_enable_display_irqs(dev_priv);
> + spin_unlock_irq(&dev_priv->irq_lock);
> +
> + /*
> + * During driver initialization/resume we can avoid restoring
> the
> + * part of the HW/SW state that will be inited anyway
> explicitly.
> + */
> + if (dev_priv->power_domains.initializing)
> + return;
> +
> + intel_hpd_init(dev_priv);
> + intel_hpd_poll_disable(dev_priv);
> +
> + /* Re-enable the ADPA, if we have one */
> + for_each_intel_encoder(&dev_priv->drm, encoder) {
> + if (encoder->type == INTEL_OUTPUT_ANALOG)
> + intel_crt_reset(&encoder->base);
> + }
> +
> + intel_vga_redisable_power_on(dev_priv);
> +
> + intel_pps_unlock_regs_wa(dev_priv);
> +}
> +
> +static void vlv_display_power_well_deinit(struct drm_i915_private
> *dev_priv)
> +{
> + spin_lock_irq(&dev_priv->irq_lock);
> + valleyview_disable_display_irqs(dev_priv);
> + spin_unlock_irq(&dev_priv->irq_lock);
> +
> + /* make sure we're done processing display irqs */
> + intel_synchronize_irq(dev_priv);
> +
> + intel_pps_reset_all(dev_priv);
> +
> + /* Prevent us from re-enabling polling on accident in late
> suspend */
> + if (!dev_priv->drm.dev->power.is_suspended)
> + intel_hpd_poll_enable(dev_priv);
> +}
> +
> +static void vlv_display_power_well_enable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + vlv_set_power_well(dev_priv, power_well, true);
> +
> + vlv_display_power_well_init(dev_priv);
> +}
> +
> +static void vlv_display_power_well_disable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + vlv_display_power_well_deinit(dev_priv);
> +
> + vlv_set_power_well(dev_priv, power_well, false);
> +}
> +
> +static void vlv_dpio_cmn_power_well_enable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + /* since ref/cri clock was enabled */
> + udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
> +
> + vlv_set_power_well(dev_priv, power_well, true);
> +
> + /*
> + * From VLV2A0_DP_eDP_DPIO_driver_vbios_notes_10.docx -
> + * 6. De-assert cmn_reset/side_reset. Same as VLV X0.
> + * a. GUnit 0x2110 bit[0] set to 1 (def 0)
> + * b. The other bits such as sfr settings / modesel may all
> + * be set to 0.
> + *
> + * This should only be done on init and resume from S3 with
> + * both PLLs disabled, or we risk losing DPIO and PLL
> + * synchronization.
> + */
> + intel_de_write(dev_priv, DPIO_CTL,
> + intel_de_read(dev_priv, DPIO_CTL) |
> DPIO_CMNRST);
> +}
> +
> +static void vlv_dpio_cmn_power_well_disable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + enum pipe pipe;
> +
> + for_each_pipe(dev_priv, pipe)
> + assert_pll_disabled(dev_priv, pipe);
> +
> + /* Assert common reset */
> + intel_de_write(dev_priv, DPIO_CTL,
> + intel_de_read(dev_priv, DPIO_CTL) &
> ~DPIO_CMNRST);
> +
> + vlv_set_power_well(dev_priv, power_well, false);
> +}
> +
> +#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
> +
> +#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
> +
> +static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
> +{
> + struct i915_power_well *cmn_bc =
> + lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
> + struct i915_power_well *cmn_d =
> + lookup_power_well(dev_priv, CHV_DISP_PW_DPIO_CMN_D);
> + u32 phy_control = dev_priv->chv_phy_control;
> + u32 phy_status = 0;
> + u32 phy_status_mask = 0xffffffff;
> +
> + /*
> + * The BIOS can leave the PHY is some weird state
> + * where it doesn't fully power down some parts.
> + * Disable the asserts until the PHY has been fully
> + * reset (ie. the power well has been disabled at
> + * least once).
> + */
> + if (!dev_priv->chv_phy_assert[DPIO_PHY0])
> + phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY0,
> DPIO_CH0) |
> + PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH0, 0) |
> + PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH0, 1) |
> + PHY_STATUS_CMN_LDO(DPIO_PHY0,
> DPIO_CH1) |
> + PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH1, 0) |
> + PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH1, 1));
> +
> + if (!dev_priv->chv_phy_assert[DPIO_PHY1])
> + phy_status_mask &= ~(PHY_STATUS_CMN_LDO(DPIO_PHY1,
> DPIO_CH0) |
> + PHY_STATUS_SPLINE_LDO(DPIO_PHY1,
> DPIO_CH0, 0) |
> + PHY_STATUS_SPLINE_LDO(DPIO_PHY1,
> DPIO_CH0, 1));
> +
> + if (intel_power_well_is_enabled(dev_priv, cmn_bc)) {
> + phy_status |= PHY_POWERGOOD(DPIO_PHY0);
> +
> + /* this assumes override is only used to enable lanes
> */
> + if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0,
> DPIO_CH0)) == 0)
> + phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf,
> DPIO_PHY0, DPIO_CH0);
> +
> + if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY0,
> DPIO_CH1)) == 0)
> + phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf,
> DPIO_PHY0, DPIO_CH1);
> +
> + /* CL1 is on whenever anything is on in either channel
> */
> + if (BITS_SET(phy_control,
> + PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0,
> DPIO_CH0) |
> + PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0,
> DPIO_CH1)))
> + phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0,
> DPIO_CH0);
> +
> + /*
> + * The DPLLB check accounts for the pipe B + port A
> usage
> + * with CL2 powered up but all the lanes in the second
> channel
> + * powered down.
> + */
> + if (BITS_SET(phy_control,
> + PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY0,
> DPIO_CH1)) &&
> + (intel_de_read(dev_priv, DPLL(PIPE_B)) &
> DPLL_VCO_ENABLE) == 0)
> + phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY0,
> DPIO_CH1);
> +
> + if (BITS_SET(phy_control,
> + PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0,
> DPIO_CH0)))
> + phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH0, 0);
> + if (BITS_SET(phy_control,
> + PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0,
> DPIO_CH0)))
> + phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH0, 1);
> +
> + if (BITS_SET(phy_control,
> + PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY0,
> DPIO_CH1)))
> + phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH1, 0);
> + if (BITS_SET(phy_control,
> + PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY0,
> DPIO_CH1)))
> + phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY0,
> DPIO_CH1, 1);
> + }
> +
> + if (intel_power_well_is_enabled(dev_priv, cmn_d)) {
> + phy_status |= PHY_POWERGOOD(DPIO_PHY1);
> +
> + /* this assumes override is only used to enable lanes
> */
> + if ((phy_control & PHY_CH_POWER_DOWN_OVRD_EN(DPIO_PHY1,
> DPIO_CH0)) == 0)
> + phy_control |= PHY_CH_POWER_DOWN_OVRD(0xf,
> DPIO_PHY1, DPIO_CH0);
> +
> + if (BITS_SET(phy_control,
> + PHY_CH_POWER_DOWN_OVRD(0xf, DPIO_PHY1,
> DPIO_CH0)))
> + phy_status |= PHY_STATUS_CMN_LDO(DPIO_PHY1,
> DPIO_CH0);
> +
> + if (BITS_SET(phy_control,
> + PHY_CH_POWER_DOWN_OVRD(0x3, DPIO_PHY1,
> DPIO_CH0)))
> + phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1,
> DPIO_CH0, 0);
> + if (BITS_SET(phy_control,
> + PHY_CH_POWER_DOWN_OVRD(0xc, DPIO_PHY1,
> DPIO_CH0)))
> + phy_status |= PHY_STATUS_SPLINE_LDO(DPIO_PHY1,
> DPIO_CH0, 1);
> + }
> +
> + phy_status &= phy_status_mask;
> +
> + /*
> + * The PHY may be busy with some initial calibration and
> whatnot,
> + * so the power state can take a while to actually change.
> + */
> + if (intel_de_wait_for_register(dev_priv, DISPLAY_PHY_STATUS,
> + phy_status_mask, phy_status,
> 10))
> + drm_err(&dev_priv->drm,
> + "Unexpected PHY_STATUS 0x%08x, expected 0x%08x
> (PHY_CONTROL=0x%08x)\n",
> + intel_de_read(dev_priv, DISPLAY_PHY_STATUS) &
> phy_status_mask,
> + phy_status, dev_priv->chv_phy_control);
> +}
> +
> +#undef BITS_SET
> +
> +static void chv_dpio_cmn_power_well_enable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + enum dpio_phy phy;
> + enum pipe pipe;
> + u32 tmp;
> +
> + drm_WARN_ON_ONCE(&dev_priv->drm,
> + power_well->desc->id !=
> VLV_DISP_PW_DPIO_CMN_BC &&
> + power_well->desc->id !=
> CHV_DISP_PW_DPIO_CMN_D);
> +
> + if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
> + pipe = PIPE_A;
> + phy = DPIO_PHY0;
> + } else {
> + pipe = PIPE_C;
> + phy = DPIO_PHY1;
> + }
> +
> + /* since ref/cri clock was enabled */
> + udelay(1); /* >10ns for cmnreset, >0ns for sidereset */
> + vlv_set_power_well(dev_priv, power_well, true);
> +
> + /* Poll for phypwrgood signal */
> + if (intel_de_wait_for_set(dev_priv, DISPLAY_PHY_STATUS,
> + PHY_POWERGOOD(phy), 1))
> + drm_err(&dev_priv->drm, "Display PHY %d is not power
> up\n",
> + phy);
> +
> + vlv_dpio_get(dev_priv);
> +
> + /* Enable dynamic power down */
> + tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW28);
> + tmp |= DPIO_DYNPWRDOWNEN_CH0 | DPIO_CL1POWERDOWNEN |
> + DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
> + vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
> +
> + if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
> + tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
> + tmp |= DPIO_DYNPWRDOWNEN_CH1;
> + vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
> + } else {
> + /*
> + * Force the non-existing CL2 off. BXT does this
> + * too, so maybe it saves some power even though
> + * CL2 doesn't exist?
> + */
> + tmp = vlv_dpio_read(dev_priv, pipe, CHV_CMN_DW30);
> + tmp |= DPIO_CL2_LDOFUSE_PWRENB;
> + vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW30, tmp);
> + }
> +
> + vlv_dpio_put(dev_priv);
> +
> + dev_priv->chv_phy_control |= PHY_COM_LANE_RESET_DEASSERT(phy);
> + intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
> + dev_priv->chv_phy_control);
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "Enabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
> + phy, dev_priv->chv_phy_control);
> +
> + assert_chv_phy_status(dev_priv);
> +}
> +
> +static void chv_dpio_cmn_power_well_disable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + enum dpio_phy phy;
> +
> + drm_WARN_ON_ONCE(&dev_priv->drm,
> + power_well->desc->id !=
> VLV_DISP_PW_DPIO_CMN_BC &&
> + power_well->desc->id !=
> CHV_DISP_PW_DPIO_CMN_D);
> +
> + if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
> + phy = DPIO_PHY0;
> + assert_pll_disabled(dev_priv, PIPE_A);
> + assert_pll_disabled(dev_priv, PIPE_B);
> + } else {
> + phy = DPIO_PHY1;
> + assert_pll_disabled(dev_priv, PIPE_C);
> + }
> +
> + dev_priv->chv_phy_control &= ~PHY_COM_LANE_RESET_DEASSERT(phy);
> + intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
> + dev_priv->chv_phy_control);
> +
> + vlv_set_power_well(dev_priv, power_well, false);
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "Disabled DPIO PHY%d (PHY_CONTROL=0x%08x)\n",
> + phy, dev_priv->chv_phy_control);
> +
> + /* PHY is fully reset now, so we can enable the PHY state
> asserts */
> + dev_priv->chv_phy_assert[phy] = true;
> +
> + assert_chv_phy_status(dev_priv);
> +}
> +
> +static void assert_chv_phy_powergate(struct drm_i915_private
> *dev_priv, enum dpio_phy phy,
> + enum dpio_channel ch, bool
> override, unsigned int mask)
> +{
> + enum pipe pipe = phy == DPIO_PHY0 ? PIPE_A : PIPE_C;
> + u32 reg, val, expected, actual;
> +
> + /*
> + * The BIOS can leave the PHY is some weird state
> + * where it doesn't fully power down some parts.
> + * Disable the asserts until the PHY has been fully
> + * reset (ie. the power well has been disabled at
> + * least once).
> + */
> + if (!dev_priv->chv_phy_assert[phy])
> + return;
> +
> + if (ch == DPIO_CH0)
> + reg = _CHV_CMN_DW0_CH0;
> + else
> + reg = _CHV_CMN_DW6_CH1;
> +
> + vlv_dpio_get(dev_priv);
> + val = vlv_dpio_read(dev_priv, pipe, reg);
> + vlv_dpio_put(dev_priv);
> +
> + /*
> + * This assumes !override is only used when the port is
> disabled.
> + * All lanes should power down even without the override when
> + * the port is disabled.
> + */
> + if (!override || mask == 0xf) {
> + expected = DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
> + /*
> + * If CH1 common lane is not active anymore
> + * (eg. for pipe B DPLL) the entire channel will
> + * shut down, which causes the common lane registers
> + * to read as 0. That means we can't actually check
> + * the lane power down status bits, but as the entire
> + * register reads as 0 it's a good indication that the
> + * channel is indeed entirely powered down.
> + */
> + if (ch == DPIO_CH1 && val == 0)
> + expected = 0;
> + } else if (mask != 0x0) {
> + expected = DPIO_ANYDL_POWERDOWN;
> + } else {
> + expected = 0;
> + }
> +
> + if (ch == DPIO_CH0)
> + actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH0;
> + else
> + actual = val >> DPIO_ANYDL_POWERDOWN_SHIFT_CH1;
> + actual &= DPIO_ALLDL_POWERDOWN | DPIO_ANYDL_POWERDOWN;
> +
> + drm_WARN(&dev_priv->drm, actual != expected,
> + "Unexpected DPIO lane power down: all %d, any %d.
> Expected: all %d, any %d. (0x%x = 0x%08x)\n",
> + !!(actual & DPIO_ALLDL_POWERDOWN),
> + !!(actual & DPIO_ANYDL_POWERDOWN),
> + !!(expected & DPIO_ALLDL_POWERDOWN),
> + !!(expected & DPIO_ANYDL_POWERDOWN),
> + reg, val);
> +}
> +
> +bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum
> dpio_phy phy,
> + enum dpio_channel ch, bool override)
> +{
> + struct i915_power_domains *power_domains = &dev_priv-
> >power_domains;
> + bool was_override;
> +
> + mutex_lock(&power_domains->lock);
> +
> + was_override = dev_priv->chv_phy_control &
> PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> +
> + if (override == was_override)
> + goto out;
> +
> + if (override)
> + dev_priv->chv_phy_control |=
> PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> + else
> + dev_priv->chv_phy_control &=
> ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> +
> + intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
> + dev_priv->chv_phy_control);
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "Power gating DPIO PHY%d CH%d
> (DPIO_PHY_CONTROL=0x%08x)\n",
> + phy, ch, dev_priv->chv_phy_control);
> +
> + assert_chv_phy_status(dev_priv);
> +
> +out:
> + mutex_unlock(&power_domains->lock);
> +
> + return was_override;
> +}
> +
> +void chv_phy_powergate_lanes(struct intel_encoder *encoder,
> + bool override, unsigned int mask)
> +{
> + struct drm_i915_private *dev_priv = to_i915(encoder->base.dev);
> + struct i915_power_domains *power_domains = &dev_priv-
> >power_domains;
> + enum dpio_phy phy =
> vlv_dig_port_to_phy(enc_to_dig_port(encoder));
> + enum dpio_channel ch =
> vlv_dig_port_to_channel(enc_to_dig_port(encoder));
> +
> + mutex_lock(&power_domains->lock);
> +
> + dev_priv->chv_phy_control &= ~PHY_CH_POWER_DOWN_OVRD(0xf, phy,
> ch);
> + dev_priv->chv_phy_control |= PHY_CH_POWER_DOWN_OVRD(mask, phy,
> ch);
> +
> + if (override)
> + dev_priv->chv_phy_control |=
> PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> + else
> + dev_priv->chv_phy_control &=
> ~PHY_CH_POWER_DOWN_OVRD_EN(phy, ch);
> +
> + intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
> + dev_priv->chv_phy_control);
> +
> + drm_dbg_kms(&dev_priv->drm,
> + "Power gating DPIO PHY%d CH%d lanes 0x%x
> (PHY_CONTROL=0x%08x)\n",
> + phy, ch, mask, dev_priv->chv_phy_control);
> +
> + assert_chv_phy_status(dev_priv);
> +
> + assert_chv_phy_powergate(dev_priv, phy, ch, override, mask);
> +
> + mutex_unlock(&power_domains->lock);
> +}
> +
> +static bool chv_pipe_power_well_enabled(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + enum pipe pipe = PIPE_A;
> + bool enabled;
> + u32 state, ctrl;
> +
> + vlv_punit_get(dev_priv);
> +
> + state = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
> DP_SSS_MASK(pipe);
> + /*
> + * We only ever set the power-on and power-gate states,
> anything
> + * else is unexpected.
> + */
> + drm_WARN_ON(&dev_priv->drm, state != DP_SSS_PWR_ON(pipe) &&
> + state != DP_SSS_PWR_GATE(pipe));
> + enabled = state == DP_SSS_PWR_ON(pipe);
> +
> + /*
> + * A transient state at this point would mean some unexpected
> party
> + * is poking at the power controls too.
> + */
> + ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
> DP_SSC_MASK(pipe);
> + drm_WARN_ON(&dev_priv->drm, ctrl << 16 != state);
> +
> + vlv_punit_put(dev_priv);
> +
> + return enabled;
> +}
> +
> +static void chv_set_pipe_power_well(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well *power_well,
> + bool enable)
> +{
> + enum pipe pipe = PIPE_A;
> + u32 state;
> + u32 ctrl;
> +
> + state = enable ? DP_SSS_PWR_ON(pipe) : DP_SSS_PWR_GATE(pipe);
> +
> + vlv_punit_get(dev_priv);
> +
> +#define COND \
> + ((vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM) &
> DP_SSS_MASK(pipe)) == state)
> +
> + if (COND)
> + goto out;
> +
> + ctrl = vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM);
> + ctrl &= ~DP_SSC_MASK(pipe);
> + ctrl |= enable ? DP_SSC_PWR_ON(pipe) : DP_SSC_PWR_GATE(pipe);
> + vlv_punit_write(dev_priv, PUNIT_REG_DSPSSPM, ctrl);
> +
> + if (wait_for(COND, 100))
> + drm_err(&dev_priv->drm,
> + "timeout setting power well state %08x
> (%08x)\n",
> + state,
> + vlv_punit_read(dev_priv, PUNIT_REG_DSPSSPM));
> +
> +#undef COND
> +
> +out:
> + vlv_punit_put(dev_priv);
> +}
> +
> +static void chv_pipe_power_well_sync_hw(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + intel_de_write(dev_priv, DISPLAY_PHY_CONTROL,
> + dev_priv->chv_phy_control);
> +}
> +
> +static void chv_pipe_power_well_enable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + chv_set_pipe_power_well(dev_priv, power_well, true);
> +
> + vlv_display_power_well_init(dev_priv);
> +}
> +
> +static void chv_pipe_power_well_disable(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + vlv_display_power_well_deinit(dev_priv);
> +
> + chv_set_pipe_power_well(dev_priv, power_well, false);
> +}
> +
> +static void
> +tgl_tc_cold_request(struct drm_i915_private *i915, bool block)
> +{
> + u8 tries = 0;
> + int ret;
> +
> + while (1) {
> + u32 low_val;
> + u32 high_val = 0;
> +
> + if (block)
> + low_val =
> TGL_PCODE_EXIT_TCCOLD_DATA_L_BLOCK_REQ;
> + else
> + low_val =
> TGL_PCODE_EXIT_TCCOLD_DATA_L_UNBLOCK_REQ;
> +
> + /*
> + * Spec states that we should timeout the request after
> 200us
> + * but the function below will timeout after 500us
> + */
> + ret = snb_pcode_read(i915, TGL_PCODE_TCCOLD, &low_val,
> &high_val);
> + if (ret == 0) {
> + if (block &&
> + (low_val &
> TGL_PCODE_EXIT_TCCOLD_DATA_L_EXIT_FAILED))
> + ret = -EIO;
> + else
> + break;
> + }
> +
> + if (++tries == 3)
> + break;
> +
> + msleep(1);
> + }
> +
> + if (ret)
> + drm_err(&i915->drm, "TC cold %sblock failed\n",
> + block ? "" : "un");
> + else
> + drm_dbg_kms(&i915->drm, "TC cold %sblock succeeded\n",
> + block ? "" : "un");
> +}
> +
> +static void
> +tgl_tc_cold_off_power_well_enable(struct drm_i915_private *i915,
> + struct i915_power_well *power_well)
> +{
> + tgl_tc_cold_request(i915, true);
> +}
> +
> +static void
> +tgl_tc_cold_off_power_well_disable(struct drm_i915_private *i915,
> + struct i915_power_well *power_well)
> +{
> + tgl_tc_cold_request(i915, false);
> +}
> +
> +static void
> +tgl_tc_cold_off_power_well_sync_hw(struct drm_i915_private *i915,
> + struct i915_power_well *power_well)
> +{
> + if (intel_power_well_refcount(power_well) > 0)
> + tgl_tc_cold_off_power_well_enable(i915, power_well);
> + else
> + tgl_tc_cold_off_power_well_disable(i915, power_well);
> +}
> +
> +static bool
> +tgl_tc_cold_off_power_well_is_enabled(struct drm_i915_private
> *dev_priv,
> + struct i915_power_well
> *power_well)
> +{
> + /*
> + * Not the correctly implementation but there is no way to just
> read it
> + * from PCODE, so returning count to avoid state mismatch
> errors
> + */
> + return intel_power_well_refcount(power_well);
> +}
> +
> +
> +const struct i915_power_well_ops i9xx_always_on_power_well_ops = {
> + .sync_hw = i9xx_power_well_sync_hw_noop,
> + .enable = i9xx_always_on_power_well_noop,
> + .disable = i9xx_always_on_power_well_noop,
> + .is_enabled = i9xx_always_on_power_well_enabled,
> +};
> +
> +const struct i915_power_well_ops chv_pipe_power_well_ops = {
> + .sync_hw = chv_pipe_power_well_sync_hw,
> + .enable = chv_pipe_power_well_enable,
> + .disable = chv_pipe_power_well_disable,
> + .is_enabled = chv_pipe_power_well_enabled,
> +};
> +
> +const struct i915_power_well_ops chv_dpio_cmn_power_well_ops = {
> + .sync_hw = i9xx_power_well_sync_hw_noop,
> + .enable = chv_dpio_cmn_power_well_enable,
> + .disable = chv_dpio_cmn_power_well_disable,
> + .is_enabled = vlv_power_well_enabled,
> +};
> +
> +const struct i915_power_well_ops i830_pipes_power_well_ops = {
> + .sync_hw = i830_pipes_power_well_sync_hw,
> + .enable = i830_pipes_power_well_enable,
> + .disable = i830_pipes_power_well_disable,
> + .is_enabled = i830_pipes_power_well_enabled,
> +};
> +
> +static const struct i915_power_well_regs hsw_power_well_regs = {
> + .bios = HSW_PWR_WELL_CTL1,
> + .driver = HSW_PWR_WELL_CTL2,
> + .kvmr = HSW_PWR_WELL_CTL3,
> + .debug = HSW_PWR_WELL_CTL4,
> +};
> +
> +const struct i915_power_well_ops hsw_power_well_ops = {
> + .regs = &hsw_power_well_regs,
> + .sync_hw = hsw_power_well_sync_hw,
> + .enable = hsw_power_well_enable,
> + .disable = hsw_power_well_disable,
> + .is_enabled = hsw_power_well_enabled,
> +};
> +
> +const struct i915_power_well_ops gen9_dc_off_power_well_ops = {
> + .sync_hw = i9xx_power_well_sync_hw_noop,
> + .enable = gen9_dc_off_power_well_enable,
> + .disable = gen9_dc_off_power_well_disable,
> + .is_enabled = gen9_dc_off_power_well_enabled,
> +};
> +
> +const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops = {
> + .sync_hw = i9xx_power_well_sync_hw_noop,
> + .enable = bxt_dpio_cmn_power_well_enable,
> + .disable = bxt_dpio_cmn_power_well_disable,
> + .is_enabled = bxt_dpio_cmn_power_well_enabled,
> +};
> +
> +const struct i915_power_well_ops vlv_display_power_well_ops = {
> + .sync_hw = i9xx_power_well_sync_hw_noop,
> + .enable = vlv_display_power_well_enable,
> + .disable = vlv_display_power_well_disable,
> + .is_enabled = vlv_power_well_enabled,
> +};
> +
> +const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops = {
> + .sync_hw = i9xx_power_well_sync_hw_noop,
> + .enable = vlv_dpio_cmn_power_well_enable,
> + .disable = vlv_dpio_cmn_power_well_disable,
> + .is_enabled = vlv_power_well_enabled,
> +};
> +
> +const struct i915_power_well_ops vlv_dpio_power_well_ops = {
> + .sync_hw = i9xx_power_well_sync_hw_noop,
> + .enable = vlv_power_well_enable,
> + .disable = vlv_power_well_disable,
> + .is_enabled = vlv_power_well_enabled,
> +};
> +
> +static const struct i915_power_well_regs icl_aux_power_well_regs = {
> + .bios = ICL_PWR_WELL_CTL_AUX1,
> + .driver = ICL_PWR_WELL_CTL_AUX2,
> + .debug = ICL_PWR_WELL_CTL_AUX4,
> +};
> +
> +const struct i915_power_well_ops icl_aux_power_well_ops = {
> + .regs = &icl_aux_power_well_regs,
> + .sync_hw = hsw_power_well_sync_hw,
> + .enable = icl_aux_power_well_enable,
> + .disable = icl_aux_power_well_disable,
> + .is_enabled = hsw_power_well_enabled,
> +};
> +
> +static const struct i915_power_well_regs icl_ddi_power_well_regs = {
> + .bios = ICL_PWR_WELL_CTL_DDI1,
> + .driver = ICL_PWR_WELL_CTL_DDI2,
> + .debug = ICL_PWR_WELL_CTL_DDI4,
> +};
> +
> +const struct i915_power_well_ops icl_ddi_power_well_ops = {
> + .regs = &icl_ddi_power_well_regs,
> + .sync_hw = hsw_power_well_sync_hw,
> + .enable = hsw_power_well_enable,
> + .disable = hsw_power_well_disable,
> + .is_enabled = hsw_power_well_enabled,
> +};
> +
> +const struct i915_power_well_ops tgl_tc_cold_off_ops = {
> + .sync_hw = tgl_tc_cold_off_power_well_sync_hw,
> + .enable = tgl_tc_cold_off_power_well_enable,
> + .disable = tgl_tc_cold_off_power_well_disable,
> + .is_enabled = tgl_tc_cold_off_power_well_is_enabled,
> +};
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> index 9a3756fdcf7fc..de3ee1bfb06d9 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
> @@ -36,41 +36,6 @@ enum i915_power_well_id {
> TGL_DISP_PW_TC_COLD_OFF,
> };
>
> -struct i915_power_well_regs {
> - i915_reg_t bios;
> - i915_reg_t driver;
> - i915_reg_t kvmr;
> - i915_reg_t debug;
> -};
> -
> -struct i915_power_well_ops {
> - const struct i915_power_well_regs *regs;
> - /*
> - * Synchronize the well's hw state to match the current sw
> state, for
> - * example enable/disable it based on the current refcount.
> Called
> - * during driver init and resume time, possibly after first
> calling
> - * the enable/disable handlers.
> - */
> - void (*sync_hw)(struct drm_i915_private *i915,
> - struct i915_power_well *power_well);
> - /*
> - * Enable the well and resources that depend on it (for example
> - * interrupts located on the well). Called after the 0->1
> refcount
> - * transition.
> - */
> - void (*enable)(struct drm_i915_private *i915,
> - struct i915_power_well *power_well);
> - /*
> - * Disable the well and resources that depend on it. Called
> after
> - * the 1->0 refcount transition.
> - */
> - void (*disable)(struct drm_i915_private *i915,
> - struct i915_power_well *power_well);
> - /* Returns the hw enabled state. */
> - bool (*is_enabled)(struct drm_i915_private *i915,
> - struct i915_power_well *power_well);
> -};
> -
> struct i915_power_well_desc {
> const char *name;
> bool always_on;
> @@ -150,4 +115,31 @@ const char *intel_power_well_name(struct
> i915_power_well *power_well);
> u64 intel_power_well_domains(struct i915_power_well *power_well);
> int intel_power_well_refcount(struct i915_power_well *power_well);
>
> +void chv_phy_powergate_lanes(struct intel_encoder *encoder,
> + bool override, unsigned int mask);
> +bool chv_phy_powergate_ch(struct drm_i915_private *dev_priv, enum
> dpio_phy phy,
> + enum dpio_channel ch, bool override);
> +
> +void gen9_enable_dc5(struct drm_i915_private *dev_priv);
> +void skl_enable_dc6(struct drm_i915_private *dev_priv);
> +void gen9_sanitize_dc_state(struct drm_i915_private *dev_priv);
> +void gen9_set_dc_state(struct drm_i915_private *dev_priv, u32
> state);
> +void gen9_disable_dc_states(struct drm_i915_private *dev_priv);
> +void bxt_enable_dc9(struct drm_i915_private *dev_priv);
> +void bxt_disable_dc9(struct drm_i915_private *dev_priv);
> +
> +extern const struct i915_power_well_ops
> i9xx_always_on_power_well_ops;
> +extern const struct i915_power_well_ops chv_pipe_power_well_ops;
> +extern const struct i915_power_well_ops chv_dpio_cmn_power_well_ops;
> +extern const struct i915_power_well_ops i830_pipes_power_well_ops;
> +extern const struct i915_power_well_ops hsw_power_well_ops;
> +extern const struct i915_power_well_ops gen9_dc_off_power_well_ops;
> +extern const struct i915_power_well_ops bxt_dpio_cmn_power_well_ops;
> +extern const struct i915_power_well_ops vlv_display_power_well_ops;
> +extern const struct i915_power_well_ops vlv_dpio_cmn_power_well_ops;
> +extern const struct i915_power_well_ops vlv_dpio_power_well_ops;
> +extern const struct i915_power_well_ops icl_aux_power_well_ops;
> +extern const struct i915_power_well_ops icl_ddi_power_well_ops;
> +extern const struct i915_power_well_ops tgl_tc_cold_off_ops;
> +
> #endif
> diff --git a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> index 44edeb2e55c0c..cc6abe761f5e3 100644
> --- a/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> +++ b/drivers/gpu/drm/i915/display/intel_dpio_phy.c
> @@ -24,6 +24,7 @@
> #include "intel_ddi.h"
> #include "intel_ddi_buf_trans.h"
> #include "intel_de.h"
> +#include "intel_display_power_well.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_dpio_phy.h"
> diff --git a/drivers/gpu/drm/i915/display/intel_pps.c
> b/drivers/gpu/drm/i915/display/intel_pps.c
> index 64bd4ca0edd47..5a598dd060391 100644
> --- a/drivers/gpu/drm/i915/display/intel_pps.c
> +++ b/drivers/gpu/drm/i915/display/intel_pps.c
> @@ -6,6 +6,7 @@
> #include "g4x_dp.h"
> #include "i915_drv.h"
> #include "intel_de.h"
> +#include "intel_display_power_well.h"
> #include "intel_display_types.h"
> #include "intel_dp.h"
> #include "intel_dpll.h"
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH v3 02/18] drm/i915: Unexport the for_each_power_well() macros
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 01/18] drm/i915: Move per-platform power well hooks to intel_display_power_well.c Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 03/18] drm/i915: Move the power domain->well mappings to intel_display_power_map.c Imre Deak
` (23 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
The for_each_power_well() macros are only used in intel_display_power.c
and intel_display_power_well.c, so unexport them.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
.../drm/i915/display/intel_display_power.c | 8 ++++++++
.../drm/i915/display/intel_display_power.h | 20 -------------------
.../i915/display/intel_display_power_well.h | 12 +++++++++++
3 files changed, 20 insertions(+), 20 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 35a5e36df8206..25b614bf09d83 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -21,6 +21,14 @@
#include "intel_snps_phy.h"
#include "vlv_sideband.h"
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
+ for_each_power_well(__dev_priv, __power_well) \
+ for_each_if((__power_well)->desc->domains & (__domain_mask))
+
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
+ for_each_power_well_reverse(__dev_priv, __power_well) \
+ for_each_if((__power_well)->desc->domains & (__domain_mask))
+
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain)
{
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 95b9391499109..e80317e7868b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -172,26 +172,6 @@ struct intel_display_power_domain_set {
for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
for_each_if(BIT_ULL(domain) & (mask))
-#define for_each_power_well(__dev_priv, __power_well) \
- for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
- (__power_well) - (__dev_priv)->power_domains.power_wells < \
- (__dev_priv)->power_domains.power_well_count; \
- (__power_well)++)
-
-#define for_each_power_well_reverse(__dev_priv, __power_well) \
- for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
- (__dev_priv)->power_domains.power_well_count - 1; \
- (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
- (__power_well)--)
-
-#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
- for_each_power_well(__dev_priv, __power_well) \
- for_each_if((__power_well)->desc->domains & (__domain_mask))
-
-#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
- for_each_power_well_reverse(__dev_priv, __power_well) \
- for_each_if((__power_well)->desc->domains & (__domain_mask))
-
int intel_power_domains_init(struct drm_i915_private *dev_priv);
void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
void intel_power_domains_init_hw(struct drm_i915_private *dev_priv, bool resume);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index de3ee1bfb06d9..c4a8a3d728e06 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -12,6 +12,18 @@
struct drm_i915_private;
struct i915_power_well;
+#define for_each_power_well(__dev_priv, __power_well) \
+ for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
+ (__power_well) - (__dev_priv)->power_domains.power_wells < \
+ (__dev_priv)->power_domains.power_well_count; \
+ (__power_well)++)
+
+#define for_each_power_well_reverse(__dev_priv, __power_well) \
+ for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
+ (__dev_priv)->power_domains.power_well_count - 1; \
+ (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
+ (__power_well)--)
+
/*
* i915_power_well_id:
*
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 03/18] drm/i915: Move the power domain->well mappings to intel_display_power_map.c
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 01/18] drm/i915: Move per-platform power well hooks to intel_display_power_well.c Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 02/18] drm/i915: Unexport the for_each_power_well() macros Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-31 7:14 ` Hogander, Jouni
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 04/18] drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield Imre Deak
` (22 subsequent siblings)
25 siblings, 1 reply; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
Move the list of platform specific power domain -> power well
definitions to intel_display_power_map.c. While at it group the
platforms' power domain macros with the corresponding power well lists
and keep all the power domain lists in the same order (matching the enum
order).
No functional changes.
v2:
- s/intel_display_power_internal.h/intel_display_power_map.h/ (Jani)
- Simplify intel_cleanup_power_wells().
- Don't move intel_display_power_domain_str().
v3:
- Rename intel_init/cleanup_power_wells() to
intel_display_power_map_init/cleanup().
- Add documentation to intel_display_power_map_init/cleanup().
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com> (v2)
---
drivers/gpu/drm/i915/Makefile | 1 +
.../drm/i915/display/intel_display_power.c | 2260 +----------------
.../i915/display/intel_display_power_map.c | 2150 ++++++++++++++++
.../i915/display/intel_display_power_map.h | 14 +
4 files changed, 2168 insertions(+), 2257 deletions(-)
create mode 100644 drivers/gpu/drm/i915/display/intel_display_power_map.c
create mode 100644 drivers/gpu/drm/i915/display/intel_display_power_map.h
diff --git a/drivers/gpu/drm/i915/Makefile b/drivers/gpu/drm/i915/Makefile
index c1d5540f60529..469ee62982b4b 100644
--- a/drivers/gpu/drm/i915/Makefile
+++ b/drivers/gpu/drm/i915/Makefile
@@ -216,6 +216,7 @@ i915-y += \
display/intel_cursor.o \
display/intel_display.o \
display/intel_display_power.o \
+ display/intel_display_power_map.o \
display/intel_display_power_well.o \
display/intel_dmc.o \
display/intel_dpio_phy.o \
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 25b614bf09d83..e999433589715 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -11,6 +11,7 @@
#include "intel_combo_phy.h"
#include "intel_de.h"
#include "intel_display_power.h"
+#include "intel_display_power_map.h"
#include "intel_display_power_well.h"
#include "intel_display_types.h"
#include "intel_dmc.h"
@@ -848,2169 +849,6 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
}
}
-#define I830_PIPES_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define CHV_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define HSW_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define BDW_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
-#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
-#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
-#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-/*
- * ICL PW_0/PG_0 domains (HW/DMC control):
- * - PCI
- * - clocks except port PLL
- * - central power except FBC
- * - shared functions except pipe interrupts, pipe MBUS, DBUF registers
- * ICL PW_1/PG_1 domains (HW/DMC control):
- * - DBUF function
- * - PIPE_A and its planes, except VGA
- * - transcoder EDP + PSR
- * - transcoder DSI
- * - DDI_A
- * - FBC
- */
-#define ICL_PW_4_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_INIT))
- /* VDSC/joining */
-#define ICL_PW_3_POWER_DOMAINS ( \
- ICL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_AUX_E) | \
- BIT_ULL(POWER_DOMAIN_AUX_F) | \
- BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
- /*
- * - transcoder WD
- * - KVMR (HW control)
- */
-#define ICL_PW_2_POWER_DOMAINS ( \
- ICL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
- /*
- * - KVMR (HW control)
- */
-#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- ICL_PW_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_DC_OFF) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define ICL_DDI_IO_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
-#define ICL_DDI_IO_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
-#define ICL_DDI_IO_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
-#define ICL_DDI_IO_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
-#define ICL_DDI_IO_E_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
-#define ICL_DDI_IO_F_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
-
-#define ICL_AUX_A_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_A))
-#define ICL_AUX_B_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_B))
-#define ICL_AUX_C_TC1_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_C))
-#define ICL_AUX_D_TC2_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_D))
-#define ICL_AUX_E_TC3_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_E))
-#define ICL_AUX_F_TC4_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_F))
-#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_C_TBT))
-#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
-#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
-#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
-
-#define TGL_PW_5_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_PW_4_POWER_DOMAINS ( \
- TGL_PW_5_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_PW_3_POWER_DOMAINS ( \
- TGL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_PW_2_POWER_DOMAINS ( \
- TGL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- TGL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define TGL_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
-#define TGL_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
-#define TGL_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
-#define TGL_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
-#define TGL_DDI_IO_TC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC5)
-#define TGL_DDI_IO_TC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC6)
-
-#define TGL_AUX_A_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_A))
-#define TGL_AUX_B_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_B))
-#define TGL_AUX_C_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_C))
-
-#define TGL_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
-#define TGL_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
-#define TGL_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
-#define TGL_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
-#define TGL_AUX_IO_USBC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC5)
-#define TGL_AUX_IO_USBC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC6)
-
-#define TGL_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
-#define TGL_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
-#define TGL_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
-#define TGL_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
-#define TGL_AUX_IO_TBT5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT5)
-#define TGL_AUX_IO_TBT6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT6)
-
-#define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
- BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
-
-#define RKL_PW_4_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define RKL_PW_3_POWER_DOMAINS ( \
- RKL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-/*
- * There is no PW_2/PG_2 on RKL.
- *
- * RKL PW_1/PG_1 domains (under HW/DMC control):
- * - DBUF function (note: registers are in PW0)
- * - PIPE_A and its planes and VDSC/joining, except VGA
- * - transcoder A
- * - DDI_A and DDI_B
- * - FBC
- *
- * RKL PW_0/PG_0 domains (under HW/DMC control):
- * - PCI
- * - clocks except port PLL
- * - shared functions:
- * * interrupts except pipe interrupts
- * * MBus except PIPE_MBUS_DBOX_CTL
- * * DBUF registers
- * - central power except FBC
- * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
- */
-
-#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- RKL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-/*
- * DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
- */
-#define DG1_PW_3_POWER_DOMAINS ( \
- TGL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define DG1_PW_2_POWER_DOMAINS ( \
- DG1_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- DG1_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-/*
- * XE_LPD Power Domains
- *
- * Previous platforms required that PG(n-1) be enabled before PG(n). That
- * dependency chain turns into a dependency tree on XE_LPD:
- *
- * PG0
- * |
- * --PG1--
- * / \
- * PGA --PG2--
- * / | \
- * PGB PGC PGD
- *
- * Power wells must be enabled from top to bottom and disabled from bottom
- * to top. This allows pipes to be power gated independently.
- */
-
-#define XELPD_PW_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_2_POWER_DOMAINS ( \
- XELPD_PW_B_POWER_DOMAINS | \
- XELPD_PW_C_POWER_DOMAINS | \
- XELPD_PW_D_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) | \
- BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-/*
- * XELPD PW_1/PG_1 domains (under HW/DMC control):
- * - DBUF function (registers are in PW0)
- * - Transcoder A
- * - DDI_A and DDI_B
- *
- * XELPD PW_0/PW_1 domains (under HW/DMC control):
- * - PCI
- * - Clocks except port PLL
- * - Shared functions:
- * * interrupts except pipe interrupts
- * * MBus except PIPE_MBUS_DBOX_CTL
- * * DBUF registers
- * - Central power except FBC
- * - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
- */
-
-#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- XELPD_PW_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
-#define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
-#define XELPD_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
-#define XELPD_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
-#define XELPD_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
-#define XELPD_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
-
-#define XELPD_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
-#define XELPD_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
-#define XELPD_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
-#define XELPD_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
-
-#define XELPD_DDI_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D_XELPD)
-#define XELPD_DDI_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E_XELPD)
-#define XELPD_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
-#define XELPD_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
-#define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
-#define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
-
-static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
-};
-
-static const struct i915_power_well_desc i830_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "pipes",
- .domains = I830_PIPES_POWER_DOMAINS,
- .ops = &i830_pipes_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
-};
-
-static const struct i915_power_well_desc hsw_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "display",
- .domains = HSW_DISPLAY_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = HSW_DISP_PW_GLOBAL,
- {
- .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
- .hsw.has_vga = true,
- },
- },
-};
-
-static const struct i915_power_well_desc bdw_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "display",
- .domains = BDW_DISPLAY_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = HSW_DISP_PW_GLOBAL,
- {
- .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- },
- },
-};
-
-static const struct i915_power_well_desc vlv_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "display",
- .domains = VLV_DISPLAY_POWER_DOMAINS,
- .ops = &vlv_display_power_well_ops,
- .id = VLV_DISP_PW_DISP2D,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
- },
- },
- {
- .name = "dpio-tx-b-01",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
- .ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
- },
- },
- {
- .name = "dpio-tx-b-23",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
- .ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
- },
- },
- {
- .name = "dpio-tx-c-01",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
- .ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
- },
- },
- {
- .name = "dpio-tx-c-23",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
- .ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
- },
- },
- {
- .name = "dpio-common",
- .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
- .ops = &vlv_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
- },
- },
-};
-
-static const struct i915_power_well_desc chv_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "display",
- /*
- * Pipe A power well is the new disp2d well. Pipe B and C
- * power wells don't actually exist. Pipe A power well is
- * required for any pipe to work.
- */
- .domains = CHV_DISPLAY_POWER_DOMAINS,
- .ops = &chv_pipe_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "dpio-common-bc",
- .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
- .ops = &chv_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
- },
- },
- {
- .name = "dpio-common-d",
- .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
- .ops = &chv_dpio_cmn_power_well_ops,
- .id = CHV_DISP_PW_DPIO_CMN_D,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
- },
- },
-};
-
-static const struct i915_power_well_desc skl_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "MISC IO power well",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_MISC_IO,
- {
- .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
- },
- },
- {
- .name = "DC off",
- .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_2,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DDI A/E IO power well",
- .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
- },
- },
- {
- .name = "DDI B IO power well",
- .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
- },
- },
- {
- .name = "DDI C IO power well",
- .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
- },
- },
- {
- .name = "DDI D IO power well",
- .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
- },
- },
-};
-
-static const struct i915_power_well_desc bxt_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DC off",
- .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_2,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "dpio-common-a",
- .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = BXT_DISP_PW_DPIO_CMN_A,
- {
- .bxt.phy = DPIO_PHY1,
- },
- },
- {
- .name = "dpio-common-bc",
- .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .bxt.phy = DPIO_PHY0,
- },
- },
-};
-
-static const struct i915_power_well_desc glk_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DC off",
- .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_2,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "dpio-common-a",
- .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = BXT_DISP_PW_DPIO_CMN_A,
- {
- .bxt.phy = DPIO_PHY1,
- },
- },
- {
- .name = "dpio-common-b",
- .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .bxt.phy = DPIO_PHY0,
- },
- },
- {
- .name = "dpio-common-c",
- .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = GLK_DISP_PW_DPIO_CMN_C,
- {
- .bxt.phy = DPIO_PHY2,
- },
- },
- {
- .name = "AUX A",
- .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
- },
- },
- {
- .name = "AUX B",
- .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
- },
- },
- {
- .name = "AUX C",
- .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
- },
- },
- {
- .name = "DDI A IO power well",
- .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
- },
- },
- {
- .name = "DDI B IO power well",
- .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
- },
- },
- {
- .name = "DDI C IO power well",
- .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
- },
- },
-};
-
-static const struct i915_power_well_desc icl_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DC off",
- .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = ICL_PW_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well 3",
- .domains = ICL_PW_3_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DDI A IO",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- },
- },
- {
- .name = "DDI B IO",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- },
- },
- {
- .name = "DDI C IO",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
- },
- },
- {
- .name = "DDI D IO",
- .domains = ICL_DDI_IO_D_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
- },
- },
- {
- .name = "DDI E IO",
- .domains = ICL_DDI_IO_E_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
- },
- },
- {
- .name = "DDI F IO",
- .domains = ICL_DDI_IO_F_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
- },
- },
- {
- .name = "AUX A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- },
- {
- .name = "AUX B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- },
- {
- .name = "AUX C TC1",
- .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX D TC2",
- .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX E TC3",
- .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX F TC4",
- .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX C TBT1",
- .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX D TBT2",
- .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX E TBT3",
- .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX F TBT4",
- .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "power well 4",
- .domains = ICL_PW_4_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
- },
- },
-};
-
-static const struct i915_power_well_desc tgl_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DC off",
- .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = TGL_PW_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well 3",
- .domains = TGL_PW_3_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DDI A IO",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
- },
- {
- .name = "DDI B IO",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- },
- {
- .name = "DDI C IO",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
- }
- },
- {
- .name = "DDI IO TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- },
- },
- {
- .name = "DDI IO TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- },
- },
- {
- .name = "DDI IO TC3",
- .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
- },
- },
- {
- .name = "DDI IO TC4",
- .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
- },
- },
- {
- .name = "DDI IO TC5",
- .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
- },
- },
- {
- .name = "DDI IO TC6",
- .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
- },
- },
- {
- .name = "TC cold off",
- .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
- .ops = &tgl_tc_cold_off_ops,
- .id = TGL_DISP_PW_TC_COLD_OFF,
- },
- {
- .name = "AUX A",
- .domains = TGL_AUX_A_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- },
- {
- .name = "AUX B",
- .domains = TGL_AUX_B_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- },
- {
- .name = "AUX C",
- .domains = TGL_AUX_C_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- },
- },
- {
- .name = "AUX USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX USBC3",
- .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX USBC4",
- .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX USBC5",
- .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX USBC6",
- .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX TBT1",
- .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT2",
- .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT3",
- .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT4",
- .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT5",
- .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT6",
- .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "power well 4",
- .domains = TGL_PW_4_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
- }
- },
- {
- .name = "power well 5",
- .domains = TGL_PW_5_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_PW_5,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_D),
- },
- },
-};
-
-static const struct i915_power_well_desc rkl_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DC off",
- .domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 3",
- .domains = RKL_PW_3_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well 4",
- .domains = RKL_PW_4_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
- }
- },
- {
- .name = "DDI A IO",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
- },
- {
- .name = "DDI B IO",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- },
- {
- .name = "DDI IO TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- },
- },
- {
- .name = "DDI IO TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- },
- },
- {
- .name = "AUX A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- },
- {
- .name = "AUX B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- },
- {
- .name = "AUX USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- },
- },
- {
- .name = "AUX USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- },
- },
-};
-
-static const struct i915_power_well_desc dg1_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DC off",
- .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = DG1_PW_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well 3",
- .domains = DG1_PW_3_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DDI A IO",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
- },
- {
- .name = "DDI B IO",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- },
- {
- .name = "DDI IO TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- },
- },
- {
- .name = "DDI IO TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- },
- },
- {
- .name = "AUX A",
- .domains = TGL_AUX_A_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- },
- {
- .name = "AUX B",
- .domains = TGL_AUX_B_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- },
- {
- .name = "AUX USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "AUX USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- .hsw.is_tc_tbt = false,
- },
- },
- {
- .name = "power well 4",
- .domains = TGL_PW_4_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
- }
- },
- {
- .name = "power well 5",
- .domains = TGL_PW_5_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_PW_5,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_D),
- },
- },
-};
-
-static const struct i915_power_well_desc xelpd_power_wells[] = {
- {
- .name = "always-on",
- .always_on = true,
- .domains = POWER_DOMAIN_MASK,
- .ops = &i9xx_always_on_power_well_ops,
- .id = DISP_PW_ID_NONE,
- },
- {
- .name = "power well 1",
- /* Handled by the DMC firmware */
- .always_on = true,
- .domains = 0,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DC off",
- .domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
- .ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
- },
- {
- .name = "power well 2",
- .domains = XELPD_PW_2_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well A",
- .domains = XELPD_PW_A_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_A,
- .hsw.irq_pipe_mask = BIT(PIPE_A),
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well B",
- .domains = XELPD_PW_B_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_B,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well C",
- .domains = XELPD_PW_C_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_C,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "power well D",
- .domains = XELPD_PW_D_POWER_DOMAINS,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_D,
- .hsw.irq_pipe_mask = BIT(PIPE_D),
- .hsw.has_fuses = true,
- },
- },
- {
- .name = "DDI A IO",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
- },
- {
- .name = "DDI B IO",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- },
- {
- .name = "DDI C IO",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
- }
- },
- {
- .name = "DDI IO D_XELPD",
- .domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_DDI_D,
- }
- },
- {
- .name = "DDI IO E_XELPD",
- .domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_DDI_E,
- }
- },
- {
- .name = "DDI IO TC1",
- .domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- }
- },
- {
- .name = "DDI IO TC2",
- .domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- }
- },
- {
- .name = "DDI IO TC3",
- .domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
- }
- },
- {
- .name = "DDI IO TC4",
- .domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
- }
- },
- {
- .name = "AUX A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- .hsw.fixed_enable_delay = 600,
- },
- },
- {
- .name = "AUX B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- .hsw.fixed_enable_delay = 600,
- },
- },
- {
- .name = "AUX C",
- .domains = TGL_AUX_C_IO_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- .hsw.fixed_enable_delay = 600,
- },
- },
- {
- .name = "AUX D_XELPD",
- .domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
- .hsw.fixed_enable_delay = 600,
- },
- },
- {
- .name = "AUX E_XELPD",
- .domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_AUX_E,
- },
- },
- {
- .name = "AUX USBC1",
- .domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- .hsw.fixed_enable_delay = 600,
- },
- },
- {
- .name = "AUX USBC2",
- .domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- },
- },
- {
- .name = "AUX USBC3",
- .domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
- },
- },
- {
- .name = "AUX USBC4",
- .domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
- },
- },
- {
- .name = "AUX TBT1",
- .domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT2",
- .domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT3",
- .domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
- .hsw.is_tc_tbt = true,
- },
- },
- {
- .name = "AUX TBT4",
- .domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
- .hsw.is_tc_tbt = true,
- },
- },
-};
-
static int
sanitize_disable_power_well_option(const struct drm_i915_private *dev_priv,
int disable_power_well)
@@ -3089,57 +927,6 @@ static u32 get_allowed_dc_mask(const struct drm_i915_private *dev_priv,
return mask;
}
-static int
-__set_power_wells(struct i915_power_domains *power_domains,
- const struct i915_power_well_desc *power_well_descs,
- int power_well_descs_sz, u64 skip_mask)
-{
- struct drm_i915_private *i915 = container_of(power_domains,
- struct drm_i915_private,
- power_domains);
- u64 power_well_ids = 0;
- int power_well_count = 0;
- int i, plt_idx = 0;
-
- for (i = 0; i < power_well_descs_sz; i++)
- if (!(BIT_ULL(power_well_descs[i].id) & skip_mask))
- power_well_count++;
-
- power_domains->power_well_count = power_well_count;
- power_domains->power_wells =
- kcalloc(power_well_count,
- sizeof(*power_domains->power_wells),
- GFP_KERNEL);
- if (!power_domains->power_wells)
- return -ENOMEM;
-
- for (i = 0; i < power_well_descs_sz; i++) {
- enum i915_power_well_id id = power_well_descs[i].id;
-
- if (BIT_ULL(id) & skip_mask)
- continue;
-
- power_domains->power_wells[plt_idx++].desc =
- &power_well_descs[i];
-
- if (id == DISP_PW_ID_NONE)
- continue;
-
- drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) * 8);
- drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id));
- power_well_ids |= BIT_ULL(id);
- }
-
- return 0;
-}
-
-#define set_power_wells_mask(power_domains, __power_well_descs, skip_mask) \
- __set_power_wells(power_domains, __power_well_descs, \
- ARRAY_SIZE(__power_well_descs), skip_mask)
-
-#define set_power_wells(power_domains, __power_well_descs) \
- set_power_wells_mask(power_domains, __power_well_descs, 0)
-
/**
* intel_power_domains_init - initializes the power domain structures
* @dev_priv: i915 device instance
@@ -3150,7 +937,6 @@ __set_power_wells(struct i915_power_domains *power_domains,
int intel_power_domains_init(struct drm_i915_private *dev_priv)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
- int err;
dev_priv->params.disable_power_well =
sanitize_disable_power_well_option(dev_priv,
@@ -3168,47 +954,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
INIT_DELAYED_WORK(&power_domains->async_put_work,
intel_display_power_put_async_work);
- /*
- * The enabling order will be from lower to higher indexed wells,
- * the disabling order is reversed.
- */
- if (!HAS_DISPLAY(dev_priv)) {
- power_domains->power_well_count = 0;
- err = 0;
- } else if (DISPLAY_VER(dev_priv) >= 13) {
- err = set_power_wells(power_domains, xelpd_power_wells);
- } else if (IS_DG1(dev_priv)) {
- err = set_power_wells(power_domains, dg1_power_wells);
- } else if (IS_ALDERLAKE_S(dev_priv)) {
- err = set_power_wells_mask(power_domains, tgl_power_wells,
- BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
- } else if (IS_ROCKETLAKE(dev_priv)) {
- err = set_power_wells(power_domains, rkl_power_wells);
- } else if (DISPLAY_VER(dev_priv) == 12) {
- err = set_power_wells(power_domains, tgl_power_wells);
- } else if (DISPLAY_VER(dev_priv) == 11) {
- err = set_power_wells(power_domains, icl_power_wells);
- } else if (IS_GEMINILAKE(dev_priv)) {
- err = set_power_wells(power_domains, glk_power_wells);
- } else if (IS_BROXTON(dev_priv)) {
- err = set_power_wells(power_domains, bxt_power_wells);
- } else if (DISPLAY_VER(dev_priv) == 9) {
- err = set_power_wells(power_domains, skl_power_wells);
- } else if (IS_CHERRYVIEW(dev_priv)) {
- err = set_power_wells(power_domains, chv_power_wells);
- } else if (IS_BROADWELL(dev_priv)) {
- err = set_power_wells(power_domains, bdw_power_wells);
- } else if (IS_HASWELL(dev_priv)) {
- err = set_power_wells(power_domains, hsw_power_wells);
- } else if (IS_VALLEYVIEW(dev_priv)) {
- err = set_power_wells(power_domains, vlv_power_wells);
- } else if (IS_I830(dev_priv)) {
- err = set_power_wells(power_domains, i830_power_wells);
- } else {
- err = set_power_wells(power_domains, i9xx_always_on_power_well);
- }
-
- return err;
+ return intel_display_power_map_init(power_domains);
}
/**
@@ -3219,7 +965,7 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
*/
void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
{
- kfree(dev_priv->power_domains.power_wells);
+ intel_display_power_map_cleanup(&dev_priv->power_domains);
}
static void intel_power_domains_sync_hw(struct drm_i915_private *dev_priv)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
new file mode 100644
index 0000000000000..97e0daec95449
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -0,0 +1,2150 @@
+// SPDX-License-Identifier: MIT
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#include "i915_drv.h"
+#include "i915_reg.h"
+
+#include "vlv_sideband_reg.h"
+
+#include "intel_display_power_map.h"
+#include "intel_display_power_well.h"
+
+#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
+
+static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ },
+};
+
+#define I830_PIPES_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc i830_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "pipes",
+ .domains = I830_PIPES_POWER_DOMAINS,
+ .ops = &i830_pipes_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ },
+};
+
+#define HSW_DISPLAY_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc hsw_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "display",
+ .domains = HSW_DISPLAY_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = HSW_DISP_PW_GLOBAL,
+ {
+ .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
+ .hsw.has_vga = true,
+ },
+ },
+};
+
+#define BDW_DISPLAY_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc bdw_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "display",
+ .domains = BDW_DISPLAY_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = HSW_DISP_PW_GLOBAL,
+ {
+ .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ },
+ },
+};
+
+#define VLV_DISPLAY_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
+ BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_GMBUS) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc vlv_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "display",
+ .domains = VLV_DISPLAY_POWER_DOMAINS,
+ .ops = &vlv_display_power_well_ops,
+ .id = VLV_DISP_PW_DISP2D,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
+ },
+ }, {
+ .name = "dpio-tx-b-01",
+ .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .ops = &vlv_dpio_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
+ },
+ }, {
+ .name = "dpio-tx-b-23",
+ .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .ops = &vlv_dpio_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
+ },
+ }, {
+ .name = "dpio-tx-c-01",
+ .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .ops = &vlv_dpio_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
+ },
+ }, {
+ .name = "dpio-tx-c-23",
+ .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
+ VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .ops = &vlv_dpio_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
+ },
+ }, {
+ .name = "dpio-common",
+ .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
+ .ops = &vlv_dpio_cmn_power_well_ops,
+ .id = VLV_DISP_PW_DPIO_CMN_BC,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
+ },
+ },
+};
+
+#define CHV_DISPLAY_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_GMBUS) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc chv_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "display",
+ /*
+ * Pipe A power well is the new disp2d well. Pipe B and C
+ * power wells don't actually exist. Pipe A power well is
+ * required for any pipe to work.
+ */
+ .domains = CHV_DISPLAY_POWER_DOMAINS,
+ .ops = &chv_pipe_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "dpio-common-bc",
+ .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
+ .ops = &chv_dpio_cmn_power_well_ops,
+ .id = VLV_DISP_PW_DPIO_CMN_BC,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
+ },
+ }, {
+ .name = "dpio-common-d",
+ .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
+ .ops = &chv_dpio_cmn_power_well_ops,
+ .id = CHV_DISP_PW_DPIO_CMN_D,
+ {
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
+ },
+ },
+};
+
+#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc skl_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "MISC IO power well",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_MISC_IO,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
+ },
+ }, {
+ .name = "DC off",
+ .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 2",
+ .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DDI A/E IO power well",
+ .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
+ },
+ }, {
+ .name = "DDI B IO power well",
+ .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
+ },
+ }, {
+ .name = "DDI C IO power well",
+ .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
+ },
+ }, {
+ .name = "DDI D IO power well",
+ .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
+ },
+ },
+};
+
+#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_GMBUS) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc bxt_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DC off",
+ .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 2",
+ .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "dpio-common-a",
+ .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
+ .ops = &bxt_dpio_cmn_power_well_ops,
+ .id = BXT_DISP_PW_DPIO_CMN_A,
+ {
+ .bxt.phy = DPIO_PHY1,
+ },
+ }, {
+ .name = "dpio-common-bc",
+ .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
+ .ops = &bxt_dpio_cmn_power_well_ops,
+ .id = VLV_DISP_PW_DPIO_CMN_BC,
+ {
+ .bxt.phy = DPIO_PHY0,
+ },
+ },
+};
+
+#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_GMBUS) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)
+#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)
+#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)
+
+#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc glk_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DC off",
+ .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 2",
+ .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
+ .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "dpio-common-a",
+ .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
+ .ops = &bxt_dpio_cmn_power_well_ops,
+ .id = BXT_DISP_PW_DPIO_CMN_A,
+ {
+ .bxt.phy = DPIO_PHY1,
+ },
+ }, {
+ .name = "dpio-common-b",
+ .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
+ .ops = &bxt_dpio_cmn_power_well_ops,
+ .id = VLV_DISP_PW_DPIO_CMN_BC,
+ {
+ .bxt.phy = DPIO_PHY0,
+ },
+ }, {
+ .name = "dpio-common-c",
+ .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
+ .ops = &bxt_dpio_cmn_power_well_ops,
+ .id = GLK_DISP_PW_DPIO_CMN_C,
+ {
+ .bxt.phy = DPIO_PHY2,
+ },
+ }, {
+ .name = "AUX A",
+ .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
+ },
+ }, {
+ .name = "AUX B",
+ .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
+ },
+ }, {
+ .name = "AUX C",
+ .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
+ },
+ }, {
+ .name = "DDI A IO power well",
+ .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
+ },
+ }, {
+ .name = "DDI B IO power well",
+ .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
+ },
+ }, {
+ .name = "DDI C IO power well",
+ .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
+ },
+ },
+};
+
+/*
+ * ICL PW_0/PG_0 domains (HW/DMC control):
+ * - PCI
+ * - clocks except port PLL
+ * - central power except FBC
+ * - shared functions except pipe interrupts, pipe MBUS, DBUF registers
+ * ICL PW_1/PG_1 domains (HW/DMC control):
+ * - DBUF function
+ * - PIPE_A and its planes, except VGA
+ * - transcoder EDP + PSR
+ * - transcoder DSI
+ * - DDI_A
+ * - FBC
+ */
+#define ICL_PW_4_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+ /* VDSC/joining */
+
+#define ICL_PW_3_POWER_DOMAINS ( \
+ ICL_PW_4_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E) | \
+ BIT_ULL(POWER_DOMAIN_AUX_F) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+ /*
+ * - transcoder WD
+ * - KVMR (HW control)
+ */
+
+#define ICL_PW_2_POWER_DOMAINS ( \
+ ICL_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+ /*
+ * - KVMR (HW control)
+ */
+
+#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ ICL_PW_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_DC_OFF) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define ICL_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)
+#define ICL_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)
+#define ICL_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)
+#define ICL_DDI_IO_D_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO)
+#define ICL_DDI_IO_E_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO)
+#define ICL_DDI_IO_F_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO)
+
+#define ICL_AUX_A_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_IO_A))
+
+#define ICL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
+#define ICL_AUX_C_TC1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
+#define ICL_AUX_D_TC2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D)
+#define ICL_AUX_E_TC3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E)
+#define ICL_AUX_F_TC4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F)
+#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C_TBT)
+#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_TBT)
+#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_TBT)
+#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F_TBT)
+
+static const struct i915_power_well_desc icl_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DC off",
+ .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 2",
+ .domains = ICL_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well 3",
+ .domains = ICL_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = ICL_DISP_PW_3,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ },
+ }, {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ },
+ }, {
+ .name = "DDI C IO",
+ .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
+ },
+ }, {
+ .name = "DDI D IO",
+ .domains = ICL_DDI_IO_D_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
+ },
+ }, {
+ .name = "DDI E IO",
+ .domains = ICL_DDI_IO_E_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
+ },
+ }, {
+ .name = "DDI F IO",
+ .domains = ICL_DDI_IO_F_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
+ },
+ }, {
+ .name = "AUX A",
+ .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ }, {
+ .name = "AUX B",
+ .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
+ }, {
+ .name = "AUX C TC1",
+ .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX D TC2",
+ .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX E TC3",
+ .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX F TC4",
+ .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX C TBT1",
+ .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX D TBT2",
+ .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX E TBT3",
+ .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX F TBT4",
+ .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "power well 4",
+ .domains = ICL_PW_4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ },
+ },
+};
+
+#define TGL_PW_5_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_PW_4_POWER_DOMAINS ( \
+ TGL_PW_5_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_PW_3_POWER_DOMAINS ( \
+ TGL_PW_4_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_PW_2_POWER_DOMAINS ( \
+ TGL_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ TGL_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define TGL_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
+#define TGL_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
+#define TGL_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
+#define TGL_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
+#define TGL_DDI_IO_TC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC5)
+#define TGL_DDI_IO_TC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC6)
+
+#define TGL_AUX_A_IO_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_IO_A))
+#define TGL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
+#define TGL_AUX_C_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
+
+#define TGL_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
+#define TGL_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
+#define TGL_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
+#define TGL_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
+#define TGL_AUX_IO_USBC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC5)
+#define TGL_AUX_IO_USBC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC6)
+
+#define TGL_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
+#define TGL_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
+#define TGL_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
+#define TGL_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
+#define TGL_AUX_IO_TBT5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT5)
+#define TGL_AUX_IO_TBT6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT6)
+
+#define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
+ BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
+
+static const struct i915_power_well_desc tgl_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DC off",
+ .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 2",
+ .domains = TGL_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well 3",
+ .domains = TGL_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = ICL_DISP_PW_3,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ }
+ }, {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ }
+ }, {
+ .name = "DDI C IO",
+ .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
+ }
+ }, {
+ .name = "DDI IO TC1",
+ .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+ },
+ }, {
+ .name = "DDI IO TC2",
+ .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+ },
+ }, {
+ .name = "DDI IO TC3",
+ .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
+ },
+ }, {
+ .name = "DDI IO TC4",
+ .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
+ },
+ }, {
+ .name = "DDI IO TC5",
+ .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
+ },
+ }, {
+ .name = "DDI IO TC6",
+ .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
+ },
+ }, {
+ .name = "TC cold off",
+ .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
+ .ops = &tgl_tc_cold_off_ops,
+ .id = TGL_DISP_PW_TC_COLD_OFF,
+ }, {
+ .name = "AUX A",
+ .domains = TGL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ }, {
+ .name = "AUX B",
+ .domains = TGL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
+ }, {
+ .name = "AUX C",
+ .domains = TGL_AUX_C_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
+ },
+ }, {
+ .name = "AUX USBC1",
+ .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX USBC2",
+ .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX USBC3",
+ .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX USBC4",
+ .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX USBC5",
+ .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX USBC6",
+ .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX TBT1",
+ .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT2",
+ .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT3",
+ .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT4",
+ .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT5",
+ .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT6",
+ .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "power well 4",
+ .domains = TGL_PW_4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ }
+ }, {
+ .name = "power well 5",
+ .domains = TGL_PW_5_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ },
+ },
+};
+
+#define RKL_PW_4_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define RKL_PW_3_POWER_DOMAINS ( \
+ RKL_PW_4_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+/*
+ * There is no PW_2/PG_2 on RKL.
+ *
+ * RKL PW_1/PG_1 domains (under HW/DMC control):
+ * - DBUF function (note: registers are in PW0)
+ * - PIPE_A and its planes and VDSC/joining, except VGA
+ * - transcoder A
+ * - DDI_A and DDI_B
+ * - FBC
+ *
+ * RKL PW_0/PG_0 domains (under HW/DMC control):
+ * - PCI
+ * - clocks except port PLL
+ * - shared functions:
+ * * interrupts except pipe interrupts
+ * * MBus except PIPE_MBUS_DBOX_CTL
+ * * DBUF registers
+ * - central power except FBC
+ * - top-level GTC (DDI-level GTC is in the well associated with the DDI)
+ */
+
+#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ RKL_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc rkl_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DC off",
+ .domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 3",
+ .domains = RKL_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = ICL_DISP_PW_3,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well 4",
+ .domains = RKL_PW_4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ }
+ }, {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ }
+ }, {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ }
+ }, {
+ .name = "DDI IO TC1",
+ .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+ },
+ }, {
+ .name = "DDI IO TC2",
+ .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+ },
+ }, {
+ .name = "AUX A",
+ .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ }, {
+ .name = "AUX B",
+ .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
+ }, {
+ .name = "AUX USBC1",
+ .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ },
+ }, {
+ .name = "AUX USBC2",
+ .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+ },
+ },
+};
+
+/*
+ * DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
+ */
+#define DG1_PW_3_POWER_DOMAINS ( \
+ TGL_PW_4_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ DG1_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define DG1_PW_2_POWER_DOMAINS ( \
+ DG1_PW_3_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+static const struct i915_power_well_desc dg1_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DC off",
+ .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 2",
+ .domains = DG1_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well 3",
+ .domains = DG1_PW_3_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = ICL_DISP_PW_3,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ }
+ }, {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ }
+ }, {
+ .name = "DDI IO TC1",
+ .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+ },
+ }, {
+ .name = "DDI IO TC2",
+ .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+ },
+ }, {
+ .name = "AUX A",
+ .domains = TGL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ },
+ }, {
+ .name = "AUX B",
+ .domains = TGL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ },
+ }, {
+ .name = "AUX USBC1",
+ .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "AUX USBC2",
+ .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+ .hsw.is_tc_tbt = false,
+ },
+ }, {
+ .name = "power well 4",
+ .domains = TGL_PW_4_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ }
+ }, {
+ .name = "power well 5",
+ .domains = TGL_PW_5_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5,
+ .hsw.has_fuses = true,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ },
+ },
+};
+
+/*
+ * XE_LPD Power Domains
+ *
+ * Previous platforms required that PG(n-1) be enabled before PG(n). That
+ * dependency chain turns into a dependency tree on XE_LPD:
+ *
+ * PG0
+ * |
+ * --PG1--
+ * / \
+ * PGA --PG2--
+ * / | \
+ * PGB PGC PGD
+ *
+ * Power wells must be enabled from top to bottom and disabled from bottom
+ * to top. This allows pipes to be power gated independently.
+ */
+
+#define XELPD_PW_D_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_D) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_C_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_C) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_B_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_A_POWER_DOMAINS ( \
+ BIT_ULL(POWER_DOMAIN_PIPE_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_PW_2_POWER_DOMAINS ( \
+ XELPD_PW_B_POWER_DOMAINS | \
+ XELPD_PW_C_POWER_DOMAINS | \
+ XELPD_PW_D_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
+ BIT_ULL(POWER_DOMAIN_VGA) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
+ BIT_ULL(POWER_DOMAIN_AUX_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+/*
+ * XELPD PW_1/PG_1 domains (under HW/DMC control):
+ * - DBUF function (registers are in PW0)
+ * - Transcoder A
+ * - DDI_A and DDI_B
+ *
+ * XELPD PW_0/PW_1 domains (under HW/DMC control):
+ * - PCI
+ * - Clocks except port PLL
+ * - Shared functions:
+ * * interrupts except pipe interrupts
+ * * MBus except PIPE_MBUS_DBOX_CTL
+ * * DBUF registers
+ * - Central power except FBC
+ * - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
+ */
+
+#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
+ XELPD_PW_2_POWER_DOMAINS | \
+ BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
+ BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
+ BIT_ULL(POWER_DOMAIN_AUX_A) | \
+ BIT_ULL(POWER_DOMAIN_AUX_B) | \
+ BIT_ULL(POWER_DOMAIN_MODESET) | \
+ BIT_ULL(POWER_DOMAIN_INIT))
+
+#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
+#define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
+#define XELPD_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
+#define XELPD_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
+#define XELPD_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
+#define XELPD_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
+
+#define XELPD_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
+#define XELPD_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
+#define XELPD_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
+#define XELPD_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
+
+#define XELPD_DDI_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D_XELPD)
+#define XELPD_DDI_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E_XELPD)
+#define XELPD_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
+#define XELPD_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
+#define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
+#define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
+
+static const struct i915_power_well_desc xelpd_power_wells[] = {
+ {
+ .name = "always-on",
+ .domains = POWER_DOMAIN_MASK,
+ .ops = &i9xx_always_on_power_well_ops,
+ .always_on = true,
+ .id = DISP_PW_ID_NONE,
+ }, {
+ .name = "power well 1",
+ /* Handled by the DMC firmware */
+ .domains = 0,
+ .ops = &hsw_power_well_ops,
+ .always_on = true,
+ .id = SKL_DISP_PW_1,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DC off",
+ .domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .ops = &gen9_dc_off_power_well_ops,
+ .id = SKL_DISP_DC_OFF,
+ }, {
+ .name = "power well 2",
+ .domains = XELPD_PW_2_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = SKL_DISP_PW_2,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .hsw.has_vga = true,
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well A",
+ .domains = XELPD_PW_A_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_A,
+ .hsw.irq_pipe_mask = BIT(PIPE_A),
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well B",
+ .domains = XELPD_PW_B_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_B,
+ .hsw.irq_pipe_mask = BIT(PIPE_B),
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well C",
+ .domains = XELPD_PW_C_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_C,
+ .hsw.irq_pipe_mask = BIT(PIPE_C),
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "power well D",
+ .domains = XELPD_PW_D_POWER_DOMAINS,
+ .ops = &hsw_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_D,
+ .hsw.irq_pipe_mask = BIT(PIPE_D),
+ .hsw.has_fuses = true,
+ },
+ }, {
+ .name = "DDI A IO",
+ .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
+ }
+ }, {
+ .name = "DDI B IO",
+ .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
+ }
+ }, {
+ .name = "DDI C IO",
+ .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
+ }
+ }, {
+ .name = "DDI IO D_XELPD",
+ .domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_DDI_D,
+ }
+ }, {
+ .name = "DDI IO E_XELPD",
+ .domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_DDI_E,
+ }
+ }, {
+ .name = "DDI IO TC1",
+ .domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
+ }
+ }, {
+ .name = "DDI IO TC2",
+ .domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
+ }
+ }, {
+ .name = "DDI IO TC3",
+ .domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
+ }
+ }, {
+ .name = "DDI IO TC4",
+ .domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
+ .ops = &icl_ddi_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
+ }
+ }, {
+ .name = "AUX A",
+ .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
+ .hsw.fixed_enable_delay = 600,
+ },
+ }, {
+ .name = "AUX B",
+ .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
+ .hsw.fixed_enable_delay = 600,
+ },
+ }, {
+ .name = "AUX C",
+ .domains = TGL_AUX_C_IO_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
+ .hsw.fixed_enable_delay = 600,
+ },
+ }, {
+ .name = "AUX D_XELPD",
+ .domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
+ .hsw.fixed_enable_delay = 600,
+ },
+ }, {
+ .name = "AUX E_XELPD",
+ .domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = XELPD_PW_CTL_IDX_AUX_E,
+ },
+ }, {
+ .name = "AUX USBC1",
+ .domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
+ .hsw.fixed_enable_delay = 600,
+ },
+ }, {
+ .name = "AUX USBC2",
+ .domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
+ },
+ }, {
+ .name = "AUX USBC3",
+ .domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
+ },
+ }, {
+ .name = "AUX USBC4",
+ .domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
+ },
+ }, {
+ .name = "AUX TBT1",
+ .domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT2",
+ .domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT3",
+ .domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
+ .hsw.is_tc_tbt = true,
+ },
+ }, {
+ .name = "AUX TBT4",
+ .domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
+ .ops = &icl_aux_power_well_ops,
+ .id = DISP_PW_ID_NONE,
+ {
+ .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
+ .hsw.is_tc_tbt = true,
+ },
+ },
+};
+
+static int
+__set_power_wells(struct i915_power_domains *power_domains,
+ const struct i915_power_well_desc *power_well_descs,
+ int power_well_descs_sz, u64 skip_mask)
+{
+ struct drm_i915_private *i915 = container_of(power_domains,
+ struct drm_i915_private,
+ power_domains);
+ u64 power_well_ids = 0;
+ int power_well_count = 0;
+ int i, plt_idx = 0;
+
+ for (i = 0; i < power_well_descs_sz; i++)
+ if (!(BIT_ULL(power_well_descs[i].id) & skip_mask))
+ power_well_count++;
+
+ power_domains->power_well_count = power_well_count;
+ power_domains->power_wells =
+ kcalloc(power_well_count,
+ sizeof(*power_domains->power_wells),
+ GFP_KERNEL);
+ if (!power_domains->power_wells)
+ return -ENOMEM;
+
+ for (i = 0; i < power_well_descs_sz; i++) {
+ enum i915_power_well_id id = power_well_descs[i].id;
+
+ if (BIT_ULL(id) & skip_mask)
+ continue;
+
+ power_domains->power_wells[plt_idx++].desc =
+ &power_well_descs[i];
+
+ if (id == DISP_PW_ID_NONE)
+ continue;
+
+ drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) * 8);
+ drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id));
+ power_well_ids |= BIT_ULL(id);
+ }
+
+ return 0;
+}
+
+#define set_power_wells_mask(power_domains, __power_well_descs, skip_mask) \
+ __set_power_wells(power_domains, __power_well_descs, \
+ ARRAY_SIZE(__power_well_descs), skip_mask)
+
+#define set_power_wells(power_domains, __power_well_descs) \
+ set_power_wells_mask(power_domains, __power_well_descs, 0)
+
+/**
+ * intel_display_power_map_init - initialize power domain -> power well mappings
+ * @power_domains: power domain state
+ *
+ * Creates all the power wells for the current platform, initializes the
+ * dynamic state for them and initializes the mapping of each power well to
+ * all the power domains the power well belongs to.
+ */
+int intel_display_power_map_init(struct i915_power_domains *power_domains)
+{
+ struct drm_i915_private *i915 = container_of(power_domains,
+ struct drm_i915_private,
+ power_domains);
+ /*
+ * The enabling order will be from lower to higher indexed wells,
+ * the disabling order is reversed.
+ */
+ if (!HAS_DISPLAY(i915)) {
+ power_domains->power_well_count = 0;
+ return 0;
+ }
+
+ if (DISPLAY_VER(i915) >= 13)
+ return set_power_wells(power_domains, xelpd_power_wells);
+ else if (IS_DG1(i915))
+ return set_power_wells(power_domains, dg1_power_wells);
+ else if (IS_ALDERLAKE_S(i915))
+ return set_power_wells_mask(power_domains, tgl_power_wells,
+ BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
+ else if (IS_ROCKETLAKE(i915))
+ return set_power_wells(power_domains, rkl_power_wells);
+ else if (DISPLAY_VER(i915) == 12)
+ return set_power_wells(power_domains, tgl_power_wells);
+ else if (DISPLAY_VER(i915) == 11)
+ return set_power_wells(power_domains, icl_power_wells);
+ else if (IS_GEMINILAKE(i915))
+ return set_power_wells(power_domains, glk_power_wells);
+ else if (IS_BROXTON(i915))
+ return set_power_wells(power_domains, bxt_power_wells);
+ else if (DISPLAY_VER(i915) == 9)
+ return set_power_wells(power_domains, skl_power_wells);
+ else if (IS_CHERRYVIEW(i915))
+ return set_power_wells(power_domains, chv_power_wells);
+ else if (IS_BROADWELL(i915))
+ return set_power_wells(power_domains, bdw_power_wells);
+ else if (IS_HASWELL(i915))
+ return set_power_wells(power_domains, hsw_power_wells);
+ else if (IS_VALLEYVIEW(i915))
+ return set_power_wells(power_domains, vlv_power_wells);
+ else if (IS_I830(i915))
+ return set_power_wells(power_domains, i830_power_wells);
+ else
+ return set_power_wells(power_domains, i9xx_always_on_power_well);
+}
+
+/**
+ * intel_display_power_map_cleanup - clean up power domain -> power well mappings
+ * @power_domains: power domain state
+ *
+ * Cleans up all the state that was initialized by intel_display_power_map_init().
+ */
+void intel_display_power_map_cleanup(struct i915_power_domains *power_domains)
+{
+ kfree(power_domains->power_wells);
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.h b/drivers/gpu/drm/i915/display/intel_display_power_map.h
new file mode 100644
index 0000000000000..da8f7055a44c6
--- /dev/null
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.h
@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: MIT */
+/*
+ * Copyright © 2022 Intel Corporation
+ */
+
+#ifndef __INTEL_DISPLAY_POWER_MAP_H__
+#define __INTEL_DISPLAY_POWER_MAP_H__
+
+struct i915_power_domains;
+
+int intel_display_power_map_init(struct i915_power_domains *power_domains);
+void intel_display_power_map_cleanup(struct i915_power_domains *power_domains);
+
+#endif
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* Re: [Intel-gfx] [PATCH v3 03/18] drm/i915: Move the power domain->well mappings to intel_display_power_map.c
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 03/18] drm/i915: Move the power domain->well mappings to intel_display_power_map.c Imre Deak
@ 2022-03-31 7:14 ` Hogander, Jouni
0 siblings, 0 replies; 29+ messages in thread
From: Hogander, Jouni @ 2022-03-31 7:14 UTC (permalink / raw)
To: intel-gfx, Deak, Imre; +Cc: Nikula, Jani
On Tue, 2022-03-29 at 19:43 +0300, Imre Deak wrote:
> Move the list of platform specific power domain -> power well
> definitions to intel_display_power_map.c. While at it group the
> platforms' power domain macros with the corresponding power well
> lists
> and keep all the power domain lists in the same order (matching the
> enum
> order).
>
> No functional changes.
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
>
> v2:
> - s/intel_display_power_internal.h/intel_display_power_map.h/ (Jani)
> - Simplify intel_cleanup_power_wells().
> - Don't move intel_display_power_domain_str().
> v3:
> - Rename intel_init/cleanup_power_wells() to
> intel_display_power_map_init/cleanup().
> - Add documentation to intel_display_power_map_init/cleanup().
>
> Cc: Jani Nikula <jani.nikula@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Reviewed-by: Jouni Högander <jouni.hogander@intel.com> (v2)
> ---
> drivers/gpu/drm/i915/Makefile | 1 +
> .../drm/i915/display/intel_display_power.c | 2260 +------------
> ----
> .../i915/display/intel_display_power_map.c | 2150
> ++++++++++++++++
> .../i915/display/intel_display_power_map.h | 14 +
> 4 files changed, 2168 insertions(+), 2257 deletions(-)
> create mode 100644
> drivers/gpu/drm/i915/display/intel_display_power_map.c
> create mode 100644
> drivers/gpu/drm/i915/display/intel_display_power_map.h
>
> diff --git a/drivers/gpu/drm/i915/Makefile
> b/drivers/gpu/drm/i915/Makefile
> index c1d5540f60529..469ee62982b4b 100644
> --- a/drivers/gpu/drm/i915/Makefile
> +++ b/drivers/gpu/drm/i915/Makefile
> @@ -216,6 +216,7 @@ i915-y += \
> display/intel_cursor.o \
> display/intel_display.o \
> display/intel_display_power.o \
> + display/intel_display_power_map.o \
> display/intel_display_power_well.o \
> display/intel_dmc.o \
> display/intel_dpio_phy.o \
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c
> b/drivers/gpu/drm/i915/display/intel_display_power.c
> index 25b614bf09d83..e999433589715 100644
> --- a/drivers/gpu/drm/i915/display/intel_display_power.c
> +++ b/drivers/gpu/drm/i915/display/intel_display_power.c
> @@ -11,6 +11,7 @@
> #include "intel_combo_phy.h"
> #include "intel_de.h"
> #include "intel_display_power.h"
> +#include "intel_display_power_map.h"
> #include "intel_display_power_well.h"
> #include "intel_display_types.h"
> #include "intel_dmc.h"
> @@ -848,2169 +849,6 @@ intel_display_power_put_mask_in_set(struct
> drm_i915_private *i915,
> }
> }
>
> -#define I830_PIPES_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define VLV_DISPLAY_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> - BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_GMBUS) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define CHV_DISPLAY_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> - BIT_ULL(POWER_DOMAIN_GMBUS) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define HSW_DISPLAY_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define BDW_DISPLAY_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_GMBUS) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
> -#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
> -#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
> -#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_GMBUS) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -/*
> - * ICL PW_0/PG_0 domains (HW/DMC control):
> - * - PCI
> - * - clocks except port PLL
> - * - central power except FBC
> - * - shared functions except pipe interrupts, pipe MBUS, DBUF
> registers
> - * ICL PW_1/PG_1 domains (HW/DMC control):
> - * - DBUF function
> - * - PIPE_A and its planes, except VGA
> - * - transcoder EDP + PSR
> - * - transcoder DSI
> - * - DDI_A
> - * - FBC
> - */
> -#define ICL_PW_4_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> - /* VDSC/joining */
> -#define ICL_PW_3_POWER_DOMAINS ( \
> - ICL_PW_4_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_D) | \
> - BIT_ULL(POWER_DOMAIN_AUX_E) | \
> - BIT_ULL(POWER_DOMAIN_AUX_F) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
> - BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
> - BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
> - BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> - /*
> - * - transcoder WD
> - * - KVMR (HW control)
> - */
> -#define ICL_PW_2_POWER_DOMAINS ( \
> - ICL_PW_3_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> - /*
> - * - KVMR (HW control)
> - */
> -#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - ICL_PW_2_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_DC_OFF) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define ICL_DDI_IO_A_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO))
> -#define ICL_DDI_IO_B_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO))
> -#define ICL_DDI_IO_C_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO))
> -#define ICL_DDI_IO_D_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO))
> -#define ICL_DDI_IO_E_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO))
> -#define ICL_DDI_IO_F_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO))
> -
> -#define ICL_AUX_A_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A))
> -#define ICL_AUX_B_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_B))
> -#define ICL_AUX_C_TC1_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_C))
> -#define ICL_AUX_D_TC2_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_D))
> -#define ICL_AUX_E_TC3_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_E))
> -#define ICL_AUX_F_TC4_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_F))
> -#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_C_TBT))
> -#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_D_TBT))
> -#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_E_TBT))
> -#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_F_TBT))
> -
> -#define TGL_PW_5_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_D) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define TGL_PW_4_POWER_DOMAINS ( \
> - TGL_PW_5_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define TGL_PW_3_POWER_DOMAINS ( \
> - TGL_PW_4_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define TGL_PW_2_POWER_DOMAINS ( \
> - TGL_PW_3_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - TGL_PW_3_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define TGL_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_I
> O_TC1)
> -#define TGL_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_I
> O_TC2)
> -#define TGL_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_I
> O_TC3)
> -#define TGL_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_I
> O_TC4)
> -#define TGL_DDI_IO_TC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_I
> O_TC5)
> -#define TGL_DDI_IO_TC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_I
> O_TC6)
> -
> -#define TGL_AUX_A_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A))
> -#define TGL_AUX_B_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_B))
> -#define TGL_AUX_C_IO_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_C))
> -
> -#define TGL_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC1)
> -#define TGL_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC2)
> -#define TGL_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC3)
> -#define TGL_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC4)
> -#define TGL_AUX_IO_USBC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC5)
> -#define TGL_AUX_IO_USBC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC6)
> -
> -#define TGL_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_TBT1)
> -#define TGL_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_TBT2)
> -#define TGL_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_TBT3)
> -#define TGL_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_TBT4)
> -#define TGL_AUX_IO_TBT5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_TBT5)
> -#define TGL_AUX_IO_TBT6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_TBT6)
> -
> -#define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> - BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
> -
> -#define RKL_PW_4_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define RKL_PW_3_POWER_DOMAINS ( \
> - RKL_PW_4_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -/*
> - * There is no PW_2/PG_2 on RKL.
> - *
> - * RKL PW_1/PG_1 domains (under HW/DMC control):
> - * - DBUF function (note: registers are in PW0)
> - * - PIPE_A and its planes and VDSC/joining, except VGA
> - * - transcoder A
> - * - DDI_A and DDI_B
> - * - FBC
> - *
> - * RKL PW_0/PG_0 domains (under HW/DMC control):
> - * - PCI
> - * - clocks except port PLL
> - * - shared functions:
> - * * interrupts except pipe interrupts
> - * * MBus except PIPE_MBUS_DBOX_CTL
> - * * DBUF registers
> - * - central power except FBC
> - * - top-level GTC (DDI-level GTC is in the well associated with the
> DDI)
> - */
> -
> -#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - RKL_PW_3_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -/*
> - * DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
> - */
> -#define DG1_PW_3_POWER_DOMAINS ( \
> - TGL_PW_4_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define DG1_PW_2_POWER_DOMAINS ( \
> - DG1_PW_3_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - DG1_PW_3_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -/*
> - * XE_LPD Power Domains
> - *
> - * Previous platforms required that PG(n-1) be enabled before
> PG(n). That
> - * dependency chain turns into a dependency tree on XE_LPD:
> - *
> - * PG0
> - * |
> - * --PG1--
> - * / \
> - * PGA --PG2--
> - * / | \
> - * PGB PGC PGD
> - *
> - * Power wells must be enabled from top to bottom and disabled from
> bottom
> - * to top. This allows pipes to be power gated independently.
> - */
> -
> -#define XELPD_PW_D_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_D) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define XELPD_PW_C_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define XELPD_PW_B_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define XELPD_PW_A_POWER_DOMAINS ( \
> - BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> - BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define XELPD_PW_2_POWER_DOMAINS ( \
> - XELPD_PW_B_POWER_DOMAINS | \
> - XELPD_PW_C_POWER_DOMAINS | \
> - XELPD_PW_D_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> - BIT_ULL(POWER_DOMAIN_VGA) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_C) | \
> - BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) | \
> - BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> - BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -/*
> - * XELPD PW_1/PG_1 domains (under HW/DMC control):
> - * - DBUF function (registers are in PW0)
> - * - Transcoder A
> - * - DDI_A and DDI_B
> - *
> - * XELPD PW_0/PW_1 domains (under HW/DMC control):
> - * - PCI
> - * - Clocks except port PLL
> - * - Shared functions:
> - * * interrupts except pipe interrupts
> - * * MBus except PIPE_MBUS_DBOX_CTL
> - * * DBUF registers
> - * - Central power except FBC
> - * - Top-level GTC (DDI-level GTC is in the well associated with
> the DDI)
> - */
> -
> -#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> - XELPD_PW_2_POWER_DOMAINS | \
> - BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> - BIT_ULL(POWER_DOMAIN_MODESET) | \
> - BIT_ULL(POWER_DOMAIN_AUX_A) | \
> - BIT_ULL(POWER_DOMAIN_AUX_B) | \
> - BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> - BIT_ULL(POWER_DOMAIN_INIT))
> -
> -#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_D_XELPD)
> -#define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_E_XELPD)
> -#define XELPD_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC1)
> -#define XELPD_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC2)
> -#define XELPD_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC3)
> -#define XELPD_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC4)
> -
> -#define XELPD_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_TBT1)
> -#define XELPD_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_TBT2)
> -#define XELPD_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_TBT3)
> -#define XELPD_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_TBT4)
> -
> -#define XELPD_DDI_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PO
> RT_DDI_IO_D_XELPD)
> -#define XELPD_DDI_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PO
> RT_DDI_IO_E_XELPD)
> -#define XELPD_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_PORT_DDI_IO_TC1)
> -#define XELPD_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_PORT_DDI_IO_TC2)
> -#define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_PORT_DDI_IO_TC3)
> -#define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_PORT_DDI_IO_TC4)
> -
> -static const struct i915_power_well_desc i9xx_always_on_power_well[]
> = {
> - {
> - .name = "always-on",
> - .always_on = true,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> -};
> -
> -static const struct i915_power_well_desc i830_power_wells[] = {
> - {
> - .name = "always-on",
> - .always_on = true,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> - {
> - .name = "pipes",
> - .domains = I830_PIPES_POWER_DOMAINS,
> - .ops = &i830_pipes_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> -};
> -
> -static const struct i915_power_well_desc hsw_power_wells[] = {
> - {
> - .name = "always-on",
> - .always_on = true,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> - {
> - .name = "display",
> - .domains = HSW_DISPLAY_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = HSW_DISP_PW_GLOBAL,
> - {
> - .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
> - .hsw.has_vga = true,
> - },
> - },
> -};
> -
> -static const struct i915_power_well_desc bdw_power_wells[] = {
> - {
> - .name = "always-on",
> - .always_on = true,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> - {
> - .name = "display",
> - .domains = BDW_DISPLAY_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = HSW_DISP_PW_GLOBAL,
> - {
> - .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
> - .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> - .hsw.has_vga = true,
> - },
> - },
> -};
> -
> -static const struct i915_power_well_desc vlv_power_wells[] = {
> - {
> - .name = "always-on",
> - .always_on = true,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> - {
> - .name = "display",
> - .domains = VLV_DISPLAY_POWER_DOMAINS,
> - .ops = &vlv_display_power_well_ops,
> - .id = VLV_DISP_PW_DISP2D,
> - {
> - .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
> - },
> - },
> - {
> - .name = "dpio-tx-b-01",
> - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> - .ops = &vlv_dpio_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
> - },
> - },
> - {
> - .name = "dpio-tx-b-23",
> - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> - .ops = &vlv_dpio_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
> - },
> - },
> - {
> - .name = "dpio-tx-c-01",
> - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> - .ops = &vlv_dpio_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
> - },
> - },
> - {
> - .name = "dpio-tx-c-23",
> - .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> - VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> - .ops = &vlv_dpio_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
> - },
> - },
> - {
> - .name = "dpio-common",
> - .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
> - .ops = &vlv_dpio_cmn_power_well_ops,
> - .id = VLV_DISP_PW_DPIO_CMN_BC,
> - {
> - .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
> - },
> - },
> -};
> -
> -static const struct i915_power_well_desc chv_power_wells[] = {
> - {
> - .name = "always-on",
> - .always_on = true,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> - {
> - .name = "display",
> - /*
> - * Pipe A power well is the new disp2d well. Pipe B and
> C
> - * power wells don't actually exist. Pipe A power well
> is
> - * required for any pipe to work.
> - */
> - .domains = CHV_DISPLAY_POWER_DOMAINS,
> - .ops = &chv_pipe_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> - {
> - .name = "dpio-common-bc",
> - .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
> - .ops = &chv_dpio_cmn_power_well_ops,
> - .id = VLV_DISP_PW_DPIO_CMN_BC,
> - {
> - .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
> - },
> - },
> - {
> - .name = "dpio-common-d",
> - .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
> - .ops = &chv_dpio_cmn_power_well_ops,
> - .id = CHV_DISP_PW_DPIO_CMN_D,
> - {
> - .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
> - },
> - },
> -};
> -
> -static const struct i915_power_well_desc skl_power_wells[] = {
> - {
> - .name = "always-on",
> - .always_on = true,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> - {
> - .name = "power well 1",
> - /* Handled by the DMC firmware */
> - .always_on = true,
> - .domains = 0,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_1,
> - {
> - .hsw.idx = SKL_PW_CTL_IDX_PW_1,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "MISC IO power well",
> - /* Handled by the DMC firmware */
> - .always_on = true,
> - .domains = 0,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_MISC_IO,
> - {
> - .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
> - },
> - },
> - {
> - .name = "DC off",
> - .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> - .ops = &gen9_dc_off_power_well_ops,
> - .id = SKL_DISP_DC_OFF,
> - },
> - {
> - .name = "power well 2",
> - .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_2,
> - {
> - .hsw.idx = SKL_PW_CTL_IDX_PW_2,
> - .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> - .hsw.has_vga = true,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "DDI A/E IO power well",
> - .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
> - },
> - },
> - {
> - .name = "DDI B IO power well",
> - .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
> - },
> - },
> - {
> - .name = "DDI C IO power well",
> - .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
> - },
> - },
> - {
> - .name = "DDI D IO power well",
> - .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
> - },
> - },
> -};
> -
> -static const struct i915_power_well_desc bxt_power_wells[] = {
> - {
> - .name = "always-on",
> - .always_on = true,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> - {
> - .name = "power well 1",
> - /* Handled by the DMC firmware */
> - .always_on = true,
> - .domains = 0,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_1,
> - {
> - .hsw.idx = SKL_PW_CTL_IDX_PW_1,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "DC off",
> - .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> - .ops = &gen9_dc_off_power_well_ops,
> - .id = SKL_DISP_DC_OFF,
> - },
> - {
> - .name = "power well 2",
> - .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_2,
> - {
> - .hsw.idx = SKL_PW_CTL_IDX_PW_2,
> - .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> - .hsw.has_vga = true,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "dpio-common-a",
> - .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
> - .ops = &bxt_dpio_cmn_power_well_ops,
> - .id = BXT_DISP_PW_DPIO_CMN_A,
> - {
> - .bxt.phy = DPIO_PHY1,
> - },
> - },
> - {
> - .name = "dpio-common-bc",
> - .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
> - .ops = &bxt_dpio_cmn_power_well_ops,
> - .id = VLV_DISP_PW_DPIO_CMN_BC,
> - {
> - .bxt.phy = DPIO_PHY0,
> - },
> - },
> -};
> -
> -static const struct i915_power_well_desc glk_power_wells[] = {
> - {
> - .name = "always-on",
> - .always_on = true,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> - {
> - .name = "power well 1",
> - /* Handled by the DMC firmware */
> - .always_on = true,
> - .domains = 0,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_1,
> - {
> - .hsw.idx = SKL_PW_CTL_IDX_PW_1,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "DC off",
> - .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
> - .ops = &gen9_dc_off_power_well_ops,
> - .id = SKL_DISP_DC_OFF,
> - },
> - {
> - .name = "power well 2",
> - .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_2,
> - {
> - .hsw.idx = SKL_PW_CTL_IDX_PW_2,
> - .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> - .hsw.has_vga = true,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "dpio-common-a",
> - .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
> - .ops = &bxt_dpio_cmn_power_well_ops,
> - .id = BXT_DISP_PW_DPIO_CMN_A,
> - {
> - .bxt.phy = DPIO_PHY1,
> - },
> - },
> - {
> - .name = "dpio-common-b",
> - .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
> - .ops = &bxt_dpio_cmn_power_well_ops,
> - .id = VLV_DISP_PW_DPIO_CMN_BC,
> - {
> - .bxt.phy = DPIO_PHY0,
> - },
> - },
> - {
> - .name = "dpio-common-c",
> - .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
> - .ops = &bxt_dpio_cmn_power_well_ops,
> - .id = GLK_DISP_PW_DPIO_CMN_C,
> - {
> - .bxt.phy = DPIO_PHY2,
> - },
> - },
> - {
> - .name = "AUX A",
> - .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
> - },
> - },
> - {
> - .name = "AUX B",
> - .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
> - },
> - },
> - {
> - .name = "AUX C",
> - .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
> - },
> - },
> - {
> - .name = "DDI A IO power well",
> - .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
> - },
> - },
> - {
> - .name = "DDI B IO power well",
> - .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
> - },
> - },
> - {
> - .name = "DDI C IO power well",
> - .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
> - },
> - },
> -};
> -
> -static const struct i915_power_well_desc icl_power_wells[] = {
> - {
> - .name = "always-on",
> - .always_on = true,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> - {
> - .name = "power well 1",
> - /* Handled by the DMC firmware */
> - .always_on = true,
> - .domains = 0,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_1,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "DC off",
> - .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
> - .ops = &gen9_dc_off_power_well_ops,
> - .id = SKL_DISP_DC_OFF,
> - },
> - {
> - .name = "power well 2",
> - .domains = ICL_PW_2_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_2,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "power well 3",
> - .domains = ICL_PW_3_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_3,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_3,
> - .hsw.irq_pipe_mask = BIT(PIPE_B),
> - .hsw.has_vga = true,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "DDI A IO",
> - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> - },
> - },
> - {
> - .name = "DDI B IO",
> - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> - },
> - },
> - {
> - .name = "DDI C IO",
> - .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
> - },
> - },
> - {
> - .name = "DDI D IO",
> - .domains = ICL_DDI_IO_D_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
> - },
> - },
> - {
> - .name = "DDI E IO",
> - .domains = ICL_DDI_IO_E_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
> - },
> - },
> - {
> - .name = "DDI F IO",
> - .domains = ICL_DDI_IO_F_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
> - },
> - },
> - {
> - .name = "AUX A",
> - .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> - },
> - },
> - {
> - .name = "AUX B",
> - .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> - },
> - },
> - {
> - .name = "AUX C TC1",
> - .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> - .hsw.is_tc_tbt = false,
> - },
> - },
> - {
> - .name = "AUX D TC2",
> - .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
> - .hsw.is_tc_tbt = false,
> - },
> - },
> - {
> - .name = "AUX E TC3",
> - .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
> - .hsw.is_tc_tbt = false,
> - },
> - },
> - {
> - .name = "AUX F TC4",
> - .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
> - .hsw.is_tc_tbt = false,
> - },
> - },
> - {
> - .name = "AUX C TBT1",
> - .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
> - .hsw.is_tc_tbt = true,
> - },
> - },
> - {
> - .name = "AUX D TBT2",
> - .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
> - .hsw.is_tc_tbt = true,
> - },
> - },
> - {
> - .name = "AUX E TBT3",
> - .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
> - .hsw.is_tc_tbt = true,
> - },
> - },
> - {
> - .name = "AUX F TBT4",
> - .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
> - .hsw.is_tc_tbt = true,
> - },
> - },
> - {
> - .name = "power well 4",
> - .domains = ICL_PW_4_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_4,
> - .hsw.has_fuses = true,
> - .hsw.irq_pipe_mask = BIT(PIPE_C),
> - },
> - },
> -};
> -
> -static const struct i915_power_well_desc tgl_power_wells[] = {
> - {
> - .name = "always-on",
> - .always_on = true,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> - {
> - .name = "power well 1",
> - /* Handled by the DMC firmware */
> - .always_on = true,
> - .domains = 0,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_1,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "DC off",
> - .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
> - .ops = &gen9_dc_off_power_well_ops,
> - .id = SKL_DISP_DC_OFF,
> - },
> - {
> - .name = "power well 2",
> - .domains = TGL_PW_2_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_2,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "power well 3",
> - .domains = TGL_PW_3_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_3,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_3,
> - .hsw.irq_pipe_mask = BIT(PIPE_B),
> - .hsw.has_vga = true,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "DDI A IO",
> - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> - }
> - },
> - {
> - .name = "DDI B IO",
> - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> - }
> - },
> - {
> - .name = "DDI C IO",
> - .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
> - }
> - },
> - {
> - .name = "DDI IO TC1",
> - .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> - },
> - },
> - {
> - .name = "DDI IO TC2",
> - .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> - },
> - },
> - {
> - .name = "DDI IO TC3",
> - .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
> - },
> - },
> - {
> - .name = "DDI IO TC4",
> - .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
> - },
> - },
> - {
> - .name = "DDI IO TC5",
> - .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
> - },
> - },
> - {
> - .name = "DDI IO TC6",
> - .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
> - },
> - },
> - {
> - .name = "TC cold off",
> - .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
> - .ops = &tgl_tc_cold_off_ops,
> - .id = TGL_DISP_PW_TC_COLD_OFF,
> - },
> - {
> - .name = "AUX A",
> - .domains = TGL_AUX_A_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> - },
> - },
> - {
> - .name = "AUX B",
> - .domains = TGL_AUX_B_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> - },
> - },
> - {
> - .name = "AUX C",
> - .domains = TGL_AUX_C_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> - },
> - },
> - {
> - .name = "AUX USBC1",
> - .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> - .hsw.is_tc_tbt = false,
> - },
> - },
> - {
> - .name = "AUX USBC2",
> - .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> - .hsw.is_tc_tbt = false,
> - },
> - },
> - {
> - .name = "AUX USBC3",
> - .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
> - .hsw.is_tc_tbt = false,
> - },
> - },
> - {
> - .name = "AUX USBC4",
> - .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
> - .hsw.is_tc_tbt = false,
> - },
> - },
> - {
> - .name = "AUX USBC5",
> - .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
> - .hsw.is_tc_tbt = false,
> - },
> - },
> - {
> - .name = "AUX USBC6",
> - .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
> - .hsw.is_tc_tbt = false,
> - },
> - },
> - {
> - .name = "AUX TBT1",
> - .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
> - .hsw.is_tc_tbt = true,
> - },
> - },
> - {
> - .name = "AUX TBT2",
> - .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
> - .hsw.is_tc_tbt = true,
> - },
> - },
> - {
> - .name = "AUX TBT3",
> - .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
> - .hsw.is_tc_tbt = true,
> - },
> - },
> - {
> - .name = "AUX TBT4",
> - .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
> - .hsw.is_tc_tbt = true,
> - },
> - },
> - {
> - .name = "AUX TBT5",
> - .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
> - .hsw.is_tc_tbt = true,
> - },
> - },
> - {
> - .name = "AUX TBT6",
> - .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
> - .hsw.is_tc_tbt = true,
> - },
> - },
> - {
> - .name = "power well 4",
> - .domains = TGL_PW_4_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_4,
> - .hsw.has_fuses = true,
> - .hsw.irq_pipe_mask = BIT(PIPE_C),
> - }
> - },
> - {
> - .name = "power well 5",
> - .domains = TGL_PW_5_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_PW_5,
> - .hsw.has_fuses = true,
> - .hsw.irq_pipe_mask = BIT(PIPE_D),
> - },
> - },
> -};
> -
> -static const struct i915_power_well_desc rkl_power_wells[] = {
> - {
> - .name = "always-on",
> - .always_on = true,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> - {
> - .name = "power well 1",
> - /* Handled by the DMC firmware */
> - .always_on = true,
> - .domains = 0,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_1,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "DC off",
> - .domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> - .ops = &gen9_dc_off_power_well_ops,
> - .id = SKL_DISP_DC_OFF,
> - },
> - {
> - .name = "power well 3",
> - .domains = RKL_PW_3_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_3,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_3,
> - .hsw.irq_pipe_mask = BIT(PIPE_B),
> - .hsw.has_vga = true,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "power well 4",
> - .domains = RKL_PW_4_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_4,
> - .hsw.has_fuses = true,
> - .hsw.irq_pipe_mask = BIT(PIPE_C),
> - }
> - },
> - {
> - .name = "DDI A IO",
> - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> - }
> - },
> - {
> - .name = "DDI B IO",
> - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> - }
> - },
> - {
> - .name = "DDI IO TC1",
> - .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> - },
> - },
> - {
> - .name = "DDI IO TC2",
> - .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> - },
> - },
> - {
> - .name = "AUX A",
> - .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> - },
> - },
> - {
> - .name = "AUX B",
> - .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> - },
> - },
> - {
> - .name = "AUX USBC1",
> - .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> - },
> - },
> - {
> - .name = "AUX USBC2",
> - .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> - },
> - },
> -};
> -
> -static const struct i915_power_well_desc dg1_power_wells[] = {
> - {
> - .name = "always-on",
> - .always_on = true,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> - {
> - .name = "power well 1",
> - /* Handled by the DMC firmware */
> - .always_on = true,
> - .domains = 0,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_1,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "DC off",
> - .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
> - .ops = &gen9_dc_off_power_well_ops,
> - .id = SKL_DISP_DC_OFF,
> - },
> - {
> - .name = "power well 2",
> - .domains = DG1_PW_2_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_2,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "power well 3",
> - .domains = DG1_PW_3_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = ICL_DISP_PW_3,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_3,
> - .hsw.irq_pipe_mask = BIT(PIPE_B),
> - .hsw.has_vga = true,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "DDI A IO",
> - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> - }
> - },
> - {
> - .name = "DDI B IO",
> - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> - }
> - },
> - {
> - .name = "DDI IO TC1",
> - .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> - },
> - },
> - {
> - .name = "DDI IO TC2",
> - .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> - },
> - },
> - {
> - .name = "AUX A",
> - .domains = TGL_AUX_A_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> - },
> - },
> - {
> - .name = "AUX B",
> - .domains = TGL_AUX_B_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> - },
> - },
> - {
> - .name = "AUX USBC1",
> - .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> - .hsw.is_tc_tbt = false,
> - },
> - },
> - {
> - .name = "AUX USBC2",
> - .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> - .hsw.is_tc_tbt = false,
> - },
> - },
> - {
> - .name = "power well 4",
> - .domains = TGL_PW_4_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_4,
> - .hsw.has_fuses = true,
> - .hsw.irq_pipe_mask = BIT(PIPE_C),
> - }
> - },
> - {
> - .name = "power well 5",
> - .domains = TGL_PW_5_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_PW_5,
> - .hsw.has_fuses = true,
> - .hsw.irq_pipe_mask = BIT(PIPE_D),
> - },
> - },
> -};
> -
> -static const struct i915_power_well_desc xelpd_power_wells[] = {
> - {
> - .name = "always-on",
> - .always_on = true,
> - .domains = POWER_DOMAIN_MASK,
> - .ops = &i9xx_always_on_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - },
> - {
> - .name = "power well 1",
> - /* Handled by the DMC firmware */
> - .always_on = true,
> - .domains = 0,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_1,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "DC off",
> - .domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
> - .ops = &gen9_dc_off_power_well_ops,
> - .id = SKL_DISP_DC_OFF,
> - },
> - {
> - .name = "power well 2",
> - .domains = XELPD_PW_2_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = SKL_DISP_PW_2,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> - .hsw.has_vga = true,
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "power well A",
> - .domains = XELPD_PW_A_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = XELPD_PW_CTL_IDX_PW_A,
> - .hsw.irq_pipe_mask = BIT(PIPE_A),
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "power well B",
> - .domains = XELPD_PW_B_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = XELPD_PW_CTL_IDX_PW_B,
> - .hsw.irq_pipe_mask = BIT(PIPE_B),
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "power well C",
> - .domains = XELPD_PW_C_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = XELPD_PW_CTL_IDX_PW_C,
> - .hsw.irq_pipe_mask = BIT(PIPE_C),
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "power well D",
> - .domains = XELPD_PW_D_POWER_DOMAINS,
> - .ops = &hsw_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = XELPD_PW_CTL_IDX_PW_D,
> - .hsw.irq_pipe_mask = BIT(PIPE_D),
> - .hsw.has_fuses = true,
> - },
> - },
> - {
> - .name = "DDI A IO",
> - .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> - }
> - },
> - {
> - .name = "DDI B IO",
> - .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> - }
> - },
> - {
> - .name = "DDI C IO",
> - .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
> - }
> - },
> - {
> - .name = "DDI IO D_XELPD",
> - .domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = XELPD_PW_CTL_IDX_DDI_D,
> - }
> - },
> - {
> - .name = "DDI IO E_XELPD",
> - .domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = XELPD_PW_CTL_IDX_DDI_E,
> - }
> - },
> - {
> - .name = "DDI IO TC1",
> - .domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> - }
> - },
> - {
> - .name = "DDI IO TC2",
> - .domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> - }
> - },
> - {
> - .name = "DDI IO TC3",
> - .domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
> - }
> - },
> - {
> - .name = "DDI IO TC4",
> - .domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
> - .ops = &icl_ddi_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
> - }
> - },
> - {
> - .name = "AUX A",
> - .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> - .hsw.fixed_enable_delay = 600,
> - },
> - },
> - {
> - .name = "AUX B",
> - .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> - .hsw.fixed_enable_delay = 600,
> - },
> - },
> - {
> - .name = "AUX C",
> - .domains = TGL_AUX_C_IO_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> - .hsw.fixed_enable_delay = 600,
> - },
> - },
> - {
> - .name = "AUX D_XELPD",
> - .domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
> - .hsw.fixed_enable_delay = 600,
> - },
> - },
> - {
> - .name = "AUX E_XELPD",
> - .domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = XELPD_PW_CTL_IDX_AUX_E,
> - },
> - },
> - {
> - .name = "AUX USBC1",
> - .domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> - .hsw.fixed_enable_delay = 600,
> - },
> - },
> - {
> - .name = "AUX USBC2",
> - .domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> - },
> - },
> - {
> - .name = "AUX USBC3",
> - .domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
> - },
> - },
> - {
> - .name = "AUX USBC4",
> - .domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
> - },
> - },
> - {
> - .name = "AUX TBT1",
> - .domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
> - .hsw.is_tc_tbt = true,
> - },
> - },
> - {
> - .name = "AUX TBT2",
> - .domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
> - .hsw.is_tc_tbt = true,
> - },
> - },
> - {
> - .name = "AUX TBT3",
> - .domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
> - .hsw.is_tc_tbt = true,
> - },
> - },
> - {
> - .name = "AUX TBT4",
> - .domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
> - .ops = &icl_aux_power_well_ops,
> - .id = DISP_PW_ID_NONE,
> - {
> - .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
> - .hsw.is_tc_tbt = true,
> - },
> - },
> -};
> -
> static int
> sanitize_disable_power_well_option(const struct drm_i915_private
> *dev_priv,
> int disable_power_well)
> @@ -3089,57 +927,6 @@ static u32 get_allowed_dc_mask(const struct
> drm_i915_private *dev_priv,
> return mask;
> }
>
> -static int
> -__set_power_wells(struct i915_power_domains *power_domains,
> - const struct i915_power_well_desc *power_well_descs,
> - int power_well_descs_sz, u64 skip_mask)
> -{
> - struct drm_i915_private *i915 = container_of(power_domains,
> - struct
> drm_i915_private,
> - power_domains);
> - u64 power_well_ids = 0;
> - int power_well_count = 0;
> - int i, plt_idx = 0;
> -
> - for (i = 0; i < power_well_descs_sz; i++)
> - if (!(BIT_ULL(power_well_descs[i].id) & skip_mask))
> - power_well_count++;
> -
> - power_domains->power_well_count = power_well_count;
> - power_domains->power_wells =
> - kcalloc(power_well_count,
> - sizeof(*power_domains-
> >power_wells),
> - GFP_KERNEL);
> - if (!power_domains->power_wells)
> - return -ENOMEM;
> -
> - for (i = 0; i < power_well_descs_sz; i++) {
> - enum i915_power_well_id id = power_well_descs[i].id;
> -
> - if (BIT_ULL(id) & skip_mask)
> - continue;
> -
> - power_domains->power_wells[plt_idx++].desc =
> - &power_well_descs[i];
> -
> - if (id == DISP_PW_ID_NONE)
> - continue;
> -
> - drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) *
> 8);
> - drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id));
> - power_well_ids |= BIT_ULL(id);
> - }
> -
> - return 0;
> -}
> -
> -#define set_power_wells_mask(power_domains, __power_well_descs,
> skip_mask) \
> - __set_power_wells(power_domains, __power_well_descs, \
> - ARRAY_SIZE(__power_well_descs), skip_mask)
> -
> -#define set_power_wells(power_domains, __power_well_descs) \
> - set_power_wells_mask(power_domains, __power_well_descs, 0)
> -
> /**
> * intel_power_domains_init - initializes the power domain
> structures
> * @dev_priv: i915 device instance
> @@ -3150,7 +937,6 @@ __set_power_wells(struct i915_power_domains
> *power_domains,
> int intel_power_domains_init(struct drm_i915_private *dev_priv)
> {
> struct i915_power_domains *power_domains = &dev_priv-
> >power_domains;
> - int err;
>
> dev_priv->params.disable_power_well =
> sanitize_disable_power_well_option(dev_priv,
> @@ -3168,47 +954,7 @@ int intel_power_domains_init(struct
> drm_i915_private *dev_priv)
> INIT_DELAYED_WORK(&power_domains->async_put_work,
> intel_display_power_put_async_work);
>
> - /*
> - * The enabling order will be from lower to higher indexed
> wells,
> - * the disabling order is reversed.
> - */
> - if (!HAS_DISPLAY(dev_priv)) {
> - power_domains->power_well_count = 0;
> - err = 0;
> - } else if (DISPLAY_VER(dev_priv) >= 13) {
> - err = set_power_wells(power_domains,
> xelpd_power_wells);
> - } else if (IS_DG1(dev_priv)) {
> - err = set_power_wells(power_domains, dg1_power_wells);
> - } else if (IS_ALDERLAKE_S(dev_priv)) {
> - err = set_power_wells_mask(power_domains,
> tgl_power_wells,
> - BIT_ULL(TGL_DISP_PW_TC_COLD_
> OFF));
> - } else if (IS_ROCKETLAKE(dev_priv)) {
> - err = set_power_wells(power_domains, rkl_power_wells);
> - } else if (DISPLAY_VER(dev_priv) == 12) {
> - err = set_power_wells(power_domains, tgl_power_wells);
> - } else if (DISPLAY_VER(dev_priv) == 11) {
> - err = set_power_wells(power_domains, icl_power_wells);
> - } else if (IS_GEMINILAKE(dev_priv)) {
> - err = set_power_wells(power_domains, glk_power_wells);
> - } else if (IS_BROXTON(dev_priv)) {
> - err = set_power_wells(power_domains, bxt_power_wells);
> - } else if (DISPLAY_VER(dev_priv) == 9) {
> - err = set_power_wells(power_domains, skl_power_wells);
> - } else if (IS_CHERRYVIEW(dev_priv)) {
> - err = set_power_wells(power_domains, chv_power_wells);
> - } else if (IS_BROADWELL(dev_priv)) {
> - err = set_power_wells(power_domains, bdw_power_wells);
> - } else if (IS_HASWELL(dev_priv)) {
> - err = set_power_wells(power_domains, hsw_power_wells);
> - } else if (IS_VALLEYVIEW(dev_priv)) {
> - err = set_power_wells(power_domains, vlv_power_wells);
> - } else if (IS_I830(dev_priv)) {
> - err = set_power_wells(power_domains, i830_power_wells);
> - } else {
> - err = set_power_wells(power_domains,
> i9xx_always_on_power_well);
> - }
> -
> - return err;
> + return intel_display_power_map_init(power_domains);
> }
>
> /**
> @@ -3219,7 +965,7 @@ int intel_power_domains_init(struct
> drm_i915_private *dev_priv)
> */
> void intel_power_domains_cleanup(struct drm_i915_private *dev_priv)
> {
> - kfree(dev_priv->power_domains.power_wells);
> + intel_display_power_map_cleanup(&dev_priv->power_domains);
> }
>
> static void intel_power_domains_sync_hw(struct drm_i915_private
> *dev_priv)
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c
> b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> new file mode 100644
> index 0000000000000..97e0daec95449
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
> @@ -0,0 +1,2150 @@
> +// SPDX-License-Identifier: MIT
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#include "i915_drv.h"
> +#include "i915_reg.h"
> +
> +#include "vlv_sideband_reg.h"
> +
> +#include "intel_display_power_map.h"
> +#include "intel_display_power_well.h"
> +
> +#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
> +
> +static const struct i915_power_well_desc i9xx_always_on_power_well[]
> = {
> + {
> + .name = "always-on",
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .always_on = true,
> + .id = DISP_PW_ID_NONE,
> + },
> +};
> +
> +#define I830_PIPES_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +static const struct i915_power_well_desc i830_power_wells[] = {
> + {
> + .name = "always-on",
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .always_on = true,
> + .id = DISP_PW_ID_NONE,
> + }, {
> + .name = "pipes",
> + .domains = I830_PIPES_POWER_DOMAINS,
> + .ops = &i830_pipes_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + },
> +};
> +
> +#define HSW_DISPLAY_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +static const struct i915_power_well_desc hsw_power_wells[] = {
> + {
> + .name = "always-on",
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .always_on = true,
> + .id = DISP_PW_ID_NONE,
> + }, {
> + .name = "display",
> + .domains = HSW_DISPLAY_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = HSW_DISP_PW_GLOBAL,
> + {
> + .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
> + .hsw.has_vga = true,
> + },
> + },
> +};
> +
> +#define BDW_DISPLAY_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +static const struct i915_power_well_desc bdw_power_wells[] = {
> + {
> + .name = "always-on",
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .always_on = true,
> + .id = DISP_PW_ID_NONE,
> + }, {
> + .name = "display",
> + .domains = BDW_DISPLAY_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = HSW_DISP_PW_GLOBAL,
> + {
> + .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
> + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> + .hsw.has_vga = true,
> + },
> + },
> +};
> +
> +#define VLV_DISPLAY_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> + BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_GMBUS) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +static const struct i915_power_well_desc vlv_power_wells[] = {
> + {
> + .name = "always-on",
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .always_on = true,
> + .id = DISP_PW_ID_NONE,
> + }, {
> + .name = "display",
> + .domains = VLV_DISPLAY_POWER_DOMAINS,
> + .ops = &vlv_display_power_well_ops,
> + .id = VLV_DISP_PW_DISP2D,
> + {
> + .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
> + },
> + }, {
> + .name = "dpio-tx-b-01",
> + .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> + VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> + VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> + VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> + .ops = &vlv_dpio_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
> + },
> + }, {
> + .name = "dpio-tx-b-23",
> + .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> + VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> + VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> + VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> + .ops = &vlv_dpio_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
> + },
> + }, {
> + .name = "dpio-tx-c-01",
> + .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> + VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> + VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> + VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> + .ops = &vlv_dpio_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
> + },
> + }, {
> + .name = "dpio-tx-c-23",
> + .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
> + VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
> + VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
> + VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
> + .ops = &vlv_dpio_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
> + },
> + }, {
> + .name = "dpio-common",
> + .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
> + .ops = &vlv_dpio_cmn_power_well_ops,
> + .id = VLV_DISP_PW_DPIO_CMN_BC,
> + {
> + .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
> + },
> + },
> +};
> +
> +#define CHV_DISPLAY_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D) | \
> + BIT_ULL(POWER_DOMAIN_GMBUS) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +static const struct i915_power_well_desc chv_power_wells[] = {
> + {
> + .name = "always-on",
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .always_on = true,
> + .id = DISP_PW_ID_NONE,
> + }, {
> + .name = "display",
> + /*
> + * Pipe A power well is the new disp2d well. Pipe B and
> C
> + * power wells don't actually exist. Pipe A power well
> is
> + * required for any pipe to work.
> + */
> + .domains = CHV_DISPLAY_POWER_DOMAINS,
> + .ops = &chv_pipe_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + }, {
> + .name = "dpio-common-bc",
> + .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
> + .ops = &chv_dpio_cmn_power_well_ops,
> + .id = VLV_DISP_PW_DPIO_CMN_BC,
> + {
> + .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
> + },
> + }, {
> + .name = "dpio-common-d",
> + .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
> + .ops = &chv_dpio_cmn_power_well_ops,
> + .id = CHV_DISP_PW_DPIO_CMN_D,
> + {
> + .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
> + },
> + },
> +};
> +
> +#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +static const struct i915_power_well_desc skl_power_wells[] = {
> + {
> + .name = "always-on",
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .always_on = true,
> + .id = DISP_PW_ID_NONE,
> + }, {
> + .name = "power well 1",
> + /* Handled by the DMC firmware */
> + .domains = 0,
> + .ops = &hsw_power_well_ops,
> + .always_on = true,
> + .id = SKL_DISP_PW_1,
> + {
> + .hsw.idx = SKL_PW_CTL_IDX_PW_1,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "MISC IO power well",
> + /* Handled by the DMC firmware */
> + .domains = 0,
> + .ops = &hsw_power_well_ops,
> + .always_on = true,
> + .id = SKL_DISP_PW_MISC_IO,
> + {
> + .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
> + },
> + }, {
> + .name = "DC off",
> + .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .id = SKL_DISP_DC_OFF,
> + }, {
> + .name = "power well 2",
> + .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = SKL_DISP_PW_2,
> + {
> + .hsw.idx = SKL_PW_CTL_IDX_PW_2,
> + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> + .hsw.has_vga = true,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "DDI A/E IO power well",
> + .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
> + },
> + }, {
> + .name = "DDI B IO power well",
> + .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
> + },
> + }, {
> + .name = "DDI C IO power well",
> + .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
> + },
> + }, {
> + .name = "DDI D IO power well",
> + .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
> + },
> + },
> +};
> +
> +#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_GMBUS) | \
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +static const struct i915_power_well_desc bxt_power_wells[] = {
> + {
> + .name = "always-on",
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .always_on = true,
> + .id = DISP_PW_ID_NONE,
> + }, {
> + .name = "power well 1",
> + /* Handled by the DMC firmware */
> + .domains = 0,
> + .ops = &hsw_power_well_ops,
> + .always_on = true,
> + .id = SKL_DISP_PW_1,
> + {
> + .hsw.idx = SKL_PW_CTL_IDX_PW_1,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "DC off",
> + .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .id = SKL_DISP_DC_OFF,
> + }, {
> + .name = "power well 2",
> + .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = SKL_DISP_PW_2,
> + {
> + .hsw.idx = SKL_PW_CTL_IDX_PW_2,
> + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> + .hsw.has_vga = true,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "dpio-common-a",
> + .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
> + .ops = &bxt_dpio_cmn_power_well_ops,
> + .id = BXT_DISP_PW_DPIO_CMN_A,
> + {
> + .bxt.phy = DPIO_PHY1,
> + },
> + }, {
> + .name = "dpio-common-bc",
> + .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
> + .ops = &bxt_dpio_cmn_power_well_ops,
> + .id = VLV_DISP_PW_DPIO_CMN_BC,
> + {
> + .bxt.phy = DPIO_PHY0,
> + },
> + },
> +};
> +
> +#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_GMBUS) | \
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PO
> RT_DDI_A_IO)
> +#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PO
> RT_DDI_B_IO)
> +#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PO
> RT_DDI_C_IO)
> +
> +#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +static const struct i915_power_well_desc glk_power_wells[] = {
> + {
> + .name = "always-on",
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .always_on = true,
> + .id = DISP_PW_ID_NONE,
> + }, {
> + .name = "power well 1",
> + /* Handled by the DMC firmware */
> + .domains = 0,
> + .ops = &hsw_power_well_ops,
> + .always_on = true,
> + .id = SKL_DISP_PW_1,
> + {
> + .hsw.idx = SKL_PW_CTL_IDX_PW_1,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "DC off",
> + .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .id = SKL_DISP_DC_OFF,
> + }, {
> + .name = "power well 2",
> + .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = SKL_DISP_PW_2,
> + {
> + .hsw.idx = SKL_PW_CTL_IDX_PW_2,
> + .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
> + .hsw.has_vga = true,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "dpio-common-a",
> + .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
> + .ops = &bxt_dpio_cmn_power_well_ops,
> + .id = BXT_DISP_PW_DPIO_CMN_A,
> + {
> + .bxt.phy = DPIO_PHY1,
> + },
> + }, {
> + .name = "dpio-common-b",
> + .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
> + .ops = &bxt_dpio_cmn_power_well_ops,
> + .id = VLV_DISP_PW_DPIO_CMN_BC,
> + {
> + .bxt.phy = DPIO_PHY0,
> + },
> + }, {
> + .name = "dpio-common-c",
> + .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
> + .ops = &bxt_dpio_cmn_power_well_ops,
> + .id = GLK_DISP_PW_DPIO_CMN_C,
> + {
> + .bxt.phy = DPIO_PHY2,
> + },
> + }, {
> + .name = "AUX A",
> + .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
> + },
> + }, {
> + .name = "AUX B",
> + .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
> + },
> + }, {
> + .name = "AUX C",
> + .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
> + },
> + }, {
> + .name = "DDI A IO power well",
> + .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
> + },
> + }, {
> + .name = "DDI B IO power well",
> + .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
> + },
> + }, {
> + .name = "DDI C IO power well",
> + .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
> + },
> + },
> +};
> +
> +/*
> + * ICL PW_0/PG_0 domains (HW/DMC control):
> + * - PCI
> + * - clocks except port PLL
> + * - central power except FBC
> + * - shared functions except pipe interrupts, pipe MBUS, DBUF
> registers
> + * ICL PW_1/PG_1 domains (HW/DMC control):
> + * - DBUF function
> + * - PIPE_A and its planes, except VGA
> + * - transcoder EDP + PSR
> + * - transcoder DSI
> + * - DDI_A
> + * - FBC
> + */
> +#define ICL_PW_4_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> + /* VDSC/joining */
> +
> +#define ICL_PW_3_POWER_DOMAINS ( \
> + ICL_PW_4_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D) | \
> + BIT_ULL(POWER_DOMAIN_AUX_E) | \
> + BIT_ULL(POWER_DOMAIN_AUX_F) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
> + BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> + /*
> + * - transcoder WD
> + * - KVMR (HW control)
> + */
> +
> +#define ICL_PW_2_POWER_DOMAINS ( \
> + ICL_PW_3_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> + /*
> + * - KVMR (HW control)
> + */
> +
> +#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + ICL_PW_2_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_DC_OFF) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define ICL_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PO
> RT_DDI_A_IO)
> +#define ICL_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PO
> RT_DDI_B_IO)
> +#define ICL_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PO
> RT_DDI_C_IO)
> +#define ICL_DDI_IO_D_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PO
> RT_DDI_D_IO)
> +#define ICL_DDI_IO_E_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PO
> RT_DDI_E_IO)
> +#define ICL_DDI_IO_F_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PO
> RT_DDI_F_IO)
> +
> +#define ICL_AUX_A_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_AUX_IO_A))
> +
> +#define ICL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_B)
> +#define ICL_AUX_C_TC1_IO_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_C)
> +#define ICL_AUX_D_TC2_IO_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_D)
> +#define ICL_AUX_E_TC3_IO_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_E)
> +#define ICL_AUX_F_TC4_IO_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_F)
> +#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_C_TBT)
> +#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_D_TBT)
> +#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_E_TBT)
> +#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_F_TBT)
> +
> +static const struct i915_power_well_desc icl_power_wells[] = {
> + {
> + .name = "always-on",
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .always_on = true,
> + .id = DISP_PW_ID_NONE,
> + }, {
> + .name = "power well 1",
> + /* Handled by the DMC firmware */
> + .domains = 0,
> + .ops = &hsw_power_well_ops,
> + .always_on = true,
> + .id = SKL_DISP_PW_1,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "DC off",
> + .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .id = SKL_DISP_DC_OFF,
> + }, {
> + .name = "power well 2",
> + .domains = ICL_PW_2_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = SKL_DISP_PW_2,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "power well 3",
> + .domains = ICL_PW_3_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = ICL_DISP_PW_3,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_3,
> + .hsw.irq_pipe_mask = BIT(PIPE_B),
> + .hsw.has_vga = true,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "DDI A IO",
> + .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> + },
> + }, {
> + .name = "DDI B IO",
> + .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> + },
> + }, {
> + .name = "DDI C IO",
> + .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
> + },
> + }, {
> + .name = "DDI D IO",
> + .domains = ICL_DDI_IO_D_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
> + },
> + }, {
> + .name = "DDI E IO",
> + .domains = ICL_DDI_IO_E_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
> + },
> + }, {
> + .name = "DDI F IO",
> + .domains = ICL_DDI_IO_F_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
> + },
> + }, {
> + .name = "AUX A",
> + .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> + },
> + }, {
> + .name = "AUX B",
> + .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> + },
> + }, {
> + .name = "AUX C TC1",
> + .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> + .hsw.is_tc_tbt = false,
> + },
> + }, {
> + .name = "AUX D TC2",
> + .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
> + .hsw.is_tc_tbt = false,
> + },
> + }, {
> + .name = "AUX E TC3",
> + .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
> + .hsw.is_tc_tbt = false,
> + },
> + }, {
> + .name = "AUX F TC4",
> + .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
> + .hsw.is_tc_tbt = false,
> + },
> + }, {
> + .name = "AUX C TBT1",
> + .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
> + .hsw.is_tc_tbt = true,
> + },
> + }, {
> + .name = "AUX D TBT2",
> + .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
> + .hsw.is_tc_tbt = true,
> + },
> + }, {
> + .name = "AUX E TBT3",
> + .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
> + .hsw.is_tc_tbt = true,
> + },
> + }, {
> + .name = "AUX F TBT4",
> + .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
> + .hsw.is_tc_tbt = true,
> + },
> + }, {
> + .name = "power well 4",
> + .domains = ICL_PW_4_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_4,
> + .hsw.has_fuses = true,
> + .hsw.irq_pipe_mask = BIT(PIPE_C),
> + },
> + },
> +};
> +
> +#define TGL_PW_5_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_D) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define TGL_PW_4_POWER_DOMAINS ( \
> + TGL_PW_5_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define TGL_PW_3_POWER_DOMAINS ( \
> + TGL_PW_4_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define TGL_PW_2_POWER_DOMAINS ( \
> + TGL_PW_3_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + TGL_PW_3_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define TGL_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_I
> O_TC1)
> +#define TGL_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_I
> O_TC2)
> +#define TGL_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_I
> O_TC3)
> +#define TGL_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_I
> O_TC4)
> +#define TGL_DDI_IO_TC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_I
> O_TC5)
> +#define TGL_DDI_IO_TC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_I
> O_TC6)
> +
> +#define TGL_AUX_A_IO_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_AUX_IO_A))
> +#define TGL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
> +#define TGL_AUX_C_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
> +
> +#define TGL_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC1)
> +#define TGL_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC2)
> +#define TGL_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC3)
> +#define TGL_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC4)
> +#define TGL_AUX_IO_USBC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC5)
> +#define TGL_AUX_IO_USBC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC6)
> +
> +#define TGL_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_TBT1)
> +#define TGL_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_TBT2)
> +#define TGL_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_TBT3)
> +#define TGL_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_TBT4)
> +#define TGL_AUX_IO_TBT5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_TBT5)
> +#define TGL_AUX_IO_TBT6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_TBT6)
> +
> +#define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
> + BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
> +
> +static const struct i915_power_well_desc tgl_power_wells[] = {
> + {
> + .name = "always-on",
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .always_on = true,
> + .id = DISP_PW_ID_NONE,
> + }, {
> + .name = "power well 1",
> + /* Handled by the DMC firmware */
> + .domains = 0,
> + .ops = &hsw_power_well_ops,
> + .always_on = true,
> + .id = SKL_DISP_PW_1,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "DC off",
> + .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .id = SKL_DISP_DC_OFF,
> + }, {
> + .name = "power well 2",
> + .domains = TGL_PW_2_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = SKL_DISP_PW_2,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "power well 3",
> + .domains = TGL_PW_3_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = ICL_DISP_PW_3,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_3,
> + .hsw.irq_pipe_mask = BIT(PIPE_B),
> + .hsw.has_vga = true,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "DDI A IO",
> + .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> + }
> + }, {
> + .name = "DDI B IO",
> + .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> + }
> + }, {
> + .name = "DDI C IO",
> + .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
> + }
> + }, {
> + .name = "DDI IO TC1",
> + .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> + },
> + }, {
> + .name = "DDI IO TC2",
> + .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> + },
> + }, {
> + .name = "DDI IO TC3",
> + .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
> + },
> + }, {
> + .name = "DDI IO TC4",
> + .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
> + },
> + }, {
> + .name = "DDI IO TC5",
> + .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
> + },
> + }, {
> + .name = "DDI IO TC6",
> + .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
> + },
> + }, {
> + .name = "TC cold off",
> + .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
> + .ops = &tgl_tc_cold_off_ops,
> + .id = TGL_DISP_PW_TC_COLD_OFF,
> + }, {
> + .name = "AUX A",
> + .domains = TGL_AUX_A_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> + },
> + }, {
> + .name = "AUX B",
> + .domains = TGL_AUX_B_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> + },
> + }, {
> + .name = "AUX C",
> + .domains = TGL_AUX_C_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> + },
> + }, {
> + .name = "AUX USBC1",
> + .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> + .hsw.is_tc_tbt = false,
> + },
> + }, {
> + .name = "AUX USBC2",
> + .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> + .hsw.is_tc_tbt = false,
> + },
> + }, {
> + .name = "AUX USBC3",
> + .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
> + .hsw.is_tc_tbt = false,
> + },
> + }, {
> + .name = "AUX USBC4",
> + .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
> + .hsw.is_tc_tbt = false,
> + },
> + }, {
> + .name = "AUX USBC5",
> + .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
> + .hsw.is_tc_tbt = false,
> + },
> + }, {
> + .name = "AUX USBC6",
> + .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
> + .hsw.is_tc_tbt = false,
> + },
> + }, {
> + .name = "AUX TBT1",
> + .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
> + .hsw.is_tc_tbt = true,
> + },
> + }, {
> + .name = "AUX TBT2",
> + .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
> + .hsw.is_tc_tbt = true,
> + },
> + }, {
> + .name = "AUX TBT3",
> + .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
> + .hsw.is_tc_tbt = true,
> + },
> + }, {
> + .name = "AUX TBT4",
> + .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
> + .hsw.is_tc_tbt = true,
> + },
> + }, {
> + .name = "AUX TBT5",
> + .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
> + .hsw.is_tc_tbt = true,
> + },
> + }, {
> + .name = "AUX TBT6",
> + .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
> + .hsw.is_tc_tbt = true,
> + },
> + }, {
> + .name = "power well 4",
> + .domains = TGL_PW_4_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_4,
> + .hsw.has_fuses = true,
> + .hsw.irq_pipe_mask = BIT(PIPE_C),
> + }
> + }, {
> + .name = "power well 5",
> + .domains = TGL_PW_5_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_PW_5,
> + .hsw.has_fuses = true,
> + .hsw.irq_pipe_mask = BIT(PIPE_D),
> + },
> + },
> +};
> +
> +#define RKL_PW_4_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define RKL_PW_3_POWER_DOMAINS ( \
> + RKL_PW_4_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +/*
> + * There is no PW_2/PG_2 on RKL.
> + *
> + * RKL PW_1/PG_1 domains (under HW/DMC control):
> + * - DBUF function (note: registers are in PW0)
> + * - PIPE_A and its planes and VDSC/joining, except VGA
> + * - transcoder A
> + * - DDI_A and DDI_B
> + * - FBC
> + *
> + * RKL PW_0/PG_0 domains (under HW/DMC control):
> + * - PCI
> + * - clocks except port PLL
> + * - shared functions:
> + * * interrupts except pipe interrupts
> + * * MBus except PIPE_MBUS_DBOX_CTL
> + * * DBUF registers
> + * - central power except FBC
> + * - top-level GTC (DDI-level GTC is in the well associated with the
> DDI)
> + */
> +
> +#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + RKL_PW_3_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +static const struct i915_power_well_desc rkl_power_wells[] = {
> + {
> + .name = "always-on",
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .always_on = true,
> + .id = DISP_PW_ID_NONE,
> + }, {
> + .name = "power well 1",
> + /* Handled by the DMC firmware */
> + .domains = 0,
> + .ops = &hsw_power_well_ops,
> + .always_on = true,
> + .id = SKL_DISP_PW_1,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "DC off",
> + .domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .id = SKL_DISP_DC_OFF,
> + }, {
> + .name = "power well 3",
> + .domains = RKL_PW_3_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = ICL_DISP_PW_3,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_3,
> + .hsw.irq_pipe_mask = BIT(PIPE_B),
> + .hsw.has_vga = true,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "power well 4",
> + .domains = RKL_PW_4_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_4,
> + .hsw.has_fuses = true,
> + .hsw.irq_pipe_mask = BIT(PIPE_C),
> + }
> + }, {
> + .name = "DDI A IO",
> + .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> + }
> + }, {
> + .name = "DDI B IO",
> + .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> + }
> + }, {
> + .name = "DDI IO TC1",
> + .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> + },
> + }, {
> + .name = "DDI IO TC2",
> + .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> + },
> + }, {
> + .name = "AUX A",
> + .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> + },
> + }, {
> + .name = "AUX B",
> + .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> + },
> + }, {
> + .name = "AUX USBC1",
> + .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> + },
> + }, {
> + .name = "AUX USBC2",
> + .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> + },
> + },
> +};
> +
> +/*
> + * DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
> + */
> +#define DG1_PW_3_POWER_DOMAINS ( \
> + TGL_PW_4_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + DG1_PW_3_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define DG1_PW_2_POWER_DOMAINS ( \
> + DG1_PW_3_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +static const struct i915_power_well_desc dg1_power_wells[] = {
> + {
> + .name = "always-on",
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .always_on = true,
> + .id = DISP_PW_ID_NONE,
> + }, {
> + .name = "power well 1",
> + /* Handled by the DMC firmware */
> + .domains = 0,
> + .ops = &hsw_power_well_ops,
> + .always_on = true,
> + .id = SKL_DISP_PW_1,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "DC off",
> + .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .id = SKL_DISP_DC_OFF,
> + }, {
> + .name = "power well 2",
> + .domains = DG1_PW_2_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = SKL_DISP_PW_2,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "power well 3",
> + .domains = DG1_PW_3_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = ICL_DISP_PW_3,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_3,
> + .hsw.irq_pipe_mask = BIT(PIPE_B),
> + .hsw.has_vga = true,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "DDI A IO",
> + .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> + }
> + }, {
> + .name = "DDI B IO",
> + .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> + }
> + }, {
> + .name = "DDI IO TC1",
> + .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> + },
> + }, {
> + .name = "DDI IO TC2",
> + .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> + },
> + }, {
> + .name = "AUX A",
> + .domains = TGL_AUX_A_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> + },
> + }, {
> + .name = "AUX B",
> + .domains = TGL_AUX_B_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> + },
> + }, {
> + .name = "AUX USBC1",
> + .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> + .hsw.is_tc_tbt = false,
> + },
> + }, {
> + .name = "AUX USBC2",
> + .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> + .hsw.is_tc_tbt = false,
> + },
> + }, {
> + .name = "power well 4",
> + .domains = TGL_PW_4_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_4,
> + .hsw.has_fuses = true,
> + .hsw.irq_pipe_mask = BIT(PIPE_C),
> + }
> + }, {
> + .name = "power well 5",
> + .domains = TGL_PW_5_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_PW_5,
> + .hsw.has_fuses = true,
> + .hsw.irq_pipe_mask = BIT(PIPE_D),
> + },
> + },
> +};
> +
> +/*
> + * XE_LPD Power Domains
> + *
> + * Previous platforms required that PG(n-1) be enabled before
> PG(n). That
> + * dependency chain turns into a dependency tree on XE_LPD:
> + *
> + * PG0
> + * |
> + * --PG1--
> + * / \
> + * PGA --PG2--
> + * / | \
> + * PGB PGC PGD
> + *
> + * Power wells must be enabled from top to bottom and disabled from
> bottom
> + * to top. This allows pipes to be power gated independently.
> + */
> +
> +#define XELPD_PW_D_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_D) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define XELPD_PW_C_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_C) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define XELPD_PW_B_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_B) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define XELPD_PW_A_POWER_DOMAINS ( \
> + BIT_ULL(POWER_DOMAIN_PIPE_A) | \
> + BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define XELPD_PW_2_POWER_DOMAINS ( \
> + XELPD_PW_B_POWER_DOMAINS | \
> + XELPD_PW_C_POWER_DOMAINS | \
> + XELPD_PW_D_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
> + BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
> + BIT_ULL(POWER_DOMAIN_VGA) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
> + BIT_ULL(POWER_DOMAIN_AUX_C) | \
> + BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) | \
> + BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
> + BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
> + BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +/*
> + * XELPD PW_1/PG_1 domains (under HW/DMC control):
> + * - DBUF function (registers are in PW0)
> + * - Transcoder A
> + * - DDI_A and DDI_B
> + *
> + * XELPD PW_0/PW_1 domains (under HW/DMC control):
> + * - PCI
> + * - Clocks except port PLL
> + * - Shared functions:
> + * * interrupts except pipe interrupts
> + * * MBus except PIPE_MBUS_DBOX_CTL
> + * * DBUF registers
> + * - Central power except FBC
> + * - Top-level GTC (DDI-level GTC is in the well associated with
> the DDI)
> + */
> +
> +#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
> + XELPD_PW_2_POWER_DOMAINS | \
> + BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
> + BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
> + BIT_ULL(POWER_DOMAIN_AUX_A) | \
> + BIT_ULL(POWER_DOMAIN_AUX_B) | \
> + BIT_ULL(POWER_DOMAIN_MODESET) | \
> + BIT_ULL(POWER_DOMAIN_INIT))
> +
> +#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_D_XELPD)
> +#define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_E_XELPD)
> +#define XELPD_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC1)
> +#define XELPD_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC2)
> +#define XELPD_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC3)
> +#define XELPD_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AU
> X_USBC4)
> +
> +#define XELPD_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_TBT1)
> +#define XELPD_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_TBT2)
> +#define XELPD_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_TBT3)
> +#define XELPD_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_AUX_TBT4)
> +
> +#define XELPD_DDI_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PO
> RT_DDI_IO_D_XELPD)
> +#define XELPD_DDI_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PO
> RT_DDI_IO_E_XELPD)
> +#define XELPD_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_PORT_DDI_IO_TC1)
> +#define XELPD_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_PORT_DDI_IO_TC2)
> +#define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_PORT_DDI_IO_TC3)
> +#define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_D
> OMAIN_PORT_DDI_IO_TC4)
> +
> +static const struct i915_power_well_desc xelpd_power_wells[] = {
> + {
> + .name = "always-on",
> + .domains = POWER_DOMAIN_MASK,
> + .ops = &i9xx_always_on_power_well_ops,
> + .always_on = true,
> + .id = DISP_PW_ID_NONE,
> + }, {
> + .name = "power well 1",
> + /* Handled by the DMC firmware */
> + .domains = 0,
> + .ops = &hsw_power_well_ops,
> + .always_on = true,
> + .id = SKL_DISP_PW_1,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_1,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "DC off",
> + .domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
> + .ops = &gen9_dc_off_power_well_ops,
> + .id = SKL_DISP_DC_OFF,
> + }, {
> + .name = "power well 2",
> + .domains = XELPD_PW_2_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = SKL_DISP_PW_2,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_PW_2,
> + .hsw.has_vga = true,
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "power well A",
> + .domains = XELPD_PW_A_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_A,
> + .hsw.irq_pipe_mask = BIT(PIPE_A),
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "power well B",
> + .domains = XELPD_PW_B_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_B,
> + .hsw.irq_pipe_mask = BIT(PIPE_B),
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "power well C",
> + .domains = XELPD_PW_C_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_C,
> + .hsw.irq_pipe_mask = BIT(PIPE_C),
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "power well D",
> + .domains = XELPD_PW_D_POWER_DOMAINS,
> + .ops = &hsw_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = XELPD_PW_CTL_IDX_PW_D,
> + .hsw.irq_pipe_mask = BIT(PIPE_D),
> + .hsw.has_fuses = true,
> + },
> + }, {
> + .name = "DDI A IO",
> + .domains = ICL_DDI_IO_A_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
> + }
> + }, {
> + .name = "DDI B IO",
> + .domains = ICL_DDI_IO_B_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
> + }
> + }, {
> + .name = "DDI C IO",
> + .domains = ICL_DDI_IO_C_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
> + }
> + }, {
> + .name = "DDI IO D_XELPD",
> + .domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = XELPD_PW_CTL_IDX_DDI_D,
> + }
> + }, {
> + .name = "DDI IO E_XELPD",
> + .domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = XELPD_PW_CTL_IDX_DDI_E,
> + }
> + }, {
> + .name = "DDI IO TC1",
> + .domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
> + }
> + }, {
> + .name = "DDI IO TC2",
> + .domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
> + }
> + }, {
> + .name = "DDI IO TC3",
> + .domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
> + }
> + }, {
> + .name = "DDI IO TC4",
> + .domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
> + .ops = &icl_ddi_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
> + }
> + }, {
> + .name = "AUX A",
> + .domains = ICL_AUX_A_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
> + .hsw.fixed_enable_delay = 600,
> + },
> + }, {
> + .name = "AUX B",
> + .domains = ICL_AUX_B_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
> + .hsw.fixed_enable_delay = 600,
> + },
> + }, {
> + .name = "AUX C",
> + .domains = TGL_AUX_C_IO_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
> + .hsw.fixed_enable_delay = 600,
> + },
> + }, {
> + .name = "AUX D_XELPD",
> + .domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
> + .hsw.fixed_enable_delay = 600,
> + },
> + }, {
> + .name = "AUX E_XELPD",
> + .domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = XELPD_PW_CTL_IDX_AUX_E,
> + },
> + }, {
> + .name = "AUX USBC1",
> + .domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
> + .hsw.fixed_enable_delay = 600,
> + },
> + }, {
> + .name = "AUX USBC2",
> + .domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
> + },
> + }, {
> + .name = "AUX USBC3",
> + .domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
> + },
> + }, {
> + .name = "AUX USBC4",
> + .domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
> + },
> + }, {
> + .name = "AUX TBT1",
> + .domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
> + .hsw.is_tc_tbt = true,
> + },
> + }, {
> + .name = "AUX TBT2",
> + .domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
> + .hsw.is_tc_tbt = true,
> + },
> + }, {
> + .name = "AUX TBT3",
> + .domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
> + .hsw.is_tc_tbt = true,
> + },
> + }, {
> + .name = "AUX TBT4",
> + .domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
> + .ops = &icl_aux_power_well_ops,
> + .id = DISP_PW_ID_NONE,
> + {
> + .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
> + .hsw.is_tc_tbt = true,
> + },
> + },
> +};
> +
> +static int
> +__set_power_wells(struct i915_power_domains *power_domains,
> + const struct i915_power_well_desc *power_well_descs,
> + int power_well_descs_sz, u64 skip_mask)
> +{
> + struct drm_i915_private *i915 = container_of(power_domains,
> + struct
> drm_i915_private,
> + power_domains);
> + u64 power_well_ids = 0;
> + int power_well_count = 0;
> + int i, plt_idx = 0;
> +
> + for (i = 0; i < power_well_descs_sz; i++)
> + if (!(BIT_ULL(power_well_descs[i].id) & skip_mask))
> + power_well_count++;
> +
> + power_domains->power_well_count = power_well_count;
> + power_domains->power_wells =
> + kcalloc(power_well_count,
> + sizeof(*power_domains-
> >power_wells),
> + GFP_KERNEL);
> + if (!power_domains->power_wells)
> + return -ENOMEM;
> +
> + for (i = 0; i < power_well_descs_sz; i++) {
> + enum i915_power_well_id id = power_well_descs[i].id;
> +
> + if (BIT_ULL(id) & skip_mask)
> + continue;
> +
> + power_domains->power_wells[plt_idx++].desc =
> + &power_well_descs[i];
> +
> + if (id == DISP_PW_ID_NONE)
> + continue;
> +
> + drm_WARN_ON(&i915->drm, id >= sizeof(power_well_ids) *
> 8);
> + drm_WARN_ON(&i915->drm, power_well_ids & BIT_ULL(id));
> + power_well_ids |= BIT_ULL(id);
> + }
> +
> + return 0;
> +}
> +
> +#define set_power_wells_mask(power_domains, __power_well_descs,
> skip_mask) \
> + __set_power_wells(power_domains, __power_well_descs, \
> + ARRAY_SIZE(__power_well_descs), skip_mask)
> +
> +#define set_power_wells(power_domains, __power_well_descs) \
> + set_power_wells_mask(power_domains, __power_well_descs, 0)
> +
> +/**
> + * intel_display_power_map_init - initialize power domain -> power
> well mappings
> + * @power_domains: power domain state
> + *
> + * Creates all the power wells for the current platform, initializes
> the
> + * dynamic state for them and initializes the mapping of each power
> well to
> + * all the power domains the power well belongs to.
> + */
> +int intel_display_power_map_init(struct i915_power_domains
> *power_domains)
> +{
> + struct drm_i915_private *i915 = container_of(power_domains,
> + struct
> drm_i915_private,
> + power_domains);
> + /*
> + * The enabling order will be from lower to higher indexed
> wells,
> + * the disabling order is reversed.
> + */
> + if (!HAS_DISPLAY(i915)) {
> + power_domains->power_well_count = 0;
> + return 0;
> + }
> +
> + if (DISPLAY_VER(i915) >= 13)
> + return set_power_wells(power_domains,
> xelpd_power_wells);
> + else if (IS_DG1(i915))
> + return set_power_wells(power_domains, dg1_power_wells);
> + else if (IS_ALDERLAKE_S(i915))
> + return set_power_wells_mask(power_domains,
> tgl_power_wells,
> + BIT_ULL(TGL_DISP_PW_TC_COLD_
> OFF));
> + else if (IS_ROCKETLAKE(i915))
> + return set_power_wells(power_domains, rkl_power_wells);
> + else if (DISPLAY_VER(i915) == 12)
> + return set_power_wells(power_domains, tgl_power_wells);
> + else if (DISPLAY_VER(i915) == 11)
> + return set_power_wells(power_domains, icl_power_wells);
> + else if (IS_GEMINILAKE(i915))
> + return set_power_wells(power_domains, glk_power_wells);
> + else if (IS_BROXTON(i915))
> + return set_power_wells(power_domains, bxt_power_wells);
> + else if (DISPLAY_VER(i915) == 9)
> + return set_power_wells(power_domains, skl_power_wells);
> + else if (IS_CHERRYVIEW(i915))
> + return set_power_wells(power_domains, chv_power_wells);
> + else if (IS_BROADWELL(i915))
> + return set_power_wells(power_domains, bdw_power_wells);
> + else if (IS_HASWELL(i915))
> + return set_power_wells(power_domains, hsw_power_wells);
> + else if (IS_VALLEYVIEW(i915))
> + return set_power_wells(power_domains, vlv_power_wells);
> + else if (IS_I830(i915))
> + return set_power_wells(power_domains,
> i830_power_wells);
> + else
> + return set_power_wells(power_domains,
> i9xx_always_on_power_well);
> +}
> +
> +/**
> + * intel_display_power_map_cleanup - clean up power domain -> power
> well mappings
> + * @power_domains: power domain state
> + *
> + * Cleans up all the state that was initialized by
> intel_display_power_map_init().
> + */
> +void intel_display_power_map_cleanup(struct i915_power_domains
> *power_domains)
> +{
> + kfree(power_domains->power_wells);
> +}
> diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.h
> b/drivers/gpu/drm/i915/display/intel_display_power_map.h
> new file mode 100644
> index 0000000000000..da8f7055a44c6
> --- /dev/null
> +++ b/drivers/gpu/drm/i915/display/intel_display_power_map.h
> @@ -0,0 +1,14 @@
> +/* SPDX-License-Identifier: MIT */
> +/*
> + * Copyright © 2022 Intel Corporation
> + */
> +
> +#ifndef __INTEL_DISPLAY_POWER_MAP_H__
> +#define __INTEL_DISPLAY_POWER_MAP_H__
> +
> +struct i915_power_domains;
> +
> +int intel_display_power_map_init(struct i915_power_domains
> *power_domains);
> +void intel_display_power_map_cleanup(struct i915_power_domains
> *power_domains);
> +
> +#endif
^ permalink raw reply [flat|nested] 29+ messages in thread
* [Intel-gfx] [PATCH v3 04/18] drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (2 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 03/18] drm/i915: Move the power domain->well mappings to intel_display_power_map.c Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 05/18] drm/i915: Move the HSW power well flags " Imre Deak
` (21 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
The DG2 fixed delay duration is always 600usec, so save some space in
the power well descriptors by converting the parameter to a flag. While
at it also use a bitfield for both the always_on and fixed_enable_delay
flag.
This change also lets simplifying the definiton of power wells sharing
the same flags in an upcoming patch.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
.../gpu/drm/i915/display/intel_display_power_map.c | 10 +++++-----
.../drm/i915/display/intel_display_power_well.c | 5 ++---
.../drm/i915/display/intel_display_power_well.h | 14 +++++++-------
3 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 97e0daec95449..e1824936a998f 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1920,37 +1920,37 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.name = "AUX A",
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX B",
.domains = ICL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX C",
.domains = TGL_AUX_C_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX D_XELPD",
.domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX E_XELPD",
@@ -1964,10 +1964,10 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.name = "AUX USBC1",
.domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- .hsw.fixed_enable_delay = 600,
},
}, {
.name = "AUX USBC2",
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index a92bb807f1972..0e13c15edfdd2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -242,15 +242,14 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
int pw_idx = power_well->desc->hsw.idx;
- int enable_delay = power_well->desc->hsw.fixed_enable_delay;
/*
* For some power wells we're not supposed to watch the status bit for
* an ack, but rather just wait a fixed amount of time and then
* proceed. This is only used on DG2.
*/
- if (IS_DG2(dev_priv) && enable_delay) {
- usleep_range(enable_delay, 2 * enable_delay);
+ if (IS_DG2(dev_priv) && power_well->desc->fixed_enable_delay) {
+ usleep_range(600, 1200);
return;
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index c4a8a3d728e06..cb4681d0ffc6a 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -50,8 +50,14 @@ enum i915_power_well_id {
struct i915_power_well_desc {
const char *name;
- bool always_on;
u64 domains;
+ u8 always_on:1;
+ /*
+ * Instead of waiting for the status bit to ack enables,
+ * just wait a specific amount of time and then consider
+ * the well enabled.
+ */
+ u8 fixed_enable_delay:1;
/* unique identifier for this power well */
enum i915_power_well_id id;
/*
@@ -77,12 +83,6 @@ struct i915_power_well_desc {
u8 idx;
/* Mask of pipes whose IRQ logic is backed by the pw */
u8 irq_pipe_mask;
- /*
- * Instead of waiting for the status bit to ack enables,
- * just wait a specific amount of time and then consider
- * the well enabled.
- */
- u16 fixed_enable_delay;
/* The pw is backing the VGA functionality */
bool has_vga:1;
bool has_fuses:1;
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 05/18] drm/i915: Move the HSW power well flags to a common bitfield
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (3 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 04/18] drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 06/18] drm/i915: Rename the power domain names to end with pipes/ports Imre Deak
` (20 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
Save some space by grouping the HSW power well descriptor flags along
with other flags in one bitfield.
This change also lets simplifying the definition of power well
descriptors sharing the same flags in an upcoming patch.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
.../i915/display/intel_display_power_map.c | 166 +++++++++---------
.../i915/display/intel_display_power_well.c | 16 +-
.../i915/display/intel_display_power_well.h | 25 +--
3 files changed, 104 insertions(+), 103 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index e1824936a998f..d566e638ac9b6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -76,10 +76,10 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
.name = "display",
.domains = HSW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
.id = HSW_DISP_PW_GLOBAL,
{
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
- .hsw.has_vga = true,
},
},
};
@@ -112,11 +112,11 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
.name = "display",
.domains = BDW_DISPLAY_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.id = HSW_DISP_PW_GLOBAL,
{
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
},
},
};
@@ -368,10 +368,10 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "MISC IO power well",
@@ -392,12 +392,12 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.name = "power well 2",
.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "DDI A/E IO power well",
@@ -484,10 +484,10 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -498,12 +498,12 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.name = "power well 2",
.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "dpio-common-a",
@@ -594,10 +594,10 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -608,12 +608,12 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.name = "power well 2",
.domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
+ .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
- .hsw.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "dpio-common-a",
@@ -789,10 +789,10 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -803,21 +803,21 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "power well 2",
.domains = ICL_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_fuses = true,
},
}, {
.name = "power well 3",
.domains = ICL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .irq_pipe_mask = BIT(PIPE_B),
+ .has_fuses = true,
.id = ICL_DISP_PW_3,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "DDI A IO",
@@ -887,83 +887,83 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.name = "AUX C TC1",
.domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX D TC2",
.domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_D,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX E TC3",
.domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_E,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX F TC4",
.domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_F,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX C TBT1",
.domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX D TBT2",
.domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX E TBT3",
.domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX F TBT4",
.domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "power well 4",
.domains = ICL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_C),
+ .has_fuses = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
},
},
};
@@ -1077,10 +1077,10 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -1091,21 +1091,21 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.name = "power well 2",
.domains = TGL_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_fuses = true,
},
}, {
.name = "power well 3",
.domains = TGL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .irq_pipe_mask = BIT(PIPE_B),
+ .has_fuses = true,
.id = ICL_DISP_PW_3,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "DDI A IO",
@@ -1212,129 +1212,129 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.name = "AUX USBC1",
.domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX USBC2",
.domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX USBC3",
.domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX USBC4",
.domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX USBC5",
.domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX USBC6",
.domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX TBT1",
.domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT2",
.domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT3",
.domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT4",
.domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT5",
.domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT6",
.domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "power well 4",
.domains = TGL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
+ .irq_pipe_mask = BIT(PIPE_C),
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
}
}, {
.name = "power well 5",
.domains = TGL_PW_5_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
+ .irq_pipe_mask = BIT(PIPE_D),
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_PW_5,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_D),
},
},
};
@@ -1400,10 +1400,10 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -1414,22 +1414,22 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.name = "power well 3",
.domains = RKL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_B),
+ .has_vga = true,
+ .has_fuses = true,
.id = ICL_DISP_PW_3,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "power well 4",
.domains = RKL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
+ .irq_pipe_mask = BIT(PIPE_C),
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
}
}, {
.name = "DDI A IO",
@@ -1540,10 +1540,10 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -1554,21 +1554,21 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.name = "power well 2",
.domains = DG1_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_fuses = true,
},
}, {
.name = "power well 3",
.domains = DG1_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_B),
+ .has_vga = true,
+ .has_fuses = true,
.id = ICL_DISP_PW_3,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "DDI A IO",
@@ -1622,39 +1622,39 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.name = "AUX USBC1",
.domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "AUX USBC2",
.domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- .hsw.is_tc_tbt = false,
},
}, {
.name = "power well 4",
.domains = TGL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
+ .irq_pipe_mask = BIT(PIPE_C),
.id = DISP_PW_ID_NONE,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
}
}, {
.name = "power well 5",
.domains = TGL_PW_5_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_fuses = true,
+ .irq_pipe_mask = BIT(PIPE_D),
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_PW_5,
- .hsw.has_fuses = true,
- .hsw.irq_pipe_mask = BIT(PIPE_D),
},
},
};
@@ -1784,10 +1784,10 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.domains = 0,
.ops = &hsw_power_well_ops,
.always_on = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_1,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .hsw.has_fuses = true,
},
}, {
.name = "DC off",
@@ -1798,51 +1798,51 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.name = "power well 2",
.domains = XELPD_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .has_vga = true,
+ .has_fuses = true,
.id = SKL_DISP_PW_2,
{
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
- .hsw.has_vga = true,
- .hsw.has_fuses = true,
},
}, {
.name = "power well A",
.domains = XELPD_PW_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_A),
+ .has_fuses = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = XELPD_PW_CTL_IDX_PW_A,
- .hsw.irq_pipe_mask = BIT(PIPE_A),
- .hsw.has_fuses = true,
},
}, {
.name = "power well B",
.domains = XELPD_PW_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_B),
+ .has_fuses = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = XELPD_PW_CTL_IDX_PW_B,
- .hsw.irq_pipe_mask = BIT(PIPE_B),
- .hsw.has_fuses = true,
},
}, {
.name = "power well C",
.domains = XELPD_PW_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_C),
+ .has_fuses = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = XELPD_PW_CTL_IDX_PW_C,
- .hsw.irq_pipe_mask = BIT(PIPE_C),
- .hsw.has_fuses = true,
},
}, {
.name = "power well D",
.domains = XELPD_PW_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
+ .irq_pipe_mask = BIT(PIPE_D),
+ .has_fuses = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = XELPD_PW_CTL_IDX_PW_D,
- .hsw.irq_pipe_mask = BIT(PIPE_D),
- .hsw.has_fuses = true,
},
}, {
.name = "DDI A IO",
@@ -1997,37 +1997,37 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.name = "AUX TBT1",
.domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT2",
.domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT3",
.domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
- .hsw.is_tc_tbt = true,
},
}, {
.name = "AUX TBT4",
.domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
+ .is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
{
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
- .hsw.is_tc_tbt = true,
},
},
};
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 0e13c15edfdd2..8d9bc7a654106 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -196,8 +196,8 @@ static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well)
{
int pw_idx = power_well->desc->hsw.idx;
- return power_well->desc->hsw.is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
- ICL_AUX_PW_TO_CH(pw_idx);
+ return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
+ ICL_AUX_PW_TO_CH(pw_idx);
}
static struct intel_digital_port *
@@ -325,7 +325,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
int pw_idx = power_well->desc->hsw.idx;
u32 val;
- if (power_well->desc->hsw.has_fuses) {
+ if (power_well->desc->has_fuses) {
enum skl_power_gate pg;
pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
@@ -352,7 +352,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
hsw_wait_for_power_well_enable(dev_priv, power_well, false);
- if (power_well->desc->hsw.has_fuses) {
+ if (power_well->desc->has_fuses) {
enum skl_power_gate pg;
pg = DISPLAY_VER(dev_priv) >= 11 ? ICL_PW_CTL_IDX_TO_PG(pw_idx) :
@@ -361,8 +361,8 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
}
hsw_power_well_post_enable(dev_priv,
- power_well->desc->hsw.irq_pipe_mask,
- power_well->desc->hsw.has_vga);
+ power_well->desc->irq_pipe_mask,
+ power_well->desc->has_vga);
}
static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
@@ -373,7 +373,7 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
u32 val;
hsw_power_well_pre_disable(dev_priv,
- power_well->desc->hsw.irq_pipe_mask);
+ power_well->desc->irq_pipe_mask);
val = intel_de_read(dev_priv, regs->driver);
intel_de_write(dev_priv, regs->driver,
@@ -490,7 +490,7 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
enum aux_ch aux_ch = icl_aux_pw_to_ch(power_well);
struct intel_digital_port *dig_port = aux_ch_to_digital_port(dev_priv, aux_ch);
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- bool is_tbt = power_well->desc->hsw.is_tc_tbt;
+ bool is_tbt = power_well->desc->is_tc_tbt;
bool timeout_expected;
u32 val;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index cb4681d0ffc6a..26fe9e1048bcc 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -51,13 +51,24 @@ enum i915_power_well_id {
struct i915_power_well_desc {
const char *name;
u64 domains;
- u8 always_on:1;
+ /* Mask of pipes whose IRQ logic is backed by the pw */
+ u16 irq_pipe_mask:4;
+ u16 always_on:1;
/*
* Instead of waiting for the status bit to ack enables,
* just wait a specific amount of time and then consider
* the well enabled.
*/
- u8 fixed_enable_delay:1;
+ u16 fixed_enable_delay:1;
+ /* The pw is backing the VGA functionality */
+ u16 has_vga:1;
+ u16 has_fuses:1;
+ /*
+ * The pw is for an ICL+ TypeC PHY port in
+ * Thunderbolt mode.
+ */
+ u16 is_tc_tbt:1;
+
/* unique identifier for this power well */
enum i915_power_well_id id;
/*
@@ -81,16 +92,6 @@ struct i915_power_well_desc {
* constrol/status registers.
*/
u8 idx;
- /* Mask of pipes whose IRQ logic is backed by the pw */
- u8 irq_pipe_mask;
- /* The pw is backing the VGA functionality */
- bool has_vga:1;
- bool has_fuses:1;
- /*
- * The pw is for an ICL+ TypeC PHY port in
- * Thunderbolt mode.
- */
- bool is_tc_tbt:1;
} hsw;
};
const struct i915_power_well_ops *ops;
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 06/18] drm/i915: Rename the power domain names to end with pipes/ports
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (4 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 05/18] drm/i915: Move the HSW power well flags " Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 07/18] drm/i915: Sanitize the power well names Imre Deak
` (19 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
Make all power domain names end with the pipe/port instance for
consistency.
No functional changes.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/icl_dsi.c | 8 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 2 +-
drivers/gpu/drm/i915/display/intel_display.c | 34 ++--
.../drm/i915/display/intel_display_power.c | 116 +++++------
.../drm/i915/display/intel_display_power.h | 66 +++----
.../i915/display/intel_display_power_map.c | 184 +++++++++---------
6 files changed, 205 insertions(+), 205 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/icl_dsi.c b/drivers/gpu/drm/i915/display/icl_dsi.c
index 44f4c65522b97..019a98bbb769e 100644
--- a/drivers/gpu/drm/i915/display/icl_dsi.c
+++ b/drivers/gpu/drm/i915/display/icl_dsi.c
@@ -399,8 +399,8 @@ static void get_dsi_io_power_domains(struct drm_i915_private *dev_priv,
intel_dsi->io_wakeref[port] =
intel_display_power_get(dev_priv,
port == PORT_A ?
- POWER_DOMAIN_PORT_DDI_A_IO :
- POWER_DOMAIN_PORT_DDI_B_IO);
+ POWER_DOMAIN_PORT_DDI_IO_A :
+ POWER_DOMAIN_PORT_DDI_IO_B);
}
}
@@ -1425,8 +1425,8 @@ static void gen11_dsi_disable_io_power(struct intel_encoder *encoder)
wakeref = fetch_and_zero(&intel_dsi->io_wakeref[port]);
intel_display_power_put(dev_priv,
port == PORT_A ?
- POWER_DOMAIN_PORT_DDI_A_IO :
- POWER_DOMAIN_PORT_DDI_B_IO,
+ POWER_DOMAIN_PORT_DDI_IO_A :
+ POWER_DOMAIN_PORT_DDI_IO_B,
wakeref);
}
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index dc208df829f16..afbb794d1f586 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -4499,7 +4499,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
}
drm_WARN_ON(&dev_priv->drm, port > PORT_I);
- dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_A_IO +
+ dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_IO_A +
port - PORT_A;
if (init_dp) {
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 28bfb73ae6471..28ba0319357e6 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2190,23 +2190,23 @@ enum intel_display_power_domain intel_port_to_power_domain(enum port port)
{
switch (port) {
case PORT_A:
- return POWER_DOMAIN_PORT_DDI_A_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_A;
case PORT_B:
- return POWER_DOMAIN_PORT_DDI_B_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_B;
case PORT_C:
- return POWER_DOMAIN_PORT_DDI_C_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_C;
case PORT_D:
- return POWER_DOMAIN_PORT_DDI_D_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_D;
case PORT_E:
- return POWER_DOMAIN_PORT_DDI_E_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_E;
case PORT_F:
- return POWER_DOMAIN_PORT_DDI_F_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_F;
case PORT_G:
- return POWER_DOMAIN_PORT_DDI_G_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_G;
case PORT_H:
- return POWER_DOMAIN_PORT_DDI_H_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_H;
case PORT_I:
- return POWER_DOMAIN_PORT_DDI_I_LANES;
+ return POWER_DOMAIN_PORT_DDI_LANES_I;
default:
MISSING_CASE(port);
return POWER_DOMAIN_PORT_OTHER;
@@ -2219,22 +2219,22 @@ intel_aux_power_domain(struct intel_digital_port *dig_port)
if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
switch (dig_port->aux_ch) {
case AUX_CH_C:
- return POWER_DOMAIN_AUX_C_TBT;
+ return POWER_DOMAIN_AUX_TBT_C;
case AUX_CH_D:
- return POWER_DOMAIN_AUX_D_TBT;
+ return POWER_DOMAIN_AUX_TBT_D;
case AUX_CH_E:
- return POWER_DOMAIN_AUX_E_TBT;
+ return POWER_DOMAIN_AUX_TBT_E;
case AUX_CH_F:
- return POWER_DOMAIN_AUX_F_TBT;
+ return POWER_DOMAIN_AUX_TBT_F;
case AUX_CH_G:
- return POWER_DOMAIN_AUX_G_TBT;
+ return POWER_DOMAIN_AUX_TBT_G;
case AUX_CH_H:
- return POWER_DOMAIN_AUX_H_TBT;
+ return POWER_DOMAIN_AUX_TBT_H;
case AUX_CH_I:
- return POWER_DOMAIN_AUX_I_TBT;
+ return POWER_DOMAIN_AUX_TBT_I;
default:
MISSING_CASE(dig_port->aux_ch);
- return POWER_DOMAIN_AUX_C_TBT;
+ return POWER_DOMAIN_AUX_TBT_C;
}
}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e999433589715..e524b24c329a2 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -44,14 +44,14 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PIPE_C";
case POWER_DOMAIN_PIPE_D:
return "PIPE_D";
- case POWER_DOMAIN_PIPE_A_PANEL_FITTER:
- return "PIPE_A_PANEL_FITTER";
- case POWER_DOMAIN_PIPE_B_PANEL_FITTER:
- return "PIPE_B_PANEL_FITTER";
- case POWER_DOMAIN_PIPE_C_PANEL_FITTER:
- return "PIPE_C_PANEL_FITTER";
- case POWER_DOMAIN_PIPE_D_PANEL_FITTER:
- return "PIPE_D_PANEL_FITTER";
+ case POWER_DOMAIN_PIPE_PANEL_FITTER_A:
+ return "PIPE_PANEL_FITTER_A";
+ case POWER_DOMAIN_PIPE_PANEL_FITTER_B:
+ return "PIPE_PANEL_FITTER_B";
+ case POWER_DOMAIN_PIPE_PANEL_FITTER_C:
+ return "PIPE_PANEL_FITTER_C";
+ case POWER_DOMAIN_PIPE_PANEL_FITTER_D:
+ return "PIPE_PANEL_FITTER_D";
case POWER_DOMAIN_TRANSCODER_A:
return "TRANSCODER_A";
case POWER_DOMAIN_TRANSCODER_B:
@@ -68,42 +68,42 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "TRANSCODER_DSI_C";
case POWER_DOMAIN_TRANSCODER_VDSC_PW2:
return "TRANSCODER_VDSC_PW2";
- case POWER_DOMAIN_PORT_DDI_A_LANES:
- return "PORT_DDI_A_LANES";
- case POWER_DOMAIN_PORT_DDI_B_LANES:
- return "PORT_DDI_B_LANES";
- case POWER_DOMAIN_PORT_DDI_C_LANES:
- return "PORT_DDI_C_LANES";
- case POWER_DOMAIN_PORT_DDI_D_LANES:
- return "PORT_DDI_D_LANES";
- case POWER_DOMAIN_PORT_DDI_E_LANES:
- return "PORT_DDI_E_LANES";
- case POWER_DOMAIN_PORT_DDI_F_LANES:
- return "PORT_DDI_F_LANES";
- case POWER_DOMAIN_PORT_DDI_G_LANES:
- return "PORT_DDI_G_LANES";
- case POWER_DOMAIN_PORT_DDI_H_LANES:
- return "PORT_DDI_H_LANES";
- case POWER_DOMAIN_PORT_DDI_I_LANES:
- return "PORT_DDI_I_LANES";
- case POWER_DOMAIN_PORT_DDI_A_IO:
- return "PORT_DDI_A_IO";
- case POWER_DOMAIN_PORT_DDI_B_IO:
- return "PORT_DDI_B_IO";
- case POWER_DOMAIN_PORT_DDI_C_IO:
- return "PORT_DDI_C_IO";
- case POWER_DOMAIN_PORT_DDI_D_IO:
- return "PORT_DDI_D_IO";
- case POWER_DOMAIN_PORT_DDI_E_IO:
- return "PORT_DDI_E_IO";
- case POWER_DOMAIN_PORT_DDI_F_IO:
- return "PORT_DDI_F_IO";
- case POWER_DOMAIN_PORT_DDI_G_IO:
- return "PORT_DDI_G_IO";
- case POWER_DOMAIN_PORT_DDI_H_IO:
- return "PORT_DDI_H_IO";
- case POWER_DOMAIN_PORT_DDI_I_IO:
- return "PORT_DDI_I_IO";
+ case POWER_DOMAIN_PORT_DDI_LANES_A:
+ return "PORT_DDI_LANES_A";
+ case POWER_DOMAIN_PORT_DDI_LANES_B:
+ return "PORT_DDI_LANES_B";
+ case POWER_DOMAIN_PORT_DDI_LANES_C:
+ return "PORT_DDI_LANES_C";
+ case POWER_DOMAIN_PORT_DDI_LANES_D:
+ return "PORT_DDI_LANES_D";
+ case POWER_DOMAIN_PORT_DDI_LANES_E:
+ return "PORT_DDI_LANES_E";
+ case POWER_DOMAIN_PORT_DDI_LANES_F:
+ return "PORT_DDI_LANES_F";
+ case POWER_DOMAIN_PORT_DDI_LANES_G:
+ return "PORT_DDI_LANES_G";
+ case POWER_DOMAIN_PORT_DDI_LANES_H:
+ return "PORT_DDI_LANES_H";
+ case POWER_DOMAIN_PORT_DDI_LANES_I:
+ return "PORT_DDI_LANES_I";
+ case POWER_DOMAIN_PORT_DDI_IO_A:
+ return "PORT_DDI_IO_A";
+ case POWER_DOMAIN_PORT_DDI_IO_B:
+ return "PORT_DDI_IO_B";
+ case POWER_DOMAIN_PORT_DDI_IO_C:
+ return "PORT_DDI_IO_C";
+ case POWER_DOMAIN_PORT_DDI_IO_D:
+ return "PORT_DDI_IO_D";
+ case POWER_DOMAIN_PORT_DDI_IO_E:
+ return "PORT_DDI_IO_E";
+ case POWER_DOMAIN_PORT_DDI_IO_F:
+ return "PORT_DDI_IO_F";
+ case POWER_DOMAIN_PORT_DDI_IO_G:
+ return "PORT_DDI_IO_G";
+ case POWER_DOMAIN_PORT_DDI_IO_H:
+ return "PORT_DDI_IO_H";
+ case POWER_DOMAIN_PORT_DDI_IO_I:
+ return "PORT_DDI_IO_I";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -136,20 +136,20 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_I";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
- case POWER_DOMAIN_AUX_C_TBT:
- return "AUX_C_TBT";
- case POWER_DOMAIN_AUX_D_TBT:
- return "AUX_D_TBT";
- case POWER_DOMAIN_AUX_E_TBT:
- return "AUX_E_TBT";
- case POWER_DOMAIN_AUX_F_TBT:
- return "AUX_F_TBT";
- case POWER_DOMAIN_AUX_G_TBT:
- return "AUX_G_TBT";
- case POWER_DOMAIN_AUX_H_TBT:
- return "AUX_H_TBT";
- case POWER_DOMAIN_AUX_I_TBT:
- return "AUX_I_TBT";
+ case POWER_DOMAIN_AUX_TBT_C:
+ return "AUX_TBT_C";
+ case POWER_DOMAIN_AUX_TBT_D:
+ return "AUX_TBT_D";
+ case POWER_DOMAIN_AUX_TBT_E:
+ return "AUX_TBT_E";
+ case POWER_DOMAIN_AUX_TBT_F:
+ return "AUX_TBT_F";
+ case POWER_DOMAIN_AUX_TBT_G:
+ return "AUX_TBT_G";
+ case POWER_DOMAIN_AUX_TBT_H:
+ return "AUX_TBT_H";
+ case POWER_DOMAIN_AUX_TBT_I:
+ return "AUX_TBT_I";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
case POWER_DOMAIN_INIT:
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index e80317e7868b6..5ae81e3300224 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -25,10 +25,10 @@ enum intel_display_power_domain {
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
POWER_DOMAIN_PIPE_D,
- POWER_DOMAIN_PIPE_A_PANEL_FITTER,
- POWER_DOMAIN_PIPE_B_PANEL_FITTER,
- POWER_DOMAIN_PIPE_C_PANEL_FITTER,
- POWER_DOMAIN_PIPE_D_PANEL_FITTER,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_D,
POWER_DOMAIN_TRANSCODER_A,
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_TRANSCODER_C,
@@ -40,17 +40,17 @@ enum intel_display_power_domain {
/* VDSC/joining for eDP/DSI transcoder (ICL) or pipe A (TGL) */
POWER_DOMAIN_TRANSCODER_VDSC_PW2,
- POWER_DOMAIN_PORT_DDI_A_LANES,
- POWER_DOMAIN_PORT_DDI_B_LANES,
- POWER_DOMAIN_PORT_DDI_C_LANES,
- POWER_DOMAIN_PORT_DDI_D_LANES,
- POWER_DOMAIN_PORT_DDI_E_LANES,
- POWER_DOMAIN_PORT_DDI_F_LANES,
- POWER_DOMAIN_PORT_DDI_G_LANES,
- POWER_DOMAIN_PORT_DDI_H_LANES,
- POWER_DOMAIN_PORT_DDI_I_LANES,
+ POWER_DOMAIN_PORT_DDI_LANES_A,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_PORT_DDI_LANES_E,
+ POWER_DOMAIN_PORT_DDI_LANES_F,
+ POWER_DOMAIN_PORT_DDI_LANES_G,
+ POWER_DOMAIN_PORT_DDI_LANES_H,
+ POWER_DOMAIN_PORT_DDI_LANES_I,
- POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_D_LANES, /* tgl+ */
+ POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_LANES_D, /* tgl+ */
POWER_DOMAIN_PORT_DDI_LANES_TC2,
POWER_DOMAIN_PORT_DDI_LANES_TC3,
POWER_DOMAIN_PORT_DDI_LANES_TC4,
@@ -60,17 +60,17 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_LANES_D_XELPD = POWER_DOMAIN_PORT_DDI_LANES_TC5, /* XELPD */
POWER_DOMAIN_PORT_DDI_LANES_E_XELPD,
- POWER_DOMAIN_PORT_DDI_A_IO,
- POWER_DOMAIN_PORT_DDI_B_IO,
- POWER_DOMAIN_PORT_DDI_C_IO,
- POWER_DOMAIN_PORT_DDI_D_IO,
- POWER_DOMAIN_PORT_DDI_E_IO,
- POWER_DOMAIN_PORT_DDI_F_IO,
- POWER_DOMAIN_PORT_DDI_G_IO,
- POWER_DOMAIN_PORT_DDI_H_IO,
- POWER_DOMAIN_PORT_DDI_I_IO,
+ POWER_DOMAIN_PORT_DDI_IO_A,
+ POWER_DOMAIN_PORT_DDI_IO_B,
+ POWER_DOMAIN_PORT_DDI_IO_C,
+ POWER_DOMAIN_PORT_DDI_IO_D,
+ POWER_DOMAIN_PORT_DDI_IO_E,
+ POWER_DOMAIN_PORT_DDI_IO_F,
+ POWER_DOMAIN_PORT_DDI_IO_G,
+ POWER_DOMAIN_PORT_DDI_IO_H,
+ POWER_DOMAIN_PORT_DDI_IO_I,
- POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_D_IO, /* tgl+ */
+ POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_IO_D, /* tgl+ */
POWER_DOMAIN_PORT_DDI_IO_TC2,
POWER_DOMAIN_PORT_DDI_IO_TC3,
POWER_DOMAIN_PORT_DDI_IO_TC4,
@@ -107,15 +107,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_E_XELPD,
POWER_DOMAIN_AUX_IO_A,
- POWER_DOMAIN_AUX_C_TBT,
- POWER_DOMAIN_AUX_D_TBT,
- POWER_DOMAIN_AUX_E_TBT,
- POWER_DOMAIN_AUX_F_TBT,
- POWER_DOMAIN_AUX_G_TBT,
- POWER_DOMAIN_AUX_H_TBT,
- POWER_DOMAIN_AUX_I_TBT,
+ POWER_DOMAIN_AUX_TBT_C,
+ POWER_DOMAIN_AUX_TBT_D,
+ POWER_DOMAIN_AUX_TBT_E,
+ POWER_DOMAIN_AUX_TBT_F,
+ POWER_DOMAIN_AUX_TBT_G,
+ POWER_DOMAIN_AUX_TBT_H,
+ POWER_DOMAIN_AUX_TBT_I,
- POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_D_TBT, /* tgl+ */
+ POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_TBT_D, /* tgl+ */
POWER_DOMAIN_AUX_TBT2,
POWER_DOMAIN_AUX_TBT3,
POWER_DOMAIN_AUX_TBT4,
@@ -134,7 +134,7 @@ enum intel_display_power_domain {
#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
#define POWER_DOMAIN_PIPE_PANEL_FITTER(pipe) \
- ((pipe) + POWER_DOMAIN_PIPE_A_PANEL_FITTER)
+ ((pipe) + POWER_DOMAIN_PIPE_PANEL_FITTER_A)
#define POWER_DOMAIN_TRANSCODER(tran) \
((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
(tran) + POWER_DOMAIN_TRANSCODER_A)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index d566e638ac9b6..dc5be70a17813 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -26,8 +26,8 @@ static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
#define I830_PIPES_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_A) | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -50,15 +50,15 @@ static const struct i915_power_well_desc i830_power_wells[] = {
#define HSW_DISPLAY_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
@@ -87,14 +87,14 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
#define BDW_DISPLAY_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
@@ -125,12 +125,12 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
BIT_ULL(POWER_DOMAIN_PIPE_A) | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
@@ -142,30 +142,30 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -244,15 +244,15 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
BIT_ULL(POWER_DOMAIN_PIPE_A) | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
@@ -264,14 +264,14 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
BIT_ULL(POWER_DOMAIN_INIT))
#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -314,15 +314,15 @@ static const struct i915_power_well_desc chv_power_wells[] = {
#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
@@ -339,20 +339,20 @@ static const struct i915_power_well_desc chv_power_wells[] = {
BIT_ULL(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
static const struct i915_power_well_desc skl_power_wells[] = {
@@ -437,13 +437,13 @@ static const struct i915_power_well_desc skl_power_wells[] = {
#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
@@ -460,13 +460,13 @@ static const struct i915_power_well_desc skl_power_wells[] = {
BIT_ULL(POWER_DOMAIN_INIT))
#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -527,13 +527,13 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
@@ -549,22 +549,22 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
BIT_ULL(POWER_DOMAIN_INIT))
-#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)
-#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)
-#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)
+#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
+#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
+#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_A_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
BIT_ULL(POWER_DOMAIN_AUX_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_AUX_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
@@ -706,22 +706,22 @@ static const struct i915_power_well_desc glk_power_wells[] = {
*/
#define ICL_PW_4_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
/* VDSC/joining */
#define ICL_PW_3_POWER_DOMAINS ( \
ICL_PW_4_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_B_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_D_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_E_LANES) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_F_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_F) | \
BIT_ULL(POWER_DOMAIN_VGA) | \
BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
@@ -730,10 +730,10 @@ static const struct i915_power_well_desc glk_power_wells[] = {
BIT_ULL(POWER_DOMAIN_AUX_D) | \
BIT_ULL(POWER_DOMAIN_AUX_E) | \
BIT_ULL(POWER_DOMAIN_AUX_F) | \
- BIT_ULL(POWER_DOMAIN_AUX_C_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_D_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_E_TBT) | \
- BIT_ULL(POWER_DOMAIN_AUX_F_TBT) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT_C) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT_D) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT_E) | \
+ BIT_ULL(POWER_DOMAIN_AUX_TBT_F) | \
BIT_ULL(POWER_DOMAIN_INIT))
/*
* - transcoder WD
@@ -755,12 +755,12 @@ static const struct i915_power_well_desc glk_power_wells[] = {
BIT_ULL(POWER_DOMAIN_DC_OFF) | \
BIT_ULL(POWER_DOMAIN_INIT))
-#define ICL_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_A_IO)
-#define ICL_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_B_IO)
-#define ICL_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_C_IO)
-#define ICL_DDI_IO_D_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_D_IO)
-#define ICL_DDI_IO_E_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_E_IO)
-#define ICL_DDI_IO_F_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_F_IO)
+#define ICL_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
+#define ICL_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
+#define ICL_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
+#define ICL_DDI_IO_D_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D)
+#define ICL_DDI_IO_E_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E)
+#define ICL_DDI_IO_F_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_F)
#define ICL_AUX_A_IO_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_AUX_A) | \
@@ -771,10 +771,10 @@ static const struct i915_power_well_desc glk_power_wells[] = {
#define ICL_AUX_D_TC2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D)
#define ICL_AUX_E_TC3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E)
#define ICL_AUX_F_TC4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F)
-#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C_TBT)
-#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_TBT)
-#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_TBT)
-#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F_TBT)
+#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_C)
+#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_D)
+#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_E)
+#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_F)
static const struct i915_power_well_desc icl_power_wells[] = {
{
@@ -970,21 +970,21 @@ static const struct i915_power_well_desc icl_power_wells[] = {
#define TGL_PW_5_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define TGL_PW_4_POWER_DOMAINS ( \
TGL_PW_5_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define TGL_PW_3_POWER_DOMAINS ( \
TGL_PW_4_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
@@ -1341,14 +1341,14 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
#define RKL_PW_4_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define RKL_PW_3_POWER_DOMAINS ( \
RKL_PW_4_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
@@ -1504,7 +1504,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
#define DG1_PW_3_POWER_DOMAINS ( \
TGL_PW_4_POWER_DOMAINS | \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
@@ -1679,32 +1679,32 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
#define XELPD_PW_D_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_D_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define XELPD_PW_C_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define XELPD_PW_B_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define XELPD_PW_A_POWER_DOMAINS ( \
BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A_PANEL_FITTER) | \
+ BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
BIT_ULL(POWER_DOMAIN_INIT))
#define XELPD_PW_2_POWER_DOMAINS ( \
XELPD_PW_B_POWER_DOMAINS | \
XELPD_PW_C_POWER_DOMAINS | \
XELPD_PW_D_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_C_LANES) | \
+ BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 07/18] drm/i915: Sanitize the power well names
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (5 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 06/18] drm/i915: Rename the power domain names to end with pipes/ports Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 08/18] drm/i915: Convert the power well descriptor domain mask to an array of domains Imre Deak
` (18 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
Use the shortest descriptive name for all power wells for simplicity and
to use the same name for the same type of power wells on multiple
platforms.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
.../i915/display/intel_display_power_map.c | 254 +++++++++---------
1 file changed, 127 insertions(+), 127 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index dc5be70a17813..42b813cf47dbf 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -363,7 +363,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -374,7 +374,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "MISC IO power well",
+ .name = "MISC_IO",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -384,12 +384,12 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 2",
+ .name = "PW_2",
.domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_vga = true,
@@ -400,7 +400,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_PW_2,
},
}, {
- .name = "DDI A/E IO power well",
+ .name = "DDI_IO_A_E",
.domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -408,7 +408,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
},
}, {
- .name = "DDI B IO power well",
+ .name = "DDI_IO_B",
.domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -416,7 +416,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
},
}, {
- .name = "DDI C IO power well",
+ .name = "DDI_IO_C",
.domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -424,7 +424,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_DDI_C,
},
}, {
- .name = "DDI D IO power well",
+ .name = "DDI_IO_D",
.domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -479,7 +479,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -490,12 +490,12 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 2",
+ .name = "PW_2",
.domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_vga = true,
@@ -589,7 +589,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -600,12 +600,12 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 2",
+ .name = "PW_2",
.domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_vga = true,
@@ -640,7 +640,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.bxt.phy = DPIO_PHY2,
},
}, {
- .name = "AUX A",
+ .name = "AUX_A",
.domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -648,7 +648,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.hsw.idx = GLK_PW_CTL_IDX_AUX_A,
},
}, {
- .name = "AUX B",
+ .name = "AUX_B",
.domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -656,7 +656,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.hsw.idx = GLK_PW_CTL_IDX_AUX_B,
},
}, {
- .name = "AUX C",
+ .name = "AUX_C",
.domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -664,7 +664,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.hsw.idx = GLK_PW_CTL_IDX_AUX_C,
},
}, {
- .name = "DDI A IO power well",
+ .name = "DDI_IO_A",
.domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -672,7 +672,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.hsw.idx = GLK_PW_CTL_IDX_DDI_A,
},
}, {
- .name = "DDI B IO power well",
+ .name = "DDI_IO_B",
.domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -680,7 +680,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
.hsw.idx = SKL_PW_CTL_IDX_DDI_B,
},
}, {
- .name = "DDI C IO power well",
+ .name = "DDI_IO_C",
.domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -784,7 +784,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -795,12 +795,12 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 2",
+ .name = "PW_2",
.domains = ICL_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -809,7 +809,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
},
}, {
- .name = "power well 3",
+ .name = "PW_3",
.domains = ICL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_vga = true,
@@ -820,7 +820,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
},
}, {
- .name = "DDI A IO",
+ .name = "DDI_IO_A",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -828,7 +828,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
},
}, {
- .name = "DDI B IO",
+ .name = "DDI_IO_B",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -836,7 +836,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
},
}, {
- .name = "DDI C IO",
+ .name = "DDI_IO_C",
.domains = ICL_DDI_IO_C_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -844,7 +844,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
},
}, {
- .name = "DDI D IO",
+ .name = "DDI_IO_D",
.domains = ICL_DDI_IO_D_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -852,7 +852,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_D,
},
}, {
- .name = "DDI E IO",
+ .name = "DDI_IO_E",
.domains = ICL_DDI_IO_E_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -860,7 +860,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_E,
},
}, {
- .name = "DDI F IO",
+ .name = "DDI_IO_F",
.domains = ICL_DDI_IO_F_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -868,7 +868,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_F,
},
}, {
- .name = "AUX A",
+ .name = "AUX_A",
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -876,7 +876,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
},
}, {
- .name = "AUX B",
+ .name = "AUX_B",
.domains = ICL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -884,7 +884,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
},
}, {
- .name = "AUX C TC1",
+ .name = "AUX_C",
.domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -893,7 +893,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
},
}, {
- .name = "AUX D TC2",
+ .name = "AUX_D",
.domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -902,7 +902,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_D,
},
}, {
- .name = "AUX E TC3",
+ .name = "AUX_E",
.domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -911,7 +911,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_E,
},
}, {
- .name = "AUX F TC4",
+ .name = "AUX_F",
.domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -920,7 +920,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_F,
},
}, {
- .name = "AUX C TBT1",
+ .name = "AUX_TBT1",
.domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -929,7 +929,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
},
}, {
- .name = "AUX D TBT2",
+ .name = "AUX_TBT2",
.domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -938,7 +938,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
},
}, {
- .name = "AUX E TBT3",
+ .name = "AUX_TBT3",
.domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -947,7 +947,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
},
}, {
- .name = "AUX F TBT4",
+ .name = "AUX_TBT4",
.domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -956,7 +956,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
},
}, {
- .name = "power well 4",
+ .name = "PW_4",
.domains = ICL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_C),
@@ -1072,7 +1072,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -1083,12 +1083,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 2",
+ .name = "PW_2",
.domains = TGL_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -1097,7 +1097,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
},
}, {
- .name = "power well 3",
+ .name = "PW_3",
.domains = TGL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_vga = true,
@@ -1108,7 +1108,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
},
}, {
- .name = "DDI A IO",
+ .name = "DDI_IO_A",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1116,7 +1116,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
}
}, {
- .name = "DDI B IO",
+ .name = "DDI_IO_B",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1124,7 +1124,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
}
}, {
- .name = "DDI C IO",
+ .name = "DDI_IO_C",
.domains = ICL_DDI_IO_C_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1132,7 +1132,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
}
}, {
- .name = "DDI IO TC1",
+ .name = "DDI_IO_TC1",
.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1140,7 +1140,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
},
}, {
- .name = "DDI IO TC2",
+ .name = "DDI_IO_TC2",
.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1148,7 +1148,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
},
}, {
- .name = "DDI IO TC3",
+ .name = "DDI_IO_TC3",
.domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1156,7 +1156,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
},
}, {
- .name = "DDI IO TC4",
+ .name = "DDI_IO_TC4",
.domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1164,7 +1164,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
},
}, {
- .name = "DDI IO TC5",
+ .name = "DDI_IO_TC5",
.domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1172,7 +1172,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
},
}, {
- .name = "DDI IO TC6",
+ .name = "DDI_IO_TC6",
.domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1180,12 +1180,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
},
}, {
- .name = "TC cold off",
+ .name = "TC_cold_off",
.domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
.ops = &tgl_tc_cold_off_ops,
.id = TGL_DISP_PW_TC_COLD_OFF,
}, {
- .name = "AUX A",
+ .name = "AUX_A",
.domains = TGL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1193,7 +1193,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
},
}, {
- .name = "AUX B",
+ .name = "AUX_B",
.domains = TGL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1201,7 +1201,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
},
}, {
- .name = "AUX C",
+ .name = "AUX_C",
.domains = TGL_AUX_C_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1209,7 +1209,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
},
}, {
- .name = "AUX USBC1",
+ .name = "AUX_USBC1",
.domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1218,7 +1218,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
},
}, {
- .name = "AUX USBC2",
+ .name = "AUX_USBC2",
.domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1227,7 +1227,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
},
}, {
- .name = "AUX USBC3",
+ .name = "AUX_USBC3",
.domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1236,7 +1236,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
},
}, {
- .name = "AUX USBC4",
+ .name = "AUX_USBC4",
.domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1245,7 +1245,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
},
}, {
- .name = "AUX USBC5",
+ .name = "AUX_USBC5",
.domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1254,7 +1254,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
},
}, {
- .name = "AUX USBC6",
+ .name = "AUX_USBC6",
.domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1263,7 +1263,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
},
}, {
- .name = "AUX TBT1",
+ .name = "AUX_TBT1",
.domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1272,7 +1272,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
},
}, {
- .name = "AUX TBT2",
+ .name = "AUX_TBT2",
.domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1281,7 +1281,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
},
}, {
- .name = "AUX TBT3",
+ .name = "AUX_TBT3",
.domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1290,7 +1290,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
},
}, {
- .name = "AUX TBT4",
+ .name = "AUX_TBT4",
.domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1299,7 +1299,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
},
}, {
- .name = "AUX TBT5",
+ .name = "AUX_TBT5",
.domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1308,7 +1308,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
},
}, {
- .name = "AUX TBT6",
+ .name = "AUX_TBT6",
.domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -1317,7 +1317,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
},
}, {
- .name = "power well 4",
+ .name = "PW_4",
.domains = TGL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -1327,7 +1327,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
}
}, {
- .name = "power well 5",
+ .name = "PW_5",
.domains = TGL_PW_5_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -1395,7 +1395,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -1406,12 +1406,12 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 3",
+ .name = "PW_3",
.domains = RKL_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
@@ -1422,7 +1422,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
},
}, {
- .name = "power well 4",
+ .name = "PW_4",
.domains = RKL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -1432,7 +1432,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
}
}, {
- .name = "DDI A IO",
+ .name = "DDI_IO_A",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1440,7 +1440,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
}
}, {
- .name = "DDI B IO",
+ .name = "DDI_IO_B",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1448,7 +1448,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
}
}, {
- .name = "DDI IO TC1",
+ .name = "DDI_IO_TC1",
.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1456,7 +1456,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
},
}, {
- .name = "DDI IO TC2",
+ .name = "DDI_IO_TC2",
.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1464,7 +1464,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
},
}, {
- .name = "AUX A",
+ .name = "AUX_A",
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1472,7 +1472,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
},
}, {
- .name = "AUX B",
+ .name = "AUX_B",
.domains = ICL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1480,7 +1480,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
},
}, {
- .name = "AUX USBC1",
+ .name = "AUX_USBC1",
.domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1488,7 +1488,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
},
}, {
- .name = "AUX USBC2",
+ .name = "AUX_USBC2",
.domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1535,7 +1535,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -1546,12 +1546,12 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 2",
+ .name = "PW_2",
.domains = DG1_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -1560,7 +1560,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
},
}, {
- .name = "power well 3",
+ .name = "PW_3",
.domains = DG1_PW_3_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
@@ -1571,7 +1571,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_3,
},
}, {
- .name = "DDI A IO",
+ .name = "DDI_IO_A",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1579,7 +1579,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
}
}, {
- .name = "DDI B IO",
+ .name = "DDI_IO_B",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1587,7 +1587,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
}
}, {
- .name = "DDI IO TC1",
+ .name = "DDI_IO_TC1",
.domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1595,7 +1595,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
},
}, {
- .name = "DDI IO TC2",
+ .name = "DDI_IO_TC2",
.domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1603,7 +1603,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
},
}, {
- .name = "AUX A",
+ .name = "AUX_A",
.domains = TGL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1611,7 +1611,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
},
}, {
- .name = "AUX B",
+ .name = "AUX_B",
.domains = TGL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1619,7 +1619,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
},
}, {
- .name = "AUX USBC1",
+ .name = "AUX_USBC1",
.domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1628,7 +1628,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
},
}, {
- .name = "AUX USBC2",
+ .name = "AUX_USBC2",
.domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
@@ -1637,7 +1637,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
},
}, {
- .name = "power well 4",
+ .name = "PW_4",
.domains = TGL_PW_4_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -1647,7 +1647,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_4,
}
}, {
- .name = "power well 5",
+ .name = "PW_5",
.domains = TGL_PW_5_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_fuses = true,
@@ -1779,7 +1779,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
- .name = "power well 1",
+ .name = "PW_1",
/* Handled by the DMC firmware */
.domains = 0,
.ops = &hsw_power_well_ops,
@@ -1790,12 +1790,12 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_1,
},
}, {
- .name = "DC off",
+ .name = "DC_off",
.domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
- .name = "power well 2",
+ .name = "PW_2",
.domains = XELPD_PW_2_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.has_vga = true,
@@ -1805,7 +1805,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_PW_2,
},
}, {
- .name = "power well A",
+ .name = "PW_A",
.domains = XELPD_PW_A_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_A),
@@ -1815,7 +1815,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_PW_A,
},
}, {
- .name = "power well B",
+ .name = "PW_B",
.domains = XELPD_PW_B_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
@@ -1825,7 +1825,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_PW_B,
},
}, {
- .name = "power well C",
+ .name = "PW_C",
.domains = XELPD_PW_C_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_C),
@@ -1835,7 +1835,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_PW_C,
},
}, {
- .name = "power well D",
+ .name = "PW_D",
.domains = XELPD_PW_D_POWER_DOMAINS,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_D),
@@ -1845,7 +1845,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_PW_D,
},
}, {
- .name = "DDI A IO",
+ .name = "DDI_IO_A",
.domains = ICL_DDI_IO_A_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1853,7 +1853,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_A,
}
}, {
- .name = "DDI B IO",
+ .name = "DDI_IO_B",
.domains = ICL_DDI_IO_B_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1861,7 +1861,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_B,
}
}, {
- .name = "DDI C IO",
+ .name = "DDI_IO_C",
.domains = ICL_DDI_IO_C_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1869,7 +1869,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_DDI_C,
}
}, {
- .name = "DDI IO D_XELPD",
+ .name = "DDI_IO_D_XELPD",
.domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1877,7 +1877,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_DDI_D,
}
}, {
- .name = "DDI IO E_XELPD",
+ .name = "DDI_IO_E_XELPD",
.domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1885,7 +1885,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_DDI_E,
}
}, {
- .name = "DDI IO TC1",
+ .name = "DDI_IO_TC1",
.domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1893,7 +1893,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
}
}, {
- .name = "DDI IO TC2",
+ .name = "DDI_IO_TC2",
.domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1901,7 +1901,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
}
}, {
- .name = "DDI IO TC3",
+ .name = "DDI_IO_TC3",
.domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1909,7 +1909,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
}
}, {
- .name = "DDI IO TC4",
+ .name = "DDI_IO_TC4",
.domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1917,7 +1917,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
}
}, {
- .name = "AUX A",
+ .name = "AUX_A",
.domains = ICL_AUX_A_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
@@ -1926,7 +1926,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_A,
},
}, {
- .name = "AUX B",
+ .name = "AUX_B",
.domains = ICL_AUX_B_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
@@ -1935,7 +1935,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_B,
},
}, {
- .name = "AUX C",
+ .name = "AUX_C",
.domains = TGL_AUX_C_IO_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
@@ -1944,7 +1944,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = ICL_PW_CTL_IDX_AUX_C,
},
}, {
- .name = "AUX D_XELPD",
+ .name = "AUX_D_XELPD",
.domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
@@ -1953,7 +1953,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
},
}, {
- .name = "AUX E_XELPD",
+ .name = "AUX_E_XELPD",
.domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1961,7 +1961,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = XELPD_PW_CTL_IDX_AUX_E,
},
}, {
- .name = "AUX USBC1",
+ .name = "AUX_USBC1",
.domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
@@ -1970,7 +1970,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
},
}, {
- .name = "AUX USBC2",
+ .name = "AUX_USBC2",
.domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1978,7 +1978,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
},
}, {
- .name = "AUX USBC3",
+ .name = "AUX_USBC3",
.domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1986,7 +1986,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
},
}, {
- .name = "AUX USBC4",
+ .name = "AUX_USBC4",
.domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
@@ -1994,7 +1994,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
},
}, {
- .name = "AUX TBT1",
+ .name = "AUX_TBT1",
.domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -2003,7 +2003,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
},
}, {
- .name = "AUX TBT2",
+ .name = "AUX_TBT2",
.domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -2012,7 +2012,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
},
}, {
- .name = "AUX TBT3",
+ .name = "AUX_TBT3",
.domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
@@ -2021,7 +2021,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
.hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
},
}, {
- .name = "AUX TBT4",
+ .name = "AUX_TBT4",
.domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 08/18] drm/i915: Convert the power well descriptor domain mask to an array of domains
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (6 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 07/18] drm/i915: Sanitize the power well names Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 09/18] drm/i915: Convert the u64 power well domains mask to a bitmap Imre Deak
` (17 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
The next patch converts the i915_power_well_desc::domain mask from a u64
mask to a bitmap. I didn't find a reasonably simple way to initialize
bitmaps statically, so prepare for the next patch here by converting the
masks to an array of domain enums and initing the masks from these
arrays during module loading.
v2: Clarify list vs. array in the commit message. (Jani)
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
.../drm/i915/display/intel_display_power.c | 4 +-
.../i915/display/intel_display_power_map.c | 1427 +++++++++--------
.../i915/display/intel_display_power_well.c | 2 +-
.../i915/display/intel_display_power_well.h | 6 +-
4 files changed, 754 insertions(+), 685 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index e524b24c329a2..b9ba8500bf984 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -24,11 +24,11 @@
#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
for_each_power_well(__dev_priv, __power_well) \
- for_each_if((__power_well)->desc->domains & (__domain_mask))
+ for_each_if((__power_well)->domains & (__domain_mask))
#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
for_each_power_well_reverse(__dev_priv, __power_well) \
- for_each_if((__power_well)->desc->domains & (__domain_mask))
+ for_each_if((__power_well)->domains & (__domain_mask))
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 42b813cf47dbf..b7aa13d6a33f3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -11,70 +11,90 @@
#include "intel_display_power_map.h"
#include "intel_display_power_well.h"
-#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
+#define __LIST_INLINE_ELEMS(__elem_type, ...) \
+ ((__elem_type[]) { __VA_ARGS__ })
+
+#define __LIST(__elems) { \
+ .list = __elems, \
+ .count = ARRAY_SIZE(__elems), \
+}
+
+#define I915_PW_DOMAINS(...) \
+ (const struct i915_power_domain_list) \
+ __LIST(__LIST_INLINE_ELEMS(enum intel_display_power_domain, __VA_ARGS__))
+
+#define I915_DECL_PW_DOMAINS(__name, ...) \
+ static const struct i915_power_domain_list __name = I915_PW_DOMAINS(__VA_ARGS__)
+
+/* Zero-length list assigns all power domains, a NULL list assigns none. */
+#define I915_PW_DOMAINS_NONE NULL
+#define I915_PW_DOMAINS_ALL /* zero-length list */
+
+
+I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
},
};
-#define I830_PIPES_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
+ POWER_DOMAIN_PIPE_A,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc i830_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "pipes",
- .domains = I830_PIPES_POWER_DOMAINS,
+ .domain_list = &i830_pwdoms_pipes,
.ops = &i830_pipes_power_well_ops,
.id = DISP_PW_ID_NONE,
},
};
-#define HSW_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_C,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_TRANSCODER_C,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_PORT_CRT, /* DDI E */
+ POWER_DOMAIN_VGA,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUDIO_PLAYBACK,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc hsw_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "display",
- .domains = HSW_DISPLAY_POWER_DOMAINS,
+ .domain_list = &hsw_pwdoms_display,
.ops = &hsw_power_well_ops,
.has_vga = true,
.id = HSW_DISP_PW_GLOBAL,
@@ -84,33 +104,33 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
},
};
-#define BDW_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | /* DDI E */ \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_C,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_TRANSCODER_C,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_PORT_CRT, /* DDI E */
+ POWER_DOMAIN_VGA,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUDIO_PLAYBACK,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc bdw_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "display",
- .domains = BDW_DISPLAY_POWER_DOMAINS,
+ .domain_list = &bdw_pwdoms_display,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
@@ -121,64 +141,51 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
},
};
-#define VLV_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
+ POWER_DOMAIN_DISPLAY_CORE,
+ POWER_DOMAIN_PIPE_A,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DSI,
+ POWER_DOMAIN_PORT_CRT,
+ POWER_DOMAIN_VGA,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUDIO_PLAYBACK,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_INIT);
-#define VLV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_CRT) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_CRT,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
-#define VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc vlv_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "display",
- .domains = VLV_DISPLAY_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_display,
.ops = &vlv_display_power_well_ops,
.id = VLV_DISP_PW_DISP2D,
{
@@ -186,10 +193,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
}, {
.name = "dpio-tx-b-01",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
.ops = &vlv_dpio_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -197,10 +201,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
}, {
.name = "dpio-tx-b-23",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
.ops = &vlv_dpio_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -208,10 +209,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
}, {
.name = "dpio-tx-c-01",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
.ops = &vlv_dpio_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -219,10 +217,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
}, {
.name = "dpio-tx-c-23",
- .domains = VLV_DPIO_TX_B_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_B_LANES_23_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_01_POWER_DOMAINS |
- VLV_DPIO_TX_C_LANES_23_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
.ops = &vlv_dpio_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -230,7 +225,7 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
}, {
.name = "dpio-common",
- .domains = VLV_DPIO_CMN_BC_POWER_DOMAINS,
+ .domain_list = &vlv_pwdoms_dpio_cmn_bc,
.ops = &vlv_dpio_cmn_power_well_ops,
.id = VLV_DISP_PW_DPIO_CMN_BC,
{
@@ -239,46 +234,46 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
};
-#define CHV_DISPLAY_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_DISPLAY_CORE) | \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(chv_pwdoms_display,
+ POWER_DOMAIN_DISPLAY_CORE,
+ POWER_DOMAIN_PIPE_A,
+ POWER_DOMAIN_PIPE_B,
+ POWER_DOMAIN_PIPE_C,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C,
+ POWER_DOMAIN_TRANSCODER_A,
+ POWER_DOMAIN_TRANSCODER_B,
+ POWER_DOMAIN_TRANSCODER_C,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_PORT_DSI,
+ POWER_DOMAIN_VGA,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUDIO_PLAYBACK,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_AUX_D,
+ POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_INIT);
-#define CHV_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
-#define CHV_DPIO_CMN_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
+ POWER_DOMAIN_AUX_D,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc chv_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
@@ -289,12 +284,12 @@ static const struct i915_power_well_desc chv_power_wells[] = {
* power wells don't actually exist. Pipe A power well is
* required for any pipe to work.
*/
- .domains = CHV_DISPLAY_POWER_DOMAINS,
+ .domain_list = &chv_pwdoms_display,
.ops = &chv_pipe_power_well_ops,
.id = DISP_PW_ID_NONE,
}, {
.name = "dpio-common-bc",
- .domains = CHV_DPIO_CMN_BC_POWER_DOMAINS,
+ .domain_list = &chv_pwdoms_dpio_cmn_bc,
.ops = &chv_dpio_cmn_power_well_ops,
.id = VLV_DISP_PW_DPIO_CMN_BC,
{
@@ -302,7 +297,7 @@ static const struct i915_power_well_desc chv_power_wells[] = {
},
}, {
.name = "dpio-common-d",
- .domains = CHV_DPIO_CMN_D_POWER_DOMAINS,
+ .domain_list = &chv_pwdoms_dpio_cmn_d,
.ops = &chv_dpio_cmn_power_well_ops,
.id = CHV_DISP_PW_DPIO_CMN_D,
{
@@ -311,61 +306,64 @@ static const struct i915_power_well_desc chv_power_wells[] = {
},
};
-#define SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define SKL_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D, \
+ POWER_DOMAIN_PORT_DDI_LANES_E, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D
-#define SKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2,
+ SKL_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
-#define SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off,
+ SKL_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_GT_IRQ,
+ POWER_DOMAIN_INIT);
-#define SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e,
+ POWER_DOMAIN_PORT_DDI_IO_A,
+ POWER_DOMAIN_PORT_DDI_IO_E,
+ POWER_DOMAIN_INIT);
-#define SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_b,
+ POWER_DOMAIN_PORT_DDI_IO_B,
+ POWER_DOMAIN_INIT);
-#define SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_c,
+ POWER_DOMAIN_PORT_DDI_IO_C,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
+ POWER_DOMAIN_PORT_DDI_IO_D,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc skl_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -376,7 +374,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
}, {
.name = "MISC_IO",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.id = SKL_DISP_PW_MISC_IO,
@@ -385,12 +383,12 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = SKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = SKL_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
@@ -401,7 +399,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
}, {
.name = "DDI_IO_A_E",
- .domains = SKL_DISPLAY_DDI_IO_A_E_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_ddi_io_a_e,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -409,7 +407,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
}, {
.name = "DDI_IO_B",
- .domains = SKL_DISPLAY_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_ddi_io_b,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -417,7 +415,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
}, {
.name = "DDI_IO_C",
- .domains = SKL_DISPLAY_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_ddi_io_c,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -425,7 +423,7 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
}, {
.name = "DDI_IO_D",
- .domains = SKL_DISPLAY_DDI_IO_D_POWER_DOMAINS,
+ .domain_list = &skl_pwdoms_ddi_io_d,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -434,54 +432,57 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
};
-#define BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define BXT_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C
-#define BXT_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2,
+ BXT_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
-#define BXT_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off,
+ BXT_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_GT_IRQ,
+ POWER_DOMAIN_INIT);
-#define BXT_DPIO_CMN_BC_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
+ POWER_DOMAIN_PORT_DDI_LANES_A,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc bxt_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -491,12 +492,12 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = BXT_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &bxt_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = BXT_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .domain_list = &bxt_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
@@ -507,7 +508,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
},
}, {
.name = "dpio-common-a",
- .domains = BXT_DPIO_CMN_A_POWER_DOMAINS,
+ .domain_list = &bxt_pwdoms_dpio_cmn_a,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = BXT_DISP_PW_DPIO_CMN_A,
{
@@ -515,7 +516,7 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
},
}, {
.name = "dpio-common-bc",
- .domains = BXT_DPIO_CMN_BC_POWER_DOMAINS,
+ .domain_list = &bxt_pwdoms_dpio_cmn_bc,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = VLV_DISP_PW_DPIO_CMN_BC,
{
@@ -524,74 +525,77 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
},
};
-#define GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_GMBUS) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_GT_IRQ) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
-#define GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
-#define GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
-
-#define GLK_DPIO_CMN_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DPIO_CMN_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DPIO_CMN_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_AUX_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_AUX_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define GLK_DISPLAY_AUX_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define GLK_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2,
+ GLK_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off,
+ GLK_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_GMBUS,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_GT_IRQ,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A);
+I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B);
+I915_DECL_PW_DOMAINS(glk_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
+ POWER_DOMAIN_PORT_DDI_LANES_A,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_IO_A,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc glk_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -601,12 +605,12 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = GLK_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = GLK_DISPLAY_POWERWELL_2_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
@@ -617,7 +621,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "dpio-common-a",
- .domains = GLK_DPIO_CMN_A_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_dpio_cmn_a,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = BXT_DISP_PW_DPIO_CMN_A,
{
@@ -625,7 +629,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "dpio-common-b",
- .domains = GLK_DPIO_CMN_B_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_dpio_cmn_b,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = VLV_DISP_PW_DPIO_CMN_BC,
{
@@ -633,7 +637,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "dpio-common-c",
- .domains = GLK_DPIO_CMN_C_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_dpio_cmn_c,
.ops = &bxt_dpio_cmn_power_well_ops,
.id = GLK_DISP_PW_DPIO_CMN_C,
{
@@ -641,7 +645,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "AUX_A",
- .domains = GLK_DISPLAY_AUX_A_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_aux_a,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -649,7 +653,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "AUX_B",
- .domains = GLK_DISPLAY_AUX_B_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_aux_b,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -657,7 +661,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "AUX_C",
- .domains = GLK_DISPLAY_AUX_C_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_aux_c,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -665,7 +669,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "DDI_IO_A",
- .domains = GLK_DISPLAY_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_ddi_io_a,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -673,7 +677,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "DDI_IO_B",
- .domains = GLK_DISPLAY_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_ddi_io_b,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -681,7 +685,7 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
}, {
.name = "DDI_IO_C",
- .domains = GLK_DISPLAY_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &glk_pwdoms_ddi_io_c,
.ops = &hsw_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -704,89 +708,97 @@ static const struct i915_power_well_desc glk_power_wells[] = {
* - DDI_A
* - FBC
*/
-#define ICL_PW_4_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define ICL_PW_4_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C
+
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
+ ICL_PW_4_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/* VDSC/joining */
-#define ICL_PW_3_POWER_DOMAINS ( \
- ICL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_A) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_F) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D) | \
- BIT_ULL(POWER_DOMAIN_AUX_E) | \
- BIT_ULL(POWER_DOMAIN_AUX_F) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT_D) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT_E) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT_F) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define ICL_PW_3_POWER_DOMAINS \
+ ICL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D, \
+ POWER_DOMAIN_PORT_DDI_LANES_E, \
+ POWER_DOMAIN_PORT_DDI_LANES_F, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D, \
+ POWER_DOMAIN_AUX_E, \
+ POWER_DOMAIN_AUX_F, \
+ POWER_DOMAIN_AUX_TBT_C, \
+ POWER_DOMAIN_AUX_TBT_D, \
+ POWER_DOMAIN_AUX_TBT_E, \
+ POWER_DOMAIN_AUX_TBT_F
+
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3,
+ ICL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/*
* - transcoder WD
* - KVMR (HW control)
*/
-#define ICL_PW_2_POWER_DOMAINS ( \
- ICL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define ICL_PW_2_POWER_DOMAINS \
+ ICL_PW_3_POWER_DOMAINS, \
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2
+
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2,
+ ICL_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/*
* - KVMR (HW control)
*/
-#define ICL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- ICL_PW_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_DC_OFF) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
+ ICL_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_DC_OFF,
+ POWER_DOMAIN_INIT);
-#define ICL_DDI_IO_A_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_A)
-#define ICL_DDI_IO_B_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_B)
-#define ICL_DDI_IO_C_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_C)
-#define ICL_DDI_IO_D_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D)
-#define ICL_DDI_IO_E_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E)
-#define ICL_DDI_IO_F_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_F)
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d, POWER_DOMAIN_PORT_DDI_IO_D);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e, POWER_DOMAIN_PORT_DDI_IO_E);
+I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f, POWER_DOMAIN_PORT_DDI_IO_F);
-#define ICL_AUX_A_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A))
-
-#define ICL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
-#define ICL_AUX_C_TC1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
-#define ICL_AUX_D_TC2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D)
-#define ICL_AUX_E_TC3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E)
-#define ICL_AUX_F_TC4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_F)
-#define ICL_AUX_C_TBT1_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_C)
-#define ICL_AUX_D_TBT2_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_D)
-#define ICL_AUX_E_TBT3_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_E)
-#define ICL_AUX_F_TBT4_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT_F)
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_IO_A);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_b, POWER_DOMAIN_AUX_B);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, POWER_DOMAIN_AUX_D);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, POWER_DOMAIN_AUX_E);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, POWER_DOMAIN_AUX_F);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT_C);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT_D);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT_E);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT_F);
static const struct i915_power_well_desc icl_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -796,12 +808,12 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = ICL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = ICL_PW_2_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.id = SKL_DISP_PW_2,
@@ -810,7 +822,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "PW_3",
- .domains = ICL_PW_3_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_pw_3,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B),
@@ -821,7 +833,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -829,7 +841,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -837,7 +849,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "DDI_IO_C",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_c,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -845,7 +857,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "DDI_IO_D",
- .domains = ICL_DDI_IO_D_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_d,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -853,7 +865,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "DDI_IO_E",
- .domains = ICL_DDI_IO_E_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_e,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -861,7 +873,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "DDI_IO_F",
- .domains = ICL_DDI_IO_F_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_f,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -869,7 +881,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -877,7 +889,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -885,7 +897,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_C",
- .domains = ICL_AUX_C_TC1_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_c,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -894,7 +906,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_D",
- .domains = ICL_AUX_D_TC2_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_d,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -903,7 +915,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_E",
- .domains = ICL_AUX_E_TC3_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_e,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -912,7 +924,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_F",
- .domains = ICL_AUX_F_TC4_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_f,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -921,7 +933,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_TBT1",
- .domains = ICL_AUX_C_TBT1_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_tbt1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -930,7 +942,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_TBT2",
- .domains = ICL_AUX_D_TBT2_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_tbt2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -939,7 +951,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_TBT3",
- .domains = ICL_AUX_E_TBT3_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_tbt3,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -948,7 +960,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "AUX_TBT4",
- .domains = ICL_AUX_F_TBT4_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_tbt4,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -957,7 +969,7 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
}, {
.name = "PW_4",
- .domains = ICL_PW_4_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_pw_4,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_C),
.has_fuses = true,
@@ -968,113 +980,122 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
};
-#define TGL_PW_5_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_PW_5_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_D, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
+ POWER_DOMAIN_TRANSCODER_D
-#define TGL_PW_4_POWER_DOMAINS ( \
- TGL_PW_5_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_5,
+ TGL_PW_5_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
-#define TGL_PW_3_POWER_DOMAINS ( \
- TGL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC5) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC6) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_PW_4_POWER_DOMAINS \
+ TGL_PW_5_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
-#define TGL_PW_2_POWER_DOMAINS ( \
- TGL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_4,
+ TGL_PW_4_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
-#define TGL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- TGL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define TGL_PW_3_POWER_DOMAINS \
+ TGL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC3, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC4, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC5, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC6, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2, \
+ POWER_DOMAIN_AUX_USBC3, \
+ POWER_DOMAIN_AUX_USBC4, \
+ POWER_DOMAIN_AUX_USBC5, \
+ POWER_DOMAIN_AUX_USBC6, \
+ POWER_DOMAIN_AUX_TBT1, \
+ POWER_DOMAIN_AUX_TBT2, \
+ POWER_DOMAIN_AUX_TBT3, \
+ POWER_DOMAIN_AUX_TBT4, \
+ POWER_DOMAIN_AUX_TBT5, \
+ POWER_DOMAIN_AUX_TBT6
-#define TGL_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
-#define TGL_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
-#define TGL_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
-#define TGL_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
-#define TGL_DDI_IO_TC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC5)
-#define TGL_DDI_IO_TC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC6)
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_3,
+ TGL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
-#define TGL_AUX_A_IO_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_IO_A))
-#define TGL_AUX_B_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_B)
-#define TGL_AUX_C_IO_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_C)
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2,
+ TGL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2,
+ POWER_DOMAIN_INIT);
-#define TGL_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
-#define TGL_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
-#define TGL_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
-#define TGL_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
-#define TGL_AUX_IO_USBC5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC5)
-#define TGL_AUX_IO_USBC6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC6)
+I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off,
+ TGL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_AUX_C,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_INIT);
-#define TGL_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
-#define TGL_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
-#define TGL_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
-#define TGL_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
-#define TGL_AUX_IO_TBT5_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT5)
-#define TGL_AUX_IO_TBT6_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT6)
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5, POWER_DOMAIN_PORT_DDI_IO_TC5);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6, POWER_DOMAIN_PORT_DDI_IO_TC6);
-#define TGL_TC_COLD_OFF_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC5) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC6) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT5) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT6) | \
- BIT_ULL(POWER_DOMAIN_TC_COLD_OFF))
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_IO_A);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_b, POWER_DOMAIN_AUX_B);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5, POWER_DOMAIN_AUX_USBC5);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6, POWER_DOMAIN_AUX_USBC6);
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5, POWER_DOMAIN_AUX_TBT5);
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6, POWER_DOMAIN_AUX_TBT6);
+
+I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
+ POWER_DOMAIN_AUX_USBC1,
+ POWER_DOMAIN_AUX_USBC2,
+ POWER_DOMAIN_AUX_USBC3,
+ POWER_DOMAIN_AUX_USBC4,
+ POWER_DOMAIN_AUX_USBC5,
+ POWER_DOMAIN_AUX_USBC6,
+ POWER_DOMAIN_AUX_TBT1,
+ POWER_DOMAIN_AUX_TBT2,
+ POWER_DOMAIN_AUX_TBT3,
+ POWER_DOMAIN_AUX_TBT4,
+ POWER_DOMAIN_AUX_TBT5,
+ POWER_DOMAIN_AUX_TBT6,
+ POWER_DOMAIN_TC_COLD_OFF);
static const struct i915_power_well_desc tgl_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -1084,12 +1105,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = TGL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = TGL_PW_2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.id = SKL_DISP_PW_2,
@@ -1098,7 +1119,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "PW_3",
- .domains = TGL_PW_3_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_3,
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B),
@@ -1109,7 +1130,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1117,7 +1138,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
}
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1125,7 +1146,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
}
}, {
.name = "DDI_IO_C",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_c,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1133,7 +1154,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
}
}, {
.name = "DDI_IO_TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc1,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1141,7 +1162,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "DDI_IO_TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc2,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1149,7 +1170,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "DDI_IO_TC3",
- .domains = TGL_DDI_IO_TC3_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc3,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1157,7 +1178,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "DDI_IO_TC4",
- .domains = TGL_DDI_IO_TC4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc4,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1165,7 +1186,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "DDI_IO_TC5",
- .domains = TGL_DDI_IO_TC5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc5,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1173,7 +1194,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "DDI_IO_TC6",
- .domains = TGL_DDI_IO_TC6_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc6,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1181,12 +1202,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "TC_cold_off",
- .domains = TGL_TC_COLD_OFF_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_tc_cold_off,
.ops = &tgl_tc_cold_off_ops,
.id = TGL_DISP_PW_TC_COLD_OFF,
}, {
.name = "AUX_A",
- .domains = TGL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1194,7 +1215,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_B",
- .domains = TGL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1202,7 +1223,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_C",
- .domains = TGL_AUX_C_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_c,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1210,7 +1231,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1219,7 +1240,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1228,7 +1249,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_USBC3",
- .domains = TGL_AUX_IO_USBC3_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc3,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1237,7 +1258,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_USBC4",
- .domains = TGL_AUX_IO_USBC4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc4,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1246,7 +1267,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_USBC5",
- .domains = TGL_AUX_IO_USBC5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc5,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1255,7 +1276,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_USBC6",
- .domains = TGL_AUX_IO_USBC6_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc6,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1264,7 +1285,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_TBT1",
- .domains = TGL_AUX_IO_TBT1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1273,7 +1294,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_TBT2",
- .domains = TGL_AUX_IO_TBT2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1282,7 +1303,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_TBT3",
- .domains = TGL_AUX_IO_TBT3_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt3,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1291,7 +1312,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_TBT4",
- .domains = TGL_AUX_IO_TBT4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt4,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1300,7 +1321,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_TBT5",
- .domains = TGL_AUX_IO_TBT5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt5,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1309,7 +1330,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "AUX_TBT6",
- .domains = TGL_AUX_IO_TBT6_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_tbt6,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -1318,7 +1339,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
}, {
.name = "PW_4",
- .domains = TGL_PW_4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_4,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
@@ -1328,7 +1349,7 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
}
}, {
.name = "PW_5",
- .domains = TGL_PW_5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_5,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_D),
@@ -1339,25 +1360,31 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
};
-#define RKL_PW_4_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define RKL_PW_4_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
-#define RKL_PW_3_POWER_DOMAINS ( \
- RKL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_4,
+ RKL_PW_4_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+#define RKL_PW_3_POWER_DOMAINS \
+ RKL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2
+
+I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3,
+ RKL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/*
* There is no PW_2/PG_2 on RKL.
@@ -1380,24 +1407,24 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
* - top-level GTC (DDI-level GTC is in the well associated with the DDI)
*/
-#define RKL_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- RKL_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
+ RKL_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc rkl_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -1407,12 +1434,12 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = RKL_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &rkl_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_3",
- .domains = RKL_PW_3_POWER_DOMAINS,
+ .domain_list = &rkl_pwdoms_pw_3,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_vga = true,
@@ -1423,7 +1450,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
}, {
.name = "PW_4",
- .domains = RKL_PW_4_POWER_DOMAINS,
+ .domain_list = &rkl_pwdoms_pw_4,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
@@ -1433,7 +1460,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
}
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1441,7 +1468,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
}
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1449,7 +1476,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
}
}, {
.name = "DDI_IO_TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc1,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1457,7 +1484,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
}, {
.name = "DDI_IO_TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc2,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1465,7 +1492,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
}, {
.name = "AUX_A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1473,7 +1500,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
}, {
.name = "AUX_B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1481,7 +1508,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
}, {
.name = "AUX_USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc1,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1489,7 +1516,7 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
}, {
.name = "AUX_USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc2,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1501,43 +1528,46 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
/*
* DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
*/
-#define DG1_PW_3_POWER_DOMAINS ( \
- TGL_PW_4_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define DG1_PW_3_POWER_DOMAINS \
+ TGL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2
-#define DG1_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- DG1_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3,
+ DG1_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
-#define DG1_PW_2_POWER_DOMAINS ( \
- DG1_PW_3_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_VDSC_PW2) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off,
+ DG1_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
+ DG1_PW_3_POWER_DOMAINS,
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2,
+ POWER_DOMAIN_INIT);
static const struct i915_power_well_desc dg1_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -1547,12 +1577,12 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = DG1_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &dg1_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = DG1_PW_2_POWER_DOMAINS,
+ .domain_list = &dg1_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.id = SKL_DISP_PW_2,
@@ -1561,7 +1591,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "PW_3",
- .domains = DG1_PW_3_POWER_DOMAINS,
+ .domain_list = &dg1_pwdoms_pw_3,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_vga = true,
@@ -1572,7 +1602,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1580,7 +1610,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
}
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1588,7 +1618,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
}
}, {
.name = "DDI_IO_TC1",
- .domains = TGL_DDI_IO_TC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc1,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1596,7 +1626,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "DDI_IO_TC2",
- .domains = TGL_DDI_IO_TC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_ddi_io_tc2,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1604,7 +1634,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "AUX_A",
- .domains = TGL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1612,7 +1642,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "AUX_B",
- .domains = TGL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1620,7 +1650,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "AUX_USBC1",
- .domains = TGL_AUX_IO_USBC1_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1629,7 +1659,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "AUX_USBC2",
- .domains = TGL_AUX_IO_USBC2_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_usbc2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = false,
.id = DISP_PW_ID_NONE,
@@ -1638,7 +1668,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
}, {
.name = "PW_4",
- .domains = TGL_PW_4_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_4,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
@@ -1648,7 +1678,7 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
}
}, {
.name = "PW_5",
- .domains = TGL_PW_5_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_pw_5,
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_D),
@@ -1677,54 +1707,66 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
* to top. This allows pipes to be power gated independently.
*/
-#define XELPD_PW_D_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_D) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_D) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_D) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_C_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_C) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_C) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_C) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_B_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_B) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_B) | \
- BIT_ULL(POWER_DOMAIN_TRANSCODER_B) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_A_POWER_DOMAINS ( \
- BIT_ULL(POWER_DOMAIN_PIPE_A) | \
- BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER_A) | \
- BIT_ULL(POWER_DOMAIN_INIT))
-
-#define XELPD_PW_2_POWER_DOMAINS ( \
- XELPD_PW_B_POWER_DOMAINS | \
- XELPD_PW_C_POWER_DOMAINS | \
- XELPD_PW_D_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_C) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_D_XELPD) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_E_XELPD) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC1) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC2) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC3) | \
- BIT_ULL(POWER_DOMAIN_PORT_DDI_LANES_TC4) | \
- BIT_ULL(POWER_DOMAIN_VGA) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_PLAYBACK) | \
- BIT_ULL(POWER_DOMAIN_AUX_C) | \
- BIT_ULL(POWER_DOMAIN_AUX_D_XELPD) | \
- BIT_ULL(POWER_DOMAIN_AUX_E_XELPD) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC1) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC2) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC3) | \
- BIT_ULL(POWER_DOMAIN_AUX_USBC4) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT1) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT2) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT3) | \
- BIT_ULL(POWER_DOMAIN_AUX_TBT4) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+#define XELPD_PW_D_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_D, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
+ POWER_DOMAIN_TRANSCODER_D
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_d,
+ XELPD_PW_D_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+#define XELPD_PW_C_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_c,
+ XELPD_PW_C_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+#define XELPD_PW_B_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_b,
+ XELPD_PW_B_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
+ POWER_DOMAIN_PIPE_A,
+ POWER_DOMAIN_PIPE_PANEL_FITTER_A,
+ POWER_DOMAIN_INIT);
+
+#define XELPD_PW_2_POWER_DOMAINS \
+ XELPD_PW_B_POWER_DOMAINS, \
+ XELPD_PW_C_POWER_DOMAINS, \
+ XELPD_PW_D_POWER_DOMAINS, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D_XELPD, \
+ POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC3, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC4, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D_XELPD, \
+ POWER_DOMAIN_AUX_E_XELPD, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2, \
+ POWER_DOMAIN_AUX_USBC3, \
+ POWER_DOMAIN_AUX_USBC4, \
+ POWER_DOMAIN_AUX_TBT1, \
+ POWER_DOMAIN_AUX_TBT2, \
+ POWER_DOMAIN_AUX_TBT3, \
+ POWER_DOMAIN_AUX_TBT4
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
+ XELPD_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_INIT);
/*
* XELPD PW_1/PG_1 domains (under HW/DMC control):
@@ -1743,45 +1785,46 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
* - Top-level GTC (DDI-level GTC is in the well associated with the DDI)
*/
-#define XELPD_DISPLAY_DC_OFF_POWER_DOMAINS ( \
- XELPD_PW_2_POWER_DOMAINS | \
- BIT_ULL(POWER_DOMAIN_PORT_DSI) | \
- BIT_ULL(POWER_DOMAIN_AUDIO_MMIO) | \
- BIT_ULL(POWER_DOMAIN_AUX_A) | \
- BIT_ULL(POWER_DOMAIN_AUX_B) | \
- BIT_ULL(POWER_DOMAIN_MODESET) | \
- BIT_ULL(POWER_DOMAIN_INIT))
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
+ XELPD_PW_2_POWER_DOMAINS,
+ POWER_DOMAIN_PORT_DSI,
+ POWER_DOMAIN_AUDIO_MMIO,
+ POWER_DOMAIN_AUX_A,
+ POWER_DOMAIN_AUX_B,
+ POWER_DOMAIN_MODESET,
+ POWER_DOMAIN_INIT);
-#define XELPD_AUX_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_D_XELPD)
-#define XELPD_AUX_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_E_XELPD)
-#define XELPD_AUX_IO_USBC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC1)
-#define XELPD_AUX_IO_USBC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC2)
-#define XELPD_AUX_IO_USBC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC3)
-#define XELPD_AUX_IO_USBC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_USBC4)
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_d_xelpd, POWER_DOMAIN_AUX_D_XELPD);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_e_xelpd, POWER_DOMAIN_AUX_E_XELPD);
-#define XELPD_AUX_IO_TBT1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT1)
-#define XELPD_AUX_IO_TBT2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT2)
-#define XELPD_AUX_IO_TBT3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT3)
-#define XELPD_AUX_IO_TBT4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_AUX_TBT4)
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4);
-#define XELPD_DDI_IO_D_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_D_XELPD)
-#define XELPD_DDI_IO_E_XELPD_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_E_XELPD)
-#define XELPD_DDI_IO_TC1_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC1)
-#define XELPD_DDI_IO_TC2_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC2)
-#define XELPD_DDI_IO_TC3_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC3)
-#define XELPD_DDI_IO_TC4_POWER_DOMAINS BIT_ULL(POWER_DOMAIN_PORT_DDI_IO_TC4)
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
+
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_d_xelpd, POWER_DOMAIN_PORT_DDI_IO_D_XELPD);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_e_xelpd, POWER_DOMAIN_PORT_DDI_IO_E_XELPD);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
static const struct i915_power_well_desc xelpd_power_wells[] = {
{
.name = "always-on",
- .domains = POWER_DOMAIN_MASK,
+ .domain_list = &i9xx_pwdoms_always_on,
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
.id = DISP_PW_ID_NONE,
}, {
.name = "PW_1",
/* Handled by the DMC firmware */
- .domains = 0,
+ .domain_list = I915_PW_DOMAINS_NONE,
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
@@ -1791,12 +1834,12 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "DC_off",
- .domains = XELPD_DISPLAY_DC_OFF_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_dc_off,
.ops = &gen9_dc_off_power_well_ops,
.id = SKL_DISP_DC_OFF,
}, {
.name = "PW_2",
- .domains = XELPD_PW_2_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_2,
.ops = &hsw_power_well_ops,
.has_vga = true,
.has_fuses = true,
@@ -1806,7 +1849,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "PW_A",
- .domains = XELPD_PW_A_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_a,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_A),
.has_fuses = true,
@@ -1816,7 +1859,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "PW_B",
- .domains = XELPD_PW_B_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_b,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_fuses = true,
@@ -1826,7 +1869,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "PW_C",
- .domains = XELPD_PW_C_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_c,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_C),
.has_fuses = true,
@@ -1836,7 +1879,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "PW_D",
- .domains = XELPD_PW_D_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_pw_d,
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_D),
.has_fuses = true,
@@ -1846,7 +1889,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "DDI_IO_A",
- .domains = ICL_DDI_IO_A_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_a,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1854,7 +1897,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_B",
- .domains = ICL_DDI_IO_B_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_b,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1862,7 +1905,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_C",
- .domains = ICL_DDI_IO_C_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_ddi_io_c,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1870,7 +1913,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_D_XELPD",
- .domains = XELPD_DDI_IO_D_XELPD_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_d_xelpd,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1878,7 +1921,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_E_XELPD",
- .domains = XELPD_DDI_IO_E_XELPD_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_e_xelpd,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1886,7 +1929,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_TC1",
- .domains = XELPD_DDI_IO_TC1_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_tc1,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1894,7 +1937,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_TC2",
- .domains = XELPD_DDI_IO_TC2_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_tc2,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1902,7 +1945,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_TC3",
- .domains = XELPD_DDI_IO_TC3_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_tc3,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1910,7 +1953,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "DDI_IO_TC4",
- .domains = XELPD_DDI_IO_TC4_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_ddi_io_tc4,
.ops = &icl_ddi_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1918,7 +1961,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
}
}, {
.name = "AUX_A",
- .domains = ICL_AUX_A_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_a,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
@@ -1927,7 +1970,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_B",
- .domains = ICL_AUX_B_IO_POWER_DOMAINS,
+ .domain_list = &icl_pwdoms_aux_b,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
@@ -1936,7 +1979,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_C",
- .domains = TGL_AUX_C_IO_POWER_DOMAINS,
+ .domain_list = &tgl_pwdoms_aux_c,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
@@ -1945,7 +1988,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_D_XELPD",
- .domains = XELPD_AUX_IO_D_XELPD_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_d_xelpd,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
@@ -1954,7 +1997,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_E_XELPD",
- .domains = XELPD_AUX_IO_E_XELPD_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_e_xelpd,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1962,7 +2005,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_USBC1",
- .domains = XELPD_AUX_IO_USBC1_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_usbc1,
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
.id = DISP_PW_ID_NONE,
@@ -1971,7 +2014,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_USBC2",
- .domains = XELPD_AUX_IO_USBC2_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_usbc2,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1979,7 +2022,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_USBC3",
- .domains = XELPD_AUX_IO_USBC3_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_usbc3,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1987,7 +2030,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_USBC4",
- .domains = XELPD_AUX_IO_USBC4_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_usbc4,
.ops = &icl_aux_power_well_ops,
.id = DISP_PW_ID_NONE,
{
@@ -1995,7 +2038,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_TBT1",
- .domains = XELPD_AUX_IO_TBT1_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_tbt1,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -2004,7 +2047,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_TBT2",
- .domains = XELPD_AUX_IO_TBT2_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_tbt2,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -2013,7 +2056,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_TBT3",
- .domains = XELPD_AUX_IO_TBT3_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_tbt3,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -2022,7 +2065,7 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
}, {
.name = "AUX_TBT4",
- .domains = XELPD_AUX_IO_TBT4_POWER_DOMAINS,
+ .domain_list = &xelpd_pwdoms_aux_tbt4,
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
.id = DISP_PW_ID_NONE,
@@ -2032,6 +2075,24 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
};
+static void init_power_well_domains(const struct i915_power_well_desc *desc,
+ struct i915_power_well *power_well)
+{
+ int j;
+
+ if (!desc->domain_list)
+ return;
+
+ if (desc->domain_list->count == 0) {
+ power_well->domains = GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0);
+
+ return;
+ }
+
+ for (j = 0; j < desc->domain_list->count; j++)
+ power_well->domains |= BIT_ULL(desc->domain_list->list[j]);
+}
+
static int
__set_power_wells(struct i915_power_domains *power_domains,
const struct i915_power_well_desc *power_well_descs,
@@ -2062,9 +2123,13 @@ __set_power_wells(struct i915_power_domains *power_domains,
if (BIT_ULL(id) & skip_mask)
continue;
- power_domains->power_wells[plt_idx++].desc =
+ power_domains->power_wells[plt_idx].desc =
&power_well_descs[i];
+ init_power_well_domains(&power_well_descs[i], &power_domains->power_wells[plt_idx]);
+
+ plt_idx++;
+
if (id == DISP_PW_ID_NONE)
continue;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 8d9bc7a654106..b3d648dfeaea3 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -155,7 +155,7 @@ const char *intel_power_well_name(struct i915_power_well *power_well)
u64 intel_power_well_domains(struct i915_power_well *power_well)
{
- return power_well->desc->domains;
+ return power_well->domains;
}
int intel_power_well_refcount(struct i915_power_well *power_well)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index 26fe9e1048bcc..0926b858d7155 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -50,7 +50,10 @@ enum i915_power_well_id {
struct i915_power_well_desc {
const char *name;
- u64 domains;
+ const struct i915_power_domain_list {
+ const enum intel_display_power_domain *list;
+ u8 count;
+ } *domain_list;
/* Mask of pipes whose IRQ logic is backed by the pw */
u16 irq_pipe_mask:4;
u16 always_on:1;
@@ -99,6 +102,7 @@ struct i915_power_well_desc {
struct i915_power_well {
const struct i915_power_well_desc *desc;
+ u64 domains;
/* power well enable/disable usage count */
int count;
/* cached hw enabled state */
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 09/18] drm/i915: Convert the u64 power well domains mask to a bitmap
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (7 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 08/18] drm/i915: Convert the power well descriptor domain mask to an array of domains Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 10/18] drm/i915: Simplify power well definitions by adding power well instances Imre Deak
` (16 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx; +Cc: Jani Nikula
To remove the aliasing of the power domain enum values in a follow-up
patch in this patchset (requiring a bigger mask) and allow for defining
additional power domains in the future (at least some upcoming TypeC
changes requires this) convert the u64 i915_power_well_desc::domains
mask to a bitmap.
For simplicity I changed the for_each_power_domain_well() macros to
accept one domain only instead of a mask, as there isn't any current
user passing multiple domains.
v2: Don't add a typedef for the bitmap struct. (Jani)
Cc: Jani Nikula <jani.nikula@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/intel_display.c | 65 ++++++-----
.../drm/i915/display/intel_display_power.c | 108 +++++++++++-------
.../drm/i915/display/intel_display_power.h | 18 +--
.../i915/display/intel_display_power_map.c | 4 +-
.../i915/display/intel_display_power_well.c | 4 +-
.../i915/display/intel_display_power_well.h | 5 +-
6 files changed, 116 insertions(+), 88 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index 28ba0319357e6..fa6580cdbc4b2 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -2273,66 +2273,71 @@ intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
}
}
-static u64 get_crtc_power_domains(struct intel_crtc_state *crtc_state)
+static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
+ struct intel_power_domain_mask *mask)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum transcoder cpu_transcoder = crtc_state->cpu_transcoder;
struct drm_encoder *encoder;
enum pipe pipe = crtc->pipe;
- u64 mask;
+
+ bitmap_zero(mask->bits, POWER_DOMAIN_NUM);
if (!crtc_state->hw.active)
- return 0;
+ return;
- mask = BIT_ULL(POWER_DOMAIN_PIPE(pipe));
- mask |= BIT_ULL(POWER_DOMAIN_TRANSCODER(cpu_transcoder));
+ set_bit(POWER_DOMAIN_PIPE(pipe), mask->bits);
+ set_bit(POWER_DOMAIN_TRANSCODER(cpu_transcoder), mask->bits);
if (crtc_state->pch_pfit.enabled ||
crtc_state->pch_pfit.force_thru)
- mask |= BIT_ULL(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe));
+ set_bit(POWER_DOMAIN_PIPE_PANEL_FITTER(pipe), mask->bits);
drm_for_each_encoder_mask(encoder, &dev_priv->drm,
crtc_state->uapi.encoder_mask) {
struct intel_encoder *intel_encoder = to_intel_encoder(encoder);
- mask |= BIT_ULL(intel_encoder->power_domain);
+ set_bit(intel_encoder->power_domain, mask->bits);
}
if (HAS_DDI(dev_priv) && crtc_state->has_audio)
- mask |= BIT_ULL(POWER_DOMAIN_AUDIO_MMIO);
+ set_bit(POWER_DOMAIN_AUDIO_MMIO, mask->bits);
if (crtc_state->shared_dpll)
- mask |= BIT_ULL(POWER_DOMAIN_DISPLAY_CORE);
+ set_bit(POWER_DOMAIN_DISPLAY_CORE, mask->bits);
if (crtc_state->dsc.compression_enable)
- mask |= BIT_ULL(intel_dsc_power_domain(crtc, cpu_transcoder));
-
- return mask;
+ set_bit(intel_dsc_power_domain(crtc, cpu_transcoder), mask->bits);
}
-static u64
-modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state)
+static void
+modeset_get_crtc_power_domains(struct intel_crtc_state *crtc_state,
+ struct intel_power_domain_mask *old_domains)
{
struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc);
struct drm_i915_private *dev_priv = to_i915(crtc->base.dev);
enum intel_display_power_domain domain;
- u64 domains, new_domains, old_domains;
+ struct intel_power_domain_mask domains, new_domains;
- domains = get_crtc_power_domains(crtc_state);
+ get_crtc_power_domains(crtc_state, &domains);
- new_domains = domains & ~crtc->enabled_power_domains.mask;
- old_domains = crtc->enabled_power_domains.mask & ~domains;
+ bitmap_andnot(new_domains.bits,
+ domains.bits,
+ crtc->enabled_power_domains.mask.bits,
+ POWER_DOMAIN_NUM);
+ bitmap_andnot(old_domains->bits,
+ crtc->enabled_power_domains.mask.bits,
+ domains.bits,
+ POWER_DOMAIN_NUM);
- for_each_power_domain(domain, new_domains)
+ for_each_power_domain(domain, &new_domains)
intel_display_power_get_in_set(dev_priv,
&crtc->enabled_power_domains,
domain);
-
- return old_domains;
}
static void modeset_put_crtc_power_domains(struct intel_crtc *crtc,
- u64 domains)
+ struct intel_power_domain_mask *domains)
{
intel_display_power_put_mask_in_set(to_i915(crtc->base.dev),
&crtc->enabled_power_domains,
@@ -8545,7 +8550,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
struct drm_i915_private *dev_priv = to_i915(dev);
struct intel_crtc_state *new_crtc_state, *old_crtc_state;
struct intel_crtc *crtc;
- u64 put_domains[I915_MAX_PIPES] = {};
+ struct intel_power_domain_mask put_domains[I915_MAX_PIPES] = {};
intel_wakeref_t wakeref = 0;
int i;
@@ -8562,9 +8567,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
new_crtc_state, i) {
if (intel_crtc_needs_modeset(new_crtc_state) ||
new_crtc_state->update_pipe) {
-
- put_domains[crtc->pipe] =
- modeset_get_crtc_power_domains(new_crtc_state);
+ modeset_get_crtc_power_domains(new_crtc_state, &put_domains[crtc->pipe]);
}
}
@@ -8663,7 +8666,7 @@ static void intel_atomic_commit_tail(struct intel_atomic_state *state)
for_each_oldnew_intel_crtc_in_state(state, crtc, old_crtc_state, new_crtc_state, i) {
intel_post_plane_update(state, crtc);
- modeset_put_crtc_power_domains(crtc, put_domains[crtc->pipe]);
+ modeset_put_crtc_power_domains(crtc, &put_domains[crtc->pipe]);
intel_modeset_verify_crtc(crtc, state, old_crtc_state, new_crtc_state);
@@ -10502,11 +10505,11 @@ intel_modeset_setup_hw_state(struct drm_device *dev,
for_each_intel_crtc(dev, crtc) {
struct intel_crtc_state *crtc_state =
to_intel_crtc_state(crtc->base.state);
- u64 put_domains;
+ struct intel_power_domain_mask put_domains;
- put_domains = modeset_get_crtc_power_domains(crtc_state);
- if (drm_WARN_ON(dev, put_domains))
- modeset_put_crtc_power_domains(crtc, put_domains);
+ modeset_get_crtc_power_domains(crtc_state, &put_domains);
+ if (drm_WARN_ON(dev, !bitmap_empty(put_domains.bits, POWER_DOMAIN_NUM)))
+ modeset_put_crtc_power_domains(crtc, &put_domains);
}
intel_display_power_put(dev_priv, POWER_DOMAIN_INIT, wakeref);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index b9ba8500bf984..9dc1be8cc1582 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -22,13 +22,13 @@
#include "intel_snps_phy.h"
#include "vlv_sideband.h"
-#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
for_each_power_well(__dev_priv, __power_well) \
- for_each_if((__power_well)->domains & (__domain_mask))
+ for_each_if(test_bit((__domain), (__power_well)->domains.bits))
-#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \
for_each_power_well_reverse(__dev_priv, __power_well) \
- for_each_if((__power_well)->domains & (__domain_mask))
+ for_each_if(test_bit((__domain), (__power_well)->domains.bits))
const char *
intel_display_power_domain_str(enum intel_display_power_domain domain)
@@ -191,7 +191,7 @@ bool __intel_display_power_is_enabled(struct drm_i915_private *dev_priv,
is_enabled = true;
- for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain)) {
+ for_each_power_domain_well_reverse(dev_priv, power_well, domain) {
if (intel_power_well_is_always_on(power_well))
continue;
@@ -307,10 +307,13 @@ void intel_display_power_set_target_dc_state(struct drm_i915_private *dev_priv,
#define POWER_DOMAIN_MASK (GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0))
-static u64 __async_put_domains_mask(struct i915_power_domains *power_domains)
+static void __async_put_domains_mask(struct i915_power_domains *power_domains,
+ struct intel_power_domain_mask *mask)
{
- return power_domains->async_put_domains[0] |
- power_domains->async_put_domains[1];
+ bitmap_or(mask->bits,
+ power_domains->async_put_domains[0].bits,
+ power_domains->async_put_domains[1].bits,
+ POWER_DOMAIN_NUM);
}
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
@@ -321,8 +324,11 @@ assert_async_put_domain_masks_disjoint(struct i915_power_domains *power_domains)
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
power_domains);
- return !drm_WARN_ON(&i915->drm, power_domains->async_put_domains[0] &
- power_domains->async_put_domains[1]);
+
+ return !drm_WARN_ON(&i915->drm,
+ bitmap_intersects(power_domains->async_put_domains[0].bits,
+ power_domains->async_put_domains[1].bits,
+ POWER_DOMAIN_NUM));
}
static bool
@@ -331,14 +337,17 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
power_domains);
+ struct intel_power_domain_mask async_put_mask;
enum intel_display_power_domain domain;
bool err = false;
err |= !assert_async_put_domain_masks_disjoint(power_domains);
- err |= drm_WARN_ON(&i915->drm, !!power_domains->async_put_wakeref !=
- !!__async_put_domains_mask(power_domains));
+ __async_put_domains_mask(power_domains, &async_put_mask);
+ err |= drm_WARN_ON(&i915->drm,
+ !!power_domains->async_put_wakeref !=
+ !bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM));
- for_each_power_domain(domain, __async_put_domains_mask(power_domains))
+ for_each_power_domain(domain, &async_put_mask)
err |= drm_WARN_ON(&i915->drm,
power_domains->domain_use_count[domain] != 1);
@@ -346,14 +355,14 @@ __async_put_domains_state_ok(struct i915_power_domains *power_domains)
}
static void print_power_domains(struct i915_power_domains *power_domains,
- const char *prefix, u64 mask)
+ const char *prefix, struct intel_power_domain_mask *mask)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
power_domains);
enum intel_display_power_domain domain;
- drm_dbg(&i915->drm, "%s (%lu):\n", prefix, hweight64(mask));
+ drm_dbg(&i915->drm, "%s (%d):\n", prefix, bitmap_weight(mask->bits, POWER_DOMAIN_NUM));
for_each_power_domain(domain, mask)
drm_dbg(&i915->drm, "%s use_count %d\n",
intel_display_power_domain_str(domain),
@@ -371,9 +380,9 @@ print_async_put_domains_state(struct i915_power_domains *power_domains)
power_domains->async_put_wakeref);
print_power_domains(power_domains, "async_put_domains[0]",
- power_domains->async_put_domains[0]);
+ &power_domains->async_put_domains[0]);
print_power_domains(power_domains, "async_put_domains[1]",
- power_domains->async_put_domains[1]);
+ &power_domains->async_put_domains[1]);
}
static void
@@ -397,11 +406,13 @@ verify_async_put_domains_state(struct i915_power_domains *power_domains)
#endif /* CONFIG_DRM_I915_DEBUG_RUNTIME_PM */
-static u64 async_put_domains_mask(struct i915_power_domains *power_domains)
+static void async_put_domains_mask(struct i915_power_domains *power_domains,
+ struct intel_power_domain_mask *mask)
+
{
assert_async_put_domain_masks_disjoint(power_domains);
- return __async_put_domains_mask(power_domains);
+ __async_put_domains_mask(power_domains, mask);
}
static void
@@ -410,8 +421,8 @@ async_put_domains_clear_domain(struct i915_power_domains *power_domains,
{
assert_async_put_domain_masks_disjoint(power_domains);
- power_domains->async_put_domains[0] &= ~BIT_ULL(domain);
- power_domains->async_put_domains[1] &= ~BIT_ULL(domain);
+ clear_bit(domain, power_domains->async_put_domains[0].bits);
+ clear_bit(domain, power_domains->async_put_domains[1].bits);
}
static bool
@@ -419,16 +430,19 @@ intel_display_power_grab_async_put_ref(struct drm_i915_private *dev_priv,
enum intel_display_power_domain domain)
{
struct i915_power_domains *power_domains = &dev_priv->power_domains;
+ struct intel_power_domain_mask async_put_mask;
bool ret = false;
- if (!(async_put_domains_mask(power_domains) & BIT_ULL(domain)))
+ async_put_domains_mask(power_domains, &async_put_mask);
+ if (!test_bit(domain, async_put_mask.bits))
goto out_verify;
async_put_domains_clear_domain(power_domains, domain);
ret = true;
- if (async_put_domains_mask(power_domains))
+ async_put_domains_mask(power_domains, &async_put_mask);
+ if (!bitmap_empty(async_put_mask.bits, POWER_DOMAIN_NUM))
goto out_verify;
cancel_delayed_work(&power_domains->async_put_work);
@@ -450,7 +464,7 @@ __intel_display_power_get_domain(struct drm_i915_private *dev_priv,
if (intel_display_power_grab_async_put_ref(dev_priv, domain))
return;
- for_each_power_domain_well(dev_priv, power_well, BIT_ULL(domain))
+ for_each_power_domain_well(dev_priv, power_well, domain)
intel_power_well_get(dev_priv, power_well);
power_domains->domain_use_count[domain]++;
@@ -531,20 +545,22 @@ __intel_display_power_put_domain(struct drm_i915_private *dev_priv,
struct i915_power_domains *power_domains;
struct i915_power_well *power_well;
const char *name = intel_display_power_domain_str(domain);
+ struct intel_power_domain_mask async_put_mask;
power_domains = &dev_priv->power_domains;
drm_WARN(&dev_priv->drm, !power_domains->domain_use_count[domain],
"Use count on domain %s is already zero\n",
name);
+ async_put_domains_mask(power_domains, &async_put_mask);
drm_WARN(&dev_priv->drm,
- async_put_domains_mask(power_domains) & BIT_ULL(domain),
+ test_bit(domain, async_put_mask.bits),
"Async disabling of domain %s is pending\n",
name);
power_domains->domain_use_count[domain]--;
- for_each_power_domain_well_reverse(dev_priv, power_well, BIT_ULL(domain))
+ for_each_power_domain_well_reverse(dev_priv, power_well, domain)
intel_power_well_put(dev_priv, power_well);
}
@@ -573,7 +589,8 @@ queue_async_put_domains_work(struct i915_power_domains *power_domains,
}
static void
-release_async_put_domains(struct i915_power_domains *power_domains, u64 mask)
+release_async_put_domains(struct i915_power_domains *power_domains,
+ struct intel_power_domain_mask *mask)
{
struct drm_i915_private *dev_priv =
container_of(power_domains, struct drm_i915_private,
@@ -621,12 +638,15 @@ intel_display_power_put_async_work(struct work_struct *work)
goto out_verify;
release_async_put_domains(power_domains,
- power_domains->async_put_domains[0]);
+ &power_domains->async_put_domains[0]);
/* Requeue the work if more domains were async put meanwhile. */
- if (power_domains->async_put_domains[1]) {
- power_domains->async_put_domains[0] =
- fetch_and_zero(&power_domains->async_put_domains[1]);
+ if (!bitmap_empty(power_domains->async_put_domains[1].bits, POWER_DOMAIN_NUM)) {
+ bitmap_copy(power_domains->async_put_domains[0].bits,
+ power_domains->async_put_domains[1].bits,
+ POWER_DOMAIN_NUM);
+ bitmap_zero(power_domains->async_put_domains[1].bits,
+ POWER_DOMAIN_NUM);
queue_async_put_domains_work(power_domains,
fetch_and_zero(&new_work_wakeref));
} else {
@@ -678,9 +698,9 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
/* Let a pending work requeue itself or queue a new one. */
if (power_domains->async_put_wakeref) {
- power_domains->async_put_domains[1] |= BIT_ULL(domain);
+ set_bit(domain, power_domains->async_put_domains[1].bits);
} else {
- power_domains->async_put_domains[0] |= BIT_ULL(domain);
+ set_bit(domain, power_domains->async_put_domains[0].bits);
queue_async_put_domains_work(power_domains,
fetch_and_zero(&work_wakeref));
}
@@ -711,6 +731,7 @@ void __intel_display_power_put_async(struct drm_i915_private *i915,
void intel_display_power_flush_work(struct drm_i915_private *i915)
{
struct i915_power_domains *power_domains = &i915->power_domains;
+ struct intel_power_domain_mask async_put_mask;
intel_wakeref_t work_wakeref;
mutex_lock(&power_domains->lock);
@@ -719,8 +740,8 @@ void intel_display_power_flush_work(struct drm_i915_private *i915)
if (!work_wakeref)
goto out_verify;
- release_async_put_domains(power_domains,
- async_put_domains_mask(power_domains));
+ async_put_domains_mask(power_domains, &async_put_mask);
+ release_async_put_domains(power_domains, &async_put_mask);
cancel_delayed_work(&power_domains->async_put_work);
out_verify:
@@ -799,13 +820,13 @@ intel_display_power_get_in_set(struct drm_i915_private *i915,
{
intel_wakeref_t __maybe_unused wf;
- drm_WARN_ON(&i915->drm, power_domain_set->mask & BIT_ULL(domain));
+ drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
wf = intel_display_power_get(i915, domain);
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
power_domain_set->wakerefs[domain] = wf;
#endif
- power_domain_set->mask |= BIT_ULL(domain);
+ set_bit(domain, power_domain_set->mask.bits);
}
bool
@@ -815,7 +836,7 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
{
intel_wakeref_t wf;
- drm_WARN_ON(&i915->drm, power_domain_set->mask & BIT_ULL(domain));
+ drm_WARN_ON(&i915->drm, test_bit(domain, power_domain_set->mask.bits));
wf = intel_display_power_get_if_enabled(i915, domain);
if (!wf)
@@ -824,7 +845,7 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
#if IS_ENABLED(CONFIG_DRM_I915_DEBUG_RUNTIME_PM)
power_domain_set->wakerefs[domain] = wf;
#endif
- power_domain_set->mask |= BIT_ULL(domain);
+ set_bit(domain, power_domain_set->mask.bits);
return true;
}
@@ -832,11 +853,12 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
void
intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
struct intel_display_power_domain_set *power_domain_set,
- u64 mask)
+ struct intel_power_domain_mask *mask)
{
enum intel_display_power_domain domain;
- drm_WARN_ON(&i915->drm, mask & ~power_domain_set->mask);
+ drm_WARN_ON(&i915->drm,
+ !bitmap_subset(mask->bits, power_domain_set->mask.bits, POWER_DOMAIN_NUM));
for_each_power_domain(domain, mask) {
intel_wakeref_t __maybe_unused wf = -1;
@@ -845,7 +867,7 @@ intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
wf = fetch_and_zero(&power_domain_set->wakerefs[domain]);
#endif
intel_display_power_put(i915, domain, wf);
- power_domain_set->mask &= ~BIT_ULL(domain);
+ clear_bit(domain, power_domain_set->mask.bits);
}
}
@@ -947,8 +969,6 @@ int intel_power_domains_init(struct drm_i915_private *dev_priv)
dev_priv->dmc.target_dc_state =
sanitize_target_dc_state(dev_priv, DC_STATE_EN_UPTO_DC6);
- BUILD_BUG_ON(POWER_DOMAIN_NUM > 64);
-
mutex_init(&power_domains->lock);
INIT_DELAYED_WORK(&power_domains->async_put_work,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 5ae81e3300224..66fef12ef3db4 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -139,6 +139,10 @@ enum intel_display_power_domain {
((tran) == TRANSCODER_EDP ? POWER_DOMAIN_TRANSCODER_EDP : \
(tran) + POWER_DOMAIN_TRANSCODER_A)
+struct intel_power_domain_mask {
+ DECLARE_BITMAP(bits, POWER_DOMAIN_NUM);
+};
+
struct i915_power_domains {
/*
* Power wells needed for initialization at driver init and suspend
@@ -156,21 +160,21 @@ struct i915_power_domains {
struct delayed_work async_put_work;
intel_wakeref_t async_put_wakeref;
- u64 async_put_domains[2];
+ struct intel_power_domain_mask async_put_domains[2];
struct i915_power_well *power_wells;
};
struct intel_display_power_domain_set {
- u64 mask;
+ struct intel_power_domain_mask mask;
#ifdef CONFIG_DRM_I915_DEBUG_RUNTIME_PM
intel_wakeref_t wakerefs[POWER_DOMAIN_NUM];
#endif
};
-#define for_each_power_domain(domain, mask) \
- for ((domain) = 0; (domain) < POWER_DOMAIN_NUM; (domain)++) \
- for_each_if(BIT_ULL(domain) & (mask))
+#define for_each_power_domain(__domain, __mask) \
+ for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \
+ for_each_if(test_bit((__domain), (__mask)->bits))
int intel_power_domains_init(struct drm_i915_private *dev_priv);
void intel_power_domains_cleanup(struct drm_i915_private *dev_priv);
@@ -251,13 +255,13 @@ intel_display_power_get_in_set_if_enabled(struct drm_i915_private *i915,
void
intel_display_power_put_mask_in_set(struct drm_i915_private *i915,
struct intel_display_power_domain_set *power_domain_set,
- u64 mask);
+ struct intel_power_domain_mask *mask);
static inline void
intel_display_power_put_all_in_set(struct drm_i915_private *i915,
struct intel_display_power_domain_set *power_domain_set)
{
- intel_display_power_put_mask_in_set(i915, power_domain_set, power_domain_set->mask);
+ intel_display_power_put_mask_in_set(i915, power_domain_set, &power_domain_set->mask);
}
void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index b7aa13d6a33f3..a9e0ebf18fca5 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -2084,13 +2084,13 @@ static void init_power_well_domains(const struct i915_power_well_desc *desc,
return;
if (desc->domain_list->count == 0) {
- power_well->domains = GENMASK_ULL(POWER_DOMAIN_NUM - 1, 0);
+ bitmap_fill(power_well->domains.bits, POWER_DOMAIN_NUM);
return;
}
for (j = 0; j < desc->domain_list->count; j++)
- power_well->domains |= BIT_ULL(desc->domain_list->list[j]);
+ set_bit(desc->domain_list->list[j], power_well->domains.bits);
}
static int
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index b3d648dfeaea3..5d8145bcb90eb 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -153,9 +153,9 @@ const char *intel_power_well_name(struct i915_power_well *power_well)
return power_well->desc->name;
}
-u64 intel_power_well_domains(struct i915_power_well *power_well)
+struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well)
{
- return power_well->domains;
+ return &power_well->domains;
}
int intel_power_well_refcount(struct i915_power_well *power_well)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index 0926b858d7155..bd60fb4166e74 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -8,6 +8,7 @@
#include <linux/types.h>
#include "intel_display.h"
+#include "intel_display_power.h"
struct drm_i915_private;
struct i915_power_well;
@@ -102,7 +103,7 @@ struct i915_power_well_desc {
struct i915_power_well {
const struct i915_power_well_desc *desc;
- u64 domains;
+ struct intel_power_domain_mask domains;
/* power well enable/disable usage count */
int count;
/* cached hw enabled state */
@@ -129,7 +130,7 @@ bool intel_display_power_well_is_enabled(struct drm_i915_private *dev_priv,
enum i915_power_well_id power_well_id);
bool intel_power_well_is_always_on(struct i915_power_well *power_well);
const char *intel_power_well_name(struct i915_power_well *power_well);
-u64 intel_power_well_domains(struct i915_power_well *power_well);
+struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well);
int intel_power_well_refcount(struct i915_power_well *power_well);
void chv_phy_powergate_lanes(struct intel_encoder *encoder,
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 10/18] drm/i915: Simplify power well definitions by adding power well instances
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (8 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 09/18] drm/i915: Convert the u64 power well domains mask to a bitmap Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 11/18] drm/i915: Allow platforms to share power well descriptors Imre Deak
` (15 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
All the port specific AUX/DDI_IO power wells share the same power well
ops struct and flags, so we can save some space and simplify the
definition of these by listing for all such power wells only the params
specific to them (name, domains, power well register index, id). Move
these params to a new i915_power_well_instance struct and convert the
per-platform power well definitions accordingly.
For all power well instance the name and power domain list params must
be specified, while the register index and id are optional, add the
I915_PW() macro that both simplifies the definitions and ensures that
the required params are set.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
.../i915/display/intel_display_power_map.c | 1515 +++++------------
.../i915/display/intel_display_power_well.c | 72 +-
.../i915/display/intel_display_power_well.h | 48 +-
3 files changed, 505 insertions(+), 1130 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index a9e0ebf18fca5..c282e05bfc1ac 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -30,16 +30,23 @@
#define I915_PW_DOMAINS_NONE NULL
#define I915_PW_DOMAINS_ALL /* zero-length list */
+#define I915_PW_INSTANCES(...) \
+ (const struct i915_power_well_instance_list) \
+ __LIST(__LIST_INLINE_ELEMS(struct i915_power_well_instance, __VA_ARGS__))
+
+#define I915_PW(_name, _domain_list, ...) \
+ { .name = _name, .domain_list = _domain_list, ## __VA_ARGS__ }
+
I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
},
};
@@ -54,16 +61,16 @@ I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
static const struct i915_power_well_desc i830_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "pipes",
- .domain_list = &i830_pwdoms_pipes,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("pipes", &i830_pwdoms_pipes),
+ ),
.ops = &i830_pipes_power_well_ops,
- .id = DISP_PW_ID_NONE,
},
};
@@ -87,20 +94,19 @@ I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
static const struct i915_power_well_desc hsw_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "display",
- .domain_list = &hsw_pwdoms_display,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("display", &hsw_pwdoms_display,
+ .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
+ .id = HSW_DISP_PW_GLOBAL),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
- .id = HSW_DISP_PW_GLOBAL,
- {
- .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
- },
},
};
@@ -123,21 +129,20 @@ I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
static const struct i915_power_well_desc bdw_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "display",
- .domain_list = &bdw_pwdoms_display,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("display", &bdw_pwdoms_display,
+ .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
+ .id = HSW_DISP_PW_GLOBAL),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
- .id = HSW_DISP_PW_GLOBAL,
- {
- .hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
- },
},
};
@@ -178,59 +183,37 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
static const struct i915_power_well_desc vlv_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "display",
- .domain_list = &vlv_pwdoms_display,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("display", &vlv_pwdoms_display,
+ .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
+ .id = VLV_DISP_PW_DISP2D),
+ ),
.ops = &vlv_display_power_well_ops,
- .id = VLV_DISP_PW_DISP2D,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DISP2D,
- },
}, {
- .name = "dpio-tx-b-01",
- .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("dpio-tx-b-01", &vlv_pwdoms_dpio_tx_bc_lanes,
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01),
+ I915_PW("dpio-tx-b-23", &vlv_pwdoms_dpio_tx_bc_lanes,
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23),
+ I915_PW("dpio-tx-c-01", &vlv_pwdoms_dpio_tx_bc_lanes,
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01),
+ I915_PW("dpio-tx-c-23", &vlv_pwdoms_dpio_tx_bc_lanes,
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23),
+ ),
.ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_01,
- },
}, {
- .name = "dpio-tx-b-23",
- .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
- .ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_B_LANES_23,
- },
- }, {
- .name = "dpio-tx-c-01",
- .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
- .ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_01,
- },
- }, {
- .name = "dpio-tx-c-23",
- .domain_list = &vlv_pwdoms_dpio_tx_bc_lanes,
- .ops = &vlv_dpio_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_TX_C_LANES_23,
- },
- }, {
- .name = "dpio-common",
- .domain_list = &vlv_pwdoms_dpio_cmn_bc,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("dpio-common", &vlv_pwdoms_dpio_cmn_bc,
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
+ .id = VLV_DISP_PW_DPIO_CMN_BC),
+ ),
.ops = &vlv_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
- },
},
};
@@ -272,37 +255,31 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
static const struct i915_power_well_desc chv_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "display",
/*
* Pipe A power well is the new disp2d well. Pipe B and C
* power wells don't actually exist. Pipe A power well is
* required for any pipe to work.
*/
- .domain_list = &chv_pwdoms_display,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("display", &chv_pwdoms_display),
+ ),
.ops = &chv_pipe_power_well_ops,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "dpio-common-bc",
- .domain_list = &chv_pwdoms_dpio_cmn_bc,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("dpio-common-bc", &chv_pwdoms_dpio_cmn_bc,
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
+ .id = VLV_DISP_PW_DPIO_CMN_BC),
+ I915_PW("dpio-common-d", &chv_pwdoms_dpio_cmn_d,
+ .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
+ .id = CHV_DISP_PW_DPIO_CMN_D),
+ ),
.ops = &chv_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_BC,
- },
- }, {
- .name = "dpio-common-d",
- .domain_list = &chv_pwdoms_dpio_cmn_d,
- .ops = &chv_dpio_cmn_power_well_ops,
- .id = CHV_DISP_PW_DPIO_CMN_D,
- {
- .vlv.idx = PUNIT_PWGT_IDX_DPIO_CMN_D,
- },
},
};
@@ -355,80 +332,54 @@ I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
static const struct i915_power_well_desc skl_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "MISC_IO",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("MISC_IO", I915_PW_DOMAINS_NONE,
+ .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
+ .id = SKL_DISP_PW_MISC_IO),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
- .id = SKL_DISP_PW_MISC_IO,
- {
- .hsw.idx = SKL_PW_CTL_IDX_MISC_IO,
- },
}, {
- .name = "DC_off",
- .domain_list = &skl_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &skl_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_2",
- .domain_list = &skl_pwdoms_pw_2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &skl_pwdoms_pw_2,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.has_fuses = true,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_2,
- },
}, {
- .name = "DDI_IO_A_E",
- .domain_list = &skl_pwdoms_ddi_io_a_e,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DDI_IO_A_E", &skl_pwdoms_ddi_io_a_e, .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E),
+ I915_PW("DDI_IO_B", &skl_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &skl_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C),
+ I915_PW("DDI_IO_D", &skl_pwdoms_ddi_io_d, .hsw.idx = SKL_PW_CTL_IDX_DDI_D),
+ ),
.ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_A_E,
- },
- }, {
- .name = "DDI_IO_B",
- .domain_list = &skl_pwdoms_ddi_io_b,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
- },
- }, {
- .name = "DDI_IO_C",
- .domain_list = &skl_pwdoms_ddi_io_c,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
- },
- }, {
- .name = "DDI_IO_D",
- .domain_list = &skl_pwdoms_ddi_io_d,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_D,
- },
},
};
@@ -474,54 +425,47 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
static const struct i915_power_well_desc bxt_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "DC_off",
- .domain_list = &bxt_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &bxt_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_2",
- .domain_list = &bxt_pwdoms_pw_2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &bxt_pwdoms_pw_2,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.has_fuses = true,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_2,
- },
}, {
- .name = "dpio-common-a",
- .domain_list = &bxt_pwdoms_dpio_cmn_a,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("dpio-common-a", &bxt_pwdoms_dpio_cmn_a,
+ .bxt.phy = DPIO_PHY1,
+ .id = BXT_DISP_PW_DPIO_CMN_A),
+ I915_PW("dpio-common-bc", &bxt_pwdoms_dpio_cmn_bc,
+ .bxt.phy = DPIO_PHY0,
+ .id = VLV_DISP_PW_DPIO_CMN_BC),
+ ),
.ops = &bxt_dpio_cmn_power_well_ops,
- .id = BXT_DISP_PW_DPIO_CMN_A,
- {
- .bxt.phy = DPIO_PHY1,
- },
- }, {
- .name = "dpio-common-bc",
- .domain_list = &bxt_pwdoms_dpio_cmn_bc,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .bxt.phy = DPIO_PHY0,
- },
},
};
@@ -587,110 +531,60 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
static const struct i915_power_well_desc glk_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "DC_off",
- .domain_list = &glk_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &glk_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_2",
- .domain_list = &glk_pwdoms_pw_2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &glk_pwdoms_pw_2,
+ .hsw.idx = SKL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B) | BIT(PIPE_C),
.has_fuses = true,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = SKL_PW_CTL_IDX_PW_2,
- },
}, {
- .name = "dpio-common-a",
- .domain_list = &glk_pwdoms_dpio_cmn_a,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("dpio-common-a", &glk_pwdoms_dpio_cmn_a,
+ .bxt.phy = DPIO_PHY1,
+ .id = BXT_DISP_PW_DPIO_CMN_A),
+ I915_PW("dpio-common-b", &glk_pwdoms_dpio_cmn_b,
+ .bxt.phy = DPIO_PHY0,
+ .id = VLV_DISP_PW_DPIO_CMN_BC),
+ I915_PW("dpio-common-c", &glk_pwdoms_dpio_cmn_c,
+ .bxt.phy = DPIO_PHY2,
+ .id = GLK_DISP_PW_DPIO_CMN_C),
+ ),
.ops = &bxt_dpio_cmn_power_well_ops,
- .id = BXT_DISP_PW_DPIO_CMN_A,
- {
- .bxt.phy = DPIO_PHY1,
- },
}, {
- .name = "dpio-common-b",
- .domain_list = &glk_pwdoms_dpio_cmn_b,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = VLV_DISP_PW_DPIO_CMN_BC,
- {
- .bxt.phy = DPIO_PHY0,
- },
- }, {
- .name = "dpio-common-c",
- .domain_list = &glk_pwdoms_dpio_cmn_c,
- .ops = &bxt_dpio_cmn_power_well_ops,
- .id = GLK_DISP_PW_DPIO_CMN_C,
- {
- .bxt.phy = DPIO_PHY2,
- },
- }, {
- .name = "AUX_A",
- .domain_list = &glk_pwdoms_aux_a,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_AUX_A,
- },
- }, {
- .name = "AUX_B",
- .domain_list = &glk_pwdoms_aux_b,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_AUX_B,
- },
- }, {
- .name = "AUX_C",
- .domain_list = &glk_pwdoms_aux_c,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_AUX_C,
- },
- }, {
- .name = "DDI_IO_A",
- .domain_list = &glk_pwdoms_ddi_io_a,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = GLK_PW_CTL_IDX_DDI_A,
- },
- }, {
- .name = "DDI_IO_B",
- .domain_list = &glk_pwdoms_ddi_io_b,
- .ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_B,
- },
- }, {
- .name = "DDI_IO_C",
- .domain_list = &glk_pwdoms_ddi_io_c,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_A", &glk_pwdoms_aux_a, .hsw.idx = GLK_PW_CTL_IDX_AUX_A),
+ I915_PW("AUX_B", &glk_pwdoms_aux_b, .hsw.idx = GLK_PW_CTL_IDX_AUX_B),
+ I915_PW("AUX_C", &glk_pwdoms_aux_c, .hsw.idx = GLK_PW_CTL_IDX_AUX_C),
+ I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = GLK_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = SKL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = SKL_PW_CTL_IDX_DDI_C),
+ ),
.ops = &hsw_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = SKL_PW_CTL_IDX_DDI_C,
- },
},
};
@@ -790,193 +684,82 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT_F);
static const struct i915_power_well_desc icl_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "DC_off",
- .domain_list = &icl_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &icl_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_2",
- .domain_list = &icl_pwdoms_pw_2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &icl_pwdoms_pw_2,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- },
}, {
- .name = "PW_3",
- .domain_list = &icl_pwdoms_pw_3,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_3", &icl_pwdoms_pw_3,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .id = ICL_DISP_PW_3),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B),
.has_fuses = true,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- },
}, {
- .name = "DDI_IO_A",
- .domain_list = &icl_pwdoms_ddi_io_a,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &icl_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
+ I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = ICL_PW_CTL_IDX_DDI_D),
+ I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = ICL_PW_CTL_IDX_DDI_E),
+ I915_PW("DDI_IO_F", &icl_pwdoms_ddi_io_f, .hsw.idx = ICL_PW_CTL_IDX_DDI_F),
+ ),
.ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- },
}, {
- .name = "DDI_IO_B",
- .domain_list = &icl_pwdoms_ddi_io_b,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- },
- }, {
- .name = "DDI_IO_C",
- .domain_list = &icl_pwdoms_ddi_io_c,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
- },
- }, {
- .name = "DDI_IO_D",
- .domain_list = &icl_pwdoms_ddi_io_d,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_D,
- },
- }, {
- .name = "DDI_IO_E",
- .domain_list = &icl_pwdoms_ddi_io_e,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_E,
- },
- }, {
- .name = "DDI_IO_F",
- .domain_list = &icl_pwdoms_ddi_io_f,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_F,
- },
- }, {
- .name = "AUX_A",
- .domain_list = &icl_pwdoms_aux_a,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- }, {
- .name = "AUX_B",
- .domain_list = &icl_pwdoms_aux_b,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
+ I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
+ I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
+ I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = ICL_PW_CTL_IDX_AUX_D),
+ I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = ICL_PW_CTL_IDX_AUX_E),
+ I915_PW("AUX_F", &icl_pwdoms_aux_f, .hsw.idx = ICL_PW_CTL_IDX_AUX_F),
+ ),
.ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- }, {
- .name = "AUX_C",
- .domain_list = &icl_pwdoms_aux_c,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- },
- }, {
- .name = "AUX_D",
- .domain_list = &icl_pwdoms_aux_d,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_D,
- },
- }, {
- .name = "AUX_E",
- .domain_list = &icl_pwdoms_aux_e,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_E,
- },
- }, {
- .name = "AUX_F",
- .domain_list = &icl_pwdoms_aux_f,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_F,
- },
- }, {
- .name = "AUX_TBT1",
- .domain_list = &icl_pwdoms_aux_tbt1,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1,
- },
- }, {
- .name = "AUX_TBT2",
- .domain_list = &icl_pwdoms_aux_tbt2,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2,
- },
- }, {
- .name = "AUX_TBT3",
- .domain_list = &icl_pwdoms_aux_tbt3,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3,
- },
}, {
- .name = "AUX_TBT4",
- .domain_list = &icl_pwdoms_aux_tbt4,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT1),
+ I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT2),
+ I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT3),
+ I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4),
+ ),
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_TBT4,
- },
}, {
- .name = "PW_4",
- .domain_list = &icl_pwdoms_pw_4,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_4", &icl_pwdoms_pw_4,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4),
+ ),
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_C),
.has_fuses = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- },
},
};
@@ -1087,276 +870,104 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
static const struct i915_power_well_desc tgl_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "DC_off",
- .domain_list = &tgl_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &tgl_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_2",
- .domain_list = &tgl_pwdoms_pw_2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &tgl_pwdoms_pw_2,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- },
}, {
- .name = "PW_3",
- .domain_list = &tgl_pwdoms_pw_3,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_3", &tgl_pwdoms_pw_3,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .id = ICL_DISP_PW_3),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
.irq_pipe_mask = BIT(PIPE_B),
.has_fuses = true,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- },
}, {
- .name = "DDI_IO_A",
- .domain_list = &icl_pwdoms_ddi_io_a,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
- }, {
- .name = "DDI_IO_B",
- .domain_list = &icl_pwdoms_ddi_io_b,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- }, {
- .name = "DDI_IO_C",
- .domain_list = &icl_pwdoms_ddi_io_c,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
- }
- }, {
- .name = "DDI_IO_TC1",
- .domain_list = &tgl_pwdoms_ddi_io_tc1,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- },
- }, {
- .name = "DDI_IO_TC2",
- .domain_list = &tgl_pwdoms_ddi_io_tc2,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- },
- }, {
- .name = "DDI_IO_TC3",
- .domain_list = &tgl_pwdoms_ddi_io_tc3,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
- },
- }, {
- .name = "DDI_IO_TC4",
- .domain_list = &tgl_pwdoms_ddi_io_tc4,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
- },
- }, {
- .name = "DDI_IO_TC5",
- .domain_list = &tgl_pwdoms_ddi_io_tc5,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5,
- },
- }, {
- .name = "DDI_IO_TC6",
- .domain_list = &tgl_pwdoms_ddi_io_tc6,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6,
- },
- }, {
- .name = "TC_cold_off",
- .domain_list = &tgl_pwdoms_tc_cold_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &icl_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
+ I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
+ I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
+ I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
+ I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4),
+ I915_PW("DDI_IO_TC5", &tgl_pwdoms_ddi_io_tc5, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC5),
+ I915_PW("DDI_IO_TC6", &tgl_pwdoms_ddi_io_tc6, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC6),
+ ),
+ .ops = &icl_ddi_power_well_ops,
+ }, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("TC_cold_off", &tgl_pwdoms_tc_cold_off,
+ .id = TGL_DISP_PW_TC_COLD_OFF),
+ ),
.ops = &tgl_tc_cold_off_ops,
- .id = TGL_DISP_PW_TC_COLD_OFF,
}, {
- .name = "AUX_A",
- .domain_list = &tgl_pwdoms_aux_a,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- }, {
- .name = "AUX_B",
- .domain_list = &tgl_pwdoms_aux_b,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- }, {
- .name = "AUX_C",
- .domain_list = &tgl_pwdoms_aux_c,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- },
- }, {
- .name = "AUX_USBC1",
- .domain_list = &tgl_pwdoms_aux_usbc1,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- },
- }, {
- .name = "AUX_USBC2",
- .domain_list = &tgl_pwdoms_aux_usbc2,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- },
- }, {
- .name = "AUX_USBC3",
- .domain_list = &tgl_pwdoms_aux_usbc3,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
- },
- }, {
- .name = "AUX_USBC4",
- .domain_list = &tgl_pwdoms_aux_usbc4,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
- },
- }, {
- .name = "AUX_USBC5",
- .domain_list = &tgl_pwdoms_aux_usbc5,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5,
- },
- }, {
- .name = "AUX_USBC6",
- .domain_list = &tgl_pwdoms_aux_usbc6,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6,
- },
- }, {
- .name = "AUX_TBT1",
- .domain_list = &tgl_pwdoms_aux_tbt1,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
- },
- }, {
- .name = "AUX_TBT2",
- .domain_list = &tgl_pwdoms_aux_tbt2,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
- },
- }, {
- .name = "AUX_TBT3",
- .domain_list = &tgl_pwdoms_aux_tbt3,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
- },
- }, {
- .name = "AUX_TBT4",
- .domain_list = &tgl_pwdoms_aux_tbt4,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
- },
- }, {
- .name = "AUX_TBT5",
- .domain_list = &tgl_pwdoms_aux_tbt5,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5,
- },
- }, {
- .name = "AUX_TBT6",
- .domain_list = &tgl_pwdoms_aux_tbt6,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_A", &tgl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
+ I915_PW("AUX_B", &tgl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
+ I915_PW("AUX_C", &tgl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
+ I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
+ I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
+ I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
+ I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
+ I915_PW("AUX_USBC5", &tgl_pwdoms_aux_usbc5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC5),
+ I915_PW("AUX_USBC6", &tgl_pwdoms_aux_usbc6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC6),
+ ),
+ .ops = &icl_aux_power_well_ops,
+ }, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_TBT1", &tgl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
+ I915_PW("AUX_TBT2", &tgl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
+ I915_PW("AUX_TBT3", &tgl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
+ I915_PW("AUX_TBT4", &tgl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
+ I915_PW("AUX_TBT5", &tgl_pwdoms_aux_tbt5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5),
+ I915_PW("AUX_TBT6", &tgl_pwdoms_aux_tbt6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6),
+ ),
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6,
- },
}, {
- .name = "PW_4",
- .domain_list = &tgl_pwdoms_pw_4,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_4", &tgl_pwdoms_pw_4,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- }
}, {
- .name = "PW_5",
- .domain_list = &tgl_pwdoms_pw_5,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_5", &tgl_pwdoms_pw_5,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_D),
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_PW_5,
- },
},
};
@@ -1416,112 +1027,61 @@ I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
static const struct i915_power_well_desc rkl_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "DC_off",
- .domain_list = &rkl_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &rkl_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_3",
- .domain_list = &rkl_pwdoms_pw_3,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_3", &rkl_pwdoms_pw_3,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .id = ICL_DISP_PW_3),
+ ),
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_vga = true,
.has_fuses = true,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- },
}, {
- .name = "PW_4",
- .domain_list = &rkl_pwdoms_pw_4,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_4", &rkl_pwdoms_pw_4,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- }
}, {
- .name = "DDI_IO_A",
- .domain_list = &icl_pwdoms_ddi_io_a,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
+ I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
+ ),
.ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
}, {
- .name = "DDI_IO_B",
- .domain_list = &icl_pwdoms_ddi_io_b,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- }, {
- .name = "DDI_IO_TC1",
- .domain_list = &tgl_pwdoms_ddi_io_tc1,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- },
- }, {
- .name = "DDI_IO_TC2",
- .domain_list = &tgl_pwdoms_ddi_io_tc2,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- },
- }, {
- .name = "AUX_A",
- .domain_list = &icl_pwdoms_aux_a,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- }, {
- .name = "AUX_B",
- .domain_list = &icl_pwdoms_aux_b,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- }, {
- .name = "AUX_USBC1",
- .domain_list = &tgl_pwdoms_aux_usbc1,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- },
- }, {
- .name = "AUX_USBC2",
- .domain_list = &tgl_pwdoms_aux_usbc2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
+ I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
+ I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
+ I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
+ ),
.ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- },
},
};
@@ -1559,133 +1119,77 @@ I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
static const struct i915_power_well_desc dg1_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "DC_off",
- .domain_list = &dg1_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &dg1_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_2",
- .domain_list = &dg1_pwdoms_pw_2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &dg1_pwdoms_pw_2,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- },
}, {
- .name = "PW_3",
- .domain_list = &dg1_pwdoms_pw_3,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_3", &dg1_pwdoms_pw_3,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_3,
+ .id = ICL_DISP_PW_3),
+ ),
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_vga = true,
.has_fuses = true,
- .id = ICL_DISP_PW_3,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_3,
- },
}, {
- .name = "DDI_IO_A",
- .domain_list = &icl_pwdoms_ddi_io_a,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
+ I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
+ ),
.ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
}, {
- .name = "DDI_IO_B",
- .domain_list = &icl_pwdoms_ddi_io_b,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- }, {
- .name = "DDI_IO_TC1",
- .domain_list = &tgl_pwdoms_ddi_io_tc1,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- },
- }, {
- .name = "DDI_IO_TC2",
- .domain_list = &tgl_pwdoms_ddi_io_tc2,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- },
- }, {
- .name = "AUX_A",
- .domain_list = &tgl_pwdoms_aux_a,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- }, {
- .name = "AUX_B",
- .domain_list = &tgl_pwdoms_aux_b,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- }, {
- .name = "AUX_USBC1",
- .domain_list = &tgl_pwdoms_aux_usbc1,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- },
- }, {
- .name = "AUX_USBC2",
- .domain_list = &tgl_pwdoms_aux_usbc2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_A", &tgl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
+ I915_PW("AUX_B", &tgl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
+ I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
+ I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
+ ),
.ops = &icl_aux_power_well_ops,
- .is_tc_tbt = false,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- },
}, {
- .name = "PW_4",
- .domain_list = &tgl_pwdoms_pw_4,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_4", &tgl_pwdoms_pw_4,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_4,
- }
}, {
- .name = "PW_5",
- .domain_list = &tgl_pwdoms_pw_5,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_5", &tgl_pwdoms_pw_5,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5),
+ ),
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_D),
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_PW_5,
- },
},
};
@@ -1816,283 +1320,131 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
static const struct i915_power_well_desc xelpd_power_wells[] = {
{
- .name = "always-on",
- .domain_list = &i9xx_pwdoms_always_on,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("always-on", &i9xx_pwdoms_always_on),
+ ),
.ops = &i9xx_always_on_power_well_ops,
.always_on = true,
- .id = DISP_PW_ID_NONE,
}, {
- .name = "PW_1",
/* Handled by the DMC firmware */
- .domain_list = I915_PW_DOMAINS_NONE,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_1", I915_PW_DOMAINS_NONE,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_1,
+ .id = SKL_DISP_PW_1),
+ ),
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- .id = SKL_DISP_PW_1,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- },
}, {
- .name = "DC_off",
- .domain_list = &xelpd_pwdoms_dc_off,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DC_off", &xelpd_pwdoms_dc_off,
+ .id = SKL_DISP_DC_OFF),
+ ),
.ops = &gen9_dc_off_power_well_ops,
- .id = SKL_DISP_DC_OFF,
}, {
- .name = "PW_2",
- .domain_list = &xelpd_pwdoms_pw_2,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_2", &xelpd_pwdoms_pw_2,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_2,
+ .id = SKL_DISP_PW_2),
+ ),
.ops = &hsw_power_well_ops,
.has_vga = true,
.has_fuses = true,
- .id = SKL_DISP_PW_2,
- {
- .hsw.idx = ICL_PW_CTL_IDX_PW_2,
- },
}, {
- .name = "PW_A",
- .domain_list = &xelpd_pwdoms_pw_a,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_A", &xelpd_pwdoms_pw_a,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_A),
+ ),
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_A),
.has_fuses = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_A,
- },
}, {
- .name = "PW_B",
- .domain_list = &xelpd_pwdoms_pw_b,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_B", &xelpd_pwdoms_pw_b,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_B),
+ ),
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_B),
.has_fuses = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_B,
- },
}, {
- .name = "PW_C",
- .domain_list = &xelpd_pwdoms_pw_c,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_C", &xelpd_pwdoms_pw_c,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_C),
+ ),
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_C),
.has_fuses = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_C,
- },
}, {
- .name = "PW_D",
- .domain_list = &xelpd_pwdoms_pw_d,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_D", &xelpd_pwdoms_pw_d,
+ .hsw.idx = XELPD_PW_CTL_IDX_PW_D),
+ ),
.ops = &hsw_power_well_ops,
.irq_pipe_mask = BIT(PIPE_D),
.has_fuses = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_PW_D,
- },
}, {
- .name = "DDI_IO_A",
- .domain_list = &icl_pwdoms_ddi_io_a,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_A,
- }
- }, {
- .name = "DDI_IO_B",
- .domain_list = &icl_pwdoms_ddi_io_b,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_B,
- }
- }, {
- .name = "DDI_IO_C",
- .domain_list = &icl_pwdoms_ddi_io_c,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_DDI_C,
- }
- }, {
- .name = "DDI_IO_D_XELPD",
- .domain_list = &xelpd_pwdoms_ddi_io_d_xelpd,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_DDI_D,
- }
- }, {
- .name = "DDI_IO_E_XELPD",
- .domain_list = &xelpd_pwdoms_ddi_io_e_xelpd,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_DDI_E,
- }
- }, {
- .name = "DDI_IO_TC1",
- .domain_list = &xelpd_pwdoms_ddi_io_tc1,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1,
- }
- }, {
- .name = "DDI_IO_TC2",
- .domain_list = &xelpd_pwdoms_ddi_io_tc2,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2,
- }
- }, {
- .name = "DDI_IO_TC3",
- .domain_list = &xelpd_pwdoms_ddi_io_tc3,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3,
- }
- }, {
- .name = "DDI_IO_TC4",
- .domain_list = &xelpd_pwdoms_ddi_io_tc4,
- .ops = &icl_ddi_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4,
- }
- }, {
- .name = "AUX_A",
- .domain_list = &icl_pwdoms_aux_a,
- .ops = &icl_aux_power_well_ops,
- .fixed_enable_delay = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_A,
- },
- }, {
- .name = "AUX_B",
- .domain_list = &icl_pwdoms_aux_b,
- .ops = &icl_aux_power_well_ops,
- .fixed_enable_delay = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_B,
- },
- }, {
- .name = "AUX_C",
- .domain_list = &tgl_pwdoms_aux_c,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &icl_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
+ I915_PW("DDI_IO_D_XELPD", &xelpd_pwdoms_ddi_io_d_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D),
+ I915_PW("DDI_IO_E_XELPD", &xelpd_pwdoms_ddi_io_e_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E),
+ I915_PW("DDI_IO_TC1", &xelpd_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
+ I915_PW("DDI_IO_TC2", &xelpd_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
+ I915_PW("DDI_IO_TC3", &xelpd_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
+ I915_PW("DDI_IO_TC4", &xelpd_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4),
+ ),
+ .ops = &icl_ddi_power_well_ops,
+ }, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
+ I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
+ I915_PW("AUX_C", &tgl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
+ I915_PW("AUX_D_XELPD", &xelpd_pwdoms_aux_d_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D),
+ I915_PW("AUX_E_XELPD", &xelpd_pwdoms_aux_e_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E),
+ I915_PW("AUX_USBC1", &xelpd_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
+ I915_PW("AUX_USBC2", &xelpd_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
+ I915_PW("AUX_USBC3", &xelpd_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
+ I915_PW("AUX_USBC4", &xelpd_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
+ ),
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = ICL_PW_CTL_IDX_AUX_C,
- },
- }, {
- .name = "AUX_D_XELPD",
- .domain_list = &xelpd_pwdoms_aux_d_xelpd,
- .ops = &icl_aux_power_well_ops,
- .fixed_enable_delay = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_AUX_D,
- },
- }, {
- .name = "AUX_E_XELPD",
- .domain_list = &xelpd_pwdoms_aux_e_xelpd,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = XELPD_PW_CTL_IDX_AUX_E,
- },
- }, {
- .name = "AUX_USBC1",
- .domain_list = &xelpd_pwdoms_aux_usbc1,
- .ops = &icl_aux_power_well_ops,
- .fixed_enable_delay = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1,
- },
- }, {
- .name = "AUX_USBC2",
- .domain_list = &xelpd_pwdoms_aux_usbc2,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2,
- },
- }, {
- .name = "AUX_USBC3",
- .domain_list = &xelpd_pwdoms_aux_usbc3,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3,
- },
- }, {
- .name = "AUX_USBC4",
- .domain_list = &xelpd_pwdoms_aux_usbc4,
- .ops = &icl_aux_power_well_ops,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4,
- },
- }, {
- .name = "AUX_TBT1",
- .domain_list = &xelpd_pwdoms_aux_tbt1,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1,
- },
- }, {
- .name = "AUX_TBT2",
- .domain_list = &xelpd_pwdoms_aux_tbt2,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2,
- },
- }, {
- .name = "AUX_TBT3",
- .domain_list = &xelpd_pwdoms_aux_tbt3,
- .ops = &icl_aux_power_well_ops,
- .is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3,
- },
}, {
- .name = "AUX_TBT4",
- .domain_list = &xelpd_pwdoms_aux_tbt4,
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("AUX_TBT1", &xelpd_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
+ I915_PW("AUX_TBT2", &xelpd_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
+ I915_PW("AUX_TBT3", &xelpd_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
+ I915_PW("AUX_TBT4", &xelpd_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
+ ),
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
- .id = DISP_PW_ID_NONE,
- {
- .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4,
- },
},
};
-static void init_power_well_domains(const struct i915_power_well_desc *desc,
+static void init_power_well_domains(const struct i915_power_well_instance *inst,
struct i915_power_well *power_well)
{
int j;
- if (!desc->domain_list)
+ if (!inst->domain_list)
return;
- if (desc->domain_list->count == 0) {
+ if (inst->domain_list->count == 0) {
bitmap_fill(power_well->domains.bits, POWER_DOMAIN_NUM);
return;
}
- for (j = 0; j < desc->domain_list->count; j++)
- set_bit(desc->domain_list->list[j], power_well->domains.bits);
+ for (j = 0; j < inst->domain_list->count; j++)
+ set_bit(inst->domain_list->list[j], power_well->domains.bits);
}
+#define for_each_power_well_instance(_desc_list, _desc_count, _desc, _inst) \
+ for ((_desc) = (_desc_list); (_desc) - (_desc_list) < (_desc_count); (_desc)++) \
+ for ((_inst) = (_desc)->instances->list; \
+ (_inst) - (_desc)->instances->list < (_desc)->instances->count; \
+ (_inst)++)
+
static int
__set_power_wells(struct i915_power_domains *power_domains,
const struct i915_power_well_desc *power_well_descs,
@@ -2102,11 +1454,13 @@ __set_power_wells(struct i915_power_domains *power_domains,
struct drm_i915_private,
power_domains);
u64 power_well_ids = 0;
+ const struct i915_power_well_desc *desc;
+ const struct i915_power_well_instance *inst;
int power_well_count = 0;
- int i, plt_idx = 0;
+ int plt_idx = 0;
- for (i = 0; i < power_well_descs_sz; i++)
- if (!(BIT_ULL(power_well_descs[i].id) & skip_mask))
+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc, inst)
+ if (!(BIT_ULL(inst->id) & skip_mask))
power_well_count++;
power_domains->power_well_count = power_well_count;
@@ -2117,16 +1471,19 @@ __set_power_wells(struct i915_power_domains *power_domains,
if (!power_domains->power_wells)
return -ENOMEM;
- for (i = 0; i < power_well_descs_sz; i++) {
- enum i915_power_well_id id = power_well_descs[i].id;
+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc, inst) {
+ struct i915_power_well *pw = &power_domains->power_wells[plt_idx];
+ enum i915_power_well_id id = inst->id;
if (BIT_ULL(id) & skip_mask)
continue;
- power_domains->power_wells[plt_idx].desc =
- &power_well_descs[i];
+ pw->desc = desc;
+ drm_WARN_ON(&i915->drm,
+ overflows_type(inst - desc->instances->list, pw->instance_idx));
+ pw->instance_idx = inst - desc->instances->list;
- init_power_well_domains(&power_well_descs[i], &power_domains->power_wells[plt_idx]);
+ init_power_well_domains(inst, pw);
plt_idx++;
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.c b/drivers/gpu/drm/i915/display/intel_display_power_well.c
index 5d8145bcb90eb..f562432dbadf9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.c
@@ -57,6 +57,12 @@ struct i915_power_well_ops {
struct i915_power_well *power_well);
};
+static const struct i915_power_well_instance *
+i915_power_well_instance(const struct i915_power_well *power_well)
+{
+ return &power_well->desc->instances->list[power_well->instance_idx];
+}
+
struct i915_power_well *
lookup_power_well(struct drm_i915_private *i915,
enum i915_power_well_id power_well_id)
@@ -64,7 +70,7 @@ lookup_power_well(struct drm_i915_private *i915,
struct i915_power_well *power_well;
for_each_power_well(i915, power_well)
- if (power_well->desc->id == power_well_id)
+ if (i915_power_well_instance(power_well)->id == power_well_id)
return power_well;
/*
@@ -83,7 +89,7 @@ lookup_power_well(struct drm_i915_private *i915,
void intel_power_well_enable(struct drm_i915_private *i915,
struct i915_power_well *power_well)
{
- drm_dbg_kms(&i915->drm, "enabling %s\n", power_well->desc->name);
+ drm_dbg_kms(&i915->drm, "enabling %s\n", intel_power_well_name(power_well));
power_well->desc->ops->enable(i915, power_well);
power_well->hw_enabled = true;
}
@@ -91,7 +97,7 @@ void intel_power_well_enable(struct drm_i915_private *i915,
void intel_power_well_disable(struct drm_i915_private *i915,
struct i915_power_well *power_well)
{
- drm_dbg_kms(&i915->drm, "disabling %s\n", power_well->desc->name);
+ drm_dbg_kms(&i915->drm, "disabling %s\n", intel_power_well_name(power_well));
power_well->hw_enabled = false;
power_well->desc->ops->disable(i915, power_well);
}
@@ -116,7 +122,7 @@ void intel_power_well_put(struct drm_i915_private *i915,
{
drm_WARN(&i915->drm, !power_well->count,
"Use count on power well %s is already zero",
- power_well->desc->name);
+ i915_power_well_instance(power_well)->name);
if (!--power_well->count)
intel_power_well_disable(i915, power_well);
@@ -150,7 +156,7 @@ bool intel_power_well_is_always_on(struct i915_power_well *power_well)
const char *intel_power_well_name(struct i915_power_well *power_well)
{
- return power_well->desc->name;
+ return i915_power_well_instance(power_well)->name;
}
struct intel_power_domain_mask *intel_power_well_domains(struct i915_power_well *power_well)
@@ -194,7 +200,7 @@ static void hsw_power_well_pre_disable(struct drm_i915_private *dev_priv,
static enum aux_ch icl_aux_pw_to_ch(const struct i915_power_well *power_well)
{
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
return power_well->desc->is_tc_tbt ? ICL_TBT_AUX_PW_TO_CH(pw_idx) :
ICL_AUX_PW_TO_CH(pw_idx);
@@ -241,7 +247,7 @@ static void hsw_wait_for_power_well_enable(struct drm_i915_private *dev_priv,
bool timeout_expected)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
/*
* For some power wells we're not supposed to watch the status bit for
@@ -284,7 +290,7 @@ static void hsw_wait_for_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
bool disabled;
u32 reqs;
@@ -322,7 +328,7 @@ static void hsw_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
u32 val;
if (power_well->desc->has_fuses) {
@@ -369,7 +375,7 @@ static void hsw_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
u32 val;
hsw_power_well_pre_disable(dev_priv,
@@ -386,7 +392,7 @@ icl_combo_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
u32 val;
@@ -418,7 +424,7 @@ icl_combo_phy_aux_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
enum phy phy = icl_aux_pw_to_phy(dev_priv, power_well);
u32 val;
@@ -504,7 +510,7 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
val = intel_de_read(dev_priv, regs->driver);
intel_de_write(dev_priv, regs->driver,
- val | HSW_PWR_WELL_CTL_REQ(power_well->desc->hsw.idx));
+ val | HSW_PWR_WELL_CTL_REQ(i915_power_well_instance(power_well)->hsw.idx));
/*
* An AUX timeout is expected if the TBT DP tunnel is down,
@@ -520,7 +526,7 @@ icl_tc_phy_aux_power_well_enable(struct drm_i915_private *dev_priv,
if (DISPLAY_VER(dev_priv) >= 12 && !is_tbt) {
enum tc_port tc_port;
- tc_port = TGL_AUX_PW_TO_TC_PORT(power_well->desc->hsw.idx);
+ tc_port = TGL_AUX_PW_TO_TC_PORT(i915_power_well_instance(power_well)->hsw.idx);
intel_de_write(dev_priv, HIP_INDEX_REG(tc_port),
HIP_INDEX_VAL(tc_port, 0x2));
@@ -582,8 +588,8 @@ static bool hsw_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- enum i915_power_well_id id = power_well->desc->id;
- int pw_idx = power_well->desc->hsw.idx;
+ enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx) |
HSW_PWR_WELL_CTL_STATE(pw_idx);
u32 val;
@@ -899,7 +905,7 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
const struct i915_power_well_regs *regs = power_well->desc->ops->regs;
- int pw_idx = power_well->desc->hsw.idx;
+ int pw_idx = i915_power_well_instance(power_well)->hsw.idx;
u32 mask = HSW_PWR_WELL_CTL_REQ(pw_idx);
u32 bios_req = intel_de_read(dev_priv, regs->bios);
@@ -916,19 +922,19 @@ static void hsw_power_well_sync_hw(struct drm_i915_private *dev_priv,
static void bxt_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- bxt_ddi_phy_init(dev_priv, power_well->desc->bxt.phy);
+ bxt_ddi_phy_init(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
}
static void bxt_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- bxt_ddi_phy_uninit(dev_priv, power_well->desc->bxt.phy);
+ bxt_ddi_phy_uninit(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
}
static bool bxt_dpio_cmn_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- return bxt_ddi_phy_is_enabled(dev_priv, power_well->desc->bxt.phy);
+ return bxt_ddi_phy_is_enabled(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
}
static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
@@ -937,18 +943,18 @@ static void bxt_verify_ddi_phy_power_wells(struct drm_i915_private *dev_priv)
power_well = lookup_power_well(dev_priv, BXT_DISP_PW_DPIO_CMN_A);
if (intel_power_well_refcount(power_well) > 0)
- bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
+ bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
power_well = lookup_power_well(dev_priv, VLV_DISP_PW_DPIO_CMN_BC);
if (intel_power_well_refcount(power_well) > 0)
- bxt_ddi_phy_verify_state(dev_priv, power_well->desc->bxt.phy);
+ bxt_ddi_phy_verify_state(dev_priv, i915_power_well_instance(power_well)->bxt.phy);
if (IS_GEMINILAKE(dev_priv)) {
power_well = lookup_power_well(dev_priv,
GLK_DISP_PW_DPIO_CMN_C);
if (intel_power_well_refcount(power_well) > 0)
bxt_ddi_phy_verify_state(dev_priv,
- power_well->desc->bxt.phy);
+ i915_power_well_instance(power_well)->bxt.phy);
}
}
@@ -1081,7 +1087,7 @@ static void i830_pipes_power_well_sync_hw(struct drm_i915_private *dev_priv,
static void vlv_set_power_well(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well, bool enable)
{
- int pw_idx = power_well->desc->vlv.idx;
+ int pw_idx = i915_power_well_instance(power_well)->vlv.idx;
u32 mask;
u32 state;
u32 ctrl;
@@ -1130,7 +1136,7 @@ static void vlv_power_well_disable(struct drm_i915_private *dev_priv,
static bool vlv_power_well_enabled(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
- int pw_idx = power_well->desc->vlv.idx;
+ int pw_idx = i915_power_well_instance(power_well)->vlv.idx;
bool enabled = false;
u32 mask;
u32 state;
@@ -1424,15 +1430,16 @@ static void assert_chv_phy_status(struct drm_i915_private *dev_priv)
static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
+ enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
enum dpio_phy phy;
enum pipe pipe;
u32 tmp;
drm_WARN_ON_ONCE(&dev_priv->drm,
- power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
- power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
+ id != VLV_DISP_PW_DPIO_CMN_BC &&
+ id != CHV_DISP_PW_DPIO_CMN_D);
- if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
+ if (id == VLV_DISP_PW_DPIO_CMN_BC) {
pipe = PIPE_A;
phy = DPIO_PHY0;
} else {
@@ -1458,7 +1465,7 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
DPIO_SUS_CLK_CONFIG_GATE_CLKREQ;
vlv_dpio_write(dev_priv, pipe, CHV_CMN_DW28, tmp);
- if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
+ if (id == VLV_DISP_PW_DPIO_CMN_BC) {
tmp = vlv_dpio_read(dev_priv, pipe, _CHV_CMN_DW6_CH1);
tmp |= DPIO_DYNPWRDOWNEN_CH1;
vlv_dpio_write(dev_priv, pipe, _CHV_CMN_DW6_CH1, tmp);
@@ -1489,13 +1496,14 @@ static void chv_dpio_cmn_power_well_enable(struct drm_i915_private *dev_priv,
static void chv_dpio_cmn_power_well_disable(struct drm_i915_private *dev_priv,
struct i915_power_well *power_well)
{
+ enum i915_power_well_id id = i915_power_well_instance(power_well)->id;
enum dpio_phy phy;
drm_WARN_ON_ONCE(&dev_priv->drm,
- power_well->desc->id != VLV_DISP_PW_DPIO_CMN_BC &&
- power_well->desc->id != CHV_DISP_PW_DPIO_CMN_D);
+ id != VLV_DISP_PW_DPIO_CMN_BC &&
+ id != CHV_DISP_PW_DPIO_CMN_D);
- if (power_well->desc->id == VLV_DISP_PW_DPIO_CMN_BC) {
+ if (id == VLV_DISP_PW_DPIO_CMN_BC) {
phy = DPIO_PHY0;
assert_pll_disabled(dev_priv, PIPE_A);
assert_pll_disabled(dev_priv, PIPE_B);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_well.h b/drivers/gpu/drm/i915/display/intel_display_power_well.h
index bd60fb4166e74..d0624642dcb62 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_well.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power_well.h
@@ -33,7 +33,7 @@ struct i915_power_well;
* wells must be assigned DISP_PW_ID_NONE.
*/
enum i915_power_well_id {
- DISP_PW_ID_NONE,
+ DISP_PW_ID_NONE = 0, /* must be kept zero */
VLV_DISP_PW_DISP2D,
BXT_DISP_PW_DPIO_CMN_A,
@@ -49,29 +49,12 @@ enum i915_power_well_id {
TGL_DISP_PW_TC_COLD_OFF,
};
-struct i915_power_well_desc {
+struct i915_power_well_instance {
const char *name;
const struct i915_power_domain_list {
const enum intel_display_power_domain *list;
u8 count;
} *domain_list;
- /* Mask of pipes whose IRQ logic is backed by the pw */
- u16 irq_pipe_mask:4;
- u16 always_on:1;
- /*
- * Instead of waiting for the status bit to ack enables,
- * just wait a specific amount of time and then consider
- * the well enabled.
- */
- u16 fixed_enable_delay:1;
- /* The pw is backing the VGA functionality */
- u16 has_vga:1;
- u16 has_fuses:1;
- /*
- * The pw is for an ICL+ TypeC PHY port in
- * Thunderbolt mode.
- */
- u16 is_tc_tbt:1;
/* unique identifier for this power well */
enum i915_power_well_id id;
@@ -98,7 +81,32 @@ struct i915_power_well_desc {
u8 idx;
} hsw;
};
+};
+
+struct i915_power_well_desc {
const struct i915_power_well_ops *ops;
+ const struct i915_power_well_instance_list {
+ const struct i915_power_well_instance *list;
+ u8 count;
+ } *instances;
+
+ /* Mask of pipes whose IRQ logic is backed by the pw */
+ u16 irq_pipe_mask:4;
+ u16 always_on:1;
+ /*
+ * Instead of waiting for the status bit to ack enables,
+ * just wait a specific amount of time and then consider
+ * the well enabled.
+ */
+ u16 fixed_enable_delay:1;
+ /* The pw is backing the VGA functionality */
+ u16 has_vga:1;
+ u16 has_fuses:1;
+ /*
+ * The pw is for an ICL+ TypeC PHY port in
+ * Thunderbolt mode.
+ */
+ u16 is_tc_tbt:1;
};
struct i915_power_well {
@@ -108,6 +116,8 @@ struct i915_power_well {
int count;
/* cached hw enabled state */
bool hw_enabled;
+ /* index into desc->instances->list */
+ u8 instance_idx;
};
struct i915_power_well *lookup_power_well(struct drm_i915_private *i915,
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 11/18] drm/i915: Allow platforms to share power well descriptors
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (9 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 10/18] drm/i915: Simplify power well definitions by adding power well instances Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 12/18] drm/i915: Simplify the DG1 " Imre Deak
` (14 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
Some power wells - like always-on and skl+/icl+ PW_1 - with the same
name, domain list, flags, ops are used by multiple platforms, so allow
platforms to reuse the descriptors of such power wells.
This change also lets the follow up patches to simplify the DG1/RKL
power well definitions, and remove the ADL-S skip_mask special casing.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
.../i915/display/intel_display_power_map.c | 281 ++++++++----------
1 file changed, 122 insertions(+), 159 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index c282e05bfc1ac..7babe3f1a3624 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -38,9 +38,17 @@
{ .name = _name, .domain_list = _domain_list, ## __VA_ARGS__ }
+struct i915_power_well_desc_list {
+ const struct i915_power_well_desc *list;
+ u8 count;
+};
+
+#define I915_PW_DESCRIPTORS(x) __LIST(x)
+
+
I915_DECL_PW_DOMAINS(i9xx_pwdoms_always_on, I915_PW_DOMAINS_ALL);
-static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
+static const struct i915_power_well_desc i9xx_power_wells_always_on[] = {
{
.instances = &I915_PW_INSTANCES(
I915_PW("always-on", &i9xx_pwdoms_always_on),
@@ -50,6 +58,10 @@ static const struct i915_power_well_desc i9xx_always_on_power_well[] = {
},
};
+static const struct i915_power_well_desc_list i9xx_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+};
+
I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
POWER_DOMAIN_PIPE_A,
POWER_DOMAIN_PIPE_B,
@@ -59,14 +71,8 @@ I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
POWER_DOMAIN_TRANSCODER_B,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc i830_power_wells[] = {
+static const struct i915_power_well_desc i830_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("pipes", &i830_pwdoms_pipes),
),
@@ -74,6 +80,11 @@ static const struct i915_power_well_desc i830_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list i830_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(i830_power_wells_main),
+};
+
I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
@@ -92,14 +103,8 @@ I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
POWER_DOMAIN_AUDIO_PLAYBACK,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc hsw_power_wells[] = {
+static const struct i915_power_well_desc hsw_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("display", &hsw_pwdoms_display,
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
@@ -110,6 +115,11 @@ static const struct i915_power_well_desc hsw_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list hsw_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(hsw_power_wells_main),
+};
+
I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
POWER_DOMAIN_PIPE_B,
POWER_DOMAIN_PIPE_C,
@@ -127,14 +137,8 @@ I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
POWER_DOMAIN_AUDIO_PLAYBACK,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc bdw_power_wells[] = {
+static const struct i915_power_well_desc bdw_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("display", &bdw_pwdoms_display,
.hsw.idx = HSW_PW_CTL_IDX_GLOBAL,
@@ -146,6 +150,11 @@ static const struct i915_power_well_desc bdw_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list bdw_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(bdw_power_wells_main),
+};
+
I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
POWER_DOMAIN_DISPLAY_CORE,
POWER_DOMAIN_PIPE_A,
@@ -181,14 +190,8 @@ I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc vlv_power_wells[] = {
+static const struct i915_power_well_desc vlv_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("display", &vlv_pwdoms_display,
.vlv.idx = PUNIT_PWGT_IDX_DISP2D,
@@ -217,6 +220,11 @@ static const struct i915_power_well_desc vlv_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list vlv_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(vlv_power_wells_main),
+};
+
I915_DECL_PW_DOMAINS(chv_pwdoms_display,
POWER_DOMAIN_DISPLAY_CORE,
POWER_DOMAIN_PIPE_A,
@@ -253,14 +261,8 @@ I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
POWER_DOMAIN_AUX_D,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc chv_power_wells[] = {
+static const struct i915_power_well_desc chv_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
/*
* Pipe A power well is the new disp2d well. Pipe B and C
* power wells don't actually exist. Pipe A power well is
@@ -283,6 +285,11 @@ static const struct i915_power_well_desc chv_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list chv_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(chv_power_wells_main),
+};
+
#define SKL_PW_2_POWER_DOMAINS \
POWER_DOMAIN_PIPE_B, \
POWER_DOMAIN_PIPE_C, \
@@ -330,14 +337,8 @@ I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
POWER_DOMAIN_PORT_DDI_IO_D,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc skl_power_wells[] = {
+static const struct i915_power_well_desc skl_power_wells_pw_1[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
/* Handled by the DMC firmware */
.instances = &I915_PW_INSTANCES(
I915_PW("PW_1", I915_PW_DOMAINS_NONE,
@@ -347,7 +348,11 @@ static const struct i915_power_well_desc skl_power_wells[] = {
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- }, {
+ },
+};
+
+static const struct i915_power_well_desc skl_power_wells_main[] = {
+ {
/* Handled by the DMC firmware */
.instances = &I915_PW_INSTANCES(
I915_PW("MISC_IO", I915_PW_DOMAINS_NONE,
@@ -383,6 +388,12 @@ static const struct i915_power_well_desc skl_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list skl_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(skl_power_wells_main),
+};
+
#define BXT_PW_2_POWER_DOMAINS \
POWER_DOMAIN_PIPE_B, \
POWER_DOMAIN_PIPE_C, \
@@ -423,24 +434,8 @@ I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc bxt_power_wells[] = {
+static const struct i915_power_well_desc bxt_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &bxt_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -469,6 +464,12 @@ static const struct i915_power_well_desc bxt_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list bxt_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(bxt_power_wells_main),
+};
+
#define GLK_PW_2_POWER_DOMAINS \
POWER_DOMAIN_PIPE_B, \
POWER_DOMAIN_PIPE_C, \
@@ -529,24 +530,8 @@ I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
POWER_DOMAIN_AUX_C,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc glk_power_wells[] = {
+static const struct i915_power_well_desc glk_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = SKL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &glk_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -588,6 +573,12 @@ static const struct i915_power_well_desc glk_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list glk_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(skl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(glk_power_wells_main),
+};
+
/*
* ICL PW_0/PG_0 domains (HW/DMC control):
* - PCI
@@ -682,14 +673,8 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT_D);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT_E);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT_F);
-static const struct i915_power_well_desc icl_power_wells[] = {
+static const struct i915_power_well_desc icl_power_wells_pw_1[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
/* Handled by the DMC firmware */
.instances = &I915_PW_INSTANCES(
I915_PW("PW_1", I915_PW_DOMAINS_NONE,
@@ -699,7 +684,11 @@ static const struct i915_power_well_desc icl_power_wells[] = {
.ops = &hsw_power_well_ops,
.always_on = true,
.has_fuses = true,
- }, {
+ },
+};
+
+static const struct i915_power_well_desc icl_power_wells_main[] = {
+ {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &icl_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -763,6 +752,12 @@ static const struct i915_power_well_desc icl_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list icl_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(icl_power_wells_main),
+};
+
#define TGL_PW_5_POWER_DOMAINS \
POWER_DOMAIN_PIPE_D, \
POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
@@ -868,24 +863,8 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
POWER_DOMAIN_AUX_TBT6,
POWER_DOMAIN_TC_COLD_OFF);
-static const struct i915_power_well_desc tgl_power_wells[] = {
+static const struct i915_power_well_desc tgl_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &tgl_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -971,6 +950,12 @@ static const struct i915_power_well_desc tgl_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list tgl_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(tgl_power_wells_main),
+};
+
#define RKL_PW_4_POWER_DOMAINS \
POWER_DOMAIN_PIPE_C, \
POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
@@ -1025,24 +1010,8 @@ I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc rkl_power_wells[] = {
+static const struct i915_power_well_desc rkl_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &rkl_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -1085,6 +1054,12 @@ static const struct i915_power_well_desc rkl_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list rkl_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(rkl_power_wells_main),
+};
+
/*
* DG1 onwards Audio MMIO/VERBS lies in PG0 power well.
*/
@@ -1117,24 +1092,8 @@ I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
POWER_DOMAIN_TRANSCODER_VDSC_PW2,
POWER_DOMAIN_INIT);
-static const struct i915_power_well_desc dg1_power_wells[] = {
+static const struct i915_power_well_desc dg1_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &dg1_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -1193,6 +1152,12 @@ static const struct i915_power_well_desc dg1_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list dg1_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(dg1_power_wells_main),
+};
+
/*
* XE_LPD Power Domains
*
@@ -1318,24 +1283,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
-static const struct i915_power_well_desc xelpd_power_wells[] = {
+static const struct i915_power_well_desc xelpd_power_wells_main[] = {
{
- .instances = &I915_PW_INSTANCES(
- I915_PW("always-on", &i9xx_pwdoms_always_on),
- ),
- .ops = &i9xx_always_on_power_well_ops,
- .always_on = true,
- }, {
- /* Handled by the DMC firmware */
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_1", I915_PW_DOMAINS_NONE,
- .hsw.idx = ICL_PW_CTL_IDX_PW_1,
- .id = SKL_DISP_PW_1),
- ),
- .ops = &hsw_power_well_ops,
- .always_on = true,
- .has_fuses = true,
- }, {
.instances = &I915_PW_INSTANCES(
I915_PW("DC_off", &xelpd_pwdoms_dc_off,
.id = SKL_DISP_DC_OFF),
@@ -1421,6 +1370,12 @@ static const struct i915_power_well_desc xelpd_power_wells[] = {
},
};
+static const struct i915_power_well_desc_list xelpd_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(xelpd_power_wells_main),
+};
+
static void init_power_well_domains(const struct i915_power_well_instance *inst,
struct i915_power_well *power_well)
{
@@ -1439,27 +1394,35 @@ static void init_power_well_domains(const struct i915_power_well_instance *inst,
set_bit(inst->domain_list->list[j], power_well->domains.bits);
}
-#define for_each_power_well_instance(_desc_list, _desc_count, _desc, _inst) \
+#define for_each_power_well_instance_in_desc_list(_desc_list, _desc_count, _desc, _inst) \
for ((_desc) = (_desc_list); (_desc) - (_desc_list) < (_desc_count); (_desc)++) \
for ((_inst) = (_desc)->instances->list; \
(_inst) - (_desc)->instances->list < (_desc)->instances->count; \
(_inst)++)
+#define for_each_power_well_instance(_desc_list, _desc_count, _descs, _desc, _inst) \
+ for ((_descs) = (_desc_list); \
+ (_descs) - (_desc_list) < (_desc_count); \
+ (_descs)++) \
+ for_each_power_well_instance_in_desc_list((_descs)->list, (_descs)->count, \
+ (_desc), (_inst))
+
static int
__set_power_wells(struct i915_power_domains *power_domains,
- const struct i915_power_well_desc *power_well_descs,
+ const struct i915_power_well_desc_list *power_well_descs,
int power_well_descs_sz, u64 skip_mask)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
power_domains);
u64 power_well_ids = 0;
+ const struct i915_power_well_desc_list *desc_list;
const struct i915_power_well_desc *desc;
const struct i915_power_well_instance *inst;
int power_well_count = 0;
int plt_idx = 0;
- for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc, inst)
+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst)
if (!(BIT_ULL(inst->id) & skip_mask))
power_well_count++;
@@ -1471,7 +1434,7 @@ __set_power_wells(struct i915_power_domains *power_domains,
if (!power_domains->power_wells)
return -ENOMEM;
- for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc, inst) {
+ for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst) {
struct i915_power_well *pw = &power_domains->power_wells[plt_idx];
enum i915_power_well_id id = inst->id;
@@ -1557,7 +1520,7 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
else if (IS_I830(i915))
return set_power_wells(power_domains, i830_power_wells);
else
- return set_power_wells(power_domains, i9xx_always_on_power_well);
+ return set_power_wells(power_domains, i9xx_power_wells);
}
/**
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 12/18] drm/i915: Simplify the DG1 power well descriptors
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (10 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 11/18] drm/i915: Allow platforms to share power well descriptors Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 13/18] drm/i915: Sanitize the ADL-S power well definition Imre Deak
` (13 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
Simplify the definition of DG1 power wells by reusing the identical
RKL DDI/AUX descriptors.
This reorders the DG1 DDI/AUX vs. PW4/5 power wells, but this shouldn't
make a difference (it is the order on RKL and the DDI/AUX power wells
don't have a dependency on PW4/5).
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
.../i915/display/intel_display_power_map.c | 24 ++++++-------------
1 file changed, 7 insertions(+), 17 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 7babe3f1a3624..4443cf0015d1e 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1035,7 +1035,11 @@ static const struct i915_power_well_desc rkl_power_wells_main[] = {
.ops = &hsw_power_well_ops,
.has_fuses = true,
.irq_pipe_mask = BIT(PIPE_C),
- }, {
+ },
+};
+
+static const struct i915_power_well_desc rkl_power_wells_ddi_aux[] = {
+ {
.instances = &I915_PW_INSTANCES(
I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
@@ -1058,6 +1062,7 @@ static const struct i915_power_well_desc_list rkl_power_wells[] = {
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
I915_PW_DESCRIPTORS(rkl_power_wells_main),
+ I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux),
};
/*
@@ -1117,22 +1122,6 @@ static const struct i915_power_well_desc dg1_power_wells_main[] = {
.irq_pipe_mask = BIT(PIPE_B),
.has_vga = true,
.has_fuses = true,
- }, {
- .instances = &I915_PW_INSTANCES(
- I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
- I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
- I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
- I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
- ),
- .ops = &icl_ddi_power_well_ops,
- }, {
- .instances = &I915_PW_INSTANCES(
- I915_PW("AUX_A", &tgl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
- I915_PW("AUX_B", &tgl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
- I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
- I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
- ),
- .ops = &icl_aux_power_well_ops,
}, {
.instances = &I915_PW_INSTANCES(
I915_PW("PW_4", &tgl_pwdoms_pw_4,
@@ -1156,6 +1145,7 @@ static const struct i915_power_well_desc_list dg1_power_wells[] = {
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
I915_PW_DESCRIPTORS(dg1_power_wells_main),
+ I915_PW_DESCRIPTORS(rkl_power_wells_ddi_aux),
};
/*
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 13/18] drm/i915: Sanitize the ADL-S power well definition
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (11 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 12/18] drm/i915: Simplify the DG1 " Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 14/18] drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform Imre Deak
` (12 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
Instead of the skip_mask special casing of the ADL-S power well
descriptors, add a power well descriptor list for ADL-S as well reusing
the TGL descriptors, w/o the TC-cold power well. ADL-S doesn't have
TypeC PHYs, so a better way would be having ADL-S specific AUX
descriptors, but I left changing this for a follow-up.
This changes the ordering of the AUX and TC-cold vs. PW_4/5 power wells
on TGL and ADL-S, but this shouldn't make a difference (PW_4/5 don't
depend on the AUX/TC-cold power wells).
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
.../i915/display/intel_display_power_map.c | 69 +++++++++++--------
1 file changed, 39 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 4443cf0015d1e..86d937f8bfe13 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -902,12 +902,36 @@ static const struct i915_power_well_desc tgl_power_wells_main[] = {
),
.ops = &icl_ddi_power_well_ops,
}, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_4", &tgl_pwdoms_pw_4,
+ .hsw.idx = ICL_PW_CTL_IDX_PW_4),
+ ),
+ .ops = &hsw_power_well_ops,
+ .has_fuses = true,
+ .irq_pipe_mask = BIT(PIPE_C),
+ }, {
+ .instances = &I915_PW_INSTANCES(
+ I915_PW("PW_5", &tgl_pwdoms_pw_5,
+ .hsw.idx = TGL_PW_CTL_IDX_PW_5),
+ ),
+ .ops = &hsw_power_well_ops,
+ .has_fuses = true,
+ .irq_pipe_mask = BIT(PIPE_D),
+ },
+};
+
+static const struct i915_power_well_desc tgl_power_wells_tc_cold_off[] = {
+ {
.instances = &I915_PW_INSTANCES(
I915_PW("TC_cold_off", &tgl_pwdoms_tc_cold_off,
.id = TGL_DISP_PW_TC_COLD_OFF),
),
.ops = &tgl_tc_cold_off_ops,
- }, {
+ },
+};
+
+static const struct i915_power_well_desc tgl_power_wells_aux[] = {
+ {
.instances = &I915_PW_INSTANCES(
I915_PW("AUX_A", &tgl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
I915_PW("AUX_B", &tgl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
@@ -931,22 +955,6 @@ static const struct i915_power_well_desc tgl_power_wells_main[] = {
),
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
- }, {
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_4", &tgl_pwdoms_pw_4,
- .hsw.idx = ICL_PW_CTL_IDX_PW_4),
- ),
- .ops = &hsw_power_well_ops,
- .has_fuses = true,
- .irq_pipe_mask = BIT(PIPE_C),
- }, {
- .instances = &I915_PW_INSTANCES(
- I915_PW("PW_5", &tgl_pwdoms_pw_5,
- .hsw.idx = TGL_PW_CTL_IDX_PW_5),
- ),
- .ops = &hsw_power_well_ops,
- .has_fuses = true,
- .irq_pipe_mask = BIT(PIPE_D),
},
};
@@ -954,6 +962,15 @@ static const struct i915_power_well_desc_list tgl_power_wells[] = {
I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
I915_PW_DESCRIPTORS(tgl_power_wells_main),
+ I915_PW_DESCRIPTORS(tgl_power_wells_tc_cold_off),
+ I915_PW_DESCRIPTORS(tgl_power_wells_aux),
+};
+
+static const struct i915_power_well_desc_list adls_power_wells[] = {
+ I915_PW_DESCRIPTORS(i9xx_power_wells_always_on),
+ I915_PW_DESCRIPTORS(icl_power_wells_pw_1),
+ I915_PW_DESCRIPTORS(tgl_power_wells_main),
+ I915_PW_DESCRIPTORS(tgl_power_wells_aux),
};
#define RKL_PW_4_POWER_DOMAINS \
@@ -1400,7 +1417,7 @@ static void init_power_well_domains(const struct i915_power_well_instance *inst,
static int
__set_power_wells(struct i915_power_domains *power_domains,
const struct i915_power_well_desc_list *power_well_descs,
- int power_well_descs_sz, u64 skip_mask)
+ int power_well_descs_sz)
{
struct drm_i915_private *i915 = container_of(power_domains,
struct drm_i915_private,
@@ -1413,8 +1430,7 @@ __set_power_wells(struct i915_power_domains *power_domains,
int plt_idx = 0;
for_each_power_well_instance(power_well_descs, power_well_descs_sz, desc_list, desc, inst)
- if (!(BIT_ULL(inst->id) & skip_mask))
- power_well_count++;
+ power_well_count++;
power_domains->power_well_count = power_well_count;
power_domains->power_wells =
@@ -1428,9 +1444,6 @@ __set_power_wells(struct i915_power_domains *power_domains,
struct i915_power_well *pw = &power_domains->power_wells[plt_idx];
enum i915_power_well_id id = inst->id;
- if (BIT_ULL(id) & skip_mask)
- continue;
-
pw->desc = desc;
drm_WARN_ON(&i915->drm,
overflows_type(inst - desc->instances->list, pw->instance_idx));
@@ -1451,12 +1464,9 @@ __set_power_wells(struct i915_power_domains *power_domains,
return 0;
}
-#define set_power_wells_mask(power_domains, __power_well_descs, skip_mask) \
- __set_power_wells(power_domains, __power_well_descs, \
- ARRAY_SIZE(__power_well_descs), skip_mask)
-
#define set_power_wells(power_domains, __power_well_descs) \
- set_power_wells_mask(power_domains, __power_well_descs, 0)
+ __set_power_wells(power_domains, __power_well_descs, \
+ ARRAY_SIZE(__power_well_descs))
/**
* intel_display_power_map_init - initialize power domain -> power well mappings
@@ -1485,8 +1495,7 @@ int intel_display_power_map_init(struct i915_power_domains *power_domains)
else if (IS_DG1(i915))
return set_power_wells(power_domains, dg1_power_wells);
else if (IS_ALDERLAKE_S(i915))
- return set_power_wells_mask(power_domains, tgl_power_wells,
- BIT_ULL(TGL_DISP_PW_TC_COLD_OFF));
+ return set_power_wells(power_domains, adls_power_wells);
else if (IS_ROCKETLAKE(i915))
return set_power_wells(power_domains, rkl_power_wells);
else if (DISPLAY_VER(i915) == 12)
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 14/18] drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (12 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 13/18] drm/i915: Sanitize the ADL-S power well definition Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 15/18] drm/i915: Remove the aliasing of power domain enum values Imre Deak
` (11 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
Atm the port -> DDI and AUX power domain mapping is specified by relying
on the aliasing of the platform specific intel_display_power_domain enum
values. For instance D12+ platforms refer to the 'D' port and power
domain instances, which doesn't match the bspec terminology, on these
platforms the corresponding port is TC1. To make it clear what
port/domain the code refers to add a mapping between them which matches
the bspec terms on different display versions.
This also allows for removing the aliasing in enum values in a follow-up
patch.
v2: Add the functions to intel_display_power.c, use
intel_display_power_ prefix.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
drivers/gpu/drm/i915/display/g4x_dp.c | 3 +-
drivers/gpu/drm/i915/display/g4x_hdmi.c | 3 +-
drivers/gpu/drm/i915/display/intel_ddi.c | 6 +-
drivers/gpu/drm/i915/display/intel_display.c | 85 +-------
drivers/gpu/drm/i915/display/intel_display.h | 4 +-
.../drm/i915/display/intel_display_power.c | 206 ++++++++++++++++++
.../drm/i915/display/intel_display_power.h | 12 +
drivers/gpu/drm/i915/display/intel_tc.c | 5 +-
8 files changed, 235 insertions(+), 89 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/g4x_dp.c b/drivers/gpu/drm/i915/display/g4x_dp.c
index 8e1338678d91a..ec353dece49bc 100644
--- a/drivers/gpu/drm/i915/display/g4x_dp.c
+++ b/drivers/gpu/drm/i915/display/g4x_dp.c
@@ -13,6 +13,7 @@
#include "intel_connector.h"
#include "intel_crtc.h"
#include "intel_de.h"
+#include "intel_display_power.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dp_link_training.h"
@@ -1383,7 +1384,7 @@ bool g4x_dp_init(struct drm_i915_private *dev_priv,
dig_port->max_lanes = 4;
intel_encoder->type = INTEL_OUTPUT_DP;
- intel_encoder->power_domain = intel_port_to_power_domain(port);
+ intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
if (IS_CHERRYVIEW(dev_priv)) {
if (port == PORT_D)
intel_encoder->pipe_mask = BIT(PIPE_C);
diff --git a/drivers/gpu/drm/i915/display/g4x_hdmi.c b/drivers/gpu/drm/i915/display/g4x_hdmi.c
index 06e00b1eaa7ce..56fa6dfba020c 100644
--- a/drivers/gpu/drm/i915/display/g4x_hdmi.c
+++ b/drivers/gpu/drm/i915/display/g4x_hdmi.c
@@ -10,6 +10,7 @@
#include "intel_connector.h"
#include "intel_crtc.h"
#include "intel_de.h"
+#include "intel_display_power.h"
#include "intel_display_types.h"
#include "intel_dpio_phy.h"
#include "intel_fifo_underrun.h"
@@ -588,7 +589,7 @@ void g4x_hdmi_init(struct drm_i915_private *dev_priv,
intel_encoder->shutdown = intel_hdmi_encoder_shutdown;
intel_encoder->type = INTEL_OUTPUT_HDMI;
- intel_encoder->power_domain = intel_port_to_power_domain(port);
+ intel_encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
intel_encoder->port = port;
if (IS_CHERRYVIEW(dev_priv)) {
if (port == PORT_D)
diff --git a/drivers/gpu/drm/i915/display/intel_ddi.c b/drivers/gpu/drm/i915/display/intel_ddi.c
index afbb794d1f586..7ce3bdca5f8fe 100644
--- a/drivers/gpu/drm/i915/display/intel_ddi.c
+++ b/drivers/gpu/drm/i915/display/intel_ddi.c
@@ -40,6 +40,7 @@
#include "intel_ddi.h"
#include "intel_ddi_buf_trans.h"
#include "intel_de.h"
+#include "intel_display_power.h"
#include "intel_display_types.h"
#include "intel_dp.h"
#include "intel_dp_link_training.h"
@@ -4371,7 +4372,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
encoder->get_power_domains = intel_ddi_get_power_domains;
encoder->type = INTEL_OUTPUT_DDI;
- encoder->power_domain = intel_port_to_power_domain(port);
+ encoder->power_domain = intel_display_power_ddi_lanes_domain(dev_priv, port);
encoder->port = port;
encoder->cloneable = 0;
encoder->pipe_mask = ~0;
@@ -4499,8 +4500,7 @@ void intel_ddi_init(struct drm_i915_private *dev_priv, enum port port)
}
drm_WARN_ON(&dev_priv->drm, port > PORT_I);
- dig_port->ddi_io_power_domain = POWER_DOMAIN_PORT_DDI_IO_A +
- port - PORT_A;
+ dig_port->ddi_io_power_domain = intel_display_power_ddi_io_domain(dev_priv, port);
if (init_dp) {
if (!intel_ddi_init_dp_connector(dig_port))
diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index fa6580cdbc4b2..e0337cc88bb24 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -51,6 +51,7 @@
#include "display/intel_crt.h"
#include "display/intel_ddi.h"
#include "display/intel_display_debugfs.h"
+#include "display/intel_display_power.h"
#include "display/intel_dp.h"
#include "display/intel_dp_mst.h"
#include "display/intel_dpll.h"
@@ -2186,91 +2187,15 @@ enum tc_port intel_port_to_tc(struct drm_i915_private *dev_priv, enum port port)
return TC_PORT_1 + port - PORT_C;
}
-enum intel_display_power_domain intel_port_to_power_domain(enum port port)
-{
- switch (port) {
- case PORT_A:
- return POWER_DOMAIN_PORT_DDI_LANES_A;
- case PORT_B:
- return POWER_DOMAIN_PORT_DDI_LANES_B;
- case PORT_C:
- return POWER_DOMAIN_PORT_DDI_LANES_C;
- case PORT_D:
- return POWER_DOMAIN_PORT_DDI_LANES_D;
- case PORT_E:
- return POWER_DOMAIN_PORT_DDI_LANES_E;
- case PORT_F:
- return POWER_DOMAIN_PORT_DDI_LANES_F;
- case PORT_G:
- return POWER_DOMAIN_PORT_DDI_LANES_G;
- case PORT_H:
- return POWER_DOMAIN_PORT_DDI_LANES_H;
- case PORT_I:
- return POWER_DOMAIN_PORT_DDI_LANES_I;
- default:
- MISSING_CASE(port);
- return POWER_DOMAIN_PORT_OTHER;
- }
-}
-
enum intel_display_power_domain
intel_aux_power_domain(struct intel_digital_port *dig_port)
{
- if (intel_tc_port_in_tbt_alt_mode(dig_port)) {
- switch (dig_port->aux_ch) {
- case AUX_CH_C:
- return POWER_DOMAIN_AUX_TBT_C;
- case AUX_CH_D:
- return POWER_DOMAIN_AUX_TBT_D;
- case AUX_CH_E:
- return POWER_DOMAIN_AUX_TBT_E;
- case AUX_CH_F:
- return POWER_DOMAIN_AUX_TBT_F;
- case AUX_CH_G:
- return POWER_DOMAIN_AUX_TBT_G;
- case AUX_CH_H:
- return POWER_DOMAIN_AUX_TBT_H;
- case AUX_CH_I:
- return POWER_DOMAIN_AUX_TBT_I;
- default:
- MISSING_CASE(dig_port->aux_ch);
- return POWER_DOMAIN_AUX_TBT_C;
- }
- }
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
- return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
-}
+ if (intel_tc_port_in_tbt_alt_mode(dig_port))
+ return intel_display_power_tbt_aux_domain(i915, dig_port->aux_ch);
-/*
- * Converts aux_ch to power_domain without caring about TBT ports for that use
- * intel_aux_power_domain()
- */
-enum intel_display_power_domain
-intel_legacy_aux_to_power_domain(enum aux_ch aux_ch)
-{
- switch (aux_ch) {
- case AUX_CH_A:
- return POWER_DOMAIN_AUX_A;
- case AUX_CH_B:
- return POWER_DOMAIN_AUX_B;
- case AUX_CH_C:
- return POWER_DOMAIN_AUX_C;
- case AUX_CH_D:
- return POWER_DOMAIN_AUX_D;
- case AUX_CH_E:
- return POWER_DOMAIN_AUX_E;
- case AUX_CH_F:
- return POWER_DOMAIN_AUX_F;
- case AUX_CH_G:
- return POWER_DOMAIN_AUX_G;
- case AUX_CH_H:
- return POWER_DOMAIN_AUX_H;
- case AUX_CH_I:
- return POWER_DOMAIN_AUX_I;
- default:
- MISSING_CASE(aux_ch);
- return POWER_DOMAIN_AUX_A;
- }
+ return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
}
static void get_crtc_power_domains(struct intel_crtc_state *crtc_state,
diff --git a/drivers/gpu/drm/i915/display/intel_display.h b/drivers/gpu/drm/i915/display/intel_display.h
index 8513703086b70..510e7295c37e1 100644
--- a/drivers/gpu/drm/i915/display/intel_display.h
+++ b/drivers/gpu/drm/i915/display/intel_display.h
@@ -635,11 +635,9 @@ void intel_cpu_transcoder_get_m2_n2(struct intel_crtc *crtc,
void i9xx_crtc_clock_get(struct intel_crtc *crtc,
struct intel_crtc_state *pipe_config);
int intel_dotclock_calculate(int link_freq, const struct intel_link_m_n *m_n);
-enum intel_display_power_domain intel_port_to_power_domain(enum port port);
+enum intel_display_power_domain intel_port_to_power_domain(struct intel_digital_port *dig_port);
enum intel_display_power_domain
intel_aux_power_domain(struct intel_digital_port *dig_port);
-enum intel_display_power_domain
-intel_legacy_aux_to_power_domain(enum aux_ch aux_ch);
void intel_crtc_arm_fifo_underrun(struct intel_crtc *crtc,
struct intel_crtc_state *crtc_state);
void ilk_pfit_disable(const struct intel_crtc_state *old_crtc_state);
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 9dc1be8cc1582..5915d70eaf00b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -2256,3 +2256,209 @@ void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m
mutex_unlock(&power_domains->lock);
}
+
+struct intel_ddi_port_domains {
+ enum port port_start;
+ enum port port_end;
+ enum aux_ch aux_ch_start;
+ enum aux_ch aux_ch_end;
+
+ enum intel_display_power_domain ddi_lanes;
+ enum intel_display_power_domain ddi_io;
+ enum intel_display_power_domain aux_legacy_usbc;
+ enum intel_display_power_domain aux_tbt;
+};
+
+static const struct intel_ddi_port_domains
+i9xx_port_domains[] = {
+ {
+ .port_start = PORT_A,
+ .port_end = PORT_F,
+ .aux_ch_start = AUX_CH_A,
+ .aux_ch_end = AUX_CH_F,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
+ .aux_tbt = POWER_DOMAIN_INVALID,
+ },
+};
+
+static const struct intel_ddi_port_domains
+d11_port_domains[] = {
+ {
+ .port_start = PORT_A,
+ .port_end = PORT_B,
+ .aux_ch_start = AUX_CH_A,
+ .aux_ch_end = AUX_CH_B,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
+ .aux_tbt = POWER_DOMAIN_INVALID,
+ }, {
+ .port_start = PORT_C,
+ .port_end = PORT_F,
+ .aux_ch_start = AUX_CH_C,
+ .aux_ch_end = AUX_CH_F,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_C,
+ .aux_tbt = POWER_DOMAIN_AUX_TBT_C,
+ },
+};
+
+static const struct intel_ddi_port_domains
+d12_port_domains[] = {
+ {
+ .port_start = PORT_A,
+ .port_end = PORT_C,
+ .aux_ch_start = AUX_CH_A,
+ .aux_ch_end = AUX_CH_C,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
+ .aux_tbt = POWER_DOMAIN_INVALID,
+ }, {
+ .port_start = PORT_TC1,
+ .port_end = PORT_TC6,
+ .aux_ch_start = AUX_CH_USBC1,
+ .aux_ch_end = AUX_CH_USBC6,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
+ .aux_tbt = POWER_DOMAIN_AUX_TBT1,
+ },
+};
+
+static const struct intel_ddi_port_domains
+d13_port_domains[] = {
+ {
+ .port_start = PORT_A,
+ .port_end = PORT_C,
+ .aux_ch_start = AUX_CH_A,
+ .aux_ch_end = AUX_CH_C,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_A,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_A,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_A,
+ .aux_tbt = POWER_DOMAIN_INVALID,
+ }, {
+ .port_start = PORT_TC1,
+ .port_end = PORT_TC4,
+ .aux_ch_start = AUX_CH_USBC1,
+ .aux_ch_end = AUX_CH_USBC4,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_TC1,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_TC1,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_USBC1,
+ .aux_tbt = POWER_DOMAIN_AUX_TBT1,
+ }, {
+ .port_start = PORT_D_XELPD,
+ .port_end = PORT_E_XELPD,
+ .aux_ch_start = AUX_CH_D_XELPD,
+ .aux_ch_end = AUX_CH_E_XELPD,
+
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D_XELPD,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D_XELPD,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_D_XELPD,
+ .aux_tbt = POWER_DOMAIN_INVALID,
+ },
+};
+
+static void
+intel_port_domains_for_platform(struct drm_i915_private *i915,
+ const struct intel_ddi_port_domains **domains,
+ int *domains_size)
+{
+ if (DISPLAY_VER(i915) >= 13) {
+ *domains = d13_port_domains;
+ *domains_size = ARRAY_SIZE(d13_port_domains);
+ } else if (DISPLAY_VER(i915) >= 12) {
+ *domains = d12_port_domains;
+ *domains_size = ARRAY_SIZE(d12_port_domains);
+ } else if (DISPLAY_VER(i915) >= 11) {
+ *domains = d11_port_domains;
+ *domains_size = ARRAY_SIZE(d11_port_domains);
+ } else {
+ *domains = i9xx_port_domains;
+ *domains_size = ARRAY_SIZE(i9xx_port_domains);
+ }
+}
+
+static const struct intel_ddi_port_domains *
+intel_port_domains_for_port(struct drm_i915_private *i915, enum port port)
+{
+ const struct intel_ddi_port_domains *domains;
+ int domains_size;
+ int i;
+
+ intel_port_domains_for_platform(i915, &domains, &domains_size);
+ for (i = 0; i < domains_size; i++)
+ if (port >= domains[i].port_start && port <= domains[i].port_end)
+ return &domains[i];
+
+ return NULL;
+}
+
+enum intel_display_power_domain
+intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port)
+{
+ const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port);
+
+ if (drm_WARN_ON(&i915->drm, !domains) || domains->ddi_io == POWER_DOMAIN_INVALID)
+ return POWER_DOMAIN_PORT_DDI_IO_A;
+
+ return domains->ddi_io + port - domains->port_start;
+}
+
+enum intel_display_power_domain
+intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port)
+{
+ const struct intel_ddi_port_domains *domains = intel_port_domains_for_port(i915, port);
+
+ if (drm_WARN_ON(&i915->drm, !domains) || domains->ddi_lanes == POWER_DOMAIN_INVALID)
+ return POWER_DOMAIN_PORT_DDI_LANES_A;
+
+ return domains->ddi_lanes + port - domains->port_start;
+}
+
+static const struct intel_ddi_port_domains *
+intel_port_domains_for_aux_ch(struct drm_i915_private *i915, enum aux_ch aux_ch)
+{
+ const struct intel_ddi_port_domains *domains;
+ int domains_size;
+ int i;
+
+ intel_port_domains_for_platform(i915, &domains, &domains_size);
+ for (i = 0; i < domains_size; i++)
+ if (aux_ch >= domains[i].aux_ch_start && aux_ch <= domains[i].aux_ch_end)
+ return &domains[i];
+
+ return NULL;
+}
+
+enum intel_display_power_domain
+intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
+{
+ const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
+
+ if (drm_WARN_ON(&i915->drm, !domains) || domains->aux_legacy_usbc == POWER_DOMAIN_INVALID)
+ return POWER_DOMAIN_AUX_A;
+
+ return domains->aux_legacy_usbc + aux_ch - domains->aux_ch_start;
+}
+
+enum intel_display_power_domain
+intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch)
+{
+ const struct intel_ddi_port_domains *domains = intel_port_domains_for_aux_ch(i915, aux_ch);
+
+ if (drm_WARN_ON(&i915->drm, !domains) || domains->aux_tbt == POWER_DOMAIN_INVALID)
+ return POWER_DOMAIN_AUX_TBT1;
+
+ return domains->aux_tbt + aux_ch - domains->aux_ch_start;
+}
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 66fef12ef3db4..2ea30a4cfaa89 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -8,8 +8,10 @@
#include "intel_runtime_pm.h"
+enum aux_ch;
enum dpio_channel;
enum dpio_phy;
+enum port;
struct drm_i915_private;
struct i915_power_well;
struct intel_encoder;
@@ -130,6 +132,7 @@ enum intel_display_power_domain {
POWER_DOMAIN_INIT,
POWER_DOMAIN_NUM,
+ POWER_DOMAIN_INVALID = POWER_DOMAIN_NUM,
};
#define POWER_DOMAIN_PIPE(pipe) ((pipe) + POWER_DOMAIN_PIPE_A)
@@ -266,6 +269,15 @@ intel_display_power_put_all_in_set(struct drm_i915_private *i915,
void intel_display_power_debug(struct drm_i915_private *i915, struct seq_file *m);
+enum intel_display_power_domain
+intel_display_power_ddi_lanes_domain(struct drm_i915_private *i915, enum port port);
+enum intel_display_power_domain
+intel_display_power_ddi_io_domain(struct drm_i915_private *i915, enum port port);
+enum intel_display_power_domain
+intel_display_power_legacy_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
+enum intel_display_power_domain
+intel_display_power_tbt_aux_domain(struct drm_i915_private *i915, enum aux_ch aux_ch);
+
/*
* FIXME: We should probably switch this to a 0-based scheme to be consistent
* with how we now name/number DBUF_CTL instances.
diff --git a/drivers/gpu/drm/i915/display/intel_tc.c b/drivers/gpu/drm/i915/display/intel_tc.c
index fc037c027ea5a..b8b822ea37553 100644
--- a/drivers/gpu/drm/i915/display/intel_tc.c
+++ b/drivers/gpu/drm/i915/display/intel_tc.c
@@ -6,6 +6,7 @@
#include "i915_drv.h"
#include "i915_reg.h"
#include "intel_display.h"
+#include "intel_display_power_map.h"
#include "intel_display_types.h"
#include "intel_dp_mst.h"
#include "intel_tc.h"
@@ -61,10 +62,12 @@ bool intel_tc_cold_requires_aux_pw(struct intel_digital_port *dig_port)
static enum intel_display_power_domain
tc_cold_get_power_domain(struct intel_digital_port *dig_port, enum tc_port_mode mode)
{
+ struct drm_i915_private *i915 = to_i915(dig_port->base.base.dev);
+
if (mode == TC_PORT_TBT_ALT || !intel_tc_cold_requires_aux_pw(dig_port))
return POWER_DOMAIN_TC_COLD_OFF;
- return intel_legacy_aux_to_power_domain(dig_port->aux_ch);
+ return intel_display_power_legacy_aux_domain(i915, dig_port->aux_ch);
}
static intel_wakeref_t
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 15/18] drm/i915: Remove the aliasing of power domain enum values
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (13 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 14/18] drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 16/18] drm/i915: Remove the ICL specific TBT power domains Imre Deak
` (10 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
Aliasing the intel_display_power_domain enum values was required because
of the u64 power domain mask size limit. This makes the dmesg/debugfs
printouts of the domain names somewhat unclear, for instance domain
names for port D are shown on D12+ platforms where the corresponding
port is called TC1. Make this clearer by removing the aliasing which is
possible after a previous patch converting the mask to a bitmap.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
.../drm/i915/display/intel_display_power.c | 84 +++++++++++++------
.../drm/i915/display/intel_display_power.h | 26 ++----
2 files changed, 67 insertions(+), 43 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 5915d70eaf00b..7065b6265ea20 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -80,12 +80,22 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_LANES_E";
case POWER_DOMAIN_PORT_DDI_LANES_F:
return "PORT_DDI_LANES_F";
- case POWER_DOMAIN_PORT_DDI_LANES_G:
- return "PORT_DDI_LANES_G";
- case POWER_DOMAIN_PORT_DDI_LANES_H:
- return "PORT_DDI_LANES_H";
- case POWER_DOMAIN_PORT_DDI_LANES_I:
- return "PORT_DDI_LANES_I";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC1:
+ return "PORT_DDI_LANES_TC1";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC2:
+ return "PORT_DDI_LANES_TC2";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC3:
+ return "PORT_DDI_LANES_TC3";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC4:
+ return "PORT_DDI_LANES_TC4";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC5:
+ return "PORT_DDI_LANES_TC5";
+ case POWER_DOMAIN_PORT_DDI_LANES_TC6:
+ return "PORT_DDI_LANES_TC6";
+ case POWER_DOMAIN_PORT_DDI_LANES_D_XELPD:
+ return "PORT_DDI_LANES_D_XELPD";
+ case POWER_DOMAIN_PORT_DDI_LANES_E_XELPD:
+ return "PORT_DDI_LANES_E_XELPD";
case POWER_DOMAIN_PORT_DDI_IO_A:
return "PORT_DDI_IO_A";
case POWER_DOMAIN_PORT_DDI_IO_B:
@@ -98,12 +108,22 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_IO_E";
case POWER_DOMAIN_PORT_DDI_IO_F:
return "PORT_DDI_IO_F";
- case POWER_DOMAIN_PORT_DDI_IO_G:
- return "PORT_DDI_IO_G";
- case POWER_DOMAIN_PORT_DDI_IO_H:
- return "PORT_DDI_IO_H";
- case POWER_DOMAIN_PORT_DDI_IO_I:
- return "PORT_DDI_IO_I";
+ case POWER_DOMAIN_PORT_DDI_IO_TC1:
+ return "PORT_DDI_IO_TC1";
+ case POWER_DOMAIN_PORT_DDI_IO_TC2:
+ return "PORT_DDI_IO_TC2";
+ case POWER_DOMAIN_PORT_DDI_IO_TC3:
+ return "PORT_DDI_IO_TC3";
+ case POWER_DOMAIN_PORT_DDI_IO_TC4:
+ return "PORT_DDI_IO_TC4";
+ case POWER_DOMAIN_PORT_DDI_IO_TC5:
+ return "PORT_DDI_IO_TC5";
+ case POWER_DOMAIN_PORT_DDI_IO_TC6:
+ return "PORT_DDI_IO_TC6";
+ case POWER_DOMAIN_PORT_DDI_IO_D_XELPD:
+ return "PORT_DDI_IO_D_XELPD";
+ case POWER_DOMAIN_PORT_DDI_IO_E_XELPD:
+ return "PORT_DDI_IO_E_XELPD";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -128,12 +148,22 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_E";
case POWER_DOMAIN_AUX_F:
return "AUX_F";
- case POWER_DOMAIN_AUX_G:
- return "AUX_G";
- case POWER_DOMAIN_AUX_H:
- return "AUX_H";
- case POWER_DOMAIN_AUX_I:
- return "AUX_I";
+ case POWER_DOMAIN_AUX_USBC1:
+ return "AUX_USBC1";
+ case POWER_DOMAIN_AUX_USBC2:
+ return "AUX_USBC2";
+ case POWER_DOMAIN_AUX_USBC3:
+ return "AUX_USBC3";
+ case POWER_DOMAIN_AUX_USBC4:
+ return "AUX_USBC4";
+ case POWER_DOMAIN_AUX_USBC5:
+ return "AUX_USBC5";
+ case POWER_DOMAIN_AUX_USBC6:
+ return "AUX_USBC6";
+ case POWER_DOMAIN_AUX_D_XELPD:
+ return "AUX_D_XELPD";
+ case POWER_DOMAIN_AUX_E_XELPD:
+ return "AUX_E_XELPD";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
case POWER_DOMAIN_AUX_TBT_C:
@@ -144,12 +174,18 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_TBT_E";
case POWER_DOMAIN_AUX_TBT_F:
return "AUX_TBT_F";
- case POWER_DOMAIN_AUX_TBT_G:
- return "AUX_TBT_G";
- case POWER_DOMAIN_AUX_TBT_H:
- return "AUX_TBT_H";
- case POWER_DOMAIN_AUX_TBT_I:
- return "AUX_TBT_I";
+ case POWER_DOMAIN_AUX_TBT1:
+ return "AUX_TBT1";
+ case POWER_DOMAIN_AUX_TBT2:
+ return "AUX_TBT2";
+ case POWER_DOMAIN_AUX_TBT3:
+ return "AUX_TBT3";
+ case POWER_DOMAIN_AUX_TBT4:
+ return "AUX_TBT4";
+ case POWER_DOMAIN_AUX_TBT5:
+ return "AUX_TBT5";
+ case POWER_DOMAIN_AUX_TBT6:
+ return "AUX_TBT6";
case POWER_DOMAIN_GMBUS:
return "GMBUS";
case POWER_DOMAIN_INIT:
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index 2ea30a4cfaa89..b58c5bada6d85 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -48,18 +48,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_LANES_D,
POWER_DOMAIN_PORT_DDI_LANES_E,
POWER_DOMAIN_PORT_DDI_LANES_F,
- POWER_DOMAIN_PORT_DDI_LANES_G,
- POWER_DOMAIN_PORT_DDI_LANES_H,
- POWER_DOMAIN_PORT_DDI_LANES_I,
- POWER_DOMAIN_PORT_DDI_LANES_TC1 = POWER_DOMAIN_PORT_DDI_LANES_D, /* tgl+ */
+ POWER_DOMAIN_PORT_DDI_LANES_TC1,
POWER_DOMAIN_PORT_DDI_LANES_TC2,
POWER_DOMAIN_PORT_DDI_LANES_TC3,
POWER_DOMAIN_PORT_DDI_LANES_TC4,
POWER_DOMAIN_PORT_DDI_LANES_TC5,
POWER_DOMAIN_PORT_DDI_LANES_TC6,
- POWER_DOMAIN_PORT_DDI_LANES_D_XELPD = POWER_DOMAIN_PORT_DDI_LANES_TC5, /* XELPD */
+ POWER_DOMAIN_PORT_DDI_LANES_D_XELPD,
POWER_DOMAIN_PORT_DDI_LANES_E_XELPD,
POWER_DOMAIN_PORT_DDI_IO_A,
@@ -68,18 +65,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_IO_D,
POWER_DOMAIN_PORT_DDI_IO_E,
POWER_DOMAIN_PORT_DDI_IO_F,
- POWER_DOMAIN_PORT_DDI_IO_G,
- POWER_DOMAIN_PORT_DDI_IO_H,
- POWER_DOMAIN_PORT_DDI_IO_I,
- POWER_DOMAIN_PORT_DDI_IO_TC1 = POWER_DOMAIN_PORT_DDI_IO_D, /* tgl+ */
+ POWER_DOMAIN_PORT_DDI_IO_TC1,
POWER_DOMAIN_PORT_DDI_IO_TC2,
POWER_DOMAIN_PORT_DDI_IO_TC3,
POWER_DOMAIN_PORT_DDI_IO_TC4,
POWER_DOMAIN_PORT_DDI_IO_TC5,
POWER_DOMAIN_PORT_DDI_IO_TC6,
- POWER_DOMAIN_PORT_DDI_IO_D_XELPD = POWER_DOMAIN_PORT_DDI_IO_TC5, /* XELPD */
+ POWER_DOMAIN_PORT_DDI_IO_D_XELPD,
POWER_DOMAIN_PORT_DDI_IO_E_XELPD,
POWER_DOMAIN_PORT_DSI,
@@ -94,18 +88,15 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_D,
POWER_DOMAIN_AUX_E,
POWER_DOMAIN_AUX_F,
- POWER_DOMAIN_AUX_G,
- POWER_DOMAIN_AUX_H,
- POWER_DOMAIN_AUX_I,
- POWER_DOMAIN_AUX_USBC1 = POWER_DOMAIN_AUX_D, /* tgl+ */
+ POWER_DOMAIN_AUX_USBC1,
POWER_DOMAIN_AUX_USBC2,
POWER_DOMAIN_AUX_USBC3,
POWER_DOMAIN_AUX_USBC4,
POWER_DOMAIN_AUX_USBC5,
POWER_DOMAIN_AUX_USBC6,
- POWER_DOMAIN_AUX_D_XELPD = POWER_DOMAIN_AUX_USBC5, /* XELPD */
+ POWER_DOMAIN_AUX_D_XELPD,
POWER_DOMAIN_AUX_E_XELPD,
POWER_DOMAIN_AUX_IO_A,
@@ -113,11 +104,8 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_TBT_D,
POWER_DOMAIN_AUX_TBT_E,
POWER_DOMAIN_AUX_TBT_F,
- POWER_DOMAIN_AUX_TBT_G,
- POWER_DOMAIN_AUX_TBT_H,
- POWER_DOMAIN_AUX_TBT_I,
- POWER_DOMAIN_AUX_TBT1 = POWER_DOMAIN_AUX_TBT_D, /* tgl+ */
+ POWER_DOMAIN_AUX_TBT1,
POWER_DOMAIN_AUX_TBT2,
POWER_DOMAIN_AUX_TBT3,
POWER_DOMAIN_AUX_TBT4,
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 16/18] drm/i915: Remove the ICL specific TBT power domains
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (14 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 15/18] drm/i915: Remove the aliasing of power domain enum values Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 17/18] drm/i915: Remove duplicate DDI/AUX power domain mappings Imre Deak
` (9 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
The spec calls the ICL TBT AUX power well instances TBT1-4 (similarly to
all later platforms), align the power domain names with the spec.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
.../gpu/drm/i915/display/intel_display_power.c | 10 +---------
.../gpu/drm/i915/display/intel_display_power.h | 4 ----
.../drm/i915/display/intel_display_power_map.c | 16 ++++++++--------
3 files changed, 9 insertions(+), 21 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 7065b6265ea20..21da53aabff8b 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -166,14 +166,6 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_E_XELPD";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
- case POWER_DOMAIN_AUX_TBT_C:
- return "AUX_TBT_C";
- case POWER_DOMAIN_AUX_TBT_D:
- return "AUX_TBT_D";
- case POWER_DOMAIN_AUX_TBT_E:
- return "AUX_TBT_E";
- case POWER_DOMAIN_AUX_TBT_F:
- return "AUX_TBT_F";
case POWER_DOMAIN_AUX_TBT1:
return "AUX_TBT1";
case POWER_DOMAIN_AUX_TBT2:
@@ -2341,7 +2333,7 @@ d11_port_domains[] = {
.ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_C,
.ddi_io = POWER_DOMAIN_PORT_DDI_IO_C,
.aux_legacy_usbc = POWER_DOMAIN_AUX_C,
- .aux_tbt = POWER_DOMAIN_AUX_TBT_C,
+ .aux_tbt = POWER_DOMAIN_AUX_TBT1,
},
};
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index b58c5bada6d85..e04b2ff7b4b99 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -100,10 +100,6 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_E_XELPD,
POWER_DOMAIN_AUX_IO_A,
- POWER_DOMAIN_AUX_TBT_C,
- POWER_DOMAIN_AUX_TBT_D,
- POWER_DOMAIN_AUX_TBT_E,
- POWER_DOMAIN_AUX_TBT_F,
POWER_DOMAIN_AUX_TBT1,
POWER_DOMAIN_AUX_TBT2,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index 86d937f8bfe13..d9cf3d3bc02e7 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -622,10 +622,10 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
POWER_DOMAIN_AUX_D, \
POWER_DOMAIN_AUX_E, \
POWER_DOMAIN_AUX_F, \
- POWER_DOMAIN_AUX_TBT_C, \
- POWER_DOMAIN_AUX_TBT_D, \
- POWER_DOMAIN_AUX_TBT_E, \
- POWER_DOMAIN_AUX_TBT_F
+ POWER_DOMAIN_AUX_TBT1, \
+ POWER_DOMAIN_AUX_TBT2, \
+ POWER_DOMAIN_AUX_TBT3, \
+ POWER_DOMAIN_AUX_TBT4
I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3,
ICL_PW_3_POWER_DOMAINS,
@@ -668,10 +668,10 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_d, POWER_DOMAIN_AUX_D);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_e, POWER_DOMAIN_AUX_E);
I915_DECL_PW_DOMAINS(icl_pwdoms_aux_f, POWER_DOMAIN_AUX_F);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT_C);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT_D);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT_E);
-I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT_F);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
static const struct i915_power_well_desc icl_power_wells_pw_1[] = {
{
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 17/18] drm/i915: Remove duplicate DDI/AUX power domain mappings
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (15 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 16/18] drm/i915: Remove the ICL specific TBT power domains Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 18/18] drm/i915: Remove the XELPD specific AUX and DDI power domains Imre Deak
` (8 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
The DDI and AUX domain -> power well mappings are identical for a few
platforms/power well instances, reuse the mappings of earlier platforms
for these removing the duplicate mapping of new platforms.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
.../i915/display/intel_display_power_map.c | 89 +++++++------------
1 file changed, 31 insertions(+), 58 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index d9cf3d3bc02e7..d647fb5da6b44 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -653,9 +653,6 @@ I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
POWER_DOMAIN_DC_OFF,
POWER_DOMAIN_INIT);
-I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_a, POWER_DOMAIN_PORT_DDI_IO_A);
-I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_b, POWER_DOMAIN_PORT_DDI_IO_B);
-I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_c, POWER_DOMAIN_PORT_DDI_IO_C);
I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_d, POWER_DOMAIN_PORT_DDI_IO_D);
I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_e, POWER_DOMAIN_PORT_DDI_IO_E);
I915_DECL_PW_DOMAINS(icl_pwdoms_ddi_io_f, POWER_DOMAIN_PORT_DDI_IO_F);
@@ -714,9 +711,9 @@ static const struct i915_power_well_desc icl_power_wells_main[] = {
.has_fuses = true,
}, {
.instances = &I915_PW_INSTANCES(
- I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
- I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
- I915_PW("DDI_IO_C", &icl_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
+ I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = ICL_PW_CTL_IDX_DDI_D),
I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = ICL_PW_CTL_IDX_DDI_E),
I915_PW("DDI_IO_F", &icl_pwdoms_ddi_io_f, .hsw.idx = ICL_PW_CTL_IDX_DDI_F),
@@ -828,12 +825,6 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc5, POWER_DOMAIN_PORT_DDI_IO_TC5);
I915_DECL_PW_DOMAINS(tgl_pwdoms_ddi_io_tc6, POWER_DOMAIN_PORT_DDI_IO_TC6);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_a,
- POWER_DOMAIN_AUX_A,
- POWER_DOMAIN_AUX_IO_A);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_b, POWER_DOMAIN_AUX_B);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_c, POWER_DOMAIN_AUX_C);
-
I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
@@ -841,10 +832,6 @@ I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4);
I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc5, POWER_DOMAIN_AUX_USBC5);
I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_usbc6, POWER_DOMAIN_AUX_USBC6);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
-I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt5, POWER_DOMAIN_AUX_TBT5);
I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_tbt6, POWER_DOMAIN_AUX_TBT6);
@@ -890,9 +877,9 @@ static const struct i915_power_well_desc tgl_power_wells_main[] = {
.has_fuses = true,
}, {
.instances = &I915_PW_INSTANCES(
- I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
- I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
- I915_PW("DDI_IO_C", &icl_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
+ I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
@@ -933,9 +920,9 @@ static const struct i915_power_well_desc tgl_power_wells_tc_cold_off[] = {
static const struct i915_power_well_desc tgl_power_wells_aux[] = {
{
.instances = &I915_PW_INSTANCES(
- I915_PW("AUX_A", &tgl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
- I915_PW("AUX_B", &tgl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
- I915_PW("AUX_C", &tgl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
+ I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
+ I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
+ I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
@@ -946,10 +933,10 @@ static const struct i915_power_well_desc tgl_power_wells_aux[] = {
.ops = &icl_aux_power_well_ops,
}, {
.instances = &I915_PW_INSTANCES(
- I915_PW("AUX_TBT1", &tgl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
- I915_PW("AUX_TBT2", &tgl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
- I915_PW("AUX_TBT3", &tgl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
- I915_PW("AUX_TBT4", &tgl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
+ I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
+ I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
+ I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
+ I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
I915_PW("AUX_TBT5", &tgl_pwdoms_aux_tbt5, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT5),
I915_PW("AUX_TBT6", &tgl_pwdoms_aux_tbt6, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT6),
),
@@ -1058,8 +1045,8 @@ static const struct i915_power_well_desc rkl_power_wells_main[] = {
static const struct i915_power_well_desc rkl_power_wells_ddi_aux[] = {
{
.instances = &I915_PW_INSTANCES(
- I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
- I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
),
@@ -1273,22 +1260,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_d_xelpd, POWER_DOMAIN_AUX_D_XELPD);
I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_e_xelpd, POWER_DOMAIN_AUX_E_XELPD);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc1, POWER_DOMAIN_AUX_USBC1);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc2, POWER_DOMAIN_AUX_USBC2);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc3, POWER_DOMAIN_AUX_USBC3);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_usbc4, POWER_DOMAIN_AUX_USBC4);
-
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt1, POWER_DOMAIN_AUX_TBT1);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt2, POWER_DOMAIN_AUX_TBT2);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt3, POWER_DOMAIN_AUX_TBT3);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_tbt4, POWER_DOMAIN_AUX_TBT4);
-
I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_d_xelpd, POWER_DOMAIN_PORT_DDI_IO_D_XELPD);
I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_e_xelpd, POWER_DOMAIN_PORT_DDI_IO_E_XELPD);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc1, POWER_DOMAIN_PORT_DDI_IO_TC1);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc2, POWER_DOMAIN_PORT_DDI_IO_TC2);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc3, POWER_DOMAIN_PORT_DDI_IO_TC3);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_tc4, POWER_DOMAIN_PORT_DDI_IO_TC4);
static const struct i915_power_well_desc xelpd_power_wells_main[] = {
{
@@ -1340,37 +1313,37 @@ static const struct i915_power_well_desc xelpd_power_wells_main[] = {
.has_fuses = true,
}, {
.instances = &I915_PW_INSTANCES(
- I915_PW("DDI_IO_A", &icl_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
- I915_PW("DDI_IO_B", &icl_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
- I915_PW("DDI_IO_C", &icl_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
+ I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
+ I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
+ I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
I915_PW("DDI_IO_D_XELPD", &xelpd_pwdoms_ddi_io_d_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D),
I915_PW("DDI_IO_E_XELPD", &xelpd_pwdoms_ddi_io_e_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E),
- I915_PW("DDI_IO_TC1", &xelpd_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
- I915_PW("DDI_IO_TC2", &xelpd_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
- I915_PW("DDI_IO_TC3", &xelpd_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
- I915_PW("DDI_IO_TC4", &xelpd_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4),
+ I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
+ I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
+ I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
+ I915_PW("DDI_IO_TC4", &tgl_pwdoms_ddi_io_tc4, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC4),
),
.ops = &icl_ddi_power_well_ops,
}, {
.instances = &I915_PW_INSTANCES(
I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
- I915_PW("AUX_C", &tgl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
+ I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
I915_PW("AUX_D_XELPD", &xelpd_pwdoms_aux_d_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D),
I915_PW("AUX_E_XELPD", &xelpd_pwdoms_aux_e_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E),
- I915_PW("AUX_USBC1", &xelpd_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
- I915_PW("AUX_USBC2", &xelpd_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
- I915_PW("AUX_USBC3", &xelpd_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
- I915_PW("AUX_USBC4", &xelpd_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
+ I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
+ I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
+ I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
+ I915_PW("AUX_USBC4", &tgl_pwdoms_aux_usbc4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC4),
),
.ops = &icl_aux_power_well_ops,
.fixed_enable_delay = true,
}, {
.instances = &I915_PW_INSTANCES(
- I915_PW("AUX_TBT1", &xelpd_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
- I915_PW("AUX_TBT2", &xelpd_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
- I915_PW("AUX_TBT3", &xelpd_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
- I915_PW("AUX_TBT4", &xelpd_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
+ I915_PW("AUX_TBT1", &icl_pwdoms_aux_tbt1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT1),
+ I915_PW("AUX_TBT2", &icl_pwdoms_aux_tbt2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT2),
+ I915_PW("AUX_TBT3", &icl_pwdoms_aux_tbt3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT3),
+ I915_PW("AUX_TBT4", &icl_pwdoms_aux_tbt4, .hsw.idx = TGL_PW_CTL_IDX_AUX_TBT4),
),
.ops = &icl_aux_power_well_ops,
.is_tc_tbt = true,
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] [PATCH v3 18/18] drm/i915: Remove the XELPD specific AUX and DDI power domains
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (16 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 17/18] drm/i915: Remove duplicate DDI/AUX power domain mappings Imre Deak
@ 2022-03-29 16:43 ` Imre Deak
2022-03-29 17:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Refactor the display power domain mappings (rev3) Patchwork
` (7 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Imre Deak @ 2022-03-29 16:43 UTC (permalink / raw)
To: intel-gfx
The spec calls the XELPD_D/E ports just D/E, the platform prefix in the
domain names was only needed by the port->domain mapping relying on
matching enum values for the whole port/domain range (and the
corresponding aliasing between the platform specific domain enums).
Since a previous patch we can define the port->domain mapping explicitly
so do this by reusing the already existing D/E power domain names.
Signed-off-by: Imre Deak <imre.deak@intel.com>
Reviewed-by: Jouni Högander <jouni.hogander@intel.com>
---
.../drm/i915/display/intel_display_power.c | 18 +++------------
.../drm/i915/display/intel_display_power.h | 9 --------
.../i915/display/intel_display_power_map.c | 22 +++++++------------
3 files changed, 11 insertions(+), 38 deletions(-)
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.c b/drivers/gpu/drm/i915/display/intel_display_power.c
index 21da53aabff8b..831eb122953c6 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power.c
@@ -92,10 +92,6 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_LANES_TC5";
case POWER_DOMAIN_PORT_DDI_LANES_TC6:
return "PORT_DDI_LANES_TC6";
- case POWER_DOMAIN_PORT_DDI_LANES_D_XELPD:
- return "PORT_DDI_LANES_D_XELPD";
- case POWER_DOMAIN_PORT_DDI_LANES_E_XELPD:
- return "PORT_DDI_LANES_E_XELPD";
case POWER_DOMAIN_PORT_DDI_IO_A:
return "PORT_DDI_IO_A";
case POWER_DOMAIN_PORT_DDI_IO_B:
@@ -120,10 +116,6 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "PORT_DDI_IO_TC5";
case POWER_DOMAIN_PORT_DDI_IO_TC6:
return "PORT_DDI_IO_TC6";
- case POWER_DOMAIN_PORT_DDI_IO_D_XELPD:
- return "PORT_DDI_IO_D_XELPD";
- case POWER_DOMAIN_PORT_DDI_IO_E_XELPD:
- return "PORT_DDI_IO_E_XELPD";
case POWER_DOMAIN_PORT_DSI:
return "PORT_DSI";
case POWER_DOMAIN_PORT_CRT:
@@ -160,10 +152,6 @@ intel_display_power_domain_str(enum intel_display_power_domain domain)
return "AUX_USBC5";
case POWER_DOMAIN_AUX_USBC6:
return "AUX_USBC6";
- case POWER_DOMAIN_AUX_D_XELPD:
- return "AUX_D_XELPD";
- case POWER_DOMAIN_AUX_E_XELPD:
- return "AUX_E_XELPD";
case POWER_DOMAIN_AUX_IO_A:
return "AUX_IO_A";
case POWER_DOMAIN_AUX_TBT1:
@@ -2390,9 +2378,9 @@ d13_port_domains[] = {
.aux_ch_start = AUX_CH_D_XELPD,
.aux_ch_end = AUX_CH_E_XELPD,
- .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D_XELPD,
- .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D_XELPD,
- .aux_legacy_usbc = POWER_DOMAIN_AUX_D_XELPD,
+ .ddi_lanes = POWER_DOMAIN_PORT_DDI_LANES_D,
+ .ddi_io = POWER_DOMAIN_PORT_DDI_IO_D,
+ .aux_legacy_usbc = POWER_DOMAIN_AUX_D,
.aux_tbt = POWER_DOMAIN_INVALID,
},
};
diff --git a/drivers/gpu/drm/i915/display/intel_display_power.h b/drivers/gpu/drm/i915/display/intel_display_power.h
index e04b2ff7b4b99..7136ea3f233e9 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power.h
+++ b/drivers/gpu/drm/i915/display/intel_display_power.h
@@ -56,9 +56,6 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_LANES_TC5,
POWER_DOMAIN_PORT_DDI_LANES_TC6,
- POWER_DOMAIN_PORT_DDI_LANES_D_XELPD,
- POWER_DOMAIN_PORT_DDI_LANES_E_XELPD,
-
POWER_DOMAIN_PORT_DDI_IO_A,
POWER_DOMAIN_PORT_DDI_IO_B,
POWER_DOMAIN_PORT_DDI_IO_C,
@@ -73,9 +70,6 @@ enum intel_display_power_domain {
POWER_DOMAIN_PORT_DDI_IO_TC5,
POWER_DOMAIN_PORT_DDI_IO_TC6,
- POWER_DOMAIN_PORT_DDI_IO_D_XELPD,
- POWER_DOMAIN_PORT_DDI_IO_E_XELPD,
-
POWER_DOMAIN_PORT_DSI,
POWER_DOMAIN_PORT_CRT,
POWER_DOMAIN_PORT_OTHER,
@@ -96,9 +90,6 @@ enum intel_display_power_domain {
POWER_DOMAIN_AUX_USBC5,
POWER_DOMAIN_AUX_USBC6,
- POWER_DOMAIN_AUX_D_XELPD,
- POWER_DOMAIN_AUX_E_XELPD,
-
POWER_DOMAIN_AUX_IO_A,
POWER_DOMAIN_AUX_TBT1,
diff --git a/drivers/gpu/drm/i915/display/intel_display_power_map.c b/drivers/gpu/drm/i915/display/intel_display_power_map.c
index d647fb5da6b44..af6f54a26a351 100644
--- a/drivers/gpu/drm/i915/display/intel_display_power_map.c
+++ b/drivers/gpu/drm/i915/display/intel_display_power_map.c
@@ -1207,8 +1207,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
XELPD_PW_C_POWER_DOMAINS, \
XELPD_PW_D_POWER_DOMAINS, \
POWER_DOMAIN_PORT_DDI_LANES_C, \
- POWER_DOMAIN_PORT_DDI_LANES_D_XELPD, \
- POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, \
+ POWER_DOMAIN_PORT_DDI_LANES_D, \
+ POWER_DOMAIN_PORT_DDI_LANES_E, \
POWER_DOMAIN_PORT_DDI_LANES_TC1, \
POWER_DOMAIN_PORT_DDI_LANES_TC2, \
POWER_DOMAIN_PORT_DDI_LANES_TC3, \
@@ -1216,8 +1216,8 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
POWER_DOMAIN_VGA, \
POWER_DOMAIN_AUDIO_PLAYBACK, \
POWER_DOMAIN_AUX_C, \
- POWER_DOMAIN_AUX_D_XELPD, \
- POWER_DOMAIN_AUX_E_XELPD, \
+ POWER_DOMAIN_AUX_D, \
+ POWER_DOMAIN_AUX_E, \
POWER_DOMAIN_AUX_USBC1, \
POWER_DOMAIN_AUX_USBC2, \
POWER_DOMAIN_AUX_USBC3, \
@@ -1257,12 +1257,6 @@ I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
POWER_DOMAIN_MODESET,
POWER_DOMAIN_INIT);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_d_xelpd, POWER_DOMAIN_AUX_D_XELPD);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_aux_e_xelpd, POWER_DOMAIN_AUX_E_XELPD);
-
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_d_xelpd, POWER_DOMAIN_PORT_DDI_IO_D_XELPD);
-I915_DECL_PW_DOMAINS(xelpd_pwdoms_ddi_io_e_xelpd, POWER_DOMAIN_PORT_DDI_IO_E_XELPD);
-
static const struct i915_power_well_desc xelpd_power_wells_main[] = {
{
.instances = &I915_PW_INSTANCES(
@@ -1316,8 +1310,8 @@ static const struct i915_power_well_desc xelpd_power_wells_main[] = {
I915_PW("DDI_IO_A", &glk_pwdoms_ddi_io_a, .hsw.idx = ICL_PW_CTL_IDX_DDI_A),
I915_PW("DDI_IO_B", &glk_pwdoms_ddi_io_b, .hsw.idx = ICL_PW_CTL_IDX_DDI_B),
I915_PW("DDI_IO_C", &glk_pwdoms_ddi_io_c, .hsw.idx = ICL_PW_CTL_IDX_DDI_C),
- I915_PW("DDI_IO_D_XELPD", &xelpd_pwdoms_ddi_io_d_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D),
- I915_PW("DDI_IO_E_XELPD", &xelpd_pwdoms_ddi_io_e_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E),
+ I915_PW("DDI_IO_D", &icl_pwdoms_ddi_io_d, .hsw.idx = XELPD_PW_CTL_IDX_DDI_D),
+ I915_PW("DDI_IO_E", &icl_pwdoms_ddi_io_e, .hsw.idx = XELPD_PW_CTL_IDX_DDI_E),
I915_PW("DDI_IO_TC1", &tgl_pwdoms_ddi_io_tc1, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC1),
I915_PW("DDI_IO_TC2", &tgl_pwdoms_ddi_io_tc2, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC2),
I915_PW("DDI_IO_TC3", &tgl_pwdoms_ddi_io_tc3, .hsw.idx = TGL_PW_CTL_IDX_DDI_TC3),
@@ -1329,8 +1323,8 @@ static const struct i915_power_well_desc xelpd_power_wells_main[] = {
I915_PW("AUX_A", &icl_pwdoms_aux_a, .hsw.idx = ICL_PW_CTL_IDX_AUX_A),
I915_PW("AUX_B", &icl_pwdoms_aux_b, .hsw.idx = ICL_PW_CTL_IDX_AUX_B),
I915_PW("AUX_C", &icl_pwdoms_aux_c, .hsw.idx = ICL_PW_CTL_IDX_AUX_C),
- I915_PW("AUX_D_XELPD", &xelpd_pwdoms_aux_d_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D),
- I915_PW("AUX_E_XELPD", &xelpd_pwdoms_aux_e_xelpd, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E),
+ I915_PW("AUX_D", &icl_pwdoms_aux_d, .hsw.idx = XELPD_PW_CTL_IDX_AUX_D),
+ I915_PW("AUX_E", &icl_pwdoms_aux_e, .hsw.idx = XELPD_PW_CTL_IDX_AUX_E),
I915_PW("AUX_USBC1", &tgl_pwdoms_aux_usbc1, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC1),
I915_PW("AUX_USBC2", &tgl_pwdoms_aux_usbc2, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC2),
I915_PW("AUX_USBC3", &tgl_pwdoms_aux_usbc3, .hsw.idx = TGL_PW_CTL_IDX_AUX_TC3),
--
2.30.2
^ permalink raw reply related [flat|nested] 29+ messages in thread* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Refactor the display power domain mappings (rev3)
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (17 preceding siblings ...)
2022-03-29 16:43 ` [Intel-gfx] [PATCH v3 18/18] drm/i915: Remove the XELPD specific AUX and DDI power domains Imre Deak
@ 2022-03-29 17:52 ` Patchwork
2022-03-29 17:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
` (6 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2022-03-29 17:52 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Refactor the display power domain mappings (rev3)
URL : https://patchwork.freedesktop.org/series/99476/
State : warning
== Summary ==
$ dim checkpatch origin/drm-tip
b760be68ea17 drm/i915: Move per-platform power well hooks to intel_display_power_well.c
-:2157: CHECK:BRACES: Blank lines aren't necessary before a close brace '}'
#2157: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:265:
+
+ }
-:2367: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst
#2367: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:475:
+ msleep(1);
-:2372: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst
#2372: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:480:
+ msleep(1);
-:2693: WARNING:LONG_LINE: line length of 105 exceeds 100 columns
#2693: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:801:
+ DMC_PROGRAM(dev_priv->dmc.dmc_info[DMC_FW_MAIN].start_mmioaddr, 0)),
-:2733: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#2733: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:841:
+ intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
-:2760: WARNING:LONG_LINE: line length of 108 exceeds 100 columns
#2760: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:868:
+ intel_de_read(dev_priv, GEN8_CHICKEN_DCPR_1) | SKL_SELECT_ALTERNATE_DC_EXIT);
-:2862: WARNING:REPEATED_WORD: Possible repeated word: 'power'
#2862: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:970:
+ "Unexpected DBuf power power state (0x%08x, expected 0x%08x)\n",
-:2937: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2937: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:1045:
+static bool i9xx_always_on_power_well_enabled(struct drm_i915_private *dev_priv,
+ struct i915_power_well *power_well)
-:3209: CHECK:MACRO_ARG_REUSE: Macro argument reuse 'bits' - possible side-effects?
#3209: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:1317:
+#define BITS_SET(val, bits) (((val) & (bits)) == (bits))
-:3664: WARNING:MSLEEP: msleep < 20ms can sleep for up to 20ms; see Documentation/timers/timers-howto.rst
#3664: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:1772:
+ msleep(1);
-:3710: CHECK:LINE_SPACING: Please don't use multiple blank lines
#3710: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.c:1818:
+
+
total: 0 errors, 7 warnings, 4 checks, 3856 lines checked
86cb72f00160 drm/i915: Unexport the for_each_power_well() macros
-:23: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#23: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:24:
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
+ for_each_power_well(__dev_priv, __power_well) \
+ for_each_if((__power_well)->desc->domains & (__domain_mask))
-:23: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#23: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:24:
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain_mask) \
+ for_each_power_well(__dev_priv, __power_well) \
+ for_each_if((__power_well)->desc->domains & (__domain_mask))
-:27: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#27: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:28:
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
+ for_each_power_well_reverse(__dev_priv, __power_well) \
+ for_each_if((__power_well)->desc->domains & (__domain_mask))
-:27: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#27: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:28:
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain_mask) \
+ for_each_power_well_reverse(__dev_priv, __power_well) \
+ for_each_if((__power_well)->desc->domains & (__domain_mask))
-:73: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__dev_priv' - possible side-effects?
#73: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.h:15:
+#define for_each_power_well(__dev_priv, __power_well) \
+ for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
+ (__power_well) - (__dev_priv)->power_domains.power_wells < \
+ (__dev_priv)->power_domains.power_well_count; \
+ (__power_well)++)
-:73: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#73: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.h:15:
+#define for_each_power_well(__dev_priv, __power_well) \
+ for ((__power_well) = (__dev_priv)->power_domains.power_wells; \
+ (__power_well) - (__dev_priv)->power_domains.power_wells < \
+ (__dev_priv)->power_domains.power_well_count; \
+ (__power_well)++)
-:79: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__dev_priv' - possible side-effects?
#79: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.h:21:
+#define for_each_power_well_reverse(__dev_priv, __power_well) \
+ for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
+ (__dev_priv)->power_domains.power_well_count - 1; \
+ (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
+ (__power_well)--)
-:79: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#79: FILE: drivers/gpu/drm/i915/display/intel_display_power_well.h:21:
+#define for_each_power_well_reverse(__dev_priv, __power_well) \
+ for ((__power_well) = (__dev_priv)->power_domains.power_wells + \
+ (__dev_priv)->power_domains.power_well_count - 1; \
+ (__power_well) - (__dev_priv)->power_domains.power_wells >= 0; \
+ (__power_well)--)
total: 2 errors, 0 warnings, 6 checks, 58 lines checked
e45b48445238 drm/i915: Move the power domain->well mappings to intel_display_power_map.c
-:2350: WARNING:FILE_PATH_CHANGES: added, moved or deleted file(s), does MAINTAINERS need updating?
#2350:
new file mode 100644
-:4433: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well_descs' - possible side-effects?
#4433: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:2079:
+#define set_power_wells_mask(power_domains, __power_well_descs, skip_mask) \
+ __set_power_wells(power_domains, __power_well_descs, \
+ ARRAY_SIZE(__power_well_descs), skip_mask)
total: 0 errors, 1 warnings, 1 checks, 4467 lines checked
4eeff3ba0f24 drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield
e6a10f0958d4 drm/i915: Move the HSW power well flags to a common bitfield
e809f351fa66 drm/i915: Rename the power domain names to end with pipes/ports
1d3d8dac9778 drm/i915: Sanitize the power well names
3e90e324a279 drm/i915: Convert the power well descriptor domain mask to an array of domains
-:52: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__elems' - possible side-effects?
#52: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:17:
+#define __LIST(__elems) { \
+ .list = __elems, \
+ .count = ARRAY_SIZE(__elems), \
+}
-:57: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#57: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:22:
+#define I915_PW_DOMAINS(...) \
+ (const struct i915_power_domain_list) \
+ __LIST(__LIST_INLINE_ELEMS(enum intel_display_power_domain, __VA_ARGS__))
-:68: CHECK:LINE_SPACING: Please don't use multiple blank lines
#68: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:33:
+
+
-:91: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#91: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:47:
+I915_DECL_PW_DOMAINS(i830_pwdoms_pipes,
+ POWER_DOMAIN_PIPE_A,
-:134: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#134: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:71:
+I915_DECL_PW_DOMAINS(hsw_pwdoms_display,
+ POWER_DOMAIN_PIPE_B,
-:187: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#187: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:108:
+I915_DECL_PW_DOMAINS(bdw_pwdoms_display,
+ POWER_DOMAIN_PIPE_B,
-:270: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#270: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:145:
+I915_DECL_PW_DOMAINS(vlv_pwdoms_display,
+ POWER_DOMAIN_DISPLAY_CORE,
-:290: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#290: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:165:
+I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
-:298: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#298: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:173:
+I915_DECL_PW_DOMAINS(vlv_pwdoms_dpio_tx_bc_lanes,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
-:416: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#416: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:238:
+I915_DECL_PW_DOMAINS(chv_pwdoms_display,
+ POWER_DOMAIN_DISPLAY_CORE,
-:440: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#440: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:262:
+I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
-:447: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#447: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:269:
+I915_DECL_PW_DOMAINS(chv_pwdoms_dpio_cmn_d,
+ POWER_DOMAIN_PORT_DDI_LANES_D,
-:530: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#530: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:309:
+#define SKL_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D, \
+ POWER_DOMAIN_PORT_DDI_LANES_E, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D
-:550: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#550: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:329:
+I915_DECL_PW_DOMAINS(skl_pwdoms_pw_2,
+ SKL_PW_2_POWER_DOMAINS,
-:554: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#554: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:333:
+I915_DECL_PW_DOMAINS(skl_pwdoms_dc_off,
+ SKL_PW_2_POWER_DOMAINS,
-:561: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#561: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:340:
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_a_e,
+ POWER_DOMAIN_PORT_DDI_IO_A,
-:566: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#566: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:345:
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_b,
+ POWER_DOMAIN_PORT_DDI_IO_B,
-:570: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#570: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:349:
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_c,
+ POWER_DOMAIN_PORT_DDI_IO_C,
-:574: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#574: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:353:
+I915_DECL_PW_DOMAINS(skl_pwdoms_ddi_io_d,
+ POWER_DOMAIN_PORT_DDI_IO_D,
-:693: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#693: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:435:
+#define BXT_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C
-:710: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#710: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:452:
+I915_DECL_PW_DOMAINS(bxt_pwdoms_pw_2,
+ BXT_PW_2_POWER_DOMAINS,
-:714: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#714: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:456:
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dc_off,
+ BXT_PW_2_POWER_DOMAINS,
-:722: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#722: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:464:
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_a,
+ POWER_DOMAIN_PORT_DDI_LANES_A,
-:727: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#727: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:469:
+I915_DECL_PW_DOMAINS(bxt_pwdoms_dpio_cmn_bc,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
-:842: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#842: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:528:
+#define GLK_PW_2_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C
-:859: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#859: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:545:
+I915_DECL_PW_DOMAINS(glk_pwdoms_pw_2,
+ GLK_PW_2_POWER_DOMAINS,
-:863: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#863: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:549:
+I915_DECL_PW_DOMAINS(glk_pwdoms_dc_off,
+ GLK_PW_2_POWER_DOMAINS,
-:875: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#875: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:561:
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_a,
+ POWER_DOMAIN_PORT_DDI_LANES_A,
-:880: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#880: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:566:
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_b,
+ POWER_DOMAIN_PORT_DDI_LANES_B,
-:885: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#885: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:571:
+I915_DECL_PW_DOMAINS(glk_pwdoms_dpio_cmn_c,
+ POWER_DOMAIN_PORT_DDI_LANES_C,
-:890: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#890: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:576:
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
-:895: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#895: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:581:
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_b,
+ POWER_DOMAIN_AUX_B,
-:899: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#899: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:585:
+I915_DECL_PW_DOMAINS(glk_pwdoms_aux_c,
+ POWER_DOMAIN_AUX_C,
-:1022: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1022: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:711:
+#define ICL_PW_4_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C
-:1027: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1027: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:716:
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_4,
+ ICL_PW_4_POWER_DOMAINS,
-:1056: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1056: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:720:
+#define ICL_PW_3_POWER_DOMAINS \
+ ICL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_A, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_TRANSCODER_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D, \
+ POWER_DOMAIN_PORT_DDI_LANES_E, \
+ POWER_DOMAIN_PORT_DDI_LANES_F, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_B, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D, \
+ POWER_DOMAIN_AUX_E, \
+ POWER_DOMAIN_AUX_F, \
+ POWER_DOMAIN_AUX_TBT_C, \
+ POWER_DOMAIN_AUX_TBT_D, \
+ POWER_DOMAIN_AUX_TBT_E, \
+ POWER_DOMAIN_AUX_TBT_F
-:1082: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1082: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:746:
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_3,
+ ICL_PW_3_POWER_DOMAINS,
-:1093: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1093: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:753:
+#define ICL_PW_2_POWER_DOMAINS \
+ ICL_PW_3_POWER_DOMAINS, \
+ POWER_DOMAIN_TRANSCODER_VDSC_PW2
-:1098: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1098: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:758:
+I915_DECL_PW_DOMAINS(icl_pwdoms_pw_2,
+ ICL_PW_2_POWER_DOMAINS,
-:1132: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1132: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:765:
+I915_DECL_PW_DOMAINS(icl_pwdoms_dc_off,
+ ICL_PW_2_POWER_DOMAINS,
-:1146: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1146: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:779:
+I915_DECL_PW_DOMAINS(icl_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
-:1450: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1450: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:983:
+#define TGL_PW_5_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_D, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
+ POWER_DOMAIN_TRANSCODER_D
-:1456: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1456: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:989:
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_5,
+ TGL_PW_5_POWER_DOMAINS,
-:1459: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1459: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:992:
+#define TGL_PW_4_POWER_DOMAINS \
+ TGL_PW_5_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
-:1466: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1466: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:999:
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_4,
+ TGL_PW_4_POWER_DOMAINS,
-:1469: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1469: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1002:
+#define TGL_PW_3_POWER_DOMAINS \
+ TGL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC3, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC4, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC5, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC6, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2, \
+ POWER_DOMAIN_AUX_USBC3, \
+ POWER_DOMAIN_AUX_USBC4, \
+ POWER_DOMAIN_AUX_USBC5, \
+ POWER_DOMAIN_AUX_USBC6, \
+ POWER_DOMAIN_AUX_TBT1, \
+ POWER_DOMAIN_AUX_TBT2, \
+ POWER_DOMAIN_AUX_TBT3, \
+ POWER_DOMAIN_AUX_TBT4, \
+ POWER_DOMAIN_AUX_TBT5, \
+ POWER_DOMAIN_AUX_TBT6
-:1497: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1497: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1030:
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_3,
+ TGL_PW_3_POWER_DOMAINS,
-:1501: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1501: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1034:
+I915_DECL_PW_DOMAINS(tgl_pwdoms_pw_2,
+ TGL_PW_3_POWER_DOMAINS,
-:1506: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1506: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1039:
+I915_DECL_PW_DOMAINS(tgl_pwdoms_dc_off,
+ TGL_PW_3_POWER_DOMAINS,
-:1521: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1521: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1054:
+I915_DECL_PW_DOMAINS(tgl_pwdoms_aux_a,
+ POWER_DOMAIN_AUX_A,
-:1541: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1541: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1074:
+I915_DECL_PW_DOMAINS(tgl_pwdoms_tc_cold_off,
+ POWER_DOMAIN_AUX_USBC1,
-:1858: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1858: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1363:
+#define RKL_PW_4_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
-:1864: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1864: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1369:
+I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_4,
+ RKL_PW_4_POWER_DOMAINS,
-:1867: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#1867: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1372:
+#define RKL_PW_3_POWER_DOMAINS \
+ RKL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_MMIO, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2
-:1881: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1881: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1386:
+I915_DECL_PW_DOMAINS(rkl_pwdoms_pw_3,
+ RKL_PW_3_POWER_DOMAINS,
-:1897: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#1897: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1411:
+I915_DECL_PW_DOMAINS(rkl_pwdoms_dc_off,
+ RKL_PW_3_POWER_DOMAINS,
-:2044: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#2044: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1531:
+#define DG1_PW_3_POWER_DOMAINS \
+ TGL_PW_4_POWER_DOMAINS, \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2
-:2057: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2057: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1544:
+I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_3,
+ DG1_PW_3_POWER_DOMAINS,
-:2061: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2061: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1548:
+I915_DECL_PW_DOMAINS(dg1_pwdoms_dc_off,
+ DG1_PW_3_POWER_DOMAINS,
-:2069: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2069: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1556:
+I915_DECL_PW_DOMAINS(dg1_pwdoms_pw_2,
+ DG1_PW_3_POWER_DOMAINS,
-:2255: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#2255: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1710:
+#define XELPD_PW_D_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_D, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_D, \
+ POWER_DOMAIN_TRANSCODER_D
-:2261: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2261: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1716:
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_d,
+ XELPD_PW_D_POWER_DOMAINS,
-:2264: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#2264: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1719:
+#define XELPD_PW_C_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_C, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_C, \
+ POWER_DOMAIN_TRANSCODER_C
-:2270: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2270: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1725:
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_c,
+ XELPD_PW_C_POWER_DOMAINS,
-:2273: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#2273: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1728:
+#define XELPD_PW_B_POWER_DOMAINS \
+ POWER_DOMAIN_PIPE_B, \
+ POWER_DOMAIN_PIPE_PANEL_FITTER_B, \
+ POWER_DOMAIN_TRANSCODER_B
-:2279: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2279: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1734:
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_b,
+ XELPD_PW_B_POWER_DOMAINS,
-:2283: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2283: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1738:
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_a,
+ POWER_DOMAIN_PIPE_A,
-:2287: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#2287: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1742:
+#define XELPD_PW_2_POWER_DOMAINS \
+ XELPD_PW_B_POWER_DOMAINS, \
+ XELPD_PW_C_POWER_DOMAINS, \
+ XELPD_PW_D_POWER_DOMAINS, \
+ POWER_DOMAIN_PORT_DDI_LANES_C, \
+ POWER_DOMAIN_PORT_DDI_LANES_D_XELPD, \
+ POWER_DOMAIN_PORT_DDI_LANES_E_XELPD, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC1, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC2, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC3, \
+ POWER_DOMAIN_PORT_DDI_LANES_TC4, \
+ POWER_DOMAIN_VGA, \
+ POWER_DOMAIN_AUDIO_PLAYBACK, \
+ POWER_DOMAIN_AUX_C, \
+ POWER_DOMAIN_AUX_D_XELPD, \
+ POWER_DOMAIN_AUX_E_XELPD, \
+ POWER_DOMAIN_AUX_USBC1, \
+ POWER_DOMAIN_AUX_USBC2, \
+ POWER_DOMAIN_AUX_USBC3, \
+ POWER_DOMAIN_AUX_USBC4, \
+ POWER_DOMAIN_AUX_TBT1, \
+ POWER_DOMAIN_AUX_TBT2, \
+ POWER_DOMAIN_AUX_TBT3, \
+ POWER_DOMAIN_AUX_TBT4
-:2313: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2313: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1768:
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_pw_2,
+ XELPD_PW_2_POWER_DOMAINS,
-:2350: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis
#2350: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:1789:
+I915_DECL_PW_DOMAINS(xelpd_pwdoms_dc_off,
+ XELPD_PW_2_POWER_DOMAINS,
total: 17 errors, 0 warnings, 53 checks, 2540 lines checked
fcd6ff9811c3 drm/i915: Convert the u64 power well domains mask to a bitmap
-:177: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#177: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:25:
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
for_each_power_well(__dev_priv, __power_well) \
+ for_each_if(test_bit((__domain), (__power_well)->domains.bits))
-:177: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#177: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:25:
+#define for_each_power_domain_well(__dev_priv, __power_well, __domain) \
for_each_power_well(__dev_priv, __power_well) \
+ for_each_if(test_bit((__domain), (__power_well)->domains.bits))
-:183: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#183: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:29:
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \
for_each_power_well_reverse(__dev_priv, __power_well) \
+ for_each_if(test_bit((__domain), (__power_well)->domains.bits))
-:183: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__power_well' - possible side-effects?
#183: FILE: drivers/gpu/drm/i915/display/intel_display_power.c:29:
+#define for_each_power_domain_well_reverse(__dev_priv, __power_well, __domain) \
for_each_power_well_reverse(__dev_priv, __power_well) \
+ for_each_if(test_bit((__domain), (__power_well)->domains.bits))
-:527: CHECK:MACRO_ARG_REUSE: Macro argument reuse '__domain' - possible side-effects?
#527: FILE: drivers/gpu/drm/i915/display/intel_display_power.h:175:
+#define for_each_power_domain(__domain, __mask) \
+ for ((__domain) = 0; (__domain) < POWER_DOMAIN_NUM; (__domain)++) \
+ for_each_if(test_bit((__domain), (__mask)->bits))
total: 2 errors, 0 warnings, 3 checks, 530 lines checked
f68ac7ab1852 drm/i915: Simplify power well definitions by adding power well instances
-:33: ERROR:COMPLEX_MACRO: Macros with complex values should be enclosed in parentheses
#33: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:33:
+#define I915_PW_INSTANCES(...) \
+ (const struct i915_power_well_instance_list) \
+ __LIST(__LIST_INLINE_ELEMS(struct i915_power_well_instance, __VA_ARGS__))
-:47: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#47: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:45:
+ .instances = &I915_PW_INSTANCES(
-:62: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#62: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:64:
+ .instances = &I915_PW_INSTANCES(
-:71: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#71: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:70:
+ .instances = &I915_PW_INSTANCES(
-:85: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#85: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:97:
+ .instances = &I915_PW_INSTANCES(
-:94: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#94: FILE: drivers/gpu/drm/i915/display/intel_display_power_map.c:103:
+ .instances = &I915_PW_INSTANCES(
-:114: CHECK:OPEN_ENDED_LINE: Lines should not end with a '('
#114: FILE: drivers/gpu/
^ permalink raw reply [flat|nested] 29+ messages in thread* [Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915: Refactor the display power domain mappings (rev3)
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (18 preceding siblings ...)
2022-03-29 17:52 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Refactor the display power domain mappings (rev3) Patchwork
@ 2022-03-29 17:53 ` Patchwork
2022-03-29 17:57 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
` (5 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2022-03-29 17:53 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Refactor the display power domain mappings (rev3)
URL : https://patchwork.freedesktop.org/series/99476/
State : warning
== Summary ==
$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
^ permalink raw reply [flat|nested] 29+ messages in thread* [Intel-gfx] ✗ Fi.CI.DOCS: warning for drm/i915: Refactor the display power domain mappings (rev3)
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (19 preceding siblings ...)
2022-03-29 17:53 ` [Intel-gfx] ✗ Fi.CI.SPARSE: " Patchwork
@ 2022-03-29 17:57 ` Patchwork
2022-03-29 18:32 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
` (4 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2022-03-29 17:57 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Refactor the display power domain mappings (rev3)
URL : https://patchwork.freedesktop.org/series/99476/
State : warning
== Summary ==
$ make htmldocs 2>&1 > /dev/null | grep i915
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_enable' not found
./drivers/gpu/drm/i915/display/intel_drrs.c:1: warning: 'intel_drrs_disable' not found
^ permalink raw reply [flat|nested] 29+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Refactor the display power domain mappings (rev3)
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (20 preceding siblings ...)
2022-03-29 17:57 ` [Intel-gfx] ✗ Fi.CI.DOCS: " Patchwork
@ 2022-03-29 18:32 ` Patchwork
2022-03-30 16:11 ` Patchwork
` (3 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2022-03-29 18:32 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 20303 bytes --]
== Series Details ==
Series: drm/i915: Refactor the display power domain mappings (rev3)
URL : https://patchwork.freedesktop.org/series/99476/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22722
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22722 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22722, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/index.html
Participating hosts (42 -> 47)
------------------------------
Additional (9): fi-cml-u2 fi-tgl-u2 fi-skl-guc bat-adlm-1 fi-icl-u2 fi-cfl-8700k bat-adlp-4 fi-ivb-3770 fi-pnv-d510
Missing (4): fi-kbl-soraka fi-bsw-cyan shard-tglu fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22722:
### IGT changes ###
#### Possible regressions ####
* igt@runner@aborted:
- bat-adlp-4: NOTRUN -> [FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlp-4/igt@runner@aborted.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-dg2-9}: [DMESG-WARN][2] ([i915#5193]) -> [DMESG-WARN][3] +3 similar issues
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-9/igt@gem_exec_suspend@basic-s0@smem.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-9/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-dg2-8}: [DMESG-WARN][4] ([i915#5193]) -> [DMESG-WARN][5] +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-8/igt@gem_exec_suspend@basic-s3@smem.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-8/igt@gem_exec_suspend@basic-s3@smem.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- {bat-adlm-1}: NOTRUN -> [INCOMPLETE][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlm-1/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- {bat-dg2-9}: NOTRUN -> [DMESG-WARN][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
Known issues
------------
Here are the changes found in Patchwork_22722 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][8] ([fdo#109271]) +17 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_basic@userptr:
- fi-cfl-8700k: NOTRUN -> [SKIP][9] ([fdo#109271]) +29 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@amdgpu/amd_basic@userptr.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][10] ([fdo#109315]) +17 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@amdgpu/amd_cs_nop@sync-compute0:
- fi-cml-u2: NOTRUN -> [SKIP][11] ([fdo#109315]) +17 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@amdgpu/amd_cs_nop@sync-compute0.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2: NOTRUN -> [SKIP][12] ([i915#1208]) +1 similar issue
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510: NOTRUN -> [SKIP][13] ([fdo#109271]) +57 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-pnv-d510/igt@gem_huc_copy@huc-copy.html
- fi-tgl-u2: NOTRUN -> [SKIP][14] ([i915#2190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
- fi-cfl-8700k: NOTRUN -> [SKIP][15] ([fdo#109271] / [i915#2190])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@gem_huc_copy@huc-copy.html
- fi-icl-u2: NOTRUN -> [SKIP][16] ([i915#2190])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
- fi-cml-u2: NOTRUN -> [SKIP][17] ([i915#2190])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][18] ([i915#4613]) +3 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
- fi-cml-u2: NOTRUN -> [SKIP][19] ([i915#4613]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- fi-skl-guc: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) +3 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-skl-guc/igt@gem_lmem_swapping@random-engines.html
- fi-ivb-3770: NOTRUN -> [SKIP][21] ([fdo#109271]) +36 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-ivb-3770/igt@gem_lmem_swapping@random-engines.html
- fi-cfl-8700k: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613]) +3 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2: NOTRUN -> [SKIP][23] ([i915#4613]) +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@gem_lmem_swapping@verify-random.html
* igt@kms_busy@basic@flip:
- fi-tgl-u2: NOTRUN -> [DMESG-WARN][24] ([i915#402])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-u2: NOTRUN -> [SKIP][25] ([fdo#109284] / [fdo#111827]) +8 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
- fi-skl-guc: NOTRUN -> [SKIP][26] ([fdo#109271] / [fdo#111827]) +8 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-skl-guc/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cfl-8700k: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +8 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-ivb-3770: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +8 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-ivb-3770/igt@kms_chamelium@dp-hpd-fast.html
- fi-cml-u2: NOTRUN -> [SKIP][29] ([fdo#109284] / [fdo#111827]) +8 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][30] ([fdo#111827]) +8 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][31] ([i915#4103]) +1 similar issue
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-icl-u2: NOTRUN -> [SKIP][32] ([fdo#109278]) +2 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-cml-u2: NOTRUN -> [SKIP][33] ([fdo#109278]) +1 similar issue
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2: NOTRUN -> [SKIP][34] ([fdo#109285])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_force_connector_basic@force-load-detect.html
- fi-tgl-u2: NOTRUN -> [SKIP][35] ([fdo#109285])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
- fi-icl-u2: NOTRUN -> [SKIP][36] ([fdo#109285])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: NOTRUN -> [DMESG-WARN][37] ([i915#4269])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-pnv-d510: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#5341])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-pnv-d510/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2: NOTRUN -> [SKIP][39] ([fdo#109278] / [i915#533])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-skl-guc: NOTRUN -> [SKIP][40] ([fdo#109271] / [i915#533])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-cfl-8700k: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#533])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-skl-guc: NOTRUN -> [SKIP][42] ([fdo#109271]) +29 similar issues
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-skl-guc/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-tgl-u2: NOTRUN -> [SKIP][43] ([i915#3555])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_setmode@basic-clone-single-crtc.html
- fi-icl-u2: NOTRUN -> [SKIP][44] ([i915#3555])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
- fi-cml-u2: NOTRUN -> [SKIP][45] ([i915#3555])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-cml-u2: NOTRUN -> [SKIP][46] ([i915#3301])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@prime_vgem@basic-userptr.html
- fi-icl-u2: NOTRUN -> [SKIP][47] ([i915#3301])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-hsw-4770: NOTRUN -> [FAIL][48] ([fdo#109271] / [i915#1436] / [i915#2722] / [i915#4312])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-hsw-4770/igt@runner@aborted.html
- fi-tgl-1115g4: NOTRUN -> [FAIL][49] ([i915#5257])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-1115g4/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_pm_rps@basic-api:
- {fi-jsl-1}: [DMESG-WARN][50] -> [PASS][51]
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-jsl-1/igt@i915_pm_rps@basic-api.html
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-jsl-1/igt@i915_pm_rps@basic-api.html
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][52] ([i915#2940]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_lrc:
- {bat-adlp-6}: [INCOMPLETE][54] -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@guc_multi_lrc:
- {bat-rpls-2}: [DMESG-WARN][56] ([i915#4391]) -> [PASS][57] +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-rpls-2/igt@i915_selftest@live@guc_multi_lrc.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-rpls-2/igt@i915_selftest@live@guc_multi_lrc.html
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-g3258}: [INCOMPLETE][58] ([i915#3303] / [i915#4785]) -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
- {fi-ehl-2}: [INCOMPLETE][60] -> [PASS][61]
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- {bat-rpls-2}: [DMESG-FAIL][62] ([i915#5087]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-rpls-2/igt@i915_selftest@live@requests.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@workarounds:
- {bat-adlp-6}: [DMESG-WARN][64] ([i915#5068]) -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@i915_selftest@live@workarounds.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlp-6/igt@i915_selftest@live@workarounds.html
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][66] ([i915#3576]) -> [PASS][67] +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@kms_busy@basic@flip.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlp-6/igt@kms_busy@basic@flip.html
- {bat-dg2-9}: [DMESG-WARN][68] ([i915#5291]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-9/igt@kms_busy@basic@flip.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-9/igt@kms_busy@basic@flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1208]: https://gitlab.freedesktop.org/drm/intel/issues/1208
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068
[i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#5193]: https://gitlab.freedesktop.org/drm/intel/issues/5193
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
[i915#5291]: https://gitlab.freedesktop.org/drm/intel/issues/5291
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
Build changes
-------------
* Linux: CI_DRM_11416 -> Patchwork_22722
CI-20190529: 20190529
CI_DRM_11416: 1dc2c6953e2689a0e5b7cca8450da14059d35f03 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6399: 9ba6cb16f04319226383b57975db203561c75781 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22722: f504bb328a7ab0d8de86b7d4a2957a2489b85115 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f504bb328a7a drm/i915: Remove the XELPD specific AUX and DDI power domains
53e740d2f452 drm/i915: Remove duplicate DDI/AUX power domain mappings
70425109390c drm/i915: Remove the ICL specific TBT power domains
3520d9c5072e drm/i915: Remove the aliasing of power domain enum values
ebbce4a52f99 drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform
1d5ca6d6fd4a drm/i915: Sanitize the ADL-S power well definition
cf5d7ea94dbd drm/i915: Simplify the DG1 power well descriptors
d264fce0b3ef drm/i915: Allow platforms to share power well descriptors
f68ac7ab1852 drm/i915: Simplify power well definitions by adding power well instances
fcd6ff9811c3 drm/i915: Convert the u64 power well domains mask to a bitmap
3e90e324a279 drm/i915: Convert the power well descriptor domain mask to an array of domains
1d3d8dac9778 drm/i915: Sanitize the power well names
e809f351fa66 drm/i915: Rename the power domain names to end with pipes/ports
e6a10f0958d4 drm/i915: Move the HSW power well flags to a common bitfield
4eeff3ba0f24 drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield
e45b48445238 drm/i915: Move the power domain->well mappings to intel_display_power_map.c
86cb72f00160 drm/i915: Unexport the for_each_power_well() macros
b760be68ea17 drm/i915: Move per-platform power well hooks to intel_display_power_well.c
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/index.html
[-- Attachment #2: Type: text/html, Size: 23907 bytes --]
^ permalink raw reply [flat|nested] 29+ messages in thread* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Refactor the display power domain mappings (rev3)
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (21 preceding siblings ...)
2022-03-29 18:32 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
@ 2022-03-30 16:11 ` Patchwork
2022-03-30 16:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
` (2 subsequent siblings)
25 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2022-03-30 16:11 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 27381 bytes --]
== Series Details ==
Series: drm/i915: Refactor the display power domain mappings (rev3)
URL : https://patchwork.freedesktop.org/series/99476/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22722
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22722 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22722, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/index.html
Participating hosts (44 -> 51)
------------------------------
Additional (9): fi-cml-u2 fi-tgl-u2 fi-skl-guc bat-adlm-1 fi-icl-u2 fi-cfl-8700k bat-adlp-4 fi-ivb-3770 fi-pnv-d510
Missing (2): fi-bsw-cyan fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22722:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@ring_submission:
- fi-kbl-soraka: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-kbl-soraka/igt@i915_selftest@live@ring_submission.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-kbl-soraka/igt@i915_selftest@live@ring_submission.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-dg2-9}: [DMESG-WARN][3] ([i915#5193]) -> [DMESG-WARN][4] +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-9/igt@gem_exec_suspend@basic-s0@smem.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-9/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-dg2-8}: [DMESG-WARN][5] ([i915#5193]) -> [DMESG-WARN][6] +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-8/igt@gem_exec_suspend@basic-s3@smem.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-8/igt@gem_exec_suspend@basic-s3@smem.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- {bat-adlm-1}: NOTRUN -> [INCOMPLETE][7]
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlm-1/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- {bat-dg2-9}: NOTRUN -> [DMESG-WARN][8]
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
Known issues
------------
Here are the changes found in Patchwork_22722 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][9] ([fdo#109271]) +17 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_basic@userptr:
- fi-cfl-8700k: NOTRUN -> [SKIP][10] ([fdo#109271]) +29 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@amdgpu/amd_basic@userptr.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][11] ([fdo#109315]) +17 similar issues
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@amdgpu/amd_cs_nop@sync-compute0:
- fi-cml-u2: NOTRUN -> [SKIP][12] ([fdo#109315]) +17 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@amdgpu/amd_cs_nop@sync-compute0.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2: NOTRUN -> [SKIP][13] ([i915#1208]) +1 similar issue
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510: NOTRUN -> [SKIP][14] ([fdo#109271]) +57 similar issues
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-pnv-d510/igt@gem_huc_copy@huc-copy.html
- fi-tgl-u2: NOTRUN -> [SKIP][15] ([i915#2190])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
- fi-cfl-8700k: NOTRUN -> [SKIP][16] ([fdo#109271] / [i915#2190])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@gem_huc_copy@huc-copy.html
- fi-icl-u2: NOTRUN -> [SKIP][17] ([i915#2190])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
- fi-cml-u2: NOTRUN -> [SKIP][18] ([i915#2190])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][19] ([i915#4613]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
- fi-cml-u2: NOTRUN -> [SKIP][20] ([i915#4613]) +3 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- fi-skl-guc: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-skl-guc/igt@gem_lmem_swapping@random-engines.html
- fi-ivb-3770: NOTRUN -> [SKIP][22] ([fdo#109271]) +36 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-ivb-3770/igt@gem_lmem_swapping@random-engines.html
- fi-cfl-8700k: NOTRUN -> [SKIP][23] ([fdo#109271] / [i915#4613]) +3 similar issues
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2: NOTRUN -> [SKIP][24] ([i915#4613]) +3 similar issues
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@gem_lmem_swapping@verify-random.html
* igt@kms_busy@basic@flip:
- fi-tgl-u2: NOTRUN -> [DMESG-WARN][25] ([i915#402])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-u2: NOTRUN -> [SKIP][26] ([fdo#109284] / [fdo#111827]) +8 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
- fi-skl-guc: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +8 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-skl-guc/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cfl-8700k: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +8 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-ivb-3770: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +8 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-ivb-3770/igt@kms_chamelium@dp-hpd-fast.html
- fi-cml-u2: NOTRUN -> [SKIP][30] ([fdo#109284] / [fdo#111827]) +8 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][31] ([fdo#111827]) +8 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][32] ([i915#4103]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-icl-u2: NOTRUN -> [SKIP][33] ([fdo#109278]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-cml-u2: NOTRUN -> [SKIP][34] ([fdo#109278]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2: NOTRUN -> [SKIP][35] ([fdo#109285])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_force_connector_basic@force-load-detect.html
- fi-tgl-u2: NOTRUN -> [SKIP][36] ([fdo#109285])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
- fi-icl-u2: NOTRUN -> [SKIP][37] ([fdo#109285])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: NOTRUN -> [DMESG-WARN][38] ([i915#4269])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-pnv-d510: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#5341])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-pnv-d510/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2: NOTRUN -> [SKIP][40] ([fdo#109278] / [i915#533])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-skl-guc: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#533])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-cfl-8700k: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#533])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-skl-guc: NOTRUN -> [SKIP][43] ([fdo#109271]) +29 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-skl-guc/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-tgl-u2: NOTRUN -> [SKIP][44] ([i915#3555])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_setmode@basic-clone-single-crtc.html
- fi-icl-u2: NOTRUN -> [SKIP][45] ([i915#3555])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
- fi-cml-u2: NOTRUN -> [SKIP][46] ([i915#3555])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-cml-u2: NOTRUN -> [SKIP][47] ([i915#3301])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@prime_vgem@basic-userptr.html
- fi-icl-u2: NOTRUN -> [SKIP][48] ([i915#3301])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-hsw-4770: NOTRUN -> [FAIL][49] ([fdo#109271] / [i915#1436] / [i915#2722] / [i915#4312])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-hsw-4770/igt@runner@aborted.html
- bat-adlp-4: NOTRUN -> [FAIL][50] ([i915#5457])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlp-4/igt@runner@aborted.html
- fi-tgl-1115g4: NOTRUN -> [FAIL][51] ([i915#5257])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-1115g4/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_pm_rps@basic-api:
- {fi-jsl-1}: [DMESG-WARN][52] ([i915#5482]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-jsl-1/igt@i915_pm_rps@basic-api.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-jsl-1/igt@i915_pm_rps@basic-api.html
* igt@i915_pm_rps@reset:
- {shard-dg1}: [FAIL][54] ([i915#3719]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-dg1-19/igt@i915_pm_rps@reset.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-dg1-17/igt@i915_pm_rps@reset.html
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][56] ([i915#2940]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_lrc:
- {bat-adlp-6}: [INCOMPLETE][58] -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@guc_multi_lrc:
- {bat-rpls-2}: [DMESG-WARN][60] ([i915#4391]) -> [PASS][61] +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-rpls-2/igt@i915_selftest@live@guc_multi_lrc.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-rpls-2/igt@i915_selftest@live@guc_multi_lrc.html
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-g3258}: [INCOMPLETE][62] ([i915#3303] / [i915#4785]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
- {fi-ehl-2}: [INCOMPLETE][64] -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- {bat-rpls-2}: [DMESG-FAIL][66] ([i915#5087]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-rpls-2/igt@i915_selftest@live@requests.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@workarounds:
- {bat-adlp-6}: [DMESG-WARN][68] ([i915#5068]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@i915_selftest@live@workarounds.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlp-6/igt@i915_selftest@live@workarounds.html
* igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180:
- {shard-rkl}: [SKIP][70] ([i915#1845] / [i915#4098]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-rkl-4/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180.html
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][72] ([i915#3576]) -> [PASS][73] +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@kms_busy@basic@flip.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlp-6/igt@kms_busy@basic@flip.html
- {bat-dg2-9}: [DMESG-WARN][74] ([i915#5291]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-9/igt@kms_busy@basic@flip.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-9/igt@kms_busy@basic@flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1208]: https://gitlab.freedesktop.org/drm/intel/issues/1208
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3719]: https://gitlab.freedesktop.org/drm/intel/issues/3719
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#4903]: https://gitlab.freedesktop.org/drm/intel/issues/4903
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068
[i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5193]: https://gitlab.freedesktop.org/drm/intel/issues/5193
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5266]: https://gitlab.freedesktop.org/drm/intel/issues/5266
[i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5291]: https://gitlab.freedesktop.org/drm/intel/issues/5291
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5457]: https://gitlab.freedesktop.org/drm/intel/issues/5457
[i915#5482]: https://gitlab.freedesktop.org/drm/intel/issues/5482
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
Build changes
-------------
* Linux: CI_DRM_11416 -> Patchwork_22722
CI-20190529: 20190529
CI_DRM_11416: 1dc2c6953e2689a0e5b7cca8450da14059d35f03 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6399: 9ba6cb16f04319226383b57975db203561c75781 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22722: f504bb328a7ab0d8de86b7d4a2957a2489b85115 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f504bb328a7a drm/i915: Remove the XELPD specific AUX and DDI power domains
53e740d2f452 drm/i915: Remove duplicate DDI/AUX power domain mappings
70425109390c drm/i915: Remove the ICL specific TBT power domains
3520d9c5072e drm/i915: Remove the aliasing of power domain enum values
ebbce4a52f99 drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform
1d5ca6d6fd4a drm/i915: Sanitize the ADL-S power well definition
cf5d7ea94dbd drm/i915: Simplify the DG1 power well descriptors
d264fce0b3ef drm/i915: Allow platforms to share power well descriptors
f68ac7ab1852 drm/i915: Simplify power well definitions by adding power well instances
fcd6ff9811c3 drm/i915: Convert the u64 power well domains mask to a bitmap
3e90e324a279 drm/i915: Convert the power well descriptor domain mask to an array of domains
1d3d8dac9778 drm/i915: Sanitize the power well names
e809f351fa66 drm/i915: Rename the power domain names to end with pipes/ports
e6a10f0958d4 drm/i915: Move the HSW power well flags to a common bitfield
4eeff3ba0f24 drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield
e45b48445238 drm/i915: Move the power domain->well mappings to intel_display_power_map.c
86cb72f00160 drm/i915: Unexport the for_each_power_well() macros
b760be68ea17 drm/i915: Move per-platform power well hooks to intel_display_power_well.c
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/index.html
[-- Attachment #2: Type: text/html, Size: 25335 bytes --]
^ permalink raw reply [flat|nested] 29+ messages in thread* [Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915: Refactor the display power domain mappings (rev3)
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (22 preceding siblings ...)
2022-03-30 16:11 ` Patchwork
@ 2022-03-30 16:57 ` Patchwork
2022-03-30 18:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
2022-03-30 21:53 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
25 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2022-03-30 16:57 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 27127 bytes --]
== Series Details ==
Series: drm/i915: Refactor the display power domain mappings (rev3)
URL : https://patchwork.freedesktop.org/series/99476/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11416 -> Patchwork_22722
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/index.html
Participating hosts (44 -> 51)
------------------------------
Additional (9): fi-cml-u2 fi-tgl-u2 fi-skl-guc bat-adlm-1 fi-icl-u2 fi-cfl-8700k bat-adlp-4 fi-ivb-3770 fi-pnv-d510
Missing (2): fi-bsw-cyan fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22722:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s0@smem:
- {bat-dg2-9}: [DMESG-WARN][1] ([i915#5193]) -> [DMESG-WARN][2] +3 similar issues
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-9/igt@gem_exec_suspend@basic-s0@smem.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-9/igt@gem_exec_suspend@basic-s0@smem.html
* igt@gem_exec_suspend@basic-s3@smem:
- {bat-dg2-8}: [DMESG-WARN][3] ([i915#5193]) -> [DMESG-WARN][4] +3 similar issues
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-8/igt@gem_exec_suspend@basic-s3@smem.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-8/igt@gem_exec_suspend@basic-s3@smem.html
* igt@kms_addfb_basic@tile-pitch-mismatch:
- {bat-adlm-1}: NOTRUN -> [INCOMPLETE][5]
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlm-1/igt@kms_addfb_basic@tile-pitch-mismatch.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- {bat-dg2-9}: NOTRUN -> [DMESG-WARN][6]
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-9/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
Known issues
------------
Here are the changes found in Patchwork_22722 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@amdgpu/amd_basic@query-info:
- fi-bsw-kefka: NOTRUN -> [SKIP][7] ([fdo#109271]) +17 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-bsw-kefka/igt@amdgpu/amd_basic@query-info.html
* igt@amdgpu/amd_basic@userptr:
- fi-cfl-8700k: NOTRUN -> [SKIP][8] ([fdo#109271]) +29 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@amdgpu/amd_basic@userptr.html
* igt@amdgpu/amd_cs_nop@fork-gfx0:
- fi-icl-u2: NOTRUN -> [SKIP][9] ([fdo#109315]) +17 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@amdgpu/amd_cs_nop@fork-gfx0.html
* igt@amdgpu/amd_cs_nop@sync-compute0:
- fi-cml-u2: NOTRUN -> [SKIP][10] ([fdo#109315]) +17 similar issues
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@amdgpu/amd_cs_nop@sync-compute0.html
* igt@gem_exec_fence@basic-busy@bcs0:
- fi-cml-u2: NOTRUN -> [SKIP][11] ([i915#1208]) +1 similar issue
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@gem_exec_fence@basic-busy@bcs0.html
* igt@gem_huc_copy@huc-copy:
- fi-pnv-d510: NOTRUN -> [SKIP][12] ([fdo#109271]) +57 similar issues
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-pnv-d510/igt@gem_huc_copy@huc-copy.html
- fi-tgl-u2: NOTRUN -> [SKIP][13] ([i915#2190])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html
- fi-cfl-8700k: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#2190])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@gem_huc_copy@huc-copy.html
- fi-icl-u2: NOTRUN -> [SKIP][15] ([i915#2190])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
- fi-cml-u2: NOTRUN -> [SKIP][16] ([i915#2190])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][17] ([i915#4613]) +3 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
- fi-cml-u2: NOTRUN -> [SKIP][18] ([i915#4613]) +3 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_lmem_swapping@random-engines:
- fi-skl-guc: NOTRUN -> [SKIP][19] ([fdo#109271] / [i915#4613]) +3 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-skl-guc/igt@gem_lmem_swapping@random-engines.html
- fi-ivb-3770: NOTRUN -> [SKIP][20] ([fdo#109271]) +36 similar issues
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-ivb-3770/igt@gem_lmem_swapping@random-engines.html
- fi-cfl-8700k: NOTRUN -> [SKIP][21] ([fdo#109271] / [i915#4613]) +3 similar issues
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@gem_lmem_swapping@random-engines.html
* igt@gem_lmem_swapping@verify-random:
- fi-tgl-u2: NOTRUN -> [SKIP][22] ([i915#4613]) +3 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@gem_lmem_swapping@verify-random.html
* igt@i915_selftest@live@ring_submission:
- fi-kbl-soraka: [PASS][23] -> [INCOMPLETE][24] ([i915#5503])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-kbl-soraka/igt@i915_selftest@live@ring_submission.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-kbl-soraka/igt@i915_selftest@live@ring_submission.html
* igt@kms_busy@basic@flip:
- fi-tgl-u2: NOTRUN -> [DMESG-WARN][25] ([i915#402])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_busy@basic@flip.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-tgl-u2: NOTRUN -> [SKIP][26] ([fdo#109284] / [fdo#111827]) +8 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_chamelium@common-hpd-after-suspend.html
- fi-skl-guc: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +8 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-skl-guc/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-cfl-8700k: NOTRUN -> [SKIP][28] ([fdo#109271] / [fdo#111827]) +8 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@dp-hpd-fast:
- fi-ivb-3770: NOTRUN -> [SKIP][29] ([fdo#109271] / [fdo#111827]) +8 similar issues
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-ivb-3770/igt@kms_chamelium@dp-hpd-fast.html
- fi-cml-u2: NOTRUN -> [SKIP][30] ([fdo#109284] / [fdo#111827]) +8 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_chamelium@dp-hpd-fast.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][31] ([fdo#111827]) +8 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-tgl-u2: NOTRUN -> [SKIP][32] ([i915#4103]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-icl-u2: NOTRUN -> [SKIP][33] ([fdo#109278]) +2 similar issues
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-cml-u2: NOTRUN -> [SKIP][34] ([fdo#109278]) +1 similar issue
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_force_connector_basic@force-load-detect:
- fi-cml-u2: NOTRUN -> [SKIP][35] ([fdo#109285])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_force_connector_basic@force-load-detect.html
- fi-tgl-u2: NOTRUN -> [SKIP][36] ([fdo#109285])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html
- fi-icl-u2: NOTRUN -> [SKIP][37] ([fdo#109285])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_frontbuffer_tracking@basic:
- fi-cml-u2: NOTRUN -> [DMESG-WARN][38] ([i915#4269])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_frontbuffer_tracking@basic.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c:
- fi-pnv-d510: NOTRUN -> [SKIP][39] ([fdo#109271] / [i915#5341])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-pnv-d510/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-cml-u2: NOTRUN -> [SKIP][40] ([fdo#109278] / [i915#533])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-skl-guc: NOTRUN -> [SKIP][41] ([fdo#109271] / [i915#533])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-skl-guc/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-cfl-8700k: NOTRUN -> [SKIP][42] ([fdo#109271] / [i915#533])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cfl-8700k/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-skl-guc: NOTRUN -> [SKIP][43] ([fdo#109271]) +29 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-skl-guc/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-tgl-u2: NOTRUN -> [SKIP][44] ([i915#3555])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-u2/igt@kms_setmode@basic-clone-single-crtc.html
- fi-icl-u2: NOTRUN -> [SKIP][45] ([i915#3555])
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
- fi-cml-u2: NOTRUN -> [SKIP][46] ([i915#3555])
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-userptr:
- fi-cml-u2: NOTRUN -> [SKIP][47] ([i915#3301])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-cml-u2/igt@prime_vgem@basic-userptr.html
- fi-icl-u2: NOTRUN -> [SKIP][48] ([i915#3301])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-icl-u2/igt@prime_vgem@basic-userptr.html
* igt@runner@aborted:
- fi-hsw-4770: NOTRUN -> [FAIL][49] ([fdo#109271] / [i915#1436] / [i915#2722] / [i915#4312])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-hsw-4770/igt@runner@aborted.html
- bat-adlp-4: NOTRUN -> [FAIL][50] ([i915#5457])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlp-4/igt@runner@aborted.html
- fi-tgl-1115g4: NOTRUN -> [FAIL][51] ([i915#5257])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-tgl-1115g4/igt@runner@aborted.html
#### Possible fixes ####
* igt@i915_pm_rps@basic-api:
- {fi-jsl-1}: [DMESG-WARN][52] ([i915#5482]) -> [PASS][53]
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-jsl-1/igt@i915_pm_rps@basic-api.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-jsl-1/igt@i915_pm_rps@basic-api.html
* igt@i915_pm_rps@reset:
- {shard-dg1}: [FAIL][54] ([i915#3719]) -> [PASS][55]
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-dg1-19/igt@i915_pm_rps@reset.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-dg1-17/igt@i915_pm_rps@reset.html
* igt@i915_selftest@live@execlists:
- fi-bsw-kefka: [INCOMPLETE][56] ([i915#2940]) -> [PASS][57]
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-bsw-kefka/igt@i915_selftest@live@execlists.html
* igt@i915_selftest@live@gt_lrc:
- {bat-adlp-6}: [INCOMPLETE][58] -> [PASS][59]
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlp-6/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@guc_multi_lrc:
- {bat-rpls-2}: [DMESG-WARN][60] ([i915#4391]) -> [PASS][61] +1 similar issue
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-rpls-2/igt@i915_selftest@live@guc_multi_lrc.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-rpls-2/igt@i915_selftest@live@guc_multi_lrc.html
* igt@i915_selftest@live@hangcheck:
- {fi-hsw-g3258}: [INCOMPLETE][62] ([i915#3303] / [i915#4785]) -> [PASS][63]
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-hsw-g3258/igt@i915_selftest@live@hangcheck.html
- {fi-ehl-2}: [INCOMPLETE][64] -> [PASS][65]
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/fi-ehl-2/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@requests:
- {bat-rpls-2}: [DMESG-FAIL][66] ([i915#5087]) -> [PASS][67]
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-rpls-2/igt@i915_selftest@live@requests.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-rpls-2/igt@i915_selftest@live@requests.html
* igt@i915_selftest@live@workarounds:
- {bat-adlp-6}: [DMESG-WARN][68] ([i915#5068]) -> [PASS][69]
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@i915_selftest@live@workarounds.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlp-6/igt@i915_selftest@live@workarounds.html
* igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180:
- {shard-rkl}: [SKIP][70] ([i915#1845] / [i915#4098]) -> [PASS][71]
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-rkl-4/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-rkl-6/igt@kms_big_fb@linear-max-hw-stride-32bpp-rotate-180.html
* igt@kms_busy@basic@flip:
- {bat-adlp-6}: [DMESG-WARN][72] ([i915#3576]) -> [PASS][73] +2 similar issues
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-adlp-6/igt@kms_busy@basic@flip.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-adlp-6/igt@kms_busy@basic@flip.html
- {bat-dg2-9}: [DMESG-WARN][74] ([i915#5291]) -> [PASS][75]
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/bat-dg2-9/igt@kms_busy@basic@flip.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/bat-dg2-9/igt@kms_busy@basic@flip.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#1208]: https://gitlab.freedesktop.org/drm/intel/issues/1208
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1436]: https://gitlab.freedesktop.org/drm/intel/issues/1436
[i915#1769]: https://gitlab.freedesktop.org/drm/intel/issues/1769
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2433]: https://gitlab.freedesktop.org/drm/intel/issues/2433
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2940]: https://gitlab.freedesktop.org/drm/intel/issues/2940
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3303]: https://gitlab.freedesktop.org/drm/intel/issues/3303
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3469]: https://gitlab.freedesktop.org/drm/intel/issues/3469
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3719]: https://gitlab.freedesktop.org/drm/intel/issues/3719
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3840]: https://gitlab.freedesktop.org/drm/intel/issues/3840
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3955]: https://gitlab.freedesktop.org/drm/intel/issues/3955
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#426]: https://gitlab.freedesktop.org/drm/intel/issues/426
[i915#4269]: https://gitlab.freedesktop.org/drm/intel/issues/4269
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4874]: https://gitlab.freedesktop.org/drm/intel/issues/4874
[i915#4880]: https://gitlab.freedesktop.org/drm/intel/issues/4880
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897
[i915#4903]: https://gitlab.freedesktop.org/drm/intel/issues/4903
[i915#4991]: https://gitlab.freedesktop.org/drm/intel/issues/4991
[i915#5068]: https://gitlab.freedesktop.org/drm/intel/issues/5068
[i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
[i915#5127]: https://gitlab.freedesktop.org/drm/intel/issues/5127
[i915#5176]: https://gitlab.freedesktop.org/drm/intel/issues/5176
[i915#5193]: https://gitlab.freedesktop.org/drm/intel/issues/5193
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5266]: https://gitlab.freedesktop.org/drm/intel/issues/5266
[i915#5270]: https://gitlab.freedesktop.org/drm/intel/issues/5270
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5291]: https://gitlab.freedesktop.org/drm/intel/issues/5291
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341
[i915#5439]: https://gitlab.freedesktop.org/drm/intel/issues/5439
[i915#5457]: https://gitlab.freedesktop.org/drm/intel/issues/5457
[i915#5482]: https://gitlab.freedesktop.org/drm/intel/issues/5482
[i915#5503]: https://gitlab.freedesktop.org/drm/intel/issues/5503
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
Build changes
-------------
* Linux: CI_DRM_11416 -> Patchwork_22722
CI-20190529: 20190529
CI_DRM_11416: 1dc2c6953e2689a0e5b7cca8450da14059d35f03 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6399: 9ba6cb16f04319226383b57975db203561c75781 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_22722: f504bb328a7ab0d8de86b7d4a2957a2489b85115 @ git://anongit.freedesktop.org/gfx-ci/linux
== Linux commits ==
f504bb328a7a drm/i915: Remove the XELPD specific AUX and DDI power domains
53e740d2f452 drm/i915: Remove duplicate DDI/AUX power domain mappings
70425109390c drm/i915: Remove the ICL specific TBT power domains
3520d9c5072e drm/i915: Remove the aliasing of power domain enum values
ebbce4a52f99 drm/i915: Sanitize the port -> DDI/AUX power domain mapping for each platform
1d5ca6d6fd4a drm/i915: Sanitize the ADL-S power well definition
cf5d7ea94dbd drm/i915: Simplify the DG1 power well descriptors
d264fce0b3ef drm/i915: Allow platforms to share power well descriptors
f68ac7ab1852 drm/i915: Simplify power well definitions by adding power well instances
fcd6ff9811c3 drm/i915: Convert the u64 power well domains mask to a bitmap
3e90e324a279 drm/i915: Convert the power well descriptor domain mask to an array of domains
1d3d8dac9778 drm/i915: Sanitize the power well names
e809f351fa66 drm/i915: Rename the power domain names to end with pipes/ports
e6a10f0958d4 drm/i915: Move the HSW power well flags to a common bitfield
4eeff3ba0f24 drm/i915: Move the dg2 fixed_enable_delay power well param to a common bitfield
e45b48445238 drm/i915: Move the power domain->well mappings to intel_display_power_map.c
86cb72f00160 drm/i915: Unexport the for_each_power_well() macros
b760be68ea17 drm/i915: Move per-platform power well hooks to intel_display_power_well.c
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/index.html
[-- Attachment #2: Type: text/html, Size: 25061 bytes --]
^ permalink raw reply [flat|nested] 29+ messages in thread* [Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915: Refactor the display power domain mappings (rev3)
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (23 preceding siblings ...)
2022-03-30 16:57 ` [Intel-gfx] ✓ Fi.CI.BAT: success " Patchwork
@ 2022-03-30 18:35 ` Patchwork
2022-03-30 21:53 ` [Intel-gfx] ✓ Fi.CI.IGT: success " Patchwork
25 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2022-03-30 18:35 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30278 bytes --]
== Series Details ==
Series: drm/i915: Refactor the display power domain mappings (rev3)
URL : https://patchwork.freedesktop.org/series/99476/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22722_full
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_22722_full absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_22722_full, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
Participating hosts (11 -> 13)
------------------------------
Additional (2): shard-rkl shard-dg1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22722_full:
### IGT changes ###
#### Possible regressions ####
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-c-edp-1-downscale-with-pixel-format:
- shard-iclb: [PASS][1] -> [INCOMPLETE][2]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb6/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-c-edp-1-downscale-with-pixel-format.html
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb2/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-c-edp-1-downscale-with-pixel-format.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_whisper@basic-forked:
- {shard-rkl}: NOTRUN -> [DMESG-WARN][3]
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-rkl-5/igt@gem_exec_whisper@basic-forked.html
* {igt@kms_psr_stress_test@flip-primary-invalidate-overlay}:
- shard-iclb: [PASS][4] -> [SKIP][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
Known issues
------------
Here are the changes found in Patchwork_22722_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#1099]) +1 similar issue
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-snb2/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-tglb: NOTRUN -> [SKIP][7] ([i915#280])
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][8] -> [FAIL][9] ([i915#232])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb7/igt@gem_eio@unwedge-stress.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb5/igt@gem_eio@unwedge-stress.html
- shard-skl: [PASS][10] -> [TIMEOUT][11] ([i915#3063])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl9/igt@gem_eio@unwedge-stress.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl2/igt@gem_eio@unwedge-stress.html
- shard-iclb: [PASS][12] -> [TIMEOUT][13] ([i915#2481] / [i915#3070])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb1/igt@gem_eio@unwedge-stress.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_capture@pi@bcs0:
- shard-skl: [PASS][14] -> [INCOMPLETE][15] ([i915#4547])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl2/igt@gem_exec_capture@pi@bcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl6/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][16] -> [FAIL][17] ([i915#2842])
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-glk: [PASS][18] -> [FAIL][19] ([i915#2842]) +1 similar issue
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-glk9/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-apl: NOTRUN -> [FAIL][20] ([i915#2842])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_lmem_swapping@parallel-random:
- shard-tglb: NOTRUN -> [SKIP][21] ([i915#4613])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@verify-random:
- shard-skl: NOTRUN -> [SKIP][22] ([fdo#109271] / [i915#4613]) +1 similar issue
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl3/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap_offset@oob-read:
- shard-skl: NOTRUN -> [DMESG-WARN][23] ([i915#1982])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl4/igt@gem_mmap_offset@oob-read.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [PASS][24] -> [FAIL][25] ([i915#644])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl6/igt@gem_ppgtt@flink-and-close-vma-leak.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl8/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][26] ([i915#2658])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-snb2/igt@gem_pread@exhaustion.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-iclb: NOTRUN -> [SKIP][27] ([i915#4270])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-tglb: NOTRUN -> [SKIP][28] ([i915#4270])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][29] ([i915#768])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-skl: NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3323])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl7/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@input-checking:
- shard-kbl: NOTRUN -> [DMESG-WARN][31] ([i915#4991])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@gem_userptr_blits@input-checking.html
* igt@gen7_exec_parse@basic-allowed:
- shard-tglb: NOTRUN -> [SKIP][32] ([fdo#109289]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@gen7_exec_parse@basic-allowed.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-iclb: NOTRUN -> [SKIP][33] ([i915#2856])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][34] ([i915#2527] / [i915#2856])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_selftest@live@gt_lrc:
- shard-tglb: NOTRUN -> [DMESG-FAIL][35] ([i915#2373])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_pm:
- shard-tglb: NOTRUN -> [DMESG-FAIL][36] ([i915#1759])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@forcewake:
- shard-kbl: [PASS][37] -> [DMESG-WARN][38] ([i915#180]) +2 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-kbl3/igt@i915_suspend@forcewake.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl7/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-180:
- shard-tglb: NOTRUN -> [SKIP][39] ([i915#5286])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][40] ([fdo#111614])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][41] ([fdo#110725] / [fdo#111614])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][42] ([i915#3743])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][43] ([fdo#110723])
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-tglb: NOTRUN -> [SKIP][44] ([fdo#111615])
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-skl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3777]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][46] ([fdo#109271] / [i915#3886]) +6 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl4/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][47] ([fdo#109271] / [i915#3886]) +3 similar issues
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][48] ([fdo#109278]) +3 similar issues
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][49] ([i915#3689] / [i915#3886])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][50] ([fdo#111615] / [i915#3689])
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][51] ([fdo#109271] / [i915#3886])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl6/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][52] ([i915#3689]) +1 similar issue
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs.html
* igt@kms_chamelium@hdmi-crc-fast:
- shard-apl: NOTRUN -> [SKIP][53] ([fdo#109271] / [fdo#111827]) +2 similar issues
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl2/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-skl: NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +14 similar issues
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl7/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_color_chamelium@pipe-a-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][55] ([fdo#109284] / [fdo#111827]) +1 similar issue
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-b-ctm-0-25:
- shard-kbl: NOTRUN -> [SKIP][56] ([fdo#109271] / [fdo#111827]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@kms_color_chamelium@pipe-b-ctm-0-25.html
* igt@kms_color_chamelium@pipe-c-ctm-0-25:
- shard-tglb: NOTRUN -> [SKIP][57] ([fdo#109284] / [fdo#111827]) +3 similar issues
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_color_chamelium@pipe-c-ctm-0-25.html
* igt@kms_color_chamelium@pipe-d-ctm-negative:
- shard-iclb: NOTRUN -> [SKIP][58] ([fdo#109278] / [fdo#109284] / [fdo#111827]) +1 similar issue
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@kms_color_chamelium@pipe-d-ctm-negative.html
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> [TIMEOUT][59] ([i915#1319])
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-tglb: NOTRUN -> [SKIP][60] ([i915#3116] / [i915#3299])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding:
- shard-tglb: NOTRUN -> [SKIP][61] ([i915#3359]) +1 similar issue
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-tglb: NOTRUN -> [SKIP][62] ([i915#4103])
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][63] -> [FAIL][64] ([i915#2346])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-iclb: [PASS][65] -> [FAIL][66] ([i915#2346])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb1/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-4tiled:
- shard-tglb: NOTRUN -> [SKIP][67] ([i915#5287])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-4tiled.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-tglb: NOTRUN -> [SKIP][68] ([fdo#109274] / [fdo#111825]) +2 similar issues
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> [SKIP][69] ([fdo#109274])
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-edp1:
- shard-skl: NOTRUN -> [INCOMPLETE][70] ([i915#4839])
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl2/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][71] -> [DMESG-WARN][72] ([i915#180]) +2 similar issues
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl: NOTRUN -> [FAIL][73] ([i915#2122])
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-iclb: [PASS][74] -> [SKIP][75] ([i915#3701]) +1 similar issue
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
- shard-iclb: NOTRUN -> [SKIP][76] ([fdo#109280]) +2 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][77] ([fdo#109271]) +178 similar issues
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl3/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-tglb: NOTRUN -> [SKIP][78] ([fdo#109280] / [fdo#111825]) +6 similar issues
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][79] ([fdo#109271] / [i915#533])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][80] ([fdo#108145] / [i915#265]) +1 similar issue
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][81] ([fdo#108145] / [i915#265])
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][82] -> [FAIL][83] ([fdo#108145] / [i915#265])
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_cursor@pipe-d-overlay-size-64:
- shard-apl: NOTRUN -> [SKIP][84] ([fdo#109271]) +40 similar issues
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl2/igt@kms_plane_cursor@pipe-d-overlay-size-64.html
* igt@kms_plane_lowres@pipe-a-tiling-4:
- shard-tglb: NOTRUN -> [SKIP][85] ([i915#5288])
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_plane_lowres@pipe-a-tiling-4.html
* igt@kms_plane_lowres@pipe-b-tiling-y:
- shard-iclb: NOTRUN -> [SKIP][86] ([i915#3536])
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@kms_plane_lowres@pipe-b-tiling-y.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-x:
- shard-kbl: NOTRUN -> [SKIP][87] ([fdo#109271]) +49 similar issues
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@kms_plane_multiple@atomic-pipe-d-tiling-x.html
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-5@pipe-c-edp-1-downscale-with-pixel-format:
- shard-iclb: [PASS][88] -> [SKIP][89] ([i915#5176]) +4 similar issues
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb1/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-5@pipe-c-edp-1-downscale-with-pixel-format.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb2/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-5@pipe-c-edp-1-downscale-with-pixel-format.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale:
- shard-iclb: [PASS][90] -> [SKIP][91] ([i915#5235]) +2 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-skl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#658]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-apl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#658])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl4/igt@kms_psr2_su@frontbuffer-xrgb8888.html
- shard-iclb: NOTRUN -> [SKIP][94] ([fdo#109642] / [fdo#111068] / [i915#658])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-tglb: NOTRUN -> [FAIL][95] ([i915#132] / [i915#3467])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [PASS][96] -> [SKIP][97] ([fdo#109441]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb4/igt@kms_psr@psr2_sprite_render.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-snb: NOTRUN -> [SKIP][98] ([fdo#109271]) +76 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-snb2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-iclb: NOTRUN -> [SKIP][99] ([i915#3555])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-skl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#533]) +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl2/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-check-output:
- shard-kbl: NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#2437])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-iclb: NOTRUN -> [SKIP][102] ([i915#2437])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-tglb: NOTRUN -> [SKIP][103] ([i915#2437])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame:
- shard-iclb: NOTRUN -> [SKIP][104] ([i915#2530])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame.html
* igt@perf@gen12-oa-tlb-invalidate:
- shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109289]) +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@perf@gen12-oa-tlb-invalidate.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][106] -> [FAIL][107] ([i915#1542])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl9/igt@perf@polling-parameterized.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl7/igt@perf@polling-parameterized.html
* igt@perf_pmu@rc6-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][108] ([i915#180])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl1/igt@perf_pmu@rc6-suspend.html
* igt@prime_nv_api@i915_nv_import_twice:
- shard-iclb: NOTRUN -> [SKIP][109] ([fdo#109291]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@prime_nv_api@i915_nv_import_twice.html
* igt@prime_nv_pcopy@test3_2:
- shard-tglb: NOTRUN -> [SKIP][110] ([fdo#109291])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@prime_nv_pcopy@test3_2.html
* igt@syncobj_timeline@invalid-transfer-non-existent-point:
- shard-kbl: NOTRUN -> [DMESG-WARN][111] ([i915#5098])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@syncobj_timeline@invalid-transfer-non-existent-point.html
* igt@sysfs_clients@busy:
- shard-kbl: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#2994])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@sysfs_clients@busy.html
* igt@sysfs_clients@fair-7:
- shard-iclb: NOTRUN -> [SKIP][113] ([i915#2994])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@sema-10:
- shard-skl: NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#2994]) +2 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl2/igt@sysfs_clients@sema-10.html
* igt@sysfs_clients@split-25:
- shard-tglb: NOTRUN -> [SKIP][115] ([i915#2994])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@sysfs_clients@split-25.html
* igt@tools_test@sysfs_l3_parity:
- shard-tglb: NOTRUN -> [SKIP][116] ([fdo#109307])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@tools_test@sysfs_l3_parity.html
#### Possible fixes ####
* igt@gem_caching@reads:
- shard-glk: [DMESG-WARN][117] ([i915#118]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk5/igt@gem_caching@reads.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-glk7/igt@gem_caching@reads.html
* igt@gem_eio@unwedge-stress:
- {shard-tglu}: [TIMEOUT][119] ([i915#3063] / [i915#3648]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglu-1/igt@gem_eio@unwedge-stress.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglu-1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][121] ([i915#4525]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb5/igt@gem_exec_balancer@parallel-balancer.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb1/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [FAIL][123] ([i915#2846]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
- shard-glk: [FAIL][125] ([i915#2846]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk8/igt@gem_exec_fair@basic-deadline.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-glk9/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][127] ([i915#2842]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][129] ([i915#2842]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl8/igt@gem_exec_fair@basic-none@vecs0.html
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/index.html
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^ permalink raw reply [flat|nested] 29+ messages in thread* [Intel-gfx] ✓ Fi.CI.IGT: success for drm/i915: Refactor the display power domain mappings (rev3)
2022-03-29 16:43 [Intel-gfx] [PATCH v3 00/18] drm/i915: Refactor the display power domain mappings Imre Deak
` (24 preceding siblings ...)
2022-03-30 18:35 ` [Intel-gfx] ✗ Fi.CI.IGT: failure " Patchwork
@ 2022-03-30 21:53 ` Patchwork
25 siblings, 0 replies; 29+ messages in thread
From: Patchwork @ 2022-03-30 21:53 UTC (permalink / raw)
To: Imre Deak; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 30282 bytes --]
== Series Details ==
Series: drm/i915: Refactor the display power domain mappings (rev3)
URL : https://patchwork.freedesktop.org/series/99476/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11416_full -> Patchwork_22722_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (11 -> 13)
------------------------------
Additional (2): shard-rkl shard-dg1
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_22722_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_whisper@basic-forked:
- {shard-rkl}: NOTRUN -> [DMESG-WARN][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-rkl-5/igt@gem_exec_whisper@basic-forked.html
* {igt@kms_psr_stress_test@flip-primary-invalidate-overlay}:
- shard-iclb: [PASS][2] -> [SKIP][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb4/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@kms_psr_stress_test@flip-primary-invalidate-overlay.html
Known issues
------------
Here are the changes found in Patchwork_22722_full that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_ctx_persistence@legacy-engines-queued:
- shard-snb: NOTRUN -> [SKIP][4] ([fdo#109271] / [i915#1099]) +1 similar issue
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-snb2/igt@gem_ctx_persistence@legacy-engines-queued.html
* igt@gem_ctx_sseu@invalid-sseu:
- shard-tglb: NOTRUN -> [SKIP][5] ([i915#280])
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@gem_ctx_sseu@invalid-sseu.html
* igt@gem_eio@unwedge-stress:
- shard-tglb: [PASS][6] -> [FAIL][7] ([i915#232])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglb7/igt@gem_eio@unwedge-stress.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb5/igt@gem_eio@unwedge-stress.html
- shard-skl: [PASS][8] -> [TIMEOUT][9] ([i915#3063])
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl9/igt@gem_eio@unwedge-stress.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl2/igt@gem_eio@unwedge-stress.html
- shard-iclb: [PASS][10] -> [TIMEOUT][11] ([i915#2481] / [i915#3070])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb1/igt@gem_eio@unwedge-stress.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb2/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_capture@pi@bcs0:
- shard-skl: [PASS][12] -> [INCOMPLETE][13] ([i915#4547])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl2/igt@gem_exec_capture@pi@bcs0.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl6/igt@gem_exec_capture@pi@bcs0.html
* igt@gem_exec_fair@basic-pace-solo@rcs0:
- shard-iclb: [PASS][14] -> [FAIL][15] ([i915#2842])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-glk: [PASS][16] -> [FAIL][17] ([i915#2842]) +1 similar issue
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk8/igt@gem_exec_fair@basic-pace-solo@rcs0.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-glk9/igt@gem_exec_fair@basic-pace-solo@rcs0.html
- shard-apl: NOTRUN -> [FAIL][18] ([i915#2842])
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl2/igt@gem_exec_fair@basic-pace-solo@rcs0.html
* igt@gem_lmem_swapping@parallel-random:
- shard-tglb: NOTRUN -> [SKIP][19] ([i915#4613])
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@gem_lmem_swapping@parallel-random.html
* igt@gem_lmem_swapping@verify-random:
- shard-skl: NOTRUN -> [SKIP][20] ([fdo#109271] / [i915#4613]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl3/igt@gem_lmem_swapping@verify-random.html
* igt@gem_mmap_offset@oob-read:
- shard-skl: NOTRUN -> [DMESG-WARN][21] ([i915#1982])
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl4/igt@gem_mmap_offset@oob-read.html
* igt@gem_ppgtt@flink-and-close-vma-leak:
- shard-apl: [PASS][22] -> [FAIL][23] ([i915#644])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl6/igt@gem_ppgtt@flink-and-close-vma-leak.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl8/igt@gem_ppgtt@flink-and-close-vma-leak.html
* igt@gem_pread@exhaustion:
- shard-snb: NOTRUN -> [WARN][24] ([i915#2658])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-snb2/igt@gem_pread@exhaustion.html
* igt@gem_pxp@reject-modify-context-protection-off-2:
- shard-iclb: NOTRUN -> [SKIP][25] ([i915#4270])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@gem_pxp@reject-modify-context-protection-off-2.html
* igt@gem_pxp@verify-pxp-stale-buf-optout-execution:
- shard-tglb: NOTRUN -> [SKIP][26] ([i915#4270])
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@gem_pxp@verify-pxp-stale-buf-optout-execution.html
* igt@gem_render_copy@linear-to-vebox-y-tiled:
- shard-iclb: NOTRUN -> [SKIP][27] ([i915#768])
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@gem_render_copy@linear-to-vebox-y-tiled.html
* igt@gem_userptr_blits@dmabuf-sync:
- shard-skl: NOTRUN -> [SKIP][28] ([fdo#109271] / [i915#3323])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl7/igt@gem_userptr_blits@dmabuf-sync.html
* igt@gem_userptr_blits@input-checking:
- shard-kbl: NOTRUN -> [DMESG-WARN][29] ([i915#4991])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@gem_userptr_blits@input-checking.html
* igt@gen7_exec_parse@basic-allowed:
- shard-tglb: NOTRUN -> [SKIP][30] ([fdo#109289]) +1 similar issue
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@gen7_exec_parse@basic-allowed.html
* igt@gen9_exec_parse@basic-rejected-ctx-param:
- shard-iclb: NOTRUN -> [SKIP][31] ([i915#2856])
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@gen9_exec_parse@basic-rejected-ctx-param.html
* igt@gen9_exec_parse@cmd-crossing-page:
- shard-tglb: NOTRUN -> [SKIP][32] ([i915#2527] / [i915#2856])
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@gen9_exec_parse@cmd-crossing-page.html
* igt@i915_selftest@live@gt_lrc:
- shard-tglb: NOTRUN -> [DMESG-FAIL][33] ([i915#2373])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@i915_selftest@live@gt_lrc.html
* igt@i915_selftest@live@gt_pm:
- shard-tglb: NOTRUN -> [DMESG-FAIL][34] ([i915#1759])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@i915_selftest@live@gt_pm.html
* igt@i915_suspend@forcewake:
- shard-kbl: [PASS][35] -> [DMESG-WARN][36] ([i915#180]) +2 similar issues
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-kbl3/igt@i915_suspend@forcewake.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl7/igt@i915_suspend@forcewake.html
* igt@kms_big_fb@4-tiled-8bpp-rotate-180:
- shard-tglb: NOTRUN -> [SKIP][37] ([i915#5286])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_big_fb@4-tiled-8bpp-rotate-180.html
* igt@kms_big_fb@linear-32bpp-rotate-270:
- shard-tglb: NOTRUN -> [SKIP][38] ([fdo#111614])
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_big_fb@linear-32bpp-rotate-270.html
* igt@kms_big_fb@linear-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][39] ([fdo#110725] / [fdo#111614])
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@kms_big_fb@linear-8bpp-rotate-270.html
* igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip:
- shard-skl: NOTRUN -> [FAIL][40] ([i915#3743])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl7/igt@kms_big_fb@x-tiled-max-hw-stride-64bpp-rotate-0-async-flip.html
* igt@kms_big_fb@yf-tiled-8bpp-rotate-270:
- shard-iclb: NOTRUN -> [SKIP][41] ([fdo#110723])
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@kms_big_fb@yf-tiled-8bpp-rotate-270.html
* igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow:
- shard-tglb: NOTRUN -> [SKIP][42] ([fdo#111615])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_big_fb@yf-tiled-addfb-size-offset-overflow.html
* igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
- shard-skl: NOTRUN -> [SKIP][43] ([fdo#109271] / [i915#3777]) +3 similar issues
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl3/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html
* igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][44] ([fdo#109271] / [i915#3886]) +6 similar issues
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl4/igt@kms_ccs@pipe-a-bad-pixel-format-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
- shard-kbl: NOTRUN -> [SKIP][45] ([fdo#109271] / [i915#3886]) +3 similar issues
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs:
- shard-iclb: NOTRUN -> [SKIP][46] ([fdo#109278]) +3 similar issues
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs.html
* igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs:
- shard-tglb: NOTRUN -> [SKIP][47] ([i915#3689] / [i915#3886])
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_ccs@pipe-a-crc-sprite-planes-basic-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][48] ([fdo#111615] / [i915#3689])
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_ccs@pipe-b-bad-rotation-90-yf_tiled_ccs.html
* igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-apl: NOTRUN -> [SKIP][49] ([fdo#109271] / [i915#3886])
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl6/igt@kms_ccs@pipe-c-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs:
- shard-tglb: NOTRUN -> [SKIP][50] ([i915#3689]) +1 similar issue
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_ccs@pipe-d-bad-aux-stride-y_tiled_ccs.html
* igt@kms_chamelium@hdmi-crc-fast:
- shard-apl: NOTRUN -> [SKIP][51] ([fdo#109271] / [fdo#111827]) +2 similar issues
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl2/igt@kms_chamelium@hdmi-crc-fast.html
* igt@kms_chamelium@hdmi-hpd-storm-disable:
- shard-skl: NOTRUN -> [SKIP][52] ([fdo#109271] / [fdo#111827]) +14 similar issues
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl7/igt@kms_chamelium@hdmi-hpd-storm-disable.html
* igt@kms_color_chamelium@pipe-a-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][53] ([fdo#109284] / [fdo#111827]) +1 similar issue
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@kms_color_chamelium@pipe-a-ctm-red-to-blue.html
* igt@kms_color_chamelium@pipe-b-ctm-0-25:
- shard-kbl: NOTRUN -> [SKIP][54] ([fdo#109271] / [fdo#111827]) +1 similar issue
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@kms_color_chamelium@pipe-b-ctm-0-25.html
* igt@kms_color_chamelium@pipe-c-ctm-0-25:
- shard-tglb: NOTRUN -> [SKIP][55] ([fdo#109284] / [fdo#111827]) +3 similar issues
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_color_chamelium@pipe-c-ctm-0-25.html
* igt@kms_color_chamelium@pipe-d-ctm-negative:
- shard-iclb: NOTRUN -> [SKIP][56] ([fdo#109278] / [fdo#109284] / [fdo#111827]) +1 similar issue
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@kms_color_chamelium@pipe-d-ctm-negative.html
* igt@kms_content_protection@atomic:
- shard-kbl: NOTRUN -> [TIMEOUT][57] ([i915#1319])
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@kms_content_protection@atomic.html
* igt@kms_content_protection@dp-mst-lic-type-1:
- shard-tglb: NOTRUN -> [SKIP][58] ([i915#3116] / [i915#3299])
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_content_protection@dp-mst-lic-type-1.html
* igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding:
- shard-tglb: NOTRUN -> [SKIP][59] ([i915#3359]) +1 similar issue
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_cursor_crc@pipe-b-cursor-32x10-sliding.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size:
- shard-tglb: NOTRUN -> [SKIP][60] ([i915#4103])
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-glk: [PASS][61] -> [FAIL][62] ([i915#2346])
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-glk8/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_cursor_legacy@flip-vs-cursor-toggle:
- shard-iclb: [PASS][63] -> [FAIL][64] ([i915#2346])
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb1/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-toggle.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-4tiled:
- shard-tglb: NOTRUN -> [SKIP][65] ([i915#5287])
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-wc-4tiled.html
* igt@kms_flip@2x-dpms-vs-vblank-race-interruptible:
- shard-tglb: NOTRUN -> [SKIP][66] ([fdo#109274] / [fdo#111825]) +2 similar issues
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_flip@2x-dpms-vs-vblank-race-interruptible.html
* igt@kms_flip@2x-flip-vs-wf_vblank-interruptible:
- shard-iclb: NOTRUN -> [SKIP][67] ([fdo#109274])
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@kms_flip@2x-flip-vs-wf_vblank-interruptible.html
* igt@kms_flip@flip-vs-suspend-interruptible@b-edp1:
- shard-skl: NOTRUN -> [INCOMPLETE][68] ([i915#4839])
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl2/igt@kms_flip@flip-vs-suspend-interruptible@b-edp1.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [PASS][69] -> [DMESG-WARN][70] ([i915#180]) +2 similar issues
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1:
- shard-skl: NOTRUN -> [FAIL][71] ([i915#2122])
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl3/igt@kms_flip@plain-flip-ts-check-interruptible@c-edp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-iclb: [PASS][72] -> [SKIP][73] ([i915#3701]) +1 similar issue
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb1/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff:
- shard-iclb: NOTRUN -> [SKIP][74] ([fdo#109280]) +2 similar issues
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@kms_frontbuffer_tracking@fbc-2p-scndscrn-cur-indfb-onoff.html
* igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt:
- shard-skl: NOTRUN -> [SKIP][75] ([fdo#109271]) +178 similar issues
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl3/igt@kms_frontbuffer_tracking@fbcpsr-1p-shrfb-fliptrack-mmap-gtt.html
* igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu:
- shard-tglb: NOTRUN -> [SKIP][76] ([fdo#109280] / [fdo#111825]) +6 similar issues
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_frontbuffer_tracking@psr-2p-primscrn-cur-indfb-draw-mmap-cpu.html
* igt@kms_pipe_crc_basic@read-crc-pipe-d:
- shard-kbl: NOTRUN -> [SKIP][77] ([fdo#109271] / [i915#533])
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@kms_pipe_crc_basic@read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max:
- shard-skl: NOTRUN -> [FAIL][78] ([fdo#108145] / [i915#265]) +1 similar issue
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl3/igt@kms_plane_alpha_blend@pipe-a-constant-alpha-max.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-kbl: NOTRUN -> [FAIL][79] ([fdo#108145] / [i915#265])
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-coverage-7efc:
- shard-skl: [PASS][80] -> [FAIL][81] ([fdo#108145] / [i915#265])
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl6/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-coverage-7efc.html
* igt@kms_plane_cursor@pipe-d-overlay-size-64:
- shard-apl: NOTRUN -> [SKIP][82] ([fdo#109271]) +40 similar issues
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl2/igt@kms_plane_cursor@pipe-d-overlay-size-64.html
* igt@kms_plane_lowres@pipe-a-tiling-4:
- shard-tglb: NOTRUN -> [SKIP][83] ([i915#5288])
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_plane_lowres@pipe-a-tiling-4.html
* igt@kms_plane_lowres@pipe-b-tiling-y:
- shard-iclb: NOTRUN -> [SKIP][84] ([i915#3536])
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@kms_plane_lowres@pipe-b-tiling-y.html
* igt@kms_plane_multiple@atomic-pipe-d-tiling-x:
- shard-kbl: NOTRUN -> [SKIP][85] ([fdo#109271]) +49 similar issues
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@kms_plane_multiple@atomic-pipe-d-tiling-x.html
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-5@pipe-c-edp-1-downscale-with-pixel-format:
- shard-iclb: [PASS][86] -> [SKIP][87] ([i915#5176]) +4 similar issues
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb1/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-5@pipe-c-edp-1-downscale-with-pixel-format.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb2/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-5@pipe-c-edp-1-downscale-with-pixel-format.html
* igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-c-edp-1-downscale-with-pixel-format:
- shard-iclb: [PASS][88] -> [INCOMPLETE][89] ([i915#5293])
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb6/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-c-edp-1-downscale-with-pixel-format.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb2/igt@kms_plane_scaling@downscale-with-pixel-format-factor-0-75@pipe-c-edp-1-downscale-with-pixel-format.html
* igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale:
- shard-iclb: [PASS][90] -> [SKIP][91] ([i915#5235]) +2 similar issues
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb6/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb2/igt@kms_plane_scaling@planes-upscale-20x20-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-skl: NOTRUN -> [SKIP][92] ([fdo#109271] / [i915#658]) +1 similar issue
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl3/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@frontbuffer-xrgb8888:
- shard-apl: NOTRUN -> [SKIP][93] ([fdo#109271] / [i915#658])
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl4/igt@kms_psr2_su@frontbuffer-xrgb8888.html
- shard-iclb: NOTRUN -> [SKIP][94] ([fdo#109642] / [fdo#111068] / [i915#658])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@kms_psr2_su@frontbuffer-xrgb8888.html
* igt@kms_psr@psr2_primary_mmap_gtt:
- shard-tglb: NOTRUN -> [FAIL][95] ([i915#132] / [i915#3467])
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_psr@psr2_primary_mmap_gtt.html
* igt@kms_psr@psr2_sprite_render:
- shard-iclb: [PASS][96] -> [SKIP][97] ([fdo#109441]) +1 similar issue
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb2/igt@kms_psr@psr2_sprite_render.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb4/igt@kms_psr@psr2_sprite_render.html
* igt@kms_rotation_crc@primary-y-tiled-reflect-x-0:
- shard-snb: NOTRUN -> [SKIP][98] ([fdo#109271]) +76 similar issues
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-snb2/igt@kms_rotation_crc@primary-y-tiled-reflect-x-0.html
* igt@kms_setmode@invalid-clone-single-crtc-stealing:
- shard-iclb: NOTRUN -> [SKIP][99] ([i915#3555])
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@kms_setmode@invalid-clone-single-crtc-stealing.html
* igt@kms_vblank@pipe-d-wait-idle:
- shard-skl: NOTRUN -> [SKIP][100] ([fdo#109271] / [i915#533]) +1 similar issue
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl2/igt@kms_vblank@pipe-d-wait-idle.html
* igt@kms_writeback@writeback-check-output:
- shard-kbl: NOTRUN -> [SKIP][101] ([fdo#109271] / [i915#2437])
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@kms_writeback@writeback-check-output.html
* igt@kms_writeback@writeback-invalid-parameters:
- shard-iclb: NOTRUN -> [SKIP][102] ([i915#2437])
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@kms_writeback@writeback-invalid-parameters.html
* igt@kms_writeback@writeback-pixel-formats:
- shard-tglb: NOTRUN -> [SKIP][103] ([i915#2437])
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@kms_writeback@writeback-pixel-formats.html
* igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame:
- shard-iclb: NOTRUN -> [SKIP][104] ([i915#2530])
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@nouveau_crc@pipe-c-ctx-flip-skip-current-frame.html
* igt@perf@gen12-oa-tlb-invalidate:
- shard-iclb: NOTRUN -> [SKIP][105] ([fdo#109289]) +1 similar issue
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb5/igt@perf@gen12-oa-tlb-invalidate.html
* igt@perf@polling-parameterized:
- shard-skl: [PASS][106] -> [FAIL][107] ([i915#1542])
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-skl9/igt@perf@polling-parameterized.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl7/igt@perf@polling-parameterized.html
* igt@perf_pmu@rc6-suspend:
- shard-kbl: NOTRUN -> [DMESG-WARN][108] ([i915#180])
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl1/igt@perf_pmu@rc6-suspend.html
* igt@prime_nv_api@i915_nv_import_twice:
- shard-iclb: NOTRUN -> [SKIP][109] ([fdo#109291]) +1 similar issue
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@prime_nv_api@i915_nv_import_twice.html
* igt@prime_nv_pcopy@test3_2:
- shard-tglb: NOTRUN -> [SKIP][110] ([fdo#109291])
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@prime_nv_pcopy@test3_2.html
* igt@syncobj_timeline@invalid-transfer-non-existent-point:
- shard-kbl: NOTRUN -> [DMESG-WARN][111] ([i915#5098])
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@syncobj_timeline@invalid-transfer-non-existent-point.html
* igt@sysfs_clients@busy:
- shard-kbl: NOTRUN -> [SKIP][112] ([fdo#109271] / [i915#2994])
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl3/igt@sysfs_clients@busy.html
* igt@sysfs_clients@fair-7:
- shard-iclb: NOTRUN -> [SKIP][113] ([i915#2994])
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb8/igt@sysfs_clients@fair-7.html
* igt@sysfs_clients@sema-10:
- shard-skl: NOTRUN -> [SKIP][114] ([fdo#109271] / [i915#2994]) +2 similar issues
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-skl2/igt@sysfs_clients@sema-10.html
* igt@sysfs_clients@split-25:
- shard-tglb: NOTRUN -> [SKIP][115] ([i915#2994])
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@sysfs_clients@split-25.html
* igt@tools_test@sysfs_l3_parity:
- shard-tglb: NOTRUN -> [SKIP][116] ([fdo#109307])
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglb1/igt@tools_test@sysfs_l3_parity.html
#### Possible fixes ####
* igt@gem_caching@reads:
- shard-glk: [DMESG-WARN][117] ([i915#118]) -> [PASS][118]
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk5/igt@gem_caching@reads.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-glk7/igt@gem_caching@reads.html
* igt@gem_eio@unwedge-stress:
- {shard-tglu}: [TIMEOUT][119] ([i915#3063] / [i915#3648]) -> [PASS][120]
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglu-1/igt@gem_eio@unwedge-stress.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-tglu-1/igt@gem_eio@unwedge-stress.html
* igt@gem_exec_balancer@parallel-balancer:
- shard-iclb: [SKIP][121] ([i915#4525]) -> [PASS][122]
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb5/igt@gem_exec_balancer@parallel-balancer.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb1/igt@gem_exec_balancer@parallel-balancer.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [FAIL][123] ([i915#2846]) -> [PASS][124]
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-kbl1/igt@gem_exec_fair@basic-deadline.html
- shard-glk: [FAIL][125] ([i915#2846]) -> [PASS][126]
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-glk8/igt@gem_exec_fair@basic-deadline.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-glk9/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-iclb: [FAIL][127] ([i915#2842]) -> [PASS][128]
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-iclb8/igt@gem_exec_fair@basic-none-share@rcs0.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-iclb7/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none@vecs0:
- shard-apl: [FAIL][129] ([i915#2842]) -> [PASS][130]
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-apl8/igt@gem_exec_fair@basic-none@vecs0.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/shard-apl8/igt@gem_exec_fair@basic-none@vecs0.html
* igt@i915_selftest@live@gt_pm:
- {shard-tglu}: [DMESG-FAIL][131] ([i915#3987]) -> [PASS][132]
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11416/shard-tglu-3/igt@i915_selftest@live@gt_pm.htm
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22722/index.html
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