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From: Damien Hedde <damien.hedde@greensocs.com>
To: qemu-devel@nongnu.org
Cc: "Damien Hedde" <damien.hedde@greensocs.com>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Alistair Francis" <alistair.francis@wdc.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	qemu-riscv@nongnu.org,
	"Alistair Francis" <alistair@alistair23.me>,
	mark.burton@greensocs.com,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Yanan Wang" <wangyanan55@huawei.com>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	qemu-arm@nongnu.org, "Palmer Dabbelt" <palmer@dabbelt.com>,
	"Vijai Kumar K" <vijai@behindbytes.com>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Alex Bennée" <alex.bennee@linaro.org>
Subject: [RFC PATCH 17/18] hw/riscv/riscv_hart: remove temporary features
Date: Wed, 30 Mar 2022 14:56:38 +0200	[thread overview]
Message-ID: <20220330125639.201937-18-damien.hedde@greensocs.com> (raw)
In-Reply-To: <20220330125639.201937-1-damien.hedde@greensocs.com>

Now that we updated all riscv machines, we can remove
the temporary realize helper and the alias property.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
---
 include/hw/riscv/riscv_hart.h |  3 ---
 hw/riscv/riscv_hart.c         | 14 --------------
 2 files changed, 17 deletions(-)

diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index 65ac0d2bc4..acf5ee8575 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -56,7 +56,4 @@ static inline unsigned riscv_array_get_num_harts(RISCVHartArrayState *s)
     return CPUS(s)->topology.cpus;
 }
 
-/* Temporary function until we migrated the riscv hart array to simple device */
-void riscv_hart_array_realize(RISCVHartArrayState *state, Error **errp);
-
 #endif
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 1b4ff7e3c6..ea798de5d5 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -27,13 +27,6 @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/cpu/cpus.h"
 
-void riscv_hart_array_realize(RISCVHartArrayState *state, Error **errp)
-{
-    /* disable the clustering */
-    cpus_disable_clustering(CPUS(state));
-    qdev_realize(DEVICE(state), NULL, errp);
-}
-
 static Property riscv_harts_props[] = {
     DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
     DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
@@ -52,12 +45,6 @@ static void riscv_harts_configure_cpu(CpusState *base, CPUState *cpu,
     cpuenv->mhartid = s->hartid_base + i;
 }
 
-static void riscv_harts_init(Object *obj)
-{
-    /* add a temporary property to keep num-harts */
-    object_property_add_alias(obj, "num-harts", obj, "num-cpus");
-}
-
 static void riscv_harts_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -73,7 +60,6 @@ static const TypeInfo riscv_harts_info = {
     .name          = TYPE_RISCV_HART_ARRAY,
     .parent        = TYPE_CPUS,
     .instance_size = sizeof(RISCVHartArrayState),
-    .instance_init = riscv_harts_init,
     .class_init    = riscv_harts_class_init,
 };
 
-- 
2.35.1



WARNING: multiple messages have this Message-ID (diff)
From: Damien Hedde <damien.hedde@greensocs.com>
To: qemu-devel@nongnu.org
Cc: mark.burton@greensocs.com,
	"Damien Hedde" <damien.hedde@greensocs.com>,
	"Alex Bennée" <alex.bennee@linaro.org>,
	"Philippe Mathieu-Daudé" <f4bug@amsat.org>,
	"Peter Maydell" <peter.maydell@linaro.org>,
	"Alistair Francis" <alistair@alistair23.me>,
	"Edgar E. Iglesias" <edgar.iglesias@gmail.com>,
	"Eduardo Habkost" <eduardo@habkost.net>,
	"Marcel Apfelbaum" <marcel.apfelbaum@gmail.com>,
	"Yanan Wang" <wangyanan55@huawei.com>,
	"Palmer Dabbelt" <palmer@dabbelt.com>,
	"Bin Meng" <bin.meng@windriver.com>,
	"Vijai Kumar K" <vijai@behindbytes.com>,
	qemu-arm@nongnu.org, qemu-riscv@nongnu.org,
	"Alistair Francis" <alistair.francis@wdc.com>
Subject: [RFC PATCH 17/18] hw/riscv/riscv_hart: remove temporary features
Date: Wed, 30 Mar 2022 14:56:38 +0200	[thread overview]
Message-ID: <20220330125639.201937-18-damien.hedde@greensocs.com> (raw)
In-Reply-To: <20220330125639.201937-1-damien.hedde@greensocs.com>

Now that we updated all riscv machines, we can remove
the temporary realize helper and the alias property.

Signed-off-by: Damien Hedde <damien.hedde@greensocs.com>
---
 include/hw/riscv/riscv_hart.h |  3 ---
 hw/riscv/riscv_hart.c         | 14 --------------
 2 files changed, 17 deletions(-)

diff --git a/include/hw/riscv/riscv_hart.h b/include/hw/riscv/riscv_hart.h
index 65ac0d2bc4..acf5ee8575 100644
--- a/include/hw/riscv/riscv_hart.h
+++ b/include/hw/riscv/riscv_hart.h
@@ -56,7 +56,4 @@ static inline unsigned riscv_array_get_num_harts(RISCVHartArrayState *s)
     return CPUS(s)->topology.cpus;
 }
 
-/* Temporary function until we migrated the riscv hart array to simple device */
-void riscv_hart_array_realize(RISCVHartArrayState *state, Error **errp);
-
 #endif
diff --git a/hw/riscv/riscv_hart.c b/hw/riscv/riscv_hart.c
index 1b4ff7e3c6..ea798de5d5 100644
--- a/hw/riscv/riscv_hart.c
+++ b/hw/riscv/riscv_hart.c
@@ -27,13 +27,6 @@
 #include "hw/riscv/riscv_hart.h"
 #include "hw/cpu/cpus.h"
 
-void riscv_hart_array_realize(RISCVHartArrayState *state, Error **errp)
-{
-    /* disable the clustering */
-    cpus_disable_clustering(CPUS(state));
-    qdev_realize(DEVICE(state), NULL, errp);
-}
-
 static Property riscv_harts_props[] = {
     DEFINE_PROP_UINT32("hartid-base", RISCVHartArrayState, hartid_base, 0),
     DEFINE_PROP_UINT64("resetvec", RISCVHartArrayState, resetvec,
@@ -52,12 +45,6 @@ static void riscv_harts_configure_cpu(CpusState *base, CPUState *cpu,
     cpuenv->mhartid = s->hartid_base + i;
 }
 
-static void riscv_harts_init(Object *obj)
-{
-    /* add a temporary property to keep num-harts */
-    object_property_add_alias(obj, "num-harts", obj, "num-cpus");
-}
-
 static void riscv_harts_class_init(ObjectClass *klass, void *data)
 {
     DeviceClass *dc = DEVICE_CLASS(klass);
@@ -73,7 +60,6 @@ static const TypeInfo riscv_harts_info = {
     .name          = TYPE_RISCV_HART_ARRAY,
     .parent        = TYPE_CPUS,
     .instance_size = sizeof(RISCVHartArrayState),
-    .instance_init = riscv_harts_init,
     .class_init    = riscv_harts_class_init,
 };
 
-- 
2.35.1



  parent reply	other threads:[~2022-03-30 13:51 UTC|newest]

Thread overview: 52+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-03-30 12:56 [RFC PATCH 00/18] user-creatable cpu clusters Damien Hedde
2022-03-30 12:56 ` Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 01/18] define MAX_CLUSTERS in cpu.h instead of cluster.h Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 02/18] hw/cpu/cpus: introduce _cpus_ device Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-04-16 17:52   ` Philippe Mathieu-Daudé
2022-04-16 17:52     ` Philippe Mathieu-Daudé
2022-04-19  9:11     ` Damien Hedde
2022-04-19  9:11       ` Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 03/18] hw/cpu/cpus: prepare to handle cpu clusters Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 04/18] hw/cpu/cluster: make _cpu-cluster_ a subclass of _cpus_ Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 05/18] gdbstub: deal with _cpus_ object instead of _cpu-cluster_ Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 06/18] hw/cpu/cluster: remove cluster_id now that gdbstub is updated Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 07/18] hw/cpu/cpus: add a common start-powered-off property Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 08/18] hw/arm/arm_cpus: add arm_cpus device Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-04-16 18:01   ` Philippe Mathieu-Daudé
2022-04-16 18:01     ` Philippe Mathieu-Daudé
2022-03-30 12:56 ` [RFC PATCH 09/18] hw/arm/xlnx-zynqmp: convert cpu clusters to arm_cpus Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-04-16 18:06   ` Philippe Mathieu-Daudé
2022-04-16 18:06     ` Philippe Mathieu-Daudé
2022-03-30 12:56 ` [RFC PATCH 10/18] hw/riscv/riscv_hart: prepare transition to cpus Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 11/18] hw/riscv: prepare riscv_hart " Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 12/18] hw/riscv/virt: " Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 13/18] hw/riscv/spike: " Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 14/18] hw/riscv/riscv_hart: use cpus as base class Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 15/18] hw/riscv/sifive_u&microchip_pfsoc: apply riscv_hart_array update Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 16/18] hw/riscv: update remaining machines due to " Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-03-30 12:56 ` Damien Hedde [this message]
2022-03-30 12:56   ` [RFC PATCH 17/18] hw/riscv/riscv_hart: remove temporary features Damien Hedde
2022-03-30 12:56 ` [RFC PATCH 18/18] add myself as reviewer of the newly added _cpus_ Damien Hedde
2022-03-30 12:56   ` Damien Hedde
2022-04-15  7:42 ` [RFC PATCH 00/18] user-creatable cpu clusters Damien Hedde
2022-04-15  7:42   ` Damien Hedde
2022-04-21 15:51 ` Peter Maydell
2022-04-21 15:51   ` Peter Maydell
2022-04-21 18:11   ` Damien Hedde
2022-04-21 18:11     ` Damien Hedde

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