* [PATCH 1/2] ARM: dts: aspeed: romed8hm3: Add lm25066 sense resistor values
@ 2022-03-31 2:24 ` Zev Weiss
0 siblings, 0 replies; 15+ messages in thread
From: Zev Weiss @ 2022-03-31 2:24 UTC (permalink / raw)
To: Joel Stanley
Cc: Zev Weiss, openbmc, Rob Herring, Krzysztof Kozlowski,
Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
With this property set the sensor readings from these devices can now
be calibrated properly.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
---
arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
index e71ccfd1df63..572a43e57cac 100644
--- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
@@ -100,12 +100,14 @@ w83773g@4c {
lm25066@40 {
compatible = "lm25066";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <1000>;
};
/* 12VSB PMIC */
lm25066@41 {
compatible = "lm25066";
reg = <0x41>;
+ shunt-resistor-micro-ohms = <10000>;
};
};
--
2.35.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 1/2] ARM: dts: aspeed: romed8hm3: Add lm25066 sense resistor values
@ 2022-03-31 2:24 ` Zev Weiss
0 siblings, 0 replies; 15+ messages in thread
From: Zev Weiss @ 2022-03-31 2:24 UTC (permalink / raw)
To: Joel Stanley
Cc: devicetree, linux-aspeed, Zev Weiss, Andrew Jeffery, openbmc,
linux-kernel, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel
With this property set the sensor readings from these devices can now
be calibrated properly.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
---
arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
index e71ccfd1df63..572a43e57cac 100644
--- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
@@ -100,12 +100,14 @@ w83773g@4c {
lm25066@40 {
compatible = "lm25066";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <1000>;
};
/* 12VSB PMIC */
lm25066@41 {
compatible = "lm25066";
reg = <0x41>;
+ shunt-resistor-micro-ohms = <10000>;
};
};
--
2.35.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 1/2] ARM: dts: aspeed: romed8hm3: Add lm25066 sense resistor values
@ 2022-03-31 2:24 ` Zev Weiss
0 siblings, 0 replies; 15+ messages in thread
From: Zev Weiss @ 2022-03-31 2:24 UTC (permalink / raw)
To: Joel Stanley
Cc: Zev Weiss, openbmc, Rob Herring, Krzysztof Kozlowski,
Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
With this property set the sensor readings from these devices can now
be calibrated properly.
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
---
arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 ++
1 file changed, 2 insertions(+)
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
index e71ccfd1df63..572a43e57cac 100644
--- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
@@ -100,12 +100,14 @@ w83773g@4c {
lm25066@40 {
compatible = "lm25066";
reg = <0x40>;
+ shunt-resistor-micro-ohms = <1000>;
};
/* 12VSB PMIC */
lm25066@41 {
compatible = "lm25066";
reg = <0x41>;
+ shunt-resistor-micro-ohms = <10000>;
};
};
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/2] ARM: dts: aspeed: romed8hm3: Fix GPIOB0 name
2022-03-31 2:24 ` Zev Weiss
(?)
@ 2022-03-31 2:24 ` Zev Weiss
-1 siblings, 0 replies; 15+ messages in thread
From: Zev Weiss @ 2022-03-31 2:24 UTC (permalink / raw)
To: Joel Stanley
Cc: Zev Weiss, openbmc, Rob Herring, Krzysztof Kozlowski,
Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
This GPIO was mislabeled as DDR_MEM_TEMP in the schematic; after a
correction from ASRock Rack its name now reflects its actual
functionality (POST_COMPLETE_N).
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
---
arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
index 572a43e57cac..ff4c07c69af1 100644
--- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
@@ -198,7 +198,7 @@ &gpio {
gpio-line-names =
/* A */ "LOCATORLED_STATUS_N", "BMC_MAC2_INTB", "NMI_BTN_N", "BMC_NMI",
"", "", "", "",
- /* B */ "DDR_MEM_TEMP", "", "", "", "", "", "", "",
+ /* B */ "POST_COMPLETE_N", "", "", "", "", "", "", "",
/* C */ "", "", "", "", "PCIE_HP_SEL_N", "PCIE_SATA_SEL_N", "LOCATORBTN", "",
/* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON",
"", "", "", "PSU_FAN_FAIL_N",
--
2.35.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/2] ARM: dts: aspeed: romed8hm3: Fix GPIOB0 name
@ 2022-03-31 2:24 ` Zev Weiss
0 siblings, 0 replies; 15+ messages in thread
From: Zev Weiss @ 2022-03-31 2:24 UTC (permalink / raw)
To: Joel Stanley
Cc: devicetree, linux-aspeed, Zev Weiss, Andrew Jeffery, openbmc,
linux-kernel, Rob Herring, Krzysztof Kozlowski, linux-arm-kernel
This GPIO was mislabeled as DDR_MEM_TEMP in the schematic; after a
correction from ASRock Rack its name now reflects its actual
functionality (POST_COMPLETE_N).
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
---
arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
index 572a43e57cac..ff4c07c69af1 100644
--- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
@@ -198,7 +198,7 @@ &gpio {
gpio-line-names =
/* A */ "LOCATORLED_STATUS_N", "BMC_MAC2_INTB", "NMI_BTN_N", "BMC_NMI",
"", "", "", "",
- /* B */ "DDR_MEM_TEMP", "", "", "", "", "", "", "",
+ /* B */ "POST_COMPLETE_N", "", "", "", "", "", "", "",
/* C */ "", "", "", "", "PCIE_HP_SEL_N", "PCIE_SATA_SEL_N", "LOCATORBTN", "",
/* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON",
"", "", "", "PSU_FAN_FAIL_N",
--
2.35.1
^ permalink raw reply related [flat|nested] 15+ messages in thread
* [PATCH 2/2] ARM: dts: aspeed: romed8hm3: Fix GPIOB0 name
@ 2022-03-31 2:24 ` Zev Weiss
0 siblings, 0 replies; 15+ messages in thread
From: Zev Weiss @ 2022-03-31 2:24 UTC (permalink / raw)
To: Joel Stanley
Cc: Zev Weiss, openbmc, Rob Herring, Krzysztof Kozlowski,
Andrew Jeffery, devicetree, linux-arm-kernel, linux-aspeed,
linux-kernel
This GPIO was mislabeled as DDR_MEM_TEMP in the schematic; after a
correction from ASRock Rack its name now reflects its actual
functionality (POST_COMPLETE_N).
Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
---
arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
index 572a43e57cac..ff4c07c69af1 100644
--- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
+++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
@@ -198,7 +198,7 @@ &gpio {
gpio-line-names =
/* A */ "LOCATORLED_STATUS_N", "BMC_MAC2_INTB", "NMI_BTN_N", "BMC_NMI",
"", "", "", "",
- /* B */ "DDR_MEM_TEMP", "", "", "", "", "", "", "",
+ /* B */ "POST_COMPLETE_N", "", "", "", "", "", "", "",
/* C */ "", "", "", "", "PCIE_HP_SEL_N", "PCIE_SATA_SEL_N", "LOCATORBTN", "",
/* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON",
"", "", "", "PSU_FAN_FAIL_N",
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] ARM: dts: aspeed: romed8hm3: Add lm25066 sense resistor values
2022-03-31 2:24 ` Zev Weiss
(?)
@ 2022-03-31 5:35 ` Joel Stanley
-1 siblings, 0 replies; 15+ messages in thread
From: Joel Stanley @ 2022-03-31 5:35 UTC (permalink / raw)
To: Zev Weiss
Cc: OpenBMC Maillist, Rob Herring, Krzysztof Kozlowski,
Andrew Jeffery, devicetree, Linux ARM, linux-aspeed,
Linux Kernel Mailing List
On Thu, 31 Mar 2022 at 02:24, Zev Weiss <zev@bewilderbeest.net> wrote:
>
> With this property set the sensor readings from these devices can now
> be calibrated properly.
>
> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
I guess:
Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
Reviewed-by: Joel Stanley <joel@jms.id.au>
I'll send some fixes in after -rc1.
> ---
> arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> index e71ccfd1df63..572a43e57cac 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> @@ -100,12 +100,14 @@ w83773g@4c {
> lm25066@40 {
> compatible = "lm25066";
> reg = <0x40>;
> + shunt-resistor-micro-ohms = <1000>;
> };
>
> /* 12VSB PMIC */
> lm25066@41 {
> compatible = "lm25066";
> reg = <0x41>;
> + shunt-resistor-micro-ohms = <10000>;
> };
> };
>
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] ARM: dts: aspeed: romed8hm3: Add lm25066 sense resistor values
@ 2022-03-31 5:35 ` Joel Stanley
0 siblings, 0 replies; 15+ messages in thread
From: Joel Stanley @ 2022-03-31 5:35 UTC (permalink / raw)
To: Zev Weiss
Cc: devicetree, linux-aspeed, Andrew Jeffery, OpenBMC Maillist,
Linux Kernel Mailing List, Rob Herring, Krzysztof Kozlowski,
Linux ARM
On Thu, 31 Mar 2022 at 02:24, Zev Weiss <zev@bewilderbeest.net> wrote:
>
> With this property set the sensor readings from these devices can now
> be calibrated properly.
>
> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
I guess:
Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
Reviewed-by: Joel Stanley <joel@jms.id.au>
I'll send some fixes in after -rc1.
> ---
> arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> index e71ccfd1df63..572a43e57cac 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> @@ -100,12 +100,14 @@ w83773g@4c {
> lm25066@40 {
> compatible = "lm25066";
> reg = <0x40>;
> + shunt-resistor-micro-ohms = <1000>;
> };
>
> /* 12VSB PMIC */
> lm25066@41 {
> compatible = "lm25066";
> reg = <0x41>;
> + shunt-resistor-micro-ohms = <10000>;
> };
> };
>
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 1/2] ARM: dts: aspeed: romed8hm3: Add lm25066 sense resistor values
@ 2022-03-31 5:35 ` Joel Stanley
0 siblings, 0 replies; 15+ messages in thread
From: Joel Stanley @ 2022-03-31 5:35 UTC (permalink / raw)
To: Zev Weiss
Cc: OpenBMC Maillist, Rob Herring, Krzysztof Kozlowski,
Andrew Jeffery, devicetree, Linux ARM, linux-aspeed,
Linux Kernel Mailing List
On Thu, 31 Mar 2022 at 02:24, Zev Weiss <zev@bewilderbeest.net> wrote:
>
> With this property set the sensor readings from these devices can now
> be calibrated properly.
>
> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
I guess:
Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
Reviewed-by: Joel Stanley <joel@jms.id.au>
I'll send some fixes in after -rc1.
> ---
> arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 ++
> 1 file changed, 2 insertions(+)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> index e71ccfd1df63..572a43e57cac 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> @@ -100,12 +100,14 @@ w83773g@4c {
> lm25066@40 {
> compatible = "lm25066";
> reg = <0x40>;
> + shunt-resistor-micro-ohms = <1000>;
> };
>
> /* 12VSB PMIC */
> lm25066@41 {
> compatible = "lm25066";
> reg = <0x41>;
> + shunt-resistor-micro-ohms = <10000>;
> };
> };
>
> --
> 2.35.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: romed8hm3: Fix GPIOB0 name
2022-03-31 2:24 ` Zev Weiss
(?)
@ 2022-03-31 5:35 ` Joel Stanley
-1 siblings, 0 replies; 15+ messages in thread
From: Joel Stanley @ 2022-03-31 5:35 UTC (permalink / raw)
To: Zev Weiss
Cc: OpenBMC Maillist, Rob Herring, Krzysztof Kozlowski,
Andrew Jeffery, devicetree, Linux ARM, linux-aspeed,
Linux Kernel Mailing List
On Thu, 31 Mar 2022 at 02:24, Zev Weiss <zev@bewilderbeest.net> wrote:
>
> This GPIO was mislabeled as DDR_MEM_TEMP in the schematic; after a
> correction from ASRock Rack its name now reflects its actual
> functionality (POST_COMPLETE_N).
Those are quite different functions :)
>
> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
Reviewed-by: Joel Stanley <joel@jms.id.au>
I'll send some fixes in after -rc1.
> ---
> arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> index 572a43e57cac..ff4c07c69af1 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> @@ -198,7 +198,7 @@ &gpio {
> gpio-line-names =
> /* A */ "LOCATORLED_STATUS_N", "BMC_MAC2_INTB", "NMI_BTN_N", "BMC_NMI",
> "", "", "", "",
> - /* B */ "DDR_MEM_TEMP", "", "", "", "", "", "", "",
> + /* B */ "POST_COMPLETE_N", "", "", "", "", "", "", "",
> /* C */ "", "", "", "", "PCIE_HP_SEL_N", "PCIE_SATA_SEL_N", "LOCATORBTN", "",
> /* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON",
> "", "", "", "PSU_FAN_FAIL_N",
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: romed8hm3: Fix GPIOB0 name
@ 2022-03-31 5:35 ` Joel Stanley
0 siblings, 0 replies; 15+ messages in thread
From: Joel Stanley @ 2022-03-31 5:35 UTC (permalink / raw)
To: Zev Weiss
Cc: devicetree, linux-aspeed, Andrew Jeffery, OpenBMC Maillist,
Linux Kernel Mailing List, Rob Herring, Krzysztof Kozlowski,
Linux ARM
On Thu, 31 Mar 2022 at 02:24, Zev Weiss <zev@bewilderbeest.net> wrote:
>
> This GPIO was mislabeled as DDR_MEM_TEMP in the schematic; after a
> correction from ASRock Rack its name now reflects its actual
> functionality (POST_COMPLETE_N).
Those are quite different functions :)
>
> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
Reviewed-by: Joel Stanley <joel@jms.id.au>
I'll send some fixes in after -rc1.
> ---
> arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> index 572a43e57cac..ff4c07c69af1 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> @@ -198,7 +198,7 @@ &gpio {
> gpio-line-names =
> /* A */ "LOCATORLED_STATUS_N", "BMC_MAC2_INTB", "NMI_BTN_N", "BMC_NMI",
> "", "", "", "",
> - /* B */ "DDR_MEM_TEMP", "", "", "", "", "", "", "",
> + /* B */ "POST_COMPLETE_N", "", "", "", "", "", "", "",
> /* C */ "", "", "", "", "PCIE_HP_SEL_N", "PCIE_SATA_SEL_N", "LOCATORBTN", "",
> /* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON",
> "", "", "", "PSU_FAN_FAIL_N",
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: romed8hm3: Fix GPIOB0 name
@ 2022-03-31 5:35 ` Joel Stanley
0 siblings, 0 replies; 15+ messages in thread
From: Joel Stanley @ 2022-03-31 5:35 UTC (permalink / raw)
To: Zev Weiss
Cc: OpenBMC Maillist, Rob Herring, Krzysztof Kozlowski,
Andrew Jeffery, devicetree, Linux ARM, linux-aspeed,
Linux Kernel Mailing List
On Thu, 31 Mar 2022 at 02:24, Zev Weiss <zev@bewilderbeest.net> wrote:
>
> This GPIO was mislabeled as DDR_MEM_TEMP in the schematic; after a
> correction from ASRock Rack its name now reflects its actual
> functionality (POST_COMPLETE_N).
Those are quite different functions :)
>
> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
Reviewed-by: Joel Stanley <joel@jms.id.au>
I'll send some fixes in after -rc1.
> ---
> arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts | 2 +-
> 1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> index 572a43e57cac..ff4c07c69af1 100644
> --- a/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> +++ b/arch/arm/boot/dts/aspeed-bmc-asrock-romed8hm3.dts
> @@ -198,7 +198,7 @@ &gpio {
> gpio-line-names =
> /* A */ "LOCATORLED_STATUS_N", "BMC_MAC2_INTB", "NMI_BTN_N", "BMC_NMI",
> "", "", "", "",
> - /* B */ "DDR_MEM_TEMP", "", "", "", "", "", "", "",
> + /* B */ "POST_COMPLETE_N", "", "", "", "", "", "", "",
> /* C */ "", "", "", "", "PCIE_HP_SEL_N", "PCIE_SATA_SEL_N", "LOCATORBTN", "",
> /* D */ "BMC_PSIN", "BMC_PSOUT", "BMC_RESETCON", "RESETCON",
> "", "", "", "PSU_FAN_FAIL_N",
> --
> 2.35.1
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
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^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: romed8hm3: Fix GPIOB0 name
2022-03-31 5:35 ` Joel Stanley
(?)
@ 2022-03-31 6:08 ` Zev Weiss
-1 siblings, 0 replies; 15+ messages in thread
From: Zev Weiss @ 2022-03-31 6:08 UTC (permalink / raw)
To: Joel Stanley
Cc: Zev Weiss, devicetree, linux-aspeed, Andrew Jeffery,
OpenBMC Maillist, Linux Kernel Mailing List, Rob Herring,
Krzysztof Kozlowski, Linux ARM
On Wed, Mar 30, 2022 at 10:35:47PM PDT, Joel Stanley wrote:
>On Thu, 31 Mar 2022 at 02:24, Zev Weiss <zev@bewilderbeest.net> wrote:
>>
>> This GPIO was mislabeled as DDR_MEM_TEMP in the schematic; after a
>> correction from ASRock Rack its name now reflects its actual
>> functionality (POST_COMPLETE_N).
>
>Those are quite different functions :)
>
Yes, rather -- that little tidbit resolved quite a bit of
head-scratching that had been going on...
>>
>> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
>
>Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
Ah yes, I'll try to remember to include those to start with.
>Reviewed-by: Joel Stanley <joel@jms.id.au>
>
>I'll send some fixes in after -rc1.
>
Thanks!
Zev
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: romed8hm3: Fix GPIOB0 name
@ 2022-03-31 6:08 ` Zev Weiss
0 siblings, 0 replies; 15+ messages in thread
From: Zev Weiss @ 2022-03-31 6:08 UTC (permalink / raw)
To: Joel Stanley
Cc: devicetree, Zev Weiss, linux-aspeed, Andrew Jeffery,
OpenBMC Maillist, Linux Kernel Mailing List, Rob Herring,
Krzysztof Kozlowski, Linux ARM
On Wed, Mar 30, 2022 at 10:35:47PM PDT, Joel Stanley wrote:
>On Thu, 31 Mar 2022 at 02:24, Zev Weiss <zev@bewilderbeest.net> wrote:
>>
>> This GPIO was mislabeled as DDR_MEM_TEMP in the schematic; after a
>> correction from ASRock Rack its name now reflects its actual
>> functionality (POST_COMPLETE_N).
>
>Those are quite different functions :)
>
Yes, rather -- that little tidbit resolved quite a bit of
head-scratching that had been going on...
>>
>> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
>
>Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
Ah yes, I'll try to remember to include those to start with.
>Reviewed-by: Joel Stanley <joel@jms.id.au>
>
>I'll send some fixes in after -rc1.
>
Thanks!
Zev
^ permalink raw reply [flat|nested] 15+ messages in thread
* Re: [PATCH 2/2] ARM: dts: aspeed: romed8hm3: Fix GPIOB0 name
@ 2022-03-31 6:08 ` Zev Weiss
0 siblings, 0 replies; 15+ messages in thread
From: Zev Weiss @ 2022-03-31 6:08 UTC (permalink / raw)
To: Joel Stanley
Cc: Zev Weiss, devicetree, linux-aspeed, Andrew Jeffery,
OpenBMC Maillist, Linux Kernel Mailing List, Rob Herring,
Krzysztof Kozlowski, Linux ARM
On Wed, Mar 30, 2022 at 10:35:47PM PDT, Joel Stanley wrote:
>On Thu, 31 Mar 2022 at 02:24, Zev Weiss <zev@bewilderbeest.net> wrote:
>>
>> This GPIO was mislabeled as DDR_MEM_TEMP in the schematic; after a
>> correction from ASRock Rack its name now reflects its actual
>> functionality (POST_COMPLETE_N).
>
>Those are quite different functions :)
>
Yes, rather -- that little tidbit resolved quite a bit of
head-scratching that had been going on...
>>
>> Signed-off-by: Zev Weiss <zev@bewilderbeest.net>
>
>Fixes: a9a3d60b937a ("ARM: dts: aspeed: Add ASRock ROMED8HM3 BMC")
Ah yes, I'll try to remember to include those to start with.
>Reviewed-by: Joel Stanley <joel@jms.id.au>
>
>I'll send some fixes in after -rc1.
>
Thanks!
Zev
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^ permalink raw reply [flat|nested] 15+ messages in thread
end of thread, other threads:[~2022-03-31 6:10 UTC | newest]
Thread overview: 15+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-31 2:24 [PATCH 1/2] ARM: dts: aspeed: romed8hm3: Add lm25066 sense resistor values Zev Weiss
2022-03-31 2:24 ` Zev Weiss
2022-03-31 2:24 ` Zev Weiss
2022-03-31 2:24 ` [PATCH 2/2] ARM: dts: aspeed: romed8hm3: Fix GPIOB0 name Zev Weiss
2022-03-31 2:24 ` Zev Weiss
2022-03-31 2:24 ` Zev Weiss
2022-03-31 5:35 ` Joel Stanley
2022-03-31 5:35 ` Joel Stanley
2022-03-31 5:35 ` Joel Stanley
2022-03-31 6:08 ` Zev Weiss
2022-03-31 6:08 ` Zev Weiss
2022-03-31 6:08 ` Zev Weiss
2022-03-31 5:35 ` [PATCH 1/2] ARM: dts: aspeed: romed8hm3: Add lm25066 sense resistor values Joel Stanley
2022-03-31 5:35 ` Joel Stanley
2022-03-31 5:35 ` Joel Stanley
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