* [PATCH v1 0/2] hw/arm: zynqmp: Add the 4 TTC timers
@ 2022-03-31 22:20 Edgar E. Iglesias
2022-03-31 22:20 ` [PATCH v1 1/2] timer: cadence_ttc: Break out header file to allow embedding Edgar E. Iglesias
` (2 more replies)
0 siblings, 3 replies; 10+ messages in thread
From: Edgar E. Iglesias @ 2022-03-31 22:20 UTC (permalink / raw)
To: qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, asifsiddiqui120,
edgar.iglesias, sai.pavan.boddu, frasse.iglesias, alistair,
richard.henderson, f4bug, francisco.iglesias, frederic.konrad,
qemu-arm
From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
This adds the 4 TTC timers in the Xilinx ZynqMP.
This is for after the 7.0.0 release.
Cheers,
Edgar
Edgar E. Iglesias (2):
timer: cadence_ttc: Break out header file to allow embedding
hw/arm/xlnx-zynqmp: Connect 4 TTC timers
include/hw/arm/xlnx-zynqmp.h | 4 +++
include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++
hw/arm/xlnx-zynqmp.c | 22 ++++++++++++++
hw/timer/cadence_ttc.c | 32 ++------------------
4 files changed, 82 insertions(+), 30 deletions(-)
create mode 100644 include/hw/timer/cadence_ttc.h
--
2.25.1
^ permalink raw reply [flat|nested] 10+ messages in thread
* [PATCH v1 1/2] timer: cadence_ttc: Break out header file to allow embedding
2022-03-31 22:20 [PATCH v1 0/2] hw/arm: zynqmp: Add the 4 TTC timers Edgar E. Iglesias
@ 2022-03-31 22:20 ` Edgar E. Iglesias
2022-04-01 5:00 ` Alistair Francis
` (2 more replies)
2022-03-31 22:20 ` [PATCH v1 2/2] hw/arm/xlnx-zynqmp: Connect 4 TTC timers Edgar E. Iglesias
2022-04-11 10:45 ` [PATCH v1 0/2] hw/arm: zynqmp: Add the " Peter Maydell
2 siblings, 3 replies; 10+ messages in thread
From: Edgar E. Iglesias @ 2022-03-31 22:20 UTC (permalink / raw)
To: qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, asifsiddiqui120,
edgar.iglesias, sai.pavan.boddu, frasse.iglesias, alistair,
richard.henderson, f4bug, francisco.iglesias, frederic.konrad,
qemu-arm
From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
Break out header file to allow embedding of the the TTC.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
---
include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++
hw/timer/cadence_ttc.c | 32 ++------------------
2 files changed, 56 insertions(+), 30 deletions(-)
create mode 100644 include/hw/timer/cadence_ttc.h
diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h
new file mode 100644
index 0000000000..e1251383f2
--- /dev/null
+++ b/include/hw/timer/cadence_ttc.h
@@ -0,0 +1,54 @@
+/*
+ * Xilinx Zynq cadence TTC model
+ *
+ * Copyright (c) 2011 Xilinx Inc.
+ * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
+ * Copyright (c) 2012 PetaLogix Pty Ltd.
+ * Written By Haibing Ma
+ * M. Habib
+ *
+ * This program is free software; you can redistribute it and/or
+ * modify it under the terms of the GNU General Public License
+ * as published by the Free Software Foundation; either version
+ * 2 of the License, or (at your option) any later version.
+ *
+ * You should have received a copy of the GNU General Public License along
+ * with this program; if not, see <http://www.gnu.org/licenses/>.
+ */
+#ifndef HW_TIMER_CADENCE_TTC_H
+#define HW_TIMER_CADENCE_TTC_H
+
+#include "hw/sysbus.h"
+#include "qemu/timer.h"
+
+typedef struct {
+ QEMUTimer *timer;
+ int freq;
+
+ uint32_t reg_clock;
+ uint32_t reg_count;
+ uint32_t reg_value;
+ uint16_t reg_interval;
+ uint16_t reg_match[3];
+ uint32_t reg_intr;
+ uint32_t reg_intr_en;
+ uint32_t reg_event_ctrl;
+ uint32_t reg_event;
+
+ uint64_t cpu_time;
+ unsigned int cpu_time_valid;
+
+ qemu_irq irq;
+} CadenceTimerState;
+
+#define TYPE_CADENCE_TTC "cadence_ttc"
+OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
+
+struct CadenceTTCState {
+ SysBusDevice parent_obj;
+
+ MemoryRegion iomem;
+ CadenceTimerState timer[3];
+};
+
+#endif
diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c
index 64108241ba..e57a0f5f09 100644
--- a/hw/timer/cadence_ttc.c
+++ b/hw/timer/cadence_ttc.c
@@ -24,6 +24,8 @@
#include "qemu/timer.h"
#include "qom/object.h"
+#include "hw/timer/cadence_ttc.h"
+
#ifdef CADENCE_TTC_ERR_DEBUG
#define DB_PRINT(...) do { \
fprintf(stderr, ": %s: ", __func__); \
@@ -49,36 +51,6 @@
#define CLOCK_CTRL_PS_EN 0x00000001
#define CLOCK_CTRL_PS_V 0x0000001e
-typedef struct {
- QEMUTimer *timer;
- int freq;
-
- uint32_t reg_clock;
- uint32_t reg_count;
- uint32_t reg_value;
- uint16_t reg_interval;
- uint16_t reg_match[3];
- uint32_t reg_intr;
- uint32_t reg_intr_en;
- uint32_t reg_event_ctrl;
- uint32_t reg_event;
-
- uint64_t cpu_time;
- unsigned int cpu_time_valid;
-
- qemu_irq irq;
-} CadenceTimerState;
-
-#define TYPE_CADENCE_TTC "cadence_ttc"
-OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
-
-struct CadenceTTCState {
- SysBusDevice parent_obj;
-
- MemoryRegion iomem;
- CadenceTimerState timer[3];
-};
-
static void cadence_timer_update(CadenceTimerState *s)
{
qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* [PATCH v1 2/2] hw/arm/xlnx-zynqmp: Connect 4 TTC timers
2022-03-31 22:20 [PATCH v1 0/2] hw/arm: zynqmp: Add the 4 TTC timers Edgar E. Iglesias
2022-03-31 22:20 ` [PATCH v1 1/2] timer: cadence_ttc: Break out header file to allow embedding Edgar E. Iglesias
@ 2022-03-31 22:20 ` Edgar E. Iglesias
2022-04-01 5:04 ` Alistair Francis
` (2 more replies)
2022-04-11 10:45 ` [PATCH v1 0/2] hw/arm: zynqmp: Add the " Peter Maydell
2 siblings, 3 replies; 10+ messages in thread
From: Edgar E. Iglesias @ 2022-03-31 22:20 UTC (permalink / raw)
To: qemu-devel
Cc: edgar.iglesias, peter.maydell, luc, asifsiddiqui120,
edgar.iglesias, sai.pavan.boddu, frasse.iglesias, alistair,
richard.henderson, f4bug, francisco.iglesias, frederic.konrad,
qemu-arm
From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
Connect the 4 TTC timers on the ZynqMP.
Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
---
include/hw/arm/xlnx-zynqmp.h | 4 ++++
hw/arm/xlnx-zynqmp.c | 22 ++++++++++++++++++++++
2 files changed, 26 insertions(+)
diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
index 9d9a9d0bf9..85fd9f53da 100644
--- a/include/hw/arm/xlnx-zynqmp.h
+++ b/include/hw/arm/xlnx-zynqmp.h
@@ -41,6 +41,7 @@
#include "hw/or-irq.h"
#include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
#include "hw/misc/xlnx-zynqmp-crf.h"
+#include "hw/timer/cadence_ttc.h"
#define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
@@ -84,6 +85,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
#define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
+#define XLNX_ZYNQMP_NUM_TTC 4
+
/*
* Unimplemented mmio regions needed to boot some images.
*/
@@ -128,6 +131,7 @@ struct XlnxZynqMPState {
qemu_or_irq qspi_irq_orgate;
XlnxZynqMPAPUCtrl apu_ctrl;
XlnxZynqMPCRF crf;
+ CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
char *boot_cpu;
ARMCPU *boot_cpu_ptr;
diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
index 5bfe285a19..375309e68e 100644
--- a/hw/arm/xlnx-zynqmp.c
+++ b/hw/arm/xlnx-zynqmp.c
@@ -68,6 +68,9 @@
#define APU_ADDR 0xfd5c0000
#define APU_IRQ 153
+#define TTC0_ADDR 0xFF110000
+#define TTC0_IRQ 36
+
#define IPI_ADDR 0xFF300000
#define IPI_IRQ 64
@@ -316,6 +319,24 @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
}
+static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic)
+{
+ SysBusDevice *sbd;
+ int i, irq;
+
+ for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) {
+ object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i],
+ TYPE_CADENCE_TTC);
+ sbd = SYS_BUS_DEVICE(&s->ttc[i]);
+
+ sysbus_realize(sbd, &error_fatal);
+ sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000);
+ for (irq = 0; irq < 3; irq++) {
+ sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]);
+ }
+ }
+}
+
static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
{
static const struct UnimpInfo {
@@ -721,6 +742,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
xlnx_zynqmp_create_efuse(s, gic_spi);
xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
xlnx_zynqmp_create_crf(s, gic_spi);
+ xlnx_zynqmp_create_ttc(s, gic_spi);
xlnx_zynqmp_create_unimp_mmio(s);
for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
--
2.25.1
^ permalink raw reply related [flat|nested] 10+ messages in thread
* Re: [PATCH v1 1/2] timer: cadence_ttc: Break out header file to allow embedding
2022-03-31 22:20 ` [PATCH v1 1/2] timer: cadence_ttc: Break out header file to allow embedding Edgar E. Iglesias
@ 2022-04-01 5:00 ` Alistair Francis
2022-04-01 7:11 ` Luc Michel
2022-04-01 8:11 ` Francisco Iglesias
2 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2022-04-01 5:00 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: Edgar Iglesias, Peter Maydell, Luc Michel, asifsiddiqui120,
edgar.iglesias, Sai Pavan Boddu, Francisco Iglesias,
Alistair Francis, Richard Henderson,
qemu-devel@nongnu.org Developers, Philippe Mathieu-Daudé,
Francisco Iglesias, KONRAD Frederic, qemu-arm
On Fri, Apr 1, 2022 at 8:24 AM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
>
> Break out header file to allow embedding of the the TTC.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++
> hw/timer/cadence_ttc.c | 32 ++------------------
> 2 files changed, 56 insertions(+), 30 deletions(-)
> create mode 100644 include/hw/timer/cadence_ttc.h
>
> diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h
> new file mode 100644
> index 0000000000..e1251383f2
> --- /dev/null
> +++ b/include/hw/timer/cadence_ttc.h
> @@ -0,0 +1,54 @@
> +/*
> + * Xilinx Zynq cadence TTC model
> + *
> + * Copyright (c) 2011 Xilinx Inc.
> + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
> + * Copyright (c) 2012 PetaLogix Pty Ltd.
> + * Written By Haibing Ma
> + * M. Habib
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef HW_TIMER_CADENCE_TTC_H
> +#define HW_TIMER_CADENCE_TTC_H
> +
> +#include "hw/sysbus.h"
> +#include "qemu/timer.h"
> +
> +typedef struct {
> + QEMUTimer *timer;
> + int freq;
> +
> + uint32_t reg_clock;
> + uint32_t reg_count;
> + uint32_t reg_value;
> + uint16_t reg_interval;
> + uint16_t reg_match[3];
> + uint32_t reg_intr;
> + uint32_t reg_intr_en;
> + uint32_t reg_event_ctrl;
> + uint32_t reg_event;
> +
> + uint64_t cpu_time;
> + unsigned int cpu_time_valid;
> +
> + qemu_irq irq;
> +} CadenceTimerState;
> +
> +#define TYPE_CADENCE_TTC "cadence_ttc"
> +OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
> +
> +struct CadenceTTCState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> + CadenceTimerState timer[3];
> +};
> +
> +#endif
> diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c
> index 64108241ba..e57a0f5f09 100644
> --- a/hw/timer/cadence_ttc.c
> +++ b/hw/timer/cadence_ttc.c
> @@ -24,6 +24,8 @@
> #include "qemu/timer.h"
> #include "qom/object.h"
>
> +#include "hw/timer/cadence_ttc.h"
> +
> #ifdef CADENCE_TTC_ERR_DEBUG
> #define DB_PRINT(...) do { \
> fprintf(stderr, ": %s: ", __func__); \
> @@ -49,36 +51,6 @@
> #define CLOCK_CTRL_PS_EN 0x00000001
> #define CLOCK_CTRL_PS_V 0x0000001e
>
> -typedef struct {
> - QEMUTimer *timer;
> - int freq;
> -
> - uint32_t reg_clock;
> - uint32_t reg_count;
> - uint32_t reg_value;
> - uint16_t reg_interval;
> - uint16_t reg_match[3];
> - uint32_t reg_intr;
> - uint32_t reg_intr_en;
> - uint32_t reg_event_ctrl;
> - uint32_t reg_event;
> -
> - uint64_t cpu_time;
> - unsigned int cpu_time_valid;
> -
> - qemu_irq irq;
> -} CadenceTimerState;
> -
> -#define TYPE_CADENCE_TTC "cadence_ttc"
> -OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
> -
> -struct CadenceTTCState {
> - SysBusDevice parent_obj;
> -
> - MemoryRegion iomem;
> - CadenceTimerState timer[3];
> -};
> -
> static void cadence_timer_update(CadenceTimerState *s)
> {
> qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 2/2] hw/arm/xlnx-zynqmp: Connect 4 TTC timers
2022-03-31 22:20 ` [PATCH v1 2/2] hw/arm/xlnx-zynqmp: Connect 4 TTC timers Edgar E. Iglesias
@ 2022-04-01 5:04 ` Alistair Francis
2022-04-01 7:11 ` Luc Michel
2022-04-01 8:12 ` Francisco Iglesias
2 siblings, 0 replies; 10+ messages in thread
From: Alistair Francis @ 2022-04-01 5:04 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: Edgar Iglesias, Peter Maydell, Luc Michel, asifsiddiqui120,
edgar.iglesias, Sai Pavan Boddu, Francisco Iglesias,
Alistair Francis, Richard Henderson,
qemu-devel@nongnu.org Developers, Philippe Mathieu-Daudé,
Francisco Iglesias, KONRAD Frederic, qemu-arm
On Fri, Apr 1, 2022 at 8:26 AM Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
>
> Connect the 4 TTC timers on the ZynqMP.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
Alistair
> ---
> include/hw/arm/xlnx-zynqmp.h | 4 ++++
> hw/arm/xlnx-zynqmp.c | 22 ++++++++++++++++++++++
> 2 files changed, 26 insertions(+)
>
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index 9d9a9d0bf9..85fd9f53da 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -41,6 +41,7 @@
> #include "hw/or-irq.h"
> #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
> #include "hw/misc/xlnx-zynqmp-crf.h"
> +#include "hw/timer/cadence_ttc.h"
>
> #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
> OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
> @@ -84,6 +85,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
> #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
> XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
>
> +#define XLNX_ZYNQMP_NUM_TTC 4
> +
> /*
> * Unimplemented mmio regions needed to boot some images.
> */
> @@ -128,6 +131,7 @@ struct XlnxZynqMPState {
> qemu_or_irq qspi_irq_orgate;
> XlnxZynqMPAPUCtrl apu_ctrl;
> XlnxZynqMPCRF crf;
> + CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
>
> char *boot_cpu;
> ARMCPU *boot_cpu_ptr;
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index 5bfe285a19..375309e68e 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -68,6 +68,9 @@
> #define APU_ADDR 0xfd5c0000
> #define APU_IRQ 153
>
> +#define TTC0_ADDR 0xFF110000
> +#define TTC0_IRQ 36
> +
> #define IPI_ADDR 0xFF300000
> #define IPI_IRQ 64
>
> @@ -316,6 +319,24 @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
> sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
> }
>
> +static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic)
> +{
> + SysBusDevice *sbd;
> + int i, irq;
> +
> + for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) {
> + object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i],
> + TYPE_CADENCE_TTC);
> + sbd = SYS_BUS_DEVICE(&s->ttc[i]);
> +
> + sysbus_realize(sbd, &error_fatal);
> + sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000);
> + for (irq = 0; irq < 3; irq++) {
> + sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]);
> + }
> + }
> +}
> +
> static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
> {
> static const struct UnimpInfo {
> @@ -721,6 +742,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> xlnx_zynqmp_create_efuse(s, gic_spi);
> xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
> xlnx_zynqmp_create_crf(s, gic_spi);
> + xlnx_zynqmp_create_ttc(s, gic_spi);
> xlnx_zynqmp_create_unimp_mmio(s);
>
> for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 1/2] timer: cadence_ttc: Break out header file to allow embedding
2022-03-31 22:20 ` [PATCH v1 1/2] timer: cadence_ttc: Break out header file to allow embedding Edgar E. Iglesias
2022-04-01 5:00 ` Alistair Francis
@ 2022-04-01 7:11 ` Luc Michel
2022-04-01 8:11 ` Francisco Iglesias
2 siblings, 0 replies; 10+ messages in thread
From: Luc Michel @ 2022-04-01 7:11 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: edgar.iglesias, peter.maydell, asifsiddiqui120, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
qemu-devel, f4bug, francisco.iglesias, frederic.konrad, qemu-arm
On 00:20 Fri 01 Apr , Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
>
> Break out header file to allow embedding of the the TTC.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++
> hw/timer/cadence_ttc.c | 32 ++------------------
> 2 files changed, 56 insertions(+), 30 deletions(-)
> create mode 100644 include/hw/timer/cadence_ttc.h
>
> diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h
> new file mode 100644
> index 0000000000..e1251383f2
> --- /dev/null
> +++ b/include/hw/timer/cadence_ttc.h
> @@ -0,0 +1,54 @@
> +/*
> + * Xilinx Zynq cadence TTC model
> + *
> + * Copyright (c) 2011 Xilinx Inc.
> + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
> + * Copyright (c) 2012 PetaLogix Pty Ltd.
> + * Written By Haibing Ma
> + * M. Habib
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef HW_TIMER_CADENCE_TTC_H
> +#define HW_TIMER_CADENCE_TTC_H
> +
> +#include "hw/sysbus.h"
> +#include "qemu/timer.h"
> +
> +typedef struct {
> + QEMUTimer *timer;
> + int freq;
> +
> + uint32_t reg_clock;
> + uint32_t reg_count;
> + uint32_t reg_value;
> + uint16_t reg_interval;
> + uint16_t reg_match[3];
> + uint32_t reg_intr;
> + uint32_t reg_intr_en;
> + uint32_t reg_event_ctrl;
> + uint32_t reg_event;
> +
> + uint64_t cpu_time;
> + unsigned int cpu_time_valid;
> +
> + qemu_irq irq;
> +} CadenceTimerState;
> +
> +#define TYPE_CADENCE_TTC "cadence_ttc"
> +OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
> +
> +struct CadenceTTCState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> + CadenceTimerState timer[3];
> +};
> +
> +#endif
> diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c
> index 64108241ba..e57a0f5f09 100644
> --- a/hw/timer/cadence_ttc.c
> +++ b/hw/timer/cadence_ttc.c
> @@ -24,6 +24,8 @@
> #include "qemu/timer.h"
> #include "qom/object.h"
>
> +#include "hw/timer/cadence_ttc.h"
> +
> #ifdef CADENCE_TTC_ERR_DEBUG
> #define DB_PRINT(...) do { \
> fprintf(stderr, ": %s: ", __func__); \
> @@ -49,36 +51,6 @@
> #define CLOCK_CTRL_PS_EN 0x00000001
> #define CLOCK_CTRL_PS_V 0x0000001e
>
> -typedef struct {
> - QEMUTimer *timer;
> - int freq;
> -
> - uint32_t reg_clock;
> - uint32_t reg_count;
> - uint32_t reg_value;
> - uint16_t reg_interval;
> - uint16_t reg_match[3];
> - uint32_t reg_intr;
> - uint32_t reg_intr_en;
> - uint32_t reg_event_ctrl;
> - uint32_t reg_event;
> -
> - uint64_t cpu_time;
> - unsigned int cpu_time_valid;
> -
> - qemu_irq irq;
> -} CadenceTimerState;
> -
> -#define TYPE_CADENCE_TTC "cadence_ttc"
> -OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
> -
> -struct CadenceTTCState {
> - SysBusDevice parent_obj;
> -
> - MemoryRegion iomem;
> - CadenceTimerState timer[3];
> -};
> -
> static void cadence_timer_update(CadenceTimerState *s)
> {
> qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
> --
> 2.25.1
>
--
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 2/2] hw/arm/xlnx-zynqmp: Connect 4 TTC timers
2022-03-31 22:20 ` [PATCH v1 2/2] hw/arm/xlnx-zynqmp: Connect 4 TTC timers Edgar E. Iglesias
2022-04-01 5:04 ` Alistair Francis
@ 2022-04-01 7:11 ` Luc Michel
2022-04-01 8:12 ` Francisco Iglesias
2 siblings, 0 replies; 10+ messages in thread
From: Luc Michel @ 2022-04-01 7:11 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: edgar.iglesias, peter.maydell, asifsiddiqui120, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
qemu-devel, f4bug, francisco.iglesias, frederic.konrad, qemu-arm
On 00:20 Fri 01 Apr , Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
>
> Connect the 4 TTC timers on the ZynqMP.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Luc Michel <luc@lmichel.fr>
> ---
> include/hw/arm/xlnx-zynqmp.h | 4 ++++
> hw/arm/xlnx-zynqmp.c | 22 ++++++++++++++++++++++
> 2 files changed, 26 insertions(+)
>
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index 9d9a9d0bf9..85fd9f53da 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -41,6 +41,7 @@
> #include "hw/or-irq.h"
> #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
> #include "hw/misc/xlnx-zynqmp-crf.h"
> +#include "hw/timer/cadence_ttc.h"
>
> #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
> OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
> @@ -84,6 +85,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
> #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
> XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
>
> +#define XLNX_ZYNQMP_NUM_TTC 4
> +
> /*
> * Unimplemented mmio regions needed to boot some images.
> */
> @@ -128,6 +131,7 @@ struct XlnxZynqMPState {
> qemu_or_irq qspi_irq_orgate;
> XlnxZynqMPAPUCtrl apu_ctrl;
> XlnxZynqMPCRF crf;
> + CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
>
> char *boot_cpu;
> ARMCPU *boot_cpu_ptr;
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index 5bfe285a19..375309e68e 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -68,6 +68,9 @@
> #define APU_ADDR 0xfd5c0000
> #define APU_IRQ 153
>
> +#define TTC0_ADDR 0xFF110000
> +#define TTC0_IRQ 36
> +
> #define IPI_ADDR 0xFF300000
> #define IPI_IRQ 64
>
> @@ -316,6 +319,24 @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
> sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
> }
>
> +static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic)
> +{
> + SysBusDevice *sbd;
> + int i, irq;
> +
> + for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) {
> + object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i],
> + TYPE_CADENCE_TTC);
> + sbd = SYS_BUS_DEVICE(&s->ttc[i]);
> +
> + sysbus_realize(sbd, &error_fatal);
> + sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000);
> + for (irq = 0; irq < 3; irq++) {
> + sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]);
> + }
> + }
> +}
> +
> static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
> {
> static const struct UnimpInfo {
> @@ -721,6 +742,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> xlnx_zynqmp_create_efuse(s, gic_spi);
> xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
> xlnx_zynqmp_create_crf(s, gic_spi);
> + xlnx_zynqmp_create_ttc(s, gic_spi);
> xlnx_zynqmp_create_unimp_mmio(s);
>
> for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
> --
> 2.25.1
>
--
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 1/2] timer: cadence_ttc: Break out header file to allow embedding
2022-03-31 22:20 ` [PATCH v1 1/2] timer: cadence_ttc: Break out header file to allow embedding Edgar E. Iglesias
2022-04-01 5:00 ` Alistair Francis
2022-04-01 7:11 ` Luc Michel
@ 2022-04-01 8:11 ` Francisco Iglesias
2 siblings, 0 replies; 10+ messages in thread
From: Francisco Iglesias @ 2022-04-01 8:11 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: edgar.iglesias, peter.maydell, luc, asifsiddiqui120,
edgar.iglesias, sai.pavan.boddu, alistair, richard.henderson,
qemu-devel, f4bug, francisco.iglesias, frederic.konrad, qemu-arm
On [2022 Apr 01] Fri 00:20:16, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
>
> Break out header file to allow embedding of the the TTC.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
> ---
> include/hw/timer/cadence_ttc.h | 54 ++++++++++++++++++++++++++++++++++
> hw/timer/cadence_ttc.c | 32 ++------------------
> 2 files changed, 56 insertions(+), 30 deletions(-)
> create mode 100644 include/hw/timer/cadence_ttc.h
>
> diff --git a/include/hw/timer/cadence_ttc.h b/include/hw/timer/cadence_ttc.h
> new file mode 100644
> index 0000000000..e1251383f2
> --- /dev/null
> +++ b/include/hw/timer/cadence_ttc.h
> @@ -0,0 +1,54 @@
> +/*
> + * Xilinx Zynq cadence TTC model
> + *
> + * Copyright (c) 2011 Xilinx Inc.
> + * Copyright (c) 2012 Peter A.G. Crosthwaite (peter.crosthwaite@petalogix.com)
> + * Copyright (c) 2012 PetaLogix Pty Ltd.
> + * Written By Haibing Ma
> + * M. Habib
> + *
> + * This program is free software; you can redistribute it and/or
> + * modify it under the terms of the GNU General Public License
> + * as published by the Free Software Foundation; either version
> + * 2 of the License, or (at your option) any later version.
> + *
> + * You should have received a copy of the GNU General Public License along
> + * with this program; if not, see <http://www.gnu.org/licenses/>.
> + */
> +#ifndef HW_TIMER_CADENCE_TTC_H
> +#define HW_TIMER_CADENCE_TTC_H
> +
> +#include "hw/sysbus.h"
> +#include "qemu/timer.h"
> +
> +typedef struct {
> + QEMUTimer *timer;
> + int freq;
> +
> + uint32_t reg_clock;
> + uint32_t reg_count;
> + uint32_t reg_value;
> + uint16_t reg_interval;
> + uint16_t reg_match[3];
> + uint32_t reg_intr;
> + uint32_t reg_intr_en;
> + uint32_t reg_event_ctrl;
> + uint32_t reg_event;
> +
> + uint64_t cpu_time;
> + unsigned int cpu_time_valid;
> +
> + qemu_irq irq;
> +} CadenceTimerState;
> +
> +#define TYPE_CADENCE_TTC "cadence_ttc"
> +OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
> +
> +struct CadenceTTCState {
> + SysBusDevice parent_obj;
> +
> + MemoryRegion iomem;
> + CadenceTimerState timer[3];
> +};
> +
> +#endif
> diff --git a/hw/timer/cadence_ttc.c b/hw/timer/cadence_ttc.c
> index 64108241ba..e57a0f5f09 100644
> --- a/hw/timer/cadence_ttc.c
> +++ b/hw/timer/cadence_ttc.c
> @@ -24,6 +24,8 @@
> #include "qemu/timer.h"
> #include "qom/object.h"
>
> +#include "hw/timer/cadence_ttc.h"
> +
> #ifdef CADENCE_TTC_ERR_DEBUG
> #define DB_PRINT(...) do { \
> fprintf(stderr, ": %s: ", __func__); \
> @@ -49,36 +51,6 @@
> #define CLOCK_CTRL_PS_EN 0x00000001
> #define CLOCK_CTRL_PS_V 0x0000001e
>
> -typedef struct {
> - QEMUTimer *timer;
> - int freq;
> -
> - uint32_t reg_clock;
> - uint32_t reg_count;
> - uint32_t reg_value;
> - uint16_t reg_interval;
> - uint16_t reg_match[3];
> - uint32_t reg_intr;
> - uint32_t reg_intr_en;
> - uint32_t reg_event_ctrl;
> - uint32_t reg_event;
> -
> - uint64_t cpu_time;
> - unsigned int cpu_time_valid;
> -
> - qemu_irq irq;
> -} CadenceTimerState;
> -
> -#define TYPE_CADENCE_TTC "cadence_ttc"
> -OBJECT_DECLARE_SIMPLE_TYPE(CadenceTTCState, CADENCE_TTC)
> -
> -struct CadenceTTCState {
> - SysBusDevice parent_obj;
> -
> - MemoryRegion iomem;
> - CadenceTimerState timer[3];
> -};
> -
> static void cadence_timer_update(CadenceTimerState *s)
> {
> qemu_set_irq(s->irq, !!(s->reg_intr & s->reg_intr_en));
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 2/2] hw/arm/xlnx-zynqmp: Connect 4 TTC timers
2022-03-31 22:20 ` [PATCH v1 2/2] hw/arm/xlnx-zynqmp: Connect 4 TTC timers Edgar E. Iglesias
2022-04-01 5:04 ` Alistair Francis
2022-04-01 7:11 ` Luc Michel
@ 2022-04-01 8:12 ` Francisco Iglesias
2 siblings, 0 replies; 10+ messages in thread
From: Francisco Iglesias @ 2022-04-01 8:12 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: edgar.iglesias, peter.maydell, luc, asifsiddiqui120,
edgar.iglesias, sai.pavan.boddu, alistair, richard.henderson,
qemu-devel, f4bug, francisco.iglesias, frederic.konrad, qemu-arm
On [2022 Apr 01] Fri 00:20:17, Edgar E. Iglesias wrote:
> From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
>
> Connect the 4 TTC timers on the ZynqMP.
>
> Signed-off-by: Edgar E. Iglesias <edgar.iglesias@amd.com>
Reviewed-by: Francisco Iglesias <frasse.iglesias@gmail.com>
> ---
> include/hw/arm/xlnx-zynqmp.h | 4 ++++
> hw/arm/xlnx-zynqmp.c | 22 ++++++++++++++++++++++
> 2 files changed, 26 insertions(+)
>
> diff --git a/include/hw/arm/xlnx-zynqmp.h b/include/hw/arm/xlnx-zynqmp.h
> index 9d9a9d0bf9..85fd9f53da 100644
> --- a/include/hw/arm/xlnx-zynqmp.h
> +++ b/include/hw/arm/xlnx-zynqmp.h
> @@ -41,6 +41,7 @@
> #include "hw/or-irq.h"
> #include "hw/misc/xlnx-zynqmp-apu-ctrl.h"
> #include "hw/misc/xlnx-zynqmp-crf.h"
> +#include "hw/timer/cadence_ttc.h"
>
> #define TYPE_XLNX_ZYNQMP "xlnx-zynqmp"
> OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
> @@ -84,6 +85,8 @@ OBJECT_DECLARE_SIMPLE_TYPE(XlnxZynqMPState, XLNX_ZYNQMP)
> #define XLNX_ZYNQMP_MAX_RAM_SIZE (XLNX_ZYNQMP_MAX_LOW_RAM_SIZE + \
> XLNX_ZYNQMP_MAX_HIGH_RAM_SIZE)
>
> +#define XLNX_ZYNQMP_NUM_TTC 4
> +
> /*
> * Unimplemented mmio regions needed to boot some images.
> */
> @@ -128,6 +131,7 @@ struct XlnxZynqMPState {
> qemu_or_irq qspi_irq_orgate;
> XlnxZynqMPAPUCtrl apu_ctrl;
> XlnxZynqMPCRF crf;
> + CadenceTTCState ttc[XLNX_ZYNQMP_NUM_TTC];
>
> char *boot_cpu;
> ARMCPU *boot_cpu_ptr;
> diff --git a/hw/arm/xlnx-zynqmp.c b/hw/arm/xlnx-zynqmp.c
> index 5bfe285a19..375309e68e 100644
> --- a/hw/arm/xlnx-zynqmp.c
> +++ b/hw/arm/xlnx-zynqmp.c
> @@ -68,6 +68,9 @@
> #define APU_ADDR 0xfd5c0000
> #define APU_IRQ 153
>
> +#define TTC0_ADDR 0xFF110000
> +#define TTC0_IRQ 36
> +
> #define IPI_ADDR 0xFF300000
> #define IPI_IRQ 64
>
> @@ -316,6 +319,24 @@ static void xlnx_zynqmp_create_crf(XlnxZynqMPState *s, qemu_irq *gic)
> sysbus_connect_irq(sbd, 0, gic[CRF_IRQ]);
> }
>
> +static void xlnx_zynqmp_create_ttc(XlnxZynqMPState *s, qemu_irq *gic)
> +{
> + SysBusDevice *sbd;
> + int i, irq;
> +
> + for (i = 0; i < XLNX_ZYNQMP_NUM_TTC; i++) {
> + object_initialize_child(OBJECT(s), "ttc[*]", &s->ttc[i],
> + TYPE_CADENCE_TTC);
> + sbd = SYS_BUS_DEVICE(&s->ttc[i]);
> +
> + sysbus_realize(sbd, &error_fatal);
> + sysbus_mmio_map(sbd, 0, TTC0_ADDR + i * 0x10000);
> + for (irq = 0; irq < 3; irq++) {
> + sysbus_connect_irq(sbd, irq, gic[TTC0_IRQ + i * 3 + irq]);
> + }
> + }
> +}
> +
> static void xlnx_zynqmp_create_unimp_mmio(XlnxZynqMPState *s)
> {
> static const struct UnimpInfo {
> @@ -721,6 +742,7 @@ static void xlnx_zynqmp_realize(DeviceState *dev, Error **errp)
> xlnx_zynqmp_create_efuse(s, gic_spi);
> xlnx_zynqmp_create_apu_ctrl(s, gic_spi);
> xlnx_zynqmp_create_crf(s, gic_spi);
> + xlnx_zynqmp_create_ttc(s, gic_spi);
> xlnx_zynqmp_create_unimp_mmio(s);
>
> for (i = 0; i < XLNX_ZYNQMP_NUM_GDMA_CH; i++) {
> --
> 2.25.1
>
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: [PATCH v1 0/2] hw/arm: zynqmp: Add the 4 TTC timers
2022-03-31 22:20 [PATCH v1 0/2] hw/arm: zynqmp: Add the 4 TTC timers Edgar E. Iglesias
2022-03-31 22:20 ` [PATCH v1 1/2] timer: cadence_ttc: Break out header file to allow embedding Edgar E. Iglesias
2022-03-31 22:20 ` [PATCH v1 2/2] hw/arm/xlnx-zynqmp: Connect 4 TTC timers Edgar E. Iglesias
@ 2022-04-11 10:45 ` Peter Maydell
2 siblings, 0 replies; 10+ messages in thread
From: Peter Maydell @ 2022-04-11 10:45 UTC (permalink / raw)
To: Edgar E. Iglesias
Cc: edgar.iglesias, luc, asifsiddiqui120, edgar.iglesias,
sai.pavan.boddu, frasse.iglesias, alistair, richard.henderson,
qemu-devel, f4bug, francisco.iglesias, frederic.konrad, qemu-arm
On Thu, 31 Mar 2022 at 23:20, Edgar E. Iglesias
<edgar.iglesias@gmail.com> wrote:
>
> From: "Edgar E. Iglesias" <edgar.iglesias@amd.com>
>
> This adds the 4 TTC timers in the Xilinx ZynqMP.
> This is for after the 7.0.0 release.
>
> Cheers,
> Edgar
>
> Edgar E. Iglesias (2):
> timer: cadence_ttc: Break out header file to allow embedding
> hw/arm/xlnx-zynqmp: Connect 4 TTC timers
Applied to target-arm.next for 7.1, thanks.
-- PMM
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2022-04-11 10:47 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-03-31 22:20 [PATCH v1 0/2] hw/arm: zynqmp: Add the 4 TTC timers Edgar E. Iglesias
2022-03-31 22:20 ` [PATCH v1 1/2] timer: cadence_ttc: Break out header file to allow embedding Edgar E. Iglesias
2022-04-01 5:00 ` Alistair Francis
2022-04-01 7:11 ` Luc Michel
2022-04-01 8:11 ` Francisco Iglesias
2022-03-31 22:20 ` [PATCH v1 2/2] hw/arm/xlnx-zynqmp: Connect 4 TTC timers Edgar E. Iglesias
2022-04-01 5:04 ` Alistair Francis
2022-04-01 7:11 ` Luc Michel
2022-04-01 8:12 ` Francisco Iglesias
2022-04-11 10:45 ` [PATCH v1 0/2] hw/arm: zynqmp: Add the " Peter Maydell
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