* [PATCH v3] dt-bindings: Fix phandle-array issues in the idle-states bindings
@ 2022-04-01 21:26 ` Palmer Dabbelt
0 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2022-04-01 21:26 UTC (permalink / raw)
To: Rob Herring
Cc: robh+dt, Paul Walmsley, Palmer Dabbelt, aou, anup, guoren, krzk,
lorenzo.pieralisi, devicetree, linux-kernel, linux-riscv,
Palmer Dabbelt
From: Palmer Dabbelt <palmer@rivosinc.com>
As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the
phandle-array bindings have been disambiguated. This fixes the new
RISC-V idle-states bindings to comply with the schema.
Fixes: 1bd524f7e8d8 ("dt-bindings: Add common bindings for ARM and RISC-V idle states")
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
Changes since v2:
* Add the missing schema requirement to riscv/cpus.yaml
Changes since v1:
* Only fix the RISC-V bindings, to avoid a merge conflict.
---
.../devicetree/bindings/cpu/idle-states.yaml | 16 ++++++++--------
.../devicetree/bindings/riscv/cpus.yaml | 2 ++
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/cpu/idle-states.yaml b/Documentation/devicetree/bindings/cpu/idle-states.yaml
index 95506ffb816c..0e89c469d0fc 100644
--- a/Documentation/devicetree/bindings/cpu/idle-states.yaml
+++ b/Documentation/devicetree/bindings/cpu/idle-states.yaml
@@ -719,8 +719,8 @@ examples:
reg = <0x0>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
- cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
- &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
+ cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
+ <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
cpu_intc0: interrupt-controller {
#interrupt-cells = <1>;
@@ -735,8 +735,8 @@ examples:
reg = <0x1>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
- cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
- &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
+ cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
+ <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
cpu_intc1: interrupt-controller {
#interrupt-cells = <1>;
@@ -751,8 +751,8 @@ examples:
reg = <0x10>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
- cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
- &CLUSTER_RET_1 &CLUSTER_NONRET_1>;
+ cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
+ <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
cpu_intc10: interrupt-controller {
#interrupt-cells = <1>;
@@ -767,8 +767,8 @@ examples:
reg = <0x11>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
- cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
- &CLUSTER_RET_1 &CLUSTER_NONRET_1>;
+ cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
+ <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
cpu_intc11: interrupt-controller {
#interrupt-cells = <1>;
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index f62f646bc695..d632ac76532e 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -101,6 +101,8 @@ properties:
cpu-idle-states:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
+ items:
+ maxItems: 1
description: |
List of phandles to idle state nodes supported
by this hart (see ./idle-states.yaml).
--
2.34.1
^ permalink raw reply related [flat|nested] 6+ messages in thread
* [PATCH v3] dt-bindings: Fix phandle-array issues in the idle-states bindings
@ 2022-04-01 21:26 ` Palmer Dabbelt
0 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2022-04-01 21:26 UTC (permalink / raw)
To: Rob Herring
Cc: robh+dt, Paul Walmsley, Palmer Dabbelt, aou, anup, guoren, krzk,
lorenzo.pieralisi, devicetree, linux-kernel, linux-riscv,
Palmer Dabbelt
From: Palmer Dabbelt <palmer@rivosinc.com>
As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the
phandle-array bindings have been disambiguated. This fixes the new
RISC-V idle-states bindings to comply with the schema.
Fixes: 1bd524f7e8d8 ("dt-bindings: Add common bindings for ARM and RISC-V idle states")
Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
---
Changes since v2:
* Add the missing schema requirement to riscv/cpus.yaml
Changes since v1:
* Only fix the RISC-V bindings, to avoid a merge conflict.
---
.../devicetree/bindings/cpu/idle-states.yaml | 16 ++++++++--------
.../devicetree/bindings/riscv/cpus.yaml | 2 ++
2 files changed, 10 insertions(+), 8 deletions(-)
diff --git a/Documentation/devicetree/bindings/cpu/idle-states.yaml b/Documentation/devicetree/bindings/cpu/idle-states.yaml
index 95506ffb816c..0e89c469d0fc 100644
--- a/Documentation/devicetree/bindings/cpu/idle-states.yaml
+++ b/Documentation/devicetree/bindings/cpu/idle-states.yaml
@@ -719,8 +719,8 @@ examples:
reg = <0x0>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
- cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
- &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
+ cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
+ <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
cpu_intc0: interrupt-controller {
#interrupt-cells = <1>;
@@ -735,8 +735,8 @@ examples:
reg = <0x1>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
- cpu-idle-states = <&CPU_RET_0_0 &CPU_NONRET_0_0
- &CLUSTER_RET_0 &CLUSTER_NONRET_0>;
+ cpu-idle-states = <&CPU_RET_0_0>, <&CPU_NONRET_0_0>,
+ <&CLUSTER_RET_0>, <&CLUSTER_NONRET_0>;
cpu_intc1: interrupt-controller {
#interrupt-cells = <1>;
@@ -751,8 +751,8 @@ examples:
reg = <0x10>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
- cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
- &CLUSTER_RET_1 &CLUSTER_NONRET_1>;
+ cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
+ <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
cpu_intc10: interrupt-controller {
#interrupt-cells = <1>;
@@ -767,8 +767,8 @@ examples:
reg = <0x11>;
riscv,isa = "rv64imafdc";
mmu-type = "riscv,sv48";
- cpu-idle-states = <&CPU_RET_1_0 &CPU_NONRET_1_0
- &CLUSTER_RET_1 &CLUSTER_NONRET_1>;
+ cpu-idle-states = <&CPU_RET_1_0>, <&CPU_NONRET_1_0>,
+ <&CLUSTER_RET_1>, <&CLUSTER_NONRET_1>;
cpu_intc11: interrupt-controller {
#interrupt-cells = <1>;
diff --git a/Documentation/devicetree/bindings/riscv/cpus.yaml b/Documentation/devicetree/bindings/riscv/cpus.yaml
index f62f646bc695..d632ac76532e 100644
--- a/Documentation/devicetree/bindings/riscv/cpus.yaml
+++ b/Documentation/devicetree/bindings/riscv/cpus.yaml
@@ -101,6 +101,8 @@ properties:
cpu-idle-states:
$ref: '/schemas/types.yaml#/definitions/phandle-array'
+ items:
+ maxItems: 1
description: |
List of phandles to idle state nodes supported
by this hart (see ./idle-states.yaml).
--
2.34.1
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply related [flat|nested] 6+ messages in thread
* Re: [PATCH v3] dt-bindings: Fix phandle-array issues in the idle-states bindings
2022-04-01 21:26 ` Palmer Dabbelt
@ 2022-04-01 21:39 ` Rob Herring
-1 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2022-04-01 21:39 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Anup Patel, Guo Ren,
Krzysztof Kozlowski, Lorenzo Pieralisi, devicetree, linux-kernel,
linux-riscv
On Fri, Apr 1, 2022 at 4:36 PM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> From: Palmer Dabbelt <palmer@rivosinc.com>
>
> As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the
> phandle-array bindings have been disambiguated. This fixes the new
> RISC-V idle-states bindings to comply with the schema.
>
> Fixes: 1bd524f7e8d8 ("dt-bindings: Add common bindings for ARM and RISC-V idle states")
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> Changes since v2:
>
> * Add the missing schema requirement to riscv/cpus.yaml
>
> Changes since v1:
>
> * Only fix the RISC-V bindings, to avoid a merge conflict.
>
> ---
> .../devicetree/bindings/cpu/idle-states.yaml | 16 ++++++++--------
> .../devicetree/bindings/riscv/cpus.yaml | 2 ++
> 2 files changed, 10 insertions(+), 8 deletions(-)
Reviewed-by: Rob Herring <robh@kernel.org>
Thanks for fixing quickly.
Rob
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3] dt-bindings: Fix phandle-array issues in the idle-states bindings
@ 2022-04-01 21:39 ` Rob Herring
0 siblings, 0 replies; 6+ messages in thread
From: Rob Herring @ 2022-04-01 21:39 UTC (permalink / raw)
To: Palmer Dabbelt
Cc: Paul Walmsley, Palmer Dabbelt, Albert Ou, Anup Patel, Guo Ren,
Krzysztof Kozlowski, Lorenzo Pieralisi, devicetree, linux-kernel,
linux-riscv
On Fri, Apr 1, 2022 at 4:36 PM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>
> From: Palmer Dabbelt <palmer@rivosinc.com>
>
> As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the
> phandle-array bindings have been disambiguated. This fixes the new
> RISC-V idle-states bindings to comply with the schema.
>
> Fixes: 1bd524f7e8d8 ("dt-bindings: Add common bindings for ARM and RISC-V idle states")
> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
> ---
> Changes since v2:
>
> * Add the missing schema requirement to riscv/cpus.yaml
>
> Changes since v1:
>
> * Only fix the RISC-V bindings, to avoid a merge conflict.
>
> ---
> .../devicetree/bindings/cpu/idle-states.yaml | 16 ++++++++--------
> .../devicetree/bindings/riscv/cpus.yaml | 2 ++
> 2 files changed, 10 insertions(+), 8 deletions(-)
Reviewed-by: Rob Herring <robh@kernel.org>
Thanks for fixing quickly.
Rob
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3] dt-bindings: Fix phandle-array issues in the idle-states bindings
2022-04-01 21:39 ` Rob Herring
@ 2022-04-01 22:26 ` Palmer Dabbelt
-1 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2022-04-01 22:26 UTC (permalink / raw)
To: Rob Herring
Cc: Paul Walmsley, aou, anup, guoren, krzk, lorenzo.pieralisi,
devicetree, linux-kernel, linux-riscv
On Fri, 01 Apr 2022 14:39:24 PDT (-0700), Rob Herring wrote:
> On Fri, Apr 1, 2022 at 4:36 PM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>>
>> From: Palmer Dabbelt <palmer@rivosinc.com>
>>
>> As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the
>> phandle-array bindings have been disambiguated. This fixes the new
>> RISC-V idle-states bindings to comply with the schema.
>>
>> Fixes: 1bd524f7e8d8 ("dt-bindings: Add common bindings for ARM and RISC-V idle states")
>> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
>> ---
>> Changes since v2:
>>
>> * Add the missing schema requirement to riscv/cpus.yaml
>>
>> Changes since v1:
>>
>> * Only fix the RISC-V bindings, to avoid a merge conflict.
>>
>> ---
>> .../devicetree/bindings/cpu/idle-states.yaml | 16 ++++++++--------
>> .../devicetree/bindings/riscv/cpus.yaml | 2 ++
>> 2 files changed, 10 insertions(+), 8 deletions(-)
>
> Reviewed-by: Rob Herring <robh@kernel.org>
>
> Thanks for fixing quickly.
Well, sorry for breaking it. I've got the DT checks running locally
now, we've got a handful of errors in RISC-V land. I'll clean those up
and then get something blocking my merges, so stuff like this is less
likely to happen.
Looks like Linus just merged my Part 2, I'll send along the Part 3 just
containing this as a fix.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: [PATCH v3] dt-bindings: Fix phandle-array issues in the idle-states bindings
@ 2022-04-01 22:26 ` Palmer Dabbelt
0 siblings, 0 replies; 6+ messages in thread
From: Palmer Dabbelt @ 2022-04-01 22:26 UTC (permalink / raw)
To: Rob Herring
Cc: Paul Walmsley, aou, anup, guoren, krzk, lorenzo.pieralisi,
devicetree, linux-kernel, linux-riscv
On Fri, 01 Apr 2022 14:39:24 PDT (-0700), Rob Herring wrote:
> On Fri, Apr 1, 2022 at 4:36 PM Palmer Dabbelt <palmer@rivosinc.com> wrote:
>>
>> From: Palmer Dabbelt <palmer@rivosinc.com>
>>
>> As per 39bd2b6a3783 ("dt-bindings: Improve phandle-array schemas"), the
>> phandle-array bindings have been disambiguated. This fixes the new
>> RISC-V idle-states bindings to comply with the schema.
>>
>> Fixes: 1bd524f7e8d8 ("dt-bindings: Add common bindings for ARM and RISC-V idle states")
>> Signed-off-by: Palmer Dabbelt <palmer@rivosinc.com>
>> ---
>> Changes since v2:
>>
>> * Add the missing schema requirement to riscv/cpus.yaml
>>
>> Changes since v1:
>>
>> * Only fix the RISC-V bindings, to avoid a merge conflict.
>>
>> ---
>> .../devicetree/bindings/cpu/idle-states.yaml | 16 ++++++++--------
>> .../devicetree/bindings/riscv/cpus.yaml | 2 ++
>> 2 files changed, 10 insertions(+), 8 deletions(-)
>
> Reviewed-by: Rob Herring <robh@kernel.org>
>
> Thanks for fixing quickly.
Well, sorry for breaking it. I've got the DT checks running locally
now, we've got a handful of errors in RISC-V land. I'll clean those up
and then get something blocking my merges, so stuff like this is less
likely to happen.
Looks like Linus just merged my Part 2, I'll send along the Part 3 just
containing this as a fix.
_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv
^ permalink raw reply [flat|nested] 6+ messages in thread
end of thread, other threads:[~2022-04-01 22:26 UTC | newest]
Thread overview: 6+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-01 21:26 [PATCH v3] dt-bindings: Fix phandle-array issues in the idle-states bindings Palmer Dabbelt
2022-04-01 21:26 ` Palmer Dabbelt
2022-04-01 21:39 ` Rob Herring
2022-04-01 21:39 ` Rob Herring
2022-04-01 22:26 ` Palmer Dabbelt
2022-04-01 22:26 ` Palmer Dabbelt
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.