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* [PATCH] ARM: imx: Enable instruction cache early on on i.MX8M
@ 2022-04-03 21:24 Marek Vasut
  2022-04-12 10:27 ` Stefano Babic
  0 siblings, 1 reply; 2+ messages in thread
From: Marek Vasut @ 2022-04-03 21:24 UTC (permalink / raw)
  To: u-boot; +Cc: Marek Vasut, Fabio Estevam, Peng Fan, Stefano Babic

Enable instruction cache early on to speed up the boot process on i.MX8M.

Signed-off-by: Marek Vasut <marex@denx.de>
Cc: Fabio Estevam <festevam@gmail.com>
Cc: Peng Fan <peng.fan@nxp.com>
Cc: Stefano Babic <sbabic@denx.de>
---
 arch/arm/mach-imx/imx8m/soc.c | 3 +++
 1 file changed, 3 insertions(+)

diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
index a41afc5b4f8..6fd4377f1c2 100644
--- a/arch/arm/mach-imx/imx8m/soc.c
+++ b/arch/arm/mach-imx/imx8m/soc.c
@@ -514,6 +514,9 @@ int arch_cpu_init_dm(void)
 int arch_cpu_init(void)
 {
 	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
+
+	icache_enable();
+
 	/*
 	 * ROM might disable clock for SCTR,
 	 * enable the clock before timer_init.
-- 
2.35.1


^ permalink raw reply related	[flat|nested] 2+ messages in thread

* Re: [PATCH] ARM: imx: Enable instruction cache early on on i.MX8M
  2022-04-03 21:24 [PATCH] ARM: imx: Enable instruction cache early on on i.MX8M Marek Vasut
@ 2022-04-12 10:27 ` Stefano Babic
  0 siblings, 0 replies; 2+ messages in thread
From: Stefano Babic @ 2022-04-12 10:27 UTC (permalink / raw)
  To: Marek Vasut, u-boot; +Cc: Fabio Estevam, Peng Fan, Stefano Babic

Hi Marek,

On 03.04.22 23:24, Marek Vasut wrote:
> Enable instruction cache early on to speed up the boot process on i.MX8M.
> 
> Signed-off-by: Marek Vasut <marex@denx.de>
> Cc: Fabio Estevam <festevam@gmail.com>
> Cc: Peng Fan <peng.fan@nxp.com>
> Cc: Stefano Babic <sbabic@denx.de>
> ---
>   arch/arm/mach-imx/imx8m/soc.c | 3 +++
>   1 file changed, 3 insertions(+)
> 
> diff --git a/arch/arm/mach-imx/imx8m/soc.c b/arch/arm/mach-imx/imx8m/soc.c
> index a41afc5b4f8..6fd4377f1c2 100644
> --- a/arch/arm/mach-imx/imx8m/soc.c
> +++ b/arch/arm/mach-imx/imx8m/soc.c
> @@ -514,6 +514,9 @@ int arch_cpu_init_dm(void)
>   int arch_cpu_init(void)
>   {
>   	struct ocotp_regs *ocotp = (struct ocotp_regs *)OCOTP_BASE_ADDR;
> +
> +	icache_enable();
> +
>   	/*
>   	 * ROM might disable clock for SCTR,
>   	 * enable the clock before timer_init.

This does not seem enough because many boards do not find icache_enable, 
for example imx8mp_rsb3720a1_4G (but there are many others). Can you 
check it and repost ? Thanks !


+====================================================
+aarch64-linux-ld.bfd: arch/arm/mach-imx/imx8m/soc.o: in function 
`arch_cpu_init':
+arch/arm/mach-imx/imx8m/soc.c:554: undefined reference to `icache_enable'
+make[2]: *** [scripts/Makefile.spl:512: spl/u-boot-spl] Error 1
+make[1]: *** [Makefile:2105: spl/u-boot-spl] Error 2
+make: *** [Makefile:177: sub-make] Error 2


Best regards,
Stefano

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^ permalink raw reply	[flat|nested] 2+ messages in thread

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2022-04-03 21:24 [PATCH] ARM: imx: Enable instruction cache early on on i.MX8M Marek Vasut
2022-04-12 10:27 ` Stefano Babic

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