[Intel-gfx] [PATCH 0/4] drm/i915/dg2: Add support for render/media decompression

[Intel-gfx] [PATCH 0/4] drm/i915/dg2: Add support for render/media decompression

[Imre Deak]

This is a rebased version of patches 15-17 of [1], adding DG2 display
engine support for decompressing render and media compressed
framebuffers.

The dependency patches from [1] should be merged already to drm-tip.

It addresses the review comments on the modifier layout description from
Nanley, updates the commit logs vs. flat CCS and Tile4 and splits out
the changes adding the modifiers to drm_fourcc.h to separate patches.

[1] https://patchwork.freedesktop.org/series/95686/

Cc: Anshuman Gupta <anshuman.gupta@intel.com>
Cc: Ramalingam C <ramalingam.c@intel.com>
Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Mika Kahola <mika.kahola@intel.com>
Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Cc: Nanley Chery <nanley.g.chery@intel.com>

Anshuman Gupta (1):
  drm/i915/dg2: Add support for DG2 clear color compression

Matt Roper (2):
  drm/fourcc: Introduce format modifiers for DG2 render and media
    compression
  drm/i915/dg2: Add support for DG2 render and media compression

Mika Kahola (1):
  drm/fourcc: Introduce format modifier for DG2 clear color

 drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
 drivers/gpu/drm/i915/display/intel_fb.c       | 53 +++++++++++++++----
 .../drm/i915/display/skl_universal_plane.c    | 49 +++++++++++++----
 include/uapi/drm/drm_fourcc.h                 | 36 +++++++++++++
 4 files changed, 122 insertions(+), 20 deletions(-)

-- 
2.30.2

[PATCH 1/4] drm/fourcc: Introduce format modifiers for DG2 render and media compression

[Imre Deak]

From: Matt Roper <matthew.d.roper@intel.com>

The render/media engines on DG2 unify render compression and media
compression into a single format for the first time, using the Tile 4
layout for main surfaces. The compression algorithm is different from
any previous platform and the display engine must still be configured to
decompress either a render or media compressed surface; as such, we
need new RC and MC framebuffer modifiers to represent buffers in this
format.

v2: Clarify modifier layout description.

Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index b73fe6797fc37..4a5117715db3c 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -583,6 +583,28 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
 
+/*
+ * Intel color control surfaces (CCS) for DG2 render compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. The CCS data is stored
+ * outside of the GEM object in a reserved memory area dedicated for the
+ * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
+ * main surface pitch is required to be a multiple of four Tile 4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
+
+/*
+ * Intel color control surfaces (CCS) for DG2 media compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. For semi-planar formats
+ * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
+ * 0 and 1, respectively. The CCS for all planes are stored outside of the
+ * GEM object in a reserved memory area dedicated for the storage of the
+ * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
+ * pitch is required to be a multiple of four Tile 4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.30.2

[Intel-gfx] [PATCH 1/4] drm/fourcc: Introduce format modifiers for DG2 render and media compression

[Imre Deak]

From: Matt Roper <matthew.d.roper@intel.com>

The render/media engines on DG2 unify render compression and media
compression into a single format for the first time, using the Tile 4
layout for main surfaces. The compression algorithm is different from
any previous platform and the display engine must still be configured to
decompress either a render or media compressed surface; as such, we
need new RC and MC framebuffer modifiers to represent buffers in this
format.

v2: Clarify modifier layout description.

Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index b73fe6797fc37..4a5117715db3c 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -583,6 +583,28 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
 
+/*
+ * Intel color control surfaces (CCS) for DG2 render compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. The CCS data is stored
+ * outside of the GEM object in a reserved memory area dedicated for the
+ * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
+ * main surface pitch is required to be a multiple of four Tile 4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
+
+/*
+ * Intel color control surfaces (CCS) for DG2 media compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. For semi-planar formats
+ * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
+ * 0 and 1, respectively. The CCS for all planes are stored outside of the
+ * GEM object in a reserved memory area dedicated for the storage of the
+ * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
+ * pitch is required to be a multiple of four Tile 4 widths.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.30.2

Re: [PATCH 1/4] drm/fourcc: Introduce format modifiers for DG2 render and media compression

[Juha-Pekka Heikkila]

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

On 4.4.2022 16.38, Imre Deak wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> The render/media engines on DG2 unify render compression and media
> compression into a single format for the first time, using the Tile 4
> layout for main surfaces. The compression algorithm is different from
> any previous platform and the display engine must still be configured to
> decompress either a render or media compressed surface; as such, we
> need new RC and MC framebuffer modifiers to represent buffers in this
> format.
> 
> v2: Clarify modifier layout description.
> 
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Acked-by: Nanley Chery <nanley.g.chery@intel.com>
> ---
>   include/uapi/drm/drm_fourcc.h | 22 ++++++++++++++++++++++
>   1 file changed, 22 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index b73fe6797fc37..4a5117715db3c 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -583,6 +583,28 @@ extern "C" {
>    */
>   #define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
>   
> +/*
> + * Intel color control surfaces (CCS) for DG2 render compression.
> + *
> + * The main surface is Tile 4 and at plane index 0. The CCS data is stored
> + * outside of the GEM object in a reserved memory area dedicated for the
> + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
> + * main surface pitch is required to be a multiple of four Tile 4 widths.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
> +
> +/*
> + * Intel color control surfaces (CCS) for DG2 media compression.
> + *
> + * The main surface is Tile 4 and at plane index 0. For semi-planar formats
> + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
> + * 0 and 1, respectively. The CCS for all planes are stored outside of the
> + * GEM object in a reserved memory area dedicated for the storage of the
> + * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
> + * pitch is required to be a multiple of four Tile 4 widths.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
> +
>   /*
>    * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>    *

Re: [PATCH 1/4] drm/fourcc: Introduce format modifiers for DG2 render and media compression

[Juha-Pekka Heikkilä]

Seems my first mail didn't come through so here's second time for this patch:

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

On Mon, Apr 4, 2022 at 4:39 PM Imre Deak <imre.deak@intel.com> wrote:
>
> From: Matt Roper <matthew.d.roper@intel.com>
>
> The render/media engines on DG2 unify render compression and media
> compression into a single format for the first time, using the Tile 4
> layout for main surfaces. The compression algorithm is different from
> any previous platform and the display engine must still be configured to
> decompress either a render or media compressed surface; as such, we
> need new RC and MC framebuffer modifiers to represent buffers in this
> format.
>
> v2: Clarify modifier layout description.
>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Acked-by: Nanley Chery <nanley.g.chery@intel.com>
> ---
>  include/uapi/drm/drm_fourcc.h | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index b73fe6797fc37..4a5117715db3c 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -583,6 +583,28 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
>
> +/*
> + * Intel color control surfaces (CCS) for DG2 render compression.
> + *
> + * The main surface is Tile 4 and at plane index 0. The CCS data is stored
> + * outside of the GEM object in a reserved memory area dedicated for the
> + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
> + * main surface pitch is required to be a multiple of four Tile 4 widths.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
> +
> +/*
> + * Intel color control surfaces (CCS) for DG2 media compression.
> + *
> + * The main surface is Tile 4 and at plane index 0. For semi-planar formats
> + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
> + * 0 and 1, respectively. The CCS for all planes are stored outside of the
> + * GEM object in a reserved memory area dedicated for the storage of the
> + * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
> + * pitch is required to be a multiple of four Tile 4 widths.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *
> --
> 2.30.2
>

Re: [Intel-gfx] [PATCH 1/4] drm/fourcc: Introduce format modifiers for DG2 render and media compression

[Juha-Pekka Heikkilä]

Seems my first mail didn't come through so here's second time for this patch:

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

On Mon, Apr 4, 2022 at 4:39 PM Imre Deak <imre.deak@intel.com> wrote:
>
> From: Matt Roper <matthew.d.roper@intel.com>
>
> The render/media engines on DG2 unify render compression and media
> compression into a single format for the first time, using the Tile 4
> layout for main surfaces. The compression algorithm is different from
> any previous platform and the display engine must still be configured to
> decompress either a render or media compressed surface; as such, we
> need new RC and MC framebuffer modifiers to represent buffers in this
> format.
>
> v2: Clarify modifier layout description.
>
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Acked-by: Nanley Chery <nanley.g.chery@intel.com>
> ---
>  include/uapi/drm/drm_fourcc.h | 22 ++++++++++++++++++++++
>  1 file changed, 22 insertions(+)
>
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index b73fe6797fc37..4a5117715db3c 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -583,6 +583,28 @@ extern "C" {
>   */
>  #define I915_FORMAT_MOD_4_TILED         fourcc_mod_code(INTEL, 9)
>
> +/*
> + * Intel color control surfaces (CCS) for DG2 render compression.
> + *
> + * The main surface is Tile 4 and at plane index 0. The CCS data is stored
> + * outside of the GEM object in a reserved memory area dedicated for the
> + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
> + * main surface pitch is required to be a multiple of four Tile 4 widths.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS fourcc_mod_code(INTEL, 10)
> +
> +/*
> + * Intel color control surfaces (CCS) for DG2 media compression.
> + *
> + * The main surface is Tile 4 and at plane index 0. For semi-planar formats
> + * like NV12, the Y and UV planes are Tile 4 and are located at plane indices
> + * 0 and 1, respectively. The CCS for all planes are stored outside of the
> + * GEM object in a reserved memory area dedicated for the storage of the
> + * CCS data for all RC/RC_CC/MC compressible GEM objects. The main surface
> + * pitch is required to be a multiple of four Tile 4 widths.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
> +
>  /*
>   * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>   *
> --
> 2.30.2
>

[Intel-gfx] [PATCH 2/4] drm/i915/dg2: Add support for DG2 render and media compression

[Imre Deak]

From: Matt Roper <matthew.d.roper@intel.com>

Add support for DG2 render and media compression, for the description of
buffer layouts see the previous patch adding the corresponding
frame buffer modifiers.

v2:
  Display version fix [Imre]
v3:
  Split out modifier addition to separate patch.

Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_fb.c       | 13 ++++++++++
 .../drm/i915/display/skl_universal_plane.c    | 26 ++++++++++++++++---
 2 files changed, 35 insertions(+), 4 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index e9ad142ac40fa..447003a91160e 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -141,6 +141,14 @@ struct intel_modifier_desc {
 
 static const struct intel_modifier_desc intel_modifiers[] = {
 	{
+		.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
+		.display_ver = { 13, 13 },
+		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
+	}, {
+		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
+		.display_ver = { 13, 13 },
+		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
+	}, {
 		.modifier = I915_FORMAT_MOD_4_TILED,
 		.display_ver = { 13, 13 },
 		.plane_caps = INTEL_PLANE_CAP_TILING_4,
@@ -550,6 +558,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 			return 128;
 		else
 			return 512;
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
 	case I915_FORMAT_MOD_4_TILED:
 		/*
 		 * Each 4K tile consists of 64B(8*8) subtiles, with
@@ -752,6 +762,9 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 	case I915_FORMAT_MOD_4_TILED:
 	case I915_FORMAT_MOD_Yf_TILED:
 		return 1 * 1024 * 1024;
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+		return 16 * 1024;
 	default:
 		MISSING_CASE(fb->modifier);
 		return 0;
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index c57fca1fe6788..b939c503bc6ff 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -773,6 +773,14 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		return PLANE_CTL_TILED_Y;
 	case I915_FORMAT_MOD_4_TILED:
 		return PLANE_CTL_TILED_4;
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+		return PLANE_CTL_TILED_4 |
+			PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+			PLANE_CTL_CLEAR_COLOR_DISABLE;
+	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
+		return PLANE_CTL_TILED_4 |
+			PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
+			PLANE_CTL_CLEAR_COLOR_DISABLE;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -2168,6 +2176,10 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
 	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
 		return false;
 
+	/* Wa_14013215631 */
+	if (IS_DG2_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
+		return false;
+
 	return plane_id < PLANE_SPRITE4;
 }
 
@@ -2415,9 +2427,10 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
 	case PLANE_CTL_TILED_Y:
 		plane_config->tiling = I915_TILING_Y;
 		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
-			fb->modifier = DISPLAY_VER(dev_priv) >= 12 ?
-				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
-				I915_FORMAT_MOD_Y_TILED_CCS;
+			if (DISPLAY_VER(dev_priv) >= 12)
+				fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
+			else
+				fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
 		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
 			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
 		else
@@ -2425,7 +2438,12 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
 		break;
 	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
 		if (HAS_4TILE(dev_priv)) {
-			fb->modifier = I915_FORMAT_MOD_4_TILED;
+			if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
+			else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
+				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
+			else
+				fb->modifier = I915_FORMAT_MOD_4_TILED;
 		} else {
 			if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
 				fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;
-- 
2.30.2

Re: [Intel-gfx] [PATCH 2/4] drm/i915/dg2: Add support for DG2 render and media compression

[Juha-Pekka Heikkila]

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

On 4.4.2022 16.38, Imre Deak wrote:
> From: Matt Roper <matthew.d.roper@intel.com>
> 
> Add support for DG2 render and media compression, for the description of
> buffer layouts see the previous patch adding the corresponding
> frame buffer modifiers.
> 
> v2:
>    Display version fix [Imre]
> v3:
>    Split out modifier addition to separate patch.
> 
> Signed-off-by: Matt Roper <matthew.d.roper@intel.com>
> cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>   drivers/gpu/drm/i915/display/intel_fb.c       | 13 ++++++++++
>   .../drm/i915/display/skl_universal_plane.c    | 26 ++++++++++++++++---
>   2 files changed, 35 insertions(+), 4 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
> index e9ad142ac40fa..447003a91160e 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -141,6 +141,14 @@ struct intel_modifier_desc {
>   
>   static const struct intel_modifier_desc intel_modifiers[] = {
>   	{
> +		.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
> +		.display_ver = { 13, 13 },
> +		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
> +	}, {
> +		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
> +		.display_ver = { 13, 13 },
> +		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC,
> +	}, {
>   		.modifier = I915_FORMAT_MOD_4_TILED,
>   		.display_ver = { 13, 13 },
>   		.plane_caps = INTEL_PLANE_CAP_TILING_4,
> @@ -550,6 +558,8 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
>   			return 128;
>   		else
>   			return 512;
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
>   	case I915_FORMAT_MOD_4_TILED:
>   		/*
>   		 * Each 4K tile consists of 64B(8*8) subtiles, with
> @@ -752,6 +762,9 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
>   	case I915_FORMAT_MOD_4_TILED:
>   	case I915_FORMAT_MOD_Yf_TILED:
>   		return 1 * 1024 * 1024;
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> +		return 16 * 1024;
>   	default:
>   		MISSING_CASE(fb->modifier);
>   		return 0;
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index c57fca1fe6788..b939c503bc6ff 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -773,6 +773,14 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
>   		return PLANE_CTL_TILED_Y;
>   	case I915_FORMAT_MOD_4_TILED:
>   		return PLANE_CTL_TILED_4;
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +		return PLANE_CTL_TILED_4 |
> +			PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> +			PLANE_CTL_CLEAR_COLOR_DISABLE;
> +	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> +		return PLANE_CTL_TILED_4 |
> +			PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
> +			PLANE_CTL_CLEAR_COLOR_DISABLE;
>   	case I915_FORMAT_MOD_Y_TILED_CCS:
>   	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>   		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -2168,6 +2176,10 @@ static bool gen12_plane_has_mc_ccs(struct drm_i915_private *i915,
>   	if (IS_ADLP_DISPLAY_STEP(i915, STEP_A0, STEP_B0))
>   		return false;
>   
> +	/* Wa_14013215631 */
> +	if (IS_DG2_DISPLAY_STEP(i915, STEP_A0, STEP_C0))
> +		return false;
> +
>   	return plane_id < PLANE_SPRITE4;
>   }
>   
> @@ -2415,9 +2427,10 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
>   	case PLANE_CTL_TILED_Y:
>   		plane_config->tiling = I915_TILING_Y;
>   		if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> -			fb->modifier = DISPLAY_VER(dev_priv) >= 12 ?
> -				I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS :
> -				I915_FORMAT_MOD_Y_TILED_CCS;
> +			if (DISPLAY_VER(dev_priv) >= 12)
> +				fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS;
> +			else
> +				fb->modifier = I915_FORMAT_MOD_Y_TILED_CCS;
>   		else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
>   			fb->modifier = I915_FORMAT_MOD_Y_TILED_GEN12_MC_CCS;
>   		else
> @@ -2425,7 +2438,12 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
>   		break;
>   	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
>   		if (HAS_4TILE(dev_priv)) {
> -			fb->modifier = I915_FORMAT_MOD_4_TILED;
> +			if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> +				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
> +			else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
> +				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
> +			else
> +				fb->modifier = I915_FORMAT_MOD_4_TILED;
>   		} else {
>   			if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
>   				fb->modifier = I915_FORMAT_MOD_Yf_TILED_CCS;

[PATCH 3/4] drm/fourcc: Introduce format modifier for DG2 clear color

[Imre Deak]

From: Mika Kahola <mika.kahola@intel.com>

DG2 clear color render compression uses Tile4 layout. Therefore, we need
to define a new format modifier for uAPI to support clear color rendering.

v2:
  Display version is fixed. [Imre]
  KDoc is enhanced for cc modifier. [Nanley & Lionel]
v3:
  Split out the modifier addition to a separate patch.
  Clarify the modifier layout description.

Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 4a5117715db3c..e5074162bcdd4 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -605,6 +605,20 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
 
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. The CCS data is stored
+ * outside of the GEM object in a reserved memory area dedicated for the
+ * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
+ * main surface pitch is required to be a multiple of four Tile 4 widths. The
+ * clear color is stored at plane index 1 and the pitch should be ignored. The
+ * format of the 256 bits of clear color data matches the one used for the
+ * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
+ * for details.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.30.2

[Intel-gfx] [PATCH 3/4] drm/fourcc: Introduce format modifier for DG2 clear color

[Imre Deak]

From: Mika Kahola <mika.kahola@intel.com>

DG2 clear color render compression uses Tile4 layout. Therefore, we need
to define a new format modifier for uAPI to support clear color rendering.

v2:
  Display version is fixed. [Imre]
  KDoc is enhanced for cc modifier. [Nanley & Lionel]
v3:
  Split out the modifier addition to a separate patch.
  Clarify the modifier layout description.

Cc: dri-devel@lists.freedesktop.org
Signed-off-by: Mika Kahola <mika.kahola@intel.com>
cc: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
Acked-by: Nanley Chery <nanley.g.chery@intel.com>
---
 include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
index 4a5117715db3c..e5074162bcdd4 100644
--- a/include/uapi/drm/drm_fourcc.h
+++ b/include/uapi/drm/drm_fourcc.h
@@ -605,6 +605,20 @@ extern "C" {
  */
 #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
 
+/*
+ * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
+ *
+ * The main surface is Tile 4 and at plane index 0. The CCS data is stored
+ * outside of the GEM object in a reserved memory area dedicated for the
+ * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
+ * main surface pitch is required to be a multiple of four Tile 4 widths. The
+ * clear color is stored at plane index 1 and the pitch should be ignored. The
+ * format of the 256 bits of clear color data matches the one used for the
+ * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
+ * for details.
+ */
+#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
+
 /*
  * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
  *
-- 
2.30.2

Re: [Intel-gfx] [PATCH 3/4] drm/fourcc: Introduce format modifier for DG2 clear color

[Juha-Pekka Heikkila]

Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>

On 4.4.2022 16.38, Imre Deak wrote:
> From: Mika Kahola <mika.kahola@intel.com>
> 
> DG2 clear color render compression uses Tile4 layout. Therefore, we need
> to define a new format modifier for uAPI to support clear color rendering.
> 
> v2:
>    Display version is fixed. [Imre]
>    KDoc is enhanced for cc modifier. [Nanley & Lionel]
> v3:
>    Split out the modifier addition to a separate patch.
>    Clarify the modifier layout description.
> 
> Cc: dri-devel@lists.freedesktop.org
> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
> cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> Acked-by: Nanley Chery <nanley.g.chery@intel.com>
> ---
>   include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++
>   1 file changed, 14 insertions(+)
> 
> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
> index 4a5117715db3c..e5074162bcdd4 100644
> --- a/include/uapi/drm/drm_fourcc.h
> +++ b/include/uapi/drm/drm_fourcc.h
> @@ -605,6 +605,20 @@ extern "C" {
>    */
>   #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
>   
> +/*
> + * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
> + *
> + * The main surface is Tile 4 and at plane index 0. The CCS data is stored
> + * outside of the GEM object in a reserved memory area dedicated for the
> + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
> + * main surface pitch is required to be a multiple of four Tile 4 widths. The
> + * clear color is stored at plane index 1 and the pitch should be ignored. The
> + * format of the 256 bits of clear color data matches the one used for the
> + * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
> + * for details.
> + */
> +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
> +
>   /*
>    * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>    *

Re: [Intel-gfx] [PATCH 3/4] drm/fourcc: Introduce format modifier for DG2 clear color

[Maarten Lankhorst]

Op 07-04-2022 om 15:37 schreef Juha-Pekka Heikkila:
> Reviewed-by: Juha-Pekka Heikkila <juhapekka.heikkila@gmail.com>
>
> On 4.4.2022 16.38, Imre Deak wrote:
>> From: Mika Kahola <mika.kahola@intel.com>
>>
>> DG2 clear color render compression uses Tile4 layout. Therefore, we need
>> to define a new format modifier for uAPI to support clear color rendering.
>>
>> v2:
>>    Display version is fixed. [Imre]
>>    KDoc is enhanced for cc modifier. [Nanley & Lionel]
>> v3:
>>    Split out the modifier addition to a separate patch.
>>    Clarify the modifier layout description.
>>
>> Cc: dri-devel@lists.freedesktop.org
>> Signed-off-by: Mika Kahola <mika.kahola@intel.com>
>> cc: Anshuman Gupta <anshuman.gupta@intel.com>
>> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
>> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
>> Signed-off-by: Imre Deak <imre.deak@intel.com>
>> Acked-by: Nanley Chery <nanley.g.chery@intel.com>
>> ---
>>   include/uapi/drm/drm_fourcc.h | 14 ++++++++++++++
>>   1 file changed, 14 insertions(+)
>>
>> diff --git a/include/uapi/drm/drm_fourcc.h b/include/uapi/drm/drm_fourcc.h
>> index 4a5117715db3c..e5074162bcdd4 100644
>> --- a/include/uapi/drm/drm_fourcc.h
>> +++ b/include/uapi/drm/drm_fourcc.h
>> @@ -605,6 +605,20 @@ extern "C" {
>>    */
>>   #define I915_FORMAT_MOD_4_TILED_DG2_MC_CCS fourcc_mod_code(INTEL, 11)
>>   +/*
>> + * Intel Color Control Surface with Clear Color (CCS) for DG2 render compression.
>> + *
>> + * The main surface is Tile 4 and at plane index 0. The CCS data is stored
>> + * outside of the GEM object in a reserved memory area dedicated for the
>> + * storage of the CCS data for all RC/RC_CC/MC compressible GEM objects. The
>> + * main surface pitch is required to be a multiple of four Tile 4 widths. The
>> + * clear color is stored at plane index 1 and the pitch should be ignored. The
>> + * format of the 256 bits of clear color data matches the one used for the
>> + * I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC modifier, see its description
>> + * for details.
>> + */
>> +#define I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC fourcc_mod_code(INTEL, 12)
>> +
>>   /*
>>    * Tiled, NV12MT, grouped in 64 (pixels) x 32 (lines) -sized macroblocks
>>    *
>
I personally think it's not required since it's a i915 only format), but for merging series through drm-intel:

Acked-by: Maarten Lankhorst <maarten.lankhorst@linux.intel.com>

[Intel-gfx] [PATCH 4/4] drm/i915/dg2: Add support for DG2 clear color compression

[Imre Deak]

From: Anshuman Gupta <anshuman.gupta@intel.com>

DG2 onwards discrete gfx has support for new flat CCS mapping,
which brings in display feature in to avoid Aux walk for compressed
surface. This support build on top of Flat CCS support added in XEHPSDV.
FLAT CCS surface base address should be 64k aligned,
Compressed displayable surfaces must use tile4 format.

HAS: 1407880786
B.Spec : 7655
B.Spec : 53902

v2: Merge all bits required for the support of functionality into this
    patch from the patch adding the corresponding modifier.

Cc: Mika Kahola <mika.kahola@intel.com>
Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
Signed-off-by: Imre Deak <imre.deak@intel.com>
---
 drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
 drivers/gpu/drm/i915/display/intel_fb.c       | 40 ++++++++++++++-----
 .../drm/i915/display/skl_universal_plane.c    | 25 ++++++++----
 3 files changed, 52 insertions(+), 17 deletions(-)

diff --git a/drivers/gpu/drm/i915/display/intel_display.c b/drivers/gpu/drm/i915/display/intel_display.c
index eee185ed41c3e..ca997a0a05174 100644
--- a/drivers/gpu/drm/i915/display/intel_display.c
+++ b/drivers/gpu/drm/i915/display/intel_display.c
@@ -8477,7 +8477,9 @@ static void intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
 
 		/*
 		 * The layout of the fast clear color value expected by HW
-		 * (the DRM ABI requiring this value to be located in fb at offset 0 of plane#2):
+		 * (the DRM ABI requiring this value to be located in fb at
+		 * offset 0 of cc plane, plane #2 previous generations or
+		 * plane #1 for flat ccs):
 		 * - 4 x 4 bytes per-channel value
 		 *   (in surface type specific float/int format provided by the fb user)
 		 * - 8 bytes native color value used by the display
diff --git a/drivers/gpu/drm/i915/display/intel_fb.c b/drivers/gpu/drm/i915/display/intel_fb.c
index 447003a91160e..9f5a6b79e95b5 100644
--- a/drivers/gpu/drm/i915/display/intel_fb.c
+++ b/drivers/gpu/drm/i915/display/intel_fb.c
@@ -107,6 +107,21 @@ static const struct drm_format_info gen12_ccs_cc_formats[] = {
 	  .hsub = 1, .vsub = 1, .has_alpha = true },
 };
 
+static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
+	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
+	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
+	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, },
+	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
+	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, .has_alpha = true },
+	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
+	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
+	  .hsub = 1, .vsub = 1, .has_alpha = true },
+};
+
 struct intel_modifier_desc {
 	u64 modifier;
 	struct {
@@ -144,6 +159,14 @@ static const struct intel_modifier_desc intel_modifiers[] = {
 		.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
 		.display_ver = { 13, 13 },
 		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_MC,
+	}, {
+		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
+		.display_ver = { 13, 13 },
+		.plane_caps = INTEL_PLANE_CAP_TILING_4 | INTEL_PLANE_CAP_CCS_RC_CC,
+
+		.ccs.cc_planes = BIT(1),
+
+		FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),
 	}, {
 		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
 		.display_ver = { 13, 13 },
@@ -393,17 +416,13 @@ bool intel_fb_plane_supports_modifier(struct intel_plane *plane, u64 modifier)
 static bool format_is_yuv_semiplanar(const struct intel_modifier_desc *md,
 				     const struct drm_format_info *info)
 {
-	int yuv_planes;
-
 	if (!info->is_yuv)
 		return false;
 
-	if (plane_caps_contain_any(md->plane_caps, INTEL_PLANE_CAP_CCS_MASK))
-		yuv_planes = 4;
+	if (hweight8(md->ccs.planar_aux_planes) == 2)
+		return info->num_planes == 4;
 	else
-		yuv_planes = 2;
-
-	return info->num_planes == yuv_planes;
+		return info->num_planes == 2;
 }
 
 /**
@@ -528,12 +547,13 @@ static unsigned int gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_p
 
 int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)
 {
+	const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
 	struct drm_i915_private *i915 = to_i915(fb->dev);
 
-	if (intel_fb_is_ccs_modifier(fb->modifier))
+	if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes)
 		return main_to_ccs_plane(fb, main_plane);
 	else if (DISPLAY_VER(i915) < 11 &&
-		 intel_format_info_is_yuv_semiplanar(fb->format, fb->modifier))
+		 format_is_yuv_semiplanar(md, fb->format))
 		return 1;
 	else
 		return 0;
@@ -559,6 +579,7 @@ intel_tile_width_bytes(const struct drm_framebuffer *fb, int color_plane)
 		else
 			return 512;
 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
 	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
 	case I915_FORMAT_MOD_4_TILED:
 		/*
@@ -763,6 +784,7 @@ unsigned int intel_surf_alignment(const struct drm_framebuffer *fb,
 	case I915_FORMAT_MOD_Yf_TILED:
 		return 1 * 1024 * 1024;
 	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
 	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
 		return 16 * 1024;
 	default:
diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c b/drivers/gpu/drm/i915/display/skl_universal_plane.c
index b939c503bc6ff..caa03324a733a 100644
--- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
+++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
@@ -781,6 +781,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
 		return PLANE_CTL_TILED_4 |
 			PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
 			PLANE_CTL_CLEAR_COLOR_DISABLE;
+	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
+		return PLANE_CTL_TILED_4 | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
 	case I915_FORMAT_MOD_Y_TILED_CCS:
 	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
 		return PLANE_CTL_TILED_Y | PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
@@ -1228,8 +1230,10 @@ icl_plane_update_noarm(struct intel_plane *plane,
 				  upper_32_bits(plane_state->ccval));
 	}
 
-	intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
-			  skl_plane_aux_dist(plane_state, color_plane));
+	/* FLAT CCS doesn't need to program AUX_DIST */
+	if (!HAS_FLAT_CCS(dev_priv))
+		intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
+				  skl_plane_aux_dist(plane_state, color_plane));
 
 	if (icl_is_hdr_plane(dev_priv, plane_id))
 		intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
@@ -1629,9 +1633,10 @@ static int skl_check_main_surface(struct intel_plane_state *plane_state)
 
 	/*
 	 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
-	 * they match with the main surface x/y offsets.
+	 * they match with the main surface x/y offsets. On DG2
+	 * there's no aux plane on fb so skip this checking.
 	 */
-	if (intel_fb_is_ccs_modifier(fb->modifier)) {
+	if (intel_fb_is_ccs_modifier(fb->modifier) && aux_plane) {
 		while (!skl_check_main_ccs_coordinates(plane_state, x, y,
 						       offset, aux_plane)) {
 			if (offset == 0)
@@ -1675,6 +1680,8 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 	const struct drm_framebuffer *fb = plane_state->hw.fb;
 	unsigned int rotation = plane_state->hw.rotation;
 	int uv_plane = 1;
+	int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ?
+			skl_main_to_aux_plane(fb, uv_plane) : 0;
 	int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation);
 	int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation);
 	int x = plane_state->uapi.src.x1 >> 17;
@@ -1695,8 +1702,7 @@ static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
 	offset = intel_plane_compute_aligned_offset(&x, &y,
 						    plane_state, uv_plane);
 
-	if (intel_fb_is_ccs_modifier(fb->modifier)) {
-		int ccs_plane = main_to_ccs_plane(fb, uv_plane);
+	if (ccs_plane) {
 		u32 aux_offset = plane_state->view.color_plane[ccs_plane].offset;
 		u32 alignment = intel_surf_alignment(fb, uv_plane);
 
@@ -2438,10 +2444,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
 		break;
 	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
 		if (HAS_4TILE(dev_priv)) {
-			if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+			u32 rc_mask = PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
+				      PLANE_CTL_CLEAR_COLOR_DISABLE;
+
+			if ((val & rc_mask) == rc_mask)
 				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
 			else if (val & PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
 				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
+			else if (val & PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
+				fb->modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
 			else
 				fb->modifier = I915_FORMAT_MOD_4_TILED;
 		} else {
-- 
2.30.2

Re: [Intel-gfx] [PATCH 4/4] drm/i915/dg2: Add support for DG2 clear color compression

[Gupta, Anshuman]

> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Monday, April 4, 2022 7:09 PM
> To: intel-gfx@lists.freedesktop.org
> Cc: Gupta, Anshuman <anshuman.gupta@intel.com>; Kahola, Mika
> <mika.kahola@intel.com>; Heikkila, Juha-pekka <juha-
> pekka.heikkila@intel.com>; C, Ramalingam <ramalingam.c@intel.com>
> Subject: [PATCH 4/4] drm/i915/dg2: Add support for DG2 clear color
> compression
> 
> From: Anshuman Gupta <anshuman.gupta@intel.com>
> 
> DG2 onwards discrete gfx has support for new flat CCS mapping, which brings in
> display feature in to avoid Aux walk for compressed surface. This support build
> on top of Flat CCS support added in XEHPSDV.
> FLAT CCS surface base address should be 64k aligned, Compressed displayable
> surfaces must use tile4 format.

IMHO commit log should also describe a bit of description for DG2 Clear color.
Original patch was meant to add FLAT_CCS support, commit log not fully aligns
with commit header.
May be it would be good if patch authorship changes to the DG2 original clear color author
for any required follow-up later ? 
> 
> HAS: 1407880786
> B.Spec : 7655
> B.Spec : 53902
> 
> v2: Merge all bits required for the support of functionality into this
>     patch from the patch adding the corresponding modifier.
> 
> Cc: Mika Kahola <mika.kahola@intel.com>
> Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> Signed-off-by: Imre Deak <imre.deak@intel.com>
> ---
>  drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
>  drivers/gpu/drm/i915/display/intel_fb.c       | 40 ++++++++++++++-----
>  .../drm/i915/display/skl_universal_plane.c    | 25 ++++++++----
>  3 files changed, 52 insertions(+), 17 deletions(-)
> 
> diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> b/drivers/gpu/drm/i915/display/intel_display.c
> index eee185ed41c3e..ca997a0a05174 100644
> --- a/drivers/gpu/drm/i915/display/intel_display.c
> +++ b/drivers/gpu/drm/i915/display/intel_display.c
> @@ -8477,7 +8477,9 @@ static void
> intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
> 
>  		/*
>  		 * The layout of the fast clear color value expected by HW
> -		 * (the DRM ABI requiring this value to be located in fb at offset
> 0 of plane#2):
> +		 * (the DRM ABI requiring this value to be located in fb at
> +		 * offset 0 of cc plane, plane #2 previous generations or
> +		 * plane #1 for flat ccs):
>  		 * - 4 x 4 bytes per-channel value
>  		 *   (in surface type specific float/int format provided by the fb
> user)
>  		 * - 8 bytes native color value used by the display diff --git
> a/drivers/gpu/drm/i915/display/intel_fb.c
> b/drivers/gpu/drm/i915/display/intel_fb.c
> index 447003a91160e..9f5a6b79e95b5 100644
> --- a/drivers/gpu/drm/i915/display/intel_fb.c
> +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> @@ -107,6 +107,21 @@ static const struct drm_format_info
> gen12_ccs_cc_formats[] = {
>  	  .hsub = 1, .vsub = 1, .has_alpha = true },  };
> 
> +static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
> +	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> +	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> +	  .hsub = 1, .vsub = 1, },
> +	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> +	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> +	  .hsub = 1, .vsub = 1, },
> +	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> +	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> +	  .hsub = 1, .vsub = 1, .has_alpha = true },
> +	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> +	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> +	  .hsub = 1, .vsub = 1, .has_alpha = true }, };
> +
>  struct intel_modifier_desc {
>  	u64 modifier;
>  	struct {
> @@ -144,6 +159,14 @@ static const struct intel_modifier_desc
> intel_modifiers[] = {
>  		.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
>  		.display_ver = { 13, 13 },
>  		.plane_caps = INTEL_PLANE_CAP_TILING_4 |
> INTEL_PLANE_CAP_CCS_MC,
> +	}, {
> +		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
> +		.display_ver = { 13, 13 },
> +		.plane_caps = INTEL_PLANE_CAP_TILING_4 |
> INTEL_PLANE_CAP_CCS_RC_CC,
> +
> +		.ccs.cc_planes = BIT(1),
> +
> +		FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),
>  	}, {
>  		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
>  		.display_ver = { 13, 13 },
> @@ -393,17 +416,13 @@ bool intel_fb_plane_supports_modifier(struct
> intel_plane *plane, u64 modifier)  static bool format_is_yuv_semiplanar(const
> struct intel_modifier_desc *md,
>  				     const struct drm_format_info *info)  {
> -	int yuv_planes;
> -
>  	if (!info->is_yuv)
>  		return false;
> 
> -	if (plane_caps_contain_any(md->plane_caps,
> INTEL_PLANE_CAP_CCS_MASK))
> -		yuv_planes = 4;
> +	if (hweight8(md->ccs.planar_aux_planes) == 2)
> +		return info->num_planes == 4;
>  	else
> -		yuv_planes = 2;
> -
> -	return info->num_planes == yuv_planes;
> +		return info->num_planes == 2;
>  }
> 
>  /**
> @@ -528,12 +547,13 @@ static unsigned int gen12_ccs_aux_stride(struct
> intel_framebuffer *fb, int ccs_p
> 
>  int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)  {
> +	const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
>  	struct drm_i915_private *i915 = to_i915(fb->dev);
> 
> -	if (intel_fb_is_ccs_modifier(fb->modifier))
> +	if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes)
>  		return main_to_ccs_plane(fb, main_plane);
>  	else if (DISPLAY_VER(i915) < 11 &&
> -		 intel_format_info_is_yuv_semiplanar(fb->format, fb-
> >modifier))
> +		 format_is_yuv_semiplanar(md, fb->format))
>  		return 1;
>  	else
>  		return 0;
> @@ -559,6 +579,7 @@ intel_tile_width_bytes(const struct drm_framebuffer
> *fb, int color_plane)
>  		else
>  			return 512;
>  	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
>  	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
>  	case I915_FORMAT_MOD_4_TILED:
>  		/*
> @@ -763,6 +784,7 @@ unsigned int intel_surf_alignment(const struct
> drm_framebuffer *fb,
>  	case I915_FORMAT_MOD_Yf_TILED:
>  		return 1 * 1024 * 1024;
>  	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
>  	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
>  		return 16 * 1024;
>  	default:
> diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> index b939c503bc6ff..caa03324a733a 100644
> --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> @@ -781,6 +781,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
>  		return PLANE_CTL_TILED_4 |
>  			PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
>  			PLANE_CTL_CLEAR_COLOR_DISABLE;
> +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> +		return PLANE_CTL_TILED_4 |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
>  	case I915_FORMAT_MOD_Y_TILED_CCS:
>  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
>  		return PLANE_CTL_TILED_Y |
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> @@ -1228,8 +1230,10 @@ icl_plane_update_noarm(struct intel_plane *plane,
>  				  upper_32_bits(plane_state->ccval));
>  	}
> 
> -	intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
> -			  skl_plane_aux_dist(plane_state, color_plane));
> +	/* FLAT CCS doesn't need to program AUX_DIST */
> +	if (!HAS_FLAT_CCS(dev_priv))
> +		intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
> +				  skl_plane_aux_dist(plane_state, color_plane));
> 
>  	if (icl_is_hdr_plane(dev_priv, plane_id))
>  		intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
> @@ -1629,9 +1633,10 @@ static int skl_check_main_surface(struct
> intel_plane_state *plane_state)
> 
>  	/*
>  	 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
> -	 * they match with the main surface x/y offsets.
> +	 * they match with the main surface x/y offsets. On DG2
> +	 * there's no aux plane on fb so skip this checking.
>  	 */
> -	if (intel_fb_is_ccs_modifier(fb->modifier)) {
> +	if (intel_fb_is_ccs_modifier(fb->modifier) && aux_plane) {
>  		while (!skl_check_main_ccs_coordinates(plane_state, x, y,
>  						       offset, aux_plane)) {
>  			if (offset == 0)
> @@ -1675,6 +1680,8 @@ static int skl_check_nv12_aux_surface(struct
> intel_plane_state *plane_state)
>  	const struct drm_framebuffer *fb = plane_state->hw.fb;
>  	unsigned int rotation = plane_state->hw.rotation;
>  	int uv_plane = 1;
> +	int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ?
> +			skl_main_to_aux_plane(fb, uv_plane) : 0;
>  	int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation);
>  	int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation);
>  	int x = plane_state->uapi.src.x1 >> 17; @@ -1695,8 +1702,7 @@ static
> int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
>  	offset = intel_plane_compute_aligned_offset(&x, &y,
>  						    plane_state, uv_plane);
> 
> -	if (intel_fb_is_ccs_modifier(fb->modifier)) {
> -		int ccs_plane = main_to_ccs_plane(fb, uv_plane);
> +	if (ccs_plane) {
>  		u32 aux_offset = plane_state-
> >view.color_plane[ccs_plane].offset;
>  		u32 alignment = intel_surf_alignment(fb, uv_plane);
> 
> @@ -2438,10 +2444,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
>  		break;
>  	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
>  		if (HAS_4TILE(dev_priv)) {
> -			if (val &
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> +			u32 rc_mask =
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> +				      PLANE_CTL_CLEAR_COLOR_DISABLE;
> +
> +			if ((val & rc_mask) == rc_mask)
>  				fb->modifier =
> I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
>  			else if (val &
> PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
>  				fb->modifier =
> I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
> +			else if (val &
> PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> +				fb->modifier =
> I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
>  			else
>  				fb->modifier = I915_FORMAT_MOD_4_TILED;
>  		} else {
> --
> 2.30.2

Re: [Intel-gfx] [PATCH 4/4] drm/i915/dg2: Add support for DG2 clear color compression

[Imre Deak]

On Thu, Apr 07, 2022 at 08:47:13AM +0300, Gupta, Anshuman wrote:
> > -----Original Message-----
> > From: Deak, Imre <imre.deak@intel.com>
> > Sent: Monday, April 4, 2022 7:09 PM
> > To: intel-gfx@lists.freedesktop.org
> > Cc: Gupta, Anshuman <anshuman.gupta@intel.com>; Kahola, Mika
> > <mika.kahola@intel.com>; Heikkila, Juha-pekka <juha-
> > pekka.heikkila@intel.com>; C, Ramalingam <ramalingam.c@intel.com>
> > Subject: [PATCH 4/4] drm/i915/dg2: Add support for DG2 clear color
> > compression
> > 
> > From: Anshuman Gupta <anshuman.gupta@intel.com>
> > 
> > DG2 onwards discrete gfx has support for new flat CCS mapping, which
> > brings in display feature in to avoid Aux walk for compressed
> > surface. This support build on top of Flat CCS support added in
> > XEHPSDV.  FLAT CCS surface base address should be 64k aligned,
> > Compressed displayable surfaces must use tile4 format.
> 
> IMHO commit log should also describe a bit of description for DG2
> Clear color. Original patch was meant to add FLAT_CCS support, commit
> log not fully aligns with commit header.
>
> May be it would be good if patch authorship changes to the DG2
> original clear color author for any required follow-up later ? 

I kept your authorship based on
https://patchwork.freedesktop.org/patch/471775/?series=95686&rev=5

and then an Ack from you. But yes, there's been some changes since the
support for DG2 CCS was originally added, with multiple people involved,
so the authorship may be not accurate. I can update that along with the
commit message.

> > HAS: 1407880786
> > B.Spec : 7655
> > B.Spec : 53902
> > 
> > v2: Merge all bits required for the support of functionality into this
> >     patch from the patch adding the corresponding modifier.
> > 
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > ---
> >  drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
> >  drivers/gpu/drm/i915/display/intel_fb.c       | 40 ++++++++++++++-----
> >  .../drm/i915/display/skl_universal_plane.c    | 25 ++++++++----
> >  3 files changed, 52 insertions(+), 17 deletions(-)
> > 
> > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > b/drivers/gpu/drm/i915/display/intel_display.c
> > index eee185ed41c3e..ca997a0a05174 100644
> > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > @@ -8477,7 +8477,9 @@ static void
> > intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
> > 
> >  		/*
> >  		 * The layout of the fast clear color value expected by HW
> > -		 * (the DRM ABI requiring this value to be located in fb at offset
> > 0 of plane#2):
> > +		 * (the DRM ABI requiring this value to be located in fb at
> > +		 * offset 0 of cc plane, plane #2 previous generations or
> > +		 * plane #1 for flat ccs):
> >  		 * - 4 x 4 bytes per-channel value
> >  		 *   (in surface type specific float/int format provided by the fb
> > user)
> >  		 * - 8 bytes native color value used by the display diff --git
> > a/drivers/gpu/drm/i915/display/intel_fb.c
> > b/drivers/gpu/drm/i915/display/intel_fb.c
> > index 447003a91160e..9f5a6b79e95b5 100644
> > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > @@ -107,6 +107,21 @@ static const struct drm_format_info
> > gen12_ccs_cc_formats[] = {
> >  	  .hsub = 1, .vsub = 1, .has_alpha = true },  };
> > 
> > +static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
> > +	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> > +	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > +	  .hsub = 1, .vsub = 1, },
> > +	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> > +	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > +	  .hsub = 1, .vsub = 1, },
> > +	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> > +	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > +	  .hsub = 1, .vsub = 1, .has_alpha = true },
> > +	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> > +	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > +	  .hsub = 1, .vsub = 1, .has_alpha = true }, };
> > +
> >  struct intel_modifier_desc {
> >  	u64 modifier;
> >  	struct {
> > @@ -144,6 +159,14 @@ static const struct intel_modifier_desc
> > intel_modifiers[] = {
> >  		.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
> >  		.display_ver = { 13, 13 },
> >  		.plane_caps = INTEL_PLANE_CAP_TILING_4 |
> > INTEL_PLANE_CAP_CCS_MC,
> > +	}, {
> > +		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
> > +		.display_ver = { 13, 13 },
> > +		.plane_caps = INTEL_PLANE_CAP_TILING_4 |
> > INTEL_PLANE_CAP_CCS_RC_CC,
> > +
> > +		.ccs.cc_planes = BIT(1),
> > +
> > +		FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),
> >  	}, {
> >  		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
> >  		.display_ver = { 13, 13 },
> > @@ -393,17 +416,13 @@ bool intel_fb_plane_supports_modifier(struct
> > intel_plane *plane, u64 modifier)  static bool format_is_yuv_semiplanar(const
> > struct intel_modifier_desc *md,
> >  				     const struct drm_format_info *info)  {
> > -	int yuv_planes;
> > -
> >  	if (!info->is_yuv)
> >  		return false;
> > 
> > -	if (plane_caps_contain_any(md->plane_caps,
> > INTEL_PLANE_CAP_CCS_MASK))
> > -		yuv_planes = 4;
> > +	if (hweight8(md->ccs.planar_aux_planes) == 2)
> > +		return info->num_planes == 4;
> >  	else
> > -		yuv_planes = 2;
> > -
> > -	return info->num_planes == yuv_planes;
> > +		return info->num_planes == 2;
> >  }
> > 
> >  /**
> > @@ -528,12 +547,13 @@ static unsigned int gen12_ccs_aux_stride(struct
> > intel_framebuffer *fb, int ccs_p
> > 
> >  int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int main_plane)  {
> > +	const struct intel_modifier_desc *md = lookup_modifier(fb->modifier);
> >  	struct drm_i915_private *i915 = to_i915(fb->dev);
> > 
> > -	if (intel_fb_is_ccs_modifier(fb->modifier))
> > +	if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes)
> >  		return main_to_ccs_plane(fb, main_plane);
> >  	else if (DISPLAY_VER(i915) < 11 &&
> > -		 intel_format_info_is_yuv_semiplanar(fb->format, fb-
> > >modifier))
> > +		 format_is_yuv_semiplanar(md, fb->format))
> >  		return 1;
> >  	else
> >  		return 0;
> > @@ -559,6 +579,7 @@ intel_tile_width_bytes(const struct drm_framebuffer
> > *fb, int color_plane)
> >  		else
> >  			return 512;
> >  	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> > +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> >  	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> >  	case I915_FORMAT_MOD_4_TILED:
> >  		/*
> > @@ -763,6 +784,7 @@ unsigned int intel_surf_alignment(const struct
> > drm_framebuffer *fb,
> >  	case I915_FORMAT_MOD_Yf_TILED:
> >  		return 1 * 1024 * 1024;
> >  	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> > +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> >  	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> >  		return 16 * 1024;
> >  	default:
> > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > index b939c503bc6ff..caa03324a733a 100644
> > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > @@ -781,6 +781,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> >  		return PLANE_CTL_TILED_4 |
> >  			PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
> >  			PLANE_CTL_CLEAR_COLOR_DISABLE;
> > +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> > +		return PLANE_CTL_TILED_4 |
> > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> >  		return PLANE_CTL_TILED_Y |
> > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > @@ -1228,8 +1230,10 @@ icl_plane_update_noarm(struct intel_plane *plane,
> >  				  upper_32_bits(plane_state->ccval));
> >  	}
> > 
> > -	intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
> > -			  skl_plane_aux_dist(plane_state, color_plane));
> > +	/* FLAT CCS doesn't need to program AUX_DIST */
> > +	if (!HAS_FLAT_CCS(dev_priv))
> > +		intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
> > +				  skl_plane_aux_dist(plane_state, color_plane));
> > 
> >  	if (icl_is_hdr_plane(dev_priv, plane_id))
> >  		intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
> > @@ -1629,9 +1633,10 @@ static int skl_check_main_surface(struct
> > intel_plane_state *plane_state)
> > 
> >  	/*
> >  	 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
> > -	 * they match with the main surface x/y offsets.
> > +	 * they match with the main surface x/y offsets. On DG2
> > +	 * there's no aux plane on fb so skip this checking.
> >  	 */
> > -	if (intel_fb_is_ccs_modifier(fb->modifier)) {
> > +	if (intel_fb_is_ccs_modifier(fb->modifier) && aux_plane) {
> >  		while (!skl_check_main_ccs_coordinates(plane_state, x, y,
> >  						       offset, aux_plane)) {
> >  			if (offset == 0)
> > @@ -1675,6 +1680,8 @@ static int skl_check_nv12_aux_surface(struct
> > intel_plane_state *plane_state)
> >  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> >  	unsigned int rotation = plane_state->hw.rotation;
> >  	int uv_plane = 1;
> > +	int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ?
> > +			skl_main_to_aux_plane(fb, uv_plane) : 0;
> >  	int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation);
> >  	int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation);
> >  	int x = plane_state->uapi.src.x1 >> 17; @@ -1695,8 +1702,7 @@ static
> > int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
> >  	offset = intel_plane_compute_aligned_offset(&x, &y,
> >  						    plane_state, uv_plane);
> > 
> > -	if (intel_fb_is_ccs_modifier(fb->modifier)) {
> > -		int ccs_plane = main_to_ccs_plane(fb, uv_plane);
> > +	if (ccs_plane) {
> >  		u32 aux_offset = plane_state-
> > >view.color_plane[ccs_plane].offset;
> >  		u32 alignment = intel_surf_alignment(fb, uv_plane);
> > 
> > @@ -2438,10 +2444,15 @@ skl_get_initial_plane_config(struct intel_crtc *crtc,
> >  		break;
> >  	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> >  		if (HAS_4TILE(dev_priv)) {
> > -			if (val &
> > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > +			u32 rc_mask =
> > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> > +				      PLANE_CTL_CLEAR_COLOR_DISABLE;
> > +
> > +			if ((val & rc_mask) == rc_mask)
> >  				fb->modifier =
> > I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
> >  			else if (val &
> > PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
> >  				fb->modifier =
> > I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
> > +			else if (val &
> > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > +				fb->modifier =
> > I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
> >  			else
> >  				fb->modifier = I915_FORMAT_MOD_4_TILED;
> >  		} else {
> > --
> > 2.30.2
> 

Re: [Intel-gfx] [PATCH 4/4] drm/i915/dg2: Add support for DG2 clear color compression

[Gupta, Anshuman]

> -----Original Message-----
> From: Deak, Imre <imre.deak@intel.com>
> Sent: Thursday, April 7, 2022 6:59 PM
> To: Gupta, Anshuman <anshuman.gupta@intel.com>
> Cc: intel-gfx@lists.freedesktop.org; Kahola, Mika <mika.kahola@intel.com>;
> Heikkila, Juha-pekka <juha-pekka.heikkila@intel.com>; C, Ramalingam
> <ramalingam.c@intel.com>
> Subject: Re: [PATCH 4/4] drm/i915/dg2: Add support for DG2 clear color
> compression
> 
> On Thu, Apr 07, 2022 at 08:47:13AM +0300, Gupta, Anshuman wrote:
> > > -----Original Message-----
> > > From: Deak, Imre <imre.deak@intel.com>
> > > Sent: Monday, April 4, 2022 7:09 PM
> > > To: intel-gfx@lists.freedesktop.org
> > > Cc: Gupta, Anshuman <anshuman.gupta@intel.com>; Kahola, Mika
> > > <mika.kahola@intel.com>; Heikkila, Juha-pekka <juha-
> > > pekka.heikkila@intel.com>; C, Ramalingam <ramalingam.c@intel.com>
> > > Subject: [PATCH 4/4] drm/i915/dg2: Add support for DG2 clear color
> > > compression
> > >
> > > From: Anshuman Gupta <anshuman.gupta@intel.com>
> > >
> > > DG2 onwards discrete gfx has support for new flat CCS mapping, which
> > > brings in display feature in to avoid Aux walk for compressed
> > > surface. This support build on top of Flat CCS support added in
> > > XEHPSDV.  FLAT CCS surface base address should be 64k aligned,
> > > Compressed displayable surfaces must use tile4 format.
> >
> > IMHO commit log should also describe a bit of description for DG2
> > Clear color. Original patch was meant to add FLAT_CCS support, commit
> > log not fully aligns with commit header.
> >
> > May be it would be good if patch authorship changes to the DG2
> > original clear color author for any required follow-up later ?
> 
> I kept your authorship based on
> https://patchwork.freedesktop.org/patch/471775/?series=95686&rev=5
> 
> and then an Ack from you. But yes, there's been some changes since the support
> for DG2 CCS was originally added, with multiple people involved, so the
> authorship may be not accurate. I can update that along with the commit
> message.
Yes, earlier I overlooked the authorship part as, but with above.
Acked-by: Anshuman Gupta <anshuman.gupta@intel.com>

> 
> > > HAS: 1407880786
> > > B.Spec : 7655
> > > B.Spec : 53902
> > >
> > > v2: Merge all bits required for the support of functionality into this
> > >     patch from the patch adding the corresponding modifier.
> > >
> > > Cc: Mika Kahola <mika.kahola@intel.com>
> > > Signed-off-by: Anshuman Gupta <anshuman.gupta@intel.com>
> > > Signed-off-by: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > > Signed-off-by: Ramalingam C <ramalingam.c@intel.com>
> > > Signed-off-by: Imre Deak <imre.deak@intel.com>
> > > ---
> > >  drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
> > >  drivers/gpu/drm/i915/display/intel_fb.c       | 40 ++++++++++++++-----
> > >  .../drm/i915/display/skl_universal_plane.c    | 25 ++++++++----
> > >  3 files changed, 52 insertions(+), 17 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/display/intel_display.c
> > > b/drivers/gpu/drm/i915/display/intel_display.c
> > > index eee185ed41c3e..ca997a0a05174 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_display.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_display.c
> > > @@ -8477,7 +8477,9 @@ static void
> > > intel_atomic_prepare_plane_clear_colors(struct intel_atomic_state *s
> > >
> > >  		/*
> > >  		 * The layout of the fast clear color value expected by HW
> > > -		 * (the DRM ABI requiring this value to be located in fb at offset
> > > 0 of plane#2):
> > > +		 * (the DRM ABI requiring this value to be located in fb at
> > > +		 * offset 0 of cc plane, plane #2 previous generations or
> > > +		 * plane #1 for flat ccs):
> > >  		 * - 4 x 4 bytes per-channel value
> > >  		 *   (in surface type specific float/int format provided by the fb
> > > user)
> > >  		 * - 8 bytes native color value used by the display diff --git
> > > a/drivers/gpu/drm/i915/display/intel_fb.c
> > > b/drivers/gpu/drm/i915/display/intel_fb.c
> > > index 447003a91160e..9f5a6b79e95b5 100644
> > > --- a/drivers/gpu/drm/i915/display/intel_fb.c
> > > +++ b/drivers/gpu/drm/i915/display/intel_fb.c
> > > @@ -107,6 +107,21 @@ static const struct drm_format_info
> > > gen12_ccs_cc_formats[] = {
> > >  	  .hsub = 1, .vsub = 1, .has_alpha = true },  };
> > >
> > > +static const struct drm_format_info gen12_flat_ccs_cc_formats[] = {
> > > +	{ .format = DRM_FORMAT_XRGB8888, .depth = 24, .num_planes = 2,
> > > +	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > > +	  .hsub = 1, .vsub = 1, },
> > > +	{ .format = DRM_FORMAT_XBGR8888, .depth = 24, .num_planes = 2,
> > > +	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > > +	  .hsub = 1, .vsub = 1, },
> > > +	{ .format = DRM_FORMAT_ARGB8888, .depth = 32, .num_planes = 2,
> > > +	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > > +	  .hsub = 1, .vsub = 1, .has_alpha = true },
> > > +	{ .format = DRM_FORMAT_ABGR8888, .depth = 32, .num_planes = 2,
> > > +	  .char_per_block = { 4, 0 }, .block_w = { 1, 2 }, .block_h = { 1, 1 },
> > > +	  .hsub = 1, .vsub = 1, .has_alpha = true }, };
> > > +
> > >  struct intel_modifier_desc {
> > >  	u64 modifier;
> > >  	struct {
> > > @@ -144,6 +159,14 @@ static const struct intel_modifier_desc
> > > intel_modifiers[] = {
> > >  		.modifier = I915_FORMAT_MOD_4_TILED_DG2_MC_CCS,
> > >  		.display_ver = { 13, 13 },
> > >  		.plane_caps = INTEL_PLANE_CAP_TILING_4 |
> INTEL_PLANE_CAP_CCS_MC,
> > > +	}, {
> > > +		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC,
> > > +		.display_ver = { 13, 13 },
> > > +		.plane_caps = INTEL_PLANE_CAP_TILING_4 |
> > > INTEL_PLANE_CAP_CCS_RC_CC,
> > > +
> > > +		.ccs.cc_planes = BIT(1),
> > > +
> > > +		FORMAT_OVERRIDE(gen12_flat_ccs_cc_formats),
> > >  	}, {
> > >  		.modifier = I915_FORMAT_MOD_4_TILED_DG2_RC_CCS,
> > >  		.display_ver = { 13, 13 },
> > > @@ -393,17 +416,13 @@ bool intel_fb_plane_supports_modifier(struct
> > > intel_plane *plane, u64 modifier)  static bool
> > > format_is_yuv_semiplanar(const struct intel_modifier_desc *md,
> > >  				     const struct drm_format_info *info)  {
> > > -	int yuv_planes;
> > > -
> > >  	if (!info->is_yuv)
> > >  		return false;
> > >
> > > -	if (plane_caps_contain_any(md->plane_caps,
> > > INTEL_PLANE_CAP_CCS_MASK))
> > > -		yuv_planes = 4;
> > > +	if (hweight8(md->ccs.planar_aux_planes) == 2)
> > > +		return info->num_planes == 4;
> > >  	else
> > > -		yuv_planes = 2;
> > > -
> > > -	return info->num_planes == yuv_planes;
> > > +		return info->num_planes == 2;
> > >  }
> > >
> > >  /**
> > > @@ -528,12 +547,13 @@ static unsigned int
> > > gen12_ccs_aux_stride(struct intel_framebuffer *fb, int ccs_p
> > >
> > >  int skl_main_to_aux_plane(const struct drm_framebuffer *fb, int
> > > main_plane)  {
> > > +	const struct intel_modifier_desc *md =
> > > +lookup_modifier(fb->modifier);
> > >  	struct drm_i915_private *i915 = to_i915(fb->dev);
> > >
> > > -	if (intel_fb_is_ccs_modifier(fb->modifier))
> > > +	if (md->ccs.packed_aux_planes | md->ccs.planar_aux_planes)
> > >  		return main_to_ccs_plane(fb, main_plane);
> > >  	else if (DISPLAY_VER(i915) < 11 &&
> > > -		 intel_format_info_is_yuv_semiplanar(fb->format, fb-
> > > >modifier))
> > > +		 format_is_yuv_semiplanar(md, fb->format))
> > >  		return 1;
> > >  	else
> > >  		return 0;
> > > @@ -559,6 +579,7 @@ intel_tile_width_bytes(const struct
> > > drm_framebuffer *fb, int color_plane)
> > >  		else
> > >  			return 512;
> > >  	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> > > +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> > >  	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> > >  	case I915_FORMAT_MOD_4_TILED:
> > >  		/*
> > > @@ -763,6 +784,7 @@ unsigned int intel_surf_alignment(const struct
> > > drm_framebuffer *fb,
> > >  	case I915_FORMAT_MOD_Yf_TILED:
> > >  		return 1 * 1024 * 1024;
> > >  	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS:
> > > +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> > >  	case I915_FORMAT_MOD_4_TILED_DG2_MC_CCS:
> > >  		return 16 * 1024;
> > >  	default:
> > > diff --git a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > index b939c503bc6ff..caa03324a733a 100644
> > > --- a/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > +++ b/drivers/gpu/drm/i915/display/skl_universal_plane.c
> > > @@ -781,6 +781,8 @@ static u32 skl_plane_ctl_tiling(u64 fb_modifier)
> > >  		return PLANE_CTL_TILED_4 |
> > >  			PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE |
> > >  			PLANE_CTL_CLEAR_COLOR_DISABLE;
> > > +	case I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC:
> > > +		return PLANE_CTL_TILED_4 |
> > > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > >  	case I915_FORMAT_MOD_Y_TILED_CCS:
> > >  	case I915_FORMAT_MOD_Y_TILED_GEN12_RC_CCS_CC:
> > >  		return PLANE_CTL_TILED_Y |
> > > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE;
> > > @@ -1228,8 +1230,10 @@ icl_plane_update_noarm(struct intel_plane
> *plane,
> > >  				  upper_32_bits(plane_state->ccval));
> > >  	}
> > >
> > > -	intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
> > > -			  skl_plane_aux_dist(plane_state, color_plane));
> > > +	/* FLAT CCS doesn't need to program AUX_DIST */
> > > +	if (!HAS_FLAT_CCS(dev_priv))
> > > +		intel_de_write_fw(dev_priv, PLANE_AUX_DIST(pipe, plane_id),
> > > +				  skl_plane_aux_dist(plane_state, color_plane));
> > >
> > >  	if (icl_is_hdr_plane(dev_priv, plane_id))
> > >  		intel_de_write_fw(dev_priv, PLANE_CUS_CTL(pipe, plane_id),
> @@
> > > -1629,9 +1633,10 @@ static int skl_check_main_surface(struct
> > > intel_plane_state *plane_state)
> > >
> > >  	/*
> > >  	 * CCS AUX surface doesn't have its own x/y offsets, we must make sure
> > > -	 * they match with the main surface x/y offsets.
> > > +	 * they match with the main surface x/y offsets. On DG2
> > > +	 * there's no aux plane on fb so skip this checking.
> > >  	 */
> > > -	if (intel_fb_is_ccs_modifier(fb->modifier)) {
> > > +	if (intel_fb_is_ccs_modifier(fb->modifier) && aux_plane) {
> > >  		while (!skl_check_main_ccs_coordinates(plane_state, x, y,
> > >  						       offset, aux_plane)) {
> > >  			if (offset == 0)
> > > @@ -1675,6 +1680,8 @@ static int skl_check_nv12_aux_surface(struct
> > > intel_plane_state *plane_state)
> > >  	const struct drm_framebuffer *fb = plane_state->hw.fb;
> > >  	unsigned int rotation = plane_state->hw.rotation;
> > >  	int uv_plane = 1;
> > > +	int ccs_plane = intel_fb_is_ccs_modifier(fb->modifier) ?
> > > +			skl_main_to_aux_plane(fb, uv_plane) : 0;
> > >  	int max_width = intel_plane_max_width(plane, fb, uv_plane, rotation);
> > >  	int max_height = intel_plane_max_height(plane, fb, uv_plane, rotation);
> > >  	int x = plane_state->uapi.src.x1 >> 17; @@ -1695,8 +1702,7 @@
> > > static int skl_check_nv12_aux_surface(struct intel_plane_state *plane_state)
> > >  	offset = intel_plane_compute_aligned_offset(&x, &y,
> > >  						    plane_state, uv_plane);
> > >
> > > -	if (intel_fb_is_ccs_modifier(fb->modifier)) {
> > > -		int ccs_plane = main_to_ccs_plane(fb, uv_plane);
> > > +	if (ccs_plane) {
> > >  		u32 aux_offset = plane_state-
> > > >view.color_plane[ccs_plane].offset;
> > >  		u32 alignment = intel_surf_alignment(fb, uv_plane);
> > >
> > > @@ -2438,10 +2444,15 @@ skl_get_initial_plane_config(struct intel_crtc
> *crtc,
> > >  		break;
> > >  	case PLANE_CTL_TILED_YF: /* aka PLANE_CTL_TILED_4 on XE_LPD+ */
> > >  		if (HAS_4TILE(dev_priv)) {
> > > -			if (val &
> > > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > +			u32 rc_mask =
> > > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE |
> > > +				      PLANE_CTL_CLEAR_COLOR_DISABLE;
> > > +
> > > +			if ((val & rc_mask) == rc_mask)
> > >  				fb->modifier =
> > > I915_FORMAT_MOD_4_TILED_DG2_RC_CCS;
> > >  			else if (val &
> > > PLANE_CTL_MEDIA_DECOMPRESSION_ENABLE)
> > >  				fb->modifier =
> > > I915_FORMAT_MOD_4_TILED_DG2_MC_CCS;
> > > +			else if (val &
> > > PLANE_CTL_RENDER_DECOMPRESSION_ENABLE)
> > > +				fb->modifier =
> > > I915_FORMAT_MOD_4_TILED_DG2_RC_CCS_CC;
> > >  			else
> > >  				fb->modifier = I915_FORMAT_MOD_4_TILED;
> > >  		} else {
> > > --
> > > 2.30.2
> >

[Intel-gfx] ✗ Fi.CI.SPARSE: warning for drm/i915/dg2: Add support for render/media decompression

[Patchwork]

== Series Details ==

Series: drm/i915/dg2: Add support for render/media decompression
URL   : https://patchwork.freedesktop.org/series/102147/
State : warning

== Summary ==

$ dim sparse --fast origin/drm-tip
Sparse version: v0.6.2
Fast mode used, each commit won't be checked separately.
-
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+./drivers/gpu/drm/amd/amdgpu/../amdgpu/amdgv_sriovmsg.h:319:49: error: static assertion failed: "amd_sriov_msg_pf2vf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1444:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1444:25:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1444:25:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1445:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1445:17:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1445:17:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1504:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1504:17:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_debugfs.c:1504:17:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:353:16: error: incompatible types in comparison expression (different type sizes):
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:353:16:    unsigned long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_device.c:353:16:    unsigned long long *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:295:25:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:296:17:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:345:17: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:345:17:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:345:17:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:596:23: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:596:23:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:596:23:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:598:25: error: incompatible types in comparison expression (different address spaces):
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:598:25:    struct dma_fence *
+drivers/gpu/drm/amd/amdgpu/amdgpu_fence.c:598:25:    struct dma_fence [noderef] __rcu *
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf_info must be 1 KB"
+drivers/gpu/drm/amd/amdgpu/amdgv_sriovmsg.h:315:49: error: static assertion failed: "amd_sriov_msg_vf2pf

[Intel-gfx] ✓ Fi.CI.BAT: success for drm/i915/dg2: Add support for render/media decompression

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 3911 bytes --]

== Series Details ==

Series: drm/i915/dg2: Add support for render/media decompression
URL   : https://patchwork.freedesktop.org/series/102147/
State : success

== Summary ==

CI Bug Log - changes from CI_DRM_11449 -> Patchwork_22772
====================================================

Summary
-------

  **SUCCESS**

  No regressions found.

  External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/index.html

Participating hosts (49 -> 44)
------------------------------

  Missing    (5): shard-tglu fi-bsw-cyan fi-pnv-d510 shard-rkl fi-bdw-samus 

Known issues
------------

  Here are the changes found in Patchwork_22772 that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@amdgpu/amd_cs_nop@fork-gfx0:
    - fi-bsw-n3050:       NOTRUN -> [SKIP][1] ([fdo#109271]) +17 similar issues
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/fi-bsw-n3050/igt@amdgpu/amd_cs_nop@fork-gfx0.html

  * igt@kms_flip@basic-plain-flip@a-edp1:
    - fi-tgl-u2:          [PASS][2] -> [DMESG-WARN][3] ([i915#402])
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/fi-tgl-u2/igt@kms_flip@basic-plain-flip@a-edp1.html

  
#### Possible fixes ####

  * igt@i915_selftest@live@active:
    - fi-bsw-n3050:       [DMESG-FAIL][4] ([i915#2927]) -> [PASS][5]
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/fi-bsw-n3050/igt@i915_selftest@live@active.html
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/fi-bsw-n3050/igt@i915_selftest@live@active.html

  * igt@i915_selftest@live@migrate:
    - fi-bsw-n3050:       [DMESG-WARN][6] -> [PASS][7]
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/fi-bsw-n3050/igt@i915_selftest@live@migrate.html
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/fi-bsw-n3050/igt@i915_selftest@live@migrate.html

  * igt@kms_flip@basic-flip-vs-modeset@a-edp1:
    - fi-tgl-u2:          [DMESG-WARN][8] ([i915#402]) -> [PASS][9]
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/fi-tgl-u2/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/fi-tgl-u2/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
    - {bat-adlp-6}:       [DMESG-WARN][10] ([i915#3576]) -> [PASS][11]
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/bat-adlp-6/igt@kms_flip@basic-flip-vs-modeset@a-edp1.html

  
  {name}: This element is suppressed. This means it is ignored when computing
          the status of the difference (SUCCESS, WARNING, or FAILURE).

  [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
  [i915#2927]: https://gitlab.freedesktop.org/drm/intel/issues/2927
  [i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
  [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402


Build changes
-------------

  * Linux: CI_DRM_11449 -> Patchwork_22772

  CI-20190529: 20190529
  CI_DRM_11449: 7f954433d09e65d55ca3ba81e1eb5eced93d4203 @ git://anongit.freedesktop.org/gfx-ci/linux
  IGT_6409: 13700f4a3ffaac3a825fe59b014c7c6c48a0a5f1 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
  Patchwork_22772: d44933b98ff5991f71da44b3a378cb691207b37f @ git://anongit.freedesktop.org/gfx-ci/linux


== Linux commits ==

d44933b98ff5 drm/i915/dg2: Add support for DG2 clear color compression
7937967ebad2 drm/fourcc: Introduce format modifier for DG2 clear color
74c0fc95d8e6 drm/i915/dg2: Add support for DG2 render and media compression
f7e22d379215 drm/fourcc: Introduce format modifiers for DG2 render and media compression

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/index.html

[-- Attachment #2: Type: text/html, Size: 4752 bytes --]

[Intel-gfx] ✗ Fi.CI.IGT: failure for drm/i915/dg2: Add support for render/media decompression

[Patchwork]

[-- Attachment #1: Type: text/plain, Size: 30277 bytes --]

== Series Details ==

Series: drm/i915/dg2: Add support for render/media decompression
URL   : https://patchwork.freedesktop.org/series/102147/
State : failure

== Summary ==

CI Bug Log - changes from CI_DRM_11449_full -> Patchwork_22772_full
====================================================

Summary
-------

  **FAILURE**

  Serious unknown changes coming with Patchwork_22772_full absolutely need to be
  verified manually.
  
  If you think the reported changes have nothing to do with the changes
  introduced in Patchwork_22772_full, please notify your bug team to allow them
  to document this new failure mode, which will reduce false positives in CI.

  

Participating hosts (13 -> 12)
------------------------------

  Missing    (1): shard-dg1 

Possible new issues
-------------------

  Here are the unknown changes that may have been introduced in Patchwork_22772_full:

### IGT changes ###

#### Possible regressions ####

  * igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled:
    - shard-kbl:          [PASS][1] -> [INCOMPLETE][2]
   [1]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-kbl4/igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled.html
   [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl3/igt@kms_draw_crc@draw-method-xrgb2101010-blt-ytiled.html

  
Known issues
------------

  Here are the changes found in Patchwork_22772_full that come from known issues:

### IGT changes ###

#### Issues hit ####

  * igt@gem_create@create-massive:
    - shard-kbl:          NOTRUN -> [DMESG-WARN][3] ([i915#4991])
   [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl7/igt@gem_create@create-massive.html
    - shard-apl:          NOTRUN -> [DMESG-WARN][4] ([i915#4991])
   [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-apl4/igt@gem_create@create-massive.html

  * igt@gem_ctx_isolation@preservation-s3@bcs0:
    - shard-kbl:          [PASS][5] -> [DMESG-WARN][6] ([i915#180]) +2 similar issues
   [5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@bcs0.html
   [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@bcs0.html

  * igt@gem_eio@in-flight-contexts-10ms:
    - shard-tglb:         [PASS][7] -> [TIMEOUT][8] ([i915#3063])
   [7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-tglb1/igt@gem_eio@in-flight-contexts-10ms.html
   [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-tglb7/igt@gem_eio@in-flight-contexts-10ms.html

  * igt@gem_exec_create@legacy@smem:
    - shard-skl:          NOTRUN -> [DMESG-WARN][9] ([i915#1982])
   [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl9/igt@gem_exec_create@legacy@smem.html

  * igt@gem_exec_fair@basic-deadline:
    - shard-skl:          NOTRUN -> [FAIL][10] ([i915#2846])
   [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl7/igt@gem_exec_fair@basic-deadline.html
    - shard-glk:          [PASS][11] -> [FAIL][12] ([i915#2846])
   [11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-glk4/igt@gem_exec_fair@basic-deadline.html
   [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-glk8/igt@gem_exec_fair@basic-deadline.html

  * igt@gem_exec_fair@basic-flow@rcs0:
    - shard-tglb:         [PASS][13] -> [FAIL][14] ([i915#2842])
   [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-tglb5/igt@gem_exec_fair@basic-flow@rcs0.html
   [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-tglb1/igt@gem_exec_fair@basic-flow@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-kbl:          [PASS][15] -> [FAIL][16] ([i915#2842])
   [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-kbl7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl6/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_lmem_swapping@heavy-random:
    - shard-skl:          NOTRUN -> [SKIP][17] ([fdo#109271] / [i915#4613]) +1 similar issue
   [17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl6/igt@gem_lmem_swapping@heavy-random.html

  * igt@gem_lmem_swapping@heavy-verify-multi:
    - shard-apl:          NOTRUN -> [SKIP][18] ([fdo#109271] / [i915#4613])
   [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-apl1/igt@gem_lmem_swapping@heavy-verify-multi.html

  * igt@gem_lmem_swapping@random:
    - shard-iclb:         NOTRUN -> [SKIP][19] ([i915#4613])
   [19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-iclb7/igt@gem_lmem_swapping@random.html

  * igt@gem_pread@exhaustion:
    - shard-skl:          NOTRUN -> [WARN][20] ([i915#2658])
   [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl10/igt@gem_pread@exhaustion.html

  * igt@gem_softpin@allocator-evict-all-engines:
    - shard-glk:          [PASS][21] -> [FAIL][22] ([i915#4171])
   [21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-glk7/igt@gem_softpin@allocator-evict-all-engines.html
   [22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-glk2/igt@gem_softpin@allocator-evict-all-engines.html

  * igt@gem_softpin@softpin:
    - shard-glk:          [PASS][23] -> [DMESG-WARN][24] ([i915#118]) +1 similar issue
   [23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-glk2/igt@gem_softpin@softpin.html
   [24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-glk5/igt@gem_softpin@softpin.html

  * igt@gem_userptr_blits@input-checking:
    - shard-iclb:         NOTRUN -> [DMESG-WARN][25] ([i915#4991])
   [25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-iclb7/igt@gem_userptr_blits@input-checking.html

  * igt@i915_module_load@reload-with-fault-injection:
    - shard-skl:          [PASS][26] -> [DMESG-WARN][27] ([i915#1982]) +1 similar issue
   [26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-skl10/igt@i915_module_load@reload-with-fault-injection.html
   [27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl4/igt@i915_module_load@reload-with-fault-injection.html

  * igt@i915_pm_dc@dc6-dpms:
    - shard-skl:          NOTRUN -> [FAIL][28] ([i915#454]) +1 similar issue
   [28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl7/igt@i915_pm_dc@dc6-dpms.html

  * igt@i915_suspend@fence-restore-tiled2untiled:
    - shard-apl:          NOTRUN -> [DMESG-WARN][29] ([i915#180]) +1 similar issue
   [29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-apl1/igt@i915_suspend@fence-restore-tiled2untiled.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip:
    - shard-skl:          NOTRUN -> [SKIP][30] ([fdo#109271] / [i915#3777]) +5 similar issues
   [30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl9/igt@kms_big_fb@y-tiled-max-hw-stride-32bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip:
    - shard-apl:          NOTRUN -> [SKIP][31] ([fdo#109271] / [i915#3777]) +1 similar issue
   [31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-apl1/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-0-hflip-async-flip.html

  * igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][32] ([i915#3763])
   [32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl9/igt@kms_big_fb@y-tiled-max-hw-stride-64bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
    - shard-skl:          NOTRUN -> [FAIL][33] ([i915#3743])
   [33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl6/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html

  * igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip:
    - shard-kbl:          NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#3777]) +1 similar issue
   [34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl7/igt@kms_big_fb@yf-tiled-max-hw-stride-32bpp-rotate-180-hflip-async-flip.html

  * igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc:
    - shard-apl:          NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#3886]) +4 similar issues
   [35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-apl1/igt@kms_ccs@pipe-a-bad-aux-stride-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc:
    - shard-iclb:         NOTRUN -> [SKIP][36] ([fdo#109278] / [i915#3886])
   [36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-iclb7/igt@kms_ccs@pipe-a-missing-ccs-buffer-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc:
    - shard-skl:          NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#3886]) +13 similar issues
   [37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl4/igt@kms_ccs@pipe-c-bad-rotation-90-y_tiled_gen12_rc_ccs_cc.html

  * igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs:
    - shard-kbl:          NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#3886]) +2 similar issues
   [38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl3/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_mc_ccs.html

  * igt@kms_chamelium@vga-hpd:
    - shard-apl:          NOTRUN -> [SKIP][39] ([fdo#109271] / [fdo#111827]) +8 similar issues
   [39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-apl1/igt@kms_chamelium@vga-hpd.html
    - shard-skl:          NOTRUN -> [SKIP][40] ([fdo#109271] / [fdo#111827]) +22 similar issues
   [40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl1/igt@kms_chamelium@vga-hpd.html

  * igt@kms_color_chamelium@pipe-a-ctm-blue-to-red:
    - shard-kbl:          NOTRUN -> [SKIP][41] ([fdo#109271] / [fdo#111827]) +6 similar issues
   [41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl7/igt@kms_color_chamelium@pipe-a-ctm-blue-to-red.html

  * igt@kms_content_protection@lic:
    - shard-apl:          NOTRUN -> [TIMEOUT][42] ([i915#1319])
   [42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-apl1/igt@kms_content_protection@lic.html

  * igt@kms_content_protection@uevent:
    - shard-kbl:          NOTRUN -> [FAIL][43] ([i915#2105])
   [43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl7/igt@kms_content_protection@uevent.html

  * igt@kms_cursor_crc@pipe-c-cursor-suspend:
    - shard-kbl:          [PASS][44] -> [INCOMPLETE][45] ([i915#3614])
   [44]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-kbl6/igt@kms_cursor_crc@pipe-c-cursor-suspend.html
   [45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl4/igt@kms_cursor_crc@pipe-c-cursor-suspend.html

  * igt@kms_draw_crc@draw-method-rgb565-blt-4tiled:
    - shard-iclb:         NOTRUN -> [SKIP][46] ([i915#5287])
   [46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-iclb7/igt@kms_draw_crc@draw-method-rgb565-blt-4tiled.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled:
    - shard-kbl:          NOTRUN -> [SKIP][47] ([fdo#109271]) +102 similar issues
   [47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl7/igt@kms_draw_crc@draw-method-rgb565-mmap-gtt-4tiled.html

  * igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
    - shard-apl:          [PASS][48] -> [DMESG-WARN][49] ([i915#180]) +2 similar issues
   [48]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-apl7/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
   [49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-apl8/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html

  * igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1:
    - shard-skl:          [PASS][50] -> [FAIL][51] ([i915#2122]) +1 similar issue
   [50]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-skl4/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html
   [51]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl8/igt@kms_flip@plain-flip-fb-recreate-interruptible@b-edp1.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite:
    - shard-apl:          NOTRUN -> [SKIP][52] ([fdo#109271]) +95 similar issues
   [52]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-apl1/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-cur-indfb-draw-pwrite.html

  * igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc:
    - shard-iclb:         NOTRUN -> [SKIP][53] ([fdo#109280])
   [53]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-iclb7/igt@kms_frontbuffer_tracking@psr-2p-scndscrn-pri-indfb-draw-mmap-wc.html

  * igt@kms_hdr@bpc-switch@bpc-switch-edp-1-pipe-a:
    - shard-skl:          NOTRUN -> [FAIL][54] ([i915#1188])
   [54]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl4/igt@kms_hdr@bpc-switch@bpc-switch-edp-1-pipe-a.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-7efc:
    - shard-skl:          NOTRUN -> [FAIL][55] ([fdo#108145] / [i915#265]) +4 similar issues
   [55]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl9/igt@kms_plane_alpha_blend@pipe-a-alpha-7efc.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb:
    - shard-apl:          NOTRUN -> [FAIL][56] ([fdo#108145] / [i915#265])
   [56]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-apl1/igt@kms_plane_alpha_blend@pipe-a-alpha-opaque-fb.html

  * igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb:
    - shard-kbl:          NOTRUN -> [FAIL][57] ([i915#265])
   [57]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl7/igt@kms_plane_alpha_blend@pipe-a-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
    - shard-apl:          NOTRUN -> [FAIL][58] ([i915#265]) +2 similar issues
   [58]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-apl1/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
    - shard-skl:          NOTRUN -> [FAIL][59] ([i915#265])
   [59]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl4/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html

  * igt@kms_plane_alpha_blend@pipe-c-alpha-basic:
    - shard-kbl:          NOTRUN -> [FAIL][60] ([fdo#108145] / [i915#265])
   [60]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl3/igt@kms_plane_alpha_blend@pipe-c-alpha-basic.html

  * igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale:
    - shard-iclb:         [PASS][61] -> [SKIP][62] ([i915#5235]) +2 similar issues
   [61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-iclb8/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
   [62]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html

  * igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-edp-1-planes-upscale-downscale:
    - shard-skl:          NOTRUN -> [SKIP][63] ([fdo#109271]) +337 similar issues
   [63]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl10/igt@kms_plane_scaling@planes-upscale-factor-0-25-downscale-factor-0-25@pipe-a-edp-1-planes-upscale-downscale.html

  * igt@kms_psr2_sf@cursor-plane-move-continuous-sf:
    - shard-kbl:          NOTRUN -> [SKIP][64] ([fdo#109271] / [i915#658])
   [64]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl7/igt@kms_psr2_sf@cursor-plane-move-continuous-sf.html

  * igt@kms_psr2_su@page_flip-xrgb8888:
    - shard-skl:          NOTRUN -> [SKIP][65] ([fdo#109271] / [i915#658]) +2 similar issues
   [65]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl7/igt@kms_psr2_su@page_flip-xrgb8888.html

  * igt@kms_psr@psr2_primary_page_flip:
    - shard-iclb:         [PASS][66] -> [SKIP][67] ([fdo#109441]) +1 similar issue
   [66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-iclb2/igt@kms_psr@psr2_primary_page_flip.html
   [67]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-iclb6/igt@kms_psr@psr2_primary_page_flip.html

  * igt@kms_vblank@pipe-a-ts-continuation-suspend:
    - shard-kbl:          [PASS][68] -> [DMESG-WARN][69] ([i915#180] / [i915#295])
   [68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-kbl4/igt@kms_vblank@pipe-a-ts-continuation-suspend.html
   [69]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl6/igt@kms_vblank@pipe-a-ts-continuation-suspend.html

  * igt@kms_vblank@pipe-d-wait-forked-hang:
    - shard-iclb:         NOTRUN -> [SKIP][70] ([fdo#109278])
   [70]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-iclb7/igt@kms_vblank@pipe-d-wait-forked-hang.html

  * igt@kms_vblank@pipe-d-wait-idle:
    - shard-skl:          NOTRUN -> [SKIP][71] ([fdo#109271] / [i915#533]) +1 similar issue
   [71]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl9/igt@kms_vblank@pipe-d-wait-idle.html

  * igt@kms_writeback@writeback-check-output:
    - shard-apl:          NOTRUN -> [SKIP][72] ([fdo#109271] / [i915#2437])
   [72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-apl1/igt@kms_writeback@writeback-check-output.html
    - shard-skl:          NOTRUN -> [SKIP][73] ([fdo#109271] / [i915#2437])
   [73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl1/igt@kms_writeback@writeback-check-output.html

  * igt@kms_writeback@writeback-pixel-formats:
    - shard-kbl:          NOTRUN -> [SKIP][74] ([fdo#109271] / [i915#2437])
   [74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl3/igt@kms_writeback@writeback-pixel-formats.html

  * igt@sysfs_clients@fair-0:
    - shard-skl:          NOTRUN -> [SKIP][75] ([fdo#109271] / [i915#2994]) +5 similar issues
   [75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl7/igt@sysfs_clients@fair-0.html

  * igt@sysfs_clients@recycle:
    - shard-kbl:          NOTRUN -> [SKIP][76] ([fdo#109271] / [i915#2994])
   [76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl7/igt@sysfs_clients@recycle.html

  
#### Possible fixes ####

  * igt@gem_ctx_isolation@preservation-s3@vcs0:
    - shard-kbl:          [DMESG-WARN][77] ([i915#180]) -> [PASS][78] +4 similar issues
   [77]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-kbl6/igt@gem_ctx_isolation@preservation-s3@vcs0.html
   [78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-kbl1/igt@gem_ctx_isolation@preservation-s3@vcs0.html

  * igt@gem_eio@in-flight-contexts-1us:
    - shard-tglb:         [TIMEOUT][79] ([i915#3063]) -> [PASS][80] +1 similar issue
   [79]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-tglb5/igt@gem_eio@in-flight-contexts-1us.html
   [80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-tglb5/igt@gem_eio@in-flight-contexts-1us.html

  * igt@gem_eio@suspend:
    - {shard-rkl}:        [FAIL][81] ([i915#5115]) -> [PASS][82]
   [81]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-rkl-5/igt@gem_eio@suspend.html
   [82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-rkl-1/igt@gem_eio@suspend.html

  * igt@gem_eio@unwedge-stress:
    - shard-tglb:         [FAIL][83] ([i915#232]) -> [PASS][84]
   [83]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-tglb5/igt@gem_eio@unwedge-stress.html
   [84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-tglb7/igt@gem_eio@unwedge-stress.html

  * igt@gem_exec_capture@pi@vecs0:
    - shard-skl:          [INCOMPLETE][85] ([i915#4547]) -> [PASS][86]
   [85]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-skl4/igt@gem_exec_capture@pi@vecs0.html
   [86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl10/igt@gem_exec_capture@pi@vecs0.html

  * igt@gem_exec_fair@basic-none@vcs0:
    - shard-apl:          [FAIL][87] ([i915#2842]) -> [PASS][88] +1 similar issue
   [87]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-apl3/igt@gem_exec_fair@basic-none@vcs0.html
   [88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-apl4/igt@gem_exec_fair@basic-none@vcs0.html

  * igt@gem_exec_fair@basic-pace-share@rcs0:
    - shard-tglb:         [FAIL][89] ([i915#2842]) -> [PASS][90]
   [89]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-tglb7/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-tglb3/igt@gem_exec_fair@basic-pace-share@rcs0.html
    - {shard-tglu}:       [FAIL][91] ([i915#2842]) -> [PASS][92]
   [91]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-tglu-3/igt@gem_exec_fair@basic-pace-share@rcs0.html
   [92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-tglu-1/igt@gem_exec_fair@basic-pace-share@rcs0.html

  * igt@gem_exec_fair@basic-pace-solo@rcs0:
    - shard-glk:          [FAIL][93] ([i915#2842]) -> [PASS][94] +1 similar issue
   [93]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-glk7/igt@gem_exec_fair@basic-pace-solo@rcs0.html
   [94]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-glk5/igt@gem_exec_fair@basic-pace-solo@rcs0.html

  * igt@gem_exec_fair@basic-throttle@rcs0:
    - shard-iclb:         [FAIL][95] ([i915#2849]) -> [PASS][96]
   [95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html
   [96]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-iclb5/igt@gem_exec_fair@basic-throttle@rcs0.html

  * igt@gem_exec_whisper@basic-normal-all:
    - shard-glk:          [DMESG-WARN][97] ([i915#118]) -> [PASS][98]
   [97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-glk3/igt@gem_exec_whisper@basic-normal-all.html
   [98]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-glk4/igt@gem_exec_whisper@basic-normal-all.html

  * igt@gem_softpin@invalid:
    - shard-skl:          [DMESG-WARN][99] ([i915#1982]) -> [PASS][100]
   [99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-skl4/igt@gem_softpin@invalid.html
   [100]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl6/igt@gem_softpin@invalid.html

  * igt@gem_softpin@noreloc-s3:
    - shard-skl:          [INCOMPLETE][101] ([i915#1373] / [i915#4939] / [i915#5230]) -> [PASS][102]
   [101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-skl9/igt@gem_softpin@noreloc-s3.html
   [102]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl8/igt@gem_softpin@noreloc-s3.html

  * igt@i915_pm_backlight@fade_with_suspend:
    - shard-skl:          [INCOMPLETE][103] ([i915#4939]) -> [PASS][104]
   [103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-skl4/igt@i915_pm_backlight@fade_with_suspend.html
   [104]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl6/igt@i915_pm_backlight@fade_with_suspend.html

  * igt@i915_pm_dc@dc6-psr:
    - shard-iclb:         [FAIL][105] ([i915#454]) -> [PASS][106]
   [105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-iclb6/igt@i915_pm_dc@dc6-psr.html
   [106]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-iclb2/igt@i915_pm_dc@dc6-psr.html

  * igt@i915_pm_rpm@drm-resources-equal:
    - {shard-rkl}:        [SKIP][107] ([fdo#109308]) -> [PASS][108]
   [107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-rkl-2/igt@i915_pm_rpm@drm-resources-equal.html
   [108]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-rkl-6/igt@i915_pm_rpm@drm-resources-equal.html

  * igt@i915_pm_rpm@system-suspend-devices:
    - {shard-rkl}:        [FAIL][109] -> [PASS][110]
   [109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-rkl-5/igt@i915_pm_rpm@system-suspend-devices.html
   [110]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-rkl-1/igt@i915_pm_rpm@system-suspend-devices.html

  * igt@kms_color@pipe-a-ctm-green-to-red:
    - {shard-rkl}:        [SKIP][111] ([i915#1149] / [i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][112] +2 similar issues
   [111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-rkl-2/igt@kms_color@pipe-a-ctm-green-to-red.html
   [112]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-rkl-6/igt@kms_color@pipe-a-ctm-green-to-red.html

  * igt@kms_color@pipe-c-invalid-degamma-lut-sizes:
    - {shard-rkl}:        [SKIP][113] ([i915#4070]) -> [PASS][114] +2 similar issues
   [113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-rkl-6/igt@kms_color@pipe-c-invalid-degamma-lut-sizes.html
   [114]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-rkl-5/igt@kms_color@pipe-c-invalid-degamma-lut-sizes.html

  * igt@kms_concurrent@pipe-a:
    - {shard-rkl}:        [SKIP][115] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][116]
   [115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-rkl-2/igt@kms_concurrent@pipe-a.html
   [116]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-rkl-6/igt@kms_concurrent@pipe-a.html

  * igt@kms_cursor_crc@pipe-b-cursor-64x64-random:
    - {shard-rkl}:        [SKIP][117] ([fdo#112022] / [i915#4070]) -> [PASS][118] +6 similar issues
   [117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-rkl-2/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html
   [118]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-rkl-6/igt@kms_cursor_crc@pipe-b-cursor-64x64-random.html

  * igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge:
    - {shard-rkl}:        [SKIP][119] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][120] +5 similar issues
   [119]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-rkl-1/igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge.html
   [120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-b-256x256-right-edge.html

  * igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions:
    - {shard-rkl}:        [SKIP][121] ([fdo#111825] / [i915#4070]) -> [PASS][122] +2 similar issues
   [121]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-rkl-2/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions.html
   [122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-rkl-6/igt@kms_cursor_legacy@cursora-vs-flipa-atomic-transitions.html

  * igt@kms_cursor_legacy@flip-vs-cursor-varying-size:
    - shard-iclb:         [FAIL][123] ([i915#2346]) -> [PASS][124]
   [123]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-iclb7/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html
   [124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-iclb3/igt@kms_cursor_legacy@flip-vs-cursor-varying-size.html

  * igt@kms_dp_aux_dev:
    - {shard-rkl}:        [SKIP][125] ([i915#1257]) -> [PASS][126]
   [125]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-rkl-2/igt@kms_dp_aux_dev.html
   [126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-rkl-6/igt@kms_dp_aux_dev.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-untiled:
    - shard-glk:          [FAIL][127] ([i915#5160]) -> [PASS][128]
   [127]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-glk9/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-untiled.html
   [128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-glk6/igt@kms_draw_crc@draw-method-rgb565-mmap-cpu-untiled.html

  * igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled:
    - {shard-rkl}:        [SKIP][129] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][130] +7 similar issues
   [129]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-rkl-1/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html
   [130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-rkl-6/igt@kms_draw_crc@draw-method-rgb565-mmap-wc-ytiled.html

  * igt@kms_fbcon_fbt@fbc-suspend:
    - shard-apl:          [INCOMPLETE][131] ([i915#180]) -> [PASS][132]
   [131]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-apl3/igt@kms_fbcon_fbt@fbc-suspend.html
   [132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-apl1/igt@kms_fbcon_fbt@fbc-suspend.html

  * igt@kms_flip@flip-vs-expired-vblank@a-edp1:
    - shard-skl:          [FAIL][133] ([i915#79]) -> [PASS][134]
   [133]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-skl1/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html
   [134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-skl7/igt@kms_flip@flip-vs-expired-vblank@a-edp1.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling:
    - shard-iclb:         [SKIP][135] ([i915#3701]) -> [PASS][136]
   [135]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-iclb2/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html
   [136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-iclb6/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-32bpp-ytileccs-downscaling.html

  * igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling:
    - shard-glk:          [FAIL][137] ([i915#4911]) -> [PASS][138]
   [137]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-glk8/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html
   [138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-glk3/igt@kms_flip_scaled_crc@flip-32bpp-ytile-to-64bpp-ytile-upscaling.html

  * igt@kms_invalid_mode@zero-hdisplay:
    - {shard-rkl}:        [SKIP][139] ([i915#4278]) -> [PASS][140]
   [139]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11449/shard-rkl-5/igt@kms_invalid_mode@zero-hdisplay.html
   [140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/shard-rkl-6/igt@kms_invalid_mode@zero-hdisplay.html

  * igt@kms_pipe_crc_basic@nonblocking-crc-pipe-b:
    - {shard-rkl}:

== Logs ==

For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22772/index.html

[-- Attachment #2: Type: text/html, Size: 33395 bytes --]

Re: [Intel-gfx] [PATCH 0/4] drm/i915/dg2: Add support for render/media decompression

[Jani Nikula]

On Mon, 04 Apr 2022, Imre Deak <imre.deak@intel.com> wrote:
> This is a rebased version of patches 15-17 of [1], adding DG2 display
> engine support for decompressing render and media compressed
> framebuffers.
>
> The dependency patches from [1] should be merged already to drm-tip.
>
> It addresses the review comments on the modifier layout description from
> Nanley, updates the commit logs vs. flat CCS and Tile4 and splits out
> the changes adding the modifiers to drm_fourcc.h to separate patches.

Cc'd a bunch more people; ack on merging patches 2 & 4 via drm-intel?

BR,
Jani.


>
> [1] https://patchwork.freedesktop.org/series/95686/
>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> Cc: Nanley Chery <nanley.g.chery@intel.com>
>
> Anshuman Gupta (1):
>   drm/i915/dg2: Add support for DG2 clear color compression
>
> Matt Roper (2):
>   drm/fourcc: Introduce format modifiers for DG2 render and media
>     compression
>   drm/i915/dg2: Add support for DG2 render and media compression
>
> Mika Kahola (1):
>   drm/fourcc: Introduce format modifier for DG2 clear color
>
>  drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
>  drivers/gpu/drm/i915/display/intel_fb.c       | 53 +++++++++++++++----
>  .../drm/i915/display/skl_universal_plane.c    | 49 +++++++++++++----
>  include/uapi/drm/drm_fourcc.h                 | 36 +++++++++++++
>  4 files changed, 122 insertions(+), 20 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 0/4] drm/i915/dg2: Add support for render/media decompression

[Jani Nikula]

On Mon, 04 Apr 2022, Imre Deak <imre.deak@intel.com> wrote:
> This is a rebased version of patches 15-17 of [1], adding DG2 display
> engine support for decompressing render and media compressed
> framebuffers.
>
> The dependency patches from [1] should be merged already to drm-tip.
>
> It addresses the review comments on the modifier layout description from
> Nanley, updates the commit logs vs. flat CCS and Tile4 and splits out
> the changes adding the modifiers to drm_fourcc.h to separate patches.

Cc'd a bunch more people; ack on merging patches 2 & 4 via drm-intel?

BR,
Jani.


>
> [1] https://patchwork.freedesktop.org/series/95686/
>
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> Cc: Nanley Chery <nanley.g.chery@intel.com>
>
> Anshuman Gupta (1):
>   drm/i915/dg2: Add support for DG2 clear color compression
>
> Matt Roper (2):
>   drm/fourcc: Introduce format modifiers for DG2 render and media
>     compression
>   drm/i915/dg2: Add support for DG2 render and media compression
>
> Mika Kahola (1):
>   drm/fourcc: Introduce format modifier for DG2 clear color
>
>  drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
>  drivers/gpu/drm/i915/display/intel_fb.c       | 53 +++++++++++++++----
>  .../drm/i915/display/skl_universal_plane.c    | 49 +++++++++++++----
>  include/uapi/drm/drm_fourcc.h                 | 36 +++++++++++++
>  4 files changed, 122 insertions(+), 20 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 0/4] drm/i915/dg2: Add support for render/media decompression

[Jani Nikula]

On Fri, 08 Apr 2022, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Mon, 04 Apr 2022, Imre Deak <imre.deak@intel.com> wrote:
>> This is a rebased version of patches 15-17 of [1], adding DG2 display
>> engine support for decompressing render and media compressed
>> framebuffers.
>>
>> The dependency patches from [1] should be merged already to drm-tip.
>>
>> It addresses the review comments on the modifier layout description from
>> Nanley, updates the commit logs vs. flat CCS and Tile4 and splits out
>> the changes adding the modifiers to drm_fourcc.h to separate patches.
>
> Cc'd a bunch more people; ack on merging patches 2 & 4 via drm-intel?

Both off by one, I mean 1 & 3.

>
> BR,
> Jani.
>
>
>>
>> [1] https://patchwork.freedesktop.org/series/95686/
>>
>> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
>> Cc: Ramalingam C <ramalingam.c@intel.com>
>> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Mika Kahola <mika.kahola@intel.com>
>> Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
>> Cc: Nanley Chery <nanley.g.chery@intel.com>
>>
>> Anshuman Gupta (1):
>>   drm/i915/dg2: Add support for DG2 clear color compression
>>
>> Matt Roper (2):
>>   drm/fourcc: Introduce format modifiers for DG2 render and media
>>     compression
>>   drm/i915/dg2: Add support for DG2 render and media compression
>>
>> Mika Kahola (1):
>>   drm/fourcc: Introduce format modifier for DG2 clear color
>>
>>  drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
>>  drivers/gpu/drm/i915/display/intel_fb.c       | 53 +++++++++++++++----
>>  .../drm/i915/display/skl_universal_plane.c    | 49 +++++++++++++----
>>  include/uapi/drm/drm_fourcc.h                 | 36 +++++++++++++
>>  4 files changed, 122 insertions(+), 20 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 0/4] drm/i915/dg2: Add support for render/media decompression

[Jani Nikula]

On Fri, 08 Apr 2022, Jani Nikula <jani.nikula@linux.intel.com> wrote:
> On Mon, 04 Apr 2022, Imre Deak <imre.deak@intel.com> wrote:
>> This is a rebased version of patches 15-17 of [1], adding DG2 display
>> engine support for decompressing render and media compressed
>> framebuffers.
>>
>> The dependency patches from [1] should be merged already to drm-tip.
>>
>> It addresses the review comments on the modifier layout description from
>> Nanley, updates the commit logs vs. flat CCS and Tile4 and splits out
>> the changes adding the modifiers to drm_fourcc.h to separate patches.
>
> Cc'd a bunch more people; ack on merging patches 2 & 4 via drm-intel?

Both off by one, I mean 1 & 3.

>
> BR,
> Jani.
>
>
>>
>> [1] https://patchwork.freedesktop.org/series/95686/
>>
>> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
>> Cc: Ramalingam C <ramalingam.c@intel.com>
>> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Mika Kahola <mika.kahola@intel.com>
>> Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
>> Cc: Nanley Chery <nanley.g.chery@intel.com>
>>
>> Anshuman Gupta (1):
>>   drm/i915/dg2: Add support for DG2 clear color compression
>>
>> Matt Roper (2):
>>   drm/fourcc: Introduce format modifiers for DG2 render and media
>>     compression
>>   drm/i915/dg2: Add support for DG2 render and media compression
>>
>> Mika Kahola (1):
>>   drm/fourcc: Introduce format modifier for DG2 clear color
>>
>>  drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
>>  drivers/gpu/drm/i915/display/intel_fb.c       | 53 +++++++++++++++----
>>  .../drm/i915/display/skl_universal_plane.c    | 49 +++++++++++++----
>>  include/uapi/drm/drm_fourcc.h                 | 36 +++++++++++++
>>  4 files changed, 122 insertions(+), 20 deletions(-)

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 0/4] drm/i915/dg2: Add support for render/media decompression

[Imre Deak]

Hi Rodrigo, Jani,

On Mon, Apr 04, 2022 at 04:38:42PM +0300, Imre Deak wrote:
> This is a rebased version of patches 15-17 of [1], adding DG2 display
> engine support for decompressing render and media compressed
> framebuffers.
> 
> The dependency patches from [1] should be merged already to drm-tip.
> 
> It addresses the review comments on the modifier layout description from
> Nanley, updates the commit logs vs. flat CCS and Tile4 and splits out
> the changes adding the modifiers to drm_fourcc.h to separate patches.
> 
> [1] https://patchwork.freedesktop.org/series/95686/
> 
> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> Cc: Ramalingam C <ramalingam.c@intel.com>
> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Mika Kahola <mika.kahola@intel.com>
> Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> Cc: Nanley Chery <nanley.g.chery@intel.com>

I'd like to push this patchset to drm-intel-next, but it depends on
https://patchwork.freedesktop.org/patch/475167/?series=100419&rev=1

which is only in drm-intel-gt-next. According to Joonas, this should be
resolved by backmerging drm-intel-gt-next to drm-intel-next, could you
help with this?

> Anshuman Gupta (1):
>   drm/i915/dg2: Add support for DG2 clear color compression
> 
> Matt Roper (2):
>   drm/fourcc: Introduce format modifiers for DG2 render and media
>     compression
>   drm/i915/dg2: Add support for DG2 render and media compression
> 
> Mika Kahola (1):
>   drm/fourcc: Introduce format modifier for DG2 clear color
> 
>  drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
>  drivers/gpu/drm/i915/display/intel_fb.c       | 53 +++++++++++++++----
>  .../drm/i915/display/skl_universal_plane.c    | 49 +++++++++++++----
>  include/uapi/drm/drm_fourcc.h                 | 36 +++++++++++++
>  4 files changed, 122 insertions(+), 20 deletions(-)
> 
> -- 
> 2.30.2
> 

Re: [Intel-gfx] [PATCH 0/4] drm/i915/dg2: Add support for render/media decompression

[Vivi, Rodrigo]

On Mon, 2022-04-11 at 15:38 +0300, Imre Deak wrote:
> Hi Rodrigo, Jani,
> 
> On Mon, Apr 04, 2022 at 04:38:42PM +0300, Imre Deak wrote:
> > This is a rebased version of patches 15-17 of [1], adding DG2
> > display
> > engine support for decompressing render and media compressed
> > framebuffers.
> > 
> > The dependency patches from [1] should be merged already to drm-
> > tip.
> > 
> > It addresses the review comments on the modifier layout description
> > from
> > Nanley, updates the commit logs vs. flat CCS and Tile4 and splits
> > out
> > the changes adding the modifiers to drm_fourcc.h to separate
> > patches.
> > 
> > [1] https://patchwork.freedesktop.org/series/95686/
> > 
> > Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> > Cc: Ramalingam C <ramalingam.c@intel.com>
> > Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> > Cc: Matt Roper <matthew.d.roper@intel.com>
> > Cc: Mika Kahola <mika.kahola@intel.com>
> > Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> > Cc: Nanley Chery <nanley.g.chery@intel.com>
> 
> I'd like to push this patchset to drm-intel-next, but it depends on
> https://patchwork.freedesktop.org/patch/475167/?series=100419&rev=1
> 
> which is only in drm-intel-gt-next. According to Joonas, this should
> be
> resolved by backmerging drm-intel-gt-next to drm-intel-next, could
> you
> help with this?

+Tvrtko.

Jani is taking care of the drm-intel-next this round.
Based on our previous experiences with this kind of conflicts I agree
with Joonas. I also believe it is a good idea to backmerge the -gt-next
when needed.

But whenever we do this wee need to be careful when sending the
drm-intel-next pull request. We should ideally get the -gt-next pull
request merged to drm-next before doing the drm-intel-next PR, so 
we guarantee it was approved already and we also don't duplicate the
commits in the PR.

That sad, the PRs will need to be in sync and the window of -gt-next
should close a bit earlier on begin of -rc5 in case of an existent
backmerge in drm-intel-next... and avoid -rc6 PRs.

> 
> > Anshuman Gupta (1):
> >   drm/i915/dg2: Add support for DG2 clear color compression
> > 
> > Matt Roper (2):
> >   drm/fourcc: Introduce format modifiers for DG2 render and media
> >     compression
> >   drm/i915/dg2: Add support for DG2 render and media compression
> > 
> > Mika Kahola (1):
> >   drm/fourcc: Introduce format modifier for DG2 clear color
> > 
> >  drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
> >  drivers/gpu/drm/i915/display/intel_fb.c       | 53
> > +++++++++++++++----
> >  .../drm/i915/display/skl_universal_plane.c    | 49 +++++++++++++--
> > --
> >  include/uapi/drm/drm_fourcc.h                 | 36 +++++++++++++
> >  4 files changed, 122 insertions(+), 20 deletions(-)
> > 
> > -- 
> > 2.30.2
> > 

Re: [Intel-gfx] [PATCH 0/4] drm/i915/dg2: Add support for render/media decompression

[Jani Nikula]

On Mon, 11 Apr 2022, Imre Deak <imre.deak@intel.com> wrote:
> Hi Rodrigo, Jani,

TL;DR, all done, for details read on. ;)

> On Mon, Apr 04, 2022 at 04:38:42PM +0300, Imre Deak wrote:
>> This is a rebased version of patches 15-17 of [1], adding DG2 display
>> engine support for decompressing render and media compressed
>> framebuffers.
>> 
>> The dependency patches from [1] should be merged already to drm-tip.
>> 
>> It addresses the review comments on the modifier layout description from
>> Nanley, updates the commit logs vs. flat CCS and Tile4 and splits out
>> the changes adding the modifiers to drm_fourcc.h to separate patches.
>> 
>> [1] https://patchwork.freedesktop.org/series/95686/
>> 
>> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
>> Cc: Ramalingam C <ramalingam.c@intel.com>
>> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Mika Kahola <mika.kahola@intel.com>
>> Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
>> Cc: Nanley Chery <nanley.g.chery@intel.com>
>
> I'd like to push this patchset to drm-intel-next, but it depends on
> https://patchwork.freedesktop.org/patch/475167/?series=100419&rev=1

Please reference commits, looking that up is just an extra step for me.

> which is only in drm-intel-gt-next. According to Joonas, this should be
> resolved by backmerging drm-intel-gt-next to drm-intel-next, could you
> help with this?

To set the record straight, we don't crossmerge drm-intel-gt-next to
drm-intel-next. The other direction is possible. These are the valid
merges:

drm-intel-next -> drm-next		feature pull
drm-intel-gt-next -> drm-next		feature pull
drm-next -> drm-intel-next		backmerge
drm-next -> drm-intel-gt-next		backmerge
drm-intel-next -> drm-intel-gt-next	crossmerge
topic/* -> *				topic merge

Anyway, drm-intel-gt-next with the commit in question 5e3094cfd9fb
("drm/i915/xehpsdv: Add has_flat_ccs to device info") has already been
merged to drm-next and -rc1. I've done a backmerge and pushed it out.

Because we don't do drm-intel-gt-next -> drm-intel-next crossmerges, it
might be better to apply things like feature flags to drm-intel-next,
because the route from gt back to drm-intel-next is longer.

I might be prudent to trigger a retest with the new baseline before
merging.


BR,
Jani.

>
>> Anshuman Gupta (1):
>>   drm/i915/dg2: Add support for DG2 clear color compression
>> 
>> Matt Roper (2):
>>   drm/fourcc: Introduce format modifiers for DG2 render and media
>>     compression
>>   drm/i915/dg2: Add support for DG2 render and media compression
>> 
>> Mika Kahola (1):
>>   drm/fourcc: Introduce format modifier for DG2 clear color
>> 
>>  drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
>>  drivers/gpu/drm/i915/display/intel_fb.c       | 53 +++++++++++++++----
>>  .../drm/i915/display/skl_universal_plane.c    | 49 +++++++++++++----
>>  include/uapi/drm/drm_fourcc.h                 | 36 +++++++++++++
>>  4 files changed, 122 insertions(+), 20 deletions(-)
>> 
>> -- 
>> 2.30.2
>> 

-- 
Jani Nikula, Intel Open Source Graphics Center

Re: [Intel-gfx] [PATCH 0/4] drm/i915/dg2: Add support for render/media decompression

[Imre Deak]

On Mon, Apr 11, 2022 at 04:38:16PM +0300, Jani Nikula wrote:
> On Mon, 11 Apr 2022, Imre Deak <imre.deak@intel.com> wrote:
> > Hi Rodrigo, Jani,
> 
> TL;DR, all done, for details read on. ;)
> 
> > On Mon, Apr 04, 2022 at 04:38:42PM +0300, Imre Deak wrote:
> >> This is a rebased version of patches 15-17 of [1], adding DG2 display
> >> engine support for decompressing render and media compressed
> >> framebuffers.
> >> 
> >> The dependency patches from [1] should be merged already to drm-tip.
> >> 
> >> It addresses the review comments on the modifier layout description from
> >> Nanley, updates the commit logs vs. flat CCS and Tile4 and splits out
> >> the changes adding the modifiers to drm_fourcc.h to separate patches.
> >> 
> >> [1] https://patchwork.freedesktop.org/series/95686/
> >> 
> >> Cc: Anshuman Gupta <anshuman.gupta@intel.com>
> >> Cc: Ramalingam C <ramalingam.c@intel.com>
> >> Cc: Radhakrishna Sripada <radhakrishna.sripada@intel.com>
> >> Cc: Matt Roper <matthew.d.roper@intel.com>
> >> Cc: Mika Kahola <mika.kahola@intel.com>
> >> Cc: Juha-Pekka Heikkilä <juha-pekka.heikkila@intel.com>
> >> Cc: Nanley Chery <nanley.g.chery@intel.com>
> >
> > I'd like to push this patchset to drm-intel-next, but it depends on
> > https://patchwork.freedesktop.org/patch/475167/?series=100419&rev=1
> 
> Please reference commits, looking that up is just an extra step for me.
> 
> > which is only in drm-intel-gt-next. According to Joonas, this should be
> > resolved by backmerging drm-intel-gt-next to drm-intel-next, could you
> > help with this?
> 
> To set the record straight, we don't crossmerge drm-intel-gt-next to
> drm-intel-next. The other direction is possible. These are the valid
> merges:
> 
> drm-intel-next -> drm-next		feature pull
> drm-intel-gt-next -> drm-next		feature pull
> drm-next -> drm-intel-next		backmerge
> drm-next -> drm-intel-gt-next		backmerge
> drm-intel-next -> drm-intel-gt-next	crossmerge
> topic/* -> *				topic merge
> 
> Anyway, drm-intel-gt-next with the commit in question 5e3094cfd9fb
> ("drm/i915/xehpsdv: Add has_flat_ccs to device info") has already been
> merged to drm-next and -rc1. I've done a backmerge and pushed it out.
> 
> Because we don't do drm-intel-gt-next -> drm-intel-next crossmerges, it
> might be better to apply things like feature flags to drm-intel-next,
> because the route from gt back to drm-intel-next is longer.
> 
> I might be prudent to trigger a retest with the new baseline before
> merging.

Ok thanks for the explanation, resent the patchset now for retesting.

> BR,
> Jani.
> 
> >
> >> Anshuman Gupta (1):
> >>   drm/i915/dg2: Add support for DG2 clear color compression
> >> 
> >> Matt Roper (2):
> >>   drm/fourcc: Introduce format modifiers for DG2 render and media
> >>     compression
> >>   drm/i915/dg2: Add support for DG2 render and media compression
> >> 
> >> Mika Kahola (1):
> >>   drm/fourcc: Introduce format modifier for DG2 clear color
> >> 
> >>  drivers/gpu/drm/i915/display/intel_display.c  |  4 +-
> >>  drivers/gpu/drm/i915/display/intel_fb.c       | 53 +++++++++++++++----
> >>  .../drm/i915/display/skl_universal_plane.c    | 49 +++++++++++++----
> >>  include/uapi/drm/drm_fourcc.h                 | 36 +++++++++++++
> >>  4 files changed, 122 insertions(+), 20 deletions(-)
> >> 
> >> -- 
> >> 2.30.2
> >> 
> 
> -- 
> Jani Nikula, Intel Open Source Graphics Center