[PATCH 0/8] ram: k3-ddrss: Enable DDRSS ECC for full DDR Space

[PATCH 0/8] ram: k3-ddrss: Enable DDRSS ECC for full DDR Space

[Dave Gerlach]

Hi,

This series adds support for single bit ECC in the TI DDRSS bridge
inline ECC and adds required support code for AM64x EVM to enable it for
the full DDR space. This ECC module checks reads and writes to and from
DDR once enabled without additional action required. ECC is stored
together with the data so because of this, 1/9th of the total SDRAM
space is used for ECC storage and the rest 8/9th is available for system
use. From system point of view this means that available SDRAM will be
reduced from the end by 1/9, but otherwise SDRAM is accessed and used
the same. This series adds updates to the k3-ddrss driver for
configuration of the ECC, and also board and arch code to automatically
resize the available DDR if ECC is enabled through DT fixup.

In order to avoid duplicating information and keeping this series
generic this series moves to use the "memory" dt node for the main
source of DDR amount and base address instead of hard coding it which
has been done for all K3 previously. All TI K3 devices that use the
k3-ddrss driver have this same inline ECC, so taking this step to make
this more generic will allow this to be extended more easily.

By default this series does NOT actually enable ECC for the any platform
due to the multi second boot time increase that comes from the ECC
priming that is done as part of ECC init, but it can be enabled by
adding the 'ti,ecc-enable` property to the memorycontroller node in
k3-am642-r5-evm DT.

Regards,
Dave

Dave Gerlach (8):
  arm: dts: k3-am642-r5-evm: Mark memory with u-boot,dm-spl
  board: ti: am64x: Use fdt functions for ram and bank init
  dt-bindings: memory-controller: Add information about ECC bindings
  ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs
  ram: k3-ddrss: Introduce ECC Functionality for full memory space
  board: ti: am64x: Account for DDR size fixups if ECC is enabled
  arm: dts: k3-am64-ddr: Add ss_cfg reg entry
  configs: am64x_evm_r5: Add CONFIG_NR_DRAM_BANKS as done in a53
    defconfig

 arch/arm/dts/k3-am64-ddr.dtsi                 |   5 +-
 arch/arm/dts/k3-am642-r5-evm.dts              |   1 +
 board/ti/am64x/evm.c                          |  74 ++++++++--
 configs/am64x_evm_r5_defconfig                |   1 +
 .../memory-controller/k3-j721e-ddrss.txt      |   8 +
 drivers/ram/k3-ddrss/k3-ddrss.c               | 138 +++++++++++++++++-
 include/k3-ddrss.h                            |  16 ++
 7 files changed, 230 insertions(+), 13 deletions(-)
 create mode 100644 include/k3-ddrss.h

-- 
2.35.0

[PATCH 1/8] arm: dts: k3-am642-r5-evm: Mark memory with u-boot, dm-spl

[Dave Gerlach]

Mark the memory node with u-boot,dm-spl so we can use it from early SPL.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
 arch/arm/dts/k3-am642-r5-evm.dts | 1 +
 1 file changed, 1 insertion(+)

diff --git a/arch/arm/dts/k3-am642-r5-evm.dts b/arch/arm/dts/k3-am642-r5-evm.dts
index cc48fd4cb607..b30d61952bde 100644
--- a/arch/arm/dts/k3-am642-r5-evm.dts
+++ b/arch/arm/dts/k3-am642-r5-evm.dts
@@ -25,6 +25,7 @@
 		/* 2G RAM */
 		reg = <0x00000000 0x80000000 0x00000000 0x80000000>;
 
+		u-boot,dm-spl;
 	};
 
 	a53_0: a53@0 {
-- 
2.35.0

[PATCH 2/8] board: ti: am64x: Use fdt functions for ram and bank init

[Dave Gerlach]

Use the appropriate fdtdec_setup_mem_size_base and
fdtdec_setup_bank_size calls in dram_init and dram_bank_init to pull
these values from DT, where they are already available, instead of
hardcoding them.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
 board/ti/am64x/evm.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)

diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
index 8373c768f189..7ea80b82bec5 100644
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -29,19 +29,24 @@ int board_init(void)
 
 int dram_init(void)
 {
-	gd->ram_size = 0x80000000;
+	s32 ret;
 
-	return 0;
+	ret = fdtdec_setup_mem_size_base();
+	if (ret)
+		printf("Error setting up mem size and base. %d\n", ret);
+
+	return ret;
 }
 
 int dram_init_banksize(void)
 {
-	/* Bank 0 declares the memory available in the DDR low region */
-	gd->bd->bi_dram[0].start = CONFIG_SYS_SDRAM_BASE;
-	gd->bd->bi_dram[0].size = 0x80000000;
-	gd->ram_size = 0x80000000;
+	s32 ret;
 
-	return 0;
+	ret = fdtdec_setup_memory_banksize();
+	if (ret)
+		printf("Error setting up memory banksize. %d\n", ret);
+
+	return ret;
 }
 
 #if defined(CONFIG_SPL_LOAD_FIT)
-- 
2.35.0

[PATCH 3/8] dt-bindings: memory-controller: Add information about ECC bindings

[Dave Gerlach]

Add DT binding documentation for enabling ECC in the DDR sub system present
on AM64 device.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
 .../memory-controller/k3-j721e-ddrss.txt                  | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
index dd0260b39407..df3290a6b9d9 100644
--- a/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
+++ b/doc/device-tree-bindings/memory-controller/k3-j721e-ddrss.txt
@@ -13,6 +13,7 @@ Required properties:
 				  "ti,am64-ddrss" for am642
 - reg-names		cfg - Map the controller configuration region
 			ctrl_mmr_lp4 - Map LP4 register region in ctrl mmr
+			ss - Map the DDRSS configuration region
 - reg:			Contains the register map per reg-names.
 - power-domains:	Should contain two entries:
 			- an entry to TISCI DDR CFG device
@@ -32,6 +33,13 @@ Required properties:
 - ti,pi-data:		An array containing the phy independent block settings
 - ti,phy-data:		An array containing the ddr phy settings.
 
+Optional properties:
+--------------------
+- reg-names 		ss - Map the DDRSS configuration region
+- reg:			Must add "ss" to list if the above ss region is included.
+- ti,ecc-enable:	Boolean flag to enable ECC. This will reduce available DDR
+			by 1/9.
+
 Example (J721E):
 ================
 
-- 
2.35.0

[PATCH 4/8] ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs

[Dave Gerlach]

The current address being read from dt actually represents the ddrss_ctl
memory region, while ddrss_ss region is something else. Introduce
ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper
purpose later so that we can avoid confusion.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
 drivers/ram/k3-ddrss/k3-ddrss.c | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index 25e3976e6569..ffed426b9cca 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -106,6 +106,7 @@ struct k3_ddrss_desc {
 	struct udevice *dev;
 	void __iomem *ddrss_ss_cfg;
 	void __iomem *ddrss_ctrl_mmr;
+	void __iomem *ddrss_ctl_cfg;
 	struct power_domain ddrcfg_pwrdmn;
 	struct power_domain ddrdata_pwrdmn;
 	struct clk ddr_clk;
@@ -319,7 +320,7 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
 		dev_err(dev, "No reg property for DDRSS wrapper logic\n");
 		return -EINVAL;
 	}
-	ddrss->ddrss_ss_cfg = (void *)reg;
+	ddrss->ddrss_ctl_cfg = (void *)reg;
 
 	reg = dev_read_addr_name(dev, "ctrl_mmr_lp4");
 	if (reg == FDT_ADDR_T_NONE) {
@@ -403,7 +404,7 @@ void k3_lpddr4_init(struct k3_ddrss_desc *ddrss)
 		hang();
 	}
 
-	config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ss_cfg;
+	config->ctlbase = (struct lpddr4_ctlregs_s *)ddrss->ddrss_ctl_cfg;
 	config->infohandler = (lpddr4_infocallback) k3_lpddr4_info_handler;
 
 	status = driverdt->init(pd, config);
-- 
2.35.0

[PATCH 5/8] ram: k3-ddrss: Introduce ECC Functionality for full memory space

[Dave Gerlach]

Introduce ECC Functionality for full memory space as implemented in the
DDRSS. The following is done to accomplish this:

 * Introduce a memory region "ss" to allow dt to provide DDRSS region,
   which is not the same as "ctl" which is the controller region.

 * Introduce a "ti,ecc-enable" flag which allows a memorycontroller
   instance to enable ecc.

 * Introduce functionality to properly program the DDRSS registers to
   enable ECC for the full DDR memory space if enabled with above flag.

 * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to
   account from DDR memory that must be reserved for ECC operation.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
 drivers/ram/k3-ddrss/k3-ddrss.c | 133 ++++++++++++++++++++++++++++++++
 include/k3-ddrss.h              |  16 ++++
 2 files changed, 149 insertions(+)
 create mode 100644 include/k3-ddrss.h

diff --git a/drivers/ram/k3-ddrss/k3-ddrss.c b/drivers/ram/k3-ddrss/k3-ddrss.c
index ffed426b9cca..2467f122a829 100644
--- a/drivers/ram/k3-ddrss/k3-ddrss.c
+++ b/drivers/ram/k3-ddrss/k3-ddrss.c
@@ -6,9 +6,12 @@
  */
 
 #include <common.h>
+#include <config.h>
 #include <clk.h>
+#include <div64.h>
 #include <dm.h>
 #include <dm/device_compat.h>
+#include <fdt_support.h>
 #include <ram.h>
 #include <hang.h>
 #include <log.h>
@@ -30,6 +33,19 @@
 #define DDRSS_V2A_R1_MAT_REG			0x0020
 #define DDRSS_ECC_CTRL_REG			0x0120
 
+#define DDRSS_ECC_CTRL_REG_ECC_EN		BIT(0)
+#define DDRSS_ECC_CTRL_REG_RMW_EN		BIT(1)
+#define DDRSS_ECC_CTRL_REG_ECC_CK		BIT(2)
+#define DDRSS_ECC_CTRL_REG_WR_ALLOC		BIT(4)
+
+#define DDRSS_ECC_R0_STR_ADDR_REG		0x0130
+#define DDRSS_ECC_R0_END_ADDR_REG		0x0134
+#define DDRSS_ECC_R1_STR_ADDR_REG		0x0138
+#define DDRSS_ECC_R1_END_ADDR_REG		0x013c
+#define DDRSS_ECC_R2_STR_ADDR_REG		0x0140
+#define DDRSS_ECC_R2_END_ADDR_REG		0x0144
+#define DDRSS_ECC_1B_ERR_CNT_REG		0x0150
+
 #define SINGLE_DDR_SUBSYSTEM	0x1
 #define MULTI_DDR_SUBSYSTEM	0x2
 
@@ -102,6 +118,13 @@ struct k3_msmc {
 	enum emif_active active;
 };
 
+#define K3_DDRSS_MAX_ECC_REGIONS		3
+
+struct k3_ddrss_ecc_region {
+	u32 start;
+	u32 range;
+};
+
 struct k3_ddrss_desc {
 	struct udevice *dev;
 	void __iomem *ddrss_ss_cfg;
@@ -119,6 +142,9 @@ struct k3_ddrss_desc {
 	lpddr4_obj *driverdt;
 	lpddr4_config config;
 	lpddr4_privatedata pd;
+	struct k3_ddrss_ecc_region ecc_regions[K3_DDRSS_MAX_ECC_REGIONS];
+	u64 ecc_reserved_space;
+	bool ti_ecc_enabled;
 };
 
 struct reginitdata {
@@ -329,6 +355,14 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
 	}
 	ddrss->ddrss_ctrl_mmr = (void *)reg;
 
+	reg = dev_read_addr_name(dev, "ss_cfg");
+	if (reg == FDT_ADDR_T_NONE) {
+		dev_dbg(dev, "No reg property for SS Config region, but this is optional so continuing.\n");
+		ddrss->ddrss_ss_cfg = NULL;
+	} else {
+		ddrss->ddrss_ss_cfg = (void *)reg;
+	}
+
 	ret = power_domain_get_by_index(dev, &ddrss->ddrcfg_pwrdmn, 0);
 	if (ret) {
 		dev_err(dev, "power_domain_get() failed: %d\n", ret);
@@ -372,6 +406,8 @@ static int k3_ddrss_ofdata_to_priv(struct udevice *dev)
 	if (ret)
 		dev_err(dev, "ddr fhs cnt not populated %d\n", ret);
 
+	ddrss->ti_ecc_enabled = dev_read_bool(dev, "ti,ecc-enable");
+
 	return ret;
 }
 
@@ -513,6 +549,60 @@ void k3_lpddr4_start(struct k3_ddrss_desc *ddrss)
 	}
 }
 
+static void k3_ddrss_set_ecc_range_r0(u32 base, u32 start_address, u32 size)
+{
+	writel((start_address) >> 16, base + DDRSS_ECC_R0_STR_ADDR_REG);
+	writel((start_address + size - 1) >> 16, base + DDRSS_ECC_R0_END_ADDR_REG);
+}
+
+static void k3_ddrss_preload_ecc_mem_region(u32 *addr, u32 size, u32 word)
+{
+	int i;
+
+	printf("ECC is enabled, priming DDR which will take several seconds.\n");
+
+	for (i = 0; i < (size / 4); i++)
+		addr[i] = word;
+}
+
+static void k3_ddrss_lpddr4_ecc_calc_reserved_mem(struct k3_ddrss_desc *ddrss)
+{
+	fdtdec_setup_mem_size_base_lowest();
+
+	ddrss->ecc_reserved_space = gd->ram_size;
+	do_div(ddrss->ecc_reserved_space, 9);
+
+	/* Round to clean number */
+	ddrss->ecc_reserved_space = 1ull << (fls(ddrss->ecc_reserved_space));
+}
+
+static void k3_ddrss_lpddr4_ecc_init(struct k3_ddrss_desc *ddrss)
+{
+	u32 ecc_region_start = ddrss->ecc_regions[0].start;
+	u32 ecc_range = ddrss->ecc_regions[0].range;
+	u32 base = (u32)ddrss->ddrss_ss_cfg;
+	u32 val;
+
+	/* Only Program region 0 which covers full ddr space */
+	k3_ddrss_set_ecc_range_r0(base, ecc_region_start - gd->ram_base, ecc_range);
+
+	/* Enable ECC, RMW, WR_ALLOC */
+	writel(DDRSS_ECC_CTRL_REG_ECC_EN | DDRSS_ECC_CTRL_REG_RMW_EN |
+	       DDRSS_ECC_CTRL_REG_WR_ALLOC, base + DDRSS_ECC_CTRL_REG);
+
+	/* Preload ECC Mem region with 0's */
+	k3_ddrss_preload_ecc_mem_region((u32 *)ecc_region_start, ecc_range,
+					0x00000000);
+
+	/* Clear Error Count Register */
+	writel(0x1, base + DDRSS_ECC_1B_ERR_CNT_REG);
+
+	/* Enable ECC Check */
+	val = readl(base + DDRSS_ECC_CTRL_REG);
+	val |= DDRSS_ECC_CTRL_REG_ECC_CK;
+	writel(val, base + DDRSS_ECC_CTRL_REG);
+}
+
 static int k3_ddrss_probe(struct udevice *dev)
 {
 	int ret;
@@ -547,9 +637,52 @@ static int k3_ddrss_probe(struct udevice *dev)
 
 	k3_lpddr4_start(ddrss);
 
+	if (ddrss->ti_ecc_enabled) {
+		if (!ddrss->ddrss_ss_cfg) {
+			printf("%s: ss_cfg is required if ecc is enabled but not provided.",
+			       __func__);
+			return -EINVAL;
+		}
+
+		k3_ddrss_lpddr4_ecc_calc_reserved_mem(ddrss);
+
+		/* Always configure one region that covers full DDR space */
+		ddrss->ecc_regions[0].start = gd->ram_base;
+		ddrss->ecc_regions[0].range = gd->ram_size - ddrss->ecc_reserved_space;
+		k3_ddrss_lpddr4_ecc_init(ddrss);
+	}
+
 	return ret;
 }
 
+int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd)
+{
+	struct k3_ddrss_desc *ddrss = dev_get_priv(dev);
+	u64 start[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+	int bank;
+
+	if (ddrss->ecc_reserved_space == 0)
+		return 0;
+
+	for (bank = CONFIG_NR_DRAM_BANKS - 1; bank >= 0; bank--) {
+		if (ddrss->ecc_reserved_space > bd->bi_dram[bank].size) {
+			ddrss->ecc_reserved_space -= bd->bi_dram[bank].size;
+			bd->bi_dram[bank].size = 0;
+		} else {
+			bd->bi_dram[bank].size -= ddrss->ecc_reserved_space;
+			break;
+		}
+	}
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		start[bank] =  bd->bi_dram[bank].start;
+		size[bank] = bd->bi_dram[bank].size;
+	}
+
+	return fdt_fixup_memory_banks(blob, start, size, CONFIG_NR_DRAM_BANKS);
+}
+
 static int k3_ddrss_get_info(struct udevice *dev, struct ram_info *info)
 {
 	return 0;
diff --git a/include/k3-ddrss.h b/include/k3-ddrss.h
new file mode 100644
index 000000000000..d7b3bf3c330a
--- /dev/null
+++ b/include/k3-ddrss.h
@@ -0,0 +1,16 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Texas Instruments' K3 DDRSS Driver
+ *
+ * Copyright (C) 2021-2022 Texas Instruments Incorporated - https://www.ti.com/
+ *
+ */
+
+#ifndef _K3_DDRSS_
+#define _K3_DDRSS_
+
+struct udevice;
+
+int k3_ddrss_ddr_fdt_fixup(struct udevice *dev, void *blob, struct bd_info *bd);
+
+#endif
-- 
2.35.0

[PATCH 6/8] board: ti: am64x: Account for DDR size fixups if ECC is enabled

[Dave Gerlach]

Call into k3-ddrss driver to fixup device tree and resize the available
amount of DDR if ECC is enabled.

A second fixup is required from A53 SPL to take the fixup as done from
R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes
this to the OS.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
 board/ti/am64x/evm.c | 55 ++++++++++++++++++++++++++++++++++++++++++--
 1 file changed, 53 insertions(+), 2 deletions(-)

diff --git a/board/ti/am64x/evm.c b/board/ti/am64x/evm.c
index 7ea80b82bec5..c88139ac7acc 100644
--- a/board/ti/am64x/evm.c
+++ b/board/ti/am64x/evm.c
@@ -2,13 +2,15 @@
 /*
  * Board specific initialization for AM642 EVM
  *
- * Copyright (C) 2020-2021 Texas Instruments Incorporated - https://www.ti.com/
+ * Copyright (C) 2020-2022 Texas Instruments Incorporated - https://www.ti.com/
  *	Keerthy <j-keerthy@ti.com>
  *
  */
 
 #include <common.h>
 #include <asm/io.h>
+#include <dm/uclass.h>
+#include <k3-ddrss.h>
 #include <spl.h>
 #include <fdt_support.h>
 #include <asm/arch/hardware.h>
@@ -66,7 +68,8 @@ int board_fit_config_name_match(const char *name)
 }
 #endif
 
-#if defined(CONFIG_SPL_BUILD) && CONFIG_IS_ENABLED(USB_STORAGE)
+#if defined(CONFIG_SPL_BUILD)
+#if CONFIG_IS_ENABLED(USB_STORAGE)
 static int fixup_usb_boot(const void *fdt_blob)
 {
 	int ret = 0;
@@ -90,10 +93,58 @@ static int fixup_usb_boot(const void *fdt_blob)
 
 	return ret;
 }
+#endif
+
+#if defined(CONFIG_K3_AM64_DDRSS)
+static void fixup_ddr_driver_for_ecc(struct spl_image_info *spl_image)
+{
+	struct udevice *dev;
+	int ret;
+
+	dram_init_banksize();
+
+	ret = uclass_get_device(UCLASS_RAM, 0, &dev);
+	if (ret)
+		panic("Cannot get RAM device for ddr size fixup: %d\n", ret);
+
+	ret = k3_ddrss_ddr_fdt_fixup(dev, spl_image->fdt_addr, gd->bd);
+	if (ret)
+		printf("Error fixing up ddr node for ECC use! %d\n", ret);
+}
+#else
+static void fixup_memory_node(struct spl_image_info *spl_image)
+{
+	u64 start[CONFIG_NR_DRAM_BANKS];
+	u64 size[CONFIG_NR_DRAM_BANKS];
+	int bank;
+	int ret;
+
+	dram_init();
+	dram_init_banksize();
+
+	for (bank = 0; bank < CONFIG_NR_DRAM_BANKS; bank++) {
+		start[bank] =  gd->bd->bi_dram[bank].start;
+		size[bank] = gd->bd->bi_dram[bank].size;
+	}
+
+	/* dram_init functions use SPL fdt, and we must fixup u-boot fdt */
+	ret = fdt_fixup_memory_banks(spl_image->fdt_addr, start, size, CONFIG_NR_DRAM_BANKS);
+	if (ret)
+		printf("Error fixing up memory node! %d\n", ret);
+}
+#endif
 
 void spl_perform_fixups(struct spl_image_info *spl_image)
 {
+#if defined(CONFIG_K3_AM64_DDRSS)
+	fixup_ddr_driver_for_ecc(spl_image);
+#else
+	fixup_memory_node(spl_image);
+#endif
+
+#if CONFIG_IS_ENABLED(USB_STORAGE)
 	fixup_usb_boot(spl_image->fdt_addr);
+#endif
 }
 #endif
 
-- 
2.35.0

[PATCH 7/8] arm: dts: k3-am64-ddr: Add ss_cfg reg entry

[Dave Gerlach]

Add 'ss_cfg' memory region for memorycontroller node which is required
to enable ECC.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
 arch/arm/dts/k3-am64-ddr.dtsi | 5 +++--
 1 file changed, 3 insertions(+), 2 deletions(-)

diff --git a/arch/arm/dts/k3-am64-ddr.dtsi b/arch/arm/dts/k3-am64-ddr.dtsi
index 026a547f0e3a..8324b389e065 100644
--- a/arch/arm/dts/k3-am64-ddr.dtsi
+++ b/arch/arm/dts/k3-am64-ddr.dtsi
@@ -7,8 +7,9 @@
 	memorycontroller: memorycontroller@f300000 {
 		compatible = "ti,am64-ddrss";
 		reg = <0x00 0x0f308000 0x00 0x4000>,
-		      <0x00 0x43014000 0x00 0x100>;
-		reg-names = "cfg", "ctrl_mmr_lp4";
+		      <0x00 0x43014000 0x00 0x100>,
+		      <0x00 0x0f300000 0x00 0x200>;
+		reg-names = "cfg", "ctrl_mmr_lp4", "ss_cfg";
 		power-domains = <&k3_pds 138 TI_SCI_PD_SHARED>,
 			<&k3_pds 55 TI_SCI_PD_SHARED>;
 		clocks = <&k3_clks 138 0>, <&k3_clks 16 4>;
-- 
2.35.0

[PATCH 8/8] configs: am64x_evm_r5: Add CONFIG_NR_DRAM_BANKS as done in a53 defconfig

[Dave Gerlach]

Add CONFIG_NR_DRAM_BANKS from am64x_evm_a53_defconfig as this is needed
to calculate the size of DDR that is available.

Signed-off-by: Dave Gerlach <d-gerlach@ti.com>
---
 configs/am64x_evm_r5_defconfig | 1 +
 1 file changed, 1 insertion(+)

diff --git a/configs/am64x_evm_r5_defconfig b/configs/am64x_evm_r5_defconfig
index 61138dd1a958..e66bd1aaf166 100644
--- a/configs/am64x_evm_r5_defconfig
+++ b/configs/am64x_evm_r5_defconfig
@@ -9,6 +9,7 @@ CONFIG_SOC_K3_AM642=y
 CONFIG_TARGET_AM642_R5_EVM=y
 CONFIG_ENV_SIZE=0x20000
 CONFIG_ENV_OFFSET=0x680000
+CONFIG_NR_DRAM_BANKS=2
 CONFIG_DM_GPIO=y
 CONFIG_SPL_DM_SPI=y
 CONFIG_DEFAULT_DEVICE_TREE="k3-am642-r5-evm"
-- 
2.35.0

Re: [PATCH 1/8] arm: dts: k3-am642-r5-evm: Mark memory with u-boot, dm-spl

[Tom Rini]

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On Thu, Mar 17, 2022 at 12:03:39PM -0500, Dave Gerlach wrote:

> Mark the memory node with u-boot,dm-spl so we can use it from early SPL.
> 
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

Applied to u-boot/master, thanks!

-- 
Tom

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Re: [PATCH 2/8] board: ti: am64x: Use fdt functions for ram and bank init

[Tom Rini]

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On Thu, Mar 17, 2022 at 12:03:40PM -0500, Dave Gerlach wrote:

> Use the appropriate fdtdec_setup_mem_size_base and
> fdtdec_setup_bank_size calls in dram_init and dram_bank_init to pull
> these values from DT, where they are already available, instead of
> hardcoding them.
> 
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

Applied to u-boot/master, thanks!

-- 
Tom

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Re: [PATCH 3/8] dt-bindings: memory-controller: Add information about ECC bindings

[Tom Rini]

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On Thu, Mar 17, 2022 at 12:03:41PM -0500, Dave Gerlach wrote:

> Add DT binding documentation for enabling ECC in the DDR sub system present
> on AM64 device.
> 
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

Applied to u-boot/master, thanks!

-- 
Tom

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Re: [PATCH 4/8] ram: k3-ddrss: Rename ddrss_ss_regs to ddrss_ctl_regs

[Tom Rini]

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On Thu, Mar 17, 2022 at 12:03:42PM -0500, Dave Gerlach wrote:

> The current address being read from dt actually represents the ddrss_ctl
> memory region, while ddrss_ss region is something else. Introduce
> ddrss_ctl_regs and use it to free up ddrss_ss_regs for its proper
> purpose later so that we can avoid confusion.
> 
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

Applied to u-boot/master, thanks!

-- 
Tom

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Re: [PATCH 5/8] ram: k3-ddrss: Introduce ECC Functionality for full memory space

[Tom Rini]

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On Thu, Mar 17, 2022 at 12:03:43PM -0500, Dave Gerlach wrote:

> Introduce ECC Functionality for full memory space as implemented in the
> DDRSS. The following is done to accomplish this:
> 
>  * Introduce a memory region "ss" to allow dt to provide DDRSS region,
>    which is not the same as "ctl" which is the controller region.
> 
>  * Introduce a "ti,ecc-enable" flag which allows a memorycontroller
>    instance to enable ecc.
> 
>  * Introduce functionality to properly program the DDRSS registers to
>    enable ECC for the full DDR memory space if enabled with above flag.
> 
>  * Expose a k3_ddrss_ddr_fdt_fixup call to allow fixup of fdt blob to
>    account from DDR memory that must be reserved for ECC operation.
> 
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

Applied to u-boot/master, thanks!

-- 
Tom

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Re: [PATCH 6/8] board: ti: am64x: Account for DDR size fixups if ECC is enabled

[Tom Rini]

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On Thu, Mar 17, 2022 at 12:03:44PM -0500, Dave Gerlach wrote:

> Call into k3-ddrss driver to fixup device tree and resize the available
> amount of DDR if ECC is enabled.
> 
> A second fixup is required from A53 SPL to take the fixup as done from
> R5 SPL and apply it to DT passed to A53 U-boot, which in turn passes
> this to the OS.
> 
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

Applied to u-boot/master, thanks!

-- 
Tom

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Re: [PATCH 7/8] arm: dts: k3-am64-ddr: Add ss_cfg reg entry

[Tom Rini]

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On Thu, Mar 17, 2022 at 12:03:45PM -0500, Dave Gerlach wrote:

> Add 'ss_cfg' memory region for memorycontroller node which is required
> to enable ECC.
> 
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

Applied to u-boot/master, thanks!

-- 
Tom

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Re: [PATCH 8/8] configs: am64x_evm_r5: Add CONFIG_NR_DRAM_BANKS as done in a53 defconfig

[Tom Rini]

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On Thu, Mar 17, 2022 at 12:03:46PM -0500, Dave Gerlach wrote:

> Add CONFIG_NR_DRAM_BANKS from am64x_evm_a53_defconfig as this is needed
> to calculate the size of DDR that is available.
> 
> Signed-off-by: Dave Gerlach <d-gerlach@ti.com>

Applied to u-boot/master, thanks!

-- 
Tom

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