* [Intel-gfx] [PATCH] drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A @ 2022-04-07 8:42 Stanislav Lisovskiy 2022-04-07 8:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork ` (6 more replies) 0 siblings, 7 replies; 12+ messages in thread From: Stanislav Lisovskiy @ 2022-04-07 8:42 UTC (permalink / raw) To: intel-gfx We had some FIFO underruns appearing on platforms like ADL, which could be fixed though by increasing CDCLK, however we were lacking explanation for that - we were not calculating CDCLK, also based on cumulative bpp W/A formula, mentioned in BSpec 64631. With that patch no FIFO underruns appear anymore. Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> --- drivers/gpu/drm/i915/display/intel_bw.c | 71 ++++++++++++++++++++++--- drivers/gpu/drm/i915/display/intel_bw.h | 2 + 2 files changed, 67 insertions(+), 6 deletions(-) diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c index 37bd7b17f3d0..3a2aeeffee7c 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.c +++ b/drivers/gpu/drm/i915/display/intel_bw.c @@ -743,20 +743,51 @@ static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state, } } -static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state, +static int intel_plane_bw_bpp(const struct drm_format_info *info) +{ + /* + * For the purposes of memory bandwidth calculations, + * planar formats are treated as if both planes had the + * same bpp (with no reduction for vertical + * subsampling). I.e we take as usual the worst case + * scenario. + */ + if (drm_format_info_is_yuv_semiplanar(info)) + return 2 * max(info->cpp[0], info->cpp[1]); + + return info->cpp[0]; +} + +static void skl_crtc_calc_dbuf_bw(struct intel_atomic_state *state, + struct intel_bw_state *bw_state, const struct intel_crtc_state *crtc_state) { struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); struct drm_i915_private *i915 = to_i915(crtc->base.dev); struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe]; - enum plane_id plane_id; + struct intel_plane *plane; memset(crtc_bw, 0, sizeof(*crtc_bw)); if (!crtc_state->hw.active) return; - for_each_plane_id_on_crtc(crtc, plane_id) { + for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { + const struct drm_framebuffer *fb; + enum plane_id plane_id = plane->id; + unsigned int plane_bpp = 0; + struct intel_plane_state *plane_state = + intel_atomic_get_new_plane_state(state, plane); + + if (plane_state) { + fb = plane_state->hw.fb; + + if (plane_state->uapi.visible && fb) + plane_bpp = intel_plane_bw_bpp(fb->format); + } + + crtc_bw->pipe_cumulative_bpp += plane_bpp; + /* * We assume cursors are small enough * to not cause bandwidth problems. @@ -773,6 +804,10 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state, &crtc_state->wm.skl.plane_ddb_y[plane_id], crtc_state->data_rate[plane_id]); } + + crtc_bw->bpp_cdclk = DIV_ROUND_UP_ULL(mul_u32_u32(crtc_state->pixel_rate, + crtc_bw->pipe_cumulative_bpp * 512), + 10) / 1000; } /* "Maximum Data Buffer Bandwidth" */ @@ -782,11 +817,13 @@ intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915, { unsigned int total_max_bw = 0; enum dbuf_slice slice; + enum pipe pipe; + unsigned int bpp_cdclk = 0; + unsigned int dbuf_bw_cdclk; for_each_dbuf_slice(i915, slice) { int num_active_planes = 0; unsigned int max_bw = 0; - enum pipe pipe; /* * The arbiter can only really guarantee an @@ -803,7 +840,29 @@ intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915, total_max_bw = max(total_max_bw, max_bw); } - return DIV_ROUND_UP(total_max_bw, 64); + for_each_pipe(i915, pipe) { + const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe]; + /* + * From BSpec 64631: + * Pipe cumulative bytes should be less or equal to + * CDCLK / (pixel_rate * scaling_factors * 51.2) thus + * CDCLK = pipe_cumulative_bpp * pixel_rate * scaling_factors * 51.2. + * Considering that intel_plane_pixel_rate already returns adjusted pixel rate, + * no scaling factors needed here. + */ + bpp_cdclk = max_t(unsigned int, crtc_bw->bpp_cdclk, + bpp_cdclk); + } + + dbuf_bw_cdclk = DIV_ROUND_UP(total_max_bw, 64); + + /* + * So now we have two CDCLK estimations: + * one is based on required DBuf BW and another is + * based on pipe cumulative bpp W/A(BSpec 64631) + * Traditionally take the more demanding into use(worst case) + */ + return max_t(unsigned int, dbuf_bw_cdclk, bpp_cdclk); } int intel_bw_min_cdclk(struct drm_i915_private *i915, @@ -842,7 +901,7 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, old_bw_state = intel_atomic_get_old_bw_state(state); - skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state); + skl_crtc_calc_dbuf_bw(state, new_bw_state, crtc_state); new_bw_state->min_cdclk[crtc->pipe] = intel_bw_crtc_min_cdclk(crtc_state); diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h index cb7ee3a24a58..9e3a6ad03b19 100644 --- a/drivers/gpu/drm/i915/display/intel_bw.h +++ b/drivers/gpu/drm/i915/display/intel_bw.h @@ -19,6 +19,8 @@ struct intel_crtc_state; struct intel_dbuf_bw { unsigned int max_bw[I915_MAX_DBUF_SLICES]; u8 active_planes[I915_MAX_DBUF_SLICES]; + unsigned int pipe_cumulative_bpp; + unsigned int bpp_cdclk; }; struct intel_bw_state { -- 2.24.1.485.gad05a3d8e5 ^ permalink raw reply related [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A 2022-04-07 8:42 [Intel-gfx] [PATCH] drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A Stanislav Lisovskiy @ 2022-04-07 8:51 ` Patchwork 2022-04-07 9:23 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork ` (5 subsequent siblings) 6 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2022-04-07 8:51 UTC (permalink / raw) To: Stanislav Lisovskiy; +Cc: intel-gfx == Series Details == Series: drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A URL : https://patchwork.freedesktop.org/series/102322/ State : warning == Summary == $ dim checkpatch origin/drm-tip b2b7dace2671 drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A -:81: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #81: FILE: drivers/gpu/drm/i915/display/intel_bw.c:809: + crtc_bw->bpp_cdclk = DIV_ROUND_UP_ULL(mul_u32_u32(crtc_state->pixel_rate, + crtc_bw->pipe_cumulative_bpp * 512), -:117: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #117: FILE: drivers/gpu/drm/i915/display/intel_bw.c:854: + bpp_cdclk = max_t(unsigned int, crtc_bw->bpp_cdclk, + bpp_cdclk); total: 0 errors, 0 warnings, 2 checks, 124 lines checked ^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A 2022-04-07 8:42 [Intel-gfx] [PATCH] drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A Stanislav Lisovskiy 2022-04-07 8:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork @ 2022-04-07 9:23 ` Patchwork 2022-04-07 9:59 ` Lisovskiy, Stanislav 2022-04-07 9:23 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork ` (4 subsequent siblings) 6 siblings, 1 reply; 12+ messages in thread From: Patchwork @ 2022-04-07 9:23 UTC (permalink / raw) To: Stanislav Lisovskiy; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 6409 bytes --] == Series Details == Series: drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A URL : https://patchwork.freedesktop.org/series/102322/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11469 -> Patchwork_22807 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_22807 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22807, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/index.html Participating hosts (50 -> 45) ------------------------------ Missing (5): shard-tglu fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_22807: ### IGT changes ### #### Possible regressions #### * igt@i915_selftest@live@coherency: - fi-bdw-5557u: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-bdw-5557u/igt@i915_selftest@live@coherency.html Known issues ------------ Here are the changes found in Patchwork_22807 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_basic@semaphore: - fi-hsw-4770: NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#109315]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-hsw-4770/igt@amdgpu/amd_basic@semaphore.html * igt@amdgpu/amd_cs_nop@fork-compute0: - fi-blb-e6850: NOTRUN -> [SKIP][3] ([fdo#109271]) +17 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-blb-e6850/igt@amdgpu/amd_cs_nop@fork-compute0.html * igt@kms_chamelium@vga-edid-read: - fi-bdw-5557u: NOTRUN -> [SKIP][4] ([fdo#109271] / [fdo#111827]) +8 similar issues [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-bdw-5557u/igt@kms_chamelium@vga-edid-read.html * igt@kms_setmode@basic-clone-single-crtc: - fi-bdw-5557u: NOTRUN -> [SKIP][5] ([fdo#109271]) +14 similar issues [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-bdw-5557u/igt@kms_setmode@basic-clone-single-crtc.html #### Possible fixes #### * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [INCOMPLETE][6] ([i915#146]) -> [PASS][7] [6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11469/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770: [INCOMPLETE][8] ([i915#4785]) -> [PASS][9] [8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11469/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html * igt@i915_selftest@live@requests: - fi-blb-e6850: [DMESG-FAIL][10] ([i915#4528]) -> [PASS][11] [10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11469/fi-blb-e6850/igt@i915_selftest@live@requests.html [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-blb-e6850/igt@i915_selftest@live@requests.html #### Warnings #### * igt@core_hotunplug@unbind-rebind: - fi-tgl-1115g4: [DMESG-WARN][12] ([i915#1982]) -> [DMESG-WARN][13] ([i915#5577]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11469/fi-tgl-1115g4/igt@core_hotunplug@unbind-rebind.html [13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-tgl-1115g4/igt@core_hotunplug@unbind-rebind.html * igt@runner@aborted: - fi-glk-j4005: [FAIL][14] ([i915#4312] / [i915#5257] / [k.org#202321]) -> [FAIL][15] ([i915#4312] / [i915#5257]) [14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11469/fi-glk-j4005/igt@runner@aborted.html [15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-glk-j4005/igt@runner@aborted.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528 [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785 [i915#4897]: https://gitlab.freedesktop.org/drm/intel/issues/4897 [i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257 [i915#5577]: https://gitlab.freedesktop.org/drm/intel/issues/5577 [k.org#202321]: https://bugzilla.kernel.org/show_bug.cgi?id=202321 Build changes ------------- * Linux: CI_DRM_11469 -> Patchwork_22807 CI-20190529: 20190529 CI_DRM_11469: d95bb535e8e80c0484bb6f13d1875efcdb084862 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6415: c3b690bd5f7fb1fb7ed786ab0f3b815930a6a55f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22807: b2b7dace2671214005e79582b62db58c64273533 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/Patchwork_22807/build_32bit.log CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) MODPOST modules-only.symvers ERROR: modpost: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined! scripts/Makefile.modpost:134: recipe for target 'modules-only.symvers' failed make[1]: *** [modules-only.symvers] Error 1 make[1]: *** Deleting file 'modules-only.symvers' Makefile:1749: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == b2b7dace2671 drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/index.html [-- Attachment #2: Type: text/html, Size: 7874 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A 2022-04-07 9:23 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork @ 2022-04-07 9:59 ` Lisovskiy, Stanislav 0 siblings, 0 replies; 12+ messages in thread From: Lisovskiy, Stanislav @ 2022-04-07 9:59 UTC (permalink / raw) To: intel-gfx gt@i915_selftest@live@coherency failure on bdw, sure doesn't have anything with this patch :D Restarted test run in hopes.. Best Regards, Lisovskiy Stanislav Organization: Intel Finland Oy - BIC 0357606-4 - Westendinkatu 7, 02160 Espoo ________________________________________ From: Patchwork <patchwork@emeril.freedesktop.org> Sent: Thursday, April 7, 2022 12:23:26 PM To: Lisovskiy, Stanislav Cc: intel-gfx@lists.freedesktop.org Subject: ✗ Fi.CI.BAT: failure for drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A Patch Details Series: drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A URL: https://patchwork.freedesktop.org/series/102322/ State: failure Details: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/index.html CI Bug Log - changes from CI_DRM_11469 -> Patchwork_22807 Summary FAILURE Serious unknown changes coming with Patchwork_22807 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22807, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/index.html Participating hosts (50 -> 45) Missing (5): shard-tglu fi-bsw-cyan fi-ctg-p8600 fi-pnv-d510 fi-bdw-samus Possible new issues Here are the unknown changes that may have been introduced in Patchwork_22807: IGT changes Possible regressions * igt@i915_selftest@live@coherency: * fi-bdw-5557u: NOTRUN -> INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-bdw-5557u/igt@i915_selftest@live@coherency.html> Known issues Here are the changes found in Patchwork_22807 that come from known issues: IGT changes Issues hit * igt@amdgpu/amd_basic@semaphore: * fi-hsw-4770: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-hsw-4770/igt@amdgpu/amd_basic@semaphore.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / fdo#109315<https://bugs.freedesktop.org/show_bug.cgi?id=109315>) +17 similar issues * igt@amdgpu/amd_cs_nop@fork-compute0: * fi-blb-e6850: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-blb-e6850/igt@amdgpu/amd_cs_nop@fork-compute0.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +17 similar issues * igt@kms_chamelium@vga-edid-read: * fi-bdw-5557u: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-bdw-5557u/igt@kms_chamelium@vga-edid-read.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271> / fdo#111827<https://bugs.freedesktop.org/show_bug.cgi?id=111827>) +8 similar issues * igt@kms_setmode@basic-clone-single-crtc: * fi-bdw-5557u: NOTRUN -> SKIP<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-bdw-5557u/igt@kms_setmode@basic-clone-single-crtc.html> (fdo#109271<https://bugs.freedesktop.org/show_bug.cgi?id=109271>) +14 similar issues Possible fixes * igt@gem_exec_suspend@basic-s3@smem: * fi-bdw-5557u: INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11469/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html> (i915#146<https://gitlab.freedesktop.org/drm/intel/issues/146>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html> * igt@i915_selftest@live@hangcheck: * fi-hsw-4770: INCOMPLETE<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11469/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html> (i915#4785<https://gitlab.freedesktop.org/drm/intel/issues/4785>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html> * igt@i915_selftest@live@requests: * fi-blb-e6850: DMESG-FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11469/fi-blb-e6850/igt@i915_selftest@live@requests.html> (i915#4528<https://gitlab.freedesktop.org/drm/intel/issues/4528>) -> PASS<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-blb-e6850/igt@i915_selftest@live@requests.html> Warnings * igt@core_hotunplug@unbind-rebind: * fi-tgl-1115g4: DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11469/fi-tgl-1115g4/igt@core_hotunplug@unbind-rebind.html> (i915#1982<https://gitlab.freedesktop.org/drm/intel/issues/1982>) -> DMESG-WARN<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-tgl-1115g4/igt@core_hotunplug@unbind-rebind.html> (i915#5577<https://gitlab.freedesktop.org/drm/intel/issues/5577>) * igt@runner@aborted: * fi-glk-j4005: FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11469/fi-glk-j4005/igt@runner@aborted.html> (i915#4312<https://gitlab.freedesktop.org/drm/intel/issues/4312> / i915#5257<https://gitlab.freedesktop.org/drm/intel/issues/5257> / k.org#202321<https://bugzilla.kernel.org/show_bug.cgi?id=202321>) -> FAIL<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-glk-j4005/igt@runner@aborted.html> (i915#4312<https://gitlab.freedesktop.org/drm/intel/issues/4312> / i915#5257<https://gitlab.freedesktop.org/drm/intel/issues/5257>) {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). Build changes * Linux: CI_DRM_11469 -> Patchwork_22807 CI-20190529: 20190529 CI_DRM_11469: d95bb535e8e80c0484bb6f13d1875efcdb084862 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6415: c3b690bd5f7fb1fb7ed786ab0f3b815930a6a55f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22807: b2b7dace2671214005e79582b62db58c64273533 @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/Patchwork_22807/build_32bit.log CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) MODPOST modules-only.symvers ERROR: modpost: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined! scripts/Makefile.modpost:134: recipe for target 'modules-only.symvers' failed make1<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-bdw-5557u/igt@i915_selftest@live@coherency.html>: [modules-only.symvers] Error 1 make1<https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/fi-bdw-5557u/igt@i915_selftest@live@coherency.html>: Deleting file 'modules-only.symvers' Makefile:1749: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == b2b7dace2671 drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A ^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A 2022-04-07 8:42 [Intel-gfx] [PATCH] drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A Stanislav Lisovskiy 2022-04-07 8:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork 2022-04-07 9:23 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork @ 2022-04-07 9:23 ` Patchwork 2022-04-07 11:10 ` [Intel-gfx] [PATCH] " Ville Syrjälä ` (3 subsequent siblings) 6 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2022-04-07 9:23 UTC (permalink / raw) To: Stanislav Lisovskiy; +Cc: intel-gfx == Series Details == Series: drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A URL : https://patchwork.freedesktop.org/series/102322/ State : warning == Summary == CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) MODPOST modules-only.symvers ERROR: modpost: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined! scripts/Makefile.modpost:134: recipe for target 'modules-only.symvers' failed make[1]: *** [modules-only.symvers] Error 1 make[1]: *** Deleting file 'modules-only.symvers' Makefile:1749: recipe for target 'modules' failed make: *** [modules] Error 2 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22807/build_32bit.log ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A 2022-04-07 8:42 [Intel-gfx] [PATCH] drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A Stanislav Lisovskiy ` (2 preceding siblings ...) 2022-04-07 9:23 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork @ 2022-04-07 11:10 ` Ville Syrjälä 2022-04-07 11:24 ` Lisovskiy, Stanislav 2022-04-07 11:39 ` Lisovskiy, Stanislav 2022-04-07 13:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A (rev2) Patchwork ` (2 subsequent siblings) 6 siblings, 2 replies; 12+ messages in thread From: Ville Syrjälä @ 2022-04-07 11:10 UTC (permalink / raw) To: Stanislav Lisovskiy; +Cc: intel-gfx On Thu, Apr 07, 2022 at 11:42:35AM +0300, Stanislav Lisovskiy wrote: > We had some FIFO underruns appearing on platforms like ADL, > which could be fixed though by increasing CDCLK, however we were > lacking explanation for that - we were not calculating CDCLK, > also based on cumulative bpp W/A formula, mentioned in BSpec 64631. We already have that in intel_bw_crtc_min_cdclk(). > > With that patch no FIFO underruns appear anymore. > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > --- > drivers/gpu/drm/i915/display/intel_bw.c | 71 ++++++++++++++++++++++--- > drivers/gpu/drm/i915/display/intel_bw.h | 2 + > 2 files changed, 67 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > index 37bd7b17f3d0..3a2aeeffee7c 100644 > --- a/drivers/gpu/drm/i915/display/intel_bw.c > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > @@ -743,20 +743,51 @@ static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state, > } > } > > -static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state, > +static int intel_plane_bw_bpp(const struct drm_format_info *info) > +{ > + /* > + * For the purposes of memory bandwidth calculations, > + * planar formats are treated as if both planes had the > + * same bpp (with no reduction for vertical > + * subsampling). I.e we take as usual the worst case > + * scenario. > + */ > + if (drm_format_info_is_yuv_semiplanar(info)) > + return 2 * max(info->cpp[0], info->cpp[1]); > + > + return info->cpp[0]; > +} > + > +static void skl_crtc_calc_dbuf_bw(struct intel_atomic_state *state, > + struct intel_bw_state *bw_state, > const struct intel_crtc_state *crtc_state) > { > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > struct drm_i915_private *i915 = to_i915(crtc->base.dev); > struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe]; > - enum plane_id plane_id; > + struct intel_plane *plane; > > memset(crtc_bw, 0, sizeof(*crtc_bw)); > > if (!crtc_state->hw.active) > return; > > - for_each_plane_id_on_crtc(crtc, plane_id) { > + for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { > + const struct drm_framebuffer *fb; > + enum plane_id plane_id = plane->id; > + unsigned int plane_bpp = 0; > + struct intel_plane_state *plane_state = > + intel_atomic_get_new_plane_state(state, plane); > + > + if (plane_state) { > + fb = plane_state->hw.fb; > + > + if (plane_state->uapi.visible && fb) > + plane_bpp = intel_plane_bw_bpp(fb->format); > + } > + > + crtc_bw->pipe_cumulative_bpp += plane_bpp; > + > /* > * We assume cursors are small enough > * to not cause bandwidth problems. > @@ -773,6 +804,10 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state, > &crtc_state->wm.skl.plane_ddb_y[plane_id], > crtc_state->data_rate[plane_id]); > } > + > + crtc_bw->bpp_cdclk = DIV_ROUND_UP_ULL(mul_u32_u32(crtc_state->pixel_rate, > + crtc_bw->pipe_cumulative_bpp * 512), > + 10) / 1000; > } > > /* "Maximum Data Buffer Bandwidth" */ > @@ -782,11 +817,13 @@ intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915, > { > unsigned int total_max_bw = 0; > enum dbuf_slice slice; > + enum pipe pipe; > + unsigned int bpp_cdclk = 0; > + unsigned int dbuf_bw_cdclk; > > for_each_dbuf_slice(i915, slice) { > int num_active_planes = 0; > unsigned int max_bw = 0; > - enum pipe pipe; > > /* > * The arbiter can only really guarantee an > @@ -803,7 +840,29 @@ intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915, > total_max_bw = max(total_max_bw, max_bw); > } > > - return DIV_ROUND_UP(total_max_bw, 64); > + for_each_pipe(i915, pipe) { > + const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe]; > + /* > + * From BSpec 64631: > + * Pipe cumulative bytes should be less or equal to > + * CDCLK / (pixel_rate * scaling_factors * 51.2) thus > + * CDCLK = pipe_cumulative_bpp * pixel_rate * scaling_factors * 51.2. > + * Considering that intel_plane_pixel_rate already returns adjusted pixel rate, > + * no scaling factors needed here. > + */ > + bpp_cdclk = max_t(unsigned int, crtc_bw->bpp_cdclk, > + bpp_cdclk); > + } > + > + dbuf_bw_cdclk = DIV_ROUND_UP(total_max_bw, 64); > + > + /* > + * So now we have two CDCLK estimations: > + * one is based on required DBuf BW and another is > + * based on pipe cumulative bpp W/A(BSpec 64631) > + * Traditionally take the more demanding into use(worst case) > + */ > + return max_t(unsigned int, dbuf_bw_cdclk, bpp_cdclk); > } > > int intel_bw_min_cdclk(struct drm_i915_private *i915, > @@ -842,7 +901,7 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, > > old_bw_state = intel_atomic_get_old_bw_state(state); > > - skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state); > + skl_crtc_calc_dbuf_bw(state, new_bw_state, crtc_state); > > new_bw_state->min_cdclk[crtc->pipe] = > intel_bw_crtc_min_cdclk(crtc_state); > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h > index cb7ee3a24a58..9e3a6ad03b19 100644 > --- a/drivers/gpu/drm/i915/display/intel_bw.h > +++ b/drivers/gpu/drm/i915/display/intel_bw.h > @@ -19,6 +19,8 @@ struct intel_crtc_state; > struct intel_dbuf_bw { > unsigned int max_bw[I915_MAX_DBUF_SLICES]; > u8 active_planes[I915_MAX_DBUF_SLICES]; > + unsigned int pipe_cumulative_bpp; > + unsigned int bpp_cdclk; > }; > > struct intel_bw_state { > -- > 2.24.1.485.gad05a3d8e5 -- Ville Syrjälä Intel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A 2022-04-07 11:10 ` [Intel-gfx] [PATCH] " Ville Syrjälä @ 2022-04-07 11:24 ` Lisovskiy, Stanislav 2022-04-07 12:04 ` Ville Syrjälä 2022-04-07 11:39 ` Lisovskiy, Stanislav 1 sibling, 1 reply; 12+ messages in thread From: Lisovskiy, Stanislav @ 2022-04-07 11:24 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx On Thu, Apr 07, 2022 at 02:10:52PM +0300, Ville Syrjälä wrote: > On Thu, Apr 07, 2022 at 11:42:35AM +0300, Stanislav Lisovskiy wrote: > > We had some FIFO underruns appearing on platforms like ADL, > > which could be fixed though by increasing CDCLK, however we were > > lacking explanation for that - we were not calculating CDCLK, > > also based on cumulative bpp W/A formula, mentioned in BSpec 64631. > > We already have that in intel_bw_crtc_min_cdclk(). It actually is not quite what BSpec is talking about it adds data_rate per plane, instead of bpp, I think it confuses those 2 from BSpec: " Plane required bandwidth MB/s = pixel rate MHz * source pixel format in bytes * plane down scale amount * pipe down scale amount Display required memory bandwidth MB/s += Plane required bandwidth Pipe cumulative bytes per pixel += plane source pixel format in bytes " then we have to different formulas used to estimate whats the CDCLK should be, one is "DBUF maximum data buffer bandwidth MB/s = CDCLK frequency MHz * 64 Bytes" another is pipe CDCLK = cumulative bytes per pixel * (pixel rate MHz * plane down scale amount * pipe down scale amount)) * 51.2) So as I checked for some tests in kms_plane_multiple the estimation from the latter was sometimes higher than the one we currently have and it happened exactly when we did have FIFO underruns, otherwise CDCLK stayed pretty much the same, which also shows that there is something obvisously wrong with current calculations. That patch fixes it and we don't have underruns at after it is applied. Stan > > > > > With that patch no FIFO underruns appear anymore. > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_bw.c | 71 ++++++++++++++++++++++--- > > drivers/gpu/drm/i915/display/intel_bw.h | 2 + > > 2 files changed, 67 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > > index 37bd7b17f3d0..3a2aeeffee7c 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bw.c > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > > @@ -743,20 +743,51 @@ static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state, > > } > > } > > > > -static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state, > > +static int intel_plane_bw_bpp(const struct drm_format_info *info) > > +{ > > + /* > > + * For the purposes of memory bandwidth calculations, > > + * planar formats are treated as if both planes had the > > + * same bpp (with no reduction for vertical > > + * subsampling). I.e we take as usual the worst case > > + * scenario. > > + */ > > + if (drm_format_info_is_yuv_semiplanar(info)) > > + return 2 * max(info->cpp[0], info->cpp[1]); > > + > > + return info->cpp[0]; > > +} > > + > > +static void skl_crtc_calc_dbuf_bw(struct intel_atomic_state *state, > > + struct intel_bw_state *bw_state, > > const struct intel_crtc_state *crtc_state) > > { > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > > struct drm_i915_private *i915 = to_i915(crtc->base.dev); > > struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe]; > > - enum plane_id plane_id; > > + struct intel_plane *plane; > > > > memset(crtc_bw, 0, sizeof(*crtc_bw)); > > > > if (!crtc_state->hw.active) > > return; > > > > - for_each_plane_id_on_crtc(crtc, plane_id) { > > + for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { > > + const struct drm_framebuffer *fb; > > + enum plane_id plane_id = plane->id; > > + unsigned int plane_bpp = 0; > > + struct intel_plane_state *plane_state = > > + intel_atomic_get_new_plane_state(state, plane); > > + > > + if (plane_state) { > > + fb = plane_state->hw.fb; > > + > > + if (plane_state->uapi.visible && fb) > > + plane_bpp = intel_plane_bw_bpp(fb->format); > > + } > > + > > + crtc_bw->pipe_cumulative_bpp += plane_bpp; > > + > > /* > > * We assume cursors are small enough > > * to not cause bandwidth problems. > > @@ -773,6 +804,10 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state, > > &crtc_state->wm.skl.plane_ddb_y[plane_id], > > crtc_state->data_rate[plane_id]); > > } > > + > > + crtc_bw->bpp_cdclk = DIV_ROUND_UP_ULL(mul_u32_u32(crtc_state->pixel_rate, > > + crtc_bw->pipe_cumulative_bpp * 512), > > + 10) / 1000; > > } > > > > /* "Maximum Data Buffer Bandwidth" */ > > @@ -782,11 +817,13 @@ intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915, > > { > > unsigned int total_max_bw = 0; > > enum dbuf_slice slice; > > + enum pipe pipe; > > + unsigned int bpp_cdclk = 0; > > + unsigned int dbuf_bw_cdclk; > > > > for_each_dbuf_slice(i915, slice) { > > int num_active_planes = 0; > > unsigned int max_bw = 0; > > - enum pipe pipe; > > > > /* > > * The arbiter can only really guarantee an > > @@ -803,7 +840,29 @@ intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915, > > total_max_bw = max(total_max_bw, max_bw); > > } > > > > - return DIV_ROUND_UP(total_max_bw, 64); > > + for_each_pipe(i915, pipe) { > > + const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe]; > > + /* > > + * From BSpec 64631: > > + * Pipe cumulative bytes should be less or equal to > > + * CDCLK / (pixel_rate * scaling_factors * 51.2) thus > > + * CDCLK = pipe_cumulative_bpp * pixel_rate * scaling_factors * 51.2. > > + * Considering that intel_plane_pixel_rate already returns adjusted pixel rate, > > + * no scaling factors needed here. > > + */ > > + bpp_cdclk = max_t(unsigned int, crtc_bw->bpp_cdclk, > > + bpp_cdclk); > > + } > > + > > + dbuf_bw_cdclk = DIV_ROUND_UP(total_max_bw, 64); > > + > > + /* > > + * So now we have two CDCLK estimations: > > + * one is based on required DBuf BW and another is > > + * based on pipe cumulative bpp W/A(BSpec 64631) > > + * Traditionally take the more demanding into use(worst case) > > + */ > > + return max_t(unsigned int, dbuf_bw_cdclk, bpp_cdclk); > > } > > > > int intel_bw_min_cdclk(struct drm_i915_private *i915, > > @@ -842,7 +901,7 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, > > > > old_bw_state = intel_atomic_get_old_bw_state(state); > > > > - skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state); > > + skl_crtc_calc_dbuf_bw(state, new_bw_state, crtc_state); > > > > new_bw_state->min_cdclk[crtc->pipe] = > > intel_bw_crtc_min_cdclk(crtc_state); > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h > > index cb7ee3a24a58..9e3a6ad03b19 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bw.h > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h > > @@ -19,6 +19,8 @@ struct intel_crtc_state; > > struct intel_dbuf_bw { > > unsigned int max_bw[I915_MAX_DBUF_SLICES]; > > u8 active_planes[I915_MAX_DBUF_SLICES]; > > + unsigned int pipe_cumulative_bpp; > > + unsigned int bpp_cdclk; > > }; > > > > struct intel_bw_state { > > -- > > 2.24.1.485.gad05a3d8e5 > > -- > Ville Syrjälä > Intel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A 2022-04-07 11:24 ` Lisovskiy, Stanislav @ 2022-04-07 12:04 ` Ville Syrjälä 0 siblings, 0 replies; 12+ messages in thread From: Ville Syrjälä @ 2022-04-07 12:04 UTC (permalink / raw) To: Lisovskiy, Stanislav; +Cc: intel-gfx On Thu, Apr 07, 2022 at 02:24:17PM +0300, Lisovskiy, Stanislav wrote: > On Thu, Apr 07, 2022 at 02:10:52PM +0300, Ville Syrjälä wrote: > > On Thu, Apr 07, 2022 at 11:42:35AM +0300, Stanislav Lisovskiy wrote: > > > We had some FIFO underruns appearing on platforms like ADL, > > > which could be fixed though by increasing CDCLK, however we were > > > lacking explanation for that - we were not calculating CDCLK, > > > also based on cumulative bpp W/A formula, mentioned in BSpec 64631. > > > > We already have that in intel_bw_crtc_min_cdclk(). > > It actually is not quite what BSpec is talking about it adds > data_rate per plane, instead of bpp, I think it confuses > those 2 from BSpec: > > " > Plane required bandwidth MB/s = pixel rate MHz * source pixel format in bytes > * plane down scale amount * pipe down scale amount > Display required memory bandwidth MB/s += Plane required bandwidth > Pipe cumulative bytes per pixel += plane source pixel format in bytes > " > > then we have to different formulas used to estimate whats the CDCLK > should be, one is "DBUF maximum data buffer bandwidth MB/s = CDCLK frequency MHz * 64 Bytes" > > another is pipe CDCLK = cumulative bytes per pixel * (pixel rate MHz * > plane down scale amount * pipe down scale amount)) * 51.2) That specific statement in the spec is kinda nonsense. Mixing "plane up/down scale amount" (which is per plane) with this "cumulative bytes per pixel" thing (which is sum of bytes per pixel across all planes) doesn't make sense. What we so is sum bytes_per_pixel*pixel_rate*plane_up/down_scale from all planes, which I think is what the spec is trying to say as that is the cumulative bw used up by all the planes. -- Ville Syrjälä Intel ^ permalink raw reply [flat|nested] 12+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A 2022-04-07 11:10 ` [Intel-gfx] [PATCH] " Ville Syrjälä 2022-04-07 11:24 ` Lisovskiy, Stanislav @ 2022-04-07 11:39 ` Lisovskiy, Stanislav 1 sibling, 0 replies; 12+ messages in thread From: Lisovskiy, Stanislav @ 2022-04-07 11:39 UTC (permalink / raw) To: Ville Syrjälä; +Cc: intel-gfx On Thu, Apr 07, 2022 at 02:10:52PM +0300, Ville Syrjälä wrote: > On Thu, Apr 07, 2022 at 11:42:35AM +0300, Stanislav Lisovskiy wrote: > > We had some FIFO underruns appearing on platforms like ADL, > > which could be fixed though by increasing CDCLK, however we were > > lacking explanation for that - we were not calculating CDCLK, > > also based on cumulative bpp W/A formula, mentioned in BSpec 64631. > > We already have that in intel_bw_crtc_min_cdclk(). One more remark, is that actually indeed the data rate should be fine for that, but looks like for some reason those calculations we have currently are not pessimistic enough. Could be because mine are lacking scaling factor - but in kms_plane_multiple we don't use scaling. Wondering if its those multiplane formats, because as I see you don't add those gens >= 11. Or something else - there must be something different, because it manages to raise CDCLK now exactly at "right" moments to avoid FIFO underrun. Stan > > > > > With that patch no FIFO underruns appear anymore. > > > > Signed-off-by: Stanislav Lisovskiy <stanislav.lisovskiy@intel.com> > > --- > > drivers/gpu/drm/i915/display/intel_bw.c | 71 ++++++++++++++++++++++--- > > drivers/gpu/drm/i915/display/intel_bw.h | 2 + > > 2 files changed, 67 insertions(+), 6 deletions(-) > > > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.c b/drivers/gpu/drm/i915/display/intel_bw.c > > index 37bd7b17f3d0..3a2aeeffee7c 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bw.c > > +++ b/drivers/gpu/drm/i915/display/intel_bw.c > > @@ -743,20 +743,51 @@ static void skl_plane_calc_dbuf_bw(struct intel_bw_state *bw_state, > > } > > } > > > > -static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state, > > +static int intel_plane_bw_bpp(const struct drm_format_info *info) > > +{ > > + /* > > + * For the purposes of memory bandwidth calculations, > > + * planar formats are treated as if both planes had the > > + * same bpp (with no reduction for vertical > > + * subsampling). I.e we take as usual the worst case > > + * scenario. > > + */ > > + if (drm_format_info_is_yuv_semiplanar(info)) > > + return 2 * max(info->cpp[0], info->cpp[1]); > > + > > + return info->cpp[0]; > > +} > > + > > +static void skl_crtc_calc_dbuf_bw(struct intel_atomic_state *state, > > + struct intel_bw_state *bw_state, > > const struct intel_crtc_state *crtc_state) > > { > > struct intel_crtc *crtc = to_intel_crtc(crtc_state->uapi.crtc); > > struct drm_i915_private *i915 = to_i915(crtc->base.dev); > > struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[crtc->pipe]; > > - enum plane_id plane_id; > > + struct intel_plane *plane; > > > > memset(crtc_bw, 0, sizeof(*crtc_bw)); > > > > if (!crtc_state->hw.active) > > return; > > > > - for_each_plane_id_on_crtc(crtc, plane_id) { > > + for_each_intel_plane_on_crtc(&i915->drm, crtc, plane) { > > + const struct drm_framebuffer *fb; > > + enum plane_id plane_id = plane->id; > > + unsigned int plane_bpp = 0; > > + struct intel_plane_state *plane_state = > > + intel_atomic_get_new_plane_state(state, plane); > > + > > + if (plane_state) { > > + fb = plane_state->hw.fb; > > + > > + if (plane_state->uapi.visible && fb) > > + plane_bpp = intel_plane_bw_bpp(fb->format); > > + } > > + > > + crtc_bw->pipe_cumulative_bpp += plane_bpp; > > + > > /* > > * We assume cursors are small enough > > * to not cause bandwidth problems. > > @@ -773,6 +804,10 @@ static void skl_crtc_calc_dbuf_bw(struct intel_bw_state *bw_state, > > &crtc_state->wm.skl.plane_ddb_y[plane_id], > > crtc_state->data_rate[plane_id]); > > } > > + > > + crtc_bw->bpp_cdclk = DIV_ROUND_UP_ULL(mul_u32_u32(crtc_state->pixel_rate, > > + crtc_bw->pipe_cumulative_bpp * 512), > > + 10) / 1000; > > } > > > > /* "Maximum Data Buffer Bandwidth" */ > > @@ -782,11 +817,13 @@ intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915, > > { > > unsigned int total_max_bw = 0; > > enum dbuf_slice slice; > > + enum pipe pipe; > > + unsigned int bpp_cdclk = 0; > > + unsigned int dbuf_bw_cdclk; > > > > for_each_dbuf_slice(i915, slice) { > > int num_active_planes = 0; > > unsigned int max_bw = 0; > > - enum pipe pipe; > > > > /* > > * The arbiter can only really guarantee an > > @@ -803,7 +840,29 @@ intel_bw_dbuf_min_cdclk(struct drm_i915_private *i915, > > total_max_bw = max(total_max_bw, max_bw); > > } > > > > - return DIV_ROUND_UP(total_max_bw, 64); > > + for_each_pipe(i915, pipe) { > > + const struct intel_dbuf_bw *crtc_bw = &bw_state->dbuf_bw[pipe]; > > + /* > > + * From BSpec 64631: > > + * Pipe cumulative bytes should be less or equal to > > + * CDCLK / (pixel_rate * scaling_factors * 51.2) thus > > + * CDCLK = pipe_cumulative_bpp * pixel_rate * scaling_factors * 51.2. > > + * Considering that intel_plane_pixel_rate already returns adjusted pixel rate, > > + * no scaling factors needed here. > > + */ > > + bpp_cdclk = max_t(unsigned int, crtc_bw->bpp_cdclk, > > + bpp_cdclk); > > + } > > + > > + dbuf_bw_cdclk = DIV_ROUND_UP(total_max_bw, 64); > > + > > + /* > > + * So now we have two CDCLK estimations: > > + * one is based on required DBuf BW and another is > > + * based on pipe cumulative bpp W/A(BSpec 64631) > > + * Traditionally take the more demanding into use(worst case) > > + */ > > + return max_t(unsigned int, dbuf_bw_cdclk, bpp_cdclk); > > } > > > > int intel_bw_min_cdclk(struct drm_i915_private *i915, > > @@ -842,7 +901,7 @@ int intel_bw_calc_min_cdclk(struct intel_atomic_state *state, > > > > old_bw_state = intel_atomic_get_old_bw_state(state); > > > > - skl_crtc_calc_dbuf_bw(new_bw_state, crtc_state); > > + skl_crtc_calc_dbuf_bw(state, new_bw_state, crtc_state); > > > > new_bw_state->min_cdclk[crtc->pipe] = > > intel_bw_crtc_min_cdclk(crtc_state); > > diff --git a/drivers/gpu/drm/i915/display/intel_bw.h b/drivers/gpu/drm/i915/display/intel_bw.h > > index cb7ee3a24a58..9e3a6ad03b19 100644 > > --- a/drivers/gpu/drm/i915/display/intel_bw.h > > +++ b/drivers/gpu/drm/i915/display/intel_bw.h > > @@ -19,6 +19,8 @@ struct intel_crtc_state; > > struct intel_dbuf_bw { > > unsigned int max_bw[I915_MAX_DBUF_SLICES]; > > u8 active_planes[I915_MAX_DBUF_SLICES]; > > + unsigned int pipe_cumulative_bpp; > > + unsigned int bpp_cdclk; > > }; > > > > struct intel_bw_state { > > -- > > 2.24.1.485.gad05a3d8e5 > > -- > Ville Syrjälä > Intel ^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A (rev2) 2022-04-07 8:42 [Intel-gfx] [PATCH] drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A Stanislav Lisovskiy ` (3 preceding siblings ...) 2022-04-07 11:10 ` [Intel-gfx] [PATCH] " Ville Syrjälä @ 2022-04-07 13:06 ` Patchwork 2022-04-07 13:39 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2022-04-07 13:39 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork 6 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2022-04-07 13:06 UTC (permalink / raw) To: Lisovskiy, Stanislav; +Cc: intel-gfx == Series Details == Series: drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A (rev2) URL : https://patchwork.freedesktop.org/series/102322/ State : warning == Summary == $ dim checkpatch origin/drm-tip c1adc525a765 drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A -:81: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #81: FILE: drivers/gpu/drm/i915/display/intel_bw.c:809: + crtc_bw->bpp_cdclk = DIV_ROUND_UP_ULL(mul_u32_u32(crtc_state->pixel_rate, + crtc_bw->pipe_cumulative_bpp * 512), -:117: CHECK:PARENTHESIS_ALIGNMENT: Alignment should match open parenthesis #117: FILE: drivers/gpu/drm/i915/display/intel_bw.c:854: + bpp_cdclk = max_t(unsigned int, crtc_bw->bpp_cdclk, + bpp_cdclk); total: 0 errors, 0 warnings, 2 checks, 124 lines checked ^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A (rev2) 2022-04-07 8:42 [Intel-gfx] [PATCH] drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A Stanislav Lisovskiy ` (4 preceding siblings ...) 2022-04-07 13:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A (rev2) Patchwork @ 2022-04-07 13:39 ` Patchwork 2022-04-07 13:39 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork 6 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2022-04-07 13:39 UTC (permalink / raw) To: Lisovskiy, Stanislav; +Cc: intel-gfx [-- Attachment #1: Type: text/plain, Size: 8327 bytes --] == Series Details == Series: drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A (rev2) URL : https://patchwork.freedesktop.org/series/102322/ State : failure == Summary == CI Bug Log - changes from CI_DRM_11471 -> Patchwork_22810 ==================================================== Summary ------- **FAILURE** Serious unknown changes coming with Patchwork_22810 absolutely need to be verified manually. If you think the reported changes have nothing to do with the changes introduced in Patchwork_22810, please notify your bug team to allow them to document this new failure mode, which will reduce false positives in CI. External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/index.html Participating hosts (50 -> 48) ------------------------------ Additional (3): fi-tgl-u2 bat-hsw-1 fi-pnv-d510 Missing (5): shard-tglu fi-bsw-cyan fi-ctg-p8600 shard-rkl fi-bdw-samus Possible new issues ------------------- Here are the unknown changes that may have been introduced in Patchwork_22810: ### IGT changes ### #### Possible regressions #### * igt@i915_selftest@live@coherency: - fi-bdw-5557u: NOTRUN -> [INCOMPLETE][1] [1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-bdw-5557u/igt@i915_selftest@live@coherency.html Known issues ------------ Here are the changes found in Patchwork_22810 that come from known issues: ### IGT changes ### #### Issues hit #### * igt@amdgpu/amd_basic@semaphore: - fi-hsw-4770: NOTRUN -> [SKIP][2] ([fdo#109271] / [fdo#109315]) +17 similar issues [2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-hsw-4770/igt@amdgpu/amd_basic@semaphore.html * igt@gem_huc_copy@huc-copy: - fi-pnv-d510: NOTRUN -> [SKIP][3] ([fdo#109271]) +57 similar issues [3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-pnv-d510/igt@gem_huc_copy@huc-copy.html - fi-tgl-u2: NOTRUN -> [SKIP][4] ([i915#2190]) [4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-tgl-u2/igt@gem_huc_copy@huc-copy.html * igt@kms_busy@basic@flip: - fi-tgl-u2: NOTRUN -> [DMESG-WARN][5] ([i915#402]) [5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-tgl-u2/igt@kms_busy@basic@flip.html * igt@kms_chamelium@common-hpd-after-suspend: - fi-tgl-u2: NOTRUN -> [SKIP][6] ([fdo#109284] / [fdo#111827]) +8 similar issues [6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-tgl-u2/igt@kms_chamelium@common-hpd-after-suspend.html * igt@kms_chamelium@vga-edid-read: - fi-bdw-5557u: NOTRUN -> [SKIP][7] ([fdo#109271] / [fdo#111827]) +8 similar issues [7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-bdw-5557u/igt@kms_chamelium@vga-edid-read.html * igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic: - fi-tgl-u2: NOTRUN -> [SKIP][8] ([i915#4103]) +1 similar issue [8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-tgl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html * igt@kms_force_connector_basic@force-load-detect: - fi-tgl-u2: NOTRUN -> [SKIP][9] ([fdo#109285]) [9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-tgl-u2/igt@kms_force_connector_basic@force-load-detect.html * igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c: - fi-pnv-d510: NOTRUN -> [SKIP][10] ([fdo#109271] / [i915#5341]) [10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-pnv-d510/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-c.html * igt@kms_setmode@basic-clone-single-crtc: - fi-bdw-5557u: NOTRUN -> [SKIP][11] ([fdo#109271]) +14 similar issues [11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-bdw-5557u/igt@kms_setmode@basic-clone-single-crtc.html - fi-tgl-u2: NOTRUN -> [SKIP][12] ([i915#3555]) [12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-tgl-u2/igt@kms_setmode@basic-clone-single-crtc.html #### Possible fixes #### * igt@gem_exec_suspend@basic-s3@smem: - fi-bdw-5557u: [INCOMPLETE][13] ([i915#146]) -> [PASS][14] [13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11471/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html [14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-bdw-5557u/igt@gem_exec_suspend@basic-s3@smem.html * igt@i915_selftest@live@gt_heartbeat: - {fi-tgl-dsi}: [DMESG-FAIL][15] -> [PASS][16] [15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11471/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html [16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-tgl-dsi/igt@i915_selftest@live@gt_heartbeat.html * igt@i915_selftest@live@hangcheck: - fi-hsw-4770: [INCOMPLETE][17] ([i915#4785]) -> [PASS][18] [17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11471/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html [18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-hsw-4770/igt@i915_selftest@live@hangcheck.html #### Warnings #### * igt@core_hotunplug@unbind-rebind: - fi-kbl-soraka: [DMESG-WARN][19] ([i915#1982] / [i915#5437]) -> [DMESG-WARN][20] ([i915#5437]) [19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11471/fi-kbl-soraka/igt@core_hotunplug@unbind-rebind.html [20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/fi-kbl-soraka/igt@core_hotunplug@unbind-rebind.html {name}: This element is suppressed. This means it is ignored when computing the status of the difference (SUCCESS, WARNING, or FAILURE). [fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271 [fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284 [fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285 [fdo#109315]: https://bugs.freedesktop.org/show_bug.cgi?id=109315 [fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827 [i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072 [i915#146]: https://gitlab.freedesktop.org/drm/intel/issues/146 [i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982 [i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190 [i915#2722]: https://gitlab.freedesktop.org/drm/intel/issues/2722 [i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012 [i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555 [i915#402]: https://gitlab.freedesktop.org/drm/intel/issues/402 [i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103 [i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312 [i915#4785]: https://gitlab.freedesktop.org/drm/intel/issues/4785 [i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533 [i915#5341]: https://gitlab.freedesktop.org/drm/intel/issues/5341 [i915#5437]: https://gitlab.freedesktop.org/drm/intel/issues/5437 [i915#5535]: https://gitlab.freedesktop.org/drm/intel/issues/5535 [i915#5552]: https://gitlab.freedesktop.org/drm/intel/issues/5552 Build changes ------------- * Linux: CI_DRM_11471 -> Patchwork_22810 CI-20190529: 20190529 CI_DRM_11471: 7067f6f93e8c8b40c9b4592d7674d0ae0960bab6 @ git://anongit.freedesktop.org/gfx-ci/linux IGT_6415: c3b690bd5f7fb1fb7ed786ab0f3b815930a6a55f @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git Patchwork_22810: c1adc525a765a01e12d87e5e405c6ee612dde2eb @ git://anongit.freedesktop.org/gfx-ci/linux == Kernel 32bit build == Warning: Kernel 32bit buildtest failed: https://intel-gfx-ci.01.org/Patchwork_22810/build_32bit.log CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) MODPOST modules-only.symvers ERROR: modpost: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined! scripts/Makefile.modpost:134: recipe for target 'modules-only.symvers' failed make[1]: *** [modules-only.symvers] Error 1 make[1]: *** Deleting file 'modules-only.symvers' Makefile:1749: recipe for target 'modules' failed make: *** [modules] Error 2 == Linux commits == c1adc525a765 drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/index.html [-- Attachment #2: Type: text/html, Size: 9602 bytes --] ^ permalink raw reply [flat|nested] 12+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BUILD: warning for drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A (rev2) 2022-04-07 8:42 [Intel-gfx] [PATCH] drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A Stanislav Lisovskiy ` (5 preceding siblings ...) 2022-04-07 13:39 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork @ 2022-04-07 13:39 ` Patchwork 6 siblings, 0 replies; 12+ messages in thread From: Patchwork @ 2022-04-07 13:39 UTC (permalink / raw) To: Lisovskiy, Stanislav; +Cc: intel-gfx == Series Details == Series: drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A (rev2) URL : https://patchwork.freedesktop.org/series/102322/ State : warning == Summary == CALL scripts/checksyscalls.sh CALL scripts/atomic/check-atomics.sh CHK include/generated/compile.h Kernel: arch/x86/boot/bzImage is ready (#1) MODPOST modules-only.symvers ERROR: modpost: "__udivdi3" [drivers/gpu/drm/i915/i915.ko] undefined! scripts/Makefile.modpost:134: recipe for target 'modules-only.symvers' failed make[1]: *** [modules-only.symvers] Error 1 make[1]: *** Deleting file 'modules-only.symvers' Makefile:1749: recipe for target 'modules' failed make: *** [modules] Error 2 == Logs == For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_22810/build_32bit.log ^ permalink raw reply [flat|nested] 12+ messages in thread
end of thread, other threads:[~2022-04-07 13:39 UTC | newest] Thread overview: 12+ messages (download: mbox.gz / follow: Atom feed) -- links below jump to the message on this page -- 2022-04-07 8:42 [Intel-gfx] [PATCH] drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A Stanislav Lisovskiy 2022-04-07 8:51 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork 2022-04-07 9:23 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2022-04-07 9:59 ` Lisovskiy, Stanislav 2022-04-07 9:23 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork 2022-04-07 11:10 ` [Intel-gfx] [PATCH] " Ville Syrjälä 2022-04-07 11:24 ` Lisovskiy, Stanislav 2022-04-07 12:04 ` Ville Syrjälä 2022-04-07 11:39 ` Lisovskiy, Stanislav 2022-04-07 13:06 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Fix FIFO underruns caused by missing cumulative bpp W/A (rev2) Patchwork 2022-04-07 13:39 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork 2022-04-07 13:39 ` [Intel-gfx] ✗ Fi.CI.BUILD: warning " Patchwork
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