[PATCH 1/2] arm64: dts: ti: k3-am65: Configure pinctrl for timer IO pads

[PATCH 1/2] arm64: dts: ti: k3-am65: Configure pinctrl for timer IO pads

[Tony Lindgren]

Compared to the earlier TI SoCs, am6 has an additional level of dedicated
multiplexing registers for the timer IO pads.

There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.

There are timer IO control registers for input and output. The registers
for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control
the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and
CTRLMMR_MCU_TIMERIO*_CTRL the output.

The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control
Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the
CASCADE_EN bit is documented in TRM "12.8.3.1 Timers Overview".

For chaining timers, the timer IO control registers also have a CASCADE_EN
input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit
muxes the previous timer output, or possibly and external TIMER_IO pad
source, to the input clock of the selected timer instance for odd numered
timers. For even numbered timers the CASCADE_EN bit does not do anything.
The timer cascade input routing options are shown in TRM "Figure 12-3632.
Timers Overview". For handling beyond multiplexing, the driver support for
timer cascading should be likely be handled via the clock framework.

Cc: Keerthy <j-keerthy@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 18 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi  | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -130,6 +130,24 @@ rng: rng@4e10000 {
 		};
 	};
 
+	/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+	main_timerio_input: pinctrl@104200 {
+		compatible = "pinctrl-single";
+		reg = <0x0 0x104200 0x0 0x30>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x0000001ff>;
+	};
+
+	/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+	main_timerio_output: pinctrl@104280 {
+		compatible = "pinctrl-single";
+		reg = <0x0 0x104280 0x0 0x20>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x0000000f>;
+	};
+
 	main_pmx0: pinctrl@11c000 {
 		compatible = "pinctrl-single";
 		reg = <0x0 0x11c000 0x0 0x2e4>;
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -20,6 +20,24 @@ phy_gmii_sel: phy@4040 {
 		};
 	};
 
+	/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+	mcu_timerio_input: pinctrl@40f04200 {
+		compatible = "pinctrl-single";
+		reg = <0x0 0x40f04200 0x0 0x10>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x00000101>;
+	};
+
+	/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+	mcu_timerio_output: pinctrl@40f04280 {
+		compatible = "pinctrl-single";
+		reg = <0x0 0x40f04280 0x0 0x8>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x00000003>;
+	};
+
 	mcu_uart0: serial@40a00000 {
 		compatible = "ti,am654-uart";
 			reg = <0x00 0x40a00000 0x00 0x100>;
-- 
2.35.1

[PATCH 1/2] arm64: dts: ti: k3-am65: Configure pinctrl for timer IO pads

[Tony Lindgren]

Compared to the earlier TI SoCs, am6 has an additional level of dedicated
multiplexing registers for the timer IO pads.

There are timer IO pads in the MCU domain, and in the MAIN domain. These
pads can be muxed for the related timers.

There are timer IO control registers for input and output. The registers
for CTRLMMR_TIMER*_CTRL and CTRLMMR_MCU_TIMER*_CTRL are used to control
the input. The registers for CTCTRLMMR_TIMERIO*_CTRL and
CTRLMMR_MCU_TIMERIO*_CTRL the output.

The multiplexing is documented in TRM "5.1.2.3.1.4 Timer IO Muxing Control
Registers" and "5.1.3.3.1.5 Timer IO Muxing Control Registers", and the
CASCADE_EN bit is documented in TRM "12.8.3.1 Timers Overview".

For chaining timers, the timer IO control registers also have a CASCADE_EN
input bit in the CTRLMMR_TIMER*_CTRL in the registers. The CASCADE_EN bit
muxes the previous timer output, or possibly and external TIMER_IO pad
source, to the input clock of the selected timer instance for odd numered
timers. For even numbered timers the CASCADE_EN bit does not do anything.
The timer cascade input routing options are shown in TRM "Figure 12-3632.
Timers Overview". For handling beyond multiplexing, the driver support for
timer cascading should be likely be handled via the clock framework.

Cc: Keerthy <j-keerthy@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 18 ++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi  | 18 ++++++++++++++++++
 2 files changed, 36 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -130,6 +130,24 @@ rng: rng@4e10000 {
 		};
 	};
 
+	/* TIMERIO pad input CTRLMMR_TIMER*_CTRL registers */
+	main_timerio_input: pinctrl@104200 {
+		compatible = "pinctrl-single";
+		reg = <0x0 0x104200 0x0 0x30>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x0000001ff>;
+	};
+
+	/* TIMERIO pad output CTCTRLMMR_TIMERIO*_CTRL registers */
+	main_timerio_output: pinctrl@104280 {
+		compatible = "pinctrl-single";
+		reg = <0x0 0x104280 0x0 0x20>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x0000000f>;
+	};
+
 	main_pmx0: pinctrl@11c000 {
 		compatible = "pinctrl-single";
 		reg = <0x0 0x11c000 0x0 0x2e4>;
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -20,6 +20,24 @@ phy_gmii_sel: phy@4040 {
 		};
 	};
 
+	/* MCU_TIMERIO pad input CTRLMMR_MCU_TIMER*_CTRL registers */
+	mcu_timerio_input: pinctrl@40f04200 {
+		compatible = "pinctrl-single";
+		reg = <0x0 0x40f04200 0x0 0x10>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x00000101>;
+	};
+
+	/* MCU_TIMERIO pad output CTRLMMR_MCU_TIMERIO*_CTRL registers */
+	mcu_timerio_output: pinctrl@40f04280 {
+		compatible = "pinctrl-single";
+		reg = <0x0 0x40f04280 0x0 0x8>;
+		#pinctrl-cells = <1>;
+		pinctrl-single,register-width = <32>;
+		pinctrl-single,function-mask = <0x00000003>;
+	};
+
 	mcu_uart0: serial@40a00000 {
 		compatible = "ti,am654-uart";
 			reg = <0x00 0x40a00000 0x00 0x100>;
-- 
2.35.1

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[PATCH 2/2] arm64: dts: ti: k3-am65: Add general purpose timers for am65

[Tony Lindgren]

There are 12 general purpose timers on am65 that can be used for things
like PWM using pwm-omap-dmtimer driver. There are also additional four
timers in the MCU domain do not have interrupts routable for Linux and
are likely reserved by the software for the ESM module.

Compared to am64, the timer clocks are different on am65. And the MCU
timers are at a different IO address. Then j72 adds more timers compared
to am65 with a total of 30 timers. And the j72 clocks are different.

To avoid duplication for dtsi files, eventually we may want to consider
adding timer specific shared dtsi files with the timer clocks mapped
using SoC specific files in include/dt-bindings/clock. But let's get
am65 timers usable first.

Cc: Keerthy <j-keerthy@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi  |  41 +++++++++
 2 files changed, 149 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -271,6 +271,114 @@ main_spi4: spi@2140000 {
 		#size-cells = <0>;
 	};
 
+	main_timer0: timer@2400000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2400000 0x00 0x400>;
+		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 23 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer1: timer@2410000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2410000 0x00 0x400>;
+		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 24 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer2: timer@2420000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2420000 0x00 0x400>;
+		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 27 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer3: timer@2430000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2430000 0x00 0x400>;
+		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 28 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer4: timer@2440000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2440000 0x00 0x400>;
+		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 29 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer5: timer@2450000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2450000 0x00 0x400>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 30 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer6: timer@2460000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2460000 0x00 0x400>;
+		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 31 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer7: timer@2470000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2470000 0x00 0x400>;
+		interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 32 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer8: timer@2480000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2480000 0x00 0x400>;
+		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 33 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer9: timer@2490000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2490000 0x00 0x400>;
+		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 34 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer10: timer@24a0000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x24a0000 0x00 0x400>;
+		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 25 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer11: timer@24b0000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x24b0000 0x00 0x400>;
+		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 26 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
 	sdhci0: mmc@4f80000 {
 		compatible = "ti,am654-sdhci-5.1";
 		reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -132,6 +132,47 @@ adc {
 		};
 	};
 
+	/*
+	 * The MCU domain timer interrupts are routed only to the ESM module,
+	 * and not currently available for Linux. The MCU domain timers are
+	 * of limited use without interrupts, and likely reserved by the ESM.
+	 */
+	mcu_timer0: timer@40400000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x40400000 0x00 0x400>;
+		clocks = <&k3_clks 35 8>;
+		clock-names = "fck";
+		ti,timer-pwm;
+		status = "reserved";
+	};
+
+	mcu_timer1: timer@40410000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x40410000 0x00 0x400>;
+		clocks = <&k3_clks 36 8>;
+		clock-names = "fck";
+		ti,timer-pwm;
+		status = "reserved";
+	};
+
+	mcu_timer2: timer@40420000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x40420000 0x00 0x400>;
+		clocks = <&k3_clks 37 8>;
+		clock-names = "fck";
+		ti,timer-pwm;
+		status = "reserved";
+	};
+
+	mcu_timer3: timer@40430000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x40430000 0x00 0x400>;
+		clocks = <&k3_clks 38 8>;
+		clock-names = "fck";
+		ti,timer-pwm;
+		status = "reserved";
+	};
+
 	mcu_navss: bus@28380000 {
 		compatible = "simple-mfd";
 		#address-cells = <2>;
-- 
2.35.1

[PATCH 2/2] arm64: dts: ti: k3-am65: Add general purpose timers for am65

[Tony Lindgren]

There are 12 general purpose timers on am65 that can be used for things
like PWM using pwm-omap-dmtimer driver. There are also additional four
timers in the MCU domain do not have interrupts routable for Linux and
are likely reserved by the software for the ESM module.

Compared to am64, the timer clocks are different on am65. And the MCU
timers are at a different IO address. Then j72 adds more timers compared
to am65 with a total of 30 timers. And the j72 clocks are different.

To avoid duplication for dtsi files, eventually we may want to consider
adding timer specific shared dtsi files with the timer clocks mapped
using SoC specific files in include/dt-bindings/clock. But let's get
am65 timers usable first.

Cc: Keerthy <j-keerthy@ti.com>
Cc: Nishanth Menon <nm@ti.com>
Cc: Vignesh Raghavendra <vigneshr@ti.com>
Signed-off-by: Tony Lindgren <tony@atomide.com>
---
 arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++
 arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi  |  41 +++++++++
 2 files changed, 149 insertions(+)

diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
--- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
@@ -271,6 +271,114 @@ main_spi4: spi@2140000 {
 		#size-cells = <0>;
 	};
 
+	main_timer0: timer@2400000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2400000 0x00 0x400>;
+		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 23 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer1: timer@2410000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2410000 0x00 0x400>;
+		interrupts = <GIC_SPI 225 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 24 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer2: timer@2420000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2420000 0x00 0x400>;
+		interrupts = <GIC_SPI 226 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 27 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer3: timer@2430000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2430000 0x00 0x400>;
+		interrupts = <GIC_SPI 227 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 28 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer4: timer@2440000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2440000 0x00 0x400>;
+		interrupts = <GIC_SPI 228 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 29 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer5: timer@2450000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2450000 0x00 0x400>;
+		interrupts = <GIC_SPI 229 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 30 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer6: timer@2460000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2460000 0x00 0x400>;
+		interrupts = <GIC_SPI 230 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 31 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer7: timer@2470000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2470000 0x00 0x400>;
+		interrupts = <GIC_SPI 231 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 32 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer8: timer@2480000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2480000 0x00 0x400>;
+		interrupts = <GIC_SPI 232 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 33 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer9: timer@2490000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x2490000 0x00 0x400>;
+		interrupts = <GIC_SPI 233 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 34 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer10: timer@24a0000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x24a0000 0x00 0x400>;
+		interrupts = <GIC_SPI 234 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 25 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
+	main_timer11: timer@24b0000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x24b0000 0x00 0x400>;
+		interrupts = <GIC_SPI 235 IRQ_TYPE_LEVEL_HIGH>;
+		clocks = <&k3_clks 26 12>;
+		clock-names = "fck";
+		ti,timer-pwm;
+	};
+
 	sdhci0: mmc@4f80000 {
 		compatible = "ti,am654-sdhci-5.1";
 		reg = <0x0 0x4f80000 0x0 0x260>, <0x0 0x4f90000 0x0 0x134>;
diff --git a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
--- a/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
+++ b/arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi
@@ -132,6 +132,47 @@ adc {
 		};
 	};
 
+	/*
+	 * The MCU domain timer interrupts are routed only to the ESM module,
+	 * and not currently available for Linux. The MCU domain timers are
+	 * of limited use without interrupts, and likely reserved by the ESM.
+	 */
+	mcu_timer0: timer@40400000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x40400000 0x00 0x400>;
+		clocks = <&k3_clks 35 8>;
+		clock-names = "fck";
+		ti,timer-pwm;
+		status = "reserved";
+	};
+
+	mcu_timer1: timer@40410000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x40410000 0x00 0x400>;
+		clocks = <&k3_clks 36 8>;
+		clock-names = "fck";
+		ti,timer-pwm;
+		status = "reserved";
+	};
+
+	mcu_timer2: timer@40420000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x40420000 0x00 0x400>;
+		clocks = <&k3_clks 37 8>;
+		clock-names = "fck";
+		ti,timer-pwm;
+		status = "reserved";
+	};
+
+	mcu_timer3: timer@40430000 {
+		compatible = "ti,am6-timer";
+		reg = <0x00 0x40430000 0x00 0x400>;
+		clocks = <&k3_clks 38 8>;
+		clock-names = "fck";
+		ti,timer-pwm;
+		status = "reserved";
+	};
+
 	mcu_navss: bus@28380000 {
 		compatible = "simple-mfd";
 		#address-cells = <2>;
-- 
2.35.1

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Re: [PATCH 2/2] arm64: dts: ti: k3-am65: Add general purpose timers for am65

[Nishanth Menon]

On 13:47-20220407, Tony Lindgren wrote:
> There are 12 general purpose timers on am65 that can be used for things
> like PWM using pwm-omap-dmtimer driver. There are also additional four
> timers in the MCU domain do not have interrupts routable for Linux and
> are likely reserved by the software for the ESM module.
> 
> Compared to am64, the timer clocks are different on am65. And the MCU
> timers are at a different IO address. Then j72 adds more timers compared
> to am65 with a total of 30 timers. And the j72 clocks are different.
> 
> To avoid duplication for dtsi files, eventually we may want to consider
> adding timer specific shared dtsi files with the timer clocks mapped
> using SoC specific files in include/dt-bindings/clock. But let's get
> am65 timers usable first.
> 
> Cc: Keerthy <j-keerthy@ti.com>
> Cc: Nishanth Menon <nm@ti.com>
> Cc: Vignesh Raghavendra <vigneshr@ti.com>
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Link: https://lore.kernel.org/r/20220407104725.41755-2-tony@atomide.com
> ---
>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++
>  arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi  |  41 +++++++++
>  2 files changed, 149 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -271,6 +271,114 @@ main_spi4: spi@2140000 {
>  		#size-cells = <0>;
>  	};
>  
> +	main_timer0: timer@2400000 {
> +		compatible = "ti,am6-timer";
> +		reg = <0x00 0x2400000 0x00 0x400>;
> +		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&k3_clks 23 12>;
> +		clock-names = "fck";
> +		ti,timer-pwm;
> +	};

Tony,
Lets hold this back one more window.. ti,am6-timer should come
in the next rc1, but I still dont see this yet in next-20220706, So, i am
going to have to skip this window at least.
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

Re: [PATCH 2/2] arm64: dts: ti: k3-am65: Add general purpose timers for am65

[Nishanth Menon]

On 13:47-20220407, Tony Lindgren wrote:
> There are 12 general purpose timers on am65 that can be used for things
> like PWM using pwm-omap-dmtimer driver. There are also additional four
> timers in the MCU domain do not have interrupts routable for Linux and
> are likely reserved by the software for the ESM module.
> 
> Compared to am64, the timer clocks are different on am65. And the MCU
> timers are at a different IO address. Then j72 adds more timers compared
> to am65 with a total of 30 timers. And the j72 clocks are different.
> 
> To avoid duplication for dtsi files, eventually we may want to consider
> adding timer specific shared dtsi files with the timer clocks mapped
> using SoC specific files in include/dt-bindings/clock. But let's get
> am65 timers usable first.
> 
> Cc: Keerthy <j-keerthy@ti.com>
> Cc: Nishanth Menon <nm@ti.com>
> Cc: Vignesh Raghavendra <vigneshr@ti.com>
> Signed-off-by: Tony Lindgren <tony@atomide.com>
> Signed-off-by: Nishanth Menon <nm@ti.com>
> Link: https://lore.kernel.org/r/20220407104725.41755-2-tony@atomide.com
> ---
>  arch/arm64/boot/dts/ti/k3-am65-main.dtsi | 108 +++++++++++++++++++++++
>  arch/arm64/boot/dts/ti/k3-am65-mcu.dtsi  |  41 +++++++++
>  2 files changed, 149 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> @@ -271,6 +271,114 @@ main_spi4: spi@2140000 {
>  		#size-cells = <0>;
>  	};
>  
> +	main_timer0: timer@2400000 {
> +		compatible = "ti,am6-timer";
> +		reg = <0x00 0x2400000 0x00 0x400>;
> +		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> +		clocks = <&k3_clks 23 12>;
> +		clock-names = "fck";
> +		ti,timer-pwm;
> +	};

Tony,
Lets hold this back one more window.. ti,am6-timer should come
in the next rc1, but I still dont see this yet in next-20220706, So, i am
going to have to skip this window at least.
-- 
Regards,
Nishanth Menon
Key (0xDDB5849D1736249D) / Fingerprint: F8A2 8693 54EB 8232 17A3  1A34 DDB5 849D 1736 249D

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Re: [PATCH 2/2] arm64: dts: ti: k3-am65: Add general purpose timers for am65

[Tony Lindgren]

Hi,

* Nishanth Menon <nm@ti.com> [220706 23:16]:
> On 13:47-20220407, Tony Lindgren wrote:
> > diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > @@ -271,6 +271,114 @@ main_spi4: spi@2140000 {
> >  		#size-cells = <0>;
> >  	};
> >  
> > +	main_timer0: timer@2400000 {
> > +		compatible = "ti,am6-timer";
> > +		reg = <0x00 0x2400000 0x00 0x400>;
> > +		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> > +		clocks = <&k3_clks 23 12>;
> > +		clock-names = "fck";
> > +		ti,timer-pwm;
> > +	};
> 
> Tony,
> Lets hold this back one more window.. ti,am6-timer should come
> in the next rc1, but I still dont see this yet in next-20220706, So, i am
> going to have to skip this window at least.

I'm seeing the clock being too fast although debugfs reports the timer
source clock at 32k. Not quite sure what is wrong, maybe the clock index
should be 1 instead of 12 here. Best to wait with the dts patches until
the clock issue has bee sorted out.

Regards,

Tony

Re: [PATCH 2/2] arm64: dts: ti: k3-am65: Add general purpose timers for am65

[Tony Lindgren]

Hi,

* Nishanth Menon <nm@ti.com> [220706 23:16]:
> On 13:47-20220407, Tony Lindgren wrote:
> > diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > @@ -271,6 +271,114 @@ main_spi4: spi@2140000 {
> >  		#size-cells = <0>;
> >  	};
> >  
> > +	main_timer0: timer@2400000 {
> > +		compatible = "ti,am6-timer";
> > +		reg = <0x00 0x2400000 0x00 0x400>;
> > +		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> > +		clocks = <&k3_clks 23 12>;
> > +		clock-names = "fck";
> > +		ti,timer-pwm;
> > +	};
> 
> Tony,
> Lets hold this back one more window.. ti,am6-timer should come
> in the next rc1, but I still dont see this yet in next-20220706, So, i am
> going to have to skip this window at least.

I'm seeing the clock being too fast although debugfs reports the timer
source clock at 32k. Not quite sure what is wrong, maybe the clock index
should be 1 instead of 12 here. Best to wait with the dts patches until
the clock issue has bee sorted out.

Regards,

Tony

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Re: [PATCH 2/2] arm64: dts: ti: k3-am65: Add general purpose timers for am65

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [220815 16:03]:
> Hi,
> 
> * Nishanth Menon <nm@ti.com> [220706 23:16]:
> > On 13:47-20220407, Tony Lindgren wrote:
> > > diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > > --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > > +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > > @@ -271,6 +271,114 @@ main_spi4: spi@2140000 {
> > >  		#size-cells = <0>;
> > >  	};
> > >  
> > > +	main_timer0: timer@2400000 {
> > > +		compatible = "ti,am6-timer";
> > > +		reg = <0x00 0x2400000 0x00 0x400>;
> > > +		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> > > +		clocks = <&k3_clks 23 12>;
> > > +		clock-names = "fck";
> > > +		ti,timer-pwm;
> > > +	};
> > 
> > Tony,
> > Lets hold this back one more window.. ti,am6-timer should come
> > in the next rc1, but I still dont see this yet in next-20220706, So, i am
> > going to have to skip this window at least.
> 
> I'm seeing the clock being too fast although debugfs reports the timer
> source clock at 32k. Not quite sure what is wrong, maybe the clock index
> should be 1 instead of 12 here. Best to wait with the dts patches until
> the clock issue has bee sorted out.

FYI the issue was caused by a wrong clock configuration. To use the 32k
source as the default clock for main_timer0:

clocks = <&k3_clks 23 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 23 0>;
assigned-clock-parents = <&k3_clks 23 12>;

Regards,

Tony

Re: [PATCH 2/2] arm64: dts: ti: k3-am65: Add general purpose timers for am65

[Tony Lindgren]

* Tony Lindgren <tony@atomide.com> [220815 16:03]:
> Hi,
> 
> * Nishanth Menon <nm@ti.com> [220706 23:16]:
> > On 13:47-20220407, Tony Lindgren wrote:
> > > diff --git a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > > --- a/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > > +++ b/arch/arm64/boot/dts/ti/k3-am65-main.dtsi
> > > @@ -271,6 +271,114 @@ main_spi4: spi@2140000 {
> > >  		#size-cells = <0>;
> > >  	};
> > >  
> > > +	main_timer0: timer@2400000 {
> > > +		compatible = "ti,am6-timer";
> > > +		reg = <0x00 0x2400000 0x00 0x400>;
> > > +		interrupts = <GIC_SPI 224 IRQ_TYPE_LEVEL_HIGH>;
> > > +		clocks = <&k3_clks 23 12>;
> > > +		clock-names = "fck";
> > > +		ti,timer-pwm;
> > > +	};
> > 
> > Tony,
> > Lets hold this back one more window.. ti,am6-timer should come
> > in the next rc1, but I still dont see this yet in next-20220706, So, i am
> > going to have to skip this window at least.
> 
> I'm seeing the clock being too fast although debugfs reports the timer
> source clock at 32k. Not quite sure what is wrong, maybe the clock index
> should be 1 instead of 12 here. Best to wait with the dts patches until
> the clock issue has bee sorted out.

FYI the issue was caused by a wrong clock configuration. To use the 32k
source as the default clock for main_timer0:

clocks = <&k3_clks 23 0>;
clock-names = "fck";
assigned-clocks = <&k3_clks 23 0>;
assigned-clock-parents = <&k3_clks 23 12>;

Regards,

Tony

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