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* [PATCH v18 00/10] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-04-12 10:31 ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: fshao, David Airlie, singo.chang, dri-devel, Fabien Parent,
	linux-stm32, roy-cw.yeh, Project_Global_Chrome_Upstream_Group,
	Yongqiang Niu, Rex-BC Chen, devicetree, nancy.lin,
	linux-mediatek, hsinyi, linux-arm-kernel, jason-jhlin,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>

Change in v18:
- change get driver data by io_start and wrap mmsys driver data into
  mmsys match data structure to support identifying multi mmsys driver
  data with the same compatible name
- change DDP_COMPONENT_DITHER to DDP_CONPONENT_DITHER0

Change in v17:
- change compatible name from 2 vdosys to 1 mmsys
- add get driver data by clk name function to get corresponding
  driver data for mt8195 vdosys0
- add all routing table setting for mt8195 vdosys0
- remove useless mutex define

Change in v16:
- rebase on linu-next tag: 'next-20220303'
- rebase on series: 'Fix MediaTek display dt-bindings issues'

Change in v15:
- remove mt8195-mmsys.h comment for mux settings
- define the mask macro to replace using value as mask
  to fix zero mask problem
- add EOF setting comment for MUTEX sof register

Change in v14:
- rebase on mediatek-drm-next-5.17
- rebase on "Add mmsys and mutex support for MDP" series
- rebase on "media: mediatek: support mdp3 on mt8183 platform" series

Change in v13:
- remove dts patch
- rebase on kernel-5.16-rc1
- rebase on mediatek-drm-next

Change in v12:
- add clock-names property to merge yaml
- using BIT(nr) macro to define the settings of mmsys routing table
- fix clk_get and clk_prepare_enable error handling issue

Change in v11:
- rebase on kernel-5.15-rc1
- change mbox label to gce0 for dts node of vdosys0
- change ovl compatibale to mt8192 to set smi_id_en=true in driver data
- move common module from display folder to common folder,
  such as AAL, COCLOR, CCORR and MUTEX

Change in v10:
- rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
- rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
- fix some typo and "mediatek" start with capital in every dt-bindings
- move mutex yaml from dfisplay folder to soc folder
- separate merge additional propoerties to an individual dt-bindings patch

Change in v9:
- separate power and gce properties of mmsys into another dt-binding patch
- rebase on "Separate aal module" series
- keep mtk_ddp_clk_enable/disable in the same place
- change mtk_dsc_start config register to mtk_drm_ddp_write_mask
- remove the 0 setting of merge fifo config function
- add CCORR driver data for mt8195

Change in v8:
- add DP_INTF0 mux into mmsys routing table
- add DP_INTF0 mutex mod and enum into add/remove comp function
- remove bypass DSC enum in mtk_ddp_comp_init

Change in v7:
- add dt=binding of mmsys and disp path into this series
- separate th modidfication of alphabetic order, remove unused define and
  rename the define of register offset to individual patch
- add comment for MERGE ultra and preultra setting

Change in v6:
- adjust alphabetic order for mediatek-drm
- move the patch that add mt8195 support for mediatek-drm as
  the lastest patch
- add MERGE define for const varriable 

Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h

Change in v4:
- extract dt-binding patches to another patch series
- squash DSC module into mtk_drm_ddp_comp.c
- add coment and simplify MERGE config function

Change in v3:
- change mmsys and display dt-bindings document from txt to yaml
- add MERGE additional description in display dt-bindings document
- fix mboxes-cells number of vdosys0 node in dts
- drop mutex eof convert define
- remove pm_runtime apis in DSC and MERGE
- change DSC and MERGE enum to alphabetic order

Change in v2:
- add DSC yaml file
- add mt8195 drm driver porting parts in to one patch
- remove useless define, variable, structure member and function
- simplify DSC and MERGE file and switch threre order

jason-jh.lin (10):
  dt-bindings: arm: mediatek: mmsys: add power and gce properties
  dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
  soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  soc: mediatek: add mtk-mutex support for mt8195 vdosys0
  drm/mediatek: add DSC support for mediatek-drm
  drm/mediatek: add MERGE support for mediatek-drm
  drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
  soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
  drm/mediatek: add postfix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
  soc: mediatek: remove DDP_DOMPONENT_DITHER enum

 .../bindings/arm/mediatek/mediatek,mmsys.yaml |  32 ++
 drivers/gpu/drm/mediatek/Makefile             |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 246 ++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  65 ++-
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        | 136 ++++++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   7 +
 drivers/soc/mediatek/mt8167-mmsys.h           |   2 +-
 drivers/soc/mediatek/mt8183-mmsys.h           |   2 +-
 drivers/soc/mediatek/mt8186-mmsys.h           |   4 +-
 drivers/soc/mediatek/mt8192-mmsys.h           |   4 +-
 drivers/soc/mediatek/mt8195-mmsys.h           | 370 ++++++++++++++++++
 drivers/soc/mediatek/mt8365-mmsys.h           |   4 +-
 drivers/soc/mediatek/mtk-mmsys.c              | 152 ++++++-
 drivers/soc/mediatek/mtk-mmsys.h              |   6 +
 drivers/soc/mediatek/mtk-mutex.c              |  95 ++++-
 include/linux/soc/mediatek/mtk-mmsys.h        |  13 +-
 19 files changed, 1122 insertions(+), 33 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

-- 
2.18.0


^ permalink raw reply	[flat|nested] 70+ messages in thread
* [PATCH v18 00/10] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-04-12 10:31 ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: David Airlie, singo.chang, dri-devel, Fabien Parent, linux-stm32,
	roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
	Rex-BC Chen, Philipp Zabel, devicetree, Daniel Vetter, CK Hu,
	nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel, jason-jhlin,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>

Change in v18:
- change get driver data by io_start and wrap mmsys driver data into
  mmsys match data structure to support identifying multi mmsys driver
  data with the same compatible name
- change DDP_COMPONENT_DITHER to DDP_CONPONENT_DITHER0

Change in v17:
- change compatible name from 2 vdosys to 1 mmsys
- add get driver data by clk name function to get corresponding
  driver data for mt8195 vdosys0
- add all routing table setting for mt8195 vdosys0
- remove useless mutex define

Change in v16:
- rebase on linu-next tag: 'next-20220303'
- rebase on series: 'Fix MediaTek display dt-bindings issues'

Change in v15:
- remove mt8195-mmsys.h comment for mux settings
- define the mask macro to replace using value as mask
  to fix zero mask problem
- add EOF setting comment for MUTEX sof register

Change in v14:
- rebase on mediatek-drm-next-5.17
- rebase on "Add mmsys and mutex support for MDP" series
- rebase on "media: mediatek: support mdp3 on mt8183 platform" series

Change in v13:
- remove dts patch
- rebase on kernel-5.16-rc1
- rebase on mediatek-drm-next

Change in v12:
- add clock-names property to merge yaml
- using BIT(nr) macro to define the settings of mmsys routing table
- fix clk_get and clk_prepare_enable error handling issue

Change in v11:
- rebase on kernel-5.15-rc1
- change mbox label to gce0 for dts node of vdosys0
- change ovl compatibale to mt8192 to set smi_id_en=true in driver data
- move common module from display folder to common folder,
  such as AAL, COCLOR, CCORR and MUTEX

Change in v10:
- rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
- rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
- fix some typo and "mediatek" start with capital in every dt-bindings
- move mutex yaml from dfisplay folder to soc folder
- separate merge additional propoerties to an individual dt-bindings patch

Change in v9:
- separate power and gce properties of mmsys into another dt-binding patch
- rebase on "Separate aal module" series
- keep mtk_ddp_clk_enable/disable in the same place
- change mtk_dsc_start config register to mtk_drm_ddp_write_mask
- remove the 0 setting of merge fifo config function
- add CCORR driver data for mt8195

Change in v8:
- add DP_INTF0 mux into mmsys routing table
- add DP_INTF0 mutex mod and enum into add/remove comp function
- remove bypass DSC enum in mtk_ddp_comp_init

Change in v7:
- add dt=binding of mmsys and disp path into this series
- separate th modidfication of alphabetic order, remove unused define and
  rename the define of register offset to individual patch
- add comment for MERGE ultra and preultra setting

Change in v6:
- adjust alphabetic order for mediatek-drm
- move the patch that add mt8195 support for mediatek-drm as
  the lastest patch
- add MERGE define for const varriable 

Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h

Change in v4:
- extract dt-binding patches to another patch series
- squash DSC module into mtk_drm_ddp_comp.c
- add coment and simplify MERGE config function

Change in v3:
- change mmsys and display dt-bindings document from txt to yaml
- add MERGE additional description in display dt-bindings document
- fix mboxes-cells number of vdosys0 node in dts
- drop mutex eof convert define
- remove pm_runtime apis in DSC and MERGE
- change DSC and MERGE enum to alphabetic order

Change in v2:
- add DSC yaml file
- add mt8195 drm driver porting parts in to one patch
- remove useless define, variable, structure member and function
- simplify DSC and MERGE file and switch threre order

jason-jh.lin (10):
  dt-bindings: arm: mediatek: mmsys: add power and gce properties
  dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
  soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  soc: mediatek: add mtk-mutex support for mt8195 vdosys0
  drm/mediatek: add DSC support for mediatek-drm
  drm/mediatek: add MERGE support for mediatek-drm
  drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
  soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
  drm/mediatek: add postfix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
  soc: mediatek: remove DDP_DOMPONENT_DITHER enum

 .../bindings/arm/mediatek/mediatek,mmsys.yaml |  32 ++
 drivers/gpu/drm/mediatek/Makefile             |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 246 ++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  65 ++-
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        | 136 ++++++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   7 +
 drivers/soc/mediatek/mt8167-mmsys.h           |   2 +-
 drivers/soc/mediatek/mt8183-mmsys.h           |   2 +-
 drivers/soc/mediatek/mt8186-mmsys.h           |   4 +-
 drivers/soc/mediatek/mt8192-mmsys.h           |   4 +-
 drivers/soc/mediatek/mt8195-mmsys.h           | 370 ++++++++++++++++++
 drivers/soc/mediatek/mt8365-mmsys.h           |   4 +-
 drivers/soc/mediatek/mtk-mmsys.c              | 152 ++++++-
 drivers/soc/mediatek/mtk-mmsys.h              |   6 +
 drivers/soc/mediatek/mtk-mutex.c              |  95 ++++-
 include/linux/soc/mediatek/mtk-mmsys.h        |  13 +-
 19 files changed, 1122 insertions(+), 33 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 70+ messages in thread
* [PATCH v18 00/10] Add Mediatek Soc DRM (vdosys0) support for mt8195
@ 2022-04-12 10:31 ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu, jason-jh . lin, Rex-BC Chen, Yongqiang Niu,
	hsinyi, fshao, moudy.ho, roy-cw.yeh, nancy.lin, singo.chang,
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group,
	jason-jhlin

From: jason-jhlin <jason-jh.lin@mediatek.corp-partner.google.com>

Change in v18:
- change get driver data by io_start and wrap mmsys driver data into
  mmsys match data structure to support identifying multi mmsys driver
  data with the same compatible name
- change DDP_COMPONENT_DITHER to DDP_CONPONENT_DITHER0

Change in v17:
- change compatible name from 2 vdosys to 1 mmsys
- add get driver data by clk name function to get corresponding
  driver data for mt8195 vdosys0
- add all routing table setting for mt8195 vdosys0
- remove useless mutex define

Change in v16:
- rebase on linu-next tag: 'next-20220303'
- rebase on series: 'Fix MediaTek display dt-bindings issues'

Change in v15:
- remove mt8195-mmsys.h comment for mux settings
- define the mask macro to replace using value as mask
  to fix zero mask problem
- add EOF setting comment for MUTEX sof register

Change in v14:
- rebase on mediatek-drm-next-5.17
- rebase on "Add mmsys and mutex support for MDP" series
- rebase on "media: mediatek: support mdp3 on mt8183 platform" series

Change in v13:
- remove dts patch
- rebase on kernel-5.16-rc1
- rebase on mediatek-drm-next

Change in v12:
- add clock-names property to merge yaml
- using BIT(nr) macro to define the settings of mmsys routing table
- fix clk_get and clk_prepare_enable error handling issue

Change in v11:
- rebase on kernel-5.15-rc1
- change mbox label to gce0 for dts node of vdosys0
- change ovl compatibale to mt8192 to set smi_id_en=true in driver data
- move common module from display folder to common folder,
  such as AAL, COCLOR, CCORR and MUTEX

Change in v10:
- rebase on "drm/mediatek: add support for mediatek SOC MT8192" series
- rebase on "soc: mediatek: mmsys: add mt8192 mmsys support" series
- fix some typo and "mediatek" start with capital in every dt-bindings
- move mutex yaml from dfisplay folder to soc folder
- separate merge additional propoerties to an individual dt-bindings patch

Change in v9:
- separate power and gce properties of mmsys into another dt-binding patch
- rebase on "Separate aal module" series
- keep mtk_ddp_clk_enable/disable in the same place
- change mtk_dsc_start config register to mtk_drm_ddp_write_mask
- remove the 0 setting of merge fifo config function
- add CCORR driver data for mt8195

Change in v8:
- add DP_INTF0 mux into mmsys routing table
- add DP_INTF0 mutex mod and enum into add/remove comp function
- remove bypass DSC enum in mtk_ddp_comp_init

Change in v7:
- add dt=binding of mmsys and disp path into this series
- separate th modidfication of alphabetic order, remove unused define and
  rename the define of register offset to individual patch
- add comment for MERGE ultra and preultra setting

Change in v6:
- adjust alphabetic order for mediatek-drm
- move the patch that add mt8195 support for mediatek-drm as
  the lastest patch
- add MERGE define for const varriable 

Change in v5:
- add power-domain property into vdosys0 and vdosys1 dts node.
- add MT8195 prifix and remove unused VDO1 define in mt8195-mmsys.h

Change in v4:
- extract dt-binding patches to another patch series
- squash DSC module into mtk_drm_ddp_comp.c
- add coment and simplify MERGE config function

Change in v3:
- change mmsys and display dt-bindings document from txt to yaml
- add MERGE additional description in display dt-bindings document
- fix mboxes-cells number of vdosys0 node in dts
- drop mutex eof convert define
- remove pm_runtime apis in DSC and MERGE
- change DSC and MERGE enum to alphabetic order

Change in v2:
- add DSC yaml file
- add mt8195 drm driver porting parts in to one patch
- remove useless define, variable, structure member and function
- simplify DSC and MERGE file and switch threre order

jason-jh.lin (10):
  dt-bindings: arm: mediatek: mmsys: add power and gce properties
  dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
  soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  soc: mediatek: add mtk-mutex support for mt8195 vdosys0
  drm/mediatek: add DSC support for mediatek-drm
  drm/mediatek: add MERGE support for mediatek-drm
  drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
  soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
  drm/mediatek: add postfix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
  soc: mediatek: remove DDP_DOMPONENT_DITHER enum

 .../bindings/arm/mediatek/mediatek,mmsys.yaml |  32 ++
 drivers/gpu/drm/mediatek/Makefile             |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h       |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c     | 246 ++++++++++++
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c      |   6 +
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c   |  65 ++-
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h   |   2 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c        | 136 ++++++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h        |   7 +
 drivers/soc/mediatek/mt8167-mmsys.h           |   2 +-
 drivers/soc/mediatek/mt8183-mmsys.h           |   2 +-
 drivers/soc/mediatek/mt8186-mmsys.h           |   4 +-
 drivers/soc/mediatek/mt8192-mmsys.h           |   4 +-
 drivers/soc/mediatek/mt8195-mmsys.h           | 370 ++++++++++++++++++
 drivers/soc/mediatek/mt8365-mmsys.h           |   4 +-
 drivers/soc/mediatek/mtk-mmsys.c              | 152 ++++++-
 drivers/soc/mediatek/mtk-mmsys.h              |   6 +
 drivers/soc/mediatek/mtk-mutex.c              |  95 ++++-
 include/linux/soc/mediatek/mtk-mmsys.h        |  13 +-
 19 files changed, 1122 insertions(+), 33 deletions(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 70+ messages in thread
* [PATCH v18 01/10] dt-bindings: arm: mediatek: mmsys: add power and gce properties
  2022-04-12 10:31 ` jason-jh.lin
  (?)
@ 2022-04-12 10:31   ` jason-jh.lin
  -1 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: fshao, David Airlie, singo.chang, dri-devel, Fabien Parent,
	linux-stm32, roy-cw.yeh, Project_Global_Chrome_Upstream_Group,
	Yongqiang Niu, Rex-BC Chen, devicetree, nancy.lin,
	linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
	linux-kernel, moudy.ho, Maxime Coquelin

Power:
1. Add description for power-domains property.

GCE:
1. Add description for mboxes property.
2. Add description for mediatek,gce-client-reg property.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mmsys.yaml | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index b31d90dc9eb4..6c2c3edcd443 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -41,6 +41,30 @@ properties:
   reg:
     maxItems: 1
 
+  power-domains:
+    description:
+      A phandle and PM domain specifier as defined by bindings
+      of the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  mboxes:
+    description:
+      Using mailbox to communicate with GCE, it should have this
+      property and list of phandle, mailbox specifiers. See
+      Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+
+  mediatek,gce-client-reg:
+    description:
+      The register of client driver can be configured by gce with 4 arguments
+      defined in this property, such as phandle of gce, subsys id,
+      register offset and size.
+      Each subsys id is mapping to a base address of display function blocks
+      register which is defined in the gce header
+      include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
   "#clock-cells":
     const: 1
 
@@ -56,9 +80,16 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/power/mt8173-power.h>
+    #include <dt-bindings/gce/mt8173-gce.h>
+
     mmsys: syscon@14000000 {
         compatible = "mediatek,mt8173-mmsys", "syscon";
         reg = <0x14000000 0x1000>;
+        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
         #clock-cells = <1>;
         #reset-cells = <1>;
+        mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+                 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
     };
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 01/10] dt-bindings: arm: mediatek: mmsys: add power and gce properties
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: David Airlie, singo.chang, dri-devel, Fabien Parent, linux-stm32,
	roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
	Rex-BC Chen, Philipp Zabel, devicetree, Daniel Vetter, CK Hu,
	nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

Power:
1. Add description for power-domains property.

GCE:
1. Add description for mboxes property.
2. Add description for mediatek,gce-client-reg property.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mmsys.yaml | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index b31d90dc9eb4..6c2c3edcd443 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -41,6 +41,30 @@ properties:
   reg:
     maxItems: 1
 
+  power-domains:
+    description:
+      A phandle and PM domain specifier as defined by bindings
+      of the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  mboxes:
+    description:
+      Using mailbox to communicate with GCE, it should have this
+      property and list of phandle, mailbox specifiers. See
+      Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+
+  mediatek,gce-client-reg:
+    description:
+      The register of client driver can be configured by gce with 4 arguments
+      defined in this property, such as phandle of gce, subsys id,
+      register offset and size.
+      Each subsys id is mapping to a base address of display function blocks
+      register which is defined in the gce header
+      include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
   "#clock-cells":
     const: 1
 
@@ -56,9 +80,16 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/power/mt8173-power.h>
+    #include <dt-bindings/gce/mt8173-gce.h>
+
     mmsys: syscon@14000000 {
         compatible = "mediatek,mt8173-mmsys", "syscon";
         reg = <0x14000000 0x1000>;
+        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
         #clock-cells = <1>;
         #reset-cells = <1>;
+        mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+                 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
     };
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 01/10] dt-bindings: arm: mediatek: mmsys: add power and gce properties
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu, jason-jh . lin, Rex-BC Chen, Yongqiang Niu,
	hsinyi, fshao, moudy.ho, roy-cw.yeh, nancy.lin, singo.chang,
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

Power:
1. Add description for power-domains property.

GCE:
1. Add description for mboxes property.
2. Add description for mediatek,gce-client-reg property.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
---
 .../bindings/arm/mediatek/mediatek,mmsys.yaml | 31 +++++++++++++++++++
 1 file changed, 31 insertions(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index b31d90dc9eb4..6c2c3edcd443 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -41,6 +41,30 @@ properties:
   reg:
     maxItems: 1
 
+  power-domains:
+    description:
+      A phandle and PM domain specifier as defined by bindings
+      of the power controller specified by phandle. See
+      Documentation/devicetree/bindings/power/power-domain.yaml for details.
+
+  mboxes:
+    description:
+      Using mailbox to communicate with GCE, it should have this
+      property and list of phandle, mailbox specifiers. See
+      Documentation/devicetree/bindings/mailbox/mtk-gce.txt for details.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+
+  mediatek,gce-client-reg:
+    description:
+      The register of client driver can be configured by gce with 4 arguments
+      defined in this property, such as phandle of gce, subsys id,
+      register offset and size.
+      Each subsys id is mapping to a base address of display function blocks
+      register which is defined in the gce header
+      include/dt-bindings/gce/<chip>-gce.h.
+    $ref: /schemas/types.yaml#/definitions/phandle-array
+    maxItems: 1
+
   "#clock-cells":
     const: 1
 
@@ -56,9 +80,16 @@ additionalProperties: false
 
 examples:
   - |
+    #include <dt-bindings/power/mt8173-power.h>
+    #include <dt-bindings/gce/mt8173-gce.h>
+
     mmsys: syscon@14000000 {
         compatible = "mediatek,mt8173-mmsys", "syscon";
         reg = <0x14000000 0x1000>;
+        power-domains = <&spm MT8173_POWER_DOMAIN_MM>;
         #clock-cells = <1>;
         #reset-cells = <1>;
+        mboxes = <&gce 0 CMDQ_THR_PRIO_HIGHEST>,
+                 <&gce 1 CMDQ_THR_PRIO_HIGHEST>;
+        mediatek,gce-client-reg = <&gce SUBSYS_1400XXXX 0 0x1000>;
     };
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 02/10] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
  2022-04-12 10:31 ` jason-jh.lin
  (?)
@ 2022-04-12 10:31   ` jason-jh.lin
  -1 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: fshao, David Airlie, singo.chang, dri-devel, Fabien Parent,
	linux-stm32, roy-cw.yeh, Project_Global_Chrome_Upstream_Group,
	Yongqiang Niu, Rex-BC Chen, devicetree, nancy.lin,
	linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
	linux-kernel, moudy.ho, Maxime Coquelin

In the SoC before, such as mt8173, it has 2 pipelines binding to one
mmsys with the same clock driver and the same power domain.

In mt8195, there are 4 pipelines binding to 4 different mmsys, such as
vdosys0, vdosys1, vppsys0 and vppsys1.
Each mmsys uses different clock drivers and different power domain.

Since each mmsys has its own mmio base address, they could be identified
by their different address during probe time.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 6c2c3edcd443..6ad023eec193 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -31,6 +31,7 @@ properties:
               - mediatek,mt8183-mmsys
               - mediatek,mt8186-mmsys
               - mediatek,mt8192-mmsys
+              - mediatek,mt8195-mmsys
               - mediatek,mt8365-mmsys
           - const: syscon
       - items:
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 02/10] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: David Airlie, singo.chang, dri-devel, Fabien Parent, linux-stm32,
	roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
	Rex-BC Chen, Philipp Zabel, devicetree, Daniel Vetter, CK Hu,
	nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

In the SoC before, such as mt8173, it has 2 pipelines binding to one
mmsys with the same clock driver and the same power domain.

In mt8195, there are 4 pipelines binding to 4 different mmsys, such as
vdosys0, vdosys1, vppsys0 and vppsys1.
Each mmsys uses different clock drivers and different power domain.

Since each mmsys has its own mmio base address, they could be identified
by their different address during probe time.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 6c2c3edcd443..6ad023eec193 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -31,6 +31,7 @@ properties:
               - mediatek,mt8183-mmsys
               - mediatek,mt8186-mmsys
               - mediatek,mt8192-mmsys
+              - mediatek,mt8195-mmsys
               - mediatek,mt8365-mmsys
           - const: syscon
       - items:
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 02/10] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu, jason-jh . lin, Rex-BC Chen, Yongqiang Niu,
	hsinyi, fshao, moudy.ho, roy-cw.yeh, nancy.lin, singo.chang,
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

In the SoC before, such as mt8173, it has 2 pipelines binding to one
mmsys with the same clock driver and the same power domain.

In mt8195, there are 4 pipelines binding to 4 different mmsys, such as
vdosys0, vdosys1, vppsys0 and vppsys1.
Each mmsys uses different clock drivers and different power domain.

Since each mmsys has its own mmio base address, they could be identified
by their different address during probe time.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: CK Hu <ck.hu@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 .../devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml         | 1 +
 1 file changed, 1 insertion(+)

diff --git a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
index 6c2c3edcd443..6ad023eec193 100644
--- a/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
+++ b/Documentation/devicetree/bindings/arm/mediatek/mediatek,mmsys.yaml
@@ -31,6 +31,7 @@ properties:
               - mediatek,mt8183-mmsys
               - mediatek,mt8186-mmsys
               - mediatek,mt8192-mmsys
+              - mediatek,mt8195-mmsys
               - mediatek,mt8365-mmsys
           - const: syscon
       - items:
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  2022-04-12 10:31 ` jason-jh.lin
  (?)
@ 2022-04-12 10:31   ` jason-jh.lin
  -1 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: fshao, David Airlie, singo.chang, dri-devel, Fabien Parent,
	linux-stm32, roy-cw.yeh, Project_Global_Chrome_Upstream_Group,
	Yongqiang Niu, Rex-BC Chen, devicetree, nancy.lin,
	linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
	linux-kernel, moudy.ho, Maxime Coquelin

1. Add mt8195 mmsys compatible for 2 vdosys.
2. Add io_start into each driver data of mt8195 vdosys.
3. Add get match data function to identify mmsys by io_start.
4. Add mt8195 routing table settings of vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/soc/mediatek/mt8195-mmsys.h    | 370 +++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c       | 152 +++++++++-
 drivers/soc/mediatek/mtk-mmsys.h       |   6 +
 include/linux/soc/mediatek/mtk-mmsys.h |  11 +
 4 files changed, 528 insertions(+), 11 deletions(-)
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..13ab0ab64396
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,370 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN					0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
+
+#define MT8195_VDO0_SEL_IN					0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK			GENMASK(1, 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK			GENMASK(4, 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		(0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK			GENMASK(5, 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		(0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK			GENMASK(8, 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		(1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK			GENMASK(9, 9)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		(0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_MASK			GENMASK(13, 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 << 0)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			(1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_MASK				GENMASK(16, 16)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			(0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			(1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_MASK				GENMASK(17, 17)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			(0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK			GENMASK(20, 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
+#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK			GENMASK(21, 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		(0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		(1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK			GENMASK(22, 22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)
+
+#define MT8195_VDO0_SEL_OUT					0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_MASK			BIT(0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_MASK			GENMASK(2, 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			(1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK			GENMASK(4, 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			(0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			(1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_MASK				GENMASK(10, 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1				(0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			(2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			(3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			(4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK		GENMASK(11, 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			(0 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK			GENMASK(13, 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			(2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK			GENMASK(17, 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			(1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+	{
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
+		MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+	}, {
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
+		MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
+	}, {
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
+		MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
+		MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
+		MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
+		MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+		MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+		MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+		MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+		MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+		MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+		MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+		MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+		MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+		MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+		MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+		MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+		MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
+		MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+		MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+		MT8195_SOUT_DISP_DITHER0_TO_DSI0
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+		MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+		MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DSI1
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
+	}
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 4fc4c2c9ea20..21a787f82e00 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -17,6 +17,7 @@
 #include "mt8183-mmsys.h"
 #include "mt8186-mmsys.h"
 #include "mt8192-mmsys.h"
+#include "mt8195-mmsys.h"
 #include "mt8365-mmsys.h"
 
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt2701_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 	.clk_driver = "clk-mt2712-mm",
 	.routes = mmsys_default_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt2712_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
 	.clk_driver = "clk-mt6779-mm",
 };
 
+static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt6779_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
 	.clk_driver = "clk-mt6797-mm",
 };
 
+static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt6797_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
 	.clk_driver = "clk-mt8167-mm",
 	.routes = mt8167_mmsys_routing_table,
 	.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8167_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.clk_driver = "clk-mt8173-mm",
 	.routes = mmsys_default_routing_table,
@@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
+static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8173_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.clk_driver = "clk-mt8183-mm",
 	.routes = mmsys_mt8183_routing_table,
@@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
+static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8183_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.clk_driver = "clk-mt8186-mm",
 	.routes = mmsys_mt8186_routing_table,
@@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
 };
 
+static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8186_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.clk_driver = "clk-mt8192-mm",
 	.routes = mmsys_mt8192_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8192_mmsys_driver_data,
+	},
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.io_start = 0x1c01a000,
+	.clk_driver = "clk-mt8195-vdo0",
+	.routes = mmsys_mt8195_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+	.io_start = 0x1c100000,
+	.clk_driver = "clk-mt8195-vdo1",
+};
+
+static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
+	.num_drv_data = 2,
+	.drv_data = {
+		&mt8195_vdosys0_driver_data,
+		&mt8195_vdosys1_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
 	.clk_driver = "clk-mt8365-mm",
 	.routes = mt8365_mmsys_routing_table,
 	.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8365_mmsys_driver_data,
+	},
+};
+
 struct mtk_mmsys {
 	void __iomem *regs;
 	const struct mtk_mmsys_driver_data *data;
 	spinlock_t lock; /* protects mmsys_sw_rst_b reg */
 	struct reset_controller_dev rcdev;
+	phys_addr_t io_start;
 };
 
+static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
+					const struct mtk_mmsys_match_data *match)
+{
+	int i;
+
+	for (i = 0; i < match->num_drv_data; i++)
+		if (mmsys->io_start == match->drv_data[i]->io_start)
+			return i;
+
+	return -EINVAL;
+}
+
 void mtk_mmsys_ddp_connect(struct device *dev,
 			   enum mtk_ddp_comp_id cur,
 			   enum mtk_ddp_comp_id next)
@@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct platform_device *clks;
 	struct platform_device *drm;
+	const struct mtk_mmsys_match_data *match_data;
 	struct mtk_mmsys *mmsys;
+	struct resource *res;
 	int ret;
 
 	mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	mmsys->data = of_device_get_match_data(&pdev->dev);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (PTR_ERR(res)) {
+		dev_err(dev, "Couldn't get mmsys resource\n");
+		return -EINVAL;
+	}
+	mmsys->io_start = res->start;
+
+	match_data = of_device_get_match_data(dev);
+	if (match_data->num_drv_data > 1) {
+		/* This SoC has multiple mmsys channels */
+		ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
+		if (ret < 0) {
+			dev_err(dev, "Couldn't get match driver data\n");
+			return ret;
+		}
+		mmsys->data = match_data->drv_data[ret];
+	} else {
+		dev_dbg(dev, "Using single mmsys channel\n");
+		mmsys->data = match_data->drv_data[0];
+	}
+
 	platform_set_drvdata(pdev, mmsys);
 
 	clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
@@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 static const struct of_device_id of_match_mtk_mmsys[] = {
 	{
 		.compatible = "mediatek,mt2701-mmsys",
-		.data = &mt2701_mmsys_driver_data,
+		.data = &mt2701_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt2712-mmsys",
-		.data = &mt2712_mmsys_driver_data,
+		.data = &mt2712_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt6779-mmsys",
-		.data = &mt6779_mmsys_driver_data,
+		.data = &mt6779_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt6797-mmsys",
-		.data = &mt6797_mmsys_driver_data,
+		.data = &mt6797_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8167-mmsys",
-		.data = &mt8167_mmsys_driver_data,
+		.data = &mt8167_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8173-mmsys",
-		.data = &mt8173_mmsys_driver_data,
+		.data = &mt8173_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8183-mmsys",
-		.data = &mt8183_mmsys_driver_data,
+		.data = &mt8183_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8186-mmsys",
-		.data = &mt8186_mmsys_driver_data,
+		.data = &mt8186_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8192-mmsys",
-		.data = &mt8192_mmsys_driver_data,
+		.data = &mt8192_mmsys_match_data,
+	},
+	{
+		.compatible = "mediatek,mt8195-mmsys",
+		.data = &mt8195_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8365-mmsys",
-		.data = &mt8365_mmsys_driver_data,
+		.data = &mt8365_mmsys_match_data,
 	},
 	{ }
 };
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 77f37f8c715b..21cf300ba864 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
 };
 
 struct mtk_mmsys_driver_data {
+	const u32 io_start;
 	const char *clk_driver;
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
 	const u16 sw0_rst_offset;
 };
 
+struct mtk_mmsys_match_data {
+	unsigned short num_drv_data;
+	const struct mtk_mmsys_driver_data *drv_data[];
+};
+
 /*
  * Routes in mt8173, mt2701, mt2712 are different. That means
  * in the same register address, it controls different input/output
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4bba275e235a..cff5c9adbf46 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_COLOR1,
 	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER1,
+	DDP_COMPONENT_DP_INTF0,
+	DDP_COMPONENT_DP_INTF1,
 	DDP_COMPONENT_DPI0,
 	DDP_COMPONENT_DPI1,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_DSC1,
 	DDP_COMPONENT_DSI0,
 	DDP_COMPONENT_DSI1,
 	DDP_COMPONENT_DSI2,
 	DDP_COMPONENT_DSI3,
 	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_MERGE1,
+	DDP_COMPONENT_MERGE2,
+	DDP_COMPONENT_MERGE3,
+	DDP_COMPONENT_MERGE4,
+	DDP_COMPONENT_MERGE5,
 	DDP_COMPONENT_OD0,
 	DDP_COMPONENT_OD1,
 	DDP_COMPONENT_OVL0,
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: David Airlie, singo.chang, dri-devel, Fabien Parent, linux-stm32,
	roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
	Rex-BC Chen, Philipp Zabel, devicetree, Daniel Vetter, CK Hu,
	nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

1. Add mt8195 mmsys compatible for 2 vdosys.
2. Add io_start into each driver data of mt8195 vdosys.
3. Add get match data function to identify mmsys by io_start.
4. Add mt8195 routing table settings of vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/soc/mediatek/mt8195-mmsys.h    | 370 +++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c       | 152 +++++++++-
 drivers/soc/mediatek/mtk-mmsys.h       |   6 +
 include/linux/soc/mediatek/mtk-mmsys.h |  11 +
 4 files changed, 528 insertions(+), 11 deletions(-)
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..13ab0ab64396
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,370 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN					0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
+
+#define MT8195_VDO0_SEL_IN					0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK			GENMASK(1, 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK			GENMASK(4, 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		(0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK			GENMASK(5, 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		(0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK			GENMASK(8, 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		(1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK			GENMASK(9, 9)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		(0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_MASK			GENMASK(13, 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 << 0)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			(1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_MASK				GENMASK(16, 16)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			(0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			(1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_MASK				GENMASK(17, 17)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			(0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK			GENMASK(20, 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
+#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK			GENMASK(21, 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		(0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		(1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK			GENMASK(22, 22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)
+
+#define MT8195_VDO0_SEL_OUT					0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_MASK			BIT(0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_MASK			GENMASK(2, 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			(1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK			GENMASK(4, 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			(0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			(1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_MASK				GENMASK(10, 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1				(0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			(2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			(3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			(4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK		GENMASK(11, 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			(0 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK			GENMASK(13, 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			(2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK			GENMASK(17, 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			(1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+	{
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
+		MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+	}, {
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
+		MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
+	}, {
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
+		MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
+		MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
+		MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
+		MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+		MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+		MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+		MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+		MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+		MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+		MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+		MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+		MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+		MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+		MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+		MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+		MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
+		MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+		MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+		MT8195_SOUT_DISP_DITHER0_TO_DSI0
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+		MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+		MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DSI1
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
+	}
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 4fc4c2c9ea20..21a787f82e00 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -17,6 +17,7 @@
 #include "mt8183-mmsys.h"
 #include "mt8186-mmsys.h"
 #include "mt8192-mmsys.h"
+#include "mt8195-mmsys.h"
 #include "mt8365-mmsys.h"
 
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt2701_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 	.clk_driver = "clk-mt2712-mm",
 	.routes = mmsys_default_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt2712_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
 	.clk_driver = "clk-mt6779-mm",
 };
 
+static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt6779_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
 	.clk_driver = "clk-mt6797-mm",
 };
 
+static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt6797_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
 	.clk_driver = "clk-mt8167-mm",
 	.routes = mt8167_mmsys_routing_table,
 	.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8167_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.clk_driver = "clk-mt8173-mm",
 	.routes = mmsys_default_routing_table,
@@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
+static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8173_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.clk_driver = "clk-mt8183-mm",
 	.routes = mmsys_mt8183_routing_table,
@@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
+static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8183_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.clk_driver = "clk-mt8186-mm",
 	.routes = mmsys_mt8186_routing_table,
@@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
 };
 
+static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8186_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.clk_driver = "clk-mt8192-mm",
 	.routes = mmsys_mt8192_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8192_mmsys_driver_data,
+	},
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.io_start = 0x1c01a000,
+	.clk_driver = "clk-mt8195-vdo0",
+	.routes = mmsys_mt8195_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+	.io_start = 0x1c100000,
+	.clk_driver = "clk-mt8195-vdo1",
+};
+
+static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
+	.num_drv_data = 2,
+	.drv_data = {
+		&mt8195_vdosys0_driver_data,
+		&mt8195_vdosys1_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
 	.clk_driver = "clk-mt8365-mm",
 	.routes = mt8365_mmsys_routing_table,
 	.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8365_mmsys_driver_data,
+	},
+};
+
 struct mtk_mmsys {
 	void __iomem *regs;
 	const struct mtk_mmsys_driver_data *data;
 	spinlock_t lock; /* protects mmsys_sw_rst_b reg */
 	struct reset_controller_dev rcdev;
+	phys_addr_t io_start;
 };
 
+static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
+					const struct mtk_mmsys_match_data *match)
+{
+	int i;
+
+	for (i = 0; i < match->num_drv_data; i++)
+		if (mmsys->io_start == match->drv_data[i]->io_start)
+			return i;
+
+	return -EINVAL;
+}
+
 void mtk_mmsys_ddp_connect(struct device *dev,
 			   enum mtk_ddp_comp_id cur,
 			   enum mtk_ddp_comp_id next)
@@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct platform_device *clks;
 	struct platform_device *drm;
+	const struct mtk_mmsys_match_data *match_data;
 	struct mtk_mmsys *mmsys;
+	struct resource *res;
 	int ret;
 
 	mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	mmsys->data = of_device_get_match_data(&pdev->dev);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (PTR_ERR(res)) {
+		dev_err(dev, "Couldn't get mmsys resource\n");
+		return -EINVAL;
+	}
+	mmsys->io_start = res->start;
+
+	match_data = of_device_get_match_data(dev);
+	if (match_data->num_drv_data > 1) {
+		/* This SoC has multiple mmsys channels */
+		ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
+		if (ret < 0) {
+			dev_err(dev, "Couldn't get match driver data\n");
+			return ret;
+		}
+		mmsys->data = match_data->drv_data[ret];
+	} else {
+		dev_dbg(dev, "Using single mmsys channel\n");
+		mmsys->data = match_data->drv_data[0];
+	}
+
 	platform_set_drvdata(pdev, mmsys);
 
 	clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
@@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 static const struct of_device_id of_match_mtk_mmsys[] = {
 	{
 		.compatible = "mediatek,mt2701-mmsys",
-		.data = &mt2701_mmsys_driver_data,
+		.data = &mt2701_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt2712-mmsys",
-		.data = &mt2712_mmsys_driver_data,
+		.data = &mt2712_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt6779-mmsys",
-		.data = &mt6779_mmsys_driver_data,
+		.data = &mt6779_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt6797-mmsys",
-		.data = &mt6797_mmsys_driver_data,
+		.data = &mt6797_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8167-mmsys",
-		.data = &mt8167_mmsys_driver_data,
+		.data = &mt8167_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8173-mmsys",
-		.data = &mt8173_mmsys_driver_data,
+		.data = &mt8173_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8183-mmsys",
-		.data = &mt8183_mmsys_driver_data,
+		.data = &mt8183_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8186-mmsys",
-		.data = &mt8186_mmsys_driver_data,
+		.data = &mt8186_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8192-mmsys",
-		.data = &mt8192_mmsys_driver_data,
+		.data = &mt8192_mmsys_match_data,
+	},
+	{
+		.compatible = "mediatek,mt8195-mmsys",
+		.data = &mt8195_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8365-mmsys",
-		.data = &mt8365_mmsys_driver_data,
+		.data = &mt8365_mmsys_match_data,
 	},
 	{ }
 };
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 77f37f8c715b..21cf300ba864 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
 };
 
 struct mtk_mmsys_driver_data {
+	const u32 io_start;
 	const char *clk_driver;
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
 	const u16 sw0_rst_offset;
 };
 
+struct mtk_mmsys_match_data {
+	unsigned short num_drv_data;
+	const struct mtk_mmsys_driver_data *drv_data[];
+};
+
 /*
  * Routes in mt8173, mt2701, mt2712 are different. That means
  * in the same register address, it controls different input/output
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4bba275e235a..cff5c9adbf46 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_COLOR1,
 	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER1,
+	DDP_COMPONENT_DP_INTF0,
+	DDP_COMPONENT_DP_INTF1,
 	DDP_COMPONENT_DPI0,
 	DDP_COMPONENT_DPI1,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_DSC1,
 	DDP_COMPONENT_DSI0,
 	DDP_COMPONENT_DSI1,
 	DDP_COMPONENT_DSI2,
 	DDP_COMPONENT_DSI3,
 	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_MERGE1,
+	DDP_COMPONENT_MERGE2,
+	DDP_COMPONENT_MERGE3,
+	DDP_COMPONENT_MERGE4,
+	DDP_COMPONENT_MERGE5,
 	DDP_COMPONENT_OD0,
 	DDP_COMPONENT_OD1,
 	DDP_COMPONENT_OVL0,
-- 
2.18.0


_______________________________________________
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Linux-mediatek@lists.infradead.org
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^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu, jason-jh . lin, Rex-BC Chen, Yongqiang Niu,
	hsinyi, fshao, moudy.ho, roy-cw.yeh, nancy.lin, singo.chang,
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

1. Add mt8195 mmsys compatible for 2 vdosys.
2. Add io_start into each driver data of mt8195 vdosys.
3. Add get match data function to identify mmsys by io_start.
4. Add mt8195 routing table settings of vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/soc/mediatek/mt8195-mmsys.h    | 370 +++++++++++++++++++++++++
 drivers/soc/mediatek/mtk-mmsys.c       | 152 +++++++++-
 drivers/soc/mediatek/mtk-mmsys.h       |   6 +
 include/linux/soc/mediatek/mtk-mmsys.h |  11 +
 4 files changed, 528 insertions(+), 11 deletions(-)
 create mode 100644 drivers/soc/mediatek/mt8195-mmsys.h

diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
new file mode 100644
index 000000000000..13ab0ab64396
--- /dev/null
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -0,0 +1,370 @@
+/* SPDX-License-Identifier: GPL-2.0-only */
+
+#ifndef __SOC_MEDIATEK_MT8195_MMSYS_H
+#define __SOC_MEDIATEK_MT8195_MMSYS_H
+
+#define MT8195_VDO0_OVL_MOUT_EN					0xf14
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0			BIT(0)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0			BIT(1)
+#define MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1			BIT(2)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1			BIT(4)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1			BIT(5)
+#define MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0			BIT(6)
+
+#define MT8195_VDO0_SEL_IN					0xf34
+#define MT8195_SEL_IN_VPP_MERGE_FROM_MASK			GENMASK(1, 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT		(0 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1		(1 << 0)
+#define MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0		(2 << 0)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK			GENMASK(4, 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0		(0 << 4)
+#define MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE		(1 << 4)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK			GENMASK(5, 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1		(0 << 5)
+#define MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE		(1 << 5)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK			GENMASK(8, 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE		(0 << 8)
+#define MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT		(1 << 8)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK			GENMASK(9, 9)
+#define MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT		(0 << 9)
+#define MT8195_SEL_IN_DP_INTF0_FROM_MASK			GENMASK(13, 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT		(0 << 0)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE			(1 << 12)
+#define MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0		(2 << 12)
+#define MT8195_SEL_IN_DSI0_FROM_MASK				GENMASK(16, 16)
+#define MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT			(0 << 16)
+#define MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0			(1 << 16)
+#define MT8195_SEL_IN_DSI1_FROM_MASK				GENMASK(17, 17)
+#define MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT			(0 << 17)
+#define MT8195_SEL_IN_DSI1_FROM_VPP_MERGE			(1 << 17)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_MASK			GENMASK(20, 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1			(0 << 20)
+#define MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE			(1 << 20)
+#define MT8195_SEL_IN_DSC_WRAP1_FROM_MASK			GENMASK(21, 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN		(0 << 21)
+#define MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1		(1 << 21)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_MASK			GENMASK(22, 22)
+#define MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0			(0 << 22)
+
+#define MT8195_VDO0_SEL_OUT					0xf38
+#define MT8195_SOUT_DISP_DITHER0_TO_MASK			BIT(0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN		(0 << 0)
+#define MT8195_SOUT_DISP_DITHER0_TO_DSI0			(1 << 0)
+#define MT8195_SOUT_DISP_DITHER1_TO_MASK			GENMASK(2, 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN		(0 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE			(1 << 1)
+#define MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT		(2 << 1)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK			GENMASK(4, 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE			(0 << 4)
+#define MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0			(1 << 4)
+#define MT8195_SOUT_VPP_MERGE_TO_MASK				GENMASK(10, 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSI1				(0 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DP_INTF0			(1 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0			(2 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1			(3 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN			(4 << 8)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK		GENMASK(11, 11)
+#define MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN			(0 << 11)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK			GENMASK(13, 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0			(0 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0		(1 << 12)
+#define MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE			(2 << 12)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK			GENMASK(17, 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1			(0 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0			(1 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0		(2 << 16)
+#define MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE			(3 << 16)
+
+static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
+	{
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_RDMA0,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0,
+		MT8195_MOUT_DISP_OVL0_TO_DISP_RDMA0
+	}, {
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0,
+		MT8195_MOUT_DISP_OVL0_TO_DISP_WDMA0
+	}, {
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_OVL1,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1,
+		MT8195_MOUT_DISP_OVL0_TO_DISP_OVL1
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_RDMA1,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1,
+		MT8195_MOUT_DISP_OVL1_TO_DISP_RDMA1
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1,
+		MT8195_MOUT_DISP_OVL1_TO_DISP_WDMA1
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_OVL0,
+		MT8195_VDO0_OVL_MOUT_EN, MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0,
+		MT8195_MOUT_DISP_OVL1_TO_DISP_OVL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+		MT8195_SEL_IN_VPP_MERGE_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+		MT8195_SEL_IN_VPP_MERGE_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
+		MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_IN_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_IN_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_IN_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINA_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINA_VIRTUAL0_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_SINB_VIRTUAL0_FROM_MASK,
+		MT8195_SEL_IN_SINB_VIRTUAL0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+		MT8195_SEL_IN_DP_INTF0_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+		MT8195_SEL_IN_DP_INTF0_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DP_INTF0_FROM_MASK,
+		MT8195_SEL_IN_DP_INTF0_FROM_VDO1_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+		MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
+		MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+		MT8195_SEL_IN_DSI1_FROM_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI1_FROM_MASK,
+		MT8195_SEL_IN_DSI1_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_OVL1, DDP_COMPONENT_WDMA1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+		MT8195_SEL_IN_DISP_WDMA1_FROM_DISP_OVL1
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA1_FROM_MASK,
+		MT8195_SEL_IN_DISP_WDMA1_FROM_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP1_FROM_MASK,
+		MT8195_SEL_IN_DSC_WRAP1_OUT_FROM_DISP_DITHER1
+	}, {
+		DDP_COMPONENT_OVL0, DDP_COMPONENT_WDMA0,
+		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
+		MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+		MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
+	}, {
+		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
+		MT8195_SOUT_DISP_DITHER0_TO_DSI0
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSC1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_DITHER1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER1_TO_MASK,
+		MT8195_SOUT_DISP_DITHER1_TO_DSC_WRAP1_OUT
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+		MT8195_SOUT_VDO1_VIRTUAL0_TO_VPP_MERGE
+	}, {
+		DDP_COMPONENT_MERGE5, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VDO1_VIRTUAL0_TO_MASK,
+		MT8195_SOUT_VDO1_VIRTUAL0_TO_DP_INTF0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DSI1
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DP_INTF0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_WDMA1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DISP_WDMA1
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP0_IN
+	}, {
+		DDP_COMPONENT_MERGE0, DDP_COMPONENT_DSC1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN_MASK,
+		MT8195_SOUT_VPP_MERGE_TO_DSC_WRAP1_IN
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DSI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_DSI0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_SINB_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC0, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP0_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP0_OUT_TO_VPP_MERGE
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DSI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_DSI1
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_DP_INTF0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DP_INTF1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_DPI1,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_SINA_VIRTUAL0
+	}, {
+		DDP_COMPONENT_DSC1, DDP_COMPONENT_MERGE0,
+		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DSC_WRAP1_OUT_TO_MASK,
+		MT8195_SOUT_DSC_WRAP1_OUT_TO_VPP_MERGE
+	}
+};
+
+#endif /* __SOC_MEDIATEK_MT8195_MMSYS_H */
diff --git a/drivers/soc/mediatek/mtk-mmsys.c b/drivers/soc/mediatek/mtk-mmsys.c
index 4fc4c2c9ea20..21a787f82e00 100644
--- a/drivers/soc/mediatek/mtk-mmsys.c
+++ b/drivers/soc/mediatek/mtk-mmsys.c
@@ -17,6 +17,7 @@
 #include "mt8183-mmsys.h"
 #include "mt8186-mmsys.h"
 #include "mt8192-mmsys.h"
+#include "mt8195-mmsys.h"
 #include "mt8365-mmsys.h"
 
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
@@ -25,26 +26,61 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt2701_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 	.clk_driver = "clk-mt2712-mm",
 	.routes = mmsys_default_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_default_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt2712_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt6779_mmsys_driver_data = {
 	.clk_driver = "clk-mt6779-mm",
 };
 
+static const struct mtk_mmsys_match_data mt6779_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt6779_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt6797_mmsys_driver_data = {
 	.clk_driver = "clk-mt6797-mm",
 };
 
+static const struct mtk_mmsys_match_data mt6797_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt6797_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
 	.clk_driver = "clk-mt8167-mm",
 	.routes = mt8167_mmsys_routing_table,
 	.num_routes = ARRAY_SIZE(mt8167_mmsys_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8167_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.clk_driver = "clk-mt8173-mm",
 	.routes = mmsys_default_routing_table,
@@ -52,6 +88,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
+static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8173_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.clk_driver = "clk-mt8183-mm",
 	.routes = mmsys_mt8183_routing_table,
@@ -59,6 +102,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.sw0_rst_offset = MT8183_MMSYS_SW0_RST_B,
 };
 
+static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8183_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.clk_driver = "clk-mt8186-mm",
 	.routes = mmsys_mt8186_routing_table,
@@ -66,25 +116,79 @@ static const struct mtk_mmsys_driver_data mt8186_mmsys_driver_data = {
 	.sw0_rst_offset = MT8186_MMSYS_SW0_RST_B,
 };
 
+static const struct mtk_mmsys_match_data mt8186_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8186_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.clk_driver = "clk-mt8192-mm",
 	.routes = mmsys_mt8192_routing_table,
 	.num_routes = ARRAY_SIZE(mmsys_mt8192_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8192_mmsys_driver_data,
+	},
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.io_start = 0x1c01a000,
+	.clk_driver = "clk-mt8195-vdo0",
+	.routes = mmsys_mt8195_routing_table,
+	.num_routes = ARRAY_SIZE(mmsys_mt8195_routing_table),
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+	.io_start = 0x1c100000,
+	.clk_driver = "clk-mt8195-vdo1",
+};
+
+static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
+	.num_drv_data = 2,
+	.drv_data = {
+		&mt8195_vdosys0_driver_data,
+		&mt8195_vdosys1_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8365_mmsys_driver_data = {
 	.clk_driver = "clk-mt8365-mm",
 	.routes = mt8365_mmsys_routing_table,
 	.num_routes = ARRAY_SIZE(mt8365_mmsys_routing_table),
 };
 
+static const struct mtk_mmsys_match_data mt8365_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8365_mmsys_driver_data,
+	},
+};
+
 struct mtk_mmsys {
 	void __iomem *regs;
 	const struct mtk_mmsys_driver_data *data;
 	spinlock_t lock; /* protects mmsys_sw_rst_b reg */
 	struct reset_controller_dev rcdev;
+	phys_addr_t io_start;
 };
 
+static int mtk_mmsys_find_match_drvdata(struct mtk_mmsys *mmsys,
+					const struct mtk_mmsys_match_data *match)
+{
+	int i;
+
+	for (i = 0; i < match->num_drv_data; i++)
+		if (mmsys->io_start == match->drv_data[i]->io_start)
+			return i;
+
+	return -EINVAL;
+}
+
 void mtk_mmsys_ddp_connect(struct device *dev,
 			   enum mtk_ddp_comp_id cur,
 			   enum mtk_ddp_comp_id next)
@@ -179,7 +283,9 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 	struct device *dev = &pdev->dev;
 	struct platform_device *clks;
 	struct platform_device *drm;
+	const struct mtk_mmsys_match_data *match_data;
 	struct mtk_mmsys *mmsys;
+	struct resource *res;
 	int ret;
 
 	mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
@@ -205,7 +311,27 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 		return ret;
 	}
 
-	mmsys->data = of_device_get_match_data(&pdev->dev);
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (PTR_ERR(res)) {
+		dev_err(dev, "Couldn't get mmsys resource\n");
+		return -EINVAL;
+	}
+	mmsys->io_start = res->start;
+
+	match_data = of_device_get_match_data(dev);
+	if (match_data->num_drv_data > 1) {
+		/* This SoC has multiple mmsys channels */
+		ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
+		if (ret < 0) {
+			dev_err(dev, "Couldn't get match driver data\n");
+			return ret;
+		}
+		mmsys->data = match_data->drv_data[ret];
+	} else {
+		dev_dbg(dev, "Using single mmsys channel\n");
+		mmsys->data = match_data->drv_data[0];
+	}
+
 	platform_set_drvdata(pdev, mmsys);
 
 	clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
@@ -226,43 +352,47 @@ static int mtk_mmsys_probe(struct platform_device *pdev)
 static const struct of_device_id of_match_mtk_mmsys[] = {
 	{
 		.compatible = "mediatek,mt2701-mmsys",
-		.data = &mt2701_mmsys_driver_data,
+		.data = &mt2701_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt2712-mmsys",
-		.data = &mt2712_mmsys_driver_data,
+		.data = &mt2712_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt6779-mmsys",
-		.data = &mt6779_mmsys_driver_data,
+		.data = &mt6779_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt6797-mmsys",
-		.data = &mt6797_mmsys_driver_data,
+		.data = &mt6797_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8167-mmsys",
-		.data = &mt8167_mmsys_driver_data,
+		.data = &mt8167_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8173-mmsys",
-		.data = &mt8173_mmsys_driver_data,
+		.data = &mt8173_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8183-mmsys",
-		.data = &mt8183_mmsys_driver_data,
+		.data = &mt8183_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8186-mmsys",
-		.data = &mt8186_mmsys_driver_data,
+		.data = &mt8186_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8192-mmsys",
-		.data = &mt8192_mmsys_driver_data,
+		.data = &mt8192_mmsys_match_data,
+	},
+	{
+		.compatible = "mediatek,mt8195-mmsys",
+		.data = &mt8195_mmsys_match_data,
 	},
 	{
 		.compatible = "mediatek,mt8365-mmsys",
-		.data = &mt8365_mmsys_driver_data,
+		.data = &mt8365_mmsys_match_data,
 	},
 	{ }
 };
diff --git a/drivers/soc/mediatek/mtk-mmsys.h b/drivers/soc/mediatek/mtk-mmsys.h
index 77f37f8c715b..21cf300ba864 100644
--- a/drivers/soc/mediatek/mtk-mmsys.h
+++ b/drivers/soc/mediatek/mtk-mmsys.h
@@ -87,12 +87,18 @@ struct mtk_mmsys_routes {
 };
 
 struct mtk_mmsys_driver_data {
+	const u32 io_start;
 	const char *clk_driver;
 	const struct mtk_mmsys_routes *routes;
 	const unsigned int num_routes;
 	const u16 sw0_rst_offset;
 };
 
+struct mtk_mmsys_match_data {
+	unsigned short num_drv_data;
+	const struct mtk_mmsys_driver_data *drv_data[];
+};
+
 /*
  * Routes in mt8173, mt2701, mt2712 are different. That means
  * in the same register address, it controls different input/output
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 4bba275e235a..cff5c9adbf46 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -17,13 +17,24 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_COLOR1,
 	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER1,
+	DDP_COMPONENT_DP_INTF0,
+	DDP_COMPONENT_DP_INTF1,
 	DDP_COMPONENT_DPI0,
 	DDP_COMPONENT_DPI1,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_DSC1,
 	DDP_COMPONENT_DSI0,
 	DDP_COMPONENT_DSI1,
 	DDP_COMPONENT_DSI2,
 	DDP_COMPONENT_DSI3,
 	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_MERGE1,
+	DDP_COMPONENT_MERGE2,
+	DDP_COMPONENT_MERGE3,
+	DDP_COMPONENT_MERGE4,
+	DDP_COMPONENT_MERGE5,
 	DDP_COMPONENT_OD0,
 	DDP_COMPONENT_OD1,
 	DDP_COMPONENT_OVL0,
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 04/10] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
  2022-04-12 10:31 ` jason-jh.lin
  (?)
@ 2022-04-12 10:31   ` jason-jh.lin
  -1 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: fshao, David Airlie, singo.chang, dri-devel, Fabien Parent,
	linux-stm32, roy-cw.yeh, Project_Global_Chrome_Upstream_Group,
	Yongqiang Niu, Rex-BC Chen, devicetree, nancy.lin,
	linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
	linux-kernel, moudy.ho, Maxime Coquelin

Add mtk-mutex support for mt8195 vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Fei Shao <fshao@chromium.org>
---
 drivers/soc/mediatek/mtk-mutex.c | 87 ++++++++++++++++++++++++++++++--
 1 file changed, 84 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index aaf8fc1abb43..729ee88035ed 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
 #define MT8183_MUTEX0_MOD0			0x30
 #define MT8183_MUTEX0_SOF0			0x2c
 
+#define MT8195_DISP_MUTEX0_MOD0			0x30
+#define MT8195_DISP_MUTEX0_SOF			0x2c
+
 #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
@@ -96,6 +99,20 @@
 #define MT8173_MUTEX_MOD_DISP_PWM1		24
 #define MT8173_MUTEX_MOD_DISP_OD		25
 
+#define MT8195_MUTEX_MOD_DISP_OVL0		0
+#define MT8195_MUTEX_MOD_DISP_WDMA0		1
+#define MT8195_MUTEX_MOD_DISP_RDMA0		2
+#define MT8195_MUTEX_MOD_DISP_COLOR0		3
+#define MT8195_MUTEX_MOD_DISP_CCORR0		4
+#define MT8195_MUTEX_MOD_DISP_AAL0		5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
+#define MT8195_MUTEX_MOD_DISP_DITHER0		7
+#define MT8195_MUTEX_MOD_DISP_DSI0		8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
+#define MT8195_MUTEX_MOD_DISP_PWM0		27
+
 #define MT2712_MUTEX_MOD_DISP_PWM2		10
 #define MT2712_MUTEX_MOD_DISP_OVL0		11
 #define MT2712_MUTEX_MOD_DISP_OVL1		12
@@ -132,9 +149,21 @@
 #define MT8167_MUTEX_SOF_DPI1			3
 #define MT8183_MUTEX_SOF_DSI0			1
 #define MT8183_MUTEX_SOF_DPI0			2
+#define MT8195_MUTEX_SOF_DSI0			1
+#define MT8195_MUTEX_SOF_DSI1			2
+#define MT8195_MUTEX_SOF_DP_INTF0		3
+#define MT8195_MUTEX_SOF_DP_INTF1		4
+#define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */
 
 #define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
 #define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1		(MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0			(MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1			(MT8195_MUTEX_SOF_DPI1 << 7)
 
 struct mtk_mutex {
 	int id;
@@ -149,6 +178,9 @@ enum mtk_mutex_sof_id {
 	MUTEX_SOF_DPI1,
 	MUTEX_SOF_DSI2,
 	MUTEX_SOF_DSI3,
+	MUTEX_SOF_DP_INTF0,
+	MUTEX_SOF_DP_INTF1,
+	DDP_MUTEX_SOF_MAX,
 };
 
 struct mtk_mutex_data {
@@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
 };
 
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+	[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+	[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+	[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+	[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -280,7 +328,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 	[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
 };
 
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -288,7 +336,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 };
 
 /* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
@@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 	[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
 };
 
+/*
+ * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
+ * select the EOF source and configure the EOF plus timing from the
+ * module that provides the timing signal.
+ * So that MUTEX can not only send a STREAM_DONE event to GCE
+ * but also detect the error at end of frame(EAEOF) when EOF signal
+ * arrives.
+ */
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+	[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+	[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+	[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+	[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+	[MUTEX_SOF_DP_INTF0] =
+		MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+	[MUTEX_SOF_DP_INTF1] =
+		MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
 	.mutex_mod = mt2701_mutex_mod,
 	.mutex_sof = mt2712_mutex_sof,
@@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
 	.mutex_sof_reg = MT8183_MUTEX0_SOF0,
 };
 
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+	.mutex_mod = mt8195_mutex_mod,
+	.mutex_sof = mt8195_mutex_sof,
+	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
 struct mtk_mutex *mtk_mutex_get(struct device *dev)
 {
 	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
 	case DDP_COMPONENT_DPI1:
 		sof_id = MUTEX_SOF_DPI1;
 		break;
+	case DDP_COMPONENT_DP_INTF0:
+		sof_id = MUTEX_SOF_DP_INTF0;
+		break;
 	default:
 		if (mtx->data->mutex_mod[id] < 32) {
 			offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
 	case DDP_COMPONENT_DSI3:
 	case DDP_COMPONENT_DPI0:
 	case DDP_COMPONENT_DPI1:
+	case DDP_COMPONENT_DP_INTF0:
 		writel_relaxed(MUTEX_SOF_SINGLE_MODE,
 			       mtx->regs +
 			       DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
@@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
 	  .data = &mt8186_mutex_driver_data},
 	{ .compatible = "mediatek,mt8192-disp-mutex",
 	  .data = &mt8192_mutex_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = &mt8195_mutex_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 04/10] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: David Airlie, singo.chang, dri-devel, Fabien Parent, linux-stm32,
	roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
	Rex-BC Chen, Philipp Zabel, devicetree, Daniel Vetter, CK Hu,
	nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

Add mtk-mutex support for mt8195 vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Fei Shao <fshao@chromium.org>
---
 drivers/soc/mediatek/mtk-mutex.c | 87 ++++++++++++++++++++++++++++++--
 1 file changed, 84 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index aaf8fc1abb43..729ee88035ed 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
 #define MT8183_MUTEX0_MOD0			0x30
 #define MT8183_MUTEX0_SOF0			0x2c
 
+#define MT8195_DISP_MUTEX0_MOD0			0x30
+#define MT8195_DISP_MUTEX0_SOF			0x2c
+
 #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
@@ -96,6 +99,20 @@
 #define MT8173_MUTEX_MOD_DISP_PWM1		24
 #define MT8173_MUTEX_MOD_DISP_OD		25
 
+#define MT8195_MUTEX_MOD_DISP_OVL0		0
+#define MT8195_MUTEX_MOD_DISP_WDMA0		1
+#define MT8195_MUTEX_MOD_DISP_RDMA0		2
+#define MT8195_MUTEX_MOD_DISP_COLOR0		3
+#define MT8195_MUTEX_MOD_DISP_CCORR0		4
+#define MT8195_MUTEX_MOD_DISP_AAL0		5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
+#define MT8195_MUTEX_MOD_DISP_DITHER0		7
+#define MT8195_MUTEX_MOD_DISP_DSI0		8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
+#define MT8195_MUTEX_MOD_DISP_PWM0		27
+
 #define MT2712_MUTEX_MOD_DISP_PWM2		10
 #define MT2712_MUTEX_MOD_DISP_OVL0		11
 #define MT2712_MUTEX_MOD_DISP_OVL1		12
@@ -132,9 +149,21 @@
 #define MT8167_MUTEX_SOF_DPI1			3
 #define MT8183_MUTEX_SOF_DSI0			1
 #define MT8183_MUTEX_SOF_DPI0			2
+#define MT8195_MUTEX_SOF_DSI0			1
+#define MT8195_MUTEX_SOF_DSI1			2
+#define MT8195_MUTEX_SOF_DP_INTF0		3
+#define MT8195_MUTEX_SOF_DP_INTF1		4
+#define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */
 
 #define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
 #define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1		(MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0			(MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1			(MT8195_MUTEX_SOF_DPI1 << 7)
 
 struct mtk_mutex {
 	int id;
@@ -149,6 +178,9 @@ enum mtk_mutex_sof_id {
 	MUTEX_SOF_DPI1,
 	MUTEX_SOF_DSI2,
 	MUTEX_SOF_DSI3,
+	MUTEX_SOF_DP_INTF0,
+	MUTEX_SOF_DP_INTF1,
+	DDP_MUTEX_SOF_MAX,
 };
 
 struct mtk_mutex_data {
@@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
 };
 
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+	[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+	[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+	[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+	[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -280,7 +328,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 	[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
 };
 
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -288,7 +336,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 };
 
 /* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
@@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 	[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
 };
 
+/*
+ * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
+ * select the EOF source and configure the EOF plus timing from the
+ * module that provides the timing signal.
+ * So that MUTEX can not only send a STREAM_DONE event to GCE
+ * but also detect the error at end of frame(EAEOF) when EOF signal
+ * arrives.
+ */
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+	[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+	[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+	[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+	[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+	[MUTEX_SOF_DP_INTF0] =
+		MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+	[MUTEX_SOF_DP_INTF1] =
+		MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
 	.mutex_mod = mt2701_mutex_mod,
 	.mutex_sof = mt2712_mutex_sof,
@@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
 	.mutex_sof_reg = MT8183_MUTEX0_SOF0,
 };
 
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+	.mutex_mod = mt8195_mutex_mod,
+	.mutex_sof = mt8195_mutex_sof,
+	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
 struct mtk_mutex *mtk_mutex_get(struct device *dev)
 {
 	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
 	case DDP_COMPONENT_DPI1:
 		sof_id = MUTEX_SOF_DPI1;
 		break;
+	case DDP_COMPONENT_DP_INTF0:
+		sof_id = MUTEX_SOF_DP_INTF0;
+		break;
 	default:
 		if (mtx->data->mutex_mod[id] < 32) {
 			offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
 	case DDP_COMPONENT_DSI3:
 	case DDP_COMPONENT_DPI0:
 	case DDP_COMPONENT_DPI1:
+	case DDP_COMPONENT_DP_INTF0:
 		writel_relaxed(MUTEX_SOF_SINGLE_MODE,
 			       mtx->regs +
 			       DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
@@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
 	  .data = &mt8186_mutex_driver_data},
 	{ .compatible = "mediatek,mt8192-disp-mutex",
 	  .data = &mt8192_mutex_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = &mt8195_mutex_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 04/10] soc: mediatek: add mtk-mutex support for mt8195 vdosys0
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu, jason-jh . lin, Rex-BC Chen, Yongqiang Niu,
	hsinyi, fshao, moudy.ho, roy-cw.yeh, nancy.lin, singo.chang,
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

Add mtk-mutex support for mt8195 vdosys0.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Tested-by: Fei Shao <fshao@chromium.org>
---
 drivers/soc/mediatek/mtk-mutex.c | 87 ++++++++++++++++++++++++++++++--
 1 file changed, 84 insertions(+), 3 deletions(-)

diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index aaf8fc1abb43..729ee88035ed 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -17,6 +17,9 @@
 #define MT8183_MUTEX0_MOD0			0x30
 #define MT8183_MUTEX0_SOF0			0x2c
 
+#define MT8195_DISP_MUTEX0_MOD0			0x30
+#define MT8195_DISP_MUTEX0_SOF			0x2c
+
 #define DISP_REG_MUTEX_EN(n)			(0x20 + 0x20 * (n))
 #define DISP_REG_MUTEX(n)			(0x24 + 0x20 * (n))
 #define DISP_REG_MUTEX_RST(n)			(0x28 + 0x20 * (n))
@@ -96,6 +99,20 @@
 #define MT8173_MUTEX_MOD_DISP_PWM1		24
 #define MT8173_MUTEX_MOD_DISP_OD		25
 
+#define MT8195_MUTEX_MOD_DISP_OVL0		0
+#define MT8195_MUTEX_MOD_DISP_WDMA0		1
+#define MT8195_MUTEX_MOD_DISP_RDMA0		2
+#define MT8195_MUTEX_MOD_DISP_COLOR0		3
+#define MT8195_MUTEX_MOD_DISP_CCORR0		4
+#define MT8195_MUTEX_MOD_DISP_AAL0		5
+#define MT8195_MUTEX_MOD_DISP_GAMMA0		6
+#define MT8195_MUTEX_MOD_DISP_DITHER0		7
+#define MT8195_MUTEX_MOD_DISP_DSI0		8
+#define MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0	9
+#define MT8195_MUTEX_MOD_DISP_VPP_MERGE		20
+#define MT8195_MUTEX_MOD_DISP_DP_INTF0		21
+#define MT8195_MUTEX_MOD_DISP_PWM0		27
+
 #define MT2712_MUTEX_MOD_DISP_PWM2		10
 #define MT2712_MUTEX_MOD_DISP_OVL0		11
 #define MT2712_MUTEX_MOD_DISP_OVL1		12
@@ -132,9 +149,21 @@
 #define MT8167_MUTEX_SOF_DPI1			3
 #define MT8183_MUTEX_SOF_DSI0			1
 #define MT8183_MUTEX_SOF_DPI0			2
+#define MT8195_MUTEX_SOF_DSI0			1
+#define MT8195_MUTEX_SOF_DSI1			2
+#define MT8195_MUTEX_SOF_DP_INTF0		3
+#define MT8195_MUTEX_SOF_DP_INTF1		4
+#define MT8195_MUTEX_SOF_DPI0			6 /* for HDMI_TX */
+#define MT8195_MUTEX_SOF_DPI1			5 /* for digital video out */
 
 #define MT8183_MUTEX_EOF_DSI0			(MT8183_MUTEX_SOF_DSI0 << 6)
 #define MT8183_MUTEX_EOF_DPI0			(MT8183_MUTEX_SOF_DPI0 << 6)
+#define MT8195_MUTEX_EOF_DSI0			(MT8195_MUTEX_SOF_DSI0 << 7)
+#define MT8195_MUTEX_EOF_DSI1			(MT8195_MUTEX_SOF_DSI1 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF0		(MT8195_MUTEX_SOF_DP_INTF0 << 7)
+#define MT8195_MUTEX_EOF_DP_INTF1		(MT8195_MUTEX_SOF_DP_INTF1 << 7)
+#define MT8195_MUTEX_EOF_DPI0			(MT8195_MUTEX_SOF_DPI0 << 7)
+#define MT8195_MUTEX_EOF_DPI1			(MT8195_MUTEX_SOF_DPI1 << 7)
 
 struct mtk_mutex {
 	int id;
@@ -149,6 +178,9 @@ enum mtk_mutex_sof_id {
 	MUTEX_SOF_DPI1,
 	MUTEX_SOF_DSI2,
 	MUTEX_SOF_DSI3,
+	MUTEX_SOF_DP_INTF0,
+	MUTEX_SOF_DP_INTF1,
+	DDP_MUTEX_SOF_MAX,
 };
 
 struct mtk_mutex_data {
@@ -270,7 +302,23 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_RDMA4] = MT8192_MUTEX_MOD_DISP_RDMA4,
 };
 
-static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
+	[DDP_COMPONENT_OVL0] = MT8195_MUTEX_MOD_DISP_OVL0,
+	[DDP_COMPONENT_WDMA0] = MT8195_MUTEX_MOD_DISP_WDMA0,
+	[DDP_COMPONENT_RDMA0] = MT8195_MUTEX_MOD_DISP_RDMA0,
+	[DDP_COMPONENT_COLOR0] = MT8195_MUTEX_MOD_DISP_COLOR0,
+	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
+	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
+	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
+	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
+	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
+	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
+	[DDP_COMPONENT_PWM0] = MT8195_MUTEX_MOD_DISP_PWM0,
+	[DDP_COMPONENT_DP_INTF0] = MT8195_MUTEX_MOD_DISP_DP_INTF0,
+};
+
+static const unsigned int mt2712_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DSI1] = MUTEX_SOF_DSI1,
@@ -280,7 +328,7 @@ static const unsigned int mt2712_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 	[MUTEX_SOF_DSI3] = MUTEX_SOF_DSI3,
 };
 
-static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8167_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8167_MUTEX_SOF_DPI0,
@@ -288,7 +336,7 @@ static const unsigned int mt8167_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 };
 
 /* Add EOF setting so overlay hardware can receive frame done irq */
-static const unsigned int mt8183_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
+static const unsigned int mt8183_mutex_sof[DDP_MUTEX_SOF_MAX] = {
 	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
 	[MUTEX_SOF_DSI0] = MUTEX_SOF_DSI0 | MT8183_MUTEX_EOF_DSI0,
 	[MUTEX_SOF_DPI0] = MT8183_MUTEX_SOF_DPI0 | MT8183_MUTEX_EOF_DPI0,
@@ -300,6 +348,26 @@ static const unsigned int mt8186_mutex_sof[MUTEX_SOF_DSI3 + 1] = {
 	[MUTEX_SOF_DPI0] = MT8186_MUTEX_SOF_DPI0 | MT8186_MUTEX_EOF_DPI0,
 };
 
+/*
+ * To support refresh mode(video mode), DISP_REG_MUTEX_SOF should
+ * select the EOF source and configure the EOF plus timing from the
+ * module that provides the timing signal.
+ * So that MUTEX can not only send a STREAM_DONE event to GCE
+ * but also detect the error at end of frame(EAEOF) when EOF signal
+ * arrives.
+ */
+static const unsigned int mt8195_mutex_sof[DDP_MUTEX_SOF_MAX] = {
+	[MUTEX_SOF_SINGLE_MODE] = MUTEX_SOF_SINGLE_MODE,
+	[MUTEX_SOF_DSI0] = MT8195_MUTEX_SOF_DSI0 | MT8195_MUTEX_EOF_DSI0,
+	[MUTEX_SOF_DSI1] = MT8195_MUTEX_SOF_DSI1 | MT8195_MUTEX_EOF_DSI1,
+	[MUTEX_SOF_DPI0] = MT8195_MUTEX_SOF_DPI0 | MT8195_MUTEX_EOF_DPI0,
+	[MUTEX_SOF_DPI1] = MT8195_MUTEX_SOF_DPI1 | MT8195_MUTEX_EOF_DPI1,
+	[MUTEX_SOF_DP_INTF0] =
+		MT8195_MUTEX_SOF_DP_INTF0 | MT8195_MUTEX_EOF_DP_INTF0,
+	[MUTEX_SOF_DP_INTF1] =
+		MT8195_MUTEX_SOF_DP_INTF1 | MT8195_MUTEX_EOF_DP_INTF1,
+};
+
 static const struct mtk_mutex_data mt2701_mutex_driver_data = {
 	.mutex_mod = mt2701_mutex_mod,
 	.mutex_sof = mt2712_mutex_sof,
@@ -351,6 +419,13 @@ static const struct mtk_mutex_data mt8192_mutex_driver_data = {
 	.mutex_sof_reg = MT8183_MUTEX0_SOF0,
 };
 
+static const struct mtk_mutex_data mt8195_mutex_driver_data = {
+	.mutex_mod = mt8195_mutex_mod,
+	.mutex_sof = mt8195_mutex_sof,
+	.mutex_mod_reg = MT8195_DISP_MUTEX0_MOD0,
+	.mutex_sof_reg = MT8195_DISP_MUTEX0_SOF,
+};
+
 struct mtk_mutex *mtk_mutex_get(struct device *dev)
 {
 	struct mtk_mutex_ctx *mtx = dev_get_drvdata(dev);
@@ -423,6 +498,9 @@ void mtk_mutex_add_comp(struct mtk_mutex *mutex,
 	case DDP_COMPONENT_DPI1:
 		sof_id = MUTEX_SOF_DPI1;
 		break;
+	case DDP_COMPONENT_DP_INTF0:
+		sof_id = MUTEX_SOF_DP_INTF0;
+		break;
 	default:
 		if (mtx->data->mutex_mod[id] < 32) {
 			offset = DISP_REG_MUTEX_MOD(mtx->data->mutex_mod_reg,
@@ -462,6 +540,7 @@ void mtk_mutex_remove_comp(struct mtk_mutex *mutex,
 	case DDP_COMPONENT_DSI3:
 	case DDP_COMPONENT_DPI0:
 	case DDP_COMPONENT_DPI1:
+	case DDP_COMPONENT_DP_INTF0:
 		writel_relaxed(MUTEX_SOF_SINGLE_MODE,
 			       mtx->regs +
 			       DISP_REG_MUTEX_SOF(mtx->data->mutex_sof_reg,
@@ -587,6 +666,8 @@ static const struct of_device_id mutex_driver_dt_match[] = {
 	  .data = &mt8186_mutex_driver_data},
 	{ .compatible = "mediatek,mt8192-disp-mutex",
 	  .data = &mt8192_mutex_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = &mt8195_mutex_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mutex_driver_dt_match);
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 05/10] drm/mediatek: add DSC support for mediatek-drm
  2022-04-12 10:31 ` jason-jh.lin
  (?)
@ 2022-04-12 10:31   ` jason-jh.lin
  -1 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: fshao, David Airlie, singo.chang, dri-devel, Fabien Parent,
	linux-stm32, roy-cw.yeh, Project_Global_Chrome_Upstream_Group,
	Yongqiang Niu, Rex-BC Chen, devicetree, nancy.lin,
	linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
	linux-kernel, moudy.ho, Maxime Coquelin

DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 +++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 2e99aee13dfe..68a00b336897 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -40,6 +40,12 @@
 #define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
 
+#define DISP_REG_DSC_CON			0x0000
+#define DSC_EN					BIT(0)
+#define DSC_DUAL_INOUT				BIT(2)
+#define DSC_BYPASS				BIT(4)
+#define DSC_UFOE_SEL				BIT(16)
+
 #define DISP_REG_OD_EN				0x0000
 #define DISP_REG_OD_CFG				0x0020
 #define OD_RELAYMODE				BIT(0)
@@ -181,6 +187,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
 			      DISP_DITHERING, cmdq_pkt);
 }
 
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+			   unsigned int h, unsigned int vrefresh,
+			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* dsc bypass mode */
+	mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_BYPASS);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_UFOE_SEL);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* write with mask to reserve the value set in mtk_dsc_config */
+	mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
 static void mtk_od_config(struct device *dev, unsigned int w,
 			  unsigned int h, unsigned int vrefresh,
 			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -270,6 +306,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
 	.stop = mtk_dpi_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+	.clk_enable = mtk_ddp_clk_enable,
+	.clk_disable = mtk_ddp_clk_disable,
+	.config = mtk_dsc_config,
+	.start = mtk_dsc_start,
+	.stop = mtk_dsc_stop,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_dsi = {
 	.start = mtk_dsi_ddp_start,
 	.stop = mtk_dsi_ddp_stop,
@@ -339,6 +383,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_CCORR] = "ccorr",
 	[MTK_DISP_COLOR] = "color",
 	[MTK_DISP_DITHER] = "dither",
+	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
@@ -369,6 +414,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DITHER]		= { MTK_DISP_DITHER,	0, &ddp_dither },
 	[DDP_COMPONENT_DPI0]		= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]		= { MTK_DPI,		1, &ddp_dpi },
+	[DDP_COMPONENT_DSC0]		= { MTK_DISP_DSC,	0, &ddp_dsc },
+	[DDP_COMPONENT_DSC1]		= { MTK_DISP_DSC,	1, &ddp_dsc },
 	[DDP_COMPONENT_DSI0]		= { MTK_DSI,		0, &ddp_dsi },
 	[DDP_COMPONENT_DSI1]		= { MTK_DSI,		1, &ddp_dsi },
 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,		2, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index ad267bb8fc9b..763725fe72b3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_CCORR,
 	MTK_DISP_COLOR,
 	MTK_DISP_DITHER,
+	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 05/10] drm/mediatek: add DSC support for mediatek-drm
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: David Airlie, singo.chang, dri-devel, Fabien Parent, linux-stm32,
	roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
	Rex-BC Chen, Philipp Zabel, devicetree, Daniel Vetter, CK Hu,
	nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 +++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 2e99aee13dfe..68a00b336897 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -40,6 +40,12 @@
 #define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
 
+#define DISP_REG_DSC_CON			0x0000
+#define DSC_EN					BIT(0)
+#define DSC_DUAL_INOUT				BIT(2)
+#define DSC_BYPASS				BIT(4)
+#define DSC_UFOE_SEL				BIT(16)
+
 #define DISP_REG_OD_EN				0x0000
 #define DISP_REG_OD_CFG				0x0020
 #define OD_RELAYMODE				BIT(0)
@@ -181,6 +187,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
 			      DISP_DITHERING, cmdq_pkt);
 }
 
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+			   unsigned int h, unsigned int vrefresh,
+			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* dsc bypass mode */
+	mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_BYPASS);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_UFOE_SEL);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* write with mask to reserve the value set in mtk_dsc_config */
+	mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
 static void mtk_od_config(struct device *dev, unsigned int w,
 			  unsigned int h, unsigned int vrefresh,
 			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -270,6 +306,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
 	.stop = mtk_dpi_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+	.clk_enable = mtk_ddp_clk_enable,
+	.clk_disable = mtk_ddp_clk_disable,
+	.config = mtk_dsc_config,
+	.start = mtk_dsc_start,
+	.stop = mtk_dsc_stop,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_dsi = {
 	.start = mtk_dsi_ddp_start,
 	.stop = mtk_dsi_ddp_stop,
@@ -339,6 +383,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_CCORR] = "ccorr",
 	[MTK_DISP_COLOR] = "color",
 	[MTK_DISP_DITHER] = "dither",
+	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
@@ -369,6 +414,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DITHER]		= { MTK_DISP_DITHER,	0, &ddp_dither },
 	[DDP_COMPONENT_DPI0]		= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]		= { MTK_DPI,		1, &ddp_dpi },
+	[DDP_COMPONENT_DSC0]		= { MTK_DISP_DSC,	0, &ddp_dsc },
+	[DDP_COMPONENT_DSC1]		= { MTK_DISP_DSC,	1, &ddp_dsc },
 	[DDP_COMPONENT_DSI0]		= { MTK_DSI,		0, &ddp_dsi },
 	[DDP_COMPONENT_DSI1]		= { MTK_DSI,		1, &ddp_dsi },
 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,		2, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index ad267bb8fc9b..763725fe72b3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_CCORR,
 	MTK_DISP_COLOR,
 	MTK_DISP_DITHER,
+	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 05/10] drm/mediatek: add DSC support for mediatek-drm
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu, jason-jh . lin, Rex-BC Chen, Yongqiang Niu,
	hsinyi, fshao, moudy.ho, roy-cw.yeh, nancy.lin, singo.chang,
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

DSC is designed for real-time systems with real-time compression,
transmission, decompression and display.
The DSC standard is a specification of the algorithms used for
compressing and decompressing image display streams, including
the specification of the syntax and semantics of the compressed
video bit stream.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 47 +++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |  1 +
 2 files changed, 48 insertions(+)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 2e99aee13dfe..68a00b336897 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -40,6 +40,12 @@
 #define DITHER_LSB_ERR_SHIFT_G(x)		(((x) & 0x7) << 12)
 #define DITHER_ADD_LSHIFT_G(x)			(((x) & 0x7) << 4)
 
+#define DISP_REG_DSC_CON			0x0000
+#define DSC_EN					BIT(0)
+#define DSC_DUAL_INOUT				BIT(2)
+#define DSC_BYPASS				BIT(4)
+#define DSC_UFOE_SEL				BIT(16)
+
 #define DISP_REG_OD_EN				0x0000
 #define DISP_REG_OD_CFG				0x0020
 #define OD_RELAYMODE				BIT(0)
@@ -181,6 +187,36 @@ static void mtk_dither_set(struct device *dev, unsigned int bpc,
 			      DISP_DITHERING, cmdq_pkt);
 }
 
+static void mtk_dsc_config(struct device *dev, unsigned int w,
+			   unsigned int h, unsigned int vrefresh,
+			   unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* dsc bypass mode */
+	mtk_ddp_write_mask(cmdq_pkt, DSC_BYPASS, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_BYPASS);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_UFOE_SEL, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_UFOE_SEL);
+	mtk_ddp_write_mask(cmdq_pkt, DSC_DUAL_INOUT, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_DSC_CON, DSC_DUAL_INOUT);
+}
+
+static void mtk_dsc_start(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	/* write with mask to reserve the value set in mtk_dsc_config */
+	mtk_ddp_write_mask(NULL, DSC_EN, &priv->cmdq_reg, priv->regs, DISP_REG_DSC_CON, DSC_EN);
+}
+
+static void mtk_dsc_stop(struct device *dev)
+{
+	struct mtk_ddp_comp_dev *priv = dev_get_drvdata(dev);
+
+	writel_relaxed(0x0, priv->regs + DISP_REG_DSC_CON);
+}
+
 static void mtk_od_config(struct device *dev, unsigned int w,
 			  unsigned int h, unsigned int vrefresh,
 			  unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
@@ -270,6 +306,14 @@ static const struct mtk_ddp_comp_funcs ddp_dpi = {
 	.stop = mtk_dpi_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_dsc = {
+	.clk_enable = mtk_ddp_clk_enable,
+	.clk_disable = mtk_ddp_clk_disable,
+	.config = mtk_dsc_config,
+	.start = mtk_dsc_start,
+	.stop = mtk_dsc_stop,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_dsi = {
 	.start = mtk_dsi_ddp_start,
 	.stop = mtk_dsi_ddp_stop,
@@ -339,6 +383,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_CCORR] = "ccorr",
 	[MTK_DISP_COLOR] = "color",
 	[MTK_DISP_DITHER] = "dither",
+	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
@@ -369,6 +414,8 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DITHER]		= { MTK_DISP_DITHER,	0, &ddp_dither },
 	[DDP_COMPONENT_DPI0]		= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]		= { MTK_DPI,		1, &ddp_dpi },
+	[DDP_COMPONENT_DSC0]		= { MTK_DISP_DSC,	0, &ddp_dsc },
+	[DDP_COMPONENT_DSC1]		= { MTK_DISP_DSC,	1, &ddp_dsc },
 	[DDP_COMPONENT_DSI0]		= { MTK_DSI,		0, &ddp_dsi },
 	[DDP_COMPONENT_DSI1]		= { MTK_DSI,		1, &ddp_dsi },
 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,		2, &ddp_dsi },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index ad267bb8fc9b..763725fe72b3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -23,6 +23,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_CCORR,
 	MTK_DISP_COLOR,
 	MTK_DISP_DITHER,
+	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 06/10] drm/mediatek: add MERGE support for mediatek-drm
  2022-04-12 10:31 ` jason-jh.lin
  (?)
@ 2022-04-12 10:31   ` jason-jh.lin
  -1 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: fshao, David Airlie, singo.chang, dri-devel, Fabien Parent,
	linux-stm32, roy-cw.yeh, Project_Global_Chrome_Upstream_Group,
	Yongqiang Niu, Rex-BC Chen, devicetree, nancy.lin,
	linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
	linux-kernel, moudy.ho, Maxime Coquelin

Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 246 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  16 ++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 7 files changed, 276 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 29098d7c8307..a38e88e82d12 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_aal.o \
 		  mtk_disp_ccorr.o \
 		  mtk_disp_color.o \
 		  mtk_disp_gamma.o \
+		  mtk_disp_merge.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
 		  mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 86c3068894b1..a33b13fe2b6e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -55,6 +55,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
 void mtk_gamma_start(struct device *dev);
 void mtk_gamma_stop(struct device *dev);
 
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+		      unsigned int height, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
 void mtk_ovl_bgclr_in_on(struct device *dev);
 void mtk_ovl_bgclr_in_off(struct device *dev);
 void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..45face638153
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL		0x000
+#define MERGE_EN				1
+#define DISP_REG_MERGE_CFG_0		0x010
+#define DISP_REG_MERGE_CFG_4		0x020
+#define DISP_REG_MERGE_CFG_10		0x038
+/* no swap */
+#define SWAP_MODE				0
+#define FLD_SWAP_MODE				GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12		0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE		6
+#define CFG_10_10_2PI_2PO_BUF_MODE		8
+#define FLD_CFG_MERGE_MODE			GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24		0x070
+#define DISP_REG_MERGE_CFG_25		0x074
+#define DISP_REG_MERGE_CFG_36		0x0a0
+#define ULTRA_EN				BIT(0)
+#define PREULTRA_EN				BIT(4)
+#define DISP_REG_MERGE_CFG_37		0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE				3
+#define FLD_BUFFER_MODE				GENMASK(1, 0)
+/*
+ * For the ultra and preultra settings, 6us ~ 9us is experience value
+ * and the maximum frequency of mmsys clock is 594MHz.
+ */
+#define DISP_REG_MERGE_CFG_40		0x0b0
+/* 6 us, 594M pixel/sec */
+#define ULTRA_TH_LOW				(6 * 594)
+/* 8 us, 594M pixel/sec */
+#define ULTRA_TH_HIGH				(8 * 594)
+#define FLD_ULTRA_TH_LOW			GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH			GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41		0x0b4
+/* 8 us, 594M pixel/sec */
+#define PREULTRA_TH_LOW				(8 * 594)
+/* 9 us, 594M pixel/sec */
+#define PREULTRA_TH_HIGH			(9 * 594)
+#define FLD_PREULTRA_TH_LOW			GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH			GENMASK(31, 16)
+
+struct mtk_disp_merge {
+	void __iomem			*regs;
+	struct clk			*clk;
+	struct clk			*async_clk;
+	struct cmdq_client_reg		cmdq_reg;
+	bool				fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+				   struct cmdq_pkt *cmdq_pkt)
+{
+	mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,
+		      &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36);
+
+	mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+			   FLD_BUFFER_MODE);
+
+	mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+			   FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+	mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+			   FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+		      unsigned int h, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+	unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+	if (!h || !w) {
+		dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+		return;
+	}
+
+	if (priv->fifo_en) {
+		mtk_merge_fifo_setting(priv, cmdq_pkt);
+		mode = CFG_10_10_2PI_2PO_BUF_MODE;
+	}
+
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_0);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_4);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_24);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_25);
+	mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+	mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+	int ret = 0;
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret) {
+		dev_err(dev, "merge clk prepare enable failed\n");
+		return ret;
+	}
+
+	ret = clk_prepare_enable(priv->async_clk);
+	if (ret) {
+		/* should clean up the state of priv->clk */
+		clk_disable_unprepare(priv->clk);
+
+		dev_err(dev, "async clk prepare enable failed\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(priv->async_clk);
+	clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+				  void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+	.bind	= mtk_disp_merge_bind,
+	.unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_disp_merge *priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap merge\n");
+		return PTR_ERR(priv->regs);
+	}
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get merge clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->async_clk = devm_clk_get_optional(dev, "merge_async");
+	if (IS_ERR(priv->async_clk)) {
+		dev_err(dev, "failed to get merge async clock\n");
+		return PTR_ERR(priv->async_clk);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+	priv->fifo_en = of_property_read_bool(dev->of_node,
+					      "mediatek,merge-fifo-en");
+
+	platform_set_drvdata(pdev, priv);
+
+	ret = component_add(dev, &mtk_disp_merge_component_ops);
+	if (ret != 0)
+		dev_err(dev, "Failed to add component: %d\n", ret);
+
+	return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+	return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8195-disp-merge", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+	.probe = mtk_disp_merge_probe,
+	.remove = mtk_disp_merge_remove,
+	.driver = {
+		.name = "mediatek-disp-merge",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_disp_merge_driver_dt_match,
+	},
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 68a00b336897..f683e768d61b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -328,6 +328,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
 	.stop = mtk_gamma_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+	.clk_enable = mtk_merge_clk_enable,
+	.clk_disable = mtk_merge_clk_disable,
+	.start = mtk_merge_start,
+	.stop = mtk_merge_stop,
+	.config = mtk_merge_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_od = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -385,6 +393,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_DITHER] = "dither",
 	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MERGE] = "merge",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_OVL] = "ovl",
@@ -421,6 +430,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,		2, &ddp_dsi },
 	[DDP_COMPONENT_DSI3]		= { MTK_DSI,		3, &ddp_dsi },
 	[DDP_COMPONENT_GAMMA]		= { MTK_DISP_GAMMA,	0, &ddp_gamma },
+	[DDP_COMPONENT_MERGE0]		= { MTK_DISP_MERGE,	0, &ddp_merge },
+	[DDP_COMPONENT_MERGE1]		= { MTK_DISP_MERGE,	1, &ddp_merge },
+	[DDP_COMPONENT_MERGE2]		= { MTK_DISP_MERGE,	2, &ddp_merge },
+	[DDP_COMPONENT_MERGE3]		= { MTK_DISP_MERGE,	3, &ddp_merge },
+	[DDP_COMPONENT_MERGE4]		= { MTK_DISP_MERGE,	4, &ddp_merge },
+	[DDP_COMPONENT_MERGE5]		= { MTK_DISP_MERGE,	5, &ddp_merge },
 	[DDP_COMPONENT_OD0]		= { MTK_DISP_OD,	0, &ddp_od },
 	[DDP_COMPONENT_OD1]		= { MTK_DISP_OD,	1, &ddp_od },
 	[DDP_COMPONENT_OVL0]		= { MTK_DISP_OVL,	0, &ddp_ovl },
@@ -523,6 +538,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
+	    type == MTK_DISP_MERGE ||
 	    type == MTK_DISP_OVL ||
 	    type == MTK_DISP_OVL_2L ||
 	    type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 763725fe72b3..09ac9496547d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_DITHER,
 	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
+	MTK_DISP_MERGE,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
 	MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 247c6ff277ef..f54b650a2ea1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -597,7 +597,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		private->comp_node[comp_id] = of_node_get(node);
 
 		/*
-		 * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+		 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
 		 * blocks have separate component platform drivers and initialize their own
 		 * DDP component structure. The others are initialized here.
 		 */
@@ -605,6 +605,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		    comp_type == MTK_DISP_CCORR ||
 		    comp_type == MTK_DISP_COLOR ||
 		    comp_type == MTK_DISP_GAMMA ||
+		    comp_type == MTK_DISP_MERGE ||
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
@@ -703,6 +704,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_ccorr_driver,
 	&mtk_disp_color_driver,
 	&mtk_disp_gamma_driver,
+	&mtk_disp_merge_driver,
 	&mtk_disp_ovl_driver,
 	&mtk_disp_rdma_driver,
 	&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 3e7d1e6fbe01..a58cebd01d35 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -50,6 +50,7 @@ extern struct platform_driver mtk_disp_aal_driver;
 extern struct platform_driver mtk_disp_ccorr_driver;
 extern struct platform_driver mtk_disp_color_driver;
 extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
 extern struct platform_driver mtk_dpi_driver;
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 06/10] drm/mediatek: add MERGE support for mediatek-drm
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: David Airlie, singo.chang, dri-devel, Fabien Parent, linux-stm32,
	roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
	Rex-BC Chen, Philipp Zabel, devicetree, Daniel Vetter, CK Hu,
	nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 246 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  16 ++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 7 files changed, 276 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 29098d7c8307..a38e88e82d12 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_aal.o \
 		  mtk_disp_ccorr.o \
 		  mtk_disp_color.o \
 		  mtk_disp_gamma.o \
+		  mtk_disp_merge.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
 		  mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 86c3068894b1..a33b13fe2b6e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -55,6 +55,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
 void mtk_gamma_start(struct device *dev);
 void mtk_gamma_stop(struct device *dev);
 
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+		      unsigned int height, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
 void mtk_ovl_bgclr_in_on(struct device *dev);
 void mtk_ovl_bgclr_in_off(struct device *dev);
 void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..45face638153
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL		0x000
+#define MERGE_EN				1
+#define DISP_REG_MERGE_CFG_0		0x010
+#define DISP_REG_MERGE_CFG_4		0x020
+#define DISP_REG_MERGE_CFG_10		0x038
+/* no swap */
+#define SWAP_MODE				0
+#define FLD_SWAP_MODE				GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12		0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE		6
+#define CFG_10_10_2PI_2PO_BUF_MODE		8
+#define FLD_CFG_MERGE_MODE			GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24		0x070
+#define DISP_REG_MERGE_CFG_25		0x074
+#define DISP_REG_MERGE_CFG_36		0x0a0
+#define ULTRA_EN				BIT(0)
+#define PREULTRA_EN				BIT(4)
+#define DISP_REG_MERGE_CFG_37		0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE				3
+#define FLD_BUFFER_MODE				GENMASK(1, 0)
+/*
+ * For the ultra and preultra settings, 6us ~ 9us is experience value
+ * and the maximum frequency of mmsys clock is 594MHz.
+ */
+#define DISP_REG_MERGE_CFG_40		0x0b0
+/* 6 us, 594M pixel/sec */
+#define ULTRA_TH_LOW				(6 * 594)
+/* 8 us, 594M pixel/sec */
+#define ULTRA_TH_HIGH				(8 * 594)
+#define FLD_ULTRA_TH_LOW			GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH			GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41		0x0b4
+/* 8 us, 594M pixel/sec */
+#define PREULTRA_TH_LOW				(8 * 594)
+/* 9 us, 594M pixel/sec */
+#define PREULTRA_TH_HIGH			(9 * 594)
+#define FLD_PREULTRA_TH_LOW			GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH			GENMASK(31, 16)
+
+struct mtk_disp_merge {
+	void __iomem			*regs;
+	struct clk			*clk;
+	struct clk			*async_clk;
+	struct cmdq_client_reg		cmdq_reg;
+	bool				fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+				   struct cmdq_pkt *cmdq_pkt)
+{
+	mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,
+		      &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36);
+
+	mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+			   FLD_BUFFER_MODE);
+
+	mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+			   FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+	mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+			   FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+		      unsigned int h, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+	unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+	if (!h || !w) {
+		dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+		return;
+	}
+
+	if (priv->fifo_en) {
+		mtk_merge_fifo_setting(priv, cmdq_pkt);
+		mode = CFG_10_10_2PI_2PO_BUF_MODE;
+	}
+
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_0);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_4);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_24);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_25);
+	mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+	mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+	int ret = 0;
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret) {
+		dev_err(dev, "merge clk prepare enable failed\n");
+		return ret;
+	}
+
+	ret = clk_prepare_enable(priv->async_clk);
+	if (ret) {
+		/* should clean up the state of priv->clk */
+		clk_disable_unprepare(priv->clk);
+
+		dev_err(dev, "async clk prepare enable failed\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(priv->async_clk);
+	clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+				  void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+	.bind	= mtk_disp_merge_bind,
+	.unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_disp_merge *priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap merge\n");
+		return PTR_ERR(priv->regs);
+	}
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get merge clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->async_clk = devm_clk_get_optional(dev, "merge_async");
+	if (IS_ERR(priv->async_clk)) {
+		dev_err(dev, "failed to get merge async clock\n");
+		return PTR_ERR(priv->async_clk);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+	priv->fifo_en = of_property_read_bool(dev->of_node,
+					      "mediatek,merge-fifo-en");
+
+	platform_set_drvdata(pdev, priv);
+
+	ret = component_add(dev, &mtk_disp_merge_component_ops);
+	if (ret != 0)
+		dev_err(dev, "Failed to add component: %d\n", ret);
+
+	return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+	return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8195-disp-merge", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+	.probe = mtk_disp_merge_probe,
+	.remove = mtk_disp_merge_remove,
+	.driver = {
+		.name = "mediatek-disp-merge",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_disp_merge_driver_dt_match,
+	},
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 68a00b336897..f683e768d61b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -328,6 +328,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
 	.stop = mtk_gamma_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+	.clk_enable = mtk_merge_clk_enable,
+	.clk_disable = mtk_merge_clk_disable,
+	.start = mtk_merge_start,
+	.stop = mtk_merge_stop,
+	.config = mtk_merge_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_od = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -385,6 +393,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_DITHER] = "dither",
 	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MERGE] = "merge",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_OVL] = "ovl",
@@ -421,6 +430,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,		2, &ddp_dsi },
 	[DDP_COMPONENT_DSI3]		= { MTK_DSI,		3, &ddp_dsi },
 	[DDP_COMPONENT_GAMMA]		= { MTK_DISP_GAMMA,	0, &ddp_gamma },
+	[DDP_COMPONENT_MERGE0]		= { MTK_DISP_MERGE,	0, &ddp_merge },
+	[DDP_COMPONENT_MERGE1]		= { MTK_DISP_MERGE,	1, &ddp_merge },
+	[DDP_COMPONENT_MERGE2]		= { MTK_DISP_MERGE,	2, &ddp_merge },
+	[DDP_COMPONENT_MERGE3]		= { MTK_DISP_MERGE,	3, &ddp_merge },
+	[DDP_COMPONENT_MERGE4]		= { MTK_DISP_MERGE,	4, &ddp_merge },
+	[DDP_COMPONENT_MERGE5]		= { MTK_DISP_MERGE,	5, &ddp_merge },
 	[DDP_COMPONENT_OD0]		= { MTK_DISP_OD,	0, &ddp_od },
 	[DDP_COMPONENT_OD1]		= { MTK_DISP_OD,	1, &ddp_od },
 	[DDP_COMPONENT_OVL0]		= { MTK_DISP_OVL,	0, &ddp_ovl },
@@ -523,6 +538,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
+	    type == MTK_DISP_MERGE ||
 	    type == MTK_DISP_OVL ||
 	    type == MTK_DISP_OVL_2L ||
 	    type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 763725fe72b3..09ac9496547d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_DITHER,
 	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
+	MTK_DISP_MERGE,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
 	MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 247c6ff277ef..f54b650a2ea1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -597,7 +597,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		private->comp_node[comp_id] = of_node_get(node);
 
 		/*
-		 * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+		 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
 		 * blocks have separate component platform drivers and initialize their own
 		 * DDP component structure. The others are initialized here.
 		 */
@@ -605,6 +605,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		    comp_type == MTK_DISP_CCORR ||
 		    comp_type == MTK_DISP_COLOR ||
 		    comp_type == MTK_DISP_GAMMA ||
+		    comp_type == MTK_DISP_MERGE ||
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
@@ -703,6 +704,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_ccorr_driver,
 	&mtk_disp_color_driver,
 	&mtk_disp_gamma_driver,
+	&mtk_disp_merge_driver,
 	&mtk_disp_ovl_driver,
 	&mtk_disp_rdma_driver,
 	&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 3e7d1e6fbe01..a58cebd01d35 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -50,6 +50,7 @@ extern struct platform_driver mtk_disp_aal_driver;
 extern struct platform_driver mtk_disp_ccorr_driver;
 extern struct platform_driver mtk_disp_color_driver;
 extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
 extern struct platform_driver mtk_dpi_driver;
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 06/10] drm/mediatek: add MERGE support for mediatek-drm
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu, jason-jh . lin, Rex-BC Chen, Yongqiang Niu,
	hsinyi, fshao, moudy.ho, roy-cw.yeh, nancy.lin, singo.chang,
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

Add MERGE engine file:
MERGE module is used to merge two slice-per-line inputs
into one side-by-side output.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
Acked-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Reviewed-by: Chun-Kuang Hu <chunkuang.hu@kernel.org>
---
 drivers/gpu/drm/mediatek/Makefile           |   1 +
 drivers/gpu/drm/mediatek/mtk_disp_drv.h     |   8 +
 drivers/gpu/drm/mediatek/mtk_disp_merge.c   | 246 ++++++++++++++++++++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c |  16 ++
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h |   1 +
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      |   4 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h      |   1 +
 7 files changed, 276 insertions(+), 1 deletion(-)
 create mode 100644 drivers/gpu/drm/mediatek/mtk_disp_merge.c

diff --git a/drivers/gpu/drm/mediatek/Makefile b/drivers/gpu/drm/mediatek/Makefile
index 29098d7c8307..a38e88e82d12 100644
--- a/drivers/gpu/drm/mediatek/Makefile
+++ b/drivers/gpu/drm/mediatek/Makefile
@@ -4,6 +4,7 @@ mediatek-drm-y := mtk_disp_aal.o \
 		  mtk_disp_ccorr.o \
 		  mtk_disp_color.o \
 		  mtk_disp_gamma.o \
+		  mtk_disp_merge.o \
 		  mtk_disp_ovl.o \
 		  mtk_disp_rdma.o \
 		  mtk_drm_crtc.o \
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_drv.h b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
index 86c3068894b1..a33b13fe2b6e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_disp_drv.h
@@ -55,6 +55,14 @@ void mtk_gamma_set_common(void __iomem *regs, struct drm_crtc_state *state);
 void mtk_gamma_start(struct device *dev);
 void mtk_gamma_stop(struct device *dev);
 
+int mtk_merge_clk_enable(struct device *dev);
+void mtk_merge_clk_disable(struct device *dev);
+void mtk_merge_config(struct device *dev, unsigned int width,
+		      unsigned int height, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt);
+void mtk_merge_start(struct device *dev);
+void mtk_merge_stop(struct device *dev);
+
 void mtk_ovl_bgclr_in_on(struct device *dev);
 void mtk_ovl_bgclr_in_off(struct device *dev);
 void mtk_ovl_bypass_shadow(struct device *dev);
diff --git a/drivers/gpu/drm/mediatek/mtk_disp_merge.c b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
new file mode 100644
index 000000000000..45face638153
--- /dev/null
+++ b/drivers/gpu/drm/mediatek/mtk_disp_merge.c
@@ -0,0 +1,246 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2021 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/component.h>
+#include <linux/of_device.h>
+#include <linux/of_irq.h>
+#include <linux/platform_device.h>
+#include <linux/soc/mediatek/mtk-cmdq.h>
+
+#include "mtk_drm_ddp_comp.h"
+#include "mtk_drm_drv.h"
+#include "mtk_disp_drv.h"
+
+#define DISP_REG_MERGE_CTRL		0x000
+#define MERGE_EN				1
+#define DISP_REG_MERGE_CFG_0		0x010
+#define DISP_REG_MERGE_CFG_4		0x020
+#define DISP_REG_MERGE_CFG_10		0x038
+/* no swap */
+#define SWAP_MODE				0
+#define FLD_SWAP_MODE				GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_12		0x040
+#define CFG_10_10_1PI_2PO_BUF_MODE		6
+#define CFG_10_10_2PI_2PO_BUF_MODE		8
+#define FLD_CFG_MERGE_MODE			GENMASK(4, 0)
+#define DISP_REG_MERGE_CFG_24		0x070
+#define DISP_REG_MERGE_CFG_25		0x074
+#define DISP_REG_MERGE_CFG_36		0x0a0
+#define ULTRA_EN				BIT(0)
+#define PREULTRA_EN				BIT(4)
+#define DISP_REG_MERGE_CFG_37		0x0a4
+/* 0: Off, 1: SRAM0, 2: SRAM1, 3: SRAM0 + SRAM1 */
+#define BUFFER_MODE				3
+#define FLD_BUFFER_MODE				GENMASK(1, 0)
+/*
+ * For the ultra and preultra settings, 6us ~ 9us is experience value
+ * and the maximum frequency of mmsys clock is 594MHz.
+ */
+#define DISP_REG_MERGE_CFG_40		0x0b0
+/* 6 us, 594M pixel/sec */
+#define ULTRA_TH_LOW				(6 * 594)
+/* 8 us, 594M pixel/sec */
+#define ULTRA_TH_HIGH				(8 * 594)
+#define FLD_ULTRA_TH_LOW			GENMASK(15, 0)
+#define FLD_ULTRA_TH_HIGH			GENMASK(31, 16)
+#define DISP_REG_MERGE_CFG_41		0x0b4
+/* 8 us, 594M pixel/sec */
+#define PREULTRA_TH_LOW				(8 * 594)
+/* 9 us, 594M pixel/sec */
+#define PREULTRA_TH_HIGH			(9 * 594)
+#define FLD_PREULTRA_TH_LOW			GENMASK(15, 0)
+#define FLD_PREULTRA_TH_HIGH			GENMASK(31, 16)
+
+struct mtk_disp_merge {
+	void __iomem			*regs;
+	struct clk			*clk;
+	struct clk			*async_clk;
+	struct cmdq_client_reg		cmdq_reg;
+	bool				fifo_en;
+};
+
+void mtk_merge_start(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(MERGE_EN, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+void mtk_merge_stop(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	writel(0x0, priv->regs + DISP_REG_MERGE_CTRL);
+}
+
+static void mtk_merge_fifo_setting(struct mtk_disp_merge *priv,
+				   struct cmdq_pkt *cmdq_pkt)
+{
+	mtk_ddp_write(cmdq_pkt, ULTRA_EN | PREULTRA_EN,
+		      &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_36);
+
+	mtk_ddp_write_mask(cmdq_pkt, BUFFER_MODE,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_37,
+			   FLD_BUFFER_MODE);
+
+	mtk_ddp_write_mask(cmdq_pkt, ULTRA_TH_LOW | ULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_40,
+			   FLD_ULTRA_TH_LOW | FLD_ULTRA_TH_HIGH);
+
+	mtk_ddp_write_mask(cmdq_pkt, PREULTRA_TH_LOW | PREULTRA_TH_HIGH << 16,
+			   &priv->cmdq_reg, priv->regs, DISP_REG_MERGE_CFG_41,
+			   FLD_PREULTRA_TH_LOW | FLD_PREULTRA_TH_HIGH);
+}
+
+void mtk_merge_config(struct device *dev, unsigned int w,
+		      unsigned int h, unsigned int vrefresh,
+		      unsigned int bpc, struct cmdq_pkt *cmdq_pkt)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+	unsigned int mode = CFG_10_10_1PI_2PO_BUF_MODE;
+
+	if (!h || !w) {
+		dev_err(dev, "%s: input width(%d) or height(%d) is invalid\n", __func__, w, h);
+		return;
+	}
+
+	if (priv->fifo_en) {
+		mtk_merge_fifo_setting(priv, cmdq_pkt);
+		mode = CFG_10_10_2PI_2PO_BUF_MODE;
+	}
+
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_0);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_4);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_24);
+	mtk_ddp_write(cmdq_pkt, h << 16 | w, &priv->cmdq_reg, priv->regs,
+		      DISP_REG_MERGE_CFG_25);
+	mtk_ddp_write_mask(cmdq_pkt, SWAP_MODE, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_10, FLD_SWAP_MODE);
+	mtk_ddp_write_mask(cmdq_pkt, mode, &priv->cmdq_reg, priv->regs,
+			   DISP_REG_MERGE_CFG_12, FLD_CFG_MERGE_MODE);
+}
+
+int mtk_merge_clk_enable(struct device *dev)
+{
+	int ret = 0;
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	ret = clk_prepare_enable(priv->clk);
+	if (ret) {
+		dev_err(dev, "merge clk prepare enable failed\n");
+		return ret;
+	}
+
+	ret = clk_prepare_enable(priv->async_clk);
+	if (ret) {
+		/* should clean up the state of priv->clk */
+		clk_disable_unprepare(priv->clk);
+
+		dev_err(dev, "async clk prepare enable failed\n");
+		return ret;
+	}
+
+	return ret;
+}
+
+void mtk_merge_clk_disable(struct device *dev)
+{
+	struct mtk_disp_merge *priv = dev_get_drvdata(dev);
+
+	clk_disable_unprepare(priv->async_clk);
+	clk_disable_unprepare(priv->clk);
+}
+
+static int mtk_disp_merge_bind(struct device *dev, struct device *master,
+			       void *data)
+{
+	return 0;
+}
+
+static void mtk_disp_merge_unbind(struct device *dev, struct device *master,
+				  void *data)
+{
+}
+
+static const struct component_ops mtk_disp_merge_component_ops = {
+	.bind	= mtk_disp_merge_bind,
+	.unbind = mtk_disp_merge_unbind,
+};
+
+static int mtk_disp_merge_probe(struct platform_device *pdev)
+{
+	struct device *dev = &pdev->dev;
+	struct resource *res;
+	struct mtk_disp_merge *priv;
+	int ret;
+
+	priv = devm_kzalloc(dev, sizeof(*priv), GFP_KERNEL);
+	if (!priv)
+		return -ENOMEM;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	priv->regs = devm_ioremap_resource(dev, res);
+	if (IS_ERR(priv->regs)) {
+		dev_err(dev, "failed to ioremap merge\n");
+		return PTR_ERR(priv->regs);
+	}
+
+	priv->clk = devm_clk_get(dev, NULL);
+	if (IS_ERR(priv->clk)) {
+		dev_err(dev, "failed to get merge clk\n");
+		return PTR_ERR(priv->clk);
+	}
+
+	priv->async_clk = devm_clk_get_optional(dev, "merge_async");
+	if (IS_ERR(priv->async_clk)) {
+		dev_err(dev, "failed to get merge async clock\n");
+		return PTR_ERR(priv->async_clk);
+	}
+
+#if IS_REACHABLE(CONFIG_MTK_CMDQ)
+	ret = cmdq_dev_get_client_reg(dev, &priv->cmdq_reg, 0);
+	if (ret)
+		dev_dbg(dev, "get mediatek,gce-client-reg fail!\n");
+#endif
+
+	priv->fifo_en = of_property_read_bool(dev->of_node,
+					      "mediatek,merge-fifo-en");
+
+	platform_set_drvdata(pdev, priv);
+
+	ret = component_add(dev, &mtk_disp_merge_component_ops);
+	if (ret != 0)
+		dev_err(dev, "Failed to add component: %d\n", ret);
+
+	return ret;
+}
+
+static int mtk_disp_merge_remove(struct platform_device *pdev)
+{
+	component_del(&pdev->dev, &mtk_disp_merge_component_ops);
+
+	return 0;
+}
+
+static const struct of_device_id mtk_disp_merge_driver_dt_match[] = {
+	{ .compatible = "mediatek,mt8195-disp-merge", },
+	{},
+};
+
+MODULE_DEVICE_TABLE(of, mtk_disp_merge_driver_dt_match);
+
+struct platform_driver mtk_disp_merge_driver = {
+	.probe = mtk_disp_merge_probe,
+	.remove = mtk_disp_merge_remove,
+	.driver = {
+		.name = "mediatek-disp-merge",
+		.owner = THIS_MODULE,
+		.of_match_table = mtk_disp_merge_driver_dt_match,
+	},
+};
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index 68a00b336897..f683e768d61b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -328,6 +328,14 @@ static const struct mtk_ddp_comp_funcs ddp_gamma = {
 	.stop = mtk_gamma_stop,
 };
 
+static const struct mtk_ddp_comp_funcs ddp_merge = {
+	.clk_enable = mtk_merge_clk_enable,
+	.clk_disable = mtk_merge_clk_disable,
+	.start = mtk_merge_start,
+	.stop = mtk_merge_stop,
+	.config = mtk_merge_config,
+};
+
 static const struct mtk_ddp_comp_funcs ddp_od = {
 	.clk_enable = mtk_ddp_clk_enable,
 	.clk_disable = mtk_ddp_clk_disable,
@@ -385,6 +393,7 @@ static const char * const mtk_ddp_comp_stem[MTK_DDP_COMP_TYPE_MAX] = {
 	[MTK_DISP_DITHER] = "dither",
 	[MTK_DISP_DSC] = "dsc",
 	[MTK_DISP_GAMMA] = "gamma",
+	[MTK_DISP_MERGE] = "merge",
 	[MTK_DISP_MUTEX] = "mutex",
 	[MTK_DISP_OD] = "od",
 	[MTK_DISP_OVL] = "ovl",
@@ -421,6 +430,12 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_DSI2]		= { MTK_DSI,		2, &ddp_dsi },
 	[DDP_COMPONENT_DSI3]		= { MTK_DSI,		3, &ddp_dsi },
 	[DDP_COMPONENT_GAMMA]		= { MTK_DISP_GAMMA,	0, &ddp_gamma },
+	[DDP_COMPONENT_MERGE0]		= { MTK_DISP_MERGE,	0, &ddp_merge },
+	[DDP_COMPONENT_MERGE1]		= { MTK_DISP_MERGE,	1, &ddp_merge },
+	[DDP_COMPONENT_MERGE2]		= { MTK_DISP_MERGE,	2, &ddp_merge },
+	[DDP_COMPONENT_MERGE3]		= { MTK_DISP_MERGE,	3, &ddp_merge },
+	[DDP_COMPONENT_MERGE4]		= { MTK_DISP_MERGE,	4, &ddp_merge },
+	[DDP_COMPONENT_MERGE5]		= { MTK_DISP_MERGE,	5, &ddp_merge },
 	[DDP_COMPONENT_OD0]		= { MTK_DISP_OD,	0, &ddp_od },
 	[DDP_COMPONENT_OD1]		= { MTK_DISP_OD,	1, &ddp_od },
 	[DDP_COMPONENT_OVL0]		= { MTK_DISP_OVL,	0, &ddp_ovl },
@@ -523,6 +538,7 @@ int mtk_ddp_comp_init(struct device_node *node, struct mtk_ddp_comp *comp,
 	    type == MTK_DISP_CCORR ||
 	    type == MTK_DISP_COLOR ||
 	    type == MTK_DISP_GAMMA ||
+	    type == MTK_DISP_MERGE ||
 	    type == MTK_DISP_OVL ||
 	    type == MTK_DISP_OVL_2L ||
 	    type == MTK_DISP_PWM ||
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
index 763725fe72b3..09ac9496547d 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.h
@@ -25,6 +25,7 @@ enum mtk_ddp_comp_type {
 	MTK_DISP_DITHER,
 	MTK_DISP_DSC,
 	MTK_DISP_GAMMA,
+	MTK_DISP_MERGE,
 	MTK_DISP_MUTEX,
 	MTK_DISP_OD,
 	MTK_DISP_OVL,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 247c6ff277ef..f54b650a2ea1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -597,7 +597,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		private->comp_node[comp_id] = of_node_get(node);
 
 		/*
-		 * Currently only the AAL, CCORR, COLOR, GAMMA, OVL, RDMA, DSI, and DPI
+		 * Currently only the AAL, CCORR, COLOR, GAMMA, MERGE, OVL, RDMA, DSI, and DPI
 		 * blocks have separate component platform drivers and initialize their own
 		 * DDP component structure. The others are initialized here.
 		 */
@@ -605,6 +605,7 @@ static int mtk_drm_probe(struct platform_device *pdev)
 		    comp_type == MTK_DISP_CCORR ||
 		    comp_type == MTK_DISP_COLOR ||
 		    comp_type == MTK_DISP_GAMMA ||
+		    comp_type == MTK_DISP_MERGE ||
 		    comp_type == MTK_DISP_OVL ||
 		    comp_type == MTK_DISP_OVL_2L ||
 		    comp_type == MTK_DISP_RDMA ||
@@ -703,6 +704,7 @@ static struct platform_driver * const mtk_drm_drivers[] = {
 	&mtk_disp_ccorr_driver,
 	&mtk_disp_color_driver,
 	&mtk_disp_gamma_driver,
+	&mtk_disp_merge_driver,
 	&mtk_disp_ovl_driver,
 	&mtk_disp_rdma_driver,
 	&mtk_dpi_driver,
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index 3e7d1e6fbe01..a58cebd01d35 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -50,6 +50,7 @@ extern struct platform_driver mtk_disp_aal_driver;
 extern struct platform_driver mtk_disp_ccorr_driver;
 extern struct platform_driver mtk_disp_color_driver;
 extern struct platform_driver mtk_disp_gamma_driver;
+extern struct platform_driver mtk_disp_merge_driver;
 extern struct platform_driver mtk_disp_ovl_driver;
 extern struct platform_driver mtk_disp_rdma_driver;
 extern struct platform_driver mtk_dpi_driver;
-- 
2.18.0


_______________________________________________
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^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 07/10] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
  2022-04-12 10:31 ` jason-jh.lin
  (?)
@ 2022-04-12 10:31   ` jason-jh.lin
  -1 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: fshao, David Airlie, singo.chang, dri-devel, Fabien Parent,
	linux-stm32, roy-cw.yeh, Project_Global_Chrome_Upstream_Group,
	Yongqiang Niu, Rex-BC Chen, devicetree, nancy.lin,
	linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
	linux-kernel, moudy.ho, Maxime Coquelin

1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
2. Add get driver data function to identify which vdosys by io_start.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c |   6 ++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 126 ++++++++++++++++++++++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h   |   6 ++
 3 files changed, 137 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 662e91d9d45f..8ce60371536e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -364,6 +364,10 @@ static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
 	.fifo_size = 5 * SZ_1K,
 };
 
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+	.fifo_size = 1920,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-rdma",
 	  .data = &mt2701_rdma_driver_data},
@@ -373,6 +377,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	  .data = &mt8183_rdma_driver_data},
 	{ .compatible = "mediatek,mt8192-disp-rdma",
 	  .data = &mt8192_rdma_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = &mt8195_rdma_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index f54b650a2ea1..1b5bef25d17b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -4,6 +4,8 @@
  * Author: YT SHEN <yt.shen@mediatek.com>
  */
 
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/component.h>
 #include <linux/iommu.h>
 #include <linux/module.h>
@@ -177,6 +179,19 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
 	DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+	DDP_COMPONENT_OVL0,
+	DDP_COMPONENT_RDMA0,
+	DDP_COMPONENT_COLOR0,
+	DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_AAL0,
+	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_DP_INTF0,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.main_path = mt2701_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -185,6 +200,13 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.shadow_register = true,
 };
 
+static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt2701_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
 	.main_path = mt7623_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
@@ -193,6 +215,13 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
 	.shadow_register = true,
 };
 
+static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt7623_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 	.main_path = mt2712_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
@@ -202,11 +231,25 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 	.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
 };
 
+static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt2712_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
 	.main_path = mt8167_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
 };
 
+static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8167_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.main_path = mt8173_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
@@ -214,6 +257,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8173_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.main_path = mt8183_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
@@ -221,6 +271,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8183_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.main_path = mt8192_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
@@ -228,6 +285,31 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8192_mmsys_driver_data,
+	},
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.io_start = 0x1c01a000,
+	.main_path = mt8195_mtk_ddp_main,
+	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+	.io_start = 0x1c100000,
+};
+
+static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8195_vdosys0_driver_data,
+		&mt8195_vdosys1_driver_data,
+	},
+};
+
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
 	struct mtk_drm_private *private = drm->dev_private;
@@ -445,12 +527,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8183-disp-dither",
 	  .data = (void *)MTK_DISP_DITHER },
+	{ .compatible = "mediatek,mt8195-disp-dsc",
+	  .data = (void *)MTK_DISP_DSC },
 	{ .compatible = "mediatek,mt8167-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
+	{ .compatible = "mediatek,mt8195-disp-merge",
+	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -463,6 +549,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8192-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8173-disp-od",
 	  .data = (void *)MTK_DISP_OD },
 	{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -497,6 +585,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8192-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -533,15 +623,37 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8183_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8192-mmsys",
 	  .data = &mt8192_mmsys_driver_data},
+	{ .compatible = "mediatek,mt8195-mmsys"},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
 
+static int mtk_drm_find_match_data(struct device *dev,
+				   const struct mtk_mmsys_match_data *match_data)
+{
+	int i;
+	struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node);
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (IS_ERR(res)) {
+		dev_err(dev, "failed to get mmsys resource\n");
+		return PTR_ERR(res);
+	}
+
+	for (i = 0; i < match_data->num_drv_data; i++)
+		if (match_data->drv_data[i]->io_start == res->start)
+			return i;
+
+	return -EINVAL;
+}
+
 static int mtk_drm_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *phandle = dev->parent->of_node;
 	const struct of_device_id *of_id;
+	const struct mtk_mmsys_match_data *match_data;
 	struct mtk_drm_private *private;
 	struct device_node *node;
 	struct component_match *match = NULL;
@@ -562,7 +674,19 @@ static int mtk_drm_probe(struct platform_device *pdev)
 	if (!of_id)
 		return -ENODEV;
 
-	private->data = of_id->data;
+	match_data = of_id->data;
+	if (match_data->num_drv_data > 1) {
+		/* This SoC has multiple mmsys channels */
+		ret = mtk_drm_find_match_data(dev, match_data);
+		if (ret < 0) {
+			dev_err(dev, "Couldn't get match driver data\n");
+			return ret;
+		}
+		private->data = match_data->drv_data[ret];
+	} else {
+		dev_dbg(dev, "Using single mmsys channel\n");
+		private->data = match_data->drv_data[0];
+	}
 
 	/* Iterate over sibling DISP function blocks */
 	for_each_child_of_node(phandle->parent, node) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index a58cebd01d35..e1a37ca091f3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -21,6 +21,7 @@ struct drm_property;
 struct regmap;
 
 struct mtk_mmsys_driver_data {
+	const unsigned int io_start;
 	const enum mtk_ddp_comp_id *main_path;
 	unsigned int main_len;
 	const enum mtk_ddp_comp_id *ext_path;
@@ -31,6 +32,11 @@ struct mtk_mmsys_driver_data {
 	bool shadow_register;
 };
 
+struct mtk_mmsys_match_data {
+	unsigned short num_drv_data;
+	const struct mtk_mmsys_driver_data *drv_data[];
+};
+
 struct mtk_drm_private {
 	struct drm_device *drm;
 	struct device *dma_dev;
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 07/10] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: David Airlie, singo.chang, dri-devel, Fabien Parent, linux-stm32,
	roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
	Rex-BC Chen, Philipp Zabel, devicetree, Daniel Vetter, CK Hu,
	nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
2. Add get driver data function to identify which vdosys by io_start.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c |   6 ++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 126 ++++++++++++++++++++++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h   |   6 ++
 3 files changed, 137 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 662e91d9d45f..8ce60371536e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -364,6 +364,10 @@ static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
 	.fifo_size = 5 * SZ_1K,
 };
 
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+	.fifo_size = 1920,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-rdma",
 	  .data = &mt2701_rdma_driver_data},
@@ -373,6 +377,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	  .data = &mt8183_rdma_driver_data},
 	{ .compatible = "mediatek,mt8192-disp-rdma",
 	  .data = &mt8192_rdma_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = &mt8195_rdma_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index f54b650a2ea1..1b5bef25d17b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -4,6 +4,8 @@
  * Author: YT SHEN <yt.shen@mediatek.com>
  */
 
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/component.h>
 #include <linux/iommu.h>
 #include <linux/module.h>
@@ -177,6 +179,19 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
 	DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+	DDP_COMPONENT_OVL0,
+	DDP_COMPONENT_RDMA0,
+	DDP_COMPONENT_COLOR0,
+	DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_AAL0,
+	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_DP_INTF0,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.main_path = mt2701_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -185,6 +200,13 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.shadow_register = true,
 };
 
+static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt2701_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
 	.main_path = mt7623_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
@@ -193,6 +215,13 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
 	.shadow_register = true,
 };
 
+static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt7623_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 	.main_path = mt2712_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
@@ -202,11 +231,25 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 	.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
 };
 
+static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt2712_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
 	.main_path = mt8167_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
 };
 
+static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8167_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.main_path = mt8173_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
@@ -214,6 +257,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8173_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.main_path = mt8183_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
@@ -221,6 +271,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8183_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.main_path = mt8192_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
@@ -228,6 +285,31 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8192_mmsys_driver_data,
+	},
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.io_start = 0x1c01a000,
+	.main_path = mt8195_mtk_ddp_main,
+	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+	.io_start = 0x1c100000,
+};
+
+static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8195_vdosys0_driver_data,
+		&mt8195_vdosys1_driver_data,
+	},
+};
+
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
 	struct mtk_drm_private *private = drm->dev_private;
@@ -445,12 +527,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8183-disp-dither",
 	  .data = (void *)MTK_DISP_DITHER },
+	{ .compatible = "mediatek,mt8195-disp-dsc",
+	  .data = (void *)MTK_DISP_DSC },
 	{ .compatible = "mediatek,mt8167-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
+	{ .compatible = "mediatek,mt8195-disp-merge",
+	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -463,6 +549,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8192-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8173-disp-od",
 	  .data = (void *)MTK_DISP_OD },
 	{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -497,6 +585,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8192-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -533,15 +623,37 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8183_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8192-mmsys",
 	  .data = &mt8192_mmsys_driver_data},
+	{ .compatible = "mediatek,mt8195-mmsys"},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
 
+static int mtk_drm_find_match_data(struct device *dev,
+				   const struct mtk_mmsys_match_data *match_data)
+{
+	int i;
+	struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node);
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (IS_ERR(res)) {
+		dev_err(dev, "failed to get mmsys resource\n");
+		return PTR_ERR(res);
+	}
+
+	for (i = 0; i < match_data->num_drv_data; i++)
+		if (match_data->drv_data[i]->io_start == res->start)
+			return i;
+
+	return -EINVAL;
+}
+
 static int mtk_drm_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *phandle = dev->parent->of_node;
 	const struct of_device_id *of_id;
+	const struct mtk_mmsys_match_data *match_data;
 	struct mtk_drm_private *private;
 	struct device_node *node;
 	struct component_match *match = NULL;
@@ -562,7 +674,19 @@ static int mtk_drm_probe(struct platform_device *pdev)
 	if (!of_id)
 		return -ENODEV;
 
-	private->data = of_id->data;
+	match_data = of_id->data;
+	if (match_data->num_drv_data > 1) {
+		/* This SoC has multiple mmsys channels */
+		ret = mtk_drm_find_match_data(dev, match_data);
+		if (ret < 0) {
+			dev_err(dev, "Couldn't get match driver data\n");
+			return ret;
+		}
+		private->data = match_data->drv_data[ret];
+	} else {
+		dev_dbg(dev, "Using single mmsys channel\n");
+		private->data = match_data->drv_data[0];
+	}
 
 	/* Iterate over sibling DISP function blocks */
 	for_each_child_of_node(phandle->parent, node) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index a58cebd01d35..e1a37ca091f3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -21,6 +21,7 @@ struct drm_property;
 struct regmap;
 
 struct mtk_mmsys_driver_data {
+	const unsigned int io_start;
 	const enum mtk_ddp_comp_id *main_path;
 	unsigned int main_len;
 	const enum mtk_ddp_comp_id *ext_path;
@@ -31,6 +32,11 @@ struct mtk_mmsys_driver_data {
 	bool shadow_register;
 };
 
+struct mtk_mmsys_match_data {
+	unsigned short num_drv_data;
+	const struct mtk_mmsys_driver_data *drv_data[];
+};
+
 struct mtk_drm_private {
 	struct drm_device *drm;
 	struct device *dma_dev;
-- 
2.18.0


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^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 07/10] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu, jason-jh . lin, Rex-BC Chen, Yongqiang Niu,
	hsinyi, fshao, moudy.ho, roy-cw.yeh, nancy.lin, singo.chang,
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

1. Add driver data of mt8195 vdosys0 to mediatek-drm and the sub driver.
2. Add get driver data function to identify which vdosys by io_start.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_disp_rdma.c |   6 ++
 drivers/gpu/drm/mediatek/mtk_drm_drv.c   | 126 ++++++++++++++++++++++-
 drivers/gpu/drm/mediatek/mtk_drm_drv.h   |   6 ++
 3 files changed, 137 insertions(+), 1 deletion(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
index 662e91d9d45f..8ce60371536e 100644
--- a/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
+++ b/drivers/gpu/drm/mediatek/mtk_disp_rdma.c
@@ -364,6 +364,10 @@ static const struct mtk_disp_rdma_data mt8192_rdma_driver_data = {
 	.fifo_size = 5 * SZ_1K,
 };
 
+static const struct mtk_disp_rdma_data mt8195_rdma_driver_data = {
+	.fifo_size = 1920,
+};
+
 static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	{ .compatible = "mediatek,mt2701-disp-rdma",
 	  .data = &mt2701_rdma_driver_data},
@@ -373,6 +377,8 @@ static const struct of_device_id mtk_disp_rdma_driver_dt_match[] = {
 	  .data = &mt8183_rdma_driver_data},
 	{ .compatible = "mediatek,mt8192-disp-rdma",
 	  .data = &mt8192_rdma_driver_data},
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = &mt8195_rdma_driver_data},
 	{},
 };
 MODULE_DEVICE_TABLE(of, mtk_disp_rdma_driver_dt_match);
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index f54b650a2ea1..1b5bef25d17b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -4,6 +4,8 @@
  * Author: YT SHEN <yt.shen@mediatek.com>
  */
 
+#include <linux/clk.h>
+#include <linux/clk-provider.h>
 #include <linux/component.h>
 #include <linux/iommu.h>
 #include <linux/module.h>
@@ -177,6 +179,19 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_ext[] = {
 	DDP_COMPONENT_DPI0,
 };
 
+static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
+	DDP_COMPONENT_OVL0,
+	DDP_COMPONENT_RDMA0,
+	DDP_COMPONENT_COLOR0,
+	DDP_COMPONENT_CCORR,
+	DDP_COMPONENT_AAL0,
+	DDP_COMPONENT_GAMMA,
+	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DSC0,
+	DDP_COMPONENT_MERGE0,
+	DDP_COMPONENT_DP_INTF0,
+};
+
 static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.main_path = mt2701_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2701_mtk_ddp_main),
@@ -185,6 +200,13 @@ static const struct mtk_mmsys_driver_data mt2701_mmsys_driver_data = {
 	.shadow_register = true,
 };
 
+static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt2701_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
 	.main_path = mt7623_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
@@ -193,6 +215,13 @@ static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
 	.shadow_register = true,
 };
 
+static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt7623_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 	.main_path = mt2712_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
@@ -202,11 +231,25 @@ static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
 	.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
 };
 
+static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt2712_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
 	.main_path = mt8167_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
 };
 
+static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8167_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.main_path = mt8173_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
@@ -214,6 +257,13 @@ static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8173_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.main_path = mt8183_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
@@ -221,6 +271,13 @@ static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8183_mmsys_driver_data,
+	},
+};
+
 static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.main_path = mt8192_mtk_ddp_main,
 	.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
@@ -228,6 +285,31 @@ static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
 	.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
 };
 
+static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8192_mmsys_driver_data,
+	},
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
+	.io_start = 0x1c01a000,
+	.main_path = mt8195_mtk_ddp_main,
+	.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
+};
+
+static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
+	.io_start = 0x1c100000,
+};
+
+static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
+	.num_drv_data = 1,
+	.drv_data = {
+		&mt8195_vdosys0_driver_data,
+		&mt8195_vdosys1_driver_data,
+	},
+};
+
 static int mtk_drm_kms_init(struct drm_device *drm)
 {
 	struct mtk_drm_private *private = drm->dev_private;
@@ -445,12 +527,16 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_DITHER },
 	{ .compatible = "mediatek,mt8183-disp-dither",
 	  .data = (void *)MTK_DISP_DITHER },
+	{ .compatible = "mediatek,mt8195-disp-dsc",
+	  .data = (void *)MTK_DISP_DSC },
 	{ .compatible = "mediatek,mt8167-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8173-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
 	{ .compatible = "mediatek,mt8183-disp-gamma",
 	  .data = (void *)MTK_DISP_GAMMA, },
+	{ .compatible = "mediatek,mt8195-disp-merge",
+	  .data = (void *)MTK_DISP_MERGE },
 	{ .compatible = "mediatek,mt2701-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt2712-disp-mutex",
@@ -463,6 +549,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8192-disp-mutex",
 	  .data = (void *)MTK_DISP_MUTEX },
+	{ .compatible = "mediatek,mt8195-disp-mutex",
+	  .data = (void *)MTK_DISP_MUTEX },
 	{ .compatible = "mediatek,mt8173-disp-od",
 	  .data = (void *)MTK_DISP_OD },
 	{ .compatible = "mediatek,mt2701-disp-ovl",
@@ -497,6 +585,8 @@ static const struct of_device_id mtk_ddp_comp_dt_ids[] = {
 	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8192-disp-rdma",
 	  .data = (void *)MTK_DISP_RDMA },
+	{ .compatible = "mediatek,mt8195-disp-rdma",
+	  .data = (void *)MTK_DISP_RDMA },
 	{ .compatible = "mediatek,mt8173-disp-ufoe",
 	  .data = (void *)MTK_DISP_UFOE },
 	{ .compatible = "mediatek,mt8173-disp-wdma",
@@ -533,15 +623,37 @@ static const struct of_device_id mtk_drm_of_ids[] = {
 	  .data = &mt8183_mmsys_driver_data},
 	{ .compatible = "mediatek,mt8192-mmsys",
 	  .data = &mt8192_mmsys_driver_data},
+	{ .compatible = "mediatek,mt8195-mmsys"},
 	{ }
 };
 MODULE_DEVICE_TABLE(of, mtk_drm_of_ids);
 
+static int mtk_drm_find_match_data(struct device *dev,
+				   const struct mtk_mmsys_match_data *match_data)
+{
+	int i;
+	struct platform_device *pdev = of_find_device_by_node(dev->parent->of_node);
+	struct resource *res;
+
+	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
+	if (IS_ERR(res)) {
+		dev_err(dev, "failed to get mmsys resource\n");
+		return PTR_ERR(res);
+	}
+
+	for (i = 0; i < match_data->num_drv_data; i++)
+		if (match_data->drv_data[i]->io_start == res->start)
+			return i;
+
+	return -EINVAL;
+}
+
 static int mtk_drm_probe(struct platform_device *pdev)
 {
 	struct device *dev = &pdev->dev;
 	struct device_node *phandle = dev->parent->of_node;
 	const struct of_device_id *of_id;
+	const struct mtk_mmsys_match_data *match_data;
 	struct mtk_drm_private *private;
 	struct device_node *node;
 	struct component_match *match = NULL;
@@ -562,7 +674,19 @@ static int mtk_drm_probe(struct platform_device *pdev)
 	if (!of_id)
 		return -ENODEV;
 
-	private->data = of_id->data;
+	match_data = of_id->data;
+	if (match_data->num_drv_data > 1) {
+		/* This SoC has multiple mmsys channels */
+		ret = mtk_drm_find_match_data(dev, match_data);
+		if (ret < 0) {
+			dev_err(dev, "Couldn't get match driver data\n");
+			return ret;
+		}
+		private->data = match_data->drv_data[ret];
+	} else {
+		dev_dbg(dev, "Using single mmsys channel\n");
+		private->data = match_data->drv_data[0];
+	}
 
 	/* Iterate over sibling DISP function blocks */
 	for_each_child_of_node(phandle->parent, node) {
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.h b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
index a58cebd01d35..e1a37ca091f3 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.h
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.h
@@ -21,6 +21,7 @@ struct drm_property;
 struct regmap;
 
 struct mtk_mmsys_driver_data {
+	const unsigned int io_start;
 	const enum mtk_ddp_comp_id *main_path;
 	unsigned int main_len;
 	const enum mtk_ddp_comp_id *ext_path;
@@ -31,6 +32,11 @@ struct mtk_mmsys_driver_data {
 	bool shadow_register;
 };
 
+struct mtk_mmsys_match_data {
+	unsigned short num_drv_data;
+	const struct mtk_mmsys_driver_data *drv_data[];
+};
+
 struct mtk_drm_private {
 	struct drm_device *drm;
 	struct device *dma_dev;
-- 
2.18.0


_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 08/10] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
  2022-04-12 10:31 ` jason-jh.lin
  (?)
@ 2022-04-12 10:31   ` jason-jh.lin
  -1 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: fshao, David Airlie, singo.chang, dri-devel, Fabien Parent,
	linux-stm32, roy-cw.yeh, Project_Global_Chrome_Upstream_Group,
	Yongqiang Niu, Rex-BC Chen, devicetree, nancy.lin,
	linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
	linux-kernel, moudy.ho, Maxime Coquelin

The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.

But its header need to keep DDP_COMPONENT_DITHER enum
until drm/mediatek also changed it.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/soc/mediatek/mt8167-mmsys.h    |  2 +-
 drivers/soc/mediatek/mt8183-mmsys.h    |  2 +-
 drivers/soc/mediatek/mt8186-mmsys.h    |  4 ++--
 drivers/soc/mediatek/mt8192-mmsys.h    |  4 ++--
 drivers/soc/mediatek/mt8195-mmsys.h    |  8 ++++----
 drivers/soc/mediatek/mt8365-mmsys.h    |  4 ++--
 drivers/soc/mediatek/mtk-mutex.c       | 10 +++++-----
 include/linux/soc/mediatek/mtk-mmsys.h |  1 +
 8 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
index 2772ef5e3934..f7a35b3656bb 100644
--- a/drivers/soc/mediatek/mt8167-mmsys.h
+++ b/drivers/soc/mediatek/mt8167-mmsys.h
@@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
 		MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
 		MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
 	}, {
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 0c021f4b76d2..ff6be1703469 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
 		MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
 		MT8183_OVL1_2L_MOUT_EN_RDMA1
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
 		MT8183_DITHER0_MOUT_IN_DSI0
 	}, {
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
index c72ccf86ea28..eb1ad9c37a9c 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
 		MT8186_RDMA0_SOUT_TO_COLOR0
 	},
 	{
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
 		MT8186_DITHER0_MOUT_TO_DSI0,
 	},
 	{
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
 		MT8186_DSI0_FROM_DITHER0
 	},
diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
index 6aae0b12b6ff..a016d80b4bc1 100644
--- a/drivers/soc/mediatek/mt8192-mmsys.h
+++ b/drivers/soc/mediatek/mt8192-mmsys.h
@@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
 		MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
 		MT8192_OVL2_2L_MOUT_EN_RDMA4
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
 		MT8192_DITHER0_MOUT_IN_DSI0
 	}, {
@@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
 		MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
 		MT8192_AAL0_SEL_IN_CCORR0
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
 		MT8192_DSI0_SEL_IN_DITHER0
 	}, {
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 13ab0ab64396..abfe94a30248 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -113,7 +113,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
 		MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
 		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
 	}, {
@@ -181,7 +181,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
 		MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
 		MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
 	}, {
@@ -245,11 +245,11 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
 		MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
 		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
 		MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
 		MT8195_SOUT_DISP_DITHER0_TO_DSI0
 	}, {
diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
index 690e3fe2dee0..24129a6c25f8 100644
--- a/drivers/soc/mediatek/mt8365-mmsys.h
+++ b/drivers/soc/mediatek/mt8365-mmsys.h
@@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
 		MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
 	},
 	{
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
 		MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
 	},
 	{
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
 		MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
 	},
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 729ee88035ed..9184684baf1d 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -232,7 +232,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
 	[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
 	[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
-	[DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
+	[DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
 	[DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
 	[DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
 	[DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
@@ -265,7 +265,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
 	[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
-	[DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
 	[DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
 	[DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
 	[DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
@@ -279,7 +279,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
 	[DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
-	[DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
 	[DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
 	[DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
 	[DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
@@ -292,7 +292,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
 	[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
-	[DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
 	[DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
 	[DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
 	[DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
@@ -310,7 +310,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
 	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
-	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
 	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
 	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
 	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index cff5c9adbf46..59117d970daf 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -17,6 +17,7 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_COLOR1,
 	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
 	DDP_COMPONENT_DITHER1,
 	DDP_COMPONENT_DP_INTF0,
 	DDP_COMPONENT_DP_INTF1,
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 08/10] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: David Airlie, singo.chang, dri-devel, Fabien Parent, linux-stm32,
	roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
	Rex-BC Chen, Philipp Zabel, devicetree, Daniel Vetter, CK Hu,
	nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.

But its header need to keep DDP_COMPONENT_DITHER enum
until drm/mediatek also changed it.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/soc/mediatek/mt8167-mmsys.h    |  2 +-
 drivers/soc/mediatek/mt8183-mmsys.h    |  2 +-
 drivers/soc/mediatek/mt8186-mmsys.h    |  4 ++--
 drivers/soc/mediatek/mt8192-mmsys.h    |  4 ++--
 drivers/soc/mediatek/mt8195-mmsys.h    |  8 ++++----
 drivers/soc/mediatek/mt8365-mmsys.h    |  4 ++--
 drivers/soc/mediatek/mtk-mutex.c       | 10 +++++-----
 include/linux/soc/mediatek/mtk-mmsys.h |  1 +
 8 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
index 2772ef5e3934..f7a35b3656bb 100644
--- a/drivers/soc/mediatek/mt8167-mmsys.h
+++ b/drivers/soc/mediatek/mt8167-mmsys.h
@@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
 		MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
 		MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
 	}, {
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 0c021f4b76d2..ff6be1703469 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
 		MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
 		MT8183_OVL1_2L_MOUT_EN_RDMA1
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
 		MT8183_DITHER0_MOUT_IN_DSI0
 	}, {
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
index c72ccf86ea28..eb1ad9c37a9c 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
 		MT8186_RDMA0_SOUT_TO_COLOR0
 	},
 	{
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
 		MT8186_DITHER0_MOUT_TO_DSI0,
 	},
 	{
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
 		MT8186_DSI0_FROM_DITHER0
 	},
diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
index 6aae0b12b6ff..a016d80b4bc1 100644
--- a/drivers/soc/mediatek/mt8192-mmsys.h
+++ b/drivers/soc/mediatek/mt8192-mmsys.h
@@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
 		MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
 		MT8192_OVL2_2L_MOUT_EN_RDMA4
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
 		MT8192_DITHER0_MOUT_IN_DSI0
 	}, {
@@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
 		MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
 		MT8192_AAL0_SEL_IN_CCORR0
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
 		MT8192_DSI0_SEL_IN_DITHER0
 	}, {
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 13ab0ab64396..abfe94a30248 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -113,7 +113,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
 		MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
 		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
 	}, {
@@ -181,7 +181,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
 		MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
 		MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
 	}, {
@@ -245,11 +245,11 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
 		MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
 		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
 		MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
 		MT8195_SOUT_DISP_DITHER0_TO_DSI0
 	}, {
diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
index 690e3fe2dee0..24129a6c25f8 100644
--- a/drivers/soc/mediatek/mt8365-mmsys.h
+++ b/drivers/soc/mediatek/mt8365-mmsys.h
@@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
 		MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
 	},
 	{
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
 		MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
 	},
 	{
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
 		MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
 	},
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 729ee88035ed..9184684baf1d 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -232,7 +232,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
 	[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
 	[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
-	[DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
+	[DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
 	[DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
 	[DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
 	[DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
@@ -265,7 +265,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
 	[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
-	[DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
 	[DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
 	[DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
 	[DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
@@ -279,7 +279,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
 	[DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
-	[DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
 	[DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
 	[DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
 	[DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
@@ -292,7 +292,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
 	[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
-	[DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
 	[DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
 	[DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
 	[DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
@@ -310,7 +310,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
 	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
-	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
 	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
 	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
 	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index cff5c9adbf46..59117d970daf 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -17,6 +17,7 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_COLOR1,
 	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
 	DDP_COMPONENT_DITHER1,
 	DDP_COMPONENT_DP_INTF0,
 	DDP_COMPONENT_DP_INTF1,
-- 
2.18.0


_______________________________________________
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Linux-mediatek@lists.infradead.org
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^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 08/10] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu, jason-jh . lin, Rex-BC Chen, Yongqiang Niu,
	hsinyi, fshao, moudy.ho, roy-cw.yeh, nancy.lin, singo.chang,
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.

But its header need to keep DDP_COMPONENT_DITHER enum
until drm/mediatek also changed it.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/soc/mediatek/mt8167-mmsys.h    |  2 +-
 drivers/soc/mediatek/mt8183-mmsys.h    |  2 +-
 drivers/soc/mediatek/mt8186-mmsys.h    |  4 ++--
 drivers/soc/mediatek/mt8192-mmsys.h    |  4 ++--
 drivers/soc/mediatek/mt8195-mmsys.h    |  8 ++++----
 drivers/soc/mediatek/mt8365-mmsys.h    |  4 ++--
 drivers/soc/mediatek/mtk-mutex.c       | 10 +++++-----
 include/linux/soc/mediatek/mtk-mmsys.h |  1 +
 8 files changed, 18 insertions(+), 17 deletions(-)

diff --git a/drivers/soc/mediatek/mt8167-mmsys.h b/drivers/soc/mediatek/mt8167-mmsys.h
index 2772ef5e3934..f7a35b3656bb 100644
--- a/drivers/soc/mediatek/mt8167-mmsys.h
+++ b/drivers/soc/mediatek/mt8167-mmsys.h
@@ -18,7 +18,7 @@ static const struct mtk_mmsys_routes mt8167_mmsys_routing_table[] = {
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
 		MT8167_DISP_REG_CONFIG_DISP_OVL0_MOUT_EN, OVL0_MOUT_EN_COLOR0,
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_RDMA0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_RDMA0,
 		MT8167_DISP_REG_CONFIG_DISP_DITHER_MOUT_EN, MT8167_DITHER_MOUT_EN_RDMA0
 	}, {
 		DDP_COMPONENT_OVL0, DDP_COMPONENT_COLOR0,
diff --git a/drivers/soc/mediatek/mt8183-mmsys.h b/drivers/soc/mediatek/mt8183-mmsys.h
index 0c021f4b76d2..ff6be1703469 100644
--- a/drivers/soc/mediatek/mt8183-mmsys.h
+++ b/drivers/soc/mediatek/mt8183-mmsys.h
@@ -41,7 +41,7 @@ static const struct mtk_mmsys_routes mmsys_mt8183_routing_table[] = {
 		MT8183_DISP_OVL1_2L_MOUT_EN, MT8183_OVL1_2L_MOUT_EN_RDMA1,
 		MT8183_OVL1_2L_MOUT_EN_RDMA1
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8183_DISP_DITHER0_MOUT_EN, MT8183_DITHER0_MOUT_IN_DSI0,
 		MT8183_DITHER0_MOUT_IN_DSI0
 	}, {
diff --git a/drivers/soc/mediatek/mt8186-mmsys.h b/drivers/soc/mediatek/mt8186-mmsys.h
index c72ccf86ea28..eb1ad9c37a9c 100644
--- a/drivers/soc/mediatek/mt8186-mmsys.h
+++ b/drivers/soc/mediatek/mt8186-mmsys.h
@@ -76,12 +76,12 @@ static const struct mtk_mmsys_routes mmsys_mt8186_routing_table[] = {
 		MT8186_RDMA0_SOUT_TO_COLOR0
 	},
 	{
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8186_DISP_DITHER0_MOUT_EN, MT8186_DITHER0_MOUT_EN_MASK,
 		MT8186_DITHER0_MOUT_TO_DSI0,
 	},
 	{
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8186_DISP_DSI0_SEL_IN, MT8186_DSI0_SEL_IN_MASK,
 		MT8186_DSI0_FROM_DITHER0
 	},
diff --git a/drivers/soc/mediatek/mt8192-mmsys.h b/drivers/soc/mediatek/mt8192-mmsys.h
index 6aae0b12b6ff..a016d80b4bc1 100644
--- a/drivers/soc/mediatek/mt8192-mmsys.h
+++ b/drivers/soc/mediatek/mt8192-mmsys.h
@@ -40,7 +40,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
 		MT8192_DISP_OVL2_2L_MOUT_EN, MT8192_OVL2_2L_MOUT_EN_RDMA4,
 		MT8192_OVL2_2L_MOUT_EN_RDMA4
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8192_DISP_DITHER0_MOUT_EN, MT8192_DITHER0_MOUT_IN_DSI0,
 		MT8192_DITHER0_MOUT_IN_DSI0
 	}, {
@@ -52,7 +52,7 @@ static const struct mtk_mmsys_routes mmsys_mt8192_routing_table[] = {
 		MT8192_DISP_AAL0_SEL_IN, MT8192_AAL0_SEL_IN_CCORR0,
 		MT8192_AAL0_SEL_IN_CCORR0
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8192_DISP_DSI0_SEL_IN, MT8192_DSI0_SEL_IN_DITHER0,
 		MT8192_DSI0_SEL_IN_DITHER0
 	}, {
diff --git a/drivers/soc/mediatek/mt8195-mmsys.h b/drivers/soc/mediatek/mt8195-mmsys.h
index 13ab0ab64396..abfe94a30248 100644
--- a/drivers/soc/mediatek/mt8195-mmsys.h
+++ b/drivers/soc/mediatek/mt8195-mmsys.h
@@ -113,7 +113,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_VPP_MERGE_FROM_MASK,
 		MT8195_SEL_IN_VPP_MERGE_FROM_VDO1_VIRTUAL0
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSC_WRAP0_IN_FROM_MASK,
 		MT8195_SEL_IN_DSC_WRAP0_IN_FROM_DISP_DITHER0
 	}, {
@@ -181,7 +181,7 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
 		MT8195_SEL_IN_DSI0_FROM_DSC_WRAP0_OUT
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DSI0_FROM_MASK,
 		MT8195_SEL_IN_DSI0_FROM_DISP_DITHER0
 	}, {
@@ -245,11 +245,11 @@ static const struct mtk_mmsys_routes mmsys_mt8195_routing_table[] = {
 		MT8195_VDO0_SEL_IN, MT8195_SEL_IN_DISP_WDMA0_FROM_MASK,
 		MT8195_SEL_IN_DISP_WDMA0_FROM_DISP_OVL0
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSC0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSC0,
 		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
 		MT8195_SOUT_DISP_DITHER0_TO_DSC_WRAP0_IN
 	}, {
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8195_VDO0_SEL_OUT, MT8195_SOUT_DISP_DITHER0_TO_MASK,
 		MT8195_SOUT_DISP_DITHER0_TO_DSI0
 	}, {
diff --git a/drivers/soc/mediatek/mt8365-mmsys.h b/drivers/soc/mediatek/mt8365-mmsys.h
index 690e3fe2dee0..24129a6c25f8 100644
--- a/drivers/soc/mediatek/mt8365-mmsys.h
+++ b/drivers/soc/mediatek/mt8365-mmsys.h
@@ -41,12 +41,12 @@ static const struct mtk_mmsys_routes mt8365_mmsys_routing_table[] = {
 		MT8365_DISP_COLOR_SEL_IN_COLOR0,MT8365_DISP_COLOR_SEL_IN_COLOR0
 	},
 	{
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8365_DISP_REG_CONFIG_DISP_DITHER0_MOUT_EN,
 		MT8365_DITHER_MOUT_EN_DSI0, MT8365_DITHER_MOUT_EN_DSI0
 	},
 	{
-		DDP_COMPONENT_DITHER, DDP_COMPONENT_DSI0,
+		DDP_COMPONENT_DITHER0, DDP_COMPONENT_DSI0,
 		MT8365_DISP_REG_CONFIG_DISP_DSI0_SEL_IN,
 		MT8365_DSI0_SEL_IN_DITHER, MT8365_DSI0_SEL_IN_DITHER
 	},
diff --git a/drivers/soc/mediatek/mtk-mutex.c b/drivers/soc/mediatek/mtk-mutex.c
index 729ee88035ed..9184684baf1d 100644
--- a/drivers/soc/mediatek/mtk-mutex.c
+++ b/drivers/soc/mediatek/mtk-mutex.c
@@ -232,7 +232,7 @@ static const unsigned int mt8167_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8167_MUTEX_MOD_DISP_AAL,
 	[DDP_COMPONENT_CCORR] = MT8167_MUTEX_MOD_DISP_CCORR,
 	[DDP_COMPONENT_COLOR0] = MT8167_MUTEX_MOD_DISP_COLOR,
-	[DDP_COMPONENT_DITHER] = MT8167_MUTEX_MOD_DISP_DITHER,
+	[DDP_COMPONENT_DITHER0] = MT8167_MUTEX_MOD_DISP_DITHER,
 	[DDP_COMPONENT_GAMMA] = MT8167_MUTEX_MOD_DISP_GAMMA,
 	[DDP_COMPONENT_OVL0] = MT8167_MUTEX_MOD_DISP_OVL0,
 	[DDP_COMPONENT_OVL1] = MT8167_MUTEX_MOD_DISP_OVL1,
@@ -265,7 +265,7 @@ static const unsigned int mt8183_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8183_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_CCORR] = MT8183_MUTEX_MOD_DISP_CCORR0,
 	[DDP_COMPONENT_COLOR0] = MT8183_MUTEX_MOD_DISP_COLOR0,
-	[DDP_COMPONENT_DITHER] = MT8183_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_DITHER0] = MT8183_MUTEX_MOD_DISP_DITHER0,
 	[DDP_COMPONENT_GAMMA] = MT8183_MUTEX_MOD_DISP_GAMMA0,
 	[DDP_COMPONENT_OVL0] = MT8183_MUTEX_MOD_DISP_OVL0,
 	[DDP_COMPONENT_OVL_2L0] = MT8183_MUTEX_MOD_DISP_OVL0_2L,
@@ -279,7 +279,7 @@ static const unsigned int mt8186_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8186_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_CCORR] = MT8186_MUTEX_MOD_DISP_CCORR0,
 	[DDP_COMPONENT_COLOR0] = MT8186_MUTEX_MOD_DISP_COLOR0,
-	[DDP_COMPONENT_DITHER] = MT8186_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_DITHER0] = MT8186_MUTEX_MOD_DISP_DITHER0,
 	[DDP_COMPONENT_GAMMA] = MT8186_MUTEX_MOD_DISP_GAMMA0,
 	[DDP_COMPONENT_OVL0] = MT8186_MUTEX_MOD_DISP_OVL0,
 	[DDP_COMPONENT_OVL_2L0] = MT8186_MUTEX_MOD_DISP_OVL0_2L,
@@ -292,7 +292,7 @@ static const unsigned int mt8192_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_AAL0] = MT8192_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_CCORR] = MT8192_MUTEX_MOD_DISP_CCORR0,
 	[DDP_COMPONENT_COLOR0] = MT8192_MUTEX_MOD_DISP_COLOR0,
-	[DDP_COMPONENT_DITHER] = MT8192_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_DITHER0] = MT8192_MUTEX_MOD_DISP_DITHER0,
 	[DDP_COMPONENT_GAMMA] = MT8192_MUTEX_MOD_DISP_GAMMA0,
 	[DDP_COMPONENT_POSTMASK0] = MT8192_MUTEX_MOD_DISP_POSTMASK0,
 	[DDP_COMPONENT_OVL0] = MT8192_MUTEX_MOD_DISP_OVL0,
@@ -310,7 +310,7 @@ static const unsigned int mt8195_mutex_mod[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_CCORR] = MT8195_MUTEX_MOD_DISP_CCORR0,
 	[DDP_COMPONENT_AAL0] = MT8195_MUTEX_MOD_DISP_AAL0,
 	[DDP_COMPONENT_GAMMA] = MT8195_MUTEX_MOD_DISP_GAMMA0,
-	[DDP_COMPONENT_DITHER] = MT8195_MUTEX_MOD_DISP_DITHER0,
+	[DDP_COMPONENT_DITHER0] = MT8195_MUTEX_MOD_DISP_DITHER0,
 	[DDP_COMPONENT_MERGE0] = MT8195_MUTEX_MOD_DISP_VPP_MERGE,
 	[DDP_COMPONENT_DSC0] = MT8195_MUTEX_MOD_DISP_DSC_WRAP0_CORE0,
 	[DDP_COMPONENT_DSI0] = MT8195_MUTEX_MOD_DISP_DSI0,
diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index cff5c9adbf46..59117d970daf 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -17,6 +17,7 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_COLOR1,
 	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
 	DDP_COMPONENT_DITHER1,
 	DDP_COMPONENT_DP_INTF0,
 	DDP_COMPONENT_DP_INTF1,
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 09/10] drm/mediatek: add postfix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
  2022-04-12 10:31 ` jason-jh.lin
  (?)
@ 2022-04-12 10:31   ` jason-jh.lin
  -1 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: fshao, David Airlie, singo.chang, dri-devel, Fabien Parent,
	linux-stm32, roy-cw.yeh, Project_Global_Chrome_Upstream_Group,
	Yongqiang Niu, Rex-BC Chen, devicetree, nancy.lin,
	linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
	linux-kernel, moudy.ho, Maxime Coquelin

Because mt8195 vdosys0 has 2 DITHER components,
so the postfix 0 need to be added to DDP_COMPONENT_DITHER.

Then DITHER enum will become:
DDP_COMPONENT_DITHER0 and DDP_COMPONENT_DITHER1.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index f683e768d61b..95722de4986b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -420,7 +420,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_CCORR]		= { MTK_DISP_CCORR,	0, &ddp_ccorr },
 	[DDP_COMPONENT_COLOR0]		= { MTK_DISP_COLOR,	0, &ddp_color },
 	[DDP_COMPONENT_COLOR1]		= { MTK_DISP_COLOR,	1, &ddp_color },
-	[DDP_COMPONENT_DITHER]		= { MTK_DISP_DITHER,	0, &ddp_dither },
+	[DDP_COMPONENT_DITHER0]		= { MTK_DISP_DITHER,	0, &ddp_dither },
 	[DDP_COMPONENT_DPI0]		= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]		= { MTK_DPI,		1, &ddp_dpi },
 	[DDP_COMPONENT_DSC0]		= { MTK_DISP_DSC,	0, &ddp_dsc },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 1b5bef25d17b..8efa6c64d7f1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -118,7 +118,7 @@ static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_RDMA0,
 	DDP_COMPONENT_DSI0,
 };
@@ -150,7 +150,7 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DSI0,
 };
 
@@ -169,7 +169,7 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
 	DDP_COMPONENT_POSTMASK0,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DSI0,
 };
 
@@ -186,7 +186,7 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DSC0,
 	DDP_COMPONENT_MERGE0,
 	DDP_COMPONENT_DP_INTF0,
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 09/10] drm/mediatek: add postfix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: David Airlie, singo.chang, dri-devel, Fabien Parent, linux-stm32,
	roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
	Rex-BC Chen, Philipp Zabel, devicetree, Daniel Vetter, CK Hu,
	nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

Because mt8195 vdosys0 has 2 DITHER components,
so the postfix 0 need to be added to DDP_COMPONENT_DITHER.

Then DITHER enum will become:
DDP_COMPONENT_DITHER0 and DDP_COMPONENT_DITHER1.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index f683e768d61b..95722de4986b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -420,7 +420,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_CCORR]		= { MTK_DISP_CCORR,	0, &ddp_ccorr },
 	[DDP_COMPONENT_COLOR0]		= { MTK_DISP_COLOR,	0, &ddp_color },
 	[DDP_COMPONENT_COLOR1]		= { MTK_DISP_COLOR,	1, &ddp_color },
-	[DDP_COMPONENT_DITHER]		= { MTK_DISP_DITHER,	0, &ddp_dither },
+	[DDP_COMPONENT_DITHER0]		= { MTK_DISP_DITHER,	0, &ddp_dither },
 	[DDP_COMPONENT_DPI0]		= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]		= { MTK_DPI,		1, &ddp_dpi },
 	[DDP_COMPONENT_DSC0]		= { MTK_DISP_DSC,	0, &ddp_dsc },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 1b5bef25d17b..8efa6c64d7f1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -118,7 +118,7 @@ static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_RDMA0,
 	DDP_COMPONENT_DSI0,
 };
@@ -150,7 +150,7 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DSI0,
 };
 
@@ -169,7 +169,7 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
 	DDP_COMPONENT_POSTMASK0,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DSI0,
 };
 
@@ -186,7 +186,7 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DSC0,
 	DDP_COMPONENT_MERGE0,
 	DDP_COMPONENT_DP_INTF0,
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 09/10] drm/mediatek: add postfix 0 to DDP_COMPONENT_DITHER for mt8195 vdosys0
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu, jason-jh . lin, Rex-BC Chen, Yongqiang Niu,
	hsinyi, fshao, moudy.ho, roy-cw.yeh, nancy.lin, singo.chang,
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

Because mt8195 vdosys0 has 2 DITHER components,
so the postfix 0 need to be added to DDP_COMPONENT_DITHER.

Then DITHER enum will become:
DDP_COMPONENT_DITHER0 and DDP_COMPONENT_DITHER1.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c | 2 +-
 drivers/gpu/drm/mediatek/mtk_drm_drv.c      | 8 ++++----
 2 files changed, 5 insertions(+), 5 deletions(-)

diff --git a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
index f683e768d61b..95722de4986b 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_ddp_comp.c
@@ -420,7 +420,7 @@ static const struct mtk_ddp_comp_match mtk_ddp_matches[DDP_COMPONENT_ID_MAX] = {
 	[DDP_COMPONENT_CCORR]		= { MTK_DISP_CCORR,	0, &ddp_ccorr },
 	[DDP_COMPONENT_COLOR0]		= { MTK_DISP_COLOR,	0, &ddp_color },
 	[DDP_COMPONENT_COLOR1]		= { MTK_DISP_COLOR,	1, &ddp_color },
-	[DDP_COMPONENT_DITHER]		= { MTK_DISP_DITHER,	0, &ddp_dither },
+	[DDP_COMPONENT_DITHER0]		= { MTK_DISP_DITHER,	0, &ddp_dither },
 	[DDP_COMPONENT_DPI0]		= { MTK_DPI,		0, &ddp_dpi },
 	[DDP_COMPONENT_DPI1]		= { MTK_DPI,		1, &ddp_dpi },
 	[DDP_COMPONENT_DSC0]		= { MTK_DISP_DSC,	0, &ddp_dsc },
diff --git a/drivers/gpu/drm/mediatek/mtk_drm_drv.c b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
index 1b5bef25d17b..8efa6c64d7f1 100644
--- a/drivers/gpu/drm/mediatek/mtk_drm_drv.c
+++ b/drivers/gpu/drm/mediatek/mtk_drm_drv.c
@@ -118,7 +118,7 @@ static enum mtk_ddp_comp_id mt8167_mtk_ddp_main[] = {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_RDMA0,
 	DDP_COMPONENT_DSI0,
 };
@@ -150,7 +150,7 @@ static const enum mtk_ddp_comp_id mt8183_mtk_ddp_main[] = {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DSI0,
 };
 
@@ -169,7 +169,7 @@ static const enum mtk_ddp_comp_id mt8192_mtk_ddp_main[] = {
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
 	DDP_COMPONENT_POSTMASK0,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DSI0,
 };
 
@@ -186,7 +186,7 @@ static const enum mtk_ddp_comp_id mt8195_mtk_ddp_main[] = {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_AAL0,
 	DDP_COMPONENT_GAMMA,
-	DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DSC0,
 	DDP_COMPONENT_MERGE0,
 	DDP_COMPONENT_DP_INTF0,
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 10/10] soc: mediatek: remove DDP_DOMPONENT_DITHER enum
  2022-04-12 10:31 ` jason-jh.lin
  (?)
@ 2022-04-12 10:31   ` jason-jh.lin
  -1 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: fshao, David Airlie, singo.chang, dri-devel, Fabien Parent,
	linux-stm32, roy-cw.yeh, Project_Global_Chrome_Upstream_Group,
	Yongqiang Niu, Rex-BC Chen, devicetree, nancy.lin,
	linux-mediatek, hsinyi, linux-arm-kernel, jason-jh . lin,
	linux-kernel, moudy.ho, Maxime Coquelin

After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
mmsys header can remove the useless DDP_COMPONENT_DITHER enum.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 59117d970daf..fb719fd1281c 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_COLOR1,
-	DDP_COMPONENT_DITHER,
-	DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DITHER1,
 	DDP_COMPONENT_DP_INTF0,
 	DDP_COMPONENT_DP_INTF1,
-- 
2.18.0


^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 10/10] soc: mediatek: remove DDP_DOMPONENT_DITHER enum
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: David Airlie, singo.chang, dri-devel, Fabien Parent, linux-stm32,
	roy-cw.yeh, Project_Global_Chrome_Upstream_Group, Yongqiang Niu,
	Rex-BC Chen, Philipp Zabel, devicetree, Daniel Vetter, CK Hu,
	nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
mmsys header can remove the useless DDP_COMPONENT_DITHER enum.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 59117d970daf..fb719fd1281c 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_COLOR1,
-	DDP_COMPONENT_DITHER,
-	DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DITHER1,
 	DDP_COMPONENT_DP_INTF0,
 	DDP_COMPONENT_DP_INTF1,
-- 
2.18.0


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* [PATCH v18 10/10] soc: mediatek: remove DDP_DOMPONENT_DITHER enum
@ 2022-04-12 10:31   ` jason-jh.lin
  0 siblings, 0 replies; 70+ messages in thread
From: jason-jh.lin @ 2022-04-12 10:31 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu, jason-jh . lin, Rex-BC Chen, Yongqiang Niu,
	hsinyi, fshao, moudy.ho, roy-cw.yeh, nancy.lin, singo.chang,
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

After mmsys and drm change DITHER enum to DDP_COMPONENT_DITHER0,
mmsys header can remove the useless DDP_COMPONENT_DITHER enum.

Signed-off-by: jason-jh.lin <jason-jh.lin@mediatek.com>
---
 include/linux/soc/mediatek/mtk-mmsys.h | 3 +--
 1 file changed, 1 insertion(+), 2 deletions(-)

diff --git a/include/linux/soc/mediatek/mtk-mmsys.h b/include/linux/soc/mediatek/mtk-mmsys.h
index 59117d970daf..fb719fd1281c 100644
--- a/include/linux/soc/mediatek/mtk-mmsys.h
+++ b/include/linux/soc/mediatek/mtk-mmsys.h
@@ -16,8 +16,7 @@ enum mtk_ddp_comp_id {
 	DDP_COMPONENT_CCORR,
 	DDP_COMPONENT_COLOR0,
 	DDP_COMPONENT_COLOR1,
-	DDP_COMPONENT_DITHER,
-	DDP_COMPONENT_DITHER0 = DDP_COMPONENT_DITHER,
+	DDP_COMPONENT_DITHER0,
 	DDP_COMPONENT_DITHER1,
 	DDP_COMPONENT_DP_INTF0,
 	DDP_COMPONENT_DP_INTF1,
-- 
2.18.0


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply related	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  2022-04-12 10:31   ` jason-jh.lin
                   ` (3 preceding siblings ...)
  (?)
@ 2022-04-13  6:07 ` Dan Carpenter
  -1 siblings, 0 replies; 70+ messages in thread
From: kernel test robot @ 2022-04-13  1:51 UTC (permalink / raw)
  To: kbuild

[-- Attachment #1: Type: text/plain, Size: 8383 bytes --]

CC: kbuild-all(a)lists.01.org
BCC: lkp(a)intel.com
In-Reply-To: <20220412103114.19922-4-jason-jh.lin@mediatek.com>
References: <20220412103114.19922-4-jason-jh.lin@mediatek.com>
TO: "jason-jh.lin" <jason-jh.lin@mediatek.com>
TO: Rob Herring <robh+dt@kernel.org>
TO: Krzysztof Kozlowski <krzk@kernel.org>
TO: Matthias Brugger <matthias.bgg@gmail.com>
TO: "Chun-Kuang Hu" <chunkuang.hu@kernel.org>
TO: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
CC: fshao(a)chromium.org
CC: David Airlie <airlied@linux.ie>
CC: singo.chang(a)mediatek.com
CC: dri-devel(a)lists.freedesktop.org
CC: Fabien Parent <fparent@baylibre.com>
CC: linux-stm32(a)st-md-mailman.stormreply.com
CC: roy-cw.yeh(a)mediatek.com
CC: Project_Global_Chrome_Upstream_Group(a)mediatek.com
CC: Yongqiang Niu <yongqiang.niu@mediatek.com>
CC: "Rex-BC Chen" <rex-bc.chen@mediatek.com>
CC: devicetree(a)vger.kernel.org
CC: nancy.lin(a)mediatek.com
CC: linux-mediatek(a)lists.infradead.org
CC: hsinyi(a)chromium.org
CC: linux-arm-kernel(a)lists.infradead.org
CC: "jason-jh . lin" <jason-jh.lin@mediatek.com>
CC: linux-kernel(a)vger.kernel.org
CC: moudy.ho(a)mediatek.com
CC: Maxime Coquelin <mcoquelin.stm32@gmail.com>

Hi "jason-jh.lin",

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm/drm-next]
[also build test WARNING on robh/for-next krzk/for-next linus/master v5.18-rc2 next-20220412]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
base:   git://anongit.freedesktop.org/drm/drm drm-next
:::::: branch date: 15 hours ago
:::::: commit date: 15 hours ago
config: arc-randconfig-m031-20220411 (https://download.01.org/0day-ci/archive/20220413/202204130935.urqkcDrG-lkp(a)intel.com/config)
compiler: arc-elf-gcc (GCC) 11.2.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

smatch warnings:
drivers/soc/mediatek/mtk-mmsys.c:315 mtk_mmsys_probe() warn: passing zero to 'PTR_ERR'

vim +/PTR_ERR +315 drivers/soc/mediatek/mtk-mmsys.c

f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  280  
13032709e23285 Matthias Brugger       2020-03-25  281  static int mtk_mmsys_probe(struct platform_device *pdev)
13032709e23285 Matthias Brugger       2020-03-25  282  {
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  283  	struct device *dev = &pdev->dev;
13032709e23285 Matthias Brugger       2020-03-25  284  	struct platform_device *clks;
667c769246b01c Enric Balletbo i Serra 2020-03-25  285  	struct platform_device *drm;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  286  	const struct mtk_mmsys_match_data *match_data;
ce15e7faa2fc54 CK Hu                  2021-03-17  287  	struct mtk_mmsys *mmsys;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  288  	struct resource *res;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  289  	int ret;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  290  
ce15e7faa2fc54 CK Hu                  2021-03-17  291  	mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
ce15e7faa2fc54 CK Hu                  2021-03-17  292  	if (!mmsys)
ce15e7faa2fc54 CK Hu                  2021-03-17  293  		return -ENOMEM;
ce15e7faa2fc54 CK Hu                  2021-03-17  294  
ce15e7faa2fc54 CK Hu                  2021-03-17  295  	mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
ce15e7faa2fc54 CK Hu                  2021-03-17  296  	if (IS_ERR(mmsys->regs)) {
ce15e7faa2fc54 CK Hu                  2021-03-17  297  		ret = PTR_ERR(mmsys->regs);
cc6576029aedc7 Enric Balletbo i Serra 2020-10-06  298  		dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  299  		return ret;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  300  	}
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  301  
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  302  	spin_lock_init(&mmsys->lock);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  303  
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  304  	mmsys->rcdev.owner = THIS_MODULE;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  305  	mmsys->rcdev.nr_resets = 32;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  306  	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  307  	mmsys->rcdev.of_node = pdev->dev.of_node;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  308  	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  309  	if (ret) {
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  310  		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  311  		return ret;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  312  	}
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  313  
8cfc54a36d3e79 jason-jh.lin           2022-04-12  314  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8cfc54a36d3e79 jason-jh.lin           2022-04-12 @315  	if (PTR_ERR(res)) {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  316  		dev_err(dev, "Couldn't get mmsys resource\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  317  		return -EINVAL;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  318  	}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  319  	mmsys->io_start = res->start;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  320  
8cfc54a36d3e79 jason-jh.lin           2022-04-12  321  	match_data = of_device_get_match_data(dev);
8cfc54a36d3e79 jason-jh.lin           2022-04-12  322  	if (match_data->num_drv_data > 1) {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  323  		/* This SoC has multiple mmsys channels */
8cfc54a36d3e79 jason-jh.lin           2022-04-12  324  		ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
8cfc54a36d3e79 jason-jh.lin           2022-04-12  325  		if (ret < 0) {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  326  			dev_err(dev, "Couldn't get match driver data\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  327  			return ret;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  328  		}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  329  		mmsys->data = match_data->drv_data[ret];
8cfc54a36d3e79 jason-jh.lin           2022-04-12  330  	} else {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  331  		dev_dbg(dev, "Using single mmsys channel\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  332  		mmsys->data = match_data->drv_data[0];
8cfc54a36d3e79 jason-jh.lin           2022-04-12  333  	}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  334  
ce15e7faa2fc54 CK Hu                  2021-03-17  335  	platform_set_drvdata(pdev, mmsys);
13032709e23285 Matthias Brugger       2020-03-25  336  
ce15e7faa2fc54 CK Hu                  2021-03-17  337  	clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
13032709e23285 Matthias Brugger       2020-03-25  338  					     PLATFORM_DEVID_AUTO, NULL, 0);
13032709e23285 Matthias Brugger       2020-03-25  339  	if (IS_ERR(clks))
13032709e23285 Matthias Brugger       2020-03-25  340  		return PTR_ERR(clks);
13032709e23285 Matthias Brugger       2020-03-25  341  
667c769246b01c Enric Balletbo i Serra 2020-03-25  342  	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
667c769246b01c Enric Balletbo i Serra 2020-03-25  343  					    PLATFORM_DEVID_AUTO, NULL, 0);
ff34e17cf9bce8 Wei Yongjun            2020-05-06  344  	if (IS_ERR(drm)) {
ff34e17cf9bce8 Wei Yongjun            2020-05-06  345  		platform_device_unregister(clks);
667c769246b01c Enric Balletbo i Serra 2020-03-25  346  		return PTR_ERR(drm);
ff34e17cf9bce8 Wei Yongjun            2020-05-06  347  	}
667c769246b01c Enric Balletbo i Serra 2020-03-25  348  
13032709e23285 Matthias Brugger       2020-03-25  349  	return 0;
13032709e23285 Matthias Brugger       2020-03-25  350  }
13032709e23285 Matthias Brugger       2020-03-25  351  

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-13  6:07 ` Dan Carpenter
  0 siblings, 0 replies; 70+ messages in thread
From: Dan Carpenter @ 2022-04-13  6:07 UTC (permalink / raw)
  To: kbuild, jason-jh.lin, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: lkp, kbuild-all, fshao, David Airlie, singo.chang, dri-devel,
	Fabien Parent, linux-stm32, roy-cw.yeh,
	Project_Global_Chrome_Upstream_Group, Yongqiang Niu, Rex-BC Chen,
	devicetree, nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

Hi "jason-jh.lin",

url:    https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: arc-randconfig-m031-20220411 (https://download.01.org/0day-ci/archive/20220413/202204130935.urqkcDrG-lkp@intel.com/config)
compiler: arc-elf-gcc (GCC) 11.2.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

smatch warnings:
drivers/soc/mediatek/mtk-mmsys.c:315 mtk_mmsys_probe() warn: passing zero to 'PTR_ERR'

vim +/PTR_ERR +315 drivers/soc/mediatek/mtk-mmsys.c

13032709e23285 Matthias Brugger       2020-03-25  281  static int mtk_mmsys_probe(struct platform_device *pdev)
13032709e23285 Matthias Brugger       2020-03-25  282  {
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  283  	struct device *dev = &pdev->dev;
13032709e23285 Matthias Brugger       2020-03-25  284  	struct platform_device *clks;
667c769246b01c Enric Balletbo i Serra 2020-03-25  285  	struct platform_device *drm;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  286  	const struct mtk_mmsys_match_data *match_data;
ce15e7faa2fc54 CK Hu                  2021-03-17  287  	struct mtk_mmsys *mmsys;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  288  	struct resource *res;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  289  	int ret;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  290  
ce15e7faa2fc54 CK Hu                  2021-03-17  291  	mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
ce15e7faa2fc54 CK Hu                  2021-03-17  292  	if (!mmsys)
ce15e7faa2fc54 CK Hu                  2021-03-17  293  		return -ENOMEM;
ce15e7faa2fc54 CK Hu                  2021-03-17  294  
ce15e7faa2fc54 CK Hu                  2021-03-17  295  	mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
ce15e7faa2fc54 CK Hu                  2021-03-17  296  	if (IS_ERR(mmsys->regs)) {
ce15e7faa2fc54 CK Hu                  2021-03-17  297  		ret = PTR_ERR(mmsys->regs);
cc6576029aedc7 Enric Balletbo i Serra 2020-10-06  298  		dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  299  		return ret;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  300  	}
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  301  
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  302  	spin_lock_init(&mmsys->lock);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  303  
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  304  	mmsys->rcdev.owner = THIS_MODULE;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  305  	mmsys->rcdev.nr_resets = 32;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  306  	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  307  	mmsys->rcdev.of_node = pdev->dev.of_node;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  308  	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  309  	if (ret) {
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  310  		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  311  		return ret;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  312  	}
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  313  
8cfc54a36d3e79 jason-jh.lin           2022-04-12  314  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8cfc54a36d3e79 jason-jh.lin           2022-04-12 @315  	if (PTR_ERR(res)) {

You probably meant IS_ERR() instead of PTR_ERR().  But actually
platform_get_resource() does not return error pointers, it returns
NULL so the correct check is:

	if (!res) {

8cfc54a36d3e79 jason-jh.lin           2022-04-12  316  		dev_err(dev, "Couldn't get mmsys resource\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  317  		return -EINVAL;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  318  	}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  319  	mmsys->io_start = res->start;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  320  
8cfc54a36d3e79 jason-jh.lin           2022-04-12  321  	match_data = of_device_get_match_data(dev);
8cfc54a36d3e79 jason-jh.lin           2022-04-12  322  	if (match_data->num_drv_data > 1) {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  323  		/* This SoC has multiple mmsys channels */
8cfc54a36d3e79 jason-jh.lin           2022-04-12  324  		ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
8cfc54a36d3e79 jason-jh.lin           2022-04-12  325  		if (ret < 0) {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  326  			dev_err(dev, "Couldn't get match driver data\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  327  			return ret;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  328  		}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  329  		mmsys->data = match_data->drv_data[ret];
8cfc54a36d3e79 jason-jh.lin           2022-04-12  330  	} else {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  331  		dev_dbg(dev, "Using single mmsys channel\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  332  		mmsys->data = match_data->drv_data[0];
8cfc54a36d3e79 jason-jh.lin           2022-04-12  333  	}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  334  
ce15e7faa2fc54 CK Hu                  2021-03-17  335  	platform_set_drvdata(pdev, mmsys);
13032709e23285 Matthias Brugger       2020-03-25  336  
ce15e7faa2fc54 CK Hu                  2021-03-17  337  	clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
13032709e23285 Matthias Brugger       2020-03-25  338  					     PLATFORM_DEVID_AUTO, NULL, 0);
13032709e23285 Matthias Brugger       2020-03-25  339  	if (IS_ERR(clks))
13032709e23285 Matthias Brugger       2020-03-25  340  		return PTR_ERR(clks);
13032709e23285 Matthias Brugger       2020-03-25  341  
667c769246b01c Enric Balletbo i Serra 2020-03-25  342  	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
667c769246b01c Enric Balletbo i Serra 2020-03-25  343  					    PLATFORM_DEVID_AUTO, NULL, 0);
ff34e17cf9bce8 Wei Yongjun            2020-05-06  344  	if (IS_ERR(drm)) {
ff34e17cf9bce8 Wei Yongjun            2020-05-06  345  		platform_device_unregister(clks);
667c769246b01c Enric Balletbo i Serra 2020-03-25  346  		return PTR_ERR(drm);
ff34e17cf9bce8 Wei Yongjun            2020-05-06  347  	}
667c769246b01c Enric Balletbo i Serra 2020-03-25  348  
13032709e23285 Matthias Brugger       2020-03-25  349  	return 0;
13032709e23285 Matthias Brugger       2020-03-25  350  }

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp


^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-13  6:07 ` Dan Carpenter
  0 siblings, 0 replies; 70+ messages in thread
From: Dan Carpenter @ 2022-04-13  6:07 UTC (permalink / raw)
  To: kbuild, jason-jh.lin, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, moudy.ho, kbuild-all, lkp, fshao, David Airlie,
	jason-jh . lin, singo.chang, roy-cw.yeh, dri-devel, linux-kernel,
	Project_Global_Chrome_Upstream_Group, Fabien Parent, nancy.lin,
	linux-mediatek, Maxime Coquelin, Yongqiang Niu, hsinyi,
	Rex-BC Chen, linux-stm32, linux-arm-kernel

Hi "jason-jh.lin",

url:    https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: arc-randconfig-m031-20220411 (https://download.01.org/0day-ci/archive/20220413/202204130935.urqkcDrG-lkp@intel.com/config)
compiler: arc-elf-gcc (GCC) 11.2.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

smatch warnings:
drivers/soc/mediatek/mtk-mmsys.c:315 mtk_mmsys_probe() warn: passing zero to 'PTR_ERR'

vim +/PTR_ERR +315 drivers/soc/mediatek/mtk-mmsys.c

13032709e23285 Matthias Brugger       2020-03-25  281  static int mtk_mmsys_probe(struct platform_device *pdev)
13032709e23285 Matthias Brugger       2020-03-25  282  {
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  283  	struct device *dev = &pdev->dev;
13032709e23285 Matthias Brugger       2020-03-25  284  	struct platform_device *clks;
667c769246b01c Enric Balletbo i Serra 2020-03-25  285  	struct platform_device *drm;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  286  	const struct mtk_mmsys_match_data *match_data;
ce15e7faa2fc54 CK Hu                  2021-03-17  287  	struct mtk_mmsys *mmsys;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  288  	struct resource *res;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  289  	int ret;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  290  
ce15e7faa2fc54 CK Hu                  2021-03-17  291  	mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
ce15e7faa2fc54 CK Hu                  2021-03-17  292  	if (!mmsys)
ce15e7faa2fc54 CK Hu                  2021-03-17  293  		return -ENOMEM;
ce15e7faa2fc54 CK Hu                  2021-03-17  294  
ce15e7faa2fc54 CK Hu                  2021-03-17  295  	mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
ce15e7faa2fc54 CK Hu                  2021-03-17  296  	if (IS_ERR(mmsys->regs)) {
ce15e7faa2fc54 CK Hu                  2021-03-17  297  		ret = PTR_ERR(mmsys->regs);
cc6576029aedc7 Enric Balletbo i Serra 2020-10-06  298  		dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  299  		return ret;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  300  	}
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  301  
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  302  	spin_lock_init(&mmsys->lock);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  303  
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  304  	mmsys->rcdev.owner = THIS_MODULE;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  305  	mmsys->rcdev.nr_resets = 32;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  306  	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  307  	mmsys->rcdev.of_node = pdev->dev.of_node;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  308  	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  309  	if (ret) {
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  310  		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  311  		return ret;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  312  	}
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  313  
8cfc54a36d3e79 jason-jh.lin           2022-04-12  314  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8cfc54a36d3e79 jason-jh.lin           2022-04-12 @315  	if (PTR_ERR(res)) {

You probably meant IS_ERR() instead of PTR_ERR().  But actually
platform_get_resource() does not return error pointers, it returns
NULL so the correct check is:

	if (!res) {

8cfc54a36d3e79 jason-jh.lin           2022-04-12  316  		dev_err(dev, "Couldn't get mmsys resource\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  317  		return -EINVAL;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  318  	}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  319  	mmsys->io_start = res->start;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  320  
8cfc54a36d3e79 jason-jh.lin           2022-04-12  321  	match_data = of_device_get_match_data(dev);
8cfc54a36d3e79 jason-jh.lin           2022-04-12  322  	if (match_data->num_drv_data > 1) {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  323  		/* This SoC has multiple mmsys channels */
8cfc54a36d3e79 jason-jh.lin           2022-04-12  324  		ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
8cfc54a36d3e79 jason-jh.lin           2022-04-12  325  		if (ret < 0) {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  326  			dev_err(dev, "Couldn't get match driver data\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  327  			return ret;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  328  		}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  329  		mmsys->data = match_data->drv_data[ret];
8cfc54a36d3e79 jason-jh.lin           2022-04-12  330  	} else {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  331  		dev_dbg(dev, "Using single mmsys channel\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  332  		mmsys->data = match_data->drv_data[0];
8cfc54a36d3e79 jason-jh.lin           2022-04-12  333  	}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  334  
ce15e7faa2fc54 CK Hu                  2021-03-17  335  	platform_set_drvdata(pdev, mmsys);
13032709e23285 Matthias Brugger       2020-03-25  336  
ce15e7faa2fc54 CK Hu                  2021-03-17  337  	clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
13032709e23285 Matthias Brugger       2020-03-25  338  					     PLATFORM_DEVID_AUTO, NULL, 0);
13032709e23285 Matthias Brugger       2020-03-25  339  	if (IS_ERR(clks))
13032709e23285 Matthias Brugger       2020-03-25  340  		return PTR_ERR(clks);
13032709e23285 Matthias Brugger       2020-03-25  341  
667c769246b01c Enric Balletbo i Serra 2020-03-25  342  	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
667c769246b01c Enric Balletbo i Serra 2020-03-25  343  					    PLATFORM_DEVID_AUTO, NULL, 0);
ff34e17cf9bce8 Wei Yongjun            2020-05-06  344  	if (IS_ERR(drm)) {
ff34e17cf9bce8 Wei Yongjun            2020-05-06  345  		platform_device_unregister(clks);
667c769246b01c Enric Balletbo i Serra 2020-03-25  346  		return PTR_ERR(drm);
ff34e17cf9bce8 Wei Yongjun            2020-05-06  347  	}
667c769246b01c Enric Balletbo i Serra 2020-03-25  348  
13032709e23285 Matthias Brugger       2020-03-25  349  	return 0;
13032709e23285 Matthias Brugger       2020-03-25  350  }

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp


^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-13  6:07 ` Dan Carpenter
  0 siblings, 0 replies; 70+ messages in thread
From: Dan Carpenter @ 2022-04-13  6:07 UTC (permalink / raw)
  To: kbuild, jason-jh.lin, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, moudy.ho, kbuild-all, lkp, Maxime Coquelin,
	David Airlie, jason-jh . lin, singo.chang, roy-cw.yeh, dri-devel,
	linux-kernel, Project_Global_Chrome_Upstream_Group,
	Fabien Parent, nancy.lin, linux-mediatek, Yongqiang Niu, hsinyi,
	Rex-BC Chen, linux-stm32, linux-arm-kernel

Hi "jason-jh.lin",

url:    https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: arc-randconfig-m031-20220411 (https://download.01.org/0day-ci/archive/20220413/202204130935.urqkcDrG-lkp@intel.com/config)
compiler: arc-elf-gcc (GCC) 11.2.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

smatch warnings:
drivers/soc/mediatek/mtk-mmsys.c:315 mtk_mmsys_probe() warn: passing zero to 'PTR_ERR'

vim +/PTR_ERR +315 drivers/soc/mediatek/mtk-mmsys.c

13032709e23285 Matthias Brugger       2020-03-25  281  static int mtk_mmsys_probe(struct platform_device *pdev)
13032709e23285 Matthias Brugger       2020-03-25  282  {
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  283  	struct device *dev = &pdev->dev;
13032709e23285 Matthias Brugger       2020-03-25  284  	struct platform_device *clks;
667c769246b01c Enric Balletbo i Serra 2020-03-25  285  	struct platform_device *drm;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  286  	const struct mtk_mmsys_match_data *match_data;
ce15e7faa2fc54 CK Hu                  2021-03-17  287  	struct mtk_mmsys *mmsys;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  288  	struct resource *res;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  289  	int ret;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  290  
ce15e7faa2fc54 CK Hu                  2021-03-17  291  	mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
ce15e7faa2fc54 CK Hu                  2021-03-17  292  	if (!mmsys)
ce15e7faa2fc54 CK Hu                  2021-03-17  293  		return -ENOMEM;
ce15e7faa2fc54 CK Hu                  2021-03-17  294  
ce15e7faa2fc54 CK Hu                  2021-03-17  295  	mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
ce15e7faa2fc54 CK Hu                  2021-03-17  296  	if (IS_ERR(mmsys->regs)) {
ce15e7faa2fc54 CK Hu                  2021-03-17  297  		ret = PTR_ERR(mmsys->regs);
cc6576029aedc7 Enric Balletbo i Serra 2020-10-06  298  		dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  299  		return ret;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  300  	}
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  301  
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  302  	spin_lock_init(&mmsys->lock);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  303  
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  304  	mmsys->rcdev.owner = THIS_MODULE;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  305  	mmsys->rcdev.nr_resets = 32;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  306  	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  307  	mmsys->rcdev.of_node = pdev->dev.of_node;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  308  	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  309  	if (ret) {
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  310  		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  311  		return ret;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  312  	}
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  313  
8cfc54a36d3e79 jason-jh.lin           2022-04-12  314  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8cfc54a36d3e79 jason-jh.lin           2022-04-12 @315  	if (PTR_ERR(res)) {

You probably meant IS_ERR() instead of PTR_ERR().  But actually
platform_get_resource() does not return error pointers, it returns
NULL so the correct check is:

	if (!res) {

8cfc54a36d3e79 jason-jh.lin           2022-04-12  316  		dev_err(dev, "Couldn't get mmsys resource\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  317  		return -EINVAL;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  318  	}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  319  	mmsys->io_start = res->start;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  320  
8cfc54a36d3e79 jason-jh.lin           2022-04-12  321  	match_data = of_device_get_match_data(dev);
8cfc54a36d3e79 jason-jh.lin           2022-04-12  322  	if (match_data->num_drv_data > 1) {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  323  		/* This SoC has multiple mmsys channels */
8cfc54a36d3e79 jason-jh.lin           2022-04-12  324  		ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
8cfc54a36d3e79 jason-jh.lin           2022-04-12  325  		if (ret < 0) {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  326  			dev_err(dev, "Couldn't get match driver data\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  327  			return ret;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  328  		}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  329  		mmsys->data = match_data->drv_data[ret];
8cfc54a36d3e79 jason-jh.lin           2022-04-12  330  	} else {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  331  		dev_dbg(dev, "Using single mmsys channel\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  332  		mmsys->data = match_data->drv_data[0];
8cfc54a36d3e79 jason-jh.lin           2022-04-12  333  	}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  334  
ce15e7faa2fc54 CK Hu                  2021-03-17  335  	platform_set_drvdata(pdev, mmsys);
13032709e23285 Matthias Brugger       2020-03-25  336  
ce15e7faa2fc54 CK Hu                  2021-03-17  337  	clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
13032709e23285 Matthias Brugger       2020-03-25  338  					     PLATFORM_DEVID_AUTO, NULL, 0);
13032709e23285 Matthias Brugger       2020-03-25  339  	if (IS_ERR(clks))
13032709e23285 Matthias Brugger       2020-03-25  340  		return PTR_ERR(clks);
13032709e23285 Matthias Brugger       2020-03-25  341  
667c769246b01c Enric Balletbo i Serra 2020-03-25  342  	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
667c769246b01c Enric Balletbo i Serra 2020-03-25  343  					    PLATFORM_DEVID_AUTO, NULL, 0);
ff34e17cf9bce8 Wei Yongjun            2020-05-06  344  	if (IS_ERR(drm)) {
ff34e17cf9bce8 Wei Yongjun            2020-05-06  345  		platform_device_unregister(clks);
667c769246b01c Enric Balletbo i Serra 2020-03-25  346  		return PTR_ERR(drm);
ff34e17cf9bce8 Wei Yongjun            2020-05-06  347  	}
667c769246b01c Enric Balletbo i Serra 2020-03-25  348  
13032709e23285 Matthias Brugger       2020-03-25  349  	return 0;
13032709e23285 Matthias Brugger       2020-03-25  350  }

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-13  6:07 ` Dan Carpenter
  0 siblings, 0 replies; 70+ messages in thread
From: Dan Carpenter @ 2022-04-13  6:07 UTC (permalink / raw)
  To: kbuild, jason-jh.lin, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: lkp, kbuild-all, fshao, David Airlie, singo.chang, dri-devel,
	Fabien Parent, linux-stm32, roy-cw.yeh,
	Project_Global_Chrome_Upstream_Group, Yongqiang Niu, Rex-BC Chen,
	devicetree, nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

Hi "jason-jh.lin",

url:    https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: arc-randconfig-m031-20220411 (https://download.01.org/0day-ci/archive/20220413/202204130935.urqkcDrG-lkp@intel.com/config)
compiler: arc-elf-gcc (GCC) 11.2.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

smatch warnings:
drivers/soc/mediatek/mtk-mmsys.c:315 mtk_mmsys_probe() warn: passing zero to 'PTR_ERR'

vim +/PTR_ERR +315 drivers/soc/mediatek/mtk-mmsys.c

13032709e23285 Matthias Brugger       2020-03-25  281  static int mtk_mmsys_probe(struct platform_device *pdev)
13032709e23285 Matthias Brugger       2020-03-25  282  {
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  283  	struct device *dev = &pdev->dev;
13032709e23285 Matthias Brugger       2020-03-25  284  	struct platform_device *clks;
667c769246b01c Enric Balletbo i Serra 2020-03-25  285  	struct platform_device *drm;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  286  	const struct mtk_mmsys_match_data *match_data;
ce15e7faa2fc54 CK Hu                  2021-03-17  287  	struct mtk_mmsys *mmsys;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  288  	struct resource *res;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  289  	int ret;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  290  
ce15e7faa2fc54 CK Hu                  2021-03-17  291  	mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
ce15e7faa2fc54 CK Hu                  2021-03-17  292  	if (!mmsys)
ce15e7faa2fc54 CK Hu                  2021-03-17  293  		return -ENOMEM;
ce15e7faa2fc54 CK Hu                  2021-03-17  294  
ce15e7faa2fc54 CK Hu                  2021-03-17  295  	mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
ce15e7faa2fc54 CK Hu                  2021-03-17  296  	if (IS_ERR(mmsys->regs)) {
ce15e7faa2fc54 CK Hu                  2021-03-17  297  		ret = PTR_ERR(mmsys->regs);
cc6576029aedc7 Enric Balletbo i Serra 2020-10-06  298  		dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  299  		return ret;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  300  	}
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  301  
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  302  	spin_lock_init(&mmsys->lock);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  303  
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  304  	mmsys->rcdev.owner = THIS_MODULE;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  305  	mmsys->rcdev.nr_resets = 32;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  306  	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  307  	mmsys->rcdev.of_node = pdev->dev.of_node;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  308  	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  309  	if (ret) {
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  310  		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  311  		return ret;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  312  	}
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  313  
8cfc54a36d3e79 jason-jh.lin           2022-04-12  314  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8cfc54a36d3e79 jason-jh.lin           2022-04-12 @315  	if (PTR_ERR(res)) {

You probably meant IS_ERR() instead of PTR_ERR().  But actually
platform_get_resource() does not return error pointers, it returns
NULL so the correct check is:

	if (!res) {

8cfc54a36d3e79 jason-jh.lin           2022-04-12  316  		dev_err(dev, "Couldn't get mmsys resource\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  317  		return -EINVAL;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  318  	}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  319  	mmsys->io_start = res->start;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  320  
8cfc54a36d3e79 jason-jh.lin           2022-04-12  321  	match_data = of_device_get_match_data(dev);
8cfc54a36d3e79 jason-jh.lin           2022-04-12  322  	if (match_data->num_drv_data > 1) {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  323  		/* This SoC has multiple mmsys channels */
8cfc54a36d3e79 jason-jh.lin           2022-04-12  324  		ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
8cfc54a36d3e79 jason-jh.lin           2022-04-12  325  		if (ret < 0) {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  326  			dev_err(dev, "Couldn't get match driver data\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  327  			return ret;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  328  		}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  329  		mmsys->data = match_data->drv_data[ret];
8cfc54a36d3e79 jason-jh.lin           2022-04-12  330  	} else {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  331  		dev_dbg(dev, "Using single mmsys channel\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  332  		mmsys->data = match_data->drv_data[0];
8cfc54a36d3e79 jason-jh.lin           2022-04-12  333  	}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  334  
ce15e7faa2fc54 CK Hu                  2021-03-17  335  	platform_set_drvdata(pdev, mmsys);
13032709e23285 Matthias Brugger       2020-03-25  336  
ce15e7faa2fc54 CK Hu                  2021-03-17  337  	clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
13032709e23285 Matthias Brugger       2020-03-25  338  					     PLATFORM_DEVID_AUTO, NULL, 0);
13032709e23285 Matthias Brugger       2020-03-25  339  	if (IS_ERR(clks))
13032709e23285 Matthias Brugger       2020-03-25  340  		return PTR_ERR(clks);
13032709e23285 Matthias Brugger       2020-03-25  341  
667c769246b01c Enric Balletbo i Serra 2020-03-25  342  	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
667c769246b01c Enric Balletbo i Serra 2020-03-25  343  					    PLATFORM_DEVID_AUTO, NULL, 0);
ff34e17cf9bce8 Wei Yongjun            2020-05-06  344  	if (IS_ERR(drm)) {
ff34e17cf9bce8 Wei Yongjun            2020-05-06  345  		platform_device_unregister(clks);
667c769246b01c Enric Balletbo i Serra 2020-03-25  346  		return PTR_ERR(drm);
ff34e17cf9bce8 Wei Yongjun            2020-05-06  347  	}
667c769246b01c Enric Balletbo i Serra 2020-03-25  348  
13032709e23285 Matthias Brugger       2020-03-25  349  	return 0;
13032709e23285 Matthias Brugger       2020-03-25  350  }

-- 
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https://01.org/lkp


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^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-13  6:07 ` Dan Carpenter
  0 siblings, 0 replies; 70+ messages in thread
From: Dan Carpenter @ 2022-04-13  6:07 UTC (permalink / raw)
  To: kbuild-all

[-- Attachment #1: Type: text/plain, Size: 6772 bytes --]

Hi "jason-jh.lin",

url:    https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: arc-randconfig-m031-20220411 (https://download.01.org/0day-ci/archive/20220413/202204130935.urqkcDrG-lkp(a)intel.com/config)
compiler: arc-elf-gcc (GCC) 11.2.0

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
Reported-by: Dan Carpenter <dan.carpenter@oracle.com>

smatch warnings:
drivers/soc/mediatek/mtk-mmsys.c:315 mtk_mmsys_probe() warn: passing zero to 'PTR_ERR'

vim +/PTR_ERR +315 drivers/soc/mediatek/mtk-mmsys.c

13032709e23285 Matthias Brugger       2020-03-25  281  static int mtk_mmsys_probe(struct platform_device *pdev)
13032709e23285 Matthias Brugger       2020-03-25  282  {
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  283  	struct device *dev = &pdev->dev;
13032709e23285 Matthias Brugger       2020-03-25  284  	struct platform_device *clks;
667c769246b01c Enric Balletbo i Serra 2020-03-25  285  	struct platform_device *drm;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  286  	const struct mtk_mmsys_match_data *match_data;
ce15e7faa2fc54 CK Hu                  2021-03-17  287  	struct mtk_mmsys *mmsys;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  288  	struct resource *res;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  289  	int ret;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  290  
ce15e7faa2fc54 CK Hu                  2021-03-17  291  	mmsys = devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
ce15e7faa2fc54 CK Hu                  2021-03-17  292  	if (!mmsys)
ce15e7faa2fc54 CK Hu                  2021-03-17  293  		return -ENOMEM;
ce15e7faa2fc54 CK Hu                  2021-03-17  294  
ce15e7faa2fc54 CK Hu                  2021-03-17  295  	mmsys->regs = devm_platform_ioremap_resource(pdev, 0);
ce15e7faa2fc54 CK Hu                  2021-03-17  296  	if (IS_ERR(mmsys->regs)) {
ce15e7faa2fc54 CK Hu                  2021-03-17  297  		ret = PTR_ERR(mmsys->regs);
cc6576029aedc7 Enric Balletbo i Serra 2020-10-06  298  		dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  299  		return ret;
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  300  	}
2c758e301ed95a Enric Balletbo i Serra 2020-03-25  301  
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  302  	spin_lock_init(&mmsys->lock);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  303  
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  304  	mmsys->rcdev.owner = THIS_MODULE;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  305  	mmsys->rcdev.nr_resets = 32;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  306  	mmsys->rcdev.ops = &mtk_mmsys_reset_ops;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  307  	mmsys->rcdev.of_node = pdev->dev.of_node;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  308  	ret = devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  309  	if (ret) {
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  310  		dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n", ret);
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  311  		return ret;
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  312  	}
f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  313  
8cfc54a36d3e79 jason-jh.lin           2022-04-12  314  	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
8cfc54a36d3e79 jason-jh.lin           2022-04-12 @315  	if (PTR_ERR(res)) {

You probably meant IS_ERR() instead of PTR_ERR().  But actually
platform_get_resource() does not return error pointers, it returns
NULL so the correct check is:

	if (!res) {

8cfc54a36d3e79 jason-jh.lin           2022-04-12  316  		dev_err(dev, "Couldn't get mmsys resource\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  317  		return -EINVAL;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  318  	}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  319  	mmsys->io_start = res->start;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  320  
8cfc54a36d3e79 jason-jh.lin           2022-04-12  321  	match_data = of_device_get_match_data(dev);
8cfc54a36d3e79 jason-jh.lin           2022-04-12  322  	if (match_data->num_drv_data > 1) {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  323  		/* This SoC has multiple mmsys channels */
8cfc54a36d3e79 jason-jh.lin           2022-04-12  324  		ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
8cfc54a36d3e79 jason-jh.lin           2022-04-12  325  		if (ret < 0) {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  326  			dev_err(dev, "Couldn't get match driver data\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  327  			return ret;
8cfc54a36d3e79 jason-jh.lin           2022-04-12  328  		}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  329  		mmsys->data = match_data->drv_data[ret];
8cfc54a36d3e79 jason-jh.lin           2022-04-12  330  	} else {
8cfc54a36d3e79 jason-jh.lin           2022-04-12  331  		dev_dbg(dev, "Using single mmsys channel\n");
8cfc54a36d3e79 jason-jh.lin           2022-04-12  332  		mmsys->data = match_data->drv_data[0];
8cfc54a36d3e79 jason-jh.lin           2022-04-12  333  	}
8cfc54a36d3e79 jason-jh.lin           2022-04-12  334  
ce15e7faa2fc54 CK Hu                  2021-03-17  335  	platform_set_drvdata(pdev, mmsys);
13032709e23285 Matthias Brugger       2020-03-25  336  
ce15e7faa2fc54 CK Hu                  2021-03-17  337  	clks = platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
13032709e23285 Matthias Brugger       2020-03-25  338  					     PLATFORM_DEVID_AUTO, NULL, 0);
13032709e23285 Matthias Brugger       2020-03-25  339  	if (IS_ERR(clks))
13032709e23285 Matthias Brugger       2020-03-25  340  		return PTR_ERR(clks);
13032709e23285 Matthias Brugger       2020-03-25  341  
667c769246b01c Enric Balletbo i Serra 2020-03-25  342  	drm = platform_device_register_data(&pdev->dev, "mediatek-drm",
667c769246b01c Enric Balletbo i Serra 2020-03-25  343  					    PLATFORM_DEVID_AUTO, NULL, 0);
ff34e17cf9bce8 Wei Yongjun            2020-05-06  344  	if (IS_ERR(drm)) {
ff34e17cf9bce8 Wei Yongjun            2020-05-06  345  		platform_device_unregister(clks);
667c769246b01c Enric Balletbo i Serra 2020-03-25  346  		return PTR_ERR(drm);
ff34e17cf9bce8 Wei Yongjun            2020-05-06  347  	}
667c769246b01c Enric Balletbo i Serra 2020-03-25  348  
13032709e23285 Matthias Brugger       2020-03-25  349  	return 0;
13032709e23285 Matthias Brugger       2020-03-25  350  }

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
  2022-04-13  6:07 ` Dan Carpenter
                     ` (2 preceding siblings ...)
  (?)
@ 2022-04-13  8:43   ` Jason-JH Lin
  -1 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-13  8:43 UTC (permalink / raw)
  To: Dan Carpenter, kbuild, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: lkp, kbuild-all, fshao, David Airlie, singo.chang, dri-devel,
	Fabien Parent, linux-stm32, roy-cw.yeh,
	Project_Global_Chrome_Upstream_Group, Yongqiang Niu, Rex-BC Chen,
	devicetree, nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	linux-kernel, moudy.ho, Maxime Coquelin

Hi Dan,

Thanks for the reviews.

On Wed, 2022-04-13 at 09:07 +0300, Dan Carpenter wrote:
> Hi "jason-jh.lin",
> 
> url:    
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359__;!!CTRNKA9wMg0ARbw!wAjdEcyQM5SvYaLtDA1d-7DTP-0V0x2EYmyKkpr3QDeGXEknO3vUGir-oiGEYodb6RAr$
>  
> base:   git://anongit.freedesktop.org/drm/drm drm-next
> config: arc-randconfig-m031-20220411 (
> https://urldefense.com/v3/__https://download.01.org/0day-ci/archive/20220413/202204130935.urqkcDrG-lkp@intel.com/config__;!!CTRNKA9wMg0ARbw!wAjdEcyQM5SvYaLtDA1d-7DTP-0V0x2EYmyKkpr3QDeGXEknO3vUGir-oiGEYvQ-IvSq$
>  )
> compiler: arc-elf-gcc (GCC) 11.2.0
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
> 
> smatch warnings:
> drivers/soc/mediatek/mtk-mmsys.c:315 mtk_mmsys_probe() warn: passing
> zero to 'PTR_ERR'
> 
> vim +/PTR_ERR +315 drivers/soc/mediatek/mtk-mmsys.c
> 
> 13032709e23285 Matthias Brugger       2020-03-25  281  static int
> mtk_mmsys_probe(struct platform_device *pdev)
> 13032709e23285 Matthias Brugger       2020-03-25  282  {
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  283  	struct
> device *dev = &pdev->dev;
> 13032709e23285 Matthias Brugger       2020-03-25  284  	struct
> platform_device *clks;
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  285  	struct
> platform_device *drm;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  286  	const
> struct mtk_mmsys_match_data *match_data;
> ce15e7faa2fc54 CK Hu                  2021-03-17  287  	struct
> mtk_mmsys *mmsys;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  288  	struct
> resource *res;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  289  	int
> ret;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  290  
> ce15e7faa2fc54 CK Hu                  2021-03-17  291  	mmsys =
> devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> ce15e7faa2fc54 CK Hu                  2021-03-17  292  	if
> (!mmsys)
> ce15e7faa2fc54 CK Hu                  2021-03-17  293  		
> return -ENOMEM;
> ce15e7faa2fc54 CK Hu                  2021-03-17  294  
> ce15e7faa2fc54 CK Hu                  2021-03-17  295  	mmsys-
> >regs = devm_platform_ioremap_resource(pdev, 0);
> ce15e7faa2fc54 CK Hu                  2021-03-17  296  	if
> (IS_ERR(mmsys->regs)) {
> ce15e7faa2fc54 CK Hu                  2021-03-17  297  		
> ret = PTR_ERR(mmsys->regs);
> cc6576029aedc7 Enric Balletbo i Serra 2020-10-06  298  		
> dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  299  		
> return ret;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  300  	}
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  301  
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  302  	spin_lo
> ck_init(&mmsys->lock);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  303  
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  304  	mmsys-
> >rcdev.owner = THIS_MODULE;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  305  	mmsys-
> >rcdev.nr_resets = 32;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  306  	mmsys-
> >rcdev.ops = &mtk_mmsys_reset_ops;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  307  	mmsys-
> >rcdev.of_node = pdev->dev.of_node;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  308  	ret =
> devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  309  	if
> (ret) {
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  310  		
> dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n",
> ret);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  311  		
> return ret;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  312  	}
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  313  
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  314  	res =
> platform_get_resource(pdev, IORESOURCE_MEM, 0);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12 @315  	if
> (PTR_ERR(res)) {
> 
> You probably meant IS_ERR() instead of PTR_ERR().  But actually
> platform_get_resource() does not return error pointers, it returns
> NULL so the correct check is:
> 
> 	if (!res) {
> 
Yes, I missed this fix and I will also apply the fix to 
mtk_drm_drv.c:639 in [v18,07/10] of this series.

Thank you!

Regards,
Jason-JH.Lin

> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  316  		
> dev_err(dev, "Couldn't get mmsys resource\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  317  		
> return -EINVAL;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  318  	}
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  319  	mmsys-
> >io_start = res->start;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  320  
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  321  	match_d
> ata = of_device_get_match_data(dev);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  322  	if
> (match_data->num_drv_data > 1) {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  323  		
> /* This SoC has multiple mmsys channels */
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  324  		
> ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  325  		
> if (ret < 0) {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  326  		
> 	dev_err(dev, "Couldn't get match driver data\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  327  		
> 	return ret;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  328  		
> }
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  329  		
> mmsys->data = match_data->drv_data[ret];
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  330  	} else
> {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  331  		
> dev_dbg(dev, "Using single mmsys channel\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  332  		
> mmsys->data = match_data->drv_data[0];
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  333  	}
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  334  
> ce15e7faa2fc54 CK Hu                  2021-03-17  335  	platfor
> m_set_drvdata(pdev, mmsys);
> 13032709e23285 Matthias Brugger       2020-03-25  336  
> ce15e7faa2fc54 CK Hu                  2021-03-17  337  	clks =
> platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> 13032709e23285 Matthias Brugger       2020-03-25  338  		
> 			     PLATFORM_DEVID_AUTO, NULL, 0);
> 13032709e23285 Matthias Brugger       2020-03-25  339  	if
> (IS_ERR(clks))
> 13032709e23285 Matthias Brugger       2020-03-25  340  		
> return PTR_ERR(clks);
> 13032709e23285 Matthias Brugger       2020-03-25  341  
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  342  	drm =
> platform_device_register_data(&pdev->dev, "mediatek-drm",
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  343  		
> 			    PLATFORM_DEVID_AUTO, NULL, 0);
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  344  	if
> (IS_ERR(drm)) {
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  345  		
> platform_device_unregister(clks);
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  346  		
> return PTR_ERR(drm);
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  347  	}
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  348  
> 13032709e23285 Matthias Brugger       2020-03-25  349  	return
> 0;
> 13032709e23285 Matthias Brugger       2020-03-25  350  }
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-13  8:43   ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-13  8:43 UTC (permalink / raw)
  To: Dan Carpenter, kbuild, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, moudy.ho, kbuild-all, lkp, fshao, David Airlie,
	Maxime Coquelin, singo.chang, roy-cw.yeh, dri-devel,
	linux-kernel, Project_Global_Chrome_Upstream_Group,
	Fabien Parent, nancy.lin, linux-mediatek, Yongqiang Niu, hsinyi,
	Rex-BC Chen, linux-stm32, linux-arm-kernel

Hi Dan,

Thanks for the reviews.

On Wed, 2022-04-13 at 09:07 +0300, Dan Carpenter wrote:
> Hi "jason-jh.lin",
> 
> url:    
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359__;!!CTRNKA9wMg0ARbw!wAjdEcyQM5SvYaLtDA1d-7DTP-0V0x2EYmyKkpr3QDeGXEknO3vUGir-oiGEYodb6RAr$
>  
> base:   git://anongit.freedesktop.org/drm/drm drm-next
> config: arc-randconfig-m031-20220411 (
> https://urldefense.com/v3/__https://download.01.org/0day-ci/archive/20220413/202204130935.urqkcDrG-lkp@intel.com/config__;!!CTRNKA9wMg0ARbw!wAjdEcyQM5SvYaLtDA1d-7DTP-0V0x2EYmyKkpr3QDeGXEknO3vUGir-oiGEYvQ-IvSq$
>  )
> compiler: arc-elf-gcc (GCC) 11.2.0
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
> 
> smatch warnings:
> drivers/soc/mediatek/mtk-mmsys.c:315 mtk_mmsys_probe() warn: passing
> zero to 'PTR_ERR'
> 
> vim +/PTR_ERR +315 drivers/soc/mediatek/mtk-mmsys.c
> 
> 13032709e23285 Matthias Brugger       2020-03-25  281  static int
> mtk_mmsys_probe(struct platform_device *pdev)
> 13032709e23285 Matthias Brugger       2020-03-25  282  {
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  283  	struct
> device *dev = &pdev->dev;
> 13032709e23285 Matthias Brugger       2020-03-25  284  	struct
> platform_device *clks;
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  285  	struct
> platform_device *drm;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  286  	const
> struct mtk_mmsys_match_data *match_data;
> ce15e7faa2fc54 CK Hu                  2021-03-17  287  	struct
> mtk_mmsys *mmsys;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  288  	struct
> resource *res;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  289  	int
> ret;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  290  
> ce15e7faa2fc54 CK Hu                  2021-03-17  291  	mmsys =
> devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> ce15e7faa2fc54 CK Hu                  2021-03-17  292  	if
> (!mmsys)
> ce15e7faa2fc54 CK Hu                  2021-03-17  293  		
> return -ENOMEM;
> ce15e7faa2fc54 CK Hu                  2021-03-17  294  
> ce15e7faa2fc54 CK Hu                  2021-03-17  295  	mmsys-
> >regs = devm_platform_ioremap_resource(pdev, 0);
> ce15e7faa2fc54 CK Hu                  2021-03-17  296  	if
> (IS_ERR(mmsys->regs)) {
> ce15e7faa2fc54 CK Hu                  2021-03-17  297  		
> ret = PTR_ERR(mmsys->regs);
> cc6576029aedc7 Enric Balletbo i Serra 2020-10-06  298  		
> dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  299  		
> return ret;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  300  	}
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  301  
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  302  	spin_lo
> ck_init(&mmsys->lock);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  303  
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  304  	mmsys-
> >rcdev.owner = THIS_MODULE;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  305  	mmsys-
> >rcdev.nr_resets = 32;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  306  	mmsys-
> >rcdev.ops = &mtk_mmsys_reset_ops;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  307  	mmsys-
> >rcdev.of_node = pdev->dev.of_node;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  308  	ret =
> devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  309  	if
> (ret) {
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  310  		
> dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n",
> ret);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  311  		
> return ret;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  312  	}
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  313  
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  314  	res =
> platform_get_resource(pdev, IORESOURCE_MEM, 0);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12 @315  	if
> (PTR_ERR(res)) {
> 
> You probably meant IS_ERR() instead of PTR_ERR().  But actually
> platform_get_resource() does not return error pointers, it returns
> NULL so the correct check is:
> 
> 	if (!res) {
> 
Yes, I missed this fix and I will also apply the fix to 
mtk_drm_drv.c:639 in [v18,07/10] of this series.

Thank you!

Regards,
Jason-JH.Lin

> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  316  		
> dev_err(dev, "Couldn't get mmsys resource\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  317  		
> return -EINVAL;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  318  	}
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  319  	mmsys-
> >io_start = res->start;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  320  
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  321  	match_d
> ata = of_device_get_match_data(dev);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  322  	if
> (match_data->num_drv_data > 1) {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  323  		
> /* This SoC has multiple mmsys channels */
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  324  		
> ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  325  		
> if (ret < 0) {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  326  		
> 	dev_err(dev, "Couldn't get match driver data\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  327  		
> 	return ret;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  328  		
> }
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  329  		
> mmsys->data = match_data->drv_data[ret];
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  330  	} else
> {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  331  		
> dev_dbg(dev, "Using single mmsys channel\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  332  		
> mmsys->data = match_data->drv_data[0];
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  333  	}
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  334  
> ce15e7faa2fc54 CK Hu                  2021-03-17  335  	platfor
> m_set_drvdata(pdev, mmsys);
> 13032709e23285 Matthias Brugger       2020-03-25  336  
> ce15e7faa2fc54 CK Hu                  2021-03-17  337  	clks =
> platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> 13032709e23285 Matthias Brugger       2020-03-25  338  		
> 			     PLATFORM_DEVID_AUTO, NULL, 0);
> 13032709e23285 Matthias Brugger       2020-03-25  339  	if
> (IS_ERR(clks))
> 13032709e23285 Matthias Brugger       2020-03-25  340  		
> return PTR_ERR(clks);
> 13032709e23285 Matthias Brugger       2020-03-25  341  
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  342  	drm =
> platform_device_register_data(&pdev->dev, "mediatek-drm",
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  343  		
> 			    PLATFORM_DEVID_AUTO, NULL, 0);
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  344  	if
> (IS_ERR(drm)) {
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  345  		
> platform_device_unregister(clks);
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  346  		
> return PTR_ERR(drm);
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  347  	}
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  348  
> 13032709e23285 Matthias Brugger       2020-03-25  349  	return
> 0;
> 13032709e23285 Matthias Brugger       2020-03-25  350  }
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-13  8:43   ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-13  8:43 UTC (permalink / raw)
  To: Dan Carpenter, kbuild, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, moudy.ho, kbuild-all, lkp, Maxime Coquelin,
	David Airlie, singo.chang, roy-cw.yeh, dri-devel, linux-kernel,
	Project_Global_Chrome_Upstream_Group, Fabien Parent, nancy.lin,
	linux-mediatek, Yongqiang Niu, hsinyi, Rex-BC Chen, linux-stm32,
	linux-arm-kernel

Hi Dan,

Thanks for the reviews.

On Wed, 2022-04-13 at 09:07 +0300, Dan Carpenter wrote:
> Hi "jason-jh.lin",
> 
> url:    
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359__;!!CTRNKA9wMg0ARbw!wAjdEcyQM5SvYaLtDA1d-7DTP-0V0x2EYmyKkpr3QDeGXEknO3vUGir-oiGEYodb6RAr$
>  
> base:   git://anongit.freedesktop.org/drm/drm drm-next
> config: arc-randconfig-m031-20220411 (
> https://urldefense.com/v3/__https://download.01.org/0day-ci/archive/20220413/202204130935.urqkcDrG-lkp@intel.com/config__;!!CTRNKA9wMg0ARbw!wAjdEcyQM5SvYaLtDA1d-7DTP-0V0x2EYmyKkpr3QDeGXEknO3vUGir-oiGEYvQ-IvSq$
>  )
> compiler: arc-elf-gcc (GCC) 11.2.0
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
> 
> smatch warnings:
> drivers/soc/mediatek/mtk-mmsys.c:315 mtk_mmsys_probe() warn: passing
> zero to 'PTR_ERR'
> 
> vim +/PTR_ERR +315 drivers/soc/mediatek/mtk-mmsys.c
> 
> 13032709e23285 Matthias Brugger       2020-03-25  281  static int
> mtk_mmsys_probe(struct platform_device *pdev)
> 13032709e23285 Matthias Brugger       2020-03-25  282  {
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  283  	struct
> device *dev = &pdev->dev;
> 13032709e23285 Matthias Brugger       2020-03-25  284  	struct
> platform_device *clks;
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  285  	struct
> platform_device *drm;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  286  	const
> struct mtk_mmsys_match_data *match_data;
> ce15e7faa2fc54 CK Hu                  2021-03-17  287  	struct
> mtk_mmsys *mmsys;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  288  	struct
> resource *res;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  289  	int
> ret;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  290  
> ce15e7faa2fc54 CK Hu                  2021-03-17  291  	mmsys =
> devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> ce15e7faa2fc54 CK Hu                  2021-03-17  292  	if
> (!mmsys)
> ce15e7faa2fc54 CK Hu                  2021-03-17  293  		
> return -ENOMEM;
> ce15e7faa2fc54 CK Hu                  2021-03-17  294  
> ce15e7faa2fc54 CK Hu                  2021-03-17  295  	mmsys-
> >regs = devm_platform_ioremap_resource(pdev, 0);
> ce15e7faa2fc54 CK Hu                  2021-03-17  296  	if
> (IS_ERR(mmsys->regs)) {
> ce15e7faa2fc54 CK Hu                  2021-03-17  297  		
> ret = PTR_ERR(mmsys->regs);
> cc6576029aedc7 Enric Balletbo i Serra 2020-10-06  298  		
> dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  299  		
> return ret;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  300  	}
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  301  
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  302  	spin_lo
> ck_init(&mmsys->lock);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  303  
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  304  	mmsys-
> >rcdev.owner = THIS_MODULE;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  305  	mmsys-
> >rcdev.nr_resets = 32;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  306  	mmsys-
> >rcdev.ops = &mtk_mmsys_reset_ops;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  307  	mmsys-
> >rcdev.of_node = pdev->dev.of_node;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  308  	ret =
> devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  309  	if
> (ret) {
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  310  		
> dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n",
> ret);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  311  		
> return ret;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  312  	}
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  313  
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  314  	res =
> platform_get_resource(pdev, IORESOURCE_MEM, 0);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12 @315  	if
> (PTR_ERR(res)) {
> 
> You probably meant IS_ERR() instead of PTR_ERR().  But actually
> platform_get_resource() does not return error pointers, it returns
> NULL so the correct check is:
> 
> 	if (!res) {
> 
Yes, I missed this fix and I will also apply the fix to 
mtk_drm_drv.c:639 in [v18,07/10] of this series.

Thank you!

Regards,
Jason-JH.Lin

> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  316  		
> dev_err(dev, "Couldn't get mmsys resource\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  317  		
> return -EINVAL;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  318  	}
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  319  	mmsys-
> >io_start = res->start;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  320  
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  321  	match_d
> ata = of_device_get_match_data(dev);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  322  	if
> (match_data->num_drv_data > 1) {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  323  		
> /* This SoC has multiple mmsys channels */
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  324  		
> ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  325  		
> if (ret < 0) {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  326  		
> 	dev_err(dev, "Couldn't get match driver data\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  327  		
> 	return ret;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  328  		
> }
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  329  		
> mmsys->data = match_data->drv_data[ret];
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  330  	} else
> {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  331  		
> dev_dbg(dev, "Using single mmsys channel\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  332  		
> mmsys->data = match_data->drv_data[0];
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  333  	}
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  334  
> ce15e7faa2fc54 CK Hu                  2021-03-17  335  	platfor
> m_set_drvdata(pdev, mmsys);
> 13032709e23285 Matthias Brugger       2020-03-25  336  
> ce15e7faa2fc54 CK Hu                  2021-03-17  337  	clks =
> platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> 13032709e23285 Matthias Brugger       2020-03-25  338  		
> 			     PLATFORM_DEVID_AUTO, NULL, 0);
> 13032709e23285 Matthias Brugger       2020-03-25  339  	if
> (IS_ERR(clks))
> 13032709e23285 Matthias Brugger       2020-03-25  340  		
> return PTR_ERR(clks);
> 13032709e23285 Matthias Brugger       2020-03-25  341  
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  342  	drm =
> platform_device_register_data(&pdev->dev, "mediatek-drm",
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  343  		
> 			    PLATFORM_DEVID_AUTO, NULL, 0);
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  344  	if
> (IS_ERR(drm)) {
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  345  		
> platform_device_unregister(clks);
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  346  		
> return PTR_ERR(drm);
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  347  	}
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  348  
> 13032709e23285 Matthias Brugger       2020-03-25  349  	return
> 0;
> 13032709e23285 Matthias Brugger       2020-03-25  350  }
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-13  8:43   ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-13  8:43 UTC (permalink / raw)
  To: Dan Carpenter, kbuild, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: lkp, kbuild-all, fshao, David Airlie, singo.chang, dri-devel,
	Fabien Parent, linux-stm32, roy-cw.yeh,
	Project_Global_Chrome_Upstream_Group, Yongqiang Niu, Rex-BC Chen,
	devicetree, nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	linux-kernel, moudy.ho, Maxime Coquelin

Hi Dan,

Thanks for the reviews.

On Wed, 2022-04-13 at 09:07 +0300, Dan Carpenter wrote:
> Hi "jason-jh.lin",
> 
> url:    
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359__;!!CTRNKA9wMg0ARbw!wAjdEcyQM5SvYaLtDA1d-7DTP-0V0x2EYmyKkpr3QDeGXEknO3vUGir-oiGEYodb6RAr$
>  
> base:   git://anongit.freedesktop.org/drm/drm drm-next
> config: arc-randconfig-m031-20220411 (
> https://urldefense.com/v3/__https://download.01.org/0day-ci/archive/20220413/202204130935.urqkcDrG-lkp@intel.com/config__;!!CTRNKA9wMg0ARbw!wAjdEcyQM5SvYaLtDA1d-7DTP-0V0x2EYmyKkpr3QDeGXEknO3vUGir-oiGEYvQ-IvSq$
>  )
> compiler: arc-elf-gcc (GCC) 11.2.0
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
> 
> smatch warnings:
> drivers/soc/mediatek/mtk-mmsys.c:315 mtk_mmsys_probe() warn: passing
> zero to 'PTR_ERR'
> 
> vim +/PTR_ERR +315 drivers/soc/mediatek/mtk-mmsys.c
> 
> 13032709e23285 Matthias Brugger       2020-03-25  281  static int
> mtk_mmsys_probe(struct platform_device *pdev)
> 13032709e23285 Matthias Brugger       2020-03-25  282  {
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  283  	struct
> device *dev = &pdev->dev;
> 13032709e23285 Matthias Brugger       2020-03-25  284  	struct
> platform_device *clks;
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  285  	struct
> platform_device *drm;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  286  	const
> struct mtk_mmsys_match_data *match_data;
> ce15e7faa2fc54 CK Hu                  2021-03-17  287  	struct
> mtk_mmsys *mmsys;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  288  	struct
> resource *res;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  289  	int
> ret;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  290  
> ce15e7faa2fc54 CK Hu                  2021-03-17  291  	mmsys =
> devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> ce15e7faa2fc54 CK Hu                  2021-03-17  292  	if
> (!mmsys)
> ce15e7faa2fc54 CK Hu                  2021-03-17  293  		
> return -ENOMEM;
> ce15e7faa2fc54 CK Hu                  2021-03-17  294  
> ce15e7faa2fc54 CK Hu                  2021-03-17  295  	mmsys-
> >regs = devm_platform_ioremap_resource(pdev, 0);
> ce15e7faa2fc54 CK Hu                  2021-03-17  296  	if
> (IS_ERR(mmsys->regs)) {
> ce15e7faa2fc54 CK Hu                  2021-03-17  297  		
> ret = PTR_ERR(mmsys->regs);
> cc6576029aedc7 Enric Balletbo i Serra 2020-10-06  298  		
> dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  299  		
> return ret;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  300  	}
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  301  
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  302  	spin_lo
> ck_init(&mmsys->lock);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  303  
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  304  	mmsys-
> >rcdev.owner = THIS_MODULE;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  305  	mmsys-
> >rcdev.nr_resets = 32;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  306  	mmsys-
> >rcdev.ops = &mtk_mmsys_reset_ops;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  307  	mmsys-
> >rcdev.of_node = pdev->dev.of_node;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  308  	ret =
> devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  309  	if
> (ret) {
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  310  		
> dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n",
> ret);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  311  		
> return ret;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  312  	}
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  313  
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  314  	res =
> platform_get_resource(pdev, IORESOURCE_MEM, 0);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12 @315  	if
> (PTR_ERR(res)) {
> 
> You probably meant IS_ERR() instead of PTR_ERR().  But actually
> platform_get_resource() does not return error pointers, it returns
> NULL so the correct check is:
> 
> 	if (!res) {
> 
Yes, I missed this fix and I will also apply the fix to 
mtk_drm_drv.c:639 in [v18,07/10] of this series.

Thank you!

Regards,
Jason-JH.Lin

> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  316  		
> dev_err(dev, "Couldn't get mmsys resource\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  317  		
> return -EINVAL;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  318  	}
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  319  	mmsys-
> >io_start = res->start;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  320  
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  321  	match_d
> ata = of_device_get_match_data(dev);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  322  	if
> (match_data->num_drv_data > 1) {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  323  		
> /* This SoC has multiple mmsys channels */
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  324  		
> ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  325  		
> if (ret < 0) {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  326  		
> 	dev_err(dev, "Couldn't get match driver data\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  327  		
> 	return ret;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  328  		
> }
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  329  		
> mmsys->data = match_data->drv_data[ret];
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  330  	} else
> {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  331  		
> dev_dbg(dev, "Using single mmsys channel\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  332  		
> mmsys->data = match_data->drv_data[0];
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  333  	}
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  334  
> ce15e7faa2fc54 CK Hu                  2021-03-17  335  	platfor
> m_set_drvdata(pdev, mmsys);
> 13032709e23285 Matthias Brugger       2020-03-25  336  
> ce15e7faa2fc54 CK Hu                  2021-03-17  337  	clks =
> platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> 13032709e23285 Matthias Brugger       2020-03-25  338  		
> 			     PLATFORM_DEVID_AUTO, NULL, 0);
> 13032709e23285 Matthias Brugger       2020-03-25  339  	if
> (IS_ERR(clks))
> 13032709e23285 Matthias Brugger       2020-03-25  340  		
> return PTR_ERR(clks);
> 13032709e23285 Matthias Brugger       2020-03-25  341  
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  342  	drm =
> platform_device_register_data(&pdev->dev, "mediatek-drm",
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  343  		
> 			    PLATFORM_DEVID_AUTO, NULL, 0);
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  344  	if
> (IS_ERR(drm)) {
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  345  		
> platform_device_unregister(clks);
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  346  		
> return PTR_ERR(drm);
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  347  	}
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  348  
> 13032709e23285 Matthias Brugger       2020-03-25  349  	return
> 0;
> 13032709e23285 Matthias Brugger       2020-03-25  350  }
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0
@ 2022-04-13  8:43   ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-13  8:43 UTC (permalink / raw)
  To: kbuild-all

[-- Attachment #1: Type: text/plain, Size: 7647 bytes --]

Hi Dan,

Thanks for the reviews.

On Wed, 2022-04-13 at 09:07 +0300, Dan Carpenter wrote:
> Hi "jason-jh.lin",
> 
> url:    
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359__;!!CTRNKA9wMg0ARbw!wAjdEcyQM5SvYaLtDA1d-7DTP-0V0x2EYmyKkpr3QDeGXEknO3vUGir-oiGEYodb6RAr$
>  
> base:   git://anongit.freedesktop.org/drm/drm drm-next
> config: arc-randconfig-m031-20220411 (
> https://urldefense.com/v3/__https://download.01.org/0day-ci/archive/20220413/202204130935.urqkcDrG-lkp(a)intel.com/config__;!!CTRNKA9wMg0ARbw!wAjdEcyQM5SvYaLtDA1d-7DTP-0V0x2EYmyKkpr3QDeGXEknO3vUGir-oiGEYvQ-IvSq$
>  )
> compiler: arc-elf-gcc (GCC) 11.2.0
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> Reported-by: Dan Carpenter <dan.carpenter@oracle.com>
> 
> smatch warnings:
> drivers/soc/mediatek/mtk-mmsys.c:315 mtk_mmsys_probe() warn: passing
> zero to 'PTR_ERR'
> 
> vim +/PTR_ERR +315 drivers/soc/mediatek/mtk-mmsys.c
> 
> 13032709e23285 Matthias Brugger       2020-03-25  281  static int
> mtk_mmsys_probe(struct platform_device *pdev)
> 13032709e23285 Matthias Brugger       2020-03-25  282  {
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  283  	struct
> device *dev = &pdev->dev;
> 13032709e23285 Matthias Brugger       2020-03-25  284  	struct
> platform_device *clks;
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  285  	struct
> platform_device *drm;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  286  	const
> struct mtk_mmsys_match_data *match_data;
> ce15e7faa2fc54 CK Hu                  2021-03-17  287  	struct
> mtk_mmsys *mmsys;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  288  	struct
> resource *res;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  289  	int
> ret;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  290  
> ce15e7faa2fc54 CK Hu                  2021-03-17  291  	mmsys =
> devm_kzalloc(dev, sizeof(*mmsys), GFP_KERNEL);
> ce15e7faa2fc54 CK Hu                  2021-03-17  292  	if
> (!mmsys)
> ce15e7faa2fc54 CK Hu                  2021-03-17  293  		
> return -ENOMEM;
> ce15e7faa2fc54 CK Hu                  2021-03-17  294  
> ce15e7faa2fc54 CK Hu                  2021-03-17  295  	mmsys-
> >regs = devm_platform_ioremap_resource(pdev, 0);
> ce15e7faa2fc54 CK Hu                  2021-03-17  296  	if
> (IS_ERR(mmsys->regs)) {
> ce15e7faa2fc54 CK Hu                  2021-03-17  297  		
> ret = PTR_ERR(mmsys->regs);
> cc6576029aedc7 Enric Balletbo i Serra 2020-10-06  298  		
> dev_err(dev, "Failed to ioremap mmsys registers: %d\n", ret);
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  299  		
> return ret;
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  300  	}
> 2c758e301ed95a Enric Balletbo i Serra 2020-03-25  301  
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  302  	spin_lo
> ck_init(&mmsys->lock);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  303  
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  304  	mmsys-
> >rcdev.owner = THIS_MODULE;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  305  	mmsys-
> >rcdev.nr_resets = 32;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  306  	mmsys-
> >rcdev.ops = &mtk_mmsys_reset_ops;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  307  	mmsys-
> >rcdev.of_node = pdev->dev.of_node;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  308  	ret =
> devm_reset_controller_register(&pdev->dev, &mmsys->rcdev);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  309  	if
> (ret) {
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  310  		
> dev_err(&pdev->dev, "Couldn't register mmsys reset controller: %d\n",
> ret);
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  311  		
> return ret;
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  312  	}
> f27ef2856343e2 Enric Balletbo i Serra 2021-09-30  313  
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  314  	res =
> platform_get_resource(pdev, IORESOURCE_MEM, 0);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12 @315  	if
> (PTR_ERR(res)) {
> 
> You probably meant IS_ERR() instead of PTR_ERR().  But actually
> platform_get_resource() does not return error pointers, it returns
> NULL so the correct check is:
> 
> 	if (!res) {
> 
Yes, I missed this fix and I will also apply the fix to 
mtk_drm_drv.c:639 in [v18,07/10] of this series.

Thank you!

Regards,
Jason-JH.Lin

> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  316  		
> dev_err(dev, "Couldn't get mmsys resource\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  317  		
> return -EINVAL;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  318  	}
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  319  	mmsys-
> >io_start = res->start;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  320  
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  321  	match_d
> ata = of_device_get_match_data(dev);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  322  	if
> (match_data->num_drv_data > 1) {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  323  		
> /* This SoC has multiple mmsys channels */
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  324  		
> ret = mtk_mmsys_find_match_drvdata(mmsys, match_data);
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  325  		
> if (ret < 0) {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  326  		
> 	dev_err(dev, "Couldn't get match driver data\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  327  		
> 	return ret;
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  328  		
> }
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  329  		
> mmsys->data = match_data->drv_data[ret];
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  330  	} else
> {
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  331  		
> dev_dbg(dev, "Using single mmsys channel\n");
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  332  		
> mmsys->data = match_data->drv_data[0];
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  333  	}
> 8cfc54a36d3e79 jason-jh.lin           2022-04-12  334  
> ce15e7faa2fc54 CK Hu                  2021-03-17  335  	platfor
> m_set_drvdata(pdev, mmsys);
> 13032709e23285 Matthias Brugger       2020-03-25  336  
> ce15e7faa2fc54 CK Hu                  2021-03-17  337  	clks =
> platform_device_register_data(&pdev->dev, mmsys->data->clk_driver,
> 13032709e23285 Matthias Brugger       2020-03-25  338  		
> 			     PLATFORM_DEVID_AUTO, NULL, 0);
> 13032709e23285 Matthias Brugger       2020-03-25  339  	if
> (IS_ERR(clks))
> 13032709e23285 Matthias Brugger       2020-03-25  340  		
> return PTR_ERR(clks);
> 13032709e23285 Matthias Brugger       2020-03-25  341  
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  342  	drm =
> platform_device_register_data(&pdev->dev, "mediatek-drm",
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  343  		
> 			    PLATFORM_DEVID_AUTO, NULL, 0);
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  344  	if
> (IS_ERR(drm)) {
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  345  		
> platform_device_unregister(clks);
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  346  		
> return PTR_ERR(drm);
> ff34e17cf9bce8 Wei Yongjun            2020-05-06  347  	}
> 667c769246b01c Enric Balletbo i Serra 2020-03-25  348  
> 13032709e23285 Matthias Brugger       2020-03-25  349  	return
> 0;
> 13032709e23285 Matthias Brugger       2020-03-25  350  }
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 02/10] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
  2022-04-12 10:31   ` jason-jh.lin
  (?)
  (?)
@ 2022-04-14  3:11     ` Jason-JH Lin
  -1 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-14  3:11 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu (胡俊光),
	Rex-BC Chen (陳柏辰),
	Yongqiang Niu (牛永强),
	hsinyi, fshao, Moudy Ho (何宗原),
	Roy-CW Yeh (葉中瑋),
	Nancy Lin (林欣螢),
	Singo Chang (張興國),
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

Hello Rob, Krzysztof,

I found the dt-binding patches in this series never appeared in
devicetree-bindings patchwork and trigger the dt-binding check bot.

Do you know the reason for this?
Could you help me with this and let me know what should I do to solve
this problem?

Thanks.

Regards,
Jason-JH.Lin


^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 02/10] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
@ 2022-04-14  3:11     ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-14  3:11 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, Rex-BC Chen (陳柏辰),
	Maxime Coquelin, fshao, David Airlie, linux-kernel,
	Singo Chang (張興國),
	Roy-CW Yeh (葉中瑋),
	dri-devel, Yongqiang Niu (牛永强),
	Project_Global_Chrome_Upstream_Group, Fabien Parent,
	Moudy Ho (何宗原),
	linux-mediatek, hsinyi, Nancy Lin (林欣螢),
	linux-stm32, linux-arm-kernel

Hello Rob, Krzysztof,

I found the dt-binding patches in this series never appeared in
devicetree-bindings patchwork and trigger the dt-binding check bot.

Do you know the reason for this?
Could you help me with this and let me know what should I do to solve
this problem?

Thanks.

Regards,
Jason-JH.Lin


^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 02/10] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
@ 2022-04-14  3:11     ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-14  3:11 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, Rex-BC Chen (陳柏辰),
	Maxime Coquelin, David Airlie, linux-kernel,
	Singo Chang (張興國),
	Roy-CW Yeh (葉中瑋),
	dri-devel, Yongqiang Niu (牛永强),
	Project_Global_Chrome_Upstream_Group, Fabien Parent,
	Moudy Ho (何宗原),
	linux-mediatek, Daniel Vetter, hsinyi,
	CK Hu (胡俊光),
	Philipp Zabel, Nancy Lin (林欣螢),
	linux-stm32, linux-arm-kernel

Hello Rob, Krzysztof,

I found the dt-binding patches in this series never appeared in
devicetree-bindings patchwork and trigger the dt-binding check bot.

Do you know the reason for this?
Could you help me with this and let me know what should I do to solve
this problem?

Thanks.

Regards,
Jason-JH.Lin


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 02/10] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
@ 2022-04-14  3:11     ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-14  3:11 UTC (permalink / raw)
  To: Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu (胡俊光),
	Rex-BC Chen (陳柏辰),
	Yongqiang Niu (牛永强),
	hsinyi, fshao, Moudy Ho (何宗原),
	Roy-CW Yeh (葉中瑋),
	Nancy Lin (林欣螢),
	Singo Chang (張興國),
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

Hello Rob, Krzysztof,

I found the dt-binding patches in this series never appeared in
devicetree-bindings patchwork and trigger the dt-binding check bot.

Do you know the reason for this?
Could you help me with this and let me know what should I do to solve
this problem?

Thanks.

Regards,
Jason-JH.Lin


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 07/10] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
  2022-04-12 10:31   ` jason-jh.lin
  (?)
  (?)
@ 2022-04-14 15:31     ` kernel test robot
  -1 siblings, 0 replies; 70+ messages in thread
From: kernel test robot @ 2022-04-14 15:31 UTC (permalink / raw)
  To: jason-jh.lin, Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: llvm, kbuild-all, fshao, David Airlie, singo.chang, dri-devel,
	Fabien Parent, linux-stm32, roy-cw.yeh,
	Project_Global_Chrome_Upstream_Group, Yongqiang Niu, Rex-BC Chen,
	devicetree, nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

Hi "jason-jh.lin",

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm/drm-next]
[also build test WARNING on robh/for-next krzk/for-next linus/master v5.18-rc2 next-20220414]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: arm64-buildonly-randconfig-r001-20220413 (https://download.01.org/0day-ci/archive/20220414/202204142333.qXgcGMI1-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 6b7e6ea489f6dd45a9b0da9ac20871560917b9b0)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # https://github.com/intel-lab-lkp/linux/commit/7c175317aa80bbc885609a730214448147a46b47
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
        git checkout 7c175317aa80bbc885609a730214448147a46b47
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/mediatek/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/mediatek/mtk_drm_drv.c:707:15: warning: cast to smaller integer type 'enum mtk_ddp_comp_type' from 'const void *' [-Wvoid-pointer-to-enum-cast]
                   comp_type = (enum mtk_ddp_comp_type)of_id->data;
                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:203:42: warning: unused variable 'mt2701_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:218:42: warning: unused variable 'mt7623_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:234:42: warning: unused variable 'mt2712_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:246:42: warning: unused variable 'mt8167_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:260:42: warning: unused variable 'mt8173_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:274:42: warning: unused variable 'mt8183_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:288:42: warning: unused variable 'mt8192_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:305:42: warning: unused variable 'mt8195_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
                                            ^
   9 warnings generated.


vim +/mt2701_mmsys_match_data +203 drivers/gpu/drm/mediatek/mtk_drm_drv.c

   202	
 > 203	static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
   204		.num_drv_data = 1,
   205		.drv_data = {
   206			&mt2701_mmsys_driver_data,
   207		},
   208	};
   209	
   210	static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
   211		.main_path = mt7623_mtk_ddp_main,
   212		.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
   213		.ext_path = mt7623_mtk_ddp_ext,
   214		.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
   215		.shadow_register = true,
   216	};
   217	
 > 218	static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
   219		.num_drv_data = 1,
   220		.drv_data = {
   221			&mt7623_mmsys_driver_data,
   222		},
   223	};
   224	
   225	static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
   226		.main_path = mt2712_mtk_ddp_main,
   227		.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
   228		.ext_path = mt2712_mtk_ddp_ext,
   229		.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
   230		.third_path = mt2712_mtk_ddp_third,
   231		.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
   232	};
   233	
 > 234	static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
   235		.num_drv_data = 1,
   236		.drv_data = {
   237			&mt2712_mmsys_driver_data,
   238		},
   239	};
   240	
   241	static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
   242		.main_path = mt8167_mtk_ddp_main,
   243		.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
   244	};
   245	
 > 246	static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
   247		.num_drv_data = 1,
   248		.drv_data = {
   249			&mt8167_mmsys_driver_data,
   250		},
   251	};
   252	
   253	static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
   254		.main_path = mt8173_mtk_ddp_main,
   255		.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
   256		.ext_path = mt8173_mtk_ddp_ext,
   257		.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
   258	};
   259	
 > 260	static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
   261		.num_drv_data = 1,
   262		.drv_data = {
   263			&mt8173_mmsys_driver_data,
   264		},
   265	};
   266	
   267	static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
   268		.main_path = mt8183_mtk_ddp_main,
   269		.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
   270		.ext_path = mt8183_mtk_ddp_ext,
   271		.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
   272	};
   273	
 > 274	static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
   275		.num_drv_data = 1,
   276		.drv_data = {
   277			&mt8183_mmsys_driver_data,
   278		},
   279	};
   280	
   281	static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
   282		.main_path = mt8192_mtk_ddp_main,
   283		.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
   284		.ext_path = mt8192_mtk_ddp_ext,
   285		.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
   286	};
   287	
 > 288	static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
   289		.num_drv_data = 1,
   290		.drv_data = {
   291			&mt8192_mmsys_driver_data,
   292		},
   293	};
   294	
   295	static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
   296		.io_start = 0x1c01a000,
   297		.main_path = mt8195_mtk_ddp_main,
   298		.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
   299	};
   300	
   301	static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
   302		.io_start = 0x1c100000,
   303	};
   304	
 > 305	static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
   306		.num_drv_data = 1,
   307		.drv_data = {
   308			&mt8195_vdosys0_driver_data,
   309			&mt8195_vdosys1_driver_data,
   310		},
   311	};
   312	

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 07/10] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-14 15:31     ` kernel test robot
  0 siblings, 0 replies; 70+ messages in thread
From: kernel test robot @ 2022-04-14 15:31 UTC (permalink / raw)
  To: jason-jh.lin, Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, moudy.ho, kbuild-all, Maxime Coquelin, David Airlie,
	jason-jh . lin, singo.chang, llvm, roy-cw.yeh, dri-devel,
	linux-kernel, Project_Global_Chrome_Upstream_Group,
	Fabien Parent, nancy.lin, linux-mediatek, Yongqiang Niu, hsinyi,
	Rex-BC Chen, linux-stm32, linux-arm-kernel

Hi "jason-jh.lin",

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm/drm-next]
[also build test WARNING on robh/for-next krzk/for-next linus/master v5.18-rc2 next-20220414]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: arm64-buildonly-randconfig-r001-20220413 (https://download.01.org/0day-ci/archive/20220414/202204142333.qXgcGMI1-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 6b7e6ea489f6dd45a9b0da9ac20871560917b9b0)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # https://github.com/intel-lab-lkp/linux/commit/7c175317aa80bbc885609a730214448147a46b47
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
        git checkout 7c175317aa80bbc885609a730214448147a46b47
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/mediatek/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/mediatek/mtk_drm_drv.c:707:15: warning: cast to smaller integer type 'enum mtk_ddp_comp_type' from 'const void *' [-Wvoid-pointer-to-enum-cast]
                   comp_type = (enum mtk_ddp_comp_type)of_id->data;
                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:203:42: warning: unused variable 'mt2701_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:218:42: warning: unused variable 'mt7623_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:234:42: warning: unused variable 'mt2712_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:246:42: warning: unused variable 'mt8167_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:260:42: warning: unused variable 'mt8173_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:274:42: warning: unused variable 'mt8183_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:288:42: warning: unused variable 'mt8192_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:305:42: warning: unused variable 'mt8195_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
                                            ^
   9 warnings generated.


vim +/mt2701_mmsys_match_data +203 drivers/gpu/drm/mediatek/mtk_drm_drv.c

   202	
 > 203	static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
   204		.num_drv_data = 1,
   205		.drv_data = {
   206			&mt2701_mmsys_driver_data,
   207		},
   208	};
   209	
   210	static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
   211		.main_path = mt7623_mtk_ddp_main,
   212		.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
   213		.ext_path = mt7623_mtk_ddp_ext,
   214		.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
   215		.shadow_register = true,
   216	};
   217	
 > 218	static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
   219		.num_drv_data = 1,
   220		.drv_data = {
   221			&mt7623_mmsys_driver_data,
   222		},
   223	};
   224	
   225	static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
   226		.main_path = mt2712_mtk_ddp_main,
   227		.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
   228		.ext_path = mt2712_mtk_ddp_ext,
   229		.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
   230		.third_path = mt2712_mtk_ddp_third,
   231		.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
   232	};
   233	
 > 234	static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
   235		.num_drv_data = 1,
   236		.drv_data = {
   237			&mt2712_mmsys_driver_data,
   238		},
   239	};
   240	
   241	static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
   242		.main_path = mt8167_mtk_ddp_main,
   243		.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
   244	};
   245	
 > 246	static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
   247		.num_drv_data = 1,
   248		.drv_data = {
   249			&mt8167_mmsys_driver_data,
   250		},
   251	};
   252	
   253	static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
   254		.main_path = mt8173_mtk_ddp_main,
   255		.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
   256		.ext_path = mt8173_mtk_ddp_ext,
   257		.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
   258	};
   259	
 > 260	static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
   261		.num_drv_data = 1,
   262		.drv_data = {
   263			&mt8173_mmsys_driver_data,
   264		},
   265	};
   266	
   267	static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
   268		.main_path = mt8183_mtk_ddp_main,
   269		.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
   270		.ext_path = mt8183_mtk_ddp_ext,
   271		.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
   272	};
   273	
 > 274	static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
   275		.num_drv_data = 1,
   276		.drv_data = {
   277			&mt8183_mmsys_driver_data,
   278		},
   279	};
   280	
   281	static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
   282		.main_path = mt8192_mtk_ddp_main,
   283		.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
   284		.ext_path = mt8192_mtk_ddp_ext,
   285		.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
   286	};
   287	
 > 288	static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
   289		.num_drv_data = 1,
   290		.drv_data = {
   291			&mt8192_mmsys_driver_data,
   292		},
   293	};
   294	
   295	static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
   296		.io_start = 0x1c01a000,
   297		.main_path = mt8195_mtk_ddp_main,
   298		.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
   299	};
   300	
   301	static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
   302		.io_start = 0x1c100000,
   303	};
   304	
 > 305	static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
   306		.num_drv_data = 1,
   307		.drv_data = {
   308			&mt8195_vdosys0_driver_data,
   309			&mt8195_vdosys1_driver_data,
   310		},
   311	};
   312	

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 07/10] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-14 15:31     ` kernel test robot
  0 siblings, 0 replies; 70+ messages in thread
From: kernel test robot @ 2022-04-14 15:31 UTC (permalink / raw)
  To: jason-jh.lin, Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, moudy.ho, kbuild-all, Maxime Coquelin, fshao,
	David Airlie, jason-jh . lin, singo.chang, llvm, roy-cw.yeh,
	dri-devel, linux-kernel, Project_Global_Chrome_Upstream_Group,
	Fabien Parent, nancy.lin, linux-mediatek, Yongqiang Niu, hsinyi,
	Rex-BC Chen, linux-stm32, linux-arm-kernel

Hi "jason-jh.lin",

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm/drm-next]
[also build test WARNING on robh/for-next krzk/for-next linus/master v5.18-rc2 next-20220414]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: arm64-buildonly-randconfig-r001-20220413 (https://download.01.org/0day-ci/archive/20220414/202204142333.qXgcGMI1-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 6b7e6ea489f6dd45a9b0da9ac20871560917b9b0)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # https://github.com/intel-lab-lkp/linux/commit/7c175317aa80bbc885609a730214448147a46b47
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
        git checkout 7c175317aa80bbc885609a730214448147a46b47
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/mediatek/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/mediatek/mtk_drm_drv.c:707:15: warning: cast to smaller integer type 'enum mtk_ddp_comp_type' from 'const void *' [-Wvoid-pointer-to-enum-cast]
                   comp_type = (enum mtk_ddp_comp_type)of_id->data;
                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:203:42: warning: unused variable 'mt2701_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:218:42: warning: unused variable 'mt7623_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:234:42: warning: unused variable 'mt2712_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:246:42: warning: unused variable 'mt8167_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:260:42: warning: unused variable 'mt8173_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:274:42: warning: unused variable 'mt8183_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:288:42: warning: unused variable 'mt8192_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:305:42: warning: unused variable 'mt8195_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
                                            ^
   9 warnings generated.


vim +/mt2701_mmsys_match_data +203 drivers/gpu/drm/mediatek/mtk_drm_drv.c

   202	
 > 203	static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
   204		.num_drv_data = 1,
   205		.drv_data = {
   206			&mt2701_mmsys_driver_data,
   207		},
   208	};
   209	
   210	static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
   211		.main_path = mt7623_mtk_ddp_main,
   212		.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
   213		.ext_path = mt7623_mtk_ddp_ext,
   214		.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
   215		.shadow_register = true,
   216	};
   217	
 > 218	static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
   219		.num_drv_data = 1,
   220		.drv_data = {
   221			&mt7623_mmsys_driver_data,
   222		},
   223	};
   224	
   225	static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
   226		.main_path = mt2712_mtk_ddp_main,
   227		.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
   228		.ext_path = mt2712_mtk_ddp_ext,
   229		.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
   230		.third_path = mt2712_mtk_ddp_third,
   231		.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
   232	};
   233	
 > 234	static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
   235		.num_drv_data = 1,
   236		.drv_data = {
   237			&mt2712_mmsys_driver_data,
   238		},
   239	};
   240	
   241	static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
   242		.main_path = mt8167_mtk_ddp_main,
   243		.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
   244	};
   245	
 > 246	static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
   247		.num_drv_data = 1,
   248		.drv_data = {
   249			&mt8167_mmsys_driver_data,
   250		},
   251	};
   252	
   253	static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
   254		.main_path = mt8173_mtk_ddp_main,
   255		.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
   256		.ext_path = mt8173_mtk_ddp_ext,
   257		.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
   258	};
   259	
 > 260	static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
   261		.num_drv_data = 1,
   262		.drv_data = {
   263			&mt8173_mmsys_driver_data,
   264		},
   265	};
   266	
   267	static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
   268		.main_path = mt8183_mtk_ddp_main,
   269		.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
   270		.ext_path = mt8183_mtk_ddp_ext,
   271		.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
   272	};
   273	
 > 274	static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
   275		.num_drv_data = 1,
   276		.drv_data = {
   277			&mt8183_mmsys_driver_data,
   278		},
   279	};
   280	
   281	static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
   282		.main_path = mt8192_mtk_ddp_main,
   283		.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
   284		.ext_path = mt8192_mtk_ddp_ext,
   285		.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
   286	};
   287	
 > 288	static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
   289		.num_drv_data = 1,
   290		.drv_data = {
   291			&mt8192_mmsys_driver_data,
   292		},
   293	};
   294	
   295	static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
   296		.io_start = 0x1c01a000,
   297		.main_path = mt8195_mtk_ddp_main,
   298		.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
   299	};
   300	
   301	static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
   302		.io_start = 0x1c100000,
   303	};
   304	
 > 305	static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
   306		.num_drv_data = 1,
   307		.drv_data = {
   308			&mt8195_vdosys0_driver_data,
   309			&mt8195_vdosys1_driver_data,
   310		},
   311	};
   312	

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 07/10] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-14 15:31     ` kernel test robot
  0 siblings, 0 replies; 70+ messages in thread
From: kernel test robot @ 2022-04-14 15:31 UTC (permalink / raw)
  To: jason-jh.lin, Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: llvm, kbuild-all, fshao, David Airlie, singo.chang, dri-devel,
	Fabien Parent, linux-stm32, roy-cw.yeh,
	Project_Global_Chrome_Upstream_Group, Yongqiang Niu, Rex-BC Chen,
	devicetree, nancy.lin, linux-mediatek, hsinyi, linux-arm-kernel,
	jason-jh . lin, linux-kernel, moudy.ho, Maxime Coquelin

Hi "jason-jh.lin",

Thank you for the patch! Perhaps something to improve:

[auto build test WARNING on drm/drm-next]
[also build test WARNING on robh/for-next krzk/for-next linus/master v5.18-rc2 next-20220414]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]

url:    https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
base:   git://anongit.freedesktop.org/drm/drm drm-next
config: arm64-buildonly-randconfig-r001-20220413 (https://download.01.org/0day-ci/archive/20220414/202204142333.qXgcGMI1-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 6b7e6ea489f6dd45a9b0da9ac20871560917b9b0)
reproduce (this is a W=1 build):
        wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
        chmod +x ~/bin/make.cross
        # install arm64 cross compiling tool for clang build
        # apt-get install binutils-aarch64-linux-gnu
        # https://github.com/intel-lab-lkp/linux/commit/7c175317aa80bbc885609a730214448147a46b47
        git remote add linux-review https://github.com/intel-lab-lkp/linux
        git fetch --no-tags linux-review jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
        git checkout 7c175317aa80bbc885609a730214448147a46b47
        # save the config file to linux build tree
        mkdir build_dir
        COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/mediatek/

If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>

All warnings (new ones prefixed by >>):

   drivers/gpu/drm/mediatek/mtk_drm_drv.c:707:15: warning: cast to smaller integer type 'enum mtk_ddp_comp_type' from 'const void *' [-Wvoid-pointer-to-enum-cast]
                   comp_type = (enum mtk_ddp_comp_type)of_id->data;
                               ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:203:42: warning: unused variable 'mt2701_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:218:42: warning: unused variable 'mt7623_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:234:42: warning: unused variable 'mt2712_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:246:42: warning: unused variable 'mt8167_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:260:42: warning: unused variable 'mt8173_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:274:42: warning: unused variable 'mt8183_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:288:42: warning: unused variable 'mt8192_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
                                            ^
>> drivers/gpu/drm/mediatek/mtk_drm_drv.c:305:42: warning: unused variable 'mt8195_mmsys_match_data' [-Wunused-const-variable]
   static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
                                            ^
   9 warnings generated.


vim +/mt2701_mmsys_match_data +203 drivers/gpu/drm/mediatek/mtk_drm_drv.c

   202	
 > 203	static const struct mtk_mmsys_match_data mt2701_mmsys_match_data = {
   204		.num_drv_data = 1,
   205		.drv_data = {
   206			&mt2701_mmsys_driver_data,
   207		},
   208	};
   209	
   210	static const struct mtk_mmsys_driver_data mt7623_mmsys_driver_data = {
   211		.main_path = mt7623_mtk_ddp_main,
   212		.main_len = ARRAY_SIZE(mt7623_mtk_ddp_main),
   213		.ext_path = mt7623_mtk_ddp_ext,
   214		.ext_len = ARRAY_SIZE(mt7623_mtk_ddp_ext),
   215		.shadow_register = true,
   216	};
   217	
 > 218	static const struct mtk_mmsys_match_data mt7623_mmsys_match_data = {
   219		.num_drv_data = 1,
   220		.drv_data = {
   221			&mt7623_mmsys_driver_data,
   222		},
   223	};
   224	
   225	static const struct mtk_mmsys_driver_data mt2712_mmsys_driver_data = {
   226		.main_path = mt2712_mtk_ddp_main,
   227		.main_len = ARRAY_SIZE(mt2712_mtk_ddp_main),
   228		.ext_path = mt2712_mtk_ddp_ext,
   229		.ext_len = ARRAY_SIZE(mt2712_mtk_ddp_ext),
   230		.third_path = mt2712_mtk_ddp_third,
   231		.third_len = ARRAY_SIZE(mt2712_mtk_ddp_third),
   232	};
   233	
 > 234	static const struct mtk_mmsys_match_data mt2712_mmsys_match_data = {
   235		.num_drv_data = 1,
   236		.drv_data = {
   237			&mt2712_mmsys_driver_data,
   238		},
   239	};
   240	
   241	static const struct mtk_mmsys_driver_data mt8167_mmsys_driver_data = {
   242		.main_path = mt8167_mtk_ddp_main,
   243		.main_len = ARRAY_SIZE(mt8167_mtk_ddp_main),
   244	};
   245	
 > 246	static const struct mtk_mmsys_match_data mt8167_mmsys_match_data = {
   247		.num_drv_data = 1,
   248		.drv_data = {
   249			&mt8167_mmsys_driver_data,
   250		},
   251	};
   252	
   253	static const struct mtk_mmsys_driver_data mt8173_mmsys_driver_data = {
   254		.main_path = mt8173_mtk_ddp_main,
   255		.main_len = ARRAY_SIZE(mt8173_mtk_ddp_main),
   256		.ext_path = mt8173_mtk_ddp_ext,
   257		.ext_len = ARRAY_SIZE(mt8173_mtk_ddp_ext),
   258	};
   259	
 > 260	static const struct mtk_mmsys_match_data mt8173_mmsys_match_data = {
   261		.num_drv_data = 1,
   262		.drv_data = {
   263			&mt8173_mmsys_driver_data,
   264		},
   265	};
   266	
   267	static const struct mtk_mmsys_driver_data mt8183_mmsys_driver_data = {
   268		.main_path = mt8183_mtk_ddp_main,
   269		.main_len = ARRAY_SIZE(mt8183_mtk_ddp_main),
   270		.ext_path = mt8183_mtk_ddp_ext,
   271		.ext_len = ARRAY_SIZE(mt8183_mtk_ddp_ext),
   272	};
   273	
 > 274	static const struct mtk_mmsys_match_data mt8183_mmsys_match_data = {
   275		.num_drv_data = 1,
   276		.drv_data = {
   277			&mt8183_mmsys_driver_data,
   278		},
   279	};
   280	
   281	static const struct mtk_mmsys_driver_data mt8192_mmsys_driver_data = {
   282		.main_path = mt8192_mtk_ddp_main,
   283		.main_len = ARRAY_SIZE(mt8192_mtk_ddp_main),
   284		.ext_path = mt8192_mtk_ddp_ext,
   285		.ext_len = ARRAY_SIZE(mt8192_mtk_ddp_ext),
   286	};
   287	
 > 288	static const struct mtk_mmsys_match_data mt8192_mmsys_match_data = {
   289		.num_drv_data = 1,
   290		.drv_data = {
   291			&mt8192_mmsys_driver_data,
   292		},
   293	};
   294	
   295	static const struct mtk_mmsys_driver_data mt8195_vdosys0_driver_data = {
   296		.io_start = 0x1c01a000,
   297		.main_path = mt8195_mtk_ddp_main,
   298		.main_len = ARRAY_SIZE(mt8195_mtk_ddp_main),
   299	};
   300	
   301	static const struct mtk_mmsys_driver_data mt8195_vdosys1_driver_data = {
   302		.io_start = 0x1c100000,
   303	};
   304	
 > 305	static const struct mtk_mmsys_match_data mt8195_mmsys_match_data = {
   306		.num_drv_data = 1,
   307		.drv_data = {
   308			&mt8195_vdosys0_driver_data,
   309			&mt8195_vdosys1_driver_data,
   310		},
   311	};
   312	

-- 
0-DAY CI Kernel Test Service
https://01.org/lkp

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 08/10] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
  2022-04-12 10:31   ` jason-jh.lin
  (?)
@ 2022-04-15  6:24     ` Rex-BC Chen
  -1 siblings, 0 replies; 70+ messages in thread
From: Rex-BC Chen @ 2022-04-15  6:24 UTC (permalink / raw)
  To: jason-jh.lin, Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, Maxime Coquelin, fshao, David Airlie, linux-kernel,
	Singo Chang (張興國),
	Roy-CW Yeh (葉中瑋),
	dri-devel, Yongqiang Niu (牛永强),
	Project_Global_Chrome_Upstream_Group, Fabien Parent,
	Moudy Ho (何宗原),
	linux-mediatek, hsinyi, Nancy Lin (林欣螢),
	linux-stm32, linux-arm-kernel

On Tue, 2022-04-12 at 18:31 +0800, jason-jh.lin wrote:
> The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
> 
> But its header need to keep DDP_COMPONENT_DITHER enum
> until drm/mediatek also changed it.

Hello Jason,

IMO, it's strange.
In this case , I think you sholud squash [v18,08/10] and [v18,09/10].
Therefore, you don't need to describe this here.

BRs,
Rex


^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 08/10] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
@ 2022-04-15  6:24     ` Rex-BC Chen
  0 siblings, 0 replies; 70+ messages in thread
From: Rex-BC Chen @ 2022-04-15  6:24 UTC (permalink / raw)
  To: jason-jh.lin, Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, Maxime Coquelin, David Airlie, linux-kernel,
	Singo Chang (張興國),
	Roy-CW Yeh (葉中瑋),
	dri-devel, Yongqiang Niu (牛永强),
	Project_Global_Chrome_Upstream_Group, Fabien Parent,
	Moudy Ho (何宗原),
	linux-mediatek, Daniel Vetter, hsinyi,
	CK Hu (胡俊光),
	Philipp Zabel, Nancy Lin (林欣螢),
	linux-stm32, linux-arm-kernel

On Tue, 2022-04-12 at 18:31 +0800, jason-jh.lin wrote:
> The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
> 
> But its header need to keep DDP_COMPONENT_DITHER enum
> until drm/mediatek also changed it.

Hello Jason,

IMO, it's strange.
In this case , I think you sholud squash [v18,08/10] and [v18,09/10].
Therefore, you don't need to describe this here.

BRs,
Rex


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 08/10] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
@ 2022-04-15  6:24     ` Rex-BC Chen
  0 siblings, 0 replies; 70+ messages in thread
From: Rex-BC Chen @ 2022-04-15  6:24 UTC (permalink / raw)
  To: jason-jh.lin, Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu (胡俊光),
	Yongqiang Niu (牛永强),
	hsinyi, fshao, Moudy Ho (何宗原),
	Roy-CW Yeh (葉中瑋),
	Nancy Lin (林欣螢),
	Singo Chang (張興國),
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

On Tue, 2022-04-12 at 18:31 +0800, jason-jh.lin wrote:
> The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
> 
> But its header need to keep DDP_COMPONENT_DITHER enum
> until drm/mediatek also changed it.

Hello Jason,

IMO, it's strange.
In this case , I think you sholud squash [v18,08/10] and [v18,09/10].
Therefore, you don't need to describe this here.

BRs,
Rex


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 07/10] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
  2022-04-14 15:31     ` kernel test robot
                         ` (2 preceding siblings ...)
  (?)
@ 2022-04-15  6:27       ` Jason-JH Lin
  -1 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-15  6:27 UTC (permalink / raw)
  To: kernel test robot, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, moudy.ho, kbuild-all, Maxime Coquelin, David Airlie,
	singo.chang, llvm, roy-cw.yeh, dri-devel, linux-kernel,
	Project_Global_Chrome_Upstream_Group, Fabien Parent, nancy.lin,
	linux-mediatek, Yongqiang Niu, hsinyi, Rex-BC Chen, linux-stm32,
	linux-arm-kernel

Hi "kernel test robot",

Thanks for the reviews.

On Thu, 2022-04-14 at 23:31 +0800, kernel test robot wrote:
> Hi "jason-jh.lin",
> 
> Thank you for the patch! Perhaps something to improve:
> 
> [auto build test WARNING on drm/drm-next]
> [also build test WARNING on robh/for-next krzk/for-next linus/master
> v5.18-rc2 next-20220414]
> [If your patch is applied to the wrong git tree, kindly drop us a
> note.
> And when submitting patch, we suggest to use '--base' as documented
> in
> 
https://urldefense.com/v3/__https://git-scm.com/docs/git-format-patch__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaGS9DHJM$
>  ]
> 
> url:    
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaP5NY9rw$
>  
> base:   git://anongit.freedesktop.org/drm/drm drm-next
> config: arm64-buildonly-randconfig-r001-20220413 (
> https://urldefense.com/v3/__https://download.01.org/0day-ci/archive/20220414/202204142333.qXgcGMI1-lkp@intel.com/config__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaMatHhNq$
>  )
> compiler: clang version 15.0.0 (
> https://urldefense.com/v3/__https://github.com/llvm/llvm-project__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaED4pz5K$
> $  6b7e6ea489f6dd45a9b0da9ac20871560917b9b0)
> reproduce (this is a W=1 build):
>         wget 
> https://urldefense.com/v3/__https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaGF0WqUy$
>   -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # install arm64 cross compiling tool for clang build
>         # apt-get install binutils-aarch64-linux-gnu
>         # 
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commit/7c175317aa80bbc885609a730214448147a46b47__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaN_w7rr0$
>  
>         git remote add linux-review 
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaMen_Lno$
>  
>         git fetch --no-tags linux-review jason-jh-lin/Add-Mediatek-
> Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
>         git checkout 7c175317aa80bbc885609a730214448147a46b47
>         # save the config file to linux build tree
>         mkdir build_dir
>         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross
> W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/mediatek/
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> 
> All warnings (new ones prefixed by >>):
> 
>    drivers/gpu/drm/mediatek/mtk_drm_drv.c:707:15: warning: cast to
> smaller integer type 'enum mtk_ddp_comp_type' from 'const void *' [-
> Wvoid-pointer-to-enum-cast]
>                    comp_type = (enum mtk_ddp_comp_type)of_id->data;
>                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
I can't reproduce this build warning in my platform, but I'd found the 
same warning fixed patch: 20210928154620.11181-4-cgzones@googlemail.com

It should not be fixed at this series. So I'll fixed this warning in
another fixed patch.

> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:203:42: warning: unused
> > > variable 'mt2701_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt2701_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:218:42: warning: unused
> > > variable 'mt7623_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt7623_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:234:42: warning: unused
> > > variable 'mt2712_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt2712_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:246:42: warning: unused
> > > variable 'mt8167_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8167_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:260:42: warning: unused
> > > variable 'mt8173_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8173_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:274:42: warning: unused
> > > variable 'mt8183_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8183_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:288:42: warning: unused
> > > variable 'mt8192_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8192_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:305:42: warning: unused
> > > variable 'mt8195_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8195_mmsys_match_data =
> {

Oh, I forgot to replace the driver_data to match_data in mtk_drm_of_ids
table. I'll fix them at the next version.

Regards,
Jason-JH.Lin



^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 07/10] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-15  6:27       ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-15  6:27 UTC (permalink / raw)
  To: kernel test robot, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, kbuild-all, Yongqiang Niu, David Airlie, singo.chang,
	llvm, roy-cw.yeh, dri-devel, linux-kernel,
	Project_Global_Chrome_Upstream_Group, Fabien Parent, moudy.ho,
	linux-mediatek, Maxime Coquelin, hsinyi, Rex-BC Chen, nancy.lin,
	linux-stm32, linux-arm-kernel

Hi "kernel test robot",

Thanks for the reviews.

On Thu, 2022-04-14 at 23:31 +0800, kernel test robot wrote:
> Hi "jason-jh.lin",
> 
> Thank you for the patch! Perhaps something to improve:
> 
> [auto build test WARNING on drm/drm-next]
> [also build test WARNING on robh/for-next krzk/for-next linus/master
> v5.18-rc2 next-20220414]
> [If your patch is applied to the wrong git tree, kindly drop us a
> note.
> And when submitting patch, we suggest to use '--base' as documented
> in
> 
https://urldefense.com/v3/__https://git-scm.com/docs/git-format-patch__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaGS9DHJM$
>  ]
> 
> url:    
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaP5NY9rw$
>  
> base:   git://anongit.freedesktop.org/drm/drm drm-next
> config: arm64-buildonly-randconfig-r001-20220413 (
> https://urldefense.com/v3/__https://download.01.org/0day-ci/archive/20220414/202204142333.qXgcGMI1-lkp@intel.com/config__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaMatHhNq$
>  )
> compiler: clang version 15.0.0 (
> https://urldefense.com/v3/__https://github.com/llvm/llvm-project__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaED4pz5K$
> $  6b7e6ea489f6dd45a9b0da9ac20871560917b9b0)
> reproduce (this is a W=1 build):
>         wget 
> https://urldefense.com/v3/__https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaGF0WqUy$
>   -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # install arm64 cross compiling tool for clang build
>         # apt-get install binutils-aarch64-linux-gnu
>         # 
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commit/7c175317aa80bbc885609a730214448147a46b47__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaN_w7rr0$
>  
>         git remote add linux-review 
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaMen_Lno$
>  
>         git fetch --no-tags linux-review jason-jh-lin/Add-Mediatek-
> Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
>         git checkout 7c175317aa80bbc885609a730214448147a46b47
>         # save the config file to linux build tree
>         mkdir build_dir
>         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross
> W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/mediatek/
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> 
> All warnings (new ones prefixed by >>):
> 
>    drivers/gpu/drm/mediatek/mtk_drm_drv.c:707:15: warning: cast to
> smaller integer type 'enum mtk_ddp_comp_type' from 'const void *' [-
> Wvoid-pointer-to-enum-cast]
>                    comp_type = (enum mtk_ddp_comp_type)of_id->data;
>                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
I can't reproduce this build warning in my platform, but I'd found the 
same warning fixed patch: 20210928154620.11181-4-cgzones@googlemail.com

It should not be fixed at this series. So I'll fixed this warning in
another fixed patch.

> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:203:42: warning: unused
> > > variable 'mt2701_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt2701_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:218:42: warning: unused
> > > variable 'mt7623_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt7623_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:234:42: warning: unused
> > > variable 'mt2712_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt2712_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:246:42: warning: unused
> > > variable 'mt8167_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8167_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:260:42: warning: unused
> > > variable 'mt8173_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8173_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:274:42: warning: unused
> > > variable 'mt8183_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8183_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:288:42: warning: unused
> > > variable 'mt8192_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8192_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:305:42: warning: unused
> > > variable 'mt8195_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8195_mmsys_match_data =
> {

Oh, I forgot to replace the driver_data to match_data in mtk_drm_of_ids
table. I'll fix them at the next version.

Regards,
Jason-JH.Lin



^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 07/10] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-15  6:27       ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-15  6:27 UTC (permalink / raw)
  To: kernel test robot, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, moudy.ho, kbuild-all, Maxime Coquelin, David Airlie,
	singo.chang, llvm, roy-cw.yeh, dri-devel, linux-kernel,
	Project_Global_Chrome_Upstream_Group, Fabien Parent, nancy.lin,
	linux-mediatek, Yongqiang Niu, hsinyi, Rex-BC Chen, linux-stm32,
	linux-arm-kernel

Hi "kernel test robot",

Thanks for the reviews.

On Thu, 2022-04-14 at 23:31 +0800, kernel test robot wrote:
> Hi "jason-jh.lin",
> 
> Thank you for the patch! Perhaps something to improve:
> 
> [auto build test WARNING on drm/drm-next]
> [also build test WARNING on robh/for-next krzk/for-next linus/master
> v5.18-rc2 next-20220414]
> [If your patch is applied to the wrong git tree, kindly drop us a
> note.
> And when submitting patch, we suggest to use '--base' as documented
> in
> 
https://urldefense.com/v3/__https://git-scm.com/docs/git-format-patch__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaGS9DHJM$
>  ]
> 
> url:    
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaP5NY9rw$
>  
> base:   git://anongit.freedesktop.org/drm/drm drm-next
> config: arm64-buildonly-randconfig-r001-20220413 (
> https://urldefense.com/v3/__https://download.01.org/0day-ci/archive/20220414/202204142333.qXgcGMI1-lkp@intel.com/config__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaMatHhNq$
>  )
> compiler: clang version 15.0.0 (
> https://urldefense.com/v3/__https://github.com/llvm/llvm-project__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaED4pz5K$
> $  6b7e6ea489f6dd45a9b0da9ac20871560917b9b0)
> reproduce (this is a W=1 build):
>         wget 
> https://urldefense.com/v3/__https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaGF0WqUy$
>   -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # install arm64 cross compiling tool for clang build
>         # apt-get install binutils-aarch64-linux-gnu
>         # 
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commit/7c175317aa80bbc885609a730214448147a46b47__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaN_w7rr0$
>  
>         git remote add linux-review 
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaMen_Lno$
>  
>         git fetch --no-tags linux-review jason-jh-lin/Add-Mediatek-
> Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
>         git checkout 7c175317aa80bbc885609a730214448147a46b47
>         # save the config file to linux build tree
>         mkdir build_dir
>         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross
> W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/mediatek/
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> 
> All warnings (new ones prefixed by >>):
> 
>    drivers/gpu/drm/mediatek/mtk_drm_drv.c:707:15: warning: cast to
> smaller integer type 'enum mtk_ddp_comp_type' from 'const void *' [-
> Wvoid-pointer-to-enum-cast]
>                    comp_type = (enum mtk_ddp_comp_type)of_id->data;
>                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
I can't reproduce this build warning in my platform, but I'd found the 
same warning fixed patch: 20210928154620.11181-4-cgzones@googlemail.com

It should not be fixed at this series. So I'll fixed this warning in
another fixed patch.

> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:203:42: warning: unused
> > > variable 'mt2701_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt2701_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:218:42: warning: unused
> > > variable 'mt7623_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt7623_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:234:42: warning: unused
> > > variable 'mt2712_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt2712_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:246:42: warning: unused
> > > variable 'mt8167_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8167_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:260:42: warning: unused
> > > variable 'mt8173_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8173_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:274:42: warning: unused
> > > variable 'mt8183_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8183_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:288:42: warning: unused
> > > variable 'mt8192_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8192_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:305:42: warning: unused
> > > variable 'mt8195_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8195_mmsys_match_data =
> {

Oh, I forgot to replace the driver_data to match_data in mtk_drm_of_ids
table. I'll fix them at the next version.

Regards,
Jason-JH.Lin



_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 07/10] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-15  6:27       ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-15  6:27 UTC (permalink / raw)
  To: kernel test robot, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, moudy.ho, kbuild-all, Maxime Coquelin, David Airlie,
	singo.chang, llvm, roy-cw.yeh, dri-devel, linux-kernel,
	Project_Global_Chrome_Upstream_Group, Fabien Parent, nancy.lin,
	linux-mediatek, Yongqiang Niu, hsinyi, Rex-BC Chen, linux-stm32,
	linux-arm-kernel

Hi "kernel test robot",

Thanks for the reviews.

On Thu, 2022-04-14 at 23:31 +0800, kernel test robot wrote:
> Hi "jason-jh.lin",
> 
> Thank you for the patch! Perhaps something to improve:
> 
> [auto build test WARNING on drm/drm-next]
> [also build test WARNING on robh/for-next krzk/for-next linus/master
> v5.18-rc2 next-20220414]
> [If your patch is applied to the wrong git tree, kindly drop us a
> note.
> And when submitting patch, we suggest to use '--base' as documented
> in
> 
https://urldefense.com/v3/__https://git-scm.com/docs/git-format-patch__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaGS9DHJM$
>  ]
> 
> url:    
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaP5NY9rw$
>  
> base:   git://anongit.freedesktop.org/drm/drm drm-next
> config: arm64-buildonly-randconfig-r001-20220413 (
> https://urldefense.com/v3/__https://download.01.org/0day-ci/archive/20220414/202204142333.qXgcGMI1-lkp@intel.com/config__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaMatHhNq$
>  )
> compiler: clang version 15.0.0 (
> https://urldefense.com/v3/__https://github.com/llvm/llvm-project__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaED4pz5K$
> $  6b7e6ea489f6dd45a9b0da9ac20871560917b9b0)
> reproduce (this is a W=1 build):
>         wget 
> https://urldefense.com/v3/__https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaGF0WqUy$
>   -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # install arm64 cross compiling tool for clang build
>         # apt-get install binutils-aarch64-linux-gnu
>         # 
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commit/7c175317aa80bbc885609a730214448147a46b47__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaN_w7rr0$
>  
>         git remote add linux-review 
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaMen_Lno$
>  
>         git fetch --no-tags linux-review jason-jh-lin/Add-Mediatek-
> Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
>         git checkout 7c175317aa80bbc885609a730214448147a46b47
>         # save the config file to linux build tree
>         mkdir build_dir
>         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross
> W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/mediatek/
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> 
> All warnings (new ones prefixed by >>):
> 
>    drivers/gpu/drm/mediatek/mtk_drm_drv.c:707:15: warning: cast to
> smaller integer type 'enum mtk_ddp_comp_type' from 'const void *' [-
> Wvoid-pointer-to-enum-cast]
>                    comp_type = (enum mtk_ddp_comp_type)of_id->data;
>                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
I can't reproduce this build warning in my platform, but I'd found the 
same warning fixed patch: 20210928154620.11181-4-cgzones@googlemail.com

It should not be fixed at this series. So I'll fixed this warning in
another fixed patch.

> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:203:42: warning: unused
> > > variable 'mt2701_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt2701_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:218:42: warning: unused
> > > variable 'mt7623_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt7623_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:234:42: warning: unused
> > > variable 'mt2712_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt2712_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:246:42: warning: unused
> > > variable 'mt8167_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8167_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:260:42: warning: unused
> > > variable 'mt8173_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8173_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:274:42: warning: unused
> > > variable 'mt8183_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8183_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:288:42: warning: unused
> > > variable 'mt8192_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8192_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:305:42: warning: unused
> > > variable 'mt8195_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8195_mmsys_match_data =
> {

Oh, I forgot to replace the driver_data to match_data in mtk_drm_of_ids
table. I'll fix them at the next version.

Regards,
Jason-JH.Lin



_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 07/10] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195
@ 2022-04-15  6:27       ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-15  6:27 UTC (permalink / raw)
  To: kbuild-all

[-- Attachment #1: Type: text/plain, Size: 5766 bytes --]

Hi "kernel test robot",

Thanks for the reviews.

On Thu, 2022-04-14 at 23:31 +0800, kernel test robot wrote:
> Hi "jason-jh.lin",
> 
> Thank you for the patch! Perhaps something to improve:
> 
> [auto build test WARNING on drm/drm-next]
> [also build test WARNING on robh/for-next krzk/for-next linus/master
> v5.18-rc2 next-20220414]
> [If your patch is applied to the wrong git tree, kindly drop us a
> note.
> And when submitting patch, we suggest to use '--base' as documented
> in
> 
https://urldefense.com/v3/__https://git-scm.com/docs/git-format-patch__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaGS9DHJM$
>  ]
> 
> url:    
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commits/jason-jh-lin/Add-Mediatek-Soc-DRM-vdosys0-support-for-mt8195/20220412-183359__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaP5NY9rw$
>  
> base:   git://anongit.freedesktop.org/drm/drm drm-next
> config: arm64-buildonly-randconfig-r001-20220413 (
> https://urldefense.com/v3/__https://download.01.org/0day-ci/archive/20220414/202204142333.qXgcGMI1-lkp(a)intel.com/config__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaMatHhNq$
>  )
> compiler: clang version 15.0.0 (
> https://urldefense.com/v3/__https://github.com/llvm/llvm-project__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaED4pz5K$
> $  6b7e6ea489f6dd45a9b0da9ac20871560917b9b0)
> reproduce (this is a W=1 build):
>         wget 
> https://urldefense.com/v3/__https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaGF0WqUy$
>   -O ~/bin/make.cross
>         chmod +x ~/bin/make.cross
>         # install arm64 cross compiling tool for clang build
>         # apt-get install binutils-aarch64-linux-gnu
>         # 
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux/commit/7c175317aa80bbc885609a730214448147a46b47__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaN_w7rr0$
>  
>         git remote add linux-review 
> https://urldefense.com/v3/__https://github.com/intel-lab-lkp/linux__;!!CTRNKA9wMg0ARbw!1fp3H7fjidBzBzfT64rjyCv4-HN-czQi_52IEZTo18hsph4srdLAEfrGamKBaMen_Lno$
>  
>         git fetch --no-tags linux-review jason-jh-lin/Add-Mediatek-
> Soc-DRM-vdosys0-support-for-mt8195/20220412-183359
>         git checkout 7c175317aa80bbc885609a730214448147a46b47
>         # save the config file to linux build tree
>         mkdir build_dir
>         COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross
> W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash drivers/gpu/drm/mediatek/
> 
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
> 
> All warnings (new ones prefixed by >>):
> 
>    drivers/gpu/drm/mediatek/mtk_drm_drv.c:707:15: warning: cast to
> smaller integer type 'enum mtk_ddp_comp_type' from 'const void *' [-
> Wvoid-pointer-to-enum-cast]
>                    comp_type = (enum mtk_ddp_comp_type)of_id->data;
>                                ^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~
I can't reproduce this build warning in my platform, but I'd found the 
same warning fixed patch: 20210928154620.11181-4-cgzones(a)googlemail.com

It should not be fixed at this series. So I'll fixed this warning in
another fixed patch.

> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:203:42: warning: unused
> > > variable 'mt2701_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt2701_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:218:42: warning: unused
> > > variable 'mt7623_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt7623_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:234:42: warning: unused
> > > variable 'mt2712_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt2712_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:246:42: warning: unused
> > > variable 'mt8167_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8167_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:260:42: warning: unused
> > > variable 'mt8173_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8173_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:274:42: warning: unused
> > > variable 'mt8183_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8183_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:288:42: warning: unused
> > > variable 'mt8192_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8192_mmsys_match_data =
> {
>                                             ^
> > > drivers/gpu/drm/mediatek/mtk_drm_drv.c:305:42: warning: unused
> > > variable 'mt8195_mmsys_match_data' [-Wunused-const-variable]
> 
>    static const struct mtk_mmsys_match_data mt8195_mmsys_match_data =
> {

Oh, I forgot to replace the driver_data to match_data in mtk_drm_of_ids
table. I'll fix them at the next version.

Regards,
Jason-JH.Lin


^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 08/10] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
  2022-04-15  6:24     ` Rex-BC Chen
  (?)
  (?)
@ 2022-04-15  8:13       ` Jason-JH Lin
  -1 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-15  8:13 UTC (permalink / raw)
  To: Rex-BC Chen, Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu (胡俊光),
	Yongqiang Niu (牛永强),
	hsinyi, fshao, Moudy Ho (何宗原),
	Roy-CW Yeh (葉中瑋),
	Nancy Lin (林欣螢),
	Singo Chang (張興國),
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

Hi Rex,

Thank for the reviews.

On Fri, 2022-04-15 at 14:24 +0800, Rex-BC Chen wrote:
> On Tue, 2022-04-12 at 18:31 +0800, jason-jh.lin wrote:
> > The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> > so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> > DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
> > 
> > But its header need to keep DDP_COMPONENT_DITHER enum
> > until drm/mediatek also changed it.
> 
> Hello Jason,
> 
> IMO, it's strange.
> In this case , I think you sholud squash [v18,08/10] and [v18,09/10].
> Therefore, you don't need to describe this here.
> 

As the CK reply before:

https://patchwork.kernel.org/project/linux-mediatek/patch/20220407030409.9664-4-jason-jh.lin@mediatek.com/#24806029

[v18,08/10] and [v18,09/10] belong to 2 different trees, so I add the
description here.

Regards,
Jason-JH.Lin


> BRs,
> Rex
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 08/10] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
@ 2022-04-15  8:13       ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-15  8:13 UTC (permalink / raw)
  To: Rex-BC Chen, Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, Maxime Coquelin, David Airlie, linux-kernel,
	Singo Chang (張興國),
	Roy-CW Yeh (葉中瑋),
	dri-devel, Yongqiang Niu (牛永强),
	Project_Global_Chrome_Upstream_Group, Fabien Parent,
	Moudy Ho (何宗原),
	linux-mediatek, Daniel Vetter, hsinyi,
	CK Hu (胡俊光),
	Philipp Zabel, Nancy Lin (林欣螢),
	linux-stm32, linux-arm-kernel

Hi Rex,

Thank for the reviews.

On Fri, 2022-04-15 at 14:24 +0800, Rex-BC Chen wrote:
> On Tue, 2022-04-12 at 18:31 +0800, jason-jh.lin wrote:
> > The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> > so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> > DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
> > 
> > But its header need to keep DDP_COMPONENT_DITHER enum
> > until drm/mediatek also changed it.
> 
> Hello Jason,
> 
> IMO, it's strange.
> In this case , I think you sholud squash [v18,08/10] and [v18,09/10].
> Therefore, you don't need to describe this here.
> 

As the CK reply before:

https://patchwork.kernel.org/project/linux-mediatek/patch/20220407030409.9664-4-jason-jh.lin@mediatek.com/#24806029

[v18,08/10] and [v18,09/10] belong to 2 different trees, so I add the
description here.

Regards,
Jason-JH.Lin


> BRs,
> Rex
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 08/10] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
@ 2022-04-15  8:13       ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-15  8:13 UTC (permalink / raw)
  To: Rex-BC Chen, Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: devicetree, Maxime Coquelin, fshao, David Airlie, linux-kernel,
	Singo Chang (張興國),
	Roy-CW Yeh (葉中瑋),
	dri-devel, Yongqiang Niu (牛永强),
	Project_Global_Chrome_Upstream_Group, Fabien Parent,
	Moudy Ho (何宗原),
	linux-mediatek, hsinyi, Nancy Lin (林欣螢),
	linux-stm32, linux-arm-kernel

Hi Rex,

Thank for the reviews.

On Fri, 2022-04-15 at 14:24 +0800, Rex-BC Chen wrote:
> On Tue, 2022-04-12 at 18:31 +0800, jason-jh.lin wrote:
> > The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> > so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> > DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
> > 
> > But its header need to keep DDP_COMPONENT_DITHER enum
> > until drm/mediatek also changed it.
> 
> Hello Jason,
> 
> IMO, it's strange.
> In this case , I think you sholud squash [v18,08/10] and [v18,09/10].
> Therefore, you don't need to describe this here.
> 

As the CK reply before:

https://patchwork.kernel.org/project/linux-mediatek/patch/20220407030409.9664-4-jason-jh.lin@mediatek.com/#24806029

[v18,08/10] and [v18,09/10] belong to 2 different trees, so I add the
description here.

Regards,
Jason-JH.Lin


> BRs,
> Rex
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 08/10] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0
@ 2022-04-15  8:13       ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-15  8:13 UTC (permalink / raw)
  To: Rex-BC Chen, Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Philipp Zabel, Maxime Coquelin, David Airlie, Daniel Vetter,
	Fabien Parent, CK Hu (胡俊光),
	Yongqiang Niu (牛永强),
	hsinyi, fshao, Moudy Ho (何宗原),
	Roy-CW Yeh (葉中瑋),
	Nancy Lin (林欣螢),
	Singo Chang (張興國),
	devicetree, linux-stm32, linux-arm-kernel, linux-mediatek,
	linux-kernel, dri-devel, Project_Global_Chrome_Upstream_Group

Hi Rex,

Thank for the reviews.

On Fri, 2022-04-15 at 14:24 +0800, Rex-BC Chen wrote:
> On Tue, 2022-04-12 at 18:31 +0800, jason-jh.lin wrote:
> > The mmsys routing table of mt8195 vdosys0 has 2 DITHER components,
> > so mmsys need to add DDP_COMPONENT_DITHER1 and change all usages of
> > DITHER enum form DDP_COMPONENT_DITHER to DDP_COMPONENT_DITHER0.
> > 
> > But its header need to keep DDP_COMPONENT_DITHER enum
> > until drm/mediatek also changed it.
> 
> Hello Jason,
> 
> IMO, it's strange.
> In this case , I think you sholud squash [v18,08/10] and [v18,09/10].
> Therefore, you don't need to describe this here.
> 

As the CK reply before:

https://patchwork.kernel.org/project/linux-mediatek/patch/20220407030409.9664-4-jason-jh.lin@mediatek.com/#24806029

[v18,08/10] and [v18,09/10] belong to 2 different trees, so I add the
description here.

Regards,
Jason-JH.Lin


> BRs,
> Rex
> 
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 02/10] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
  2022-04-14  3:11     ` Jason-JH Lin
  (?)
@ 2022-04-18 17:03       ` Krzysztof Kozlowski
  -1 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-18 17:03 UTC (permalink / raw)
  To: Jason-JH Lin, Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Rex-BC Chen (陳柏辰),
	devicetree, linux-arm-kernel, linux-mediatek

[-- Attachment #1: Type: text/plain, Size: 940 bytes --]

On 14/04/2022 05:11, Jason-JH Lin wrote:
> Hello Rob, Krzysztof,
> 
> I found the dt-binding patches in this series never appeared in
> devicetree-bindings patchwork and trigger the dt-binding check bot.
> 
> Do you know the reason for this?
> Could you help me with this and let me know what should I do to solve
> this problem?

Hi,

All your emails end up regularly in my Gmail spam folder, similarly to
emails from some other Mediatek people (e.g. Rex-BC Chen), so maybe
that's the cause?

Why they end up in spam? I don't know, but it would be nice if you could
work on this with your IT department. I know that corporate environments
are tricky to change, but there is not much else to do. Google flags
your emails always as spam.

You can see in the headers two DMARC failures:
dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=QUARANTINE)
header.from=mediatek.com

Spamming 27 recipients is maybe another reason...

Best regards,
Krzysztof

[-- Attachment #2: mediatek-spam.txt --]
[-- Type: text/plain, Size: 1501 bytes --]

smtp.mailfrom="SRS0=SiiB=UW=mediatek.com=jason-jh.lin@kernel.org";
       dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=QUARANTINE) header.from=mediatek.com
Return-Path: <SRS0=SiiB=UW=mediatek.com=jason-jh.lin@kernel.org>
Received: from ams.source.kernel.org (ams.source.kernel.org. [2604:1380:4601:e00::1])
        by mx.google.com with ESMTPS id m2-20020a17090679c200b006e881149e83si5514956ejo.629.2022.04.12.03.31.30
        for <k.kozlowski.k+kernel@gmail.com>
        (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128);
        Tue, 12 Apr 2022 03:31:30 -0700 (PDT)
Received-SPF: pass (google.com: domain of srs0=siib=uw=mediatek.com=jason-jh.lin@kernel.org designates 2604:1380:4601:e00::1 as permitted sender) client-ip=2604:1380:4601:e00::1;
Authentication-Results: mx.google.com;
       spf=pass (google.com: domain of srs0=siib=uw=mediatek.com=jason-jh.lin@kernel.org designates 2604:1380:4601:e00::1 as permitted sender) smtp.mailfrom="SRS0=SiiB=UW=mediatek.com=jason-jh.lin@kernel.org";
       dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=QUARANTINE) header.from=mediatek.com
Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id C63D9B81CA1 for <k.kozlowski.k+kernel@gmail.com>; Tue, 12 Apr 2022 10:31:29 +0000 (UTC)
Received: by smtp.kernel.org (Postfix) id 8CA9AC385A6; Tue, 12 Apr 2022 10:31:29 +0000 (UTC)

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 02/10] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
@ 2022-04-18 17:03       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-18 17:03 UTC (permalink / raw)
  To: Jason-JH Lin, Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Rex-BC Chen (陳柏辰),
	devicetree, linux-arm-kernel, linux-mediatek

[-- Attachment #1: Type: text/plain, Size: 940 bytes --]

On 14/04/2022 05:11, Jason-JH Lin wrote:
> Hello Rob, Krzysztof,
> 
> I found the dt-binding patches in this series never appeared in
> devicetree-bindings patchwork and trigger the dt-binding check bot.
> 
> Do you know the reason for this?
> Could you help me with this and let me know what should I do to solve
> this problem?

Hi,

All your emails end up regularly in my Gmail spam folder, similarly to
emails from some other Mediatek people (e.g. Rex-BC Chen), so maybe
that's the cause?

Why they end up in spam? I don't know, but it would be nice if you could
work on this with your IT department. I know that corporate environments
are tricky to change, but there is not much else to do. Google flags
your emails always as spam.

You can see in the headers two DMARC failures:
dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=QUARANTINE)
header.from=mediatek.com

Spamming 27 recipients is maybe another reason...

Best regards,
Krzysztof

[-- Attachment #2: mediatek-spam.txt --]
[-- Type: text/plain, Size: 1501 bytes --]

smtp.mailfrom="SRS0=SiiB=UW=mediatek.com=jason-jh.lin@kernel.org";
       dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=QUARANTINE) header.from=mediatek.com
Return-Path: <SRS0=SiiB=UW=mediatek.com=jason-jh.lin@kernel.org>
Received: from ams.source.kernel.org (ams.source.kernel.org. [2604:1380:4601:e00::1])
        by mx.google.com with ESMTPS id m2-20020a17090679c200b006e881149e83si5514956ejo.629.2022.04.12.03.31.30
        for <k.kozlowski.k+kernel@gmail.com>
        (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128);
        Tue, 12 Apr 2022 03:31:30 -0700 (PDT)
Received-SPF: pass (google.com: domain of srs0=siib=uw=mediatek.com=jason-jh.lin@kernel.org designates 2604:1380:4601:e00::1 as permitted sender) client-ip=2604:1380:4601:e00::1;
Authentication-Results: mx.google.com;
       spf=pass (google.com: domain of srs0=siib=uw=mediatek.com=jason-jh.lin@kernel.org designates 2604:1380:4601:e00::1 as permitted sender) smtp.mailfrom="SRS0=SiiB=UW=mediatek.com=jason-jh.lin@kernel.org";
       dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=QUARANTINE) header.from=mediatek.com
Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id C63D9B81CA1 for <k.kozlowski.k+kernel@gmail.com>; Tue, 12 Apr 2022 10:31:29 +0000 (UTC)
Received: by smtp.kernel.org (Postfix) id 8CA9AC385A6; Tue, 12 Apr 2022 10:31:29 +0000 (UTC)

[-- Attachment #3: Type: text/plain, Size: 170 bytes --]

_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 02/10] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
@ 2022-04-18 17:03       ` Krzysztof Kozlowski
  0 siblings, 0 replies; 70+ messages in thread
From: Krzysztof Kozlowski @ 2022-04-18 17:03 UTC (permalink / raw)
  To: Jason-JH Lin, Rob Herring, Krzysztof Kozlowski, Matthias Brugger,
	Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Rex-BC Chen (陳柏辰),
	devicetree, linux-arm-kernel, linux-mediatek

[-- Attachment #1: Type: text/plain, Size: 940 bytes --]

On 14/04/2022 05:11, Jason-JH Lin wrote:
> Hello Rob, Krzysztof,
> 
> I found the dt-binding patches in this series never appeared in
> devicetree-bindings patchwork and trigger the dt-binding check bot.
> 
> Do you know the reason for this?
> Could you help me with this and let me know what should I do to solve
> this problem?

Hi,

All your emails end up regularly in my Gmail spam folder, similarly to
emails from some other Mediatek people (e.g. Rex-BC Chen), so maybe
that's the cause?

Why they end up in spam? I don't know, but it would be nice if you could
work on this with your IT department. I know that corporate environments
are tricky to change, but there is not much else to do. Google flags
your emails always as spam.

You can see in the headers two DMARC failures:
dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=QUARANTINE)
header.from=mediatek.com

Spamming 27 recipients is maybe another reason...

Best regards,
Krzysztof

[-- Attachment #2: mediatek-spam.txt --]
[-- Type: text/plain, Size: 1501 bytes --]

smtp.mailfrom="SRS0=SiiB=UW=mediatek.com=jason-jh.lin@kernel.org";
       dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=QUARANTINE) header.from=mediatek.com
Return-Path: <SRS0=SiiB=UW=mediatek.com=jason-jh.lin@kernel.org>
Received: from ams.source.kernel.org (ams.source.kernel.org. [2604:1380:4601:e00::1])
        by mx.google.com with ESMTPS id m2-20020a17090679c200b006e881149e83si5514956ejo.629.2022.04.12.03.31.30
        for <k.kozlowski.k+kernel@gmail.com>
        (version=TLS1_2 cipher=ECDHE-ECDSA-AES128-GCM-SHA256 bits=128/128);
        Tue, 12 Apr 2022 03:31:30 -0700 (PDT)
Received-SPF: pass (google.com: domain of srs0=siib=uw=mediatek.com=jason-jh.lin@kernel.org designates 2604:1380:4601:e00::1 as permitted sender) client-ip=2604:1380:4601:e00::1;
Authentication-Results: mx.google.com;
       spf=pass (google.com: domain of srs0=siib=uw=mediatek.com=jason-jh.lin@kernel.org designates 2604:1380:4601:e00::1 as permitted sender) smtp.mailfrom="SRS0=SiiB=UW=mediatek.com=jason-jh.lin@kernel.org";
       dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=QUARANTINE) header.from=mediatek.com
Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by ams.source.kernel.org (Postfix) with ESMTPS id C63D9B81CA1 for <k.kozlowski.k+kernel@gmail.com>; Tue, 12 Apr 2022 10:31:29 +0000 (UTC)
Received: by smtp.kernel.org (Postfix) id 8CA9AC385A6; Tue, 12 Apr 2022 10:31:29 +0000 (UTC)

[-- Attachment #3: Type: text/plain, Size: 176 bytes --]

_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 02/10] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
  2022-04-18 17:03       ` Krzysztof Kozlowski
  (?)
@ 2022-04-19  1:53         ` Jason-JH Lin
  -1 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-19  1:53 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Rex-BC Chen (陳柏辰),
	devicetree, linux-arm-kernel, linux-mediatek

Hi Krzysztof,

Really appreciate your helpful information.
I hope we can figure out with IT soon.

Thank you very much!

Regards,
Jason-JH.Lin

On Mon, 2022-04-18 at 19:03 +0200, Krzysztof Kozlowski wrote:
> On 14/04/2022 05:11, Jason-JH Lin wrote:
> > Hello Rob, Krzysztof,
> > 
> > I found the dt-binding patches in this series never appeared in
> > devicetree-bindings patchwork and trigger the dt-binding check bot.
> > 
> > Do you know the reason for this?
> > Could you help me with this and let me know what should I do to
> > solve
> > this problem?
> 
> Hi,
> 
> All your emails end up regularly in my Gmail spam folder, similarly
> to
> emails from some other Mediatek people (e.g. Rex-BC Chen), so maybe
> that's the cause?
> 
> Why they end up in spam? I don't know, but it would be nice if you
> could
> work on this with your IT department. I know that corporate
> environments
> are tricky to change, but there is not much else to do. Google flags
> your emails always as spam.
> 
> You can see in the headers two DMARC failures:
> dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=QUARANTINE)
> header.from=mediatek.com
> 
> Spamming 27 recipients is maybe another reason...
> 
> Best regards,
> Krzysztof
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 02/10] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
@ 2022-04-19  1:53         ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-19  1:53 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Rex-BC Chen (陳柏辰),
	devicetree, linux-arm-kernel, linux-mediatek

Hi Krzysztof,

Really appreciate your helpful information.
I hope we can figure out with IT soon.

Thank you very much!

Regards,
Jason-JH.Lin

On Mon, 2022-04-18 at 19:03 +0200, Krzysztof Kozlowski wrote:
> On 14/04/2022 05:11, Jason-JH Lin wrote:
> > Hello Rob, Krzysztof,
> > 
> > I found the dt-binding patches in this series never appeared in
> > devicetree-bindings patchwork and trigger the dt-binding check bot.
> > 
> > Do you know the reason for this?
> > Could you help me with this and let me know what should I do to
> > solve
> > this problem?
> 
> Hi,
> 
> All your emails end up regularly in my Gmail spam folder, similarly
> to
> emails from some other Mediatek people (e.g. Rex-BC Chen), so maybe
> that's the cause?
> 
> Why they end up in spam? I don't know, but it would be nice if you
> could
> work on this with your IT department. I know that corporate
> environments
> are tricky to change, but there is not much else to do. Google flags
> your emails always as spam.
> 
> You can see in the headers two DMARC failures:
> dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=QUARANTINE)
> header.from=mediatek.com
> 
> Spamming 27 recipients is maybe another reason...
> 
> Best regards,
> Krzysztof
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek

^ permalink raw reply	[flat|nested] 70+ messages in thread
* Re: [PATCH v18 02/10] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding
@ 2022-04-19  1:53         ` Jason-JH Lin
  0 siblings, 0 replies; 70+ messages in thread
From: Jason-JH Lin @ 2022-04-19  1:53 UTC (permalink / raw)
  To: Krzysztof Kozlowski, Rob Herring, Krzysztof Kozlowski,
	Matthias Brugger, Chun-Kuang Hu, AngeloGioacchino Del Regno
  Cc: Rex-BC Chen (陳柏辰),
	devicetree, linux-arm-kernel, linux-mediatek

Hi Krzysztof,

Really appreciate your helpful information.
I hope we can figure out with IT soon.

Thank you very much!

Regards,
Jason-JH.Lin

On Mon, 2022-04-18 at 19:03 +0200, Krzysztof Kozlowski wrote:
> On 14/04/2022 05:11, Jason-JH Lin wrote:
> > Hello Rob, Krzysztof,
> > 
> > I found the dt-binding patches in this series never appeared in
> > devicetree-bindings patchwork and trigger the dt-binding check bot.
> > 
> > Do you know the reason for this?
> > Could you help me with this and let me know what should I do to
> > solve
> > this problem?
> 
> Hi,
> 
> All your emails end up regularly in my Gmail spam folder, similarly
> to
> emails from some other Mediatek people (e.g. Rex-BC Chen), so maybe
> that's the cause?
> 
> Why they end up in spam? I don't know, but it would be nice if you
> could
> work on this with your IT department. I know that corporate
> environments
> are tricky to change, but there is not much else to do. Google flags
> your emails always as spam.
> 
> You can see in the headers two DMARC failures:
> dmarc=fail (p=QUARANTINE sp=QUARANTINE dis=QUARANTINE)
> header.from=mediatek.com
> 
> Spamming 27 recipients is maybe another reason...
> 
> Best regards,
> Krzysztof
-- 
Jason-JH Lin <jason-jh.lin@mediatek.com>


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

^ permalink raw reply	[flat|nested] 70+ messages in thread
end of thread, other threads:[~2022-04-19  1:55 UTC | newest]

Thread overview: 70+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-12 10:31 [PATCH v18 00/10] Add Mediatek Soc DRM (vdosys0) support for mt8195 jason-jh.lin
2022-04-12 10:31 ` jason-jh.lin
2022-04-12 10:31 ` jason-jh.lin
2022-04-12 10:31 ` [PATCH v18 01/10] dt-bindings: arm: mediatek: mmsys: add power and gce properties jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31 ` [PATCH v18 02/10] dt-bindings: arm: mediatek: mmsys: add mt8195 SoC binding jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-14  3:11   ` Jason-JH Lin
2022-04-14  3:11     ` Jason-JH Lin
2022-04-14  3:11     ` Jason-JH Lin
2022-04-14  3:11     ` Jason-JH Lin
2022-04-18 17:03     ` Krzysztof Kozlowski
2022-04-18 17:03       ` Krzysztof Kozlowski
2022-04-18 17:03       ` Krzysztof Kozlowski
2022-04-19  1:53       ` Jason-JH Lin
2022-04-19  1:53         ` Jason-JH Lin
2022-04-19  1:53         ` Jason-JH Lin
2022-04-12 10:31 ` [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31 ` [PATCH v18 04/10] soc: mediatek: add mtk-mutex " jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31 ` [PATCH v18 05/10] drm/mediatek: add DSC support for mediatek-drm jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31 ` [PATCH v18 06/10] drm/mediatek: add MERGE " jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31 ` [PATCH v18 07/10] drm/mediatek: add mediatek-drm of vdosys0 support for mt8195 jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-14 15:31   ` kernel test robot
2022-04-14 15:31     ` kernel test robot
2022-04-14 15:31     ` kernel test robot
2022-04-14 15:31     ` kernel test robot
2022-04-15  6:27     ` Jason-JH Lin
2022-04-15  6:27       ` Jason-JH Lin
2022-04-15  6:27       ` Jason-JH Lin
2022-04-15  6:27       ` Jason-JH Lin
2022-04-15  6:27       ` Jason-JH Lin
2022-04-12 10:31 ` [PATCH v18 08/10] soc: mediatek: add DDP_DOMPONENT_DITHER0 enum for mt8195 vdosys0 jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-15  6:24   ` Rex-BC Chen
2022-04-15  6:24     ` Rex-BC Chen
2022-04-15  6:24     ` Rex-BC Chen
2022-04-15  8:13     ` Jason-JH Lin
2022-04-15  8:13       ` Jason-JH Lin
2022-04-15  8:13       ` Jason-JH Lin
2022-04-15  8:13       ` Jason-JH Lin
2022-04-12 10:31 ` [PATCH v18 09/10] drm/mediatek: add postfix 0 to DDP_COMPONENT_DITHER " jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31 ` [PATCH v18 10/10] soc: mediatek: remove DDP_DOMPONENT_DITHER enum jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-12 10:31   ` jason-jh.lin
2022-04-13  1:51 [PATCH v18 03/10] soc: mediatek: add mtk-mmsys support for mt8195 vdosys0 kernel test robot
2022-04-13  6:07 ` Dan Carpenter
2022-04-13  6:07 ` Dan Carpenter
2022-04-13  6:07 ` Dan Carpenter
2022-04-13  6:07 ` Dan Carpenter
2022-04-13  6:07 ` Dan Carpenter
2022-04-13  8:43 ` Jason-JH Lin
2022-04-13  8:43   ` Jason-JH Lin
2022-04-13  8:43   ` Jason-JH Lin
2022-04-13  8:43   ` Jason-JH Lin
2022-04-13  8:43   ` Jason-JH Lin

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