* [PATCH 0/1] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-04-08 10:41 ` Allen-KH Cheng
0 siblings, 0 replies; 19+ messages in thread
From: Allen-KH Cheng @ 2022-04-08 10:41 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Allen-KH Cheng
Take vcodec lat and core nodes patch from series 20220330133816.30806-1-allen-kh.cheng@mediatek.com/
This patch is based on matthias.bgg/linux.git, v5.18-next/dts64
We add vcodec lat and core nodes for cell sizes of 2 cells for "dt-bindings:
media: mediatek,vcodec: Fix addressing cell sizes, commit a50e431bbc6".
change history from previous series,
- remove the comment
- vcodec: correct the clk names (remove vdec- prefix)
- vcodec: use ranges for regs of subnodes
- vcodec lat and core: use '-' instead of '_' in the node name, fix indentation and
set mtk-vcodec-lat and mtk-vcodec-core as subnodes of vcodec-dec
Allen-KH Cheng (1):
arm64: dts: mt8192: Add vcodec lat and core nodes
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
1 file changed, 60 insertions(+)
--
2.18.0
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 0/1] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-04-08 10:41 ` Allen-KH Cheng
0 siblings, 0 replies; 19+ messages in thread
From: Allen-KH Cheng @ 2022-04-08 10:41 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Allen-KH Cheng
Take vcodec lat and core nodes patch from series 20220330133816.30806-1-allen-kh.cheng@mediatek.com/
This patch is based on matthias.bgg/linux.git, v5.18-next/dts64
We add vcodec lat and core nodes for cell sizes of 2 cells for "dt-bindings:
media: mediatek,vcodec: Fix addressing cell sizes, commit a50e431bbc6".
change history from previous series,
- remove the comment
- vcodec: correct the clk names (remove vdec- prefix)
- vcodec: use ranges for regs of subnodes
- vcodec lat and core: use '-' instead of '_' in the node name, fix indentation and
set mtk-vcodec-lat and mtk-vcodec-core as subnodes of vcodec-dec
Allen-KH Cheng (1):
arm64: dts: mt8192: Add vcodec lat and core nodes
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
1 file changed, 60 insertions(+)
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 0/1] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-04-08 10:41 ` Allen-KH Cheng
0 siblings, 0 replies; 19+ messages in thread
From: Allen-KH Cheng @ 2022-04-08 10:41 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Allen-KH Cheng
Take vcodec lat and core nodes patch from series 20220330133816.30806-1-allen-kh.cheng@mediatek.com/
This patch is based on matthias.bgg/linux.git, v5.18-next/dts64
We add vcodec lat and core nodes for cell sizes of 2 cells for "dt-bindings:
media: mediatek,vcodec: Fix addressing cell sizes, commit a50e431bbc6".
change history from previous series,
- remove the comment
- vcodec: correct the clk names (remove vdec- prefix)
- vcodec: use ranges for regs of subnodes
- vcodec lat and core: use '-' instead of '_' in the node name, fix indentation and
set mtk-vcodec-lat and mtk-vcodec-core as subnodes of vcodec-dec
Allen-KH Cheng (1):
arm64: dts: mt8192: Add vcodec lat and core nodes
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
1 file changed, 60 insertions(+)
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 19+ messages in thread
* [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
2022-04-08 10:41 ` Allen-KH Cheng
(?)
@ 2022-04-08 10:41 ` Allen-KH Cheng
-1 siblings, 0 replies; 19+ messages in thread
From: Allen-KH Cheng @ 2022-04-08 10:41 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Allen-KH Cheng
Add vcodec lat and core nodes for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 18a58239d6f1..c7f4b2fbb315 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1120,6 +1120,66 @@
power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
};
+ vcodec_dec: vcodec-dec@16000000 {
+ compatible = "mediatek,mt8192-vcodec-dec";
+ reg = <0 0x16000000 0 0x1000>;
+ mediatek,scp = <&scp>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+ dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0x16000000 0 0x26000>;
+
+ vcodec_lat: vcodec-lat@10000 {
+ compatible = "mediatek,mtk-vcodec-lat";
+ reg = <0x0 0x10000 0 0x800>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
+ vcodec_core: vcodec-core@25000 {
+ compatible = "mediatek,mtk-vcodec-core";
+ reg = <0 0x25000 0 0x1000>;
+ interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&vdecsys CLK_VDEC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
+ };
+
larb5: larb@1600d000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1600d000 0 0x1000>;
--
2.18.0
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-04-08 10:41 ` Allen-KH Cheng
0 siblings, 0 replies; 19+ messages in thread
From: Allen-KH Cheng @ 2022-04-08 10:41 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Allen-KH Cheng
Add vcodec lat and core nodes for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 18a58239d6f1..c7f4b2fbb315 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1120,6 +1120,66 @@
power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
};
+ vcodec_dec: vcodec-dec@16000000 {
+ compatible = "mediatek,mt8192-vcodec-dec";
+ reg = <0 0x16000000 0 0x1000>;
+ mediatek,scp = <&scp>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+ dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0x16000000 0 0x26000>;
+
+ vcodec_lat: vcodec-lat@10000 {
+ compatible = "mediatek,mtk-vcodec-lat";
+ reg = <0x0 0x10000 0 0x800>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
+ vcodec_core: vcodec-core@25000 {
+ compatible = "mediatek,mtk-vcodec-core";
+ reg = <0 0x25000 0 0x1000>;
+ interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&vdecsys CLK_VDEC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
+ };
+
larb5: larb@1600d000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1600d000 0 0x1000>;
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 19+ messages in thread
* [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-04-08 10:41 ` Allen-KH Cheng
0 siblings, 0 replies; 19+ messages in thread
From: Allen-KH Cheng @ 2022-04-08 10:41 UTC (permalink / raw)
To: Matthias Brugger, Rob Herring, Krzysztof Kozlowski
Cc: Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Allen-KH Cheng
Add vcodec lat and core nodes for mt8192 SoC.
Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
---
arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
1 file changed, 60 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
index 18a58239d6f1..c7f4b2fbb315 100644
--- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
@@ -1120,6 +1120,66 @@
power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
};
+ vcodec_dec: vcodec-dec@16000000 {
+ compatible = "mediatek,mt8192-vcodec-dec";
+ reg = <0 0x16000000 0 0x1000>;
+ mediatek,scp = <&scp>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
+ dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
+ #address-cells = <2>;
+ #size-cells = <2>;
+ ranges = <0 0 0 0x16000000 0 0x26000>;
+
+ vcodec_lat: vcodec-lat@10000 {
+ compatible = "mediatek,mtk-vcodec-lat";
+ reg = <0x0 0x10000 0 0x800>;
+ interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
+ <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
+ <&vdecsys_soc CLK_VDEC_SOC_LAT>,
+ <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
+ };
+
+ vcodec_core: vcodec-core@25000 {
+ compatible = "mediatek,mtk-vcodec-core";
+ reg = <0 0x25000 0 0x1000>;
+ interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
+ iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
+ <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
+ clocks = <&topckgen CLK_TOP_VDEC_SEL>,
+ <&vdecsys CLK_VDEC_VDEC>,
+ <&vdecsys CLK_VDEC_LAT>,
+ <&vdecsys CLK_VDEC_LARB1>,
+ <&topckgen CLK_TOP_MAINPLL_D4>;
+ clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
+ assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
+ assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
+ power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
+ };
+ };
+
larb5: larb@1600d000 {
compatible = "mediatek,mt8192-smi-larb";
reg = <0 0x1600d000 0 0x1000>;
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
2022-04-08 10:41 ` Allen-KH Cheng
(?)
@ 2022-04-12 23:08 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 19+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-04-12 23:08 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
Hi Allen,
On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 18a58239d6f1..c7f4b2fbb315 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1120,6 +1120,66 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> };
>
> + vcodec_dec: vcodec-dec@16000000 {
> + compatible = "mediatek,mt8192-vcodec-dec";
> + reg = <0 0x16000000 0 0x1000>;
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
The dt-binding says address-cells and size-cells should be 1. Then most of the
extra 0s can be dropped from ranges and the children's regs.
Other than that,
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Thanks,
Nícolas
> + ranges = <0 0 0 0x16000000 0 0x26000>;
> +
> + vcodec_lat: vcodec-lat@10000 {
> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0x0 0x10000 0 0x800>;
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec_core: vcodec-core@25000 {
> + compatible = "mediatek,mtk-vcodec-core";
> + reg = <0 0x25000 0 0x1000>;
> + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys CLK_VDEC_VDEC>,
> + <&vdecsys CLK_VDEC_LAT>,
> + <&vdecsys CLK_VDEC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> + };
> + };
> +
> larb5: larb@1600d000 {
> compatible = "mediatek,mt8192-smi-larb";
> reg = <0 0x1600d000 0 0x1000>;
> --
> 2.18.0
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-04-12 23:08 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 19+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-04-12 23:08 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
Hi Allen,
On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 18a58239d6f1..c7f4b2fbb315 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1120,6 +1120,66 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> };
>
> + vcodec_dec: vcodec-dec@16000000 {
> + compatible = "mediatek,mt8192-vcodec-dec";
> + reg = <0 0x16000000 0 0x1000>;
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
The dt-binding says address-cells and size-cells should be 1. Then most of the
extra 0s can be dropped from ranges and the children's regs.
Other than that,
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Thanks,
Nícolas
> + ranges = <0 0 0 0x16000000 0 0x26000>;
> +
> + vcodec_lat: vcodec-lat@10000 {
> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0x0 0x10000 0 0x800>;
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec_core: vcodec-core@25000 {
> + compatible = "mediatek,mtk-vcodec-core";
> + reg = <0 0x25000 0 0x1000>;
> + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys CLK_VDEC_VDEC>,
> + <&vdecsys CLK_VDEC_LAT>,
> + <&vdecsys CLK_VDEC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> + };
> + };
> +
> larb5: larb@1600d000 {
> compatible = "mediatek,mt8192-smi-larb";
> reg = <0 0x1600d000 0 0x1000>;
> --
> 2.18.0
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-04-12 23:08 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 19+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-04-12 23:08 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
Hi Allen,
On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 18a58239d6f1..c7f4b2fbb315 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1120,6 +1120,66 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> };
>
> + vcodec_dec: vcodec-dec@16000000 {
> + compatible = "mediatek,mt8192-vcodec-dec";
> + reg = <0 0x16000000 0 0x1000>;
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
The dt-binding says address-cells and size-cells should be 1. Then most of the
extra 0s can be dropped from ranges and the children's regs.
Other than that,
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Thanks,
Nícolas
> + ranges = <0 0 0 0x16000000 0 0x26000>;
> +
> + vcodec_lat: vcodec-lat@10000 {
> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0x0 0x10000 0 0x800>;
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec_core: vcodec-core@25000 {
> + compatible = "mediatek,mtk-vcodec-core";
> + reg = <0 0x25000 0 0x1000>;
> + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys CLK_VDEC_VDEC>,
> + <&vdecsys CLK_VDEC_LAT>,
> + <&vdecsys CLK_VDEC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> + };
> + };
> +
> larb5: larb@1600d000 {
> compatible = "mediatek,mt8192-smi-larb";
> reg = <0 0x1600d000 0 0x1000>;
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
2022-04-12 23:08 ` Nícolas F. R. A. Prado
@ 2022-04-13 7:21 ` allen-kh.cheng
-1 siblings, 0 replies; 19+ messages in thread
From: allen-kh.cheng @ 2022-04-13 7:21 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
Hi Nícolas,
On Tue, 2022-04-12 at 19:08 -0400, Nícolas F. R. A. Prado wrote:
> Hi Allen,
>
> On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote:
> > Add vcodec lat and core nodes for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60
> > ++++++++++++++++++++++++
> > 1 file changed, 60 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 18a58239d6f1..c7f4b2fbb315 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1120,6 +1120,66 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_ISP2>;
> > };
> >
> > + vcodec_dec: vcodec-dec@16000000 {
> > + compatible = "mediatek,mt8192-vcodec-dec";
> > + reg = <0 0x16000000 0 0x1000>;
> > + mediatek,scp = <&scp>;
> > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0
> > 0xfff00000>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
>
> The dt-binding says address-cells and size-cells should be 1. Then
> most of the
> extra 0s can be dropped from ranges and the children's regs.
>
> Other than that,
>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
>
> Thanks,
> Nícolas
>
I have checked the description in mediatek,vcodec-subdev-decoder.yaml
address-cells and size-cells are two after the below commit is merged.
media: mediatek,vcodec: Fix addressing cell sizes
linux/kernel/git/next/linux-next.git
commit/id=a50e431bbc6fc5768ed26be5fab5b149b7b8b1fe
Correct me if I got this wrong.
Thanks,
Allen
> > + ranges = <0 0 0 0x16000000 0 0x26000>;
> > +
> > + vcodec_lat: vcodec-lat@10000 {
> > + compatible = "mediatek,mtk-vcodec-lat";
> > + reg = <0x0 0x10000 0 0x800>;
> > + interrupts = <GIC_SPI 426
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > + iommus = <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys_soc
> > CLK_VDEC_SOC_VDEC>,
> > + <&vdecsys_soc
> > CLK_VDEC_SOC_LAT>,
> > + <&vdecsys_soc
> > CLK_VDEC_SOC_LARB1>,
> > + <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + clock-names = "sel", "soc-vdec", "soc-
> > lat", "vdec", "top";
> > + assigned-clocks = <&topckgen
> > CLK_TOP_VDEC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC>;
> > + };
> > +
> > + vcodec_core: vcodec-core@25000 {
> > + compatible = "mediatek,mtk-vcodec-
> > core";
> > + reg = <0 0x25000 0 0x1000>;
> > + interrupts = <GIC_SPI 425
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > + iommus = <&iommu0
> > M4U_PORT_L4_VDEC_MC_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_UFO_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_PP_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_TILE_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_VLD_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_VLD2_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys CLK_VDEC_VDEC>,
> > + <&vdecsys CLK_VDEC_LAT>,
> > + <&vdecsys CLK_VDEC_LARB1>,
> > + <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + clock-names = "sel", "soc-vdec", "soc-
> > lat", "vdec", "top";
> > + assigned-clocks = <&topckgen
> > CLK_TOP_VDEC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC2>;
> > + };
> > + };
> > +
> > larb5: larb@1600d000 {
> > compatible = "mediatek,mt8192-smi-larb";
> > reg = <0 0x1600d000 0 0x1000>;
> > --
> > 2.18.0
> >
> >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-04-13 7:21 ` allen-kh.cheng
0 siblings, 0 replies; 19+ messages in thread
From: allen-kh.cheng @ 2022-04-13 7:21 UTC (permalink / raw)
To: Nícolas F. R. A. Prado
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
Hi Nícolas,
On Tue, 2022-04-12 at 19:08 -0400, Nícolas F. R. A. Prado wrote:
> Hi Allen,
>
> On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote:
> > Add vcodec lat and core nodes for mt8192 SoC.
> >
> > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > Reviewed-by: AngeloGioacchino Del Regno <
> > angelogioacchino.delregno@collabora.com>
> > ---
> > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60
> > ++++++++++++++++++++++++
> > 1 file changed, 60 insertions(+)
> >
> > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > index 18a58239d6f1..c7f4b2fbb315 100644
> > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > @@ -1120,6 +1120,66 @@
> > power-domains = <&spm
> > MT8192_POWER_DOMAIN_ISP2>;
> > };
> >
> > + vcodec_dec: vcodec-dec@16000000 {
> > + compatible = "mediatek,mt8192-vcodec-dec";
> > + reg = <0 0x16000000 0 0x1000>;
> > + mediatek,scp = <&scp>;
> > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0
> > 0xfff00000>;
> > + #address-cells = <2>;
> > + #size-cells = <2>;
>
> The dt-binding says address-cells and size-cells should be 1. Then
> most of the
> extra 0s can be dropped from ranges and the children's regs.
>
> Other than that,
>
> Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
>
> Thanks,
> Nícolas
>
I have checked the description in mediatek,vcodec-subdev-decoder.yaml
address-cells and size-cells are two after the below commit is merged.
media: mediatek,vcodec: Fix addressing cell sizes
linux/kernel/git/next/linux-next.git
commit/id=a50e431bbc6fc5768ed26be5fab5b149b7b8b1fe
Correct me if I got this wrong.
Thanks,
Allen
> > + ranges = <0 0 0 0x16000000 0 0x26000>;
> > +
> > + vcodec_lat: vcodec-lat@10000 {
> > + compatible = "mediatek,mtk-vcodec-lat";
> > + reg = <0x0 0x10000 0 0x800>;
> > + interrupts = <GIC_SPI 426
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > + iommus = <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > + <&iommu0
> > M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys_soc
> > CLK_VDEC_SOC_VDEC>,
> > + <&vdecsys_soc
> > CLK_VDEC_SOC_LAT>,
> > + <&vdecsys_soc
> > CLK_VDEC_SOC_LARB1>,
> > + <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + clock-names = "sel", "soc-vdec", "soc-
> > lat", "vdec", "top";
> > + assigned-clocks = <&topckgen
> > CLK_TOP_VDEC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC>;
> > + };
> > +
> > + vcodec_core: vcodec-core@25000 {
> > + compatible = "mediatek,mtk-vcodec-
> > core";
> > + reg = <0 0x25000 0 0x1000>;
> > + interrupts = <GIC_SPI 425
> > IRQ_TYPE_LEVEL_HIGH 0>;
> > + iommus = <&iommu0
> > M4U_PORT_L4_VDEC_MC_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_UFO_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_PP_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_TILE_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_VLD_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_VLD2_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > + <&iommu0
> > M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > + <&vdecsys CLK_VDEC_VDEC>,
> > + <&vdecsys CLK_VDEC_LAT>,
> > + <&vdecsys CLK_VDEC_LARB1>,
> > + <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + clock-names = "sel", "soc-vdec", "soc-
> > lat", "vdec", "top";
> > + assigned-clocks = <&topckgen
> > CLK_TOP_VDEC_SEL>;
> > + assigned-clock-parents = <&topckgen
> > CLK_TOP_MAINPLL_D4>;
> > + power-domains = <&spm
> > MT8192_POWER_DOMAIN_VDEC2>;
> > + };
> > + };
> > +
> > larb5: larb@1600d000 {
> > compatible = "mediatek,mt8192-smi-larb";
> > reg = <0 0x1600d000 0 0x1000>;
> > --
> > 2.18.0
> >
> >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
2022-04-13 7:21 ` allen-kh.cheng
(?)
@ 2022-04-13 15:29 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 19+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-04-13 15:29 UTC (permalink / raw)
To: allen-kh.cheng
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
On Wed, Apr 13, 2022 at 03:21:29PM +0800, allen-kh.cheng wrote:
> Hi Nícolas,
>
> On Tue, 2022-04-12 at 19:08 -0400, Nícolas F. R. A. Prado wrote:
> > Hi Allen,
> >
> > On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote:
> > > Add vcodec lat and core nodes for mt8192 SoC.
> > >
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > ---
> > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60
> > > ++++++++++++++++++++++++
> > > 1 file changed, 60 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 18a58239d6f1..c7f4b2fbb315 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -1120,6 +1120,66 @@
> > > power-domains = <&spm
> > > MT8192_POWER_DOMAIN_ISP2>;
> > > };
> > >
> > > + vcodec_dec: vcodec-dec@16000000 {
> > > + compatible = "mediatek,mt8192-vcodec-dec";
> > > + reg = <0 0x16000000 0 0x1000>;
> > > + mediatek,scp = <&scp>;
> > > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0
> > > 0xfff00000>;
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> >
> > The dt-binding says address-cells and size-cells should be 1. Then
> > most of the
> > extra 0s can be dropped from ranges and the children's regs.
> >
> > Other than that,
> >
> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> >
> > Thanks,
> > Nícolas
> >
>
> I have checked the description in mediatek,vcodec-subdev-decoder.yaml
>
> address-cells and size-cells are two after the below commit is merged.
>
> media: mediatek,vcodec: Fix addressing cell sizes
> linux/kernel/git/next/linux-next.git
> commit/id=a50e431bbc6fc5768ed26be5fab5b149b7b8b1fe
Hi Allen,
yes, you're right. I missed that commit, sorry. This patch is perfectly fine
as it is then.
Thanks,
Nícolas
>
> Correct me if I got this wrong.
>
> Thanks,
> Allen
>
> > > + ranges = <0 0 0 0x16000000 0 0x26000>;
> > > +
> > > + vcodec_lat: vcodec-lat@10000 {
> > > + compatible = "mediatek,mtk-vcodec-lat";
> > > + reg = <0x0 0x10000 0 0x800>;
> > > + interrupts = <GIC_SPI 426
> > > IRQ_TYPE_LEVEL_HIGH 0>;
> > > + iommus = <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > > + <&vdecsys_soc
> > > CLK_VDEC_SOC_VDEC>,
> > > + <&vdecsys_soc
> > > CLK_VDEC_SOC_LAT>,
> > > + <&vdecsys_soc
> > > CLK_VDEC_SOC_LARB1>,
> > > + <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + clock-names = "sel", "soc-vdec", "soc-
> > > lat", "vdec", "top";
> > > + assigned-clocks = <&topckgen
> > > CLK_TOP_VDEC_SEL>;
> > > + assigned-clock-parents = <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + power-domains = <&spm
> > > MT8192_POWER_DOMAIN_VDEC>;
> > > + };
> > > +
> > > + vcodec_core: vcodec-core@25000 {
> > > + compatible = "mediatek,mtk-vcodec-
> > > core";
> > > + reg = <0 0x25000 0 0x1000>;
> > > + interrupts = <GIC_SPI 425
> > > IRQ_TYPE_LEVEL_HIGH 0>;
> > > + iommus = <&iommu0
> > > M4U_PORT_L4_VDEC_MC_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_UFO_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PP_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_TILE_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_VLD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_VLD2_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > > + <&vdecsys CLK_VDEC_VDEC>,
> > > + <&vdecsys CLK_VDEC_LAT>,
> > > + <&vdecsys CLK_VDEC_LARB1>,
> > > + <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + clock-names = "sel", "soc-vdec", "soc-
> > > lat", "vdec", "top";
> > > + assigned-clocks = <&topckgen
> > > CLK_TOP_VDEC_SEL>;
> > > + assigned-clock-parents = <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + power-domains = <&spm
> > > MT8192_POWER_DOMAIN_VDEC2>;
> > > + };
> > > + };
> > > +
> > > larb5: larb@1600d000 {
> > > compatible = "mediatek,mt8192-smi-larb";
> > > reg = <0 0x1600d000 0 0x1000>;
> > > --
> > > 2.18.0
> > >
> > >
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-04-13 15:29 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 19+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-04-13 15:29 UTC (permalink / raw)
To: allen-kh.cheng
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
On Wed, Apr 13, 2022 at 03:21:29PM +0800, allen-kh.cheng wrote:
> Hi Nícolas,
>
> On Tue, 2022-04-12 at 19:08 -0400, Nícolas F. R. A. Prado wrote:
> > Hi Allen,
> >
> > On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote:
> > > Add vcodec lat and core nodes for mt8192 SoC.
> > >
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > ---
> > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60
> > > ++++++++++++++++++++++++
> > > 1 file changed, 60 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 18a58239d6f1..c7f4b2fbb315 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -1120,6 +1120,66 @@
> > > power-domains = <&spm
> > > MT8192_POWER_DOMAIN_ISP2>;
> > > };
> > >
> > > + vcodec_dec: vcodec-dec@16000000 {
> > > + compatible = "mediatek,mt8192-vcodec-dec";
> > > + reg = <0 0x16000000 0 0x1000>;
> > > + mediatek,scp = <&scp>;
> > > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0
> > > 0xfff00000>;
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> >
> > The dt-binding says address-cells and size-cells should be 1. Then
> > most of the
> > extra 0s can be dropped from ranges and the children's regs.
> >
> > Other than that,
> >
> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> >
> > Thanks,
> > Nícolas
> >
>
> I have checked the description in mediatek,vcodec-subdev-decoder.yaml
>
> address-cells and size-cells are two after the below commit is merged.
>
> media: mediatek,vcodec: Fix addressing cell sizes
> linux/kernel/git/next/linux-next.git
> commit/id=a50e431bbc6fc5768ed26be5fab5b149b7b8b1fe
Hi Allen,
yes, you're right. I missed that commit, sorry. This patch is perfectly fine
as it is then.
Thanks,
Nícolas
>
> Correct me if I got this wrong.
>
> Thanks,
> Allen
>
> > > + ranges = <0 0 0 0x16000000 0 0x26000>;
> > > +
> > > + vcodec_lat: vcodec-lat@10000 {
> > > + compatible = "mediatek,mtk-vcodec-lat";
> > > + reg = <0x0 0x10000 0 0x800>;
> > > + interrupts = <GIC_SPI 426
> > > IRQ_TYPE_LEVEL_HIGH 0>;
> > > + iommus = <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > > + <&vdecsys_soc
> > > CLK_VDEC_SOC_VDEC>,
> > > + <&vdecsys_soc
> > > CLK_VDEC_SOC_LAT>,
> > > + <&vdecsys_soc
> > > CLK_VDEC_SOC_LARB1>,
> > > + <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + clock-names = "sel", "soc-vdec", "soc-
> > > lat", "vdec", "top";
> > > + assigned-clocks = <&topckgen
> > > CLK_TOP_VDEC_SEL>;
> > > + assigned-clock-parents = <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + power-domains = <&spm
> > > MT8192_POWER_DOMAIN_VDEC>;
> > > + };
> > > +
> > > + vcodec_core: vcodec-core@25000 {
> > > + compatible = "mediatek,mtk-vcodec-
> > > core";
> > > + reg = <0 0x25000 0 0x1000>;
> > > + interrupts = <GIC_SPI 425
> > > IRQ_TYPE_LEVEL_HIGH 0>;
> > > + iommus = <&iommu0
> > > M4U_PORT_L4_VDEC_MC_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_UFO_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PP_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_TILE_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_VLD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_VLD2_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > > + <&vdecsys CLK_VDEC_VDEC>,
> > > + <&vdecsys CLK_VDEC_LAT>,
> > > + <&vdecsys CLK_VDEC_LARB1>,
> > > + <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + clock-names = "sel", "soc-vdec", "soc-
> > > lat", "vdec", "top";
> > > + assigned-clocks = <&topckgen
> > > CLK_TOP_VDEC_SEL>;
> > > + assigned-clock-parents = <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + power-domains = <&spm
> > > MT8192_POWER_DOMAIN_VDEC2>;
> > > + };
> > > + };
> > > +
> > > larb5: larb@1600d000 {
> > > compatible = "mediatek,mt8192-smi-larb";
> > > reg = <0 0x1600d000 0 0x1000>;
> > > --
> > > 2.18.0
> > >
> > >
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-04-13 15:29 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 19+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-04-13 15:29 UTC (permalink / raw)
To: allen-kh.cheng
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
On Wed, Apr 13, 2022 at 03:21:29PM +0800, allen-kh.cheng wrote:
> Hi Nícolas,
>
> On Tue, 2022-04-12 at 19:08 -0400, Nícolas F. R. A. Prado wrote:
> > Hi Allen,
> >
> > On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote:
> > > Add vcodec lat and core nodes for mt8192 SoC.
> > >
> > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > Reviewed-by: AngeloGioacchino Del Regno <
> > > angelogioacchino.delregno@collabora.com>
> > > ---
> > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60
> > > ++++++++++++++++++++++++
> > > 1 file changed, 60 insertions(+)
> > >
> > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > index 18a58239d6f1..c7f4b2fbb315 100644
> > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > @@ -1120,6 +1120,66 @@
> > > power-domains = <&spm
> > > MT8192_POWER_DOMAIN_ISP2>;
> > > };
> > >
> > > + vcodec_dec: vcodec-dec@16000000 {
> > > + compatible = "mediatek,mt8192-vcodec-dec";
> > > + reg = <0 0x16000000 0 0x1000>;
> > > + mediatek,scp = <&scp>;
> > > + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> > > + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0
> > > 0xfff00000>;
> > > + #address-cells = <2>;
> > > + #size-cells = <2>;
> >
> > The dt-binding says address-cells and size-cells should be 1. Then
> > most of the
> > extra 0s can be dropped from ranges and the children's regs.
> >
> > Other than that,
> >
> > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> >
> > Thanks,
> > Nícolas
> >
>
> I have checked the description in mediatek,vcodec-subdev-decoder.yaml
>
> address-cells and size-cells are two after the below commit is merged.
>
> media: mediatek,vcodec: Fix addressing cell sizes
> linux/kernel/git/next/linux-next.git
> commit/id=a50e431bbc6fc5768ed26be5fab5b149b7b8b1fe
Hi Allen,
yes, you're right. I missed that commit, sorry. This patch is perfectly fine
as it is then.
Thanks,
Nícolas
>
> Correct me if I got this wrong.
>
> Thanks,
> Allen
>
> > > + ranges = <0 0 0 0x16000000 0 0x26000>;
> > > +
> > > + vcodec_lat: vcodec-lat@10000 {
> > > + compatible = "mediatek,mtk-vcodec-lat";
> > > + reg = <0x0 0x10000 0 0x800>;
> > > + interrupts = <GIC_SPI 426
> > > IRQ_TYPE_LEVEL_HIGH 0>;
> > > + iommus = <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > > + <&vdecsys_soc
> > > CLK_VDEC_SOC_VDEC>,
> > > + <&vdecsys_soc
> > > CLK_VDEC_SOC_LAT>,
> > > + <&vdecsys_soc
> > > CLK_VDEC_SOC_LARB1>,
> > > + <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + clock-names = "sel", "soc-vdec", "soc-
> > > lat", "vdec", "top";
> > > + assigned-clocks = <&topckgen
> > > CLK_TOP_VDEC_SEL>;
> > > + assigned-clock-parents = <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + power-domains = <&spm
> > > MT8192_POWER_DOMAIN_VDEC>;
> > > + };
> > > +
> > > + vcodec_core: vcodec-core@25000 {
> > > + compatible = "mediatek,mtk-vcodec-
> > > core";
> > > + reg = <0 0x25000 0 0x1000>;
> > > + interrupts = <GIC_SPI 425
> > > IRQ_TYPE_LEVEL_HIGH 0>;
> > > + iommus = <&iommu0
> > > M4U_PORT_L4_VDEC_MC_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_UFO_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PP_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_TILE_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_VLD_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_VLD2_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > > + <&iommu0
> > > M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > > + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> > > + <&vdecsys CLK_VDEC_VDEC>,
> > > + <&vdecsys CLK_VDEC_LAT>,
> > > + <&vdecsys CLK_VDEC_LARB1>,
> > > + <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + clock-names = "sel", "soc-vdec", "soc-
> > > lat", "vdec", "top";
> > > + assigned-clocks = <&topckgen
> > > CLK_TOP_VDEC_SEL>;
> > > + assigned-clock-parents = <&topckgen
> > > CLK_TOP_MAINPLL_D4>;
> > > + power-domains = <&spm
> > > MT8192_POWER_DOMAIN_VDEC2>;
> > > + };
> > > + };
> > > +
> > > larb5: larb@1600d000 {
> > > compatible = "mediatek,mt8192-smi-larb";
> > > reg = <0 0x1600d000 0 0x1000>;
> > > --
> > > 2.18.0
> > >
> > >
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
2022-04-13 15:29 ` Nícolas F. R. A. Prado
@ 2022-05-05 13:41 ` allen-kh.cheng
-1 siblings, 0 replies; 19+ messages in thread
From: allen-kh.cheng @ 2022-05-05 13:41 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Nícolas F. R. A. Prado
Hi Matthias,
Do you have any comments on this PATCH?
Thanks,
Allen
On Wed, 2022-04-13 at 11:29 -0400, Nícolas F. R. A. Prado wrote:
> On Wed, Apr 13, 2022 at 03:21:29PM +0800, allen-kh.cheng wrote:
> > Hi Nícolas,
> >
> > On Tue, 2022-04-12 at 19:08 -0400, Nícolas F. R. A. Prado wrote:
> > > Hi Allen,
> > >
> > > On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote:
> > > > Add vcodec lat and core nodes for mt8192 SoC.
> > > >
> > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > ---
> > > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60
> > > > ++++++++++++++++++++++++
> > > > 1 file changed, 60 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > index 18a58239d6f1..c7f4b2fbb315 100644
> > > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > @@ -1120,6 +1120,66 @@
> > > > power-domains = <&spm
> > > > MT8192_POWER_DOMAIN_ISP2>;
> > > > };
> > > >
> > > > + vcodec_dec: vcodec-dec@16000000 {
> > > > + compatible = "mediatek,mt8192-vcodec-
> > > > dec";
> > > > + reg = <0 0x16000000 0 0x1000>;
> > > > + mediatek,scp = <&scp>;
> > > > + iommus = <&iommu0
> > > > M4U_PORT_L4_VDEC_MC_EXT>;
> > > > + dma-ranges = <0x1 0x0 0x0 0x40000000
> > > > 0x0
> > > > 0xfff00000>;
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > >
> > > The dt-binding says address-cells and size-cells should be 1.
> > > Then
> > > most of the
> > > extra 0s can be dropped from ranges and the children's regs.
> > >
> > > Other than that,
> > >
> > > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > >
> > > Thanks,
> > > Nícolas
> > >
> >
> > I have checked the description in mediatek,vcodec-subdev-
> > decoder.yaml
> >
> > address-cells and size-cells are two after the below commit is
> > merged.
> >
> > media: mediatek,vcodec: Fix addressing cell sizes
> > linux/kernel/git/next/linux-next.git
> > commit/id=a50e431bbc6fc5768ed26be5fab5b149b7b8b1fe
>
> Hi Allen,
>
> yes, you're right. I missed that commit, sorry. This patch is
> perfectly fine
> as it is then.
>
> Thanks,
> Nícolas
>
> >
> > Correct me if I got this wrong.
> >
> > Thanks,
> > Allen
> >
> > > > + ranges = <0 0 0 0x16000000 0 0x26000>;
> > > > +
> > > > + vcodec_lat: vcodec-lat@10000 {
> > > > + compatible = "mediatek,mtk-
> > > > vcodec-lat";
> > > > + reg = <0x0 0x10000 0 0x800>;
> > > > + interrupts = <GIC_SPI 426
> > > > IRQ_TYPE_LEVEL_HIGH 0>;
> > > > + iommus = <&iommu0
> > > > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > > > + clocks = <&topckgen
> > > > CLK_TOP_VDEC_SEL>,
> > > > + <&vdecsys_soc
> > > > CLK_VDEC_SOC_VDEC>,
> > > > + <&vdecsys_soc
> > > > CLK_VDEC_SOC_LAT>,
> > > > + <&vdecsys_soc
> > > > CLK_VDEC_SOC_LARB1>,
> > > > + <&topckgen
> > > > CLK_TOP_MAINPLL_D4>;
> > > > + clock-names = "sel", "soc-
> > > > vdec", "soc-
> > > > lat", "vdec", "top";
> > > > + assigned-clocks = <&topckgen
> > > > CLK_TOP_VDEC_SEL>;
> > > > + assigned-clock-parents =
> > > > <&topckgen
> > > > CLK_TOP_MAINPLL_D4>;
> > > > + power-domains = <&spm
> > > > MT8192_POWER_DOMAIN_VDEC>;
> > > > + };
> > > > +
> > > > + vcodec_core: vcodec-core@25000 {
> > > > + compatible = "mediatek,mtk-
> > > > vcodec-
> > > > core";
> > > > + reg = <0 0x25000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 425
> > > > IRQ_TYPE_LEVEL_HIGH 0>;
> > > > + iommus = <&iommu0
> > > > M4U_PORT_L4_VDEC_MC_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_UFO_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_PP_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_TILE_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_VLD_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_VLD2_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > > > + clocks = <&topckgen
> > > > CLK_TOP_VDEC_SEL>,
> > > > + <&vdecsys
> > > > CLK_VDEC_VDEC>,
> > > > + <&vdecsys
> > > > CLK_VDEC_LAT>,
> > > > + <&vdecsys
> > > > CLK_VDEC_LARB1>,
> > > > + <&topckgen
> > > > CLK_TOP_MAINPLL_D4>;
> > > > + clock-names = "sel", "soc-
> > > > vdec", "soc-
> > > > lat", "vdec", "top";
> > > > + assigned-clocks = <&topckgen
> > > > CLK_TOP_VDEC_SEL>;
> > > > + assigned-clock-parents =
> > > > <&topckgen
> > > > CLK_TOP_MAINPLL_D4>;
> > > > + power-domains = <&spm
> > > > MT8192_POWER_DOMAIN_VDEC2>;
> > > > + };
> > > > + };
> > > > +
> > > > larb5: larb@1600d000 {
> > > > compatible = "mediatek,mt8192-smi-
> > > > larb";
> > > > reg = <0 0x1600d000 0 0x1000>;
> > > > --
> > > > 2.18.0
> > > >
> > > >
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-05-05 13:41 ` allen-kh.cheng
0 siblings, 0 replies; 19+ messages in thread
From: allen-kh.cheng @ 2022-05-05 13:41 UTC (permalink / raw)
To: Matthias Brugger
Cc: Rob Herring, Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu, Nícolas F. R. A. Prado
Hi Matthias,
Do you have any comments on this PATCH?
Thanks,
Allen
On Wed, 2022-04-13 at 11:29 -0400, Nícolas F. R. A. Prado wrote:
> On Wed, Apr 13, 2022 at 03:21:29PM +0800, allen-kh.cheng wrote:
> > Hi Nícolas,
> >
> > On Tue, 2022-04-12 at 19:08 -0400, Nícolas F. R. A. Prado wrote:
> > > Hi Allen,
> > >
> > > On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote:
> > > > Add vcodec lat and core nodes for mt8192 SoC.
> > > >
> > > > Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> > > > Reviewed-by: AngeloGioacchino Del Regno <
> > > > angelogioacchino.delregno@collabora.com>
> > > > ---
> > > > arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60
> > > > ++++++++++++++++++++++++
> > > > 1 file changed, 60 insertions(+)
> > > >
> > > > diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > index 18a58239d6f1..c7f4b2fbb315 100644
> > > > --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> > > > @@ -1120,6 +1120,66 @@
> > > > power-domains = <&spm
> > > > MT8192_POWER_DOMAIN_ISP2>;
> > > > };
> > > >
> > > > + vcodec_dec: vcodec-dec@16000000 {
> > > > + compatible = "mediatek,mt8192-vcodec-
> > > > dec";
> > > > + reg = <0 0x16000000 0 0x1000>;
> > > > + mediatek,scp = <&scp>;
> > > > + iommus = <&iommu0
> > > > M4U_PORT_L4_VDEC_MC_EXT>;
> > > > + dma-ranges = <0x1 0x0 0x0 0x40000000
> > > > 0x0
> > > > 0xfff00000>;
> > > > + #address-cells = <2>;
> > > > + #size-cells = <2>;
> > >
> > > The dt-binding says address-cells and size-cells should be 1.
> > > Then
> > > most of the
> > > extra 0s can be dropped from ranges and the children's regs.
> > >
> > > Other than that,
> > >
> > > Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
> > >
> > > Thanks,
> > > Nícolas
> > >
> >
> > I have checked the description in mediatek,vcodec-subdev-
> > decoder.yaml
> >
> > address-cells and size-cells are two after the below commit is
> > merged.
> >
> > media: mediatek,vcodec: Fix addressing cell sizes
> > linux/kernel/git/next/linux-next.git
> > commit/id=a50e431bbc6fc5768ed26be5fab5b149b7b8b1fe
>
> Hi Allen,
>
> yes, you're right. I missed that commit, sorry. This patch is
> perfectly fine
> as it is then.
>
> Thanks,
> Nícolas
>
> >
> > Correct me if I got this wrong.
> >
> > Thanks,
> > Allen
> >
> > > > + ranges = <0 0 0 0x16000000 0 0x26000>;
> > > > +
> > > > + vcodec_lat: vcodec-lat@10000 {
> > > > + compatible = "mediatek,mtk-
> > > > vcodec-lat";
> > > > + reg = <0x0 0x10000 0 0x800>;
> > > > + interrupts = <GIC_SPI 426
> > > > IRQ_TYPE_LEVEL_HIGH 0>;
> > > > + iommus = <&iommu0
> > > > M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> > > > + clocks = <&topckgen
> > > > CLK_TOP_VDEC_SEL>,
> > > > + <&vdecsys_soc
> > > > CLK_VDEC_SOC_VDEC>,
> > > > + <&vdecsys_soc
> > > > CLK_VDEC_SOC_LAT>,
> > > > + <&vdecsys_soc
> > > > CLK_VDEC_SOC_LARB1>,
> > > > + <&topckgen
> > > > CLK_TOP_MAINPLL_D4>;
> > > > + clock-names = "sel", "soc-
> > > > vdec", "soc-
> > > > lat", "vdec", "top";
> > > > + assigned-clocks = <&topckgen
> > > > CLK_TOP_VDEC_SEL>;
> > > > + assigned-clock-parents =
> > > > <&topckgen
> > > > CLK_TOP_MAINPLL_D4>;
> > > > + power-domains = <&spm
> > > > MT8192_POWER_DOMAIN_VDEC>;
> > > > + };
> > > > +
> > > > + vcodec_core: vcodec-core@25000 {
> > > > + compatible = "mediatek,mtk-
> > > > vcodec-
> > > > core";
> > > > + reg = <0 0x25000 0 0x1000>;
> > > > + interrupts = <GIC_SPI 425
> > > > IRQ_TYPE_LEVEL_HIGH 0>;
> > > > + iommus = <&iommu0
> > > > M4U_PORT_L4_VDEC_MC_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_UFO_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_PP_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_TILE_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_VLD_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_VLD2_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> > > > + <&iommu0
> > > > M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> > > > + clocks = <&topckgen
> > > > CLK_TOP_VDEC_SEL>,
> > > > + <&vdecsys
> > > > CLK_VDEC_VDEC>,
> > > > + <&vdecsys
> > > > CLK_VDEC_LAT>,
> > > > + <&vdecsys
> > > > CLK_VDEC_LARB1>,
> > > > + <&topckgen
> > > > CLK_TOP_MAINPLL_D4>;
> > > > + clock-names = "sel", "soc-
> > > > vdec", "soc-
> > > > lat", "vdec", "top";
> > > > + assigned-clocks = <&topckgen
> > > > CLK_TOP_VDEC_SEL>;
> > > > + assigned-clock-parents =
> > > > <&topckgen
> > > > CLK_TOP_MAINPLL_D4>;
> > > > + power-domains = <&spm
> > > > MT8192_POWER_DOMAIN_VDEC2>;
> > > > + };
> > > > + };
> > > > +
> > > > larb5: larb@1600d000 {
> > > > compatible = "mediatek,mt8192-smi-
> > > > larb";
> > > > reg = <0 0x1600d000 0 0x1000>;
> > > > --
> > > > 2.18.0
> > > >
> > > >
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
2022-04-08 10:41 ` Allen-KH Cheng
(?)
@ 2022-05-17 15:52 ` Nícolas F. R. A. Prado
-1 siblings, 0 replies; 19+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-05-17 15:52 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Hi,
With the new mt8192 scp.img firmware merged on linux-firmware [1] and the
mtk-vcodec decoder support for mt8192 merged in the media tree [2], the DT nodes
for the decoder added in this patch are the last missing piece to have the
decoder usable on mt8192-based machines.
With this patch applied, I was able to run fluster [3] on
mt8192-asurada-spherion and obtain the following results:
VP8: 59/61
VP9: 249/303
H.264: 92/135
So,
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Thanks,
Nícolas
[1] https://lore.kernel.org/all/CA+5PVA43SgXKz5EA6RTk74FxiDALy899G1Rvi_aO=q9Yd_pCKw@mail.gmail.com/
[2] https://lore.kernel.org/all/875b24355315311db3a0c846be5f553b3d0c7498.camel@mediatek.com/
[3] https://github.com/fluendo/fluster
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 18a58239d6f1..c7f4b2fbb315 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1120,6 +1120,66 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> };
>
> + vcodec_dec: vcodec-dec@16000000 {
> + compatible = "mediatek,mt8192-vcodec-dec";
> + reg = <0 0x16000000 0 0x1000>;
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0 0 0x16000000 0 0x26000>;
> +
> + vcodec_lat: vcodec-lat@10000 {
> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0x0 0x10000 0 0x800>;
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec_core: vcodec-core@25000 {
> + compatible = "mediatek,mtk-vcodec-core";
> + reg = <0 0x25000 0 0x1000>;
> + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys CLK_VDEC_VDEC>,
> + <&vdecsys CLK_VDEC_LAT>,
> + <&vdecsys CLK_VDEC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> + };
> + };
> +
> larb5: larb@1600d000 {
> compatible = "mediatek,mt8192-smi-larb";
> reg = <0 0x1600d000 0 0x1000>;
> --
> 2.18.0
>
>
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-05-17 15:52 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 19+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-05-17 15:52 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Hi,
With the new mt8192 scp.img firmware merged on linux-firmware [1] and the
mtk-vcodec decoder support for mt8192 merged in the media tree [2], the DT nodes
for the decoder added in this patch are the last missing piece to have the
decoder usable on mt8192-based machines.
With this patch applied, I was able to run fluster [3] on
mt8192-asurada-spherion and obtain the following results:
VP8: 59/61
VP9: 249/303
H.264: 92/135
So,
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Thanks,
Nícolas
[1] https://lore.kernel.org/all/CA+5PVA43SgXKz5EA6RTk74FxiDALy899G1Rvi_aO=q9Yd_pCKw@mail.gmail.com/
[2] https://lore.kernel.org/all/875b24355315311db3a0c846be5f553b3d0c7498.camel@mediatek.com/
[3] https://github.com/fluendo/fluster
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 18a58239d6f1..c7f4b2fbb315 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1120,6 +1120,66 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> };
>
> + vcodec_dec: vcodec-dec@16000000 {
> + compatible = "mediatek,mt8192-vcodec-dec";
> + reg = <0 0x16000000 0 0x1000>;
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0 0 0x16000000 0 0x26000>;
> +
> + vcodec_lat: vcodec-lat@10000 {
> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0x0 0x10000 0 0x800>;
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec_core: vcodec-core@25000 {
> + compatible = "mediatek,mtk-vcodec-core";
> + reg = <0 0x25000 0 0x1000>;
> + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys CLK_VDEC_VDEC>,
> + <&vdecsys CLK_VDEC_LAT>,
> + <&vdecsys CLK_VDEC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> + };
> + };
> +
> larb5: larb@1600d000 {
> compatible = "mediatek,mt8192-smi-larb";
> reg = <0 0x1600d000 0 0x1000>;
> --
> 2.18.0
>
>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 19+ messages in thread
* Re: [PATCH 1/1] arm64: dts: mt8192: Add vcodec lat and core nodes
@ 2022-05-17 15:52 ` Nícolas F. R. A. Prado
0 siblings, 0 replies; 19+ messages in thread
From: Nícolas F. R. A. Prado @ 2022-05-17 15:52 UTC (permalink / raw)
To: Allen-KH Cheng
Cc: Matthias Brugger, Rob Herring, Krzysztof Kozlowski,
Project_Global_Chrome_Upstream_Group, devicetree,
linux-arm-kernel, linux-kernel, linux-mediatek, Chen-Yu Tsai,
Ryder Lee, Hui Liu
On Fri, Apr 08, 2022 at 06:41:24PM +0800, Allen-KH Cheng wrote:
> Add vcodec lat and core nodes for mt8192 SoC.
>
> Signed-off-by: Allen-KH Cheng <allen-kh.cheng@mediatek.com>
> Reviewed-by: AngeloGioacchino Del Regno <angelogioacchino.delregno@collabora.com>
Hi,
With the new mt8192 scp.img firmware merged on linux-firmware [1] and the
mtk-vcodec decoder support for mt8192 merged in the media tree [2], the DT nodes
for the decoder added in this patch are the last missing piece to have the
decoder usable on mt8192-based machines.
With this patch applied, I was able to run fluster [3] on
mt8192-asurada-spherion and obtain the following results:
VP8: 59/61
VP9: 249/303
H.264: 92/135
So,
Reviewed-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Tested-by: Nícolas F. R. A. Prado <nfraprado@collabora.com>
Thanks,
Nícolas
[1] https://lore.kernel.org/all/CA+5PVA43SgXKz5EA6RTk74FxiDALy899G1Rvi_aO=q9Yd_pCKw@mail.gmail.com/
[2] https://lore.kernel.org/all/875b24355315311db3a0c846be5f553b3d0c7498.camel@mediatek.com/
[3] https://github.com/fluendo/fluster
> ---
> arch/arm64/boot/dts/mediatek/mt8192.dtsi | 60 ++++++++++++++++++++++++
> 1 file changed, 60 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/mediatek/mt8192.dtsi b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> index 18a58239d6f1..c7f4b2fbb315 100644
> --- a/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> +++ b/arch/arm64/boot/dts/mediatek/mt8192.dtsi
> @@ -1120,6 +1120,66 @@
> power-domains = <&spm MT8192_POWER_DOMAIN_ISP2>;
> };
>
> + vcodec_dec: vcodec-dec@16000000 {
> + compatible = "mediatek,mt8192-vcodec-dec";
> + reg = <0 0x16000000 0 0x1000>;
> + mediatek,scp = <&scp>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>;
> + dma-ranges = <0x1 0x0 0x0 0x40000000 0x0 0xfff00000>;
> + #address-cells = <2>;
> + #size-cells = <2>;
> + ranges = <0 0 0 0x16000000 0 0x26000>;
> +
> + vcodec_lat: vcodec-lat@10000 {
> + compatible = "mediatek,mtk-vcodec-lat";
> + reg = <0x0 0x10000 0 0x800>;
> + interrupts = <GIC_SPI 426 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_TILE_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_WDMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_LAT0_RG_CTRL_DMA_EXT>,
> + <&iommu0 M4U_PORT_L5_VDEC_UFO_ENC_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys_soc CLK_VDEC_SOC_VDEC>,
> + <&vdecsys_soc CLK_VDEC_SOC_LAT>,
> + <&vdecsys_soc CLK_VDEC_SOC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC>;
> + };
> +
> + vcodec_core: vcodec-core@25000 {
> + compatible = "mediatek,mtk-vcodec-core";
> + reg = <0 0x25000 0 0x1000>;
> + interrupts = <GIC_SPI 425 IRQ_TYPE_LEVEL_HIGH 0>;
> + iommus = <&iommu0 M4U_PORT_L4_VDEC_MC_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_UFO_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_RD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PRED_WR_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_PPWRAP_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_TILE_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_VLD2_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_AVC_MV_EXT>,
> + <&iommu0 M4U_PORT_L4_VDEC_RG_CTRL_DMA_EXT>;
> + clocks = <&topckgen CLK_TOP_VDEC_SEL>,
> + <&vdecsys CLK_VDEC_VDEC>,
> + <&vdecsys CLK_VDEC_LAT>,
> + <&vdecsys CLK_VDEC_LARB1>,
> + <&topckgen CLK_TOP_MAINPLL_D4>;
> + clock-names = "sel", "soc-vdec", "soc-lat", "vdec", "top";
> + assigned-clocks = <&topckgen CLK_TOP_VDEC_SEL>;
> + assigned-clock-parents = <&topckgen CLK_TOP_MAINPLL_D4>;
> + power-domains = <&spm MT8192_POWER_DOMAIN_VDEC2>;
> + };
> + };
> +
> larb5: larb@1600d000 {
> compatible = "mediatek,mt8192-smi-larb";
> reg = <0 0x1600d000 0 0x1000>;
> --
> 2.18.0
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 19+ messages in thread
end of thread, other threads:[~2022-05-17 15:53 UTC | newest]
Thread overview: 19+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-08 10:41 [PATCH 0/1] arm64: dts: mt8192: Add vcodec lat and core nodes Allen-KH Cheng
2022-04-08 10:41 ` Allen-KH Cheng
2022-04-08 10:41 ` Allen-KH Cheng
2022-04-08 10:41 ` [PATCH 1/1] " Allen-KH Cheng
2022-04-08 10:41 ` Allen-KH Cheng
2022-04-08 10:41 ` Allen-KH Cheng
2022-04-12 23:08 ` Nícolas F. R. A. Prado
2022-04-12 23:08 ` Nícolas F. R. A. Prado
2022-04-12 23:08 ` Nícolas F. R. A. Prado
2022-04-13 7:21 ` allen-kh.cheng
2022-04-13 7:21 ` allen-kh.cheng
2022-04-13 15:29 ` Nícolas F. R. A. Prado
2022-04-13 15:29 ` Nícolas F. R. A. Prado
2022-04-13 15:29 ` Nícolas F. R. A. Prado
2022-05-05 13:41 ` allen-kh.cheng
2022-05-05 13:41 ` allen-kh.cheng
2022-05-17 15:52 ` Nícolas F. R. A. Prado
2022-05-17 15:52 ` Nícolas F. R. A. Prado
2022-05-17 15:52 ` Nícolas F. R. A. Prado
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.