From: Heiko Stuebner <heiko@sntech.de> To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, liush@allwinnertech.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, drew@beagleboard.org, hch@lst.de, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, Heiko Stuebner <heiko@sntech.de> Subject: [PATCH v9 05/12] riscv: extend concatenated alternatives-lines to the same length Date: Wed, 13 Apr 2022 05:03:00 +0200 [thread overview] Message-ID: <20220413030307.133807-6-heiko@sntech.de> (raw) In-Reply-To: <20220413030307.133807-1-heiko@sntech.de> ALT_NEW_CONTENT already uses same-length assembler lines, so extend this to the other elements as well. This makes it more readable when these elements need to be extended in the future. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- arch/riscv/include/asm/alternative-macros.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h index 9e04cd53afc8..8c2bbc7bbe50 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -62,14 +62,14 @@ #include <asm/asm.h> #include <linux/stringify.h> -#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \ - RISCV_PTR " " oldptr "\n" \ - RISCV_PTR " " newptr "\n" \ - REG_ASM " " vendor_id "\n" \ - REG_ASM " " newlen "\n" \ +#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \ + RISCV_PTR " " oldptr "\n" \ + RISCV_PTR " " newptr "\n" \ + REG_ASM " " vendor_id "\n" \ + REG_ASM " " newlen "\n" \ ".word " errata_id "\n" -#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \ +#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \ ".if " __stringify(enable) " == 1\n" \ ".pushsection .alternative, \"a\"\n" \ ALT_ENTRY("886b", "888f", __stringify(vendor_id), __stringify(errata_id), "889f - 888f") \ @@ -83,10 +83,10 @@ ".org . - (889b - 888b) + (887b - 886b)\n" \ ".endif\n" -#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \ - "886 :\n" \ - old_c "\n" \ - "887 :\n" \ +#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \ + "886 :\n" \ + old_c "\n" \ + "887 :\n" \ ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \ -- 2.35.1
WARNING: multiple messages have this Message-ID (diff)
From: Heiko Stuebner <heiko@sntech.de> To: palmer@dabbelt.com, paul.walmsley@sifive.com, aou@eecs.berkeley.edu Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, wefu@redhat.com, liush@allwinnertech.com, guoren@kernel.org, atishp@atishpatra.org, anup@brainfault.org, drew@beagleboard.org, hch@lst.de, arnd@arndb.de, wens@csie.org, maxime@cerno.tech, gfavor@ventanamicro.com, andrea.mondelli@huawei.com, behrensj@mit.edu, xinhaoqu@huawei.com, mick@ics.forth.gr, allen.baum@esperantotech.com, jscheid@ventanamicro.com, rtrauben@gmail.com, samuel@sholland.org, cmuellner@linux.com, philipp.tomsich@vrull.eu, Heiko Stuebner <heiko@sntech.de> Subject: [PATCH v9 05/12] riscv: extend concatenated alternatives-lines to the same length Date: Wed, 13 Apr 2022 05:03:00 +0200 [thread overview] Message-ID: <20220413030307.133807-6-heiko@sntech.de> (raw) In-Reply-To: <20220413030307.133807-1-heiko@sntech.de> ALT_NEW_CONTENT already uses same-length assembler lines, so extend this to the other elements as well. This makes it more readable when these elements need to be extended in the future. Signed-off-by: Heiko Stuebner <heiko@sntech.de> --- arch/riscv/include/asm/alternative-macros.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/alternative-macros.h b/arch/riscv/include/asm/alternative-macros.h index 9e04cd53afc8..8c2bbc7bbe50 100644 --- a/arch/riscv/include/asm/alternative-macros.h +++ b/arch/riscv/include/asm/alternative-macros.h @@ -62,14 +62,14 @@ #include <asm/asm.h> #include <linux/stringify.h> -#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \ - RISCV_PTR " " oldptr "\n" \ - RISCV_PTR " " newptr "\n" \ - REG_ASM " " vendor_id "\n" \ - REG_ASM " " newlen "\n" \ +#define ALT_ENTRY(oldptr, newptr, vendor_id, errata_id, newlen) \ + RISCV_PTR " " oldptr "\n" \ + RISCV_PTR " " newptr "\n" \ + REG_ASM " " vendor_id "\n" \ + REG_ASM " " newlen "\n" \ ".word " errata_id "\n" -#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \ +#define ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) \ ".if " __stringify(enable) " == 1\n" \ ".pushsection .alternative, \"a\"\n" \ ALT_ENTRY("886b", "888f", __stringify(vendor_id), __stringify(errata_id), "889f - 888f") \ @@ -83,10 +83,10 @@ ".org . - (889b - 888b) + (887b - 886b)\n" \ ".endif\n" -#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \ - "886 :\n" \ - old_c "\n" \ - "887 :\n" \ +#define __ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, enable) \ + "886 :\n" \ + old_c "\n" \ + "887 :\n" \ ALT_NEW_CONTENT(vendor_id, errata_id, enable, new_c) #define _ALTERNATIVE_CFG(old_c, new_c, vendor_id, errata_id, CONFIG_k) \ -- 2.35.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-04-13 3:03 UTC|newest] Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-04-13 3:02 [PATCH v9 00/12] riscv: support for Svpbmt and D1 memory types Heiko Stuebner 2022-04-13 3:02 ` Heiko Stuebner 2022-04-13 3:02 ` [PATCH v9 01/12] riscv: integrate alternatives better into the main architecture Heiko Stuebner 2022-04-13 3:02 ` Heiko Stuebner 2022-04-13 9:05 ` Philipp Tomsich 2022-04-13 9:05 ` Philipp Tomsich 2022-04-13 3:02 ` [PATCH v9 02/12] riscv: allow different stages with alternatives Heiko Stuebner 2022-04-13 3:02 ` Heiko Stuebner 2022-04-13 9:05 ` Philipp Tomsich 2022-04-13 9:05 ` Philipp Tomsich 2022-04-13 3:02 ` [PATCH v9 03/12] riscv: implement module alternatives Heiko Stuebner 2022-04-13 3:02 ` Heiko Stuebner 2022-04-13 9:07 ` Philipp Tomsich 2022-04-13 9:07 ` Philipp Tomsich 2022-04-13 3:02 ` [PATCH v9 04/12] riscv: implement ALTERNATIVE_2 macro Heiko Stuebner 2022-04-13 3:02 ` Heiko Stuebner 2022-04-13 9:08 ` Philipp Tomsich 2022-04-13 9:08 ` Philipp Tomsich 2022-04-13 3:03 ` Heiko Stuebner [this message] 2022-04-13 3:03 ` [PATCH v9 05/12] riscv: extend concatenated alternatives-lines to the same length Heiko Stuebner 2022-04-13 9:08 ` Philipp Tomsich 2022-04-13 9:08 ` Philipp Tomsich 2022-04-13 3:03 ` [PATCH v9 06/12] riscv: prevent compressed instructions in alternatives Heiko Stuebner 2022-04-13 3:03 ` Heiko Stuebner 2022-04-13 9:09 ` Philipp Tomsich 2022-04-13 9:09 ` Philipp Tomsich 2022-04-16 5:51 ` kernel test robot 2022-04-13 3:03 ` [PATCH v9 07/12] riscv: move boot alternatives to after fill_hwcap Heiko Stuebner 2022-04-13 3:03 ` Heiko Stuebner 2022-04-13 5:46 ` Guo Ren 2022-04-13 5:46 ` Guo Ren 2022-04-13 9:15 ` Philipp Tomsich 2022-04-13 9:15 ` Philipp Tomsich 2022-04-13 3:03 ` [PATCH v9 08/12] riscv: Fix accessing pfn bits in PTEs for non-32bit variants Heiko Stuebner 2022-04-13 3:03 ` Heiko Stuebner 2022-04-13 9:09 ` Philipp Tomsich 2022-04-13 9:09 ` Philipp Tomsich 2022-04-13 3:03 ` [PATCH v9 09/12] riscv: add RISC-V Svpbmt extension support Heiko Stuebner 2022-04-13 3:03 ` Heiko Stuebner 2022-04-13 9:11 ` Philipp Tomsich 2022-04-13 9:11 ` Philipp Tomsich 2022-04-13 3:03 ` [PATCH v9 10/12] riscv: remove FIXMAP_PAGE_IO and fall back to its default value Heiko Stuebner 2022-04-13 3:03 ` Heiko Stuebner 2022-04-13 5:41 ` Guo Ren 2022-04-13 5:41 ` Guo Ren 2022-04-13 9:14 ` Philipp Tomsich 2022-04-13 9:14 ` Philipp Tomsich 2022-04-13 3:03 ` [PATCH v9 11/12] riscv: don't use global static vars to store alternative data Heiko Stuebner 2022-04-13 3:03 ` Heiko Stuebner 2022-04-13 5:43 ` Guo Ren 2022-04-13 5:43 ` Guo Ren 2022-04-13 9:16 ` Philipp Tomsich 2022-04-13 9:16 ` Philipp Tomsich 2022-04-13 3:03 ` [PATCH v9 12/12] riscv: add memory-type errata for T-Head Heiko Stuebner 2022-04-13 3:03 ` Heiko Stuebner 2022-04-13 5:41 ` Guo Ren 2022-04-13 5:41 ` Guo Ren 2022-04-13 9:17 ` Philipp Tomsich 2022-04-13 9:17 ` Philipp Tomsich
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