* [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs
@ 2022-04-21 0:33 Bin Meng
2022-04-21 0:33 ` [PATCH v5 1/6] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng
` (6 more replies)
0 siblings, 7 replies; 9+ messages in thread
From: Bin Meng @ 2022-04-21 0:33 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv
This adds initial support for the Sdtrig extension via the Trigger Module,
as defined in the RISC-V Debug Specification [1].
Only "Address / Data Match" trigger (type 2) is implemented as of now,
which is mainly used for hardware breakpoint and watchpoint. The number
of type 2 triggers implemented is 2, which is the number that we can
find in the SiFive U54/U74 cores.
[1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
Changes in v5:
- rebase against riscv-to-apply.next
- drop patch 1 in v4 which is already in riscv-to-apply.next
- adjust patch order to let patch 2 in v4 come later
Changes in v4:
- move riscv_trigger_init() call to riscv_cpu_reset()
Changes in v3:
- add riscv_trigger_init(), moved from patch #1 to this patch
- enable debug feature by default for all CPUs
Changes in v2:
- use 0 instead of GETPC()
- change the config option to 'disabled' by default
- new patch: add debug state description
Bin Meng (6):
target/riscv: debug: Implement debug related TCGCPUOps
target/riscv: cpu: Add a config option for native debug
target/riscv: csr: Hook debug CSR read/write
target/riscv: machine: Add debug state description
target/riscv: cpu: Enable native debug feature
hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
include/hw/core/tcg-cpu-ops.h | 1 +
target/riscv/cpu.h | 4 +-
target/riscv/debug.h | 6 ++
target/riscv/cpu.c | 12 ++++
target/riscv/csr.c | 57 +++++++++++++++++++
target/riscv/debug.c | 102 ++++++++++++++++++++++++++++++++++
target/riscv/machine.c | 32 +++++++++++
7 files changed, 213 insertions(+), 1 deletion(-)
--
2.25.1
^ permalink raw reply [flat|nested] 9+ messages in thread
* [PATCH v5 1/6] target/riscv: debug: Implement debug related TCGCPUOps
2022-04-21 0:33 [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Bin Meng
@ 2022-04-21 0:33 ` Bin Meng
2022-04-21 0:33 ` [PATCH v5 2/6] target/riscv: cpu: Add a config option for native debug Bin Meng
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Bin Meng @ 2022-04-21 0:33 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Implement .debug_excp_handler, .debug_check_{breakpoint, watchpoint}
TCGCPUOps and hook them into riscv_tcg_ops.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v2)
Changes in v2:
- use 0 instead of GETPC()
target/riscv/debug.h | 4 +++
target/riscv/cpu.c | 3 ++
target/riscv/debug.c | 75 ++++++++++++++++++++++++++++++++++++++++++++
3 files changed, 82 insertions(+)
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index fbc5f946e2..fb21706e1c 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -105,4 +105,8 @@ void tselect_csr_write(CPURISCVState *env, target_ulong val);
target_ulong tdata_csr_read(CPURISCVState *env, int tdata_index);
void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val);
+void riscv_cpu_debug_excp_handler(CPUState *cs);
+bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
+bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
+
#endif /* RISCV_DEBUG_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 94f9434411..8919928f4f 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -880,6 +880,9 @@ static const struct TCGCPUOps riscv_tcg_ops = {
.do_interrupt = riscv_cpu_do_interrupt,
.do_transaction_failed = riscv_cpu_do_transaction_failed,
.do_unaligned_access = riscv_cpu_do_unaligned_access,
+ .debug_excp_handler = riscv_cpu_debug_excp_handler,
+ .debug_check_breakpoint = riscv_cpu_debug_check_breakpoint,
+ .debug_check_watchpoint = riscv_cpu_debug_check_watchpoint,
#endif /* !CONFIG_USER_ONLY */
};
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index c8cec39217..1a9392645e 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -337,3 +337,78 @@ void tdata_csr_write(CPURISCVState *env, int tdata_index, target_ulong val)
return write_func(env, env->trigger_cur, tdata_index, val);
}
+
+void riscv_cpu_debug_excp_handler(CPUState *cs)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+
+ if (cs->watchpoint_hit) {
+ if (cs->watchpoint_hit->flags & BP_CPU) {
+ cs->watchpoint_hit = NULL;
+ riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
+ }
+ } else {
+ if (cpu_breakpoint_test(cs, env->pc, BP_CPU)) {
+ riscv_raise_exception(env, RISCV_EXCP_BREAKPOINT, 0);
+ }
+ }
+}
+
+bool riscv_cpu_debug_check_breakpoint(CPUState *cs)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ CPUBreakpoint *bp;
+ target_ulong ctrl;
+ target_ulong pc;
+ int i;
+
+ QTAILQ_FOREACH(bp, &cs->breakpoints, entry) {
+ for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
+ ctrl = env->type2_trig[i].mcontrol;
+ pc = env->type2_trig[i].maddress;
+
+ if ((ctrl & TYPE2_EXEC) && (bp->pc == pc)) {
+ /* check U/S/M bit against current privilege level */
+ if ((ctrl >> 3) & BIT(env->priv)) {
+ return true;
+ }
+ }
+ }
+ }
+
+ return false;
+}
+
+bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
+{
+ RISCVCPU *cpu = RISCV_CPU(cs);
+ CPURISCVState *env = &cpu->env;
+ target_ulong ctrl;
+ target_ulong addr;
+ int flags;
+ int i;
+
+ for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
+ ctrl = env->type2_trig[i].mcontrol;
+ addr = env->type2_trig[i].maddress;
+ flags = 0;
+
+ if (ctrl & TYPE2_LOAD) {
+ flags |= BP_MEM_READ;
+ }
+ if (ctrl & TYPE2_STORE) {
+ flags |= BP_MEM_WRITE;
+ }
+
+ if ((wp->flags & flags) && (wp->vaddr == addr)) {
+ /* check U/S/M bit against current privilege level */
+ if ((ctrl >> 3) & BIT(env->priv)) {
+ return true;
+ }
+ }
+ }
+
+ return false;
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 2/6] target/riscv: cpu: Add a config option for native debug
2022-04-21 0:33 [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Bin Meng
2022-04-21 0:33 ` [PATCH v5 1/6] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng
@ 2022-04-21 0:33 ` Bin Meng
2022-04-21 0:33 ` [PATCH v5 3/6] target/riscv: csr: Hook debug CSR read/write Bin Meng
` (4 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Bin Meng @ 2022-04-21 0:33 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Add a config option to enable support for native M-mode debug.
This is disabled by default and can be enabled with 'debug=true'.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v2)
Changes in v2:
- change the config option to 'disabled' by default
target/riscv/cpu.h | 4 +++-
target/riscv/cpu.c | 5 +++++
2 files changed, 8 insertions(+), 1 deletion(-)
diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
index 39a9ff17d3..62e53e3653 100644
--- a/target/riscv/cpu.h
+++ b/target/riscv/cpu.h
@@ -79,7 +79,8 @@ enum {
RISCV_FEATURE_PMP,
RISCV_FEATURE_EPMP,
RISCV_FEATURE_MISA,
- RISCV_FEATURE_AIA
+ RISCV_FEATURE_AIA,
+ RISCV_FEATURE_DEBUG
};
/* Privileged specification version */
@@ -405,6 +406,7 @@ struct RISCVCPUConfig {
bool pmp;
bool epmp;
bool aia;
+ bool debug;
uint64_t resetvec;
};
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 8919928f4f..477961b619 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -548,6 +548,10 @@ static void riscv_cpu_realize(DeviceState *dev, Error **errp)
riscv_set_feature(env, RISCV_FEATURE_AIA);
}
+ if (cpu->cfg.debug) {
+ riscv_set_feature(env, RISCV_FEATURE_DEBUG);
+ }
+
set_resetvec(env, cpu->cfg.resetvec);
/* Validate that MISA_MXL is set properly. */
@@ -795,6 +799,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
+ DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 3/6] target/riscv: csr: Hook debug CSR read/write
2022-04-21 0:33 [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Bin Meng
2022-04-21 0:33 ` [PATCH v5 1/6] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng
2022-04-21 0:33 ` [PATCH v5 2/6] target/riscv: cpu: Add a config option for native debug Bin Meng
@ 2022-04-21 0:33 ` Bin Meng
2022-04-21 0:33 ` [PATCH v5 4/6] target/riscv: machine: Add debug state description Bin Meng
` (3 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Bin Meng @ 2022-04-21 0:33 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
This adds debug CSR read/write support to the RISC-V CSR RW table.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v4)
Changes in v4:
- move riscv_trigger_init() call to riscv_cpu_reset()
Changes in v3:
- add riscv_trigger_init(), moved from patch #1 to this patch
target/riscv/debug.h | 2 ++
target/riscv/cpu.c | 4 ++++
target/riscv/csr.c | 57 ++++++++++++++++++++++++++++++++++++++++++++
target/riscv/debug.c | 27 +++++++++++++++++++++
4 files changed, 90 insertions(+)
diff --git a/target/riscv/debug.h b/target/riscv/debug.h
index fb21706e1c..27b9cac6b4 100644
--- a/target/riscv/debug.h
+++ b/target/riscv/debug.h
@@ -109,4 +109,6 @@ void riscv_cpu_debug_excp_handler(CPUState *cs);
bool riscv_cpu_debug_check_breakpoint(CPUState *cs);
bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp);
+void riscv_trigger_init(CPURISCVState *env);
+
#endif /* RISCV_DEBUG_H */
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 477961b619..85656cdcc3 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -466,6 +466,10 @@ static void riscv_cpu_reset(DeviceState *dev)
set_default_nan_mode(1, &env->fp_status);
#ifndef CONFIG_USER_ONLY
+ if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
+ riscv_trigger_init(env);
+ }
+
if (kvm_enabled()) {
kvm_riscv_reset_vcpu(cpu);
}
diff --git a/target/riscv/csr.c b/target/riscv/csr.c
index a09126a011..6ba85e7b5d 100644
--- a/target/riscv/csr.c
+++ b/target/riscv/csr.c
@@ -290,6 +290,15 @@ static RISCVException epmp(CPURISCVState *env, int csrno)
return RISCV_EXCP_ILLEGAL_INST;
}
+
+static RISCVException debug(CPURISCVState *env, int csrno)
+{
+ if (riscv_feature(env, RISCV_FEATURE_DEBUG)) {
+ return RISCV_EXCP_NONE;
+ }
+
+ return RISCV_EXCP_ILLEGAL_INST;
+}
#endif
/* User Floating-Point CSRs */
@@ -2677,6 +2686,48 @@ static RISCVException write_pmpaddr(CPURISCVState *env, int csrno,
return RISCV_EXCP_NONE;
}
+static RISCVException read_tselect(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ *val = tselect_csr_read(env);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_tselect(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ tselect_csr_write(env, val);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException read_tdata(CPURISCVState *env, int csrno,
+ target_ulong *val)
+{
+ /* return 0 in tdata1 to end the trigger enumeration */
+ if (env->trigger_cur >= TRIGGER_NUM && csrno == CSR_TDATA1) {
+ *val = 0;
+ return RISCV_EXCP_NONE;
+ }
+
+ if (!tdata_available(env, csrno - CSR_TDATA1)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ *val = tdata_csr_read(env, csrno - CSR_TDATA1);
+ return RISCV_EXCP_NONE;
+}
+
+static RISCVException write_tdata(CPURISCVState *env, int csrno,
+ target_ulong val)
+{
+ if (!tdata_available(env, csrno - CSR_TDATA1)) {
+ return RISCV_EXCP_ILLEGAL_INST;
+ }
+
+ tdata_csr_write(env, csrno - CSR_TDATA1, val);
+ return RISCV_EXCP_NONE;
+}
+
/*
* Functions to access Pointer Masking feature registers
* We have to check if current priv lvl could modify
@@ -3418,6 +3469,12 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = {
[CSR_PMPADDR14] = { "pmpaddr14", pmp, read_pmpaddr, write_pmpaddr },
[CSR_PMPADDR15] = { "pmpaddr15", pmp, read_pmpaddr, write_pmpaddr },
+ /* Debug CSRs */
+ [CSR_TSELECT] = { "tselect", debug, read_tselect, write_tselect },
+ [CSR_TDATA1] = { "tdata1", debug, read_tdata, write_tdata },
+ [CSR_TDATA2] = { "tdata2", debug, read_tdata, write_tdata },
+ [CSR_TDATA3] = { "tdata3", debug, read_tdata, write_tdata },
+
/* User Pointer Masking */
[CSR_UMTE] = { "umte", pointer_masking, read_umte, write_umte },
[CSR_UPMMASK] = { "upmmask", pointer_masking, read_upmmask, write_upmmask },
diff --git a/target/riscv/debug.c b/target/riscv/debug.c
index 1a9392645e..2f2a51c732 100644
--- a/target/riscv/debug.c
+++ b/target/riscv/debug.c
@@ -412,3 +412,30 @@ bool riscv_cpu_debug_check_watchpoint(CPUState *cs, CPUWatchpoint *wp)
return false;
}
+
+void riscv_trigger_init(CPURISCVState *env)
+{
+ target_ulong type2 = trigger_type(env, TRIGGER_TYPE_AD_MATCH);
+ int i;
+
+ /* type 2 triggers */
+ for (i = 0; i < TRIGGER_TYPE2_NUM; i++) {
+ /*
+ * type = TRIGGER_TYPE_AD_MATCH
+ * dmode = 0 (both debug and M-mode can write tdata)
+ * maskmax = 0 (unimplemented, always 0)
+ * sizehi = 0 (match against any size, RV64 only)
+ * hit = 0 (unimplemented, always 0)
+ * select = 0 (always 0, perform match on address)
+ * timing = 0 (always 0, trigger before instruction)
+ * sizelo = 0 (match against any size)
+ * action = 0 (always 0, raise a breakpoint exception)
+ * chain = 0 (unimplemented, always 0)
+ * match = 0 (always 0, when any compare value equals tdata2)
+ */
+ env->type2_trig[i].mcontrol = type2;
+ env->type2_trig[i].maddress = 0;
+ env->type2_trig[i].bp = NULL;
+ env->type2_trig[i].wp = NULL;
+ }
+}
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 4/6] target/riscv: machine: Add debug state description
2022-04-21 0:33 [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Bin Meng
` (2 preceding siblings ...)
2022-04-21 0:33 ` [PATCH v5 3/6] target/riscv: csr: Hook debug CSR read/write Bin Meng
@ 2022-04-21 0:33 ` Bin Meng
2022-04-21 0:33 ` [PATCH v5 5/6] target/riscv: cpu: Enable native debug feature Bin Meng
` (2 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Bin Meng @ 2022-04-21 0:33 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Add a subsection to machine.c to migrate debug CSR state.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v2)
Changes in v2:
- new patch: add debug state description
target/riscv/machine.c | 32 ++++++++++++++++++++++++++++++++
1 file changed, 32 insertions(+)
diff --git a/target/riscv/machine.c b/target/riscv/machine.c
index 243f567949..2a437b29a1 100644
--- a/target/riscv/machine.c
+++ b/target/riscv/machine.c
@@ -216,7 +216,38 @@ static const VMStateDescription vmstate_kvmtimer = {
VMSTATE_UINT64(env.kvm_timer_time, RISCVCPU),
VMSTATE_UINT64(env.kvm_timer_compare, RISCVCPU),
VMSTATE_UINT64(env.kvm_timer_state, RISCVCPU),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static bool debug_needed(void *opaque)
+{
+ RISCVCPU *cpu = opaque;
+ CPURISCVState *env = &cpu->env;
+
+ return riscv_feature(env, RISCV_FEATURE_DEBUG);
+}
+static const VMStateDescription vmstate_debug_type2 = {
+ .name = "cpu/debug/type2",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(mcontrol, type2_trigger_t),
+ VMSTATE_UINTTL(maddress, type2_trigger_t),
+ VMSTATE_END_OF_LIST()
+ }
+};
+
+static const VMStateDescription vmstate_debug = {
+ .name = "cpu/debug",
+ .version_id = 1,
+ .minimum_version_id = 1,
+ .needed = debug_needed,
+ .fields = (VMStateField[]) {
+ VMSTATE_UINTTL(env.trigger_cur, RISCVCPU),
+ VMSTATE_STRUCT_ARRAY(env.type2_trig, RISCVCPU, TRIGGER_TYPE2_NUM,
+ 0, vmstate_debug_type2, type2_trigger_t),
VMSTATE_END_OF_LIST()
}
};
@@ -315,6 +346,7 @@ const VMStateDescription vmstate_riscv_cpu = {
&vmstate_rv128,
&vmstate_kvmtimer,
&vmstate_envcfg,
+ &vmstate_debug,
NULL
}
};
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 5/6] target/riscv: cpu: Enable native debug feature
2022-04-21 0:33 [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Bin Meng
` (3 preceding siblings ...)
2022-04-21 0:33 ` [PATCH v5 4/6] target/riscv: machine: Add debug state description Bin Meng
@ 2022-04-21 0:33 ` Bin Meng
2022-04-21 0:33 ` [PATCH v5 6/6] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Bin Meng
2022-04-21 1:45 ` Alistair Francis
6 siblings, 0 replies; 9+ messages in thread
From: Bin Meng @ 2022-04-21 0:33 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng
From: Bin Meng <bin.meng@windriver.com>
Turn on native debug feature by default for all CPUs.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v3)
Changes in v3:
- enable debug feature by default for all CPUs
target/riscv/cpu.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/target/riscv/cpu.c b/target/riscv/cpu.c
index 85656cdcc3..0c774056c5 100644
--- a/target/riscv/cpu.c
+++ b/target/riscv/cpu.c
@@ -803,7 +803,7 @@ static Property riscv_cpu_properties[] = {
DEFINE_PROP_BOOL("Zve64f", RISCVCPU, cfg.ext_zve64f, false),
DEFINE_PROP_BOOL("mmu", RISCVCPU, cfg.mmu, true),
DEFINE_PROP_BOOL("pmp", RISCVCPU, cfg.pmp, true),
- DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, false),
+ DEFINE_PROP_BOOL("debug", RISCVCPU, cfg.debug, true),
DEFINE_PROP_STRING("priv_spec", RISCVCPU, cfg.priv_spec),
DEFINE_PROP_STRING("vext_spec", RISCVCPU, cfg.vext_spec),
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* [PATCH v5 6/6] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
2022-04-21 0:33 [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Bin Meng
` (4 preceding siblings ...)
2022-04-21 0:33 ` [PATCH v5 5/6] target/riscv: cpu: Enable native debug feature Bin Meng
@ 2022-04-21 0:33 ` Bin Meng
2022-04-21 1:45 ` Alistair Francis
6 siblings, 0 replies; 9+ messages in thread
From: Bin Meng @ 2022-04-21 0:33 UTC (permalink / raw)
To: Alistair Francis, qemu-devel, qemu-riscv; +Cc: Bin Meng, Richard Henderson
From: Bin Meng <bin.meng@windriver.com>
This is now used by RISC-V as well. Update the comments.
Signed-off-by: Bin Meng <bin.meng@windriver.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Alistair Francis <alistair.francis@wdc.com>
---
(no changes since v1)
include/hw/core/tcg-cpu-ops.h | 1 +
1 file changed, 1 insertion(+)
diff --git a/include/hw/core/tcg-cpu-ops.h b/include/hw/core/tcg-cpu-ops.h
index e13898553a..f98671ff32 100644
--- a/include/hw/core/tcg-cpu-ops.h
+++ b/include/hw/core/tcg-cpu-ops.h
@@ -90,6 +90,7 @@ struct TCGCPUOps {
/**
* @debug_check_watchpoint: return true if the architectural
* watchpoint whose address has matched should really fire, used by ARM
+ * and RISC-V
*/
bool (*debug_check_watchpoint)(CPUState *cpu, CPUWatchpoint *wp);
--
2.25.1
^ permalink raw reply related [flat|nested] 9+ messages in thread
* Re: [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs
2022-04-21 0:33 [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Bin Meng
@ 2022-04-21 1:45 ` Alistair Francis
2022-04-21 0:33 ` [PATCH v5 2/6] target/riscv: cpu: Add a config option for native debug Bin Meng
` (5 subsequent siblings)
6 siblings, 0 replies; 9+ messages in thread
From: Alistair Francis @ 2022-04-21 1:45 UTC (permalink / raw)
To: Bin Meng
Cc: open list:RISC-V, Alistair Francis, qemu-devel@nongnu.org Developers
On Thu, Apr 21, 2022 at 10:35 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
>
> This adds initial support for the Sdtrig extension via the Trigger Module,
> as defined in the RISC-V Debug Specification [1].
>
> Only "Address / Data Match" trigger (type 2) is implemented as of now,
> which is mainly used for hardware breakpoint and watchpoint. The number
> of type 2 triggers implemented is 2, which is the number that we can
> find in the SiFive U54/U74 cores.
>
> [1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
>
> Changes in v5:
> - rebase against riscv-to-apply.next
> - drop patch 1 in v4 which is already in riscv-to-apply.next
> - adjust patch order to let patch 2 in v4 come later
>
> Changes in v4:
> - move riscv_trigger_init() call to riscv_cpu_reset()
>
> Changes in v3:
> - add riscv_trigger_init(), moved from patch #1 to this patch
> - enable debug feature by default for all CPUs
>
> Changes in v2:
> - use 0 instead of GETPC()
> - change the config option to 'disabled' by default
> - new patch: add debug state description
>
> Bin Meng (6):
> target/riscv: debug: Implement debug related TCGCPUOps
> target/riscv: cpu: Add a config option for native debug
> target/riscv: csr: Hook debug CSR read/write
> target/riscv: machine: Add debug state description
> target/riscv: cpu: Enable native debug feature
> hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> include/hw/core/tcg-cpu-ops.h | 1 +
> target/riscv/cpu.h | 4 +-
> target/riscv/debug.h | 6 ++
> target/riscv/cpu.c | 12 ++++
> target/riscv/csr.c | 57 +++++++++++++++++++
> target/riscv/debug.c | 102 ++++++++++++++++++++++++++++++++++
> target/riscv/machine.c | 32 +++++++++++
> 7 files changed, 213 insertions(+), 1 deletion(-)
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
* Re: [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs
@ 2022-04-21 1:45 ` Alistair Francis
0 siblings, 0 replies; 9+ messages in thread
From: Alistair Francis @ 2022-04-21 1:45 UTC (permalink / raw)
To: Bin Meng
Cc: Alistair Francis, qemu-devel@nongnu.org Developers, open list:RISC-V
On Thu, Apr 21, 2022 at 10:35 AM Bin Meng <bmeng.cn@gmail.com> wrote:
>
>
> This adds initial support for the Sdtrig extension via the Trigger Module,
> as defined in the RISC-V Debug Specification [1].
>
> Only "Address / Data Match" trigger (type 2) is implemented as of now,
> which is mainly used for hardware breakpoint and watchpoint. The number
> of type 2 triggers implemented is 2, which is the number that we can
> find in the SiFive U54/U74 cores.
>
> [1] https://github.com/riscv/riscv-debug-spec/raw/master/riscv-debug-stable.pdf
>
> Changes in v5:
> - rebase against riscv-to-apply.next
> - drop patch 1 in v4 which is already in riscv-to-apply.next
> - adjust patch order to let patch 2 in v4 come later
>
> Changes in v4:
> - move riscv_trigger_init() call to riscv_cpu_reset()
>
> Changes in v3:
> - add riscv_trigger_init(), moved from patch #1 to this patch
> - enable debug feature by default for all CPUs
>
> Changes in v2:
> - use 0 instead of GETPC()
> - change the config option to 'disabled' by default
> - new patch: add debug state description
>
> Bin Meng (6):
> target/riscv: debug: Implement debug related TCGCPUOps
> target/riscv: cpu: Add a config option for native debug
> target/riscv: csr: Hook debug CSR read/write
> target/riscv: machine: Add debug state description
> target/riscv: cpu: Enable native debug feature
> hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint()
Thanks!
Applied to riscv-to-apply.next
Alistair
>
> include/hw/core/tcg-cpu-ops.h | 1 +
> target/riscv/cpu.h | 4 +-
> target/riscv/debug.h | 6 ++
> target/riscv/cpu.c | 12 ++++
> target/riscv/csr.c | 57 +++++++++++++++++++
> target/riscv/debug.c | 102 ++++++++++++++++++++++++++++++++++
> target/riscv/machine.c | 32 +++++++++++
> 7 files changed, 213 insertions(+), 1 deletion(-)
>
> --
> 2.25.1
>
>
^ permalink raw reply [flat|nested] 9+ messages in thread
end of thread, other threads:[~2022-04-21 1:47 UTC | newest]
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2022-04-21 0:33 [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Bin Meng
2022-04-21 0:33 ` [PATCH v5 1/6] target/riscv: debug: Implement debug related TCGCPUOps Bin Meng
2022-04-21 0:33 ` [PATCH v5 2/6] target/riscv: cpu: Add a config option for native debug Bin Meng
2022-04-21 0:33 ` [PATCH v5 3/6] target/riscv: csr: Hook debug CSR read/write Bin Meng
2022-04-21 0:33 ` [PATCH v5 4/6] target/riscv: machine: Add debug state description Bin Meng
2022-04-21 0:33 ` [PATCH v5 5/6] target/riscv: cpu: Enable native debug feature Bin Meng
2022-04-21 0:33 ` [PATCH v5 6/6] hw/core: tcg-cpu-ops.h: Update comments of debug_check_watchpoint() Bin Meng
2022-04-21 1:45 ` [PATCH v5 0/6] target/riscv: Initial support for the Sdtrig extension via M-mode CSRs Alistair Francis
2022-04-21 1:45 ` Alistair Francis
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