[PATCH V3 09/17] clk: mediatek: reset: Add support for input offset and bit from DT

[Rex-BC Chen <rex-bc.chen@mediatek.com>]

To use the clock reset function easier, we implement the of_xlate.
The calculation of return value is different from each reset version.

There is no impact for original use. If the argument number is not
larger than 1, it will return original id.

With this implementation if we want to set offset 0x120 and bit 16,
we can just write "resets = <&infra_rst 0x120 16>;" in the module node.

Signed-off-by: Rex-BC Chen <rex-bc.chen@mediatek.com>
---
 drivers/clk/mediatek/reset.c | 31 +++++++++++++++++++++++++++++++
 drivers/clk/mediatek/reset.h |  1 +
 2 files changed, 32 insertions(+)

diff --git a/drivers/clk/mediatek/reset.c b/drivers/clk/mediatek/reset.c
index fe917b2eeab4..2a2f3dede77f 100644
--- a/drivers/clk/mediatek/reset.c
+++ b/drivers/clk/mediatek/reset.c
@@ -97,6 +97,33 @@ static const struct reset_control_ops mtk_reset_ops_set_clr = {
 	.reset = mtk_reset_set_clr,
 };
 
+static int reset_xlate(struct reset_controller_dev *rcdev,
+		       const struct of_phandle_args *reset_spec)
+{
+	struct mtk_clk_rst_data *data = to_mtk_clk_rst_data(rcdev);
+	unsigned int offset, bit, shift;
+
+	if (reset_spec->args_count <= 1)
+		return reset_spec->args[0];
+
+	switch (data->desc->version) {
+	case MTK_RST_SIMPLE:
+		shift = 2;
+		break;
+	case MTK_RST_SET_CLR:
+		shift = 4;
+		break;
+	default:
+		pr_err("Unknown reset version %d\n", data->desc->version);
+		return -EINVAL;
+	}
+
+	offset = reset_spec->args[0];
+	bit = reset_spec->args[1];
+
+	return (offset >> shift) * 32 + bit;
+}
+
 int mtk_register_reset_controller(struct device_node *np,
 				  const struct mtk_clk_rst_desc *desc)
 {
@@ -138,6 +165,8 @@ int mtk_register_reset_controller(struct device_node *np,
 	data->rcdev.nr_resets = desc->rst_set_nr * 32;
 	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
+	data->rcdev.of_reset_n_cells = max(desc->reset_n_cells, 1);
+	data->rcdev.of_xlate = reset_xlate;
 
 	ret = reset_controller_register(&data->rcdev);
 	if (ret) {
@@ -192,6 +221,8 @@ int mtk_register_reset_controller_with_dev(struct device *dev,
 	data->rcdev.ops = rcops;
 	data->rcdev.of_node = np;
 	data->rcdev.dev = dev;
+	data->rcdev.of_reset_n_cells = max(desc->reset_n_cells, 1);
+	data->rcdev.of_xlate = reset_xlate;
 
 	ret = devm_reset_controller_register(dev, &data->rcdev);
 	if (ret) {
diff --git a/drivers/clk/mediatek/reset.h b/drivers/clk/mediatek/reset.h
index 79efbea37c9b..6838a644eaef 100644
--- a/drivers/clk/mediatek/reset.h
+++ b/drivers/clk/mediatek/reset.h
@@ -19,6 +19,7 @@ struct mtk_clk_rst_desc {
 	u8 version;
 	u32 rst_set_nr;
 	u16 reg_ofs;
+	int reset_n_cells;
 };
 
 struct mtk_clk_rst_data {
-- 
2.18.0