[PATCH v2 0/9] nvmem: sfp: binding updates and additions

[PATCH v2 0/9] nvmem: sfp: binding updates and additions

[Sean Anderson]

This adds several properties to the Layerscape Security Fuse Processor
(SFP) necessary for writing. Although the Linux driver does not use
these bindings, I plan to use them in U-Boot [1]. It also adds a new
compatibles for Trust Architecture (TA) 2.1 devices. In addition, it
also adds an SFP binding for all TA 2.1 and 3.0 devices.

[1] https://lore.kernel.org/u-boot/7c8e206a-cd40-2a77-6282-7f4bead2b13a@seco.com/T/#m591f8425b6f096ab3d54e6f7bd258e41cfa4c43b

Changes in v2:
- Mention "regulator" in the description for ta-prog-sfp-supply
- Convert sfp driver to use regmap
- Fix various typos in commit messages

Sean Anderson (9):
  dt-bindings: nvmem: sfp: Fix typo
  dt-bindings: nvmem: sfp: Add clock properties
  dt-bindings: nvmem: sfp: Add TA_PROG_SFP supply
  dt-bindings: nvmem: sfp: Add compatible binding for TA 2.1 SFPs
  arm64: dts: ls1028a: Update SFP binding to include clock
  ARM: dts: layerscape: Add SFP binding for TA 2.1 devices
  ARM: dts: Add SFP binding for TA 3.0 devices
  nvmem: sfp: Use regmap
  nvmem: sfp: Add support for TA 2.1 devices

 .../bindings/nvmem/fsl,layerscape-sfp.yaml    | 30 ++++++++++++++--
 arch/arm/boot/dts/ls1021a.dtsi                |  7 ++++
 .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi |  5 ++-
 .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi |  8 +++++
 drivers/nvmem/Kconfig                         |  1 +
 drivers/nvmem/layerscape-sfp.c                | 36 ++++++++++++++-----
 11 files changed, 115 insertions(+), 12 deletions(-)

-- 
2.35.1.1320.gc452695387.dirty

[PATCH v2 0/9] nvmem: sfp: binding updates and additions

[Sean Anderson]

This adds several properties to the Layerscape Security Fuse Processor
(SFP) necessary for writing. Although the Linux driver does not use
these bindings, I plan to use them in U-Boot [1]. It also adds a new
compatibles for Trust Architecture (TA) 2.1 devices. In addition, it
also adds an SFP binding for all TA 2.1 and 3.0 devices.

[1] https://lore.kernel.org/u-boot/7c8e206a-cd40-2a77-6282-7f4bead2b13a@seco.com/T/#m591f8425b6f096ab3d54e6f7bd258e41cfa4c43b

Changes in v2:
- Mention "regulator" in the description for ta-prog-sfp-supply
- Convert sfp driver to use regmap
- Fix various typos in commit messages

Sean Anderson (9):
  dt-bindings: nvmem: sfp: Fix typo
  dt-bindings: nvmem: sfp: Add clock properties
  dt-bindings: nvmem: sfp: Add TA_PROG_SFP supply
  dt-bindings: nvmem: sfp: Add compatible binding for TA 2.1 SFPs
  arm64: dts: ls1028a: Update SFP binding to include clock
  ARM: dts: layerscape: Add SFP binding for TA 2.1 devices
  ARM: dts: Add SFP binding for TA 3.0 devices
  nvmem: sfp: Use regmap
  nvmem: sfp: Add support for TA 2.1 devices

 .../bindings/nvmem/fsl,layerscape-sfp.yaml    | 30 ++++++++++++++--
 arch/arm/boot/dts/ls1021a.dtsi                |  7 ++++
 .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi |  5 ++-
 .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi |  8 +++++
 .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi |  8 +++++
 drivers/nvmem/Kconfig                         |  1 +
 drivers/nvmem/layerscape-sfp.c                | 36 ++++++++++++++-----
 11 files changed, 115 insertions(+), 12 deletions(-)

-- 
2.35.1.1320.gc452695387.dirty


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[PATCH v2 1/9] dt-bindings: nvmem: sfp: Fix typo

[Sean Anderson]

There is a small grammatical error in the description. Fix it.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
index 80914b93638e..b7798e903191 100644
--- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
+++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
@@ -10,7 +10,7 @@ maintainers:
   - Michael Walle <michael@walle.cc>
 
 description: |
-  SFP is the security fuse processor which among other things provide a
+  SFP is the security fuse processor which among other things provides a
   unique identifier per part.
 
 allOf:
-- 
2.35.1.1320.gc452695387.dirty

[PATCH v2 1/9] dt-bindings: nvmem: sfp: Fix typo

[Sean Anderson]

There is a small grammatical error in the description. Fix it.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
index 80914b93638e..b7798e903191 100644
--- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
+++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
@@ -10,7 +10,7 @@ maintainers:
   - Michael Walle <michael@walle.cc>
 
 description: |
-  SFP is the security fuse processor which among other things provide a
+  SFP is the security fuse processor which among other things provides a
   unique identifier per part.
 
 allOf:
-- 
2.35.1.1320.gc452695387.dirty


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[PATCH v2 2/9] dt-bindings: nvmem: sfp: Add clock properties

[Sean Anderson]

To program fuses, it is necessary to set the fuse programming time. This
is determined based on the value of the platform clock. Add a clock
property.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 .../bindings/nvmem/fsl,layerscape-sfp.yaml         | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
index b7798e903191..54086f50157d 100644
--- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
+++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
@@ -24,15 +24,29 @@ properties:
   reg:
     maxItems: 1
 
+  clocks:
+    maxItems: 1
+    description:
+      The SFP clock. Typically, this is the platform clock divided by 4.
+
+  clock-names:
+    const: sfp
+
 required:
   - compatible
   - reg
+  - clock-names
+  - clocks
 
 unevaluatedProperties: false
 
 examples:
   - |
+    #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
     efuse@1e80000 {
         compatible = "fsl,ls1028a-sfp";
         reg = <0x1e80000 0x8000>;
+        clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+                            QORIQ_CLK_PLL_DIV(4)>;
+        clock-names = "sfp";
     };
-- 
2.35.1.1320.gc452695387.dirty

[PATCH v2 2/9] dt-bindings: nvmem: sfp: Add clock properties

[Sean Anderson]

To program fuses, it is necessary to set the fuse programming time. This
is determined based on the value of the platform clock. Add a clock
property.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 .../bindings/nvmem/fsl,layerscape-sfp.yaml         | 14 ++++++++++++++
 1 file changed, 14 insertions(+)

diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
index b7798e903191..54086f50157d 100644
--- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
+++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
@@ -24,15 +24,29 @@ properties:
   reg:
     maxItems: 1
 
+  clocks:
+    maxItems: 1
+    description:
+      The SFP clock. Typically, this is the platform clock divided by 4.
+
+  clock-names:
+    const: sfp
+
 required:
   - compatible
   - reg
+  - clock-names
+  - clocks
 
 unevaluatedProperties: false
 
 examples:
   - |
+    #include <dt-bindings/clock/fsl,qoriq-clockgen.h>
     efuse@1e80000 {
         compatible = "fsl,ls1028a-sfp";
         reg = <0x1e80000 0x8000>;
+        clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+                            QORIQ_CLK_PLL_DIV(4)>;
+        clock-names = "sfp";
     };
-- 
2.35.1.1320.gc452695387.dirty


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[PATCH v2 3/9] dt-bindings: nvmem: sfp: Add TA_PROG_SFP supply

[Sean Anderson]

The TA_PROG_SFP supply must be enabled to program the fuses, and
disabled to read the fuses (such as at power-on-reset). On many boards,
this supply is controlled by a jumper. The user must manually insert or
remove it at the appropriate time in the programming process. However,
on other boards this supply is controlled by an FPGA or a GPIO. In
these cases, the driver can automatically enable and disable it as
necessary.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

Changes in v2:
- Mention "regulator" in the description for ta-prog-sfp-supply

 .../devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml        | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
index 54086f50157d..c5d7375b840a 100644
--- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
+++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
@@ -32,6 +32,11 @@ properties:
   clock-names:
     const: sfp
 
+  ta-prog-sfp-supply:
+    description:
+      The regulator for the TA_PROG_SFP pin. It will be enabled for programming
+      and disabled for reading.
+
 required:
   - compatible
   - reg
-- 
2.35.1.1320.gc452695387.dirty

[PATCH v2 3/9] dt-bindings: nvmem: sfp: Add TA_PROG_SFP supply

[Sean Anderson]

The TA_PROG_SFP supply must be enabled to program the fuses, and
disabled to read the fuses (such as at power-on-reset). On many boards,
this supply is controlled by a jumper. The user must manually insert or
remove it at the appropriate time in the programming process. However,
on other boards this supply is controlled by an FPGA or a GPIO. In
these cases, the driver can automatically enable and disable it as
necessary.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

Changes in v2:
- Mention "regulator" in the description for ta-prog-sfp-supply

 .../devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml        | 5 +++++
 1 file changed, 5 insertions(+)

diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
index 54086f50157d..c5d7375b840a 100644
--- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
+++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
@@ -32,6 +32,11 @@ properties:
   clock-names:
     const: sfp
 
+  ta-prog-sfp-supply:
+    description:
+      The regulator for the TA_PROG_SFP pin. It will be enabled for programming
+      and disabled for reading.
+
 required:
   - compatible
   - reg
-- 
2.35.1.1320.gc452695387.dirty


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[PATCH v2 4/9] dt-bindings: nvmem: sfp: Add compatible binding for TA 2.1 SFPs

[Sean Anderson]

Trust Architecture (TA) 2.1 devices include the LS1012A, LS1021A,
LS1043A, and LS1046A. The SFP device on TA 2.1 devices is very similar
to the SFP on TA 3.0 devices. The primary difference is a few fields in
the control register. Add a compatible string.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 .../devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml    | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
index c5d7375b840a..3b4e6e94cb81 100644
--- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
+++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
@@ -18,8 +18,13 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - fsl,ls1028a-sfp
+    oneOf:
+      - description: Trust architecture 2.1 SFP
+        items:
+          - const: fsl,ls1021a-sfp
+      - description: Trust architecture 3.0 SFP
+        items:
+          - const: fsl,ls1028a-sfp
 
   reg:
     maxItems: 1
-- 
2.35.1.1320.gc452695387.dirty

[PATCH v2 4/9] dt-bindings: nvmem: sfp: Add compatible binding for TA 2.1 SFPs

[Sean Anderson]

Trust Architecture (TA) 2.1 devices include the LS1012A, LS1021A,
LS1043A, and LS1046A. The SFP device on TA 2.1 devices is very similar
to the SFP on TA 3.0 devices. The primary difference is a few fields in
the control register. Add a compatible string.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 .../devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml    | 9 +++++++--
 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
index c5d7375b840a..3b4e6e94cb81 100644
--- a/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
+++ b/Documentation/devicetree/bindings/nvmem/fsl,layerscape-sfp.yaml
@@ -18,8 +18,13 @@ allOf:
 
 properties:
   compatible:
-    enum:
-      - fsl,ls1028a-sfp
+    oneOf:
+      - description: Trust architecture 2.1 SFP
+        items:
+          - const: fsl,ls1021a-sfp
+      - description: Trust architecture 3.0 SFP
+        items:
+          - const: fsl,ls1028a-sfp
 
   reg:
     maxItems: 1
-- 
2.35.1.1320.gc452695387.dirty


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[PATCH v2 5/9] arm64: dts: ls1028a: Update SFP binding to include clock

[Sean Anderson]

The clocks property is now mandatory. Add it.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 088271d49139..59b289b52a28 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -224,9 +224,12 @@ rst: syscon@1e60000 {
 			little-endian;
 		};
 
-		efuse@1e80000 {
+		sfp: efuse@1e80000 {
 			compatible = "fsl,ls1028a-sfp";
 			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-- 
2.35.1.1320.gc452695387.dirty

[PATCH v2 5/9] arm64: dts: ls1028a: Update SFP binding to include clock

[Sean Anderson]

The clocks property is now mandatory. Add it.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi | 5 ++++-
 1 file changed, 4 insertions(+), 1 deletion(-)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
index 088271d49139..59b289b52a28 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1028a.dtsi
@@ -224,9 +224,12 @@ rst: syscon@1e60000 {
 			little-endian;
 		};
 
-		efuse@1e80000 {
+		sfp: efuse@1e80000 {
 			compatible = "fsl,ls1028a-sfp";
 			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
 			#address-cells = <1>;
 			#size-cells = <1>;
 
-- 
2.35.1.1320.gc452695387.dirty


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[PATCH v2 6/9] ARM: dts: layerscape: Add SFP binding for TA 2.1 devices

[Sean Anderson]

This adds an appropriate SFP binding for Trust Architecture 2.1 devices.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 arch/arm/boot/dts/ls1021a.dtsi                 | 7 +++++++
 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 8 ++++++++
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++++++
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 8 ++++++++
 4 files changed, 31 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 2e69d6eab4d1..c1e94a317cba 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -129,6 +129,13 @@ ifc: ifc@1530000 {
 			status = "disabled";
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen 4 3>;
+			clock-names = "sfp";
+		};
+
 		dcfg: dcfg@1ee0000 {
 			compatible = "fsl,ls1021a-dcfg", "syscon";
 			reg = <0x0 0x1ee0000 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 50a72cda4727..47ce525e0a72 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -271,6 +271,14 @@ rtic_d: rtic-d@60 {
 			};
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		sec_mon: sec_mon@1e90000 {
 			compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
 				     "fsl,sec-v4.0-mon";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 35d1939e690b..b0ab0b19de7e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -383,6 +383,14 @@ sec_jr3: jr@40000 {
 			};
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		dcfg: dcfg@1ee0000 {
 			compatible = "fsl,ls1043a-dcfg", "syscon";
 			reg = <0x0 0x1ee0000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 4e7bd04d9798..c30056afc02a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -413,6 +413,14 @@ bportals: bman-portals@508000000 {
 			ranges = <0x0 0x5 0x08000000 0x8000000>;
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		dcfg: dcfg@1ee0000 {
 			compatible = "fsl,ls1046a-dcfg", "syscon";
 			reg = <0x0 0x1ee0000 0x0 0x1000>;
-- 
2.35.1.1320.gc452695387.dirty

[PATCH v2 6/9] ARM: dts: layerscape: Add SFP binding for TA 2.1 devices

[Sean Anderson]

This adds an appropriate SFP binding for Trust Architecture 2.1 devices.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 arch/arm/boot/dts/ls1021a.dtsi                 | 7 +++++++
 arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi | 8 ++++++++
 arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi | 8 ++++++++
 arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi | 8 ++++++++
 4 files changed, 31 insertions(+)

diff --git a/arch/arm/boot/dts/ls1021a.dtsi b/arch/arm/boot/dts/ls1021a.dtsi
index 2e69d6eab4d1..c1e94a317cba 100644
--- a/arch/arm/boot/dts/ls1021a.dtsi
+++ b/arch/arm/boot/dts/ls1021a.dtsi
@@ -129,6 +129,13 @@ ifc: ifc@1530000 {
 			status = "disabled";
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen 4 3>;
+			clock-names = "sfp";
+		};
+
 		dcfg: dcfg@1ee0000 {
 			compatible = "fsl,ls1021a-dcfg", "syscon";
 			reg = <0x0 0x1ee0000 0x0 0x1000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
index 50a72cda4727..47ce525e0a72 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1012a.dtsi
@@ -271,6 +271,14 @@ rtic_d: rtic-d@60 {
 			};
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		sec_mon: sec_mon@1e90000 {
 			compatible = "fsl,sec-v5.4-mon", "fsl,sec-v5.0-mon",
 				     "fsl,sec-v4.0-mon";
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
index 35d1939e690b..b0ab0b19de7e 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1043a.dtsi
@@ -383,6 +383,14 @@ sec_jr3: jr@40000 {
 			};
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		dcfg: dcfg@1ee0000 {
 			compatible = "fsl,ls1043a-dcfg", "syscon";
 			reg = <0x0 0x1ee0000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
index 4e7bd04d9798..c30056afc02a 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1046a.dtsi
@@ -413,6 +413,14 @@ bportals: bman-portals@508000000 {
 			ranges = <0x0 0x5 0x08000000 0x8000000>;
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		dcfg: dcfg@1ee0000 {
 			compatible = "fsl,ls1046a-dcfg", "syscon";
 			reg = <0x0 0x1ee0000 0x0 0x1000>;
-- 
2.35.1.1320.gc452695387.dirty


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 7/9] ARM: dts: Add SFP binding for TA 3.0 devices

[Sean Anderson]

This adds an SFP binding for Trust Architecture 3.0 devices.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 8 ++++++++
 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 8 ++++++++
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++
 3 files changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 18e529118476..1a58e8671047 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -269,6 +269,14 @@ extirq: interrupt-controller@14 {
 			};
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1028a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		tmu: tmu@1f80000 {
 			compatible = "fsl,qoriq-tmu";
 			reg = <0x0 0x1f80000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 1282b61da8a5..5705ec554bf9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -278,6 +278,14 @@ dcfg: dcfg@1e00000 {
 			little-endian;
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1028a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		isc: syscon@1f70000 {
 			compatible = "fsl,ls2080a-isc", "syscon";
 			reg = <0x0 0x1f70000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index c5daa15b020d..53dd8c7dc048 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -671,6 +671,14 @@ dcfg: syscon@1e00000 {
 			little-endian;
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1028a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		isc: syscon@1f70000 {
 			compatible = "fsl,lx2160a-isc", "syscon";
 			reg = <0x0 0x1f70000 0x0 0x10000>;
-- 
2.35.1.1320.gc452695387.dirty

[PATCH v2 7/9] ARM: dts: Add SFP binding for TA 3.0 devices

[Sean Anderson]

This adds an SFP binding for Trust Architecture 3.0 devices.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi | 8 ++++++++
 arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi | 8 ++++++++
 arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi | 8 ++++++++
 3 files changed, 24 insertions(+)

diff --git a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
index 18e529118476..1a58e8671047 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls1088a.dtsi
@@ -269,6 +269,14 @@ extirq: interrupt-controller@14 {
 			};
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1028a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		tmu: tmu@1f80000 {
 			compatible = "fsl,qoriq-tmu";
 			reg = <0x0 0x1f80000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
index 1282b61da8a5..5705ec554bf9 100644
--- a/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-ls208xa.dtsi
@@ -278,6 +278,14 @@ dcfg: dcfg@1e00000 {
 			little-endian;
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1028a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		isc: syscon@1f70000 {
 			compatible = "fsl,ls2080a-isc", "syscon";
 			reg = <0x0 0x1f70000 0x0 0x10000>;
diff --git a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
index c5daa15b020d..53dd8c7dc048 100644
--- a/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
+++ b/arch/arm64/boot/dts/freescale/fsl-lx2160a.dtsi
@@ -671,6 +671,14 @@ dcfg: syscon@1e00000 {
 			little-endian;
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1028a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen QORIQ_CLK_PLATFORM_PLL
+					    QORIQ_CLK_PLL_DIV(4)>;
+			clock-names = "sfp";
+		};
+
 		isc: syscon@1f70000 {
 			compatible = "fsl,lx2160a-isc", "syscon";
 			reg = <0x0 0x1f70000 0x0 0x10000>;
-- 
2.35.1.1320.gc452695387.dirty


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 8/9] nvmem: sfp: Use regmap

[Sean Anderson]

This converts the SFP driver to use regmap. This will allow easily
supporting devices with different endians. We disallow byte-level
access, as regmap_bulk_read doesn't support it (and it's unclear what
the correct result would be when we have an endianness difference).

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

Changes in v2:
- New

 drivers/nvmem/Kconfig          |  1 +
 drivers/nvmem/layerscape-sfp.c | 30 ++++++++++++++++++++++--------
 2 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 555aa77a574d..403ed5257592 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -304,6 +304,7 @@ config NVMEM_LAYERSCAPE_SFP
 	tristate "Layerscape SFP (Security Fuse Processor) support"
 	depends on ARCH_LAYERSCAPE || COMPILE_TEST
 	depends on HAS_IOMEM
+	select REGMAP_MMIO
 	help
 	  This driver provides support to read the eFuses on Freescale
 	  Layerscape SoC's. For example, the vendor provides a per part
diff --git a/drivers/nvmem/layerscape-sfp.c b/drivers/nvmem/layerscape-sfp.c
index e591c1511e33..59083f048921 100644
--- a/drivers/nvmem/layerscape-sfp.c
+++ b/drivers/nvmem/layerscape-sfp.c
@@ -13,15 +13,17 @@
 #include <linux/nvmem-provider.h>
 #include <linux/platform_device.h>
 #include <linux/property.h>
+#include <linux/regmap.h>
 
 #define LAYERSCAPE_SFP_OTP_OFFSET	0x0200
 
 struct layerscape_sfp_priv {
-	void __iomem *base;
+	struct regmap *regmap;
 };
 
 struct layerscape_sfp_data {
 	int size;
+	enum regmap_endian endian;
 };
 
 static int layerscape_sfp_read(void *context, unsigned int offset, void *val,
@@ -29,15 +31,16 @@ static int layerscape_sfp_read(void *context, unsigned int offset, void *val,
 {
 	struct layerscape_sfp_priv *priv = context;
 
-	memcpy_fromio(val, priv->base + LAYERSCAPE_SFP_OTP_OFFSET + offset,
-		      bytes);
-
-	return 0;
+	return regmap_bulk_read(priv->regmap,
+				LAYERSCAPE_SFP_OTP_OFFSET + offset, val,
+				bytes / 4);
 }
 
 static struct nvmem_config layerscape_sfp_nvmem_config = {
 	.name = "fsl-sfp",
 	.reg_read = layerscape_sfp_read,
+	.word_size = 4,
+	.stride = 4,
 };
 
 static int layerscape_sfp_probe(struct platform_device *pdev)
@@ -45,16 +48,26 @@ static int layerscape_sfp_probe(struct platform_device *pdev)
 	const struct layerscape_sfp_data *data;
 	struct layerscape_sfp_priv *priv;
 	struct nvmem_device *nvmem;
+	struct regmap_config config = { 0 };
+	void __iomem *base;
 
 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
 
-	priv->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(priv->base))
-		return PTR_ERR(priv->base);
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
 
 	data = device_get_match_data(&pdev->dev);
+	config.reg_bits = 32;
+	config.reg_stride = 4;
+	config.val_bits = 32;
+	config.val_format_endian = data->endian;
+	config.max_register = LAYERSCAPE_SFP_OTP_OFFSET + data->size - 4;
+	priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, &config);
+	if (IS_ERR(priv->regmap))
+		return PTR_ERR(priv->regmap);
 
 	layerscape_sfp_nvmem_config.size = data->size;
 	layerscape_sfp_nvmem_config.dev = &pdev->dev;
@@ -67,6 +80,7 @@ static int layerscape_sfp_probe(struct platform_device *pdev)
 
 static const struct layerscape_sfp_data ls1028a_data = {
 	.size = 0x88,
+	.endian = REGMAP_ENDIAN_LITTLE,
 };
 
 static const struct of_device_id layerscape_sfp_dt_ids[] = {
-- 
2.35.1.1320.gc452695387.dirty

[PATCH v2 8/9] nvmem: sfp: Use regmap

[Sean Anderson]

This converts the SFP driver to use regmap. This will allow easily
supporting devices with different endians. We disallow byte-level
access, as regmap_bulk_read doesn't support it (and it's unclear what
the correct result would be when we have an endianness difference).

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

Changes in v2:
- New

 drivers/nvmem/Kconfig          |  1 +
 drivers/nvmem/layerscape-sfp.c | 30 ++++++++++++++++++++++--------
 2 files changed, 23 insertions(+), 8 deletions(-)

diff --git a/drivers/nvmem/Kconfig b/drivers/nvmem/Kconfig
index 555aa77a574d..403ed5257592 100644
--- a/drivers/nvmem/Kconfig
+++ b/drivers/nvmem/Kconfig
@@ -304,6 +304,7 @@ config NVMEM_LAYERSCAPE_SFP
 	tristate "Layerscape SFP (Security Fuse Processor) support"
 	depends on ARCH_LAYERSCAPE || COMPILE_TEST
 	depends on HAS_IOMEM
+	select REGMAP_MMIO
 	help
 	  This driver provides support to read the eFuses on Freescale
 	  Layerscape SoC's. For example, the vendor provides a per part
diff --git a/drivers/nvmem/layerscape-sfp.c b/drivers/nvmem/layerscape-sfp.c
index e591c1511e33..59083f048921 100644
--- a/drivers/nvmem/layerscape-sfp.c
+++ b/drivers/nvmem/layerscape-sfp.c
@@ -13,15 +13,17 @@
 #include <linux/nvmem-provider.h>
 #include <linux/platform_device.h>
 #include <linux/property.h>
+#include <linux/regmap.h>
 
 #define LAYERSCAPE_SFP_OTP_OFFSET	0x0200
 
 struct layerscape_sfp_priv {
-	void __iomem *base;
+	struct regmap *regmap;
 };
 
 struct layerscape_sfp_data {
 	int size;
+	enum regmap_endian endian;
 };
 
 static int layerscape_sfp_read(void *context, unsigned int offset, void *val,
@@ -29,15 +31,16 @@ static int layerscape_sfp_read(void *context, unsigned int offset, void *val,
 {
 	struct layerscape_sfp_priv *priv = context;
 
-	memcpy_fromio(val, priv->base + LAYERSCAPE_SFP_OTP_OFFSET + offset,
-		      bytes);
-
-	return 0;
+	return regmap_bulk_read(priv->regmap,
+				LAYERSCAPE_SFP_OTP_OFFSET + offset, val,
+				bytes / 4);
 }
 
 static struct nvmem_config layerscape_sfp_nvmem_config = {
 	.name = "fsl-sfp",
 	.reg_read = layerscape_sfp_read,
+	.word_size = 4,
+	.stride = 4,
 };
 
 static int layerscape_sfp_probe(struct platform_device *pdev)
@@ -45,16 +48,26 @@ static int layerscape_sfp_probe(struct platform_device *pdev)
 	const struct layerscape_sfp_data *data;
 	struct layerscape_sfp_priv *priv;
 	struct nvmem_device *nvmem;
+	struct regmap_config config = { 0 };
+	void __iomem *base;
 
 	priv = devm_kzalloc(&pdev->dev, sizeof(*priv), GFP_KERNEL);
 	if (!priv)
 		return -ENOMEM;
 
-	priv->base = devm_platform_ioremap_resource(pdev, 0);
-	if (IS_ERR(priv->base))
-		return PTR_ERR(priv->base);
+	base = devm_platform_ioremap_resource(pdev, 0);
+	if (IS_ERR(base))
+		return PTR_ERR(base);
 
 	data = device_get_match_data(&pdev->dev);
+	config.reg_bits = 32;
+	config.reg_stride = 4;
+	config.val_bits = 32;
+	config.val_format_endian = data->endian;
+	config.max_register = LAYERSCAPE_SFP_OTP_OFFSET + data->size - 4;
+	priv->regmap = devm_regmap_init_mmio(&pdev->dev, base, &config);
+	if (IS_ERR(priv->regmap))
+		return PTR_ERR(priv->regmap);
 
 	layerscape_sfp_nvmem_config.size = data->size;
 	layerscape_sfp_nvmem_config.dev = &pdev->dev;
@@ -67,6 +80,7 @@ static int layerscape_sfp_probe(struct platform_device *pdev)
 
 static const struct layerscape_sfp_data ls1028a_data = {
 	.size = 0x88,
+	.endian = REGMAP_ENDIAN_LITTLE,
 };
 
 static const struct of_device_id layerscape_sfp_dt_ids[] = {
-- 
2.35.1.1320.gc452695387.dirty


_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel

[PATCH v2 9/9] nvmem: sfp: Add support for TA 2.1 devices

[Sean Anderson]

This adds support for Trust Architecture (TA) 2.1 devices to the SFP driver.
There are few differences between TA 2.1 and TA 3.0, especially for
read-only support, so just re-use the existing data.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 drivers/nvmem/layerscape-sfp.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/nvmem/layerscape-sfp.c b/drivers/nvmem/layerscape-sfp.c
index 59083f048921..e2b424561949 100644
--- a/drivers/nvmem/layerscape-sfp.c
+++ b/drivers/nvmem/layerscape-sfp.c
@@ -78,12 +78,18 @@ static int layerscape_sfp_probe(struct platform_device *pdev)
 	return PTR_ERR_OR_ZERO(nvmem);
 }
 
+static const struct layerscape_sfp_data ls1021a_data = {
+	.size = 0x88,
+	.endian = REGMAP_ENDIAN_BIG,
+};
+
 static const struct layerscape_sfp_data ls1028a_data = {
 	.size = 0x88,
 	.endian = REGMAP_ENDIAN_LITTLE,
 };
 
 static const struct of_device_id layerscape_sfp_dt_ids[] = {
+	{ .compatible = "fsl,ls1021a-sfp", .data = &ls1021a_data },
 	{ .compatible = "fsl,ls1028a-sfp", .data = &ls1028a_data },
 	{},
 };
-- 
2.35.1.1320.gc452695387.dirty

[PATCH v2 9/9] nvmem: sfp: Add support for TA 2.1 devices

[Sean Anderson]

This adds support for Trust Architecture (TA) 2.1 devices to the SFP driver.
There are few differences between TA 2.1 and TA 3.0, especially for
read-only support, so just re-use the existing data.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 drivers/nvmem/layerscape-sfp.c | 6 ++++++
 1 file changed, 6 insertions(+)

diff --git a/drivers/nvmem/layerscape-sfp.c b/drivers/nvmem/layerscape-sfp.c
index 59083f048921..e2b424561949 100644
--- a/drivers/nvmem/layerscape-sfp.c
+++ b/drivers/nvmem/layerscape-sfp.c
@@ -78,12 +78,18 @@ static int layerscape_sfp_probe(struct platform_device *pdev)
 	return PTR_ERR_OR_ZERO(nvmem);
 }
 
+static const struct layerscape_sfp_data ls1021a_data = {
+	.size = 0x88,
+	.endian = REGMAP_ENDIAN_BIG,
+};
+
 static const struct layerscape_sfp_data ls1028a_data = {
 	.size = 0x88,
 	.endian = REGMAP_ENDIAN_LITTLE,
 };
 
 static const struct of_device_id layerscape_sfp_dt_ids[] = {
+	{ .compatible = "fsl,ls1021a-sfp", .data = &ls1021a_data },
 	{ .compatible = "fsl,ls1028a-sfp", .data = &ls1028a_data },
 	{},
 };
-- 
2.35.1.1320.gc452695387.dirty


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Re: [PATCH v2 0/9] nvmem: sfp: binding updates and additions

[Sean Anderson]

On 4/22/22 10:51 AM, Sean Anderson wrote:
> This adds several properties to the Layerscape Security Fuse Processor
> (SFP) necessary for writing. Although the Linux driver does not use
> these bindings, I plan to use them in U-Boot [1]. It also adds a new
> compatibles for Trust Architecture (TA) 2.1 devices. In addition, it
> also adds an SFP binding for all TA 2.1 and 3.0 devices.
> 
> [1] https://lore.kernel.org/u-boot/7c8e206a-cd40-2a77-6282-7f4bead2b13a@seco.com/T/#m591f8425b6f096ab3d54e6f7bd258e41cfa4c43b
> 
> Changes in v2:
> - Mention "regulator" in the description for ta-prog-sfp-supply
> - Convert sfp driver to use regmap
> - Fix various typos in commit messages
> 
> Sean Anderson (9):
>   dt-bindings: nvmem: sfp: Fix typo
>   dt-bindings: nvmem: sfp: Add clock properties
>   dt-bindings: nvmem: sfp: Add TA_PROG_SFP supply
>   dt-bindings: nvmem: sfp: Add compatible binding for TA 2.1 SFPs
>   arm64: dts: ls1028a: Update SFP binding to include clock
>   ARM: dts: layerscape: Add SFP binding for TA 2.1 devices
>   ARM: dts: Add SFP binding for TA 3.0 devices
>   nvmem: sfp: Use regmap
>   nvmem: sfp: Add support for TA 2.1 devices
> 
>  .../bindings/nvmem/fsl,layerscape-sfp.yaml    | 30 ++++++++++++++--
>  arch/arm/boot/dts/ls1021a.dtsi                |  7 ++++
>  .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi |  8 +++++
>  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi |  5 ++-
>  .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi |  8 +++++
>  .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi |  8 +++++
>  .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi |  8 +++++
>  .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi |  8 +++++
>  .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi |  8 +++++
>  drivers/nvmem/Kconfig                         |  1 +
>  drivers/nvmem/layerscape-sfp.c                | 36 ++++++++++++++-----
>  11 files changed, 115 insertions(+), 12 deletions(-)
> 

I forgot to pick up Reviewed-bys from v1. I can resend this or add them for v3.

--Sean

Re: [PATCH v2 0/9] nvmem: sfp: binding updates and additions

[Sean Anderson]

On 4/22/22 10:51 AM, Sean Anderson wrote:
> This adds several properties to the Layerscape Security Fuse Processor
> (SFP) necessary for writing. Although the Linux driver does not use
> these bindings, I plan to use them in U-Boot [1]. It also adds a new
> compatibles for Trust Architecture (TA) 2.1 devices. In addition, it
> also adds an SFP binding for all TA 2.1 and 3.0 devices.
> 
> [1] https://lore.kernel.org/u-boot/7c8e206a-cd40-2a77-6282-7f4bead2b13a@seco.com/T/#m591f8425b6f096ab3d54e6f7bd258e41cfa4c43b
> 
> Changes in v2:
> - Mention "regulator" in the description for ta-prog-sfp-supply
> - Convert sfp driver to use regmap
> - Fix various typos in commit messages
> 
> Sean Anderson (9):
>   dt-bindings: nvmem: sfp: Fix typo
>   dt-bindings: nvmem: sfp: Add clock properties
>   dt-bindings: nvmem: sfp: Add TA_PROG_SFP supply
>   dt-bindings: nvmem: sfp: Add compatible binding for TA 2.1 SFPs
>   arm64: dts: ls1028a: Update SFP binding to include clock
>   ARM: dts: layerscape: Add SFP binding for TA 2.1 devices
>   ARM: dts: Add SFP binding for TA 3.0 devices
>   nvmem: sfp: Use regmap
>   nvmem: sfp: Add support for TA 2.1 devices
> 
>  .../bindings/nvmem/fsl,layerscape-sfp.yaml    | 30 ++++++++++++++--
>  arch/arm/boot/dts/ls1021a.dtsi                |  7 ++++
>  .../arm64/boot/dts/freescale/fsl-ls1012a.dtsi |  8 +++++
>  .../arm64/boot/dts/freescale/fsl-ls1028a.dtsi |  5 ++-
>  .../arm64/boot/dts/freescale/fsl-ls1043a.dtsi |  8 +++++
>  .../arm64/boot/dts/freescale/fsl-ls1046a.dtsi |  8 +++++
>  .../arm64/boot/dts/freescale/fsl-ls1088a.dtsi |  8 +++++
>  .../arm64/boot/dts/freescale/fsl-ls208xa.dtsi |  8 +++++
>  .../arm64/boot/dts/freescale/fsl-lx2160a.dtsi |  8 +++++
>  drivers/nvmem/Kconfig                         |  1 +
>  drivers/nvmem/layerscape-sfp.c                | 36 ++++++++++++++-----
>  11 files changed, 115 insertions(+), 12 deletions(-)
> 

I forgot to pick up Reviewed-bys from v1. I can resend this or add them for v3.

--Sean

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Re: [PATCH v2 0/9] nvmem: sfp: binding updates and additions

[Andrew Lunn]

> I forgot to pick up Reviewed-bys from v1. I can resend this or add
> them for v3.

I suggest you wait a few days and see if you get any more comments,
which require a v3.

      Andrew

Re: [PATCH v2 0/9] nvmem: sfp: binding updates and additions

[Andrew Lunn]

> I forgot to pick up Reviewed-bys from v1. I can resend this or add
> them for v3.

I suggest you wait a few days and see if you get any more comments,
which require a v3.

      Andrew

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Re: [PATCH v2 3/9] dt-bindings: nvmem: sfp: Add TA_PROG_SFP supply

[Andrew Lunn]

On Fri, Apr 22, 2022 at 10:51:41AM -0400, Sean Anderson wrote:
> The TA_PROG_SFP supply must be enabled to program the fuses, and
> disabled to read the fuses (such as at power-on-reset). On many boards,
> this supply is controlled by a jumper. The user must manually insert or
> remove it at the appropriate time in the programming process. However,
> on other boards this supply is controlled by an FPGA or a GPIO. In
> these cases, the driver can automatically enable and disable it as
> necessary.
> 
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

Re: [PATCH v2 3/9] dt-bindings: nvmem: sfp: Add TA_PROG_SFP supply

[Andrew Lunn]

On Fri, Apr 22, 2022 at 10:51:41AM -0400, Sean Anderson wrote:
> The TA_PROG_SFP supply must be enabled to program the fuses, and
> disabled to read the fuses (such as at power-on-reset). On many boards,
> this supply is controlled by a jumper. The user must manually insert or
> remove it at the appropriate time in the programming process. However,
> on other boards this supply is controlled by an FPGA or a GPIO. In
> these cases, the driver can automatically enable and disable it as
> necessary.
> 
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>

Reviewed-by: Andrew Lunn <andrew@lunn.ch>

    Andrew

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Re: [PATCH v2 2/9] dt-bindings: nvmem: sfp: Add clock properties

[Rob Herring]

On Fri, 22 Apr 2022 10:51:40 -0400, Sean Anderson wrote:
> To program fuses, it is necessary to set the fuse programming time. This
> is determined based on the value of the platform clock. Add a clock
> property.
> 
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> ---
> 
> (no changes since v1)
> 
>  .../bindings/nvmem/fsl,layerscape-sfp.yaml         | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/


efuse@1e80000: 'clock-names' is a required property
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dtb

efuse@1e80000: 'clocks' is a required property
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dtb


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Re: [PATCH v2 2/9] dt-bindings: nvmem: sfp: Add clock properties

[Rob Herring]

On Fri, 22 Apr 2022 10:51:40 -0400, Sean Anderson wrote:
> To program fuses, it is necessary to set the fuse programming time. This
> is determined based on the value of the platform clock. Add a clock
> property.
> 
> Signed-off-by: Sean Anderson <sean.anderson@seco.com>
> ---
> 
> (no changes since v1)
> 
>  .../bindings/nvmem/fsl,layerscape-sfp.yaml         | 14 ++++++++++++++
>  1 file changed, 14 insertions(+)
> 

Running 'make dtbs_check' with the schema in this patch gives the
following warnings. Consider if they are expected or the schema is
incorrect. These may not be new warnings.

Note that it is not yet a requirement to have 0 warnings for dtbs_check.
This will change in the future.

Full log is available here: https://patchwork.ozlabs.org/patch/


efuse@1e80000: 'clock-names' is a required property
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dtb

efuse@1e80000: 'clocks' is a required property
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-kbox-a-230-ls.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var1.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var2.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var3-ads2.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-kontron-sl28-var4.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-qds.dtb
	arch/arm64/boot/dts/freescale/fsl-ls1028a-rdb.dtb