[PATCH v2 0/3] arm: layerscape: Add sfp driver

[PATCH v2 0/3] arm: layerscape: Add sfp driver

[Sean Anderson]

This adds a driver for the Security Fuse Processor (SFP). It only
supports Trust Architecture (TA) 2.1 SFPs, but it should be fairly
trivial to add support for TA 3.1 SFPs. See [1] for Linux
bindings/driver support.

[1] https://lore.kernel.org/linux-arm-kernel/20220422145147.2210587-1-sean.anderson@seco.com/

Changes in v2:
- Use the sfp clock directly, instead of assuming we get the platform
  clock. This corresponds better to what other drivers on these devices
  do.
- Rename clock to "sfp" to be more descriptive.
- update the clockgen node for ls1021a

Sean Anderson (3):
  arm: layerscape: Add sfp driver
  ARM: dts: ls1021a: update the clockgen node
  arch: layerscape: Add SFP binding

 MAINTAINERS                   |   5 +
 arch/arm/dts/fsl-ls1012a.dtsi |   7 +
 arch/arm/dts/fsl-ls1043a.dtsi |   7 +
 arch/arm/dts/fsl-ls1046a.dtsi |   7 +
 arch/arm/dts/ls1021a.dtsi     |  87 ++++-----
 drivers/misc/Kconfig          |  14 ++
 drivers/misc/Makefile         |   1 +
 drivers/misc/ls2_sfp.c        | 350 ++++++++++++++++++++++++++++++++++
 8 files changed, 426 insertions(+), 52 deletions(-)
 create mode 100644 drivers/misc/ls2_sfp.c

-- 
2.35.1.1320.gc452695387.dirty

[PATCH v2 1/3] arm: layerscape: Add sfp driver

[Sean Anderson]

This adds a driver for the Security Fuse Processor (SFP) present on
LS1012A, LS1021A, LS1043A, and LS1046A processors. It holds the
Super-Root Key (SRK), One-Time-Programmable Master Key (OTPMK), and
other "security" related fuses. Similar devices (sharing the same name)
are present on other processors, but for the moment this just supports
the LS2 variants.

The mirror registers are loaded during power-on reset. All mirror
registers must be programmed or read at once. Because of this, `fuse
prog` will program all fuses, even though only one might be specified.
To prevent accidentally burning through all your fuse programming cycles
with something like `fuse prog 0 0 A B C D`, we limit ourselves to one
programming cycle per reset. Fuses are numbered based on their address.
The fuse at 0x1e80200 is 0, the fuse at 0x1e80204 is 1, etc.

The TA_PROG_SFP supply must be enabled when programming fuses, but must
be disabled when reading them. Typically this supply is enabled by
inserting a jumper or by setting a register in the board's FPGA. I've
also added support for using a regulator. This could be helpful for
automatically issuing the FPGA write, or for toggling a GPIO controlling
the supply.

I suggest using the following procedure for programming:

1. Override the fuses you wish to program
   => fuse override 0 2 A B C D
2. Inspect the values and ensure that they are what you expect
   => fuse sense 0 2 4
3. Enable TA_PROG_SFP
4. Issue a program command using OSPR0 as a dummy. Since it contains the
   write-protect bit you will usually want to write it last anyway.
   => fuse prog 0 0 0
5. Disable TA_PROG_SFP
6. Read back the fuses and ensure they are correct
   => fuse read 0 2 4

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

Changes in v2:
- Use the sfp clock directly, instead of assuming we get the platform
  clock. This corresponds better to what other drivers on these devices
  do.
- Rename clock to "sfp" to be more descriptive.

 MAINTAINERS            |   5 +
 drivers/misc/Kconfig   |  14 ++
 drivers/misc/Makefile  |   1 +
 drivers/misc/ls2_sfp.c | 350 +++++++++++++++++++++++++++++++++++++++++
 4 files changed, 370 insertions(+)
 create mode 100644 drivers/misc/ls2_sfp.c

diff --git a/MAINTAINERS b/MAINTAINERS
index 7a9e3156f4..6a302b35e2 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -271,6 +271,11 @@ F:	drivers/spi/spi-qup.c
 F:	drivers/net/mdio-ipq4019.c
 F:	drivers/rng/msm_rng.c
 
+ARM LAYERSCAPE SFP
+M:	Sean Anderson <sean.anderson@seco.com>
+S:	Maintained
+F:	drivers/misc/ls2_sfp.c
+
 ARM MARVELL KIRKWOOD ARMADA-XP ARMADA-38X ARMADA-37XX ARMADA-7K/8K
 M:	Stefan Roese <sr@denx.de>
 S:	Maintained
diff --git a/drivers/misc/Kconfig b/drivers/misc/Kconfig
index 7029bb7b5c..2a86c42017 100644
--- a/drivers/misc/Kconfig
+++ b/drivers/misc/Kconfig
@@ -224,6 +224,20 @@ config JZ4780_EFUSE
 	help
 	  This selects support for the eFUSE on Ingenic JZ4780 SoCs.
 
+config LS2_SFP
+	bool "Layerscape Security Fuse Processor"
+	depends on FSL_LSCH2 || ARCH_LS1021A
+	depends on MISC
+	imply DM_REGULATOR
+	help
+	  This adds support for the Security Fuse Processor found on Layerscape
+	  SoCs. It contains various fuses related to secure boot, including the
+	  Super Root Key hash, One-Time-Programmable Master Key, Debug
+	  Challenge/Response values, and others. Fuses are numbered according
+	  to their four-byte offset from the start of the bank.
+
+	  If you don't need to read/program fuses, say 'n'.
+
 config MXC_OCOTP
 	bool "Enable MXC OCOTP Driver"
 	depends on ARCH_IMX8M || ARCH_MX6 || ARCH_MX7 || ARCH_MX7ULP || ARCH_VF610
diff --git a/drivers/misc/Makefile b/drivers/misc/Makefile
index b7a8ef68ab..4926671833 100644
--- a/drivers/misc/Makefile
+++ b/drivers/misc/Makefile
@@ -50,6 +50,7 @@ obj-$(CONFIG_IMX8ULP) += imx8ulp/
 obj-$(CONFIG_LED_STATUS) += status_led.o
 obj-$(CONFIG_LED_STATUS_GPIO) += gpio_led.o
 obj-$(CONFIG_MPC83XX_SERDES) += mpc83xx_serdes.o
+obj-$(CONFIG_$(SPL_TPL_)LS2_SFP) += ls2_sfp.o
 obj-$(CONFIG_$(SPL_)MXC_OCOTP) += mxc_ocotp.o
 obj-$(CONFIG_MXS_OCOTP) += mxs_ocotp.o
 obj-$(CONFIG_NUVOTON_NCT6102D) += nuvoton_nct6102d.o
diff --git a/drivers/misc/ls2_sfp.c b/drivers/misc/ls2_sfp.c
new file mode 100644
index 0000000000..dd104962c2
--- /dev/null
+++ b/drivers/misc/ls2_sfp.c
@@ -0,0 +1,350 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright (C) 2022 Sean Anderson <sean.anderson@seco.com>
+ *
+ * This driver supports the Security Fuse Processor device found on some
+ * Layerscape processors. At the moment, we only support a few processors.
+ * This driver was written with reference to the Layerscape SDK User
+ * Guide [1] and the ATF SFP driver [2].
+ *
+ * [1] https://docs.nxp.com/bundle/GUID-487B2E69-BB19-42CB-AC38-7EF18C0FE3AE/page/GUID-27FC40AD-3321-4A82-B29E-7BB49EE94F23.html
+ * [2] https://source.codeaurora.org/external/qoriq/qoriq-components/atf/tree/drivers/nxp/sfp?h=github.com/master
+ */
+
+#define LOG_CATEGORY UCLASS_MISC
+#include <common.h>
+#include <clk.h>
+#include <fuse.h>
+#include <misc.h>
+#include <asm/io.h>
+#include <dm/device_compat.h>
+#include <dm/read.h>
+#include <linux/bitfield.h>
+#include <power/regulator.h>
+
+DECLARE_GLOBAL_DATA_PTR;
+
+#define SFP_INGR	0x20
+#define SFP_SVHESR	0x24
+#define SFP_SFPCR	0x28
+
+#define SFP_START	0x200
+#define SFP_END		0x284
+#define SFP_SIZE	(SFP_END - SFP_START + 4)
+
+#define SFP_INGR_ERR	BIT(8)
+#define SFP_INGR_INST	GENMASK(7, 0)
+
+#define SFP_INGR_READFB	0x01
+#define SFP_INGR_PROGFB	0x02
+
+#define SFP_SFPCR_PPW	GENMASK(15, 0)
+
+enum ls2_sfp_ioctl {
+	LS2_SFP_IOCTL_READ,
+	LS2_SFP_IOCTL_PROG,
+};
+
+/**
+ * struct ls2_sfp_priv - private data for LS2 SFP
+ * @base: Base address of SFP
+ * @supply: The (optional) supply for TA_PROG_SFP
+ * @programmed: Whether we've already programmed the fuses since the last
+ *              reset. The SFP has a *very* limited amount of programming
+ *              cycles (two to six, depending on the model), so we try and
+ *              prevent accidentally performing additional programming
+ *              cycles.
+ * @dirty: Whether the mirror registers have been written to (overridden)
+ *         since we've last read the fuses (either as part of the reset
+ *         process or using a READFB instruction). There is a much larger,
+ *         but still finite, limit on the number of SFP read cycles (around
+ *         300,000), so we try and minimize reads as well.
+ */
+struct ls2_sfp_priv {
+	void __iomem *base;
+	struct udevice *supply;
+	bool programmed, dirty;
+};
+
+static u32 ls2_sfp_readl(struct ls2_sfp_priv *priv, ulong off)
+{
+	u32 val = be32_to_cpu(readl(priv->base + off));
+
+	log_debug("%08x = readl(%p)\n", val, priv->base + off);
+	return val;
+}
+
+static void ls2_sfp_writel(struct ls2_sfp_priv *priv, ulong val, ulong off)
+{
+	log_debug("writel(%08lx, %p)\n", val, priv->base + off);
+	writel(cpu_to_be32(val), priv->base + off);
+}
+
+static bool ls2_sfp_validate(struct udevice *dev, int offset, int size)
+{
+	if (offset < 0 || size < 0) {
+		dev_notice(dev, "size and offset must be positive\n");
+		return false;
+	}
+
+	if (offset & 3 || size & 3) {
+		dev_notice(dev, "size and offset must be multiples of 4\n");
+		return false;
+	}
+
+	if (offset + size > SFP_SIZE) {
+		dev_notice(dev, "size + offset must be <= %#x\n", SFP_SIZE);
+		return false;
+	}
+
+	return true;
+}
+
+static int ls2_sfp_read(struct udevice *dev, int offset, void *buf_bytes,
+			int size)
+{
+	int i;
+	struct ls2_sfp_priv *priv = dev_get_priv(dev);
+	u32 *buf = buf_bytes;
+
+	if (!ls2_sfp_validate(dev, offset, size))
+		return -EINVAL;
+
+	for (i = 0; i < size; i += 4)
+		buf[i >> 2] = ls2_sfp_readl(priv, SFP_START + offset + i);
+
+	return size;
+}
+
+static int ls2_sfp_write(struct udevice *dev, int offset,
+			 const void *buf_bytes, int size)
+{
+	int i;
+	struct ls2_sfp_priv *priv = dev_get_priv(dev);
+	const u32 *buf = buf_bytes;
+
+	if (!ls2_sfp_validate(dev, offset, size))
+		return -EINVAL;
+
+	for (i = 0; i < size; i += 4)
+		ls2_sfp_writel(priv, buf[i >> 2], SFP_START + offset + i);
+
+	priv->dirty = true;
+	return size;
+}
+
+static int ls2_sfp_check_secret(struct udevice *dev)
+{
+	struct ls2_sfp_priv *priv = dev_get_priv(dev);
+	u32 svhesr = ls2_sfp_readl(priv, SFP_SVHESR);
+
+	if (svhesr) {
+		dev_warn(dev, "secret value hamming error not zero: %08x\n",
+			 svhesr);
+		return -EIO;
+	}
+	return 0;
+}
+
+static int ls2_sfp_transaction(struct ls2_sfp_priv *priv, ulong inst)
+{
+	u32 ingr;
+
+	ls2_sfp_writel(priv, inst, SFP_INGR);
+
+	do {
+		ingr = ls2_sfp_readl(priv, SFP_INGR);
+	} while (FIELD_GET(SFP_INGR_INST, ingr));
+
+	return FIELD_GET(SFP_INGR_ERR, ingr) ? -EIO : 0;
+}
+
+static int ls2_sfp_ioctl(struct udevice *dev, unsigned long request, void *buf)
+{
+	int ret;
+	struct ls2_sfp_priv *priv = dev_get_priv(dev);
+
+	switch (request) {
+	case LS2_SFP_IOCTL_READ:
+		if (!priv->dirty) {
+			dev_dbg(dev, "ignoring read request, since fuses are not dirty\n");
+			return 0;
+		}
+
+		ret = ls2_sfp_transaction(priv, SFP_INGR_READFB);
+		if (ret) {
+			dev_err(dev, "error reading fuses\n");
+			return ret;
+		}
+
+		ls2_sfp_check_secret(dev);
+		priv->dirty = false;
+		return 0;
+	case LS2_SFP_IOCTL_PROG:
+		if (priv->programmed) {
+			dev_warn(dev, "fuses already programmed\n");
+			return -EPERM;
+		}
+
+		ret = ls2_sfp_check_secret(dev);
+		if (ret)
+			return ret;
+
+		if (priv->supply) {
+			ret = regulator_set_enable(priv->supply, true);
+			if (ret)
+				return ret;
+		}
+
+		ret = ls2_sfp_transaction(priv, SFP_INGR_PROGFB);
+		priv->programmed = true;
+		if (priv->supply)
+			regulator_set_enable(priv->supply, false);
+
+		if (ret)
+			dev_err(dev, "error programming fuses\n");
+		return ret;
+	default:
+		dev_dbg(dev, "unknown ioctl %lu\n", request);
+		return -EINVAL;
+	}
+}
+
+static const struct misc_ops ls2_sfp_ops = {
+	.read = ls2_sfp_read,
+	.write = ls2_sfp_write,
+	.ioctl = ls2_sfp_ioctl,
+};
+
+static int ls2_sfp_probe(struct udevice *dev)
+{
+	int ret;
+	struct clk clk;
+	struct ls2_sfp_priv *priv = dev_get_priv(dev);
+	ulong rate;
+
+	priv->base = dev_read_addr_ptr(dev);
+	if (!priv->base) {
+		dev_dbg(dev, "could not read register base\n");
+		return -EINVAL;
+	}
+
+	ret = device_get_supply_regulator(dev, "ta-sfp-prog", &priv->supply);
+	if (ret && ret != -ENODEV && ret != -ENOSYS) {
+		dev_dbg(dev, "problem getting supply (err %d)\n", ret);
+		return ret;
+	}
+
+	ret = clk_get_by_name(dev, "sfp", &clk);
+	if (ret == -ENOSYS) {
+		rate = gd->bus_clk / 4;
+	} else if (ret) {
+		dev_dbg(dev, "could not get clock (err %d)\n", ret);
+		return ret;
+	} else {
+		ret = clk_enable(&clk);
+		if (ret) {
+			dev_dbg(dev, "could not enable clock (err %d)\n", ret);
+			return ret;
+		}
+
+		rate = clk_get_rate(&clk);
+		clk_free(&clk);
+		if (!rate || IS_ERR_VALUE(rate)) {
+			ret = rate ? rate : -ENOENT;
+			dev_dbg(dev, "could not get clock rate (err %d)\n",
+				ret);
+			return ret;
+		}
+	}
+
+	/* sfp clock in MHz * 12 */
+	ls2_sfp_writel(priv, FIELD_PREP(SFP_SFPCR_PPW, rate * 12 / 1000000),
+		       SFP_SFPCR);
+
+	ls2_sfp_check_secret(dev);
+	return 0;
+}
+
+static const struct udevice_id ls2_sfp_ids[] = {
+	{ .compatible = "fsl,ls1021a-sfp" },
+	{ }
+};
+
+U_BOOT_DRIVER(ls2_sfp) = {
+	.name		= "ls2_sfp",
+	.id		= UCLASS_MISC,
+	.of_match	= ls2_sfp_ids,
+	.probe		= ls2_sfp_probe,
+	.ops		= &ls2_sfp_ops,
+	.priv_auto	= sizeof(struct ls2_sfp_priv),
+};
+
+static int ls2_sfp_device(struct udevice **dev)
+{
+	int ret = uclass_get_device_by_driver(UCLASS_MISC,
+					      DM_DRIVER_GET(ls2_sfp), dev);
+
+	if (ret)
+		log_debug("device not found (err %d)\n", ret);
+	return ret;
+}
+
+int fuse_read(u32 bank, u32 word, u32 *val)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = ls2_sfp_device(&dev);
+	if (ret)
+		return ret;
+
+	ret = misc_ioctl(dev, LS2_SFP_IOCTL_READ, NULL);
+	if (ret)
+		return ret;
+
+	ret = misc_read(dev, word << 2, val, sizeof(*val));
+	return ret < 0 ? ret : 0;
+}
+
+int fuse_sense(u32 bank, u32 word, u32 *val)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = ls2_sfp_device(&dev);
+	if (ret)
+		return ret;
+
+	ret = misc_read(dev, word << 2, val, sizeof(*val));
+	return ret < 0 ? ret : 0;
+}
+
+int fuse_prog(u32 bank, u32 word, u32 val)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = ls2_sfp_device(&dev);
+	if (ret)
+		return ret;
+
+	ret = misc_write(dev, word << 2, &val, sizeof(val));
+	if (ret < 0)
+		return ret;
+
+	return misc_ioctl(dev, LS2_SFP_IOCTL_PROG, NULL);
+}
+
+int fuse_override(u32 bank, u32 word, u32 val)
+{
+	int ret;
+	struct udevice *dev;
+
+	ret = ls2_sfp_device(&dev);
+	if (ret)
+		return ret;
+
+	ret = misc_write(dev, word << 2, &val, sizeof(val));
+	return ret < 0 ? ret : 0;
+}
-- 
2.35.1.1320.gc452695387.dirty

[PATCH v2 2/3] ARM: dts: ls1021a: update the clockgen node

[Sean Anderson]

QorIQ platforms now use different clock bindings. Although we don't use
the device tree for clocks on this platform, it is helpful to sync it
because then the bindings will more closely match Linux. Additionally,
it allows for using more clock fractions (such as platform/4).

This corresponds to Linux commit b6f5e7019391 ("ARM: dts: ls1021a:
update the clockgen node").

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

Changes in v2:
- New

 arch/arm/dts/ls1021a.dtsi | 80 ++++++++++++++-------------------------
 1 file changed, 28 insertions(+), 52 deletions(-)

diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 86192cbb7f..99f7d81e20 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -30,17 +30,24 @@
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <0xf00>;
-			clocks = <&cluster1_clk>;
+			clocks = <&clockgen 1 0>;
 		};
 
 		cpu@f01 {
 			compatible = "arm,cortex-a7";
 			device_type = "cpu";
 			reg = <0xf01>;
-			clocks = <&cluster1_clk>;
+			clocks = <&clockgen 1 0>;
 		};
 	};
 
+	sysclk: sysclk {
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <100000000>;
+		clock-output-names = "sysclk";
+	};
+
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(2) | IRQ_TYPE_LEVEL_LOW)>,
@@ -145,41 +152,10 @@
 		};
 
 		clockgen: clocking@1ee1000 {
-			#address-cells = <1>;
-			#size-cells = <1>;
-			ranges = <0x0 0x1ee1000 0x10000>;
-
-			sysclk: sysclk {
-				compatible = "fixed-clock";
-				#clock-cells = <0>;
-				clock-output-names = "sysclk";
-			};
-
-			cga_pll1: pll@800 {
-				compatible = "fsl,qoriq-core-pll-2.0";
-				#clock-cells = <1>;
-				reg = <0x800 0x10>;
-				clocks = <&sysclk>;
-				clock-output-names = "cga-pll1", "cga-pll1-div2",
-						     "cga-pll1-div4";
-			};
-
-			platform_clk: pll@c00 {
-				compatible = "fsl,qoriq-core-pll-2.0";
-				#clock-cells = <1>;
-				reg = <0xc00 0x10>;
-				clocks = <&sysclk>;
-				clock-output-names = "platform-clk", "platform-clk-div2";
-			};
-
-			cluster1_clk: clk0c0@0 {
-				compatible = "fsl,qoriq-core-mux-2.0";
-				#clock-cells = <0>;
-				reg = <0x0 0x10>;
-				clock-names = "pll1cga", "pll1cga-div2", "pll1cga-div4";
-				clocks = <&cga_pll1 0>, <&cga_pll1 1>, <&cga_pll1 2>;
-				clock-output-names = "cluster1-clk";
-			};
+			compatible = "fsl,ls1021a-clockgen";
+			reg = <0x0 0x1ee1000 0x0 0x1000>;
+			#clock-cells = <2>;
+			clocks = <&sysclk>;
 		};
 
 		dspi0: dspi@2100000 {
@@ -189,7 +165,7 @@
 			reg = <0x2100000 0x10000>;
 			interrupts = <GIC_SPI 96 IRQ_TYPE_LEVEL_HIGH>;
 			clock-names = "dspi";
-			clocks = <&platform_clk 1>;
+			clocks = <&clockgen 4 1>;
 			spi-num-chipselects = <6>;
 			big-endian;
 			status = "disabled";
@@ -202,7 +178,7 @@
 			reg = <0x2110000 0x10000>;
 			interrupts = <GIC_SPI 97 IRQ_TYPE_LEVEL_HIGH>;
 			clock-names = "dspi";
-			clocks = <&platform_clk 1>;
+			clocks = <&clockgen 4 1>;
 			spi-num-chipselects = <6>;
 			big-endian;
 			status = "disabled";
@@ -225,7 +201,7 @@
 			reg = <0x2180000 0x10000>;
 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;
 			clock-names = "i2c";
-			clocks = <&platform_clk 1>;
+			clocks = <&clockgen 4 1>;
 			status = "disabled";
 		};
 
@@ -236,7 +212,7 @@
 			reg = <0x2190000 0x10000>;
 			interrupts = <GIC_SPI 89 IRQ_TYPE_LEVEL_HIGH>;
 			clock-names = "i2c";
-			clocks = <&platform_clk 1>;
+			clocks = <&clockgen 4 1>;
 			status = "disabled";
 		};
 
@@ -247,7 +223,7 @@
 			reg = <0x21a0000 0x10000>;
 			interrupts = <GIC_SPI 90 IRQ_TYPE_LEVEL_HIGH>;
 			clock-names = "i2c";
-			clocks = <&platform_clk 1>;
+			clocks = <&clockgen 4 1>;
 			status = "disabled";
 		};
 
@@ -296,7 +272,7 @@
 			compatible = "fsl,ls1021a-lpuart";
 			reg = <0x2960000 0x1000>;
 			interrupts = <GIC_SPI 81 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&platform_clk 1>;
+			clocks = <&clockgen 4 1>;
 			clock-names = "ipg";
 			status = "disabled";
 		};
@@ -305,7 +281,7 @@
 			compatible = "fsl,ls1021a-lpuart";
 			reg = <0x2970000 0x1000>;
 			interrupts = <GIC_SPI 82 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&platform_clk 1>;
+			clocks = <&clockgen 4 1>;
 			clock-names = "ipg";
 			status = "disabled";
 		};
@@ -314,7 +290,7 @@
 			compatible = "fsl,ls1021a-lpuart";
 			reg = <0x2980000 0x1000>;
 			interrupts = <GIC_SPI 83 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&platform_clk 1>;
+			clocks = <&clockgen 4 1>;
 			clock-names = "ipg";
 			status = "disabled";
 		};
@@ -323,7 +299,7 @@
 			compatible = "fsl,ls1021a-lpuart";
 			reg = <0x2990000 0x1000>;
 			interrupts = <GIC_SPI 84 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&platform_clk 1>;
+			clocks = <&clockgen 4 1>;
 			clock-names = "ipg";
 			status = "disabled";
 		};
@@ -332,7 +308,7 @@
 			compatible = "fsl,ls1021a-lpuart";
 			reg = <0x29a0000 0x1000>;
 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&platform_clk 1>;
+			clocks = <&clockgen 4 1>;
 			clock-names = "ipg";
 			status = "disabled";
 		};
@@ -341,7 +317,7 @@
 			compatible = "fsl,imx21-wdt";
 			reg = <0x2ad0000 0x10000>;
 			interrupts = <GIC_SPI 115 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&platform_clk 1>;
+			clocks = <&clockgen 4 1>;
 			clock-names = "wdog-en";
 			big-endian;
 		};
@@ -350,7 +326,7 @@
 			compatible = "fsl,vf610-sai";
 			reg = <0x2b50000 0x10000>;
 			interrupts = <GIC_SPI 132 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&platform_clk 1>;
+			clocks = <&clockgen 4 1>;
 			clock-names = "sai";
 			dma-names = "tx", "rx";
 			dmas = <&edma0 1 47>,
@@ -363,7 +339,7 @@
 			compatible = "fsl,vf610-sai";
 			reg = <0x2b60000 0x10000>;
 			interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>;
-			clocks = <&platform_clk 1>;
+			clocks = <&clockgen 4 1>;
 			clock-names = "sai";
 			dma-names = "tx", "rx";
 			dmas = <&edma0 1 45>,
@@ -384,8 +360,8 @@
 			dma-channels = <32>;
 			big-endian;
 			clock-names = "dmamux0", "dmamux1";
-			clocks = <&platform_clk 1>,
-				 <&platform_clk 1>;
+			clocks = <&clockgen 4 1>,
+				 <&clockgen 4 1>;
 		};
 
 		enet0: ethernet@2d10000 {
-- 
2.35.1.1320.gc452695387.dirty

[PATCH v2 3/3] arch: layerscape: Add SFP binding

[Sean Anderson]

This adds an SFP binding for the processors it is present on. I have
only tested this for the LS1046A.

Signed-off-by: Sean Anderson <sean.anderson@seco.com>
---

(no changes since v1)

 arch/arm/dts/fsl-ls1012a.dtsi | 7 +++++++
 arch/arm/dts/fsl-ls1043a.dtsi | 7 +++++++
 arch/arm/dts/fsl-ls1046a.dtsi | 7 +++++++
 arch/arm/dts/ls1021a.dtsi     | 7 +++++++
 4 files changed, 28 insertions(+)

diff --git a/arch/arm/dts/fsl-ls1012a.dtsi b/arch/arm/dts/fsl-ls1012a.dtsi
index 0ea899c7d7..afdaec1ca1 100644
--- a/arch/arm/dts/fsl-ls1012a.dtsi
+++ b/arch/arm/dts/fsl-ls1012a.dtsi
@@ -34,6 +34,13 @@
 		#size-cells = <2>;
 		ranges;
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x1000>;
+			clocks = <&clockgen 4 3>;
+			clock-names = "sfp";
+		};
+
 		clockgen: clocking@1ee1000 {
 			compatible = "fsl,ls1012a-clockgen";
 			reg = <0x0 0x1ee1000 0x0 0x1000>;
diff --git a/arch/arm/dts/fsl-ls1043a.dtsi b/arch/arm/dts/fsl-ls1043a.dtsi
index 52dc5a9638..2303178db9 100644
--- a/arch/arm/dts/fsl-ls1043a.dtsi
+++ b/arch/arm/dts/fsl-ls1043a.dtsi
@@ -38,6 +38,13 @@
 		#size-cells = <2>;
 		ranges;
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x1000>;
+			clocks = <&clockgen 4 3>;
+			clock-names = "sfp";
+		};
+
 		clockgen: clocking@1ee1000 {
 			compatible = "fsl,ls1043a-clockgen";
 			reg = <0x0 0x1ee1000 0x0 0x1000>;
diff --git a/arch/arm/dts/fsl-ls1046a.dtsi b/arch/arm/dts/fsl-ls1046a.dtsi
index a60cbf11fc..8efa30adad 100644
--- a/arch/arm/dts/fsl-ls1046a.dtsi
+++ b/arch/arm/dts/fsl-ls1046a.dtsi
@@ -37,6 +37,13 @@
 		#size-cells = <2>;
 		ranges;
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x1000>;
+			clocks = <&clockgen 4 3>;
+			clock-names = "sfp";
+		};
+
 		clockgen: clocking@1ee1000 {
 			compatible = "fsl,ls1046a-clockgen";
 			reg = <0x0 0x1ee1000 0x0 0x1000>;
diff --git a/arch/arm/dts/ls1021a.dtsi b/arch/arm/dts/ls1021a.dtsi
index 99f7d81e20..6cee0ff520 100644
--- a/arch/arm/dts/ls1021a.dtsi
+++ b/arch/arm/dts/ls1021a.dtsi
@@ -88,6 +88,13 @@
 			interrupts = <GIC_SPI 75 IRQ_TYPE_LEVEL_HIGH>;
 		};
 
+		sfp: efuse@1e80000 {
+			compatible = "fsl,ls1021a-sfp";
+			reg = <0x0 0x1e80000 0x0 0x10000>;
+			clocks = <&clockgen 4 3>;
+			clock-names = "sfp";
+		};
+
 		dcfg: dcfg@1ee0000 {
 			compatible = "fsl,ls1021a-dcfg", "syscon";
 			reg = <0x1ee0000 0x10000>;
-- 
2.35.1.1320.gc452695387.dirty

Re: [PATCH v2 0/3] arm: layerscape: Add sfp driver

[Sean Anderson]

On 4/22/22 2:34 PM, Sean Anderson wrote:
> This adds a driver for the Security Fuse Processor (SFP). It only
> supports Trust Architecture (TA) 2.1 SFPs, but it should be fairly
> trivial to add support for TA 3.1 SFPs. See [1] for Linux
> bindings/driver support.
> 
> [1] https://lore.kernel.org/linux-arm-kernel/20220422145147.2210587-1-sean.anderson@seco.com/
> 
> Changes in v2:
> - Use the sfp clock directly, instead of assuming we get the platform
>    clock. This corresponds better to what other drivers on these devices
>    do.
> - Rename clock to "sfp" to be more descriptive.
> - update the clockgen node for ls1021a
> 
> Sean Anderson (3):
>    arm: layerscape: Add sfp driver
>    ARM: dts: ls1021a: update the clockgen node
>    arch: layerscape: Add SFP binding
> 
>   MAINTAINERS                   |   5 +
>   arch/arm/dts/fsl-ls1012a.dtsi |   7 +
>   arch/arm/dts/fsl-ls1043a.dtsi |   7 +
>   arch/arm/dts/fsl-ls1046a.dtsi |   7 +
>   arch/arm/dts/ls1021a.dtsi     |  87 ++++-----
>   drivers/misc/Kconfig          |  14 ++
>   drivers/misc/Makefile         |   1 +
>   drivers/misc/ls2_sfp.c        | 350 ++++++++++++++++++++++++++++++++++
>   8 files changed, 426 insertions(+), 52 deletions(-)
>   create mode 100644 drivers/misc/ls2_sfp.c
> 

ping

Re: [PATCH v2 0/3] arm: layerscape: Add sfp driver

[Sean Anderson]

On 8/13/22 2:16 AM, Sean Anderson wrote:
> On 4/22/22 2:34 PM, Sean Anderson wrote:
>> This adds a driver for the Security Fuse Processor (SFP). It only
>> supports Trust Architecture (TA) 2.1 SFPs, but it should be fairly
>> trivial to add support for TA 3.1 SFPs. See [1] for Linux
>> bindings/driver support.
>>
>> [1] https://lore.kernel.org/linux-arm-kernel/20220422145147.2210587-1-sean.anderson@seco.com/
>>
>> Changes in v2:
>> - Use the sfp clock directly, instead of assuming we get the platform
>>    clock. This corresponds better to what other drivers on these devices
>>    do.
>> - Rename clock to "sfp" to be more descriptive.
>> - update the clockgen node for ls1021a
>>
>> Sean Anderson (3):
>>    arm: layerscape: Add sfp driver
>>    ARM: dts: ls1021a: update the clockgen node
>>    arch: layerscape: Add SFP binding
>>
>>   MAINTAINERS                   |   5 +
>>   arch/arm/dts/fsl-ls1012a.dtsi |   7 +
>>   arch/arm/dts/fsl-ls1043a.dtsi |   7 +
>>   arch/arm/dts/fsl-ls1046a.dtsi |   7 +
>>   arch/arm/dts/ls1021a.dtsi     |  87 ++++-----
>>   drivers/misc/Kconfig          |  14 ++
>>   drivers/misc/Makefile         |   1 +
>>   drivers/misc/ls2_sfp.c        | 350 ++++++++++++++++++++++++++++++++++
>>   8 files changed, 426 insertions(+), 52 deletions(-)
>>   create mode 100644 drivers/misc/ls2_sfp.c
>>
> 
> ping

Looks like this was applied as 2645bc0e12 ("arm: layerscape: Add sfp driver") (and others)