* [PATCH 0/6] Add RZ/G2UL CLK and Reset entries for I2C,SSI,USB,CANFD,OSTM and WDT
@ 2022-04-25 9:52 Biju Das
2022-04-25 9:52 ` [PATCH 1/6] clk: renesas: r9a07g043: Add I2C clocks/resets Biju Das
` (5 more replies)
0 siblings, 6 replies; 14+ messages in thread
From: Biju Das @ 2022-04-25 9:52 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
This patch series aims to add CLK and Reset entries for I2C,SSI,USB,CANFD,
OSTM and WDT found on RZ/G2UL SoC to RZ/G2L CPG driver.
Biju Das (6):
clk: renesas: r9a07g043: Add I2C clocks/resets
clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries
clk: renesas: r9a07g043: Add USB clocks/resets
clk: renesas: r9a07g043: Add clock and reset entries for CANFD
clk: renesas: r9a07g043: Add OSTM clock and reset entries
clk: renesas: r9a07g043: Add WDT clock and reset entries
drivers/clk/renesas/r9a07g043-cpg.c | 68 +++++++++++++++++++++++++++++
1 file changed, 68 insertions(+)
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/6] clk: renesas: r9a07g043: Add I2C clocks/resets
2022-04-25 9:52 [PATCH 0/6] Add RZ/G2UL CLK and Reset entries for I2C,SSI,USB,CANFD,OSTM and WDT Biju Das
@ 2022-04-25 9:52 ` Biju Das
2022-04-28 12:21 ` Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 2/6] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries Biju Das
` (4 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-04-25 9:52 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add I2C{0,1,2,3} clock and reset entries.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g043-cpg.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 2d6c96789f5c..961216d55e0b 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -152,6 +152,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x57c, 1),
DEF_COUPLED("eth1_chi", R9A07G043_ETH1_CLK_CHI, R9A07G043_CLK_ZT,
0x57c, 1),
+ DEF_MOD("i2c0", R9A07G043_I2C0_PCLK, R9A07G043_CLK_P0,
+ 0x580, 0),
+ DEF_MOD("i2c1", R9A07G043_I2C1_PCLK, R9A07G043_CLK_P0,
+ 0x580, 1),
+ DEF_MOD("i2c2", R9A07G043_I2C2_PCLK, R9A07G043_CLK_P0,
+ 0x580, 2),
+ DEF_MOD("i2c3", R9A07G043_I2C3_PCLK, R9A07G043_CLK_P0,
+ 0x580, 3),
DEF_MOD("scif0", R9A07G043_SCIF0_CLK_PCK, R9A07G043_CLK_P0,
0x584, 0),
DEF_MOD("scif1", R9A07G043_SCIF1_CLK_PCK, R9A07G043_CLK_P0,
@@ -180,6 +188,10 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
+ DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),
+ DEF_RST(R9A07G043_I2C1_MRST, 0x880, 1),
+ DEF_RST(R9A07G043_I2C2_MRST, 0x880, 2),
+ DEF_RST(R9A07G043_I2C3_MRST, 0x880, 3),
DEF_RST(R9A07G043_SCIF0_RST_SYSTEM_N, 0x884, 0),
DEF_RST(R9A07G043_SCIF1_RST_SYSTEM_N, 0x884, 1),
DEF_RST(R9A07G043_SCIF2_RST_SYSTEM_N, 0x884, 2),
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/6] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries
2022-04-25 9:52 [PATCH 0/6] Add RZ/G2UL CLK and Reset entries for I2C,SSI,USB,CANFD,OSTM and WDT Biju Das
2022-04-25 9:52 ` [PATCH 1/6] clk: renesas: r9a07g043: Add I2C clocks/resets Biju Das
@ 2022-04-25 9:52 ` Biju Das
2022-04-28 12:21 ` Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 3/6] clk: renesas: r9a07g043: Add USB clocks/resets Biju Das
` (3 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-04-25 9:52 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g043-cpg.c | 20 ++++++++++++++++++++
1 file changed, 20 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 961216d55e0b..d54bccf7b61b 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -144,6 +144,22 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x554, 6),
DEF_MOD("sdhi1_aclk", R9A07G043_SDHI1_ACLK, R9A07G043_CLK_P1,
0x554, 7),
+ DEF_MOD("ssi0_pclk", R9A07G043_SSI0_PCLK2, R9A07G043_CLK_P0,
+ 0x570, 0),
+ DEF_MOD("ssi0_sfr", R9A07G043_SSI0_PCLK_SFR, R9A07G043_CLK_P0,
+ 0x570, 1),
+ DEF_MOD("ssi1_pclk", R9A07G043_SSI1_PCLK2, R9A07G043_CLK_P0,
+ 0x570, 2),
+ DEF_MOD("ssi1_sfr", R9A07G043_SSI1_PCLK_SFR, R9A07G043_CLK_P0,
+ 0x570, 3),
+ DEF_MOD("ssi2_pclk", R9A07G043_SSI2_PCLK2, R9A07G043_CLK_P0,
+ 0x570, 4),
+ DEF_MOD("ssi2_sfr", R9A07G043_SSI2_PCLK_SFR, R9A07G043_CLK_P0,
+ 0x570, 5),
+ DEF_MOD("ssi3_pclk", R9A07G043_SSI3_PCLK2, R9A07G043_CLK_P0,
+ 0x570, 6),
+ DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0,
+ 0x570, 7),
DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,
0x57c, 0),
DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,
@@ -186,6 +202,10 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
+ DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),
+ DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1),
+ DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2),
+ DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3),
DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/6] clk: renesas: r9a07g043: Add USB clocks/resets
2022-04-25 9:52 [PATCH 0/6] Add RZ/G2UL CLK and Reset entries for I2C,SSI,USB,CANFD,OSTM and WDT Biju Das
2022-04-25 9:52 ` [PATCH 1/6] clk: renesas: r9a07g043: Add I2C clocks/resets Biju Das
2022-04-25 9:52 ` [PATCH 2/6] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries Biju Das
@ 2022-04-25 9:52 ` Biju Das
2022-04-28 12:21 ` Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 4/6] clk: renesas: r9a07g043: Add clock and reset entries for CANFD Biju Das
` (2 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-04-25 9:52 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add clock/reset entries for USB PHY control, USB2.0 host and device.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g043-cpg.c | 12 ++++++++++++
1 file changed, 12 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index d54bccf7b61b..ea826f000d8d 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -160,6 +160,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x570, 6),
DEF_MOD("ssi3_sfr", R9A07G043_SSI3_PCLK_SFR, R9A07G043_CLK_P0,
0x570, 7),
+ DEF_MOD("usb0_host", R9A07G043_USB_U2H0_HCLK, R9A07G043_CLK_P1,
+ 0x578, 0),
+ DEF_MOD("usb1_host", R9A07G043_USB_U2H1_HCLK, R9A07G043_CLK_P1,
+ 0x578, 1),
+ DEF_MOD("usb0_func", R9A07G043_USB_U2P_EXR_CPUCLK, R9A07G043_CLK_P1,
+ 0x578, 2),
+ DEF_MOD("usb_pclk", R9A07G043_USB_PCLK, R9A07G043_CLK_P1,
+ 0x578, 3),
DEF_COUPLED("eth0_axi", R9A07G043_ETH0_CLK_AXI, R9A07G043_CLK_M0,
0x57c, 0),
DEF_COUPLED("eth0_chi", R9A07G043_ETH0_CLK_CHI, R9A07G043_CLK_ZT,
@@ -206,6 +214,10 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_SSI1_RST_M2_REG, 0x870, 1),
DEF_RST(R9A07G043_SSI2_RST_M2_REG, 0x870, 2),
DEF_RST(R9A07G043_SSI3_RST_M2_REG, 0x870, 3),
+ DEF_RST(R9A07G043_USB_U2H0_HRESETN, 0x878, 0),
+ DEF_RST(R9A07G043_USB_U2H1_HRESETN, 0x878, 1),
+ DEF_RST(R9A07G043_USB_U2P_EXL_SYSRST, 0x878, 2),
+ DEF_RST(R9A07G043_USB_PRESETN, 0x878, 3),
DEF_RST(R9A07G043_ETH0_RST_HW_N, 0x87c, 0),
DEF_RST(R9A07G043_ETH1_RST_HW_N, 0x87c, 1),
DEF_RST(R9A07G043_I2C0_MRST, 0x880, 0),
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/6] clk: renesas: r9a07g043: Add clock and reset entries for CANFD
2022-04-25 9:52 [PATCH 0/6] Add RZ/G2UL CLK and Reset entries for I2C,SSI,USB,CANFD,OSTM and WDT Biju Das
` (2 preceding siblings ...)
2022-04-25 9:52 ` [PATCH 3/6] clk: renesas: r9a07g043: Add USB clocks/resets Biju Das
@ 2022-04-25 9:52 ` Biju Das
2022-04-28 12:20 ` Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 5/6] clk: renesas: r9a07g043: Add OSTM clock and reset entries Biju Das
2022-04-25 9:52 ` [PATCH 6/6] clk: renesas: r9a07g043: Add WDT " Biju Das
5 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-04-25 9:52 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add clock and reset entries for CANFD in CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g043-cpg.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index ea826f000d8d..59d5405474a5 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -100,6 +100,7 @@ static const struct cpg_core_clk r9a07g043_core_clks[] __initconst = {
CLK_DIVIDER_HIWORD_MASK),
DEF_DIV("P0", R9A07G043_CLK_P0, CLK_PLL2_DIV2_8, DIVPL2A,
dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
+ DEF_FIXED("P0_DIV2", R9A07G043_CLK_P0_DIV2, R9A07G043_CLK_P0, 1, 2),
DEF_DIV("P1", R9A07G043_CLK_P1, CLK_PLL3_DIV2_4,
DIVPL3B, dtable_1_32, CLK_DIVIDER_HIWORD_MASK),
DEF_FIXED("P1_DIV2", CLK_P1_DIV2, R9A07G043_CLK_P1, 1, 2),
@@ -198,6 +199,8 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x588, 0),
DEF_MOD("sci1", R9A07G043_SCI1_CLKP, R9A07G043_CLK_P0,
0x588, 1),
+ DEF_MOD("canfd", R9A07G043_CANFD_PCLK, R9A07G043_CLK_P0,
+ 0x594, 0),
DEF_MOD("gpio", R9A07G043_GPIO_HCLK, R9A07G043_OSCCLK,
0x598, 0),
};
@@ -231,6 +234,8 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_SCIF4_RST_SYSTEM_N, 0x884, 4),
DEF_RST(R9A07G043_SCI0_RST, 0x888, 0),
DEF_RST(R9A07G043_SCI1_RST, 0x888, 1),
+ DEF_RST(R9A07G043_CANFD_RSTP_N, 0x894, 0),
+ DEF_RST(R9A07G043_CANFD_RSTC_N, 0x894, 1),
DEF_RST(R9A07G043_GPIO_RSTN, 0x898, 0),
DEF_RST(R9A07G043_GPIO_PORT_RESETN, 0x898, 1),
DEF_RST(R9A07G043_GPIO_SPARE_RESETN, 0x898, 2),
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/6] clk: renesas: r9a07g043: Add OSTM clock and reset entries
2022-04-25 9:52 [PATCH 0/6] Add RZ/G2UL CLK and Reset entries for I2C,SSI,USB,CANFD,OSTM and WDT Biju Das
` (3 preceding siblings ...)
2022-04-25 9:52 ` [PATCH 4/6] clk: renesas: r9a07g043: Add clock and reset entries for CANFD Biju Das
@ 2022-04-25 9:52 ` Biju Das
2022-04-28 12:19 ` Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 6/6] clk: renesas: r9a07g043: Add WDT " Biju Das
5 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-04-25 9:52 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add OSTM{0,1,2} clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g043-cpg.c | 9 +++++++++
1 file changed, 9 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index 59d5405474a5..ac2b361efbb6 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -129,6 +129,12 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x52c, 0),
DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
0x52c, 1),
+ DEF_MOD("ostm0", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0,
+ 0x534, 0),
+ DEF_MOD("ostm1", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0,
+ 0x534, 1),
+ DEF_MOD("ostm2", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
+ 0x534, 2),
DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4,
0x554, 0),
DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4,
@@ -211,6 +217,9 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_IA55_RESETN, 0x818, 0),
DEF_RST(R9A07G043_DMAC_ARESETN, 0x82c, 0),
DEF_RST(R9A07G043_DMAC_RST_ASYNC, 0x82c, 1),
+ DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
+ DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
+ DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 6/6] clk: renesas: r9a07g043: Add WDT clock and reset entries
2022-04-25 9:52 [PATCH 0/6] Add RZ/G2UL CLK and Reset entries for I2C,SSI,USB,CANFD,OSTM and WDT Biju Das
` (4 preceding siblings ...)
2022-04-25 9:52 ` [PATCH 5/6] clk: renesas: r9a07g043: Add OSTM clock and reset entries Biju Das
@ 2022-04-25 9:52 ` Biju Das
2022-04-28 12:18 ` Geert Uytterhoeven
5 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-04-25 9:52 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd
Cc: Biju Das, Geert Uytterhoeven, linux-renesas-soc, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add WDT{0,2} clock and reset entries to CPG driver.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
drivers/clk/renesas/r9a07g043-cpg.c | 10 ++++++++++
1 file changed, 10 insertions(+)
diff --git a/drivers/clk/renesas/r9a07g043-cpg.c b/drivers/clk/renesas/r9a07g043-cpg.c
index ac2b361efbb6..c7e5efc17965 100644
--- a/drivers/clk/renesas/r9a07g043-cpg.c
+++ b/drivers/clk/renesas/r9a07g043-cpg.c
@@ -135,6 +135,14 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
0x534, 1),
DEF_MOD("ostm2", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
0x534, 2),
+ DEF_MOD("wdt0_pclk", R9A07G043_WDT0_PCLK, R9A07G043_CLK_P0,
+ 0x548, 0),
+ DEF_MOD("wdt0_clk", R9A07G043_WDT0_CLK, R9A07G043_OSCCLK,
+ 0x548, 1),
+ DEF_MOD("wdt2_pclk", R9A07G043_WDT2_PCLK, R9A07G043_CLK_P0,
+ 0x548, 4),
+ DEF_MOD("wdt2_clk", R9A07G043_WDT2_CLK, R9A07G043_OSCCLK,
+ 0x548, 5),
DEF_MOD("sdhi0_imclk", R9A07G043_SDHI0_IMCLK, CLK_SD0_DIV4,
0x554, 0),
DEF_MOD("sdhi0_imclk2", R9A07G043_SDHI0_IMCLK2, CLK_SD0_DIV4,
@@ -220,6 +228,8 @@ static struct rzg2l_reset r9a07g043_resets[] = {
DEF_RST(R9A07G043_OSTM0_PRESETZ, 0x834, 0),
DEF_RST(R9A07G043_OSTM1_PRESETZ, 0x834, 1),
DEF_RST(R9A07G043_OSTM2_PRESETZ, 0x834, 2),
+ DEF_RST(R9A07G043_WDT0_PRESETN, 0x848, 0),
+ DEF_RST(R9A07G043_WDT2_PRESETN, 0x848, 2),
DEF_RST(R9A07G043_SDHI0_IXRST, 0x854, 0),
DEF_RST(R9A07G043_SDHI1_IXRST, 0x854, 1),
DEF_RST(R9A07G043_SSI0_RST_M2_REG, 0x870, 0),
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 6/6] clk: renesas: r9a07g043: Add WDT clock and reset entries
2022-04-25 9:52 ` [PATCH 6/6] clk: renesas: r9a07g043: Add WDT " Biju Das
@ 2022-04-28 12:18 ` Geert Uytterhoeven
0 siblings, 0 replies; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-04-28 12:18 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Geert Uytterhoeven,
Linux-Renesas, linux-clk, Chris Paterson, Biju Das,
Prabhakar Mahadev Lad
On Mon, Apr 25, 2022 at 11:53 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add WDT{0,2} clock and reset entries to CPG driver.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 5/6] clk: renesas: r9a07g043: Add OSTM clock and reset entries
2022-04-25 9:52 ` [PATCH 5/6] clk: renesas: r9a07g043: Add OSTM clock and reset entries Biju Das
@ 2022-04-28 12:19 ` Geert Uytterhoeven
2022-04-28 12:23 ` Biju Das
0 siblings, 1 reply; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-04-28 12:19 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Biju,
On Mon, Apr 25, 2022 at 11:53 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add OSTM{0,1,2} clock and reset entries to CPG driver.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Thanks for your patch!
> --- a/drivers/clk/renesas/r9a07g043-cpg.c
> +++ b/drivers/clk/renesas/r9a07g043-cpg.c
> @@ -129,6 +129,12 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] = {
> 0x52c, 0),
> DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
> 0x52c, 1),
> + DEF_MOD("ostm0", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0,
> + 0x534, 0),
> + DEF_MOD("ostm1", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0,
> + 0x534, 1),
> + DEF_MOD("ostm2", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
> + 0x534, 2),
Do you mind if I change the clock names to "ostm[012_pclk"
while applying, for consistency with r9a07g044-cpg.c.
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 4/6] clk: renesas: r9a07g043: Add clock and reset entries for CANFD
2022-04-25 9:52 ` [PATCH 4/6] clk: renesas: r9a07g043: Add clock and reset entries for CANFD Biju Das
@ 2022-04-28 12:20 ` Geert Uytterhoeven
0 siblings, 0 replies; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-04-28 12:20 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Mon, Apr 25, 2022 at 11:53 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add clock and reset entries for CANFD in CPG driver.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/6] clk: renesas: r9a07g043: Add USB clocks/resets
2022-04-25 9:52 ` [PATCH 3/6] clk: renesas: r9a07g043: Add USB clocks/resets Biju Das
@ 2022-04-28 12:21 ` Geert Uytterhoeven
0 siblings, 0 replies; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-04-28 12:21 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Mon, Apr 25, 2022 at 11:53 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add clock/reset entries for USB PHY control, USB2.0 host and device.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/6] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries
2022-04-25 9:52 ` [PATCH 2/6] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries Biju Das
@ 2022-04-28 12:21 ` Geert Uytterhoeven
0 siblings, 0 replies; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-04-28 12:21 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Mon, Apr 25, 2022 at 11:53 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add SSIF-2{0,1,2,3} clock and reset entries in CPG driver.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/6] clk: renesas: r9a07g043: Add I2C clocks/resets
2022-04-25 9:52 ` [PATCH 1/6] clk: renesas: r9a07g043: Add I2C clocks/resets Biju Das
@ 2022-04-28 12:21 ` Geert Uytterhoeven
0 siblings, 0 replies; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-04-28 12:21 UTC (permalink / raw)
To: Biju Das
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Mon, Apr 25, 2022 at 11:52 AM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add I2C{0,1,2,3} clock and reset entries.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-clk-for-v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH 5/6] clk: renesas: r9a07g043: Add OSTM clock and reset entries
2022-04-28 12:19 ` Geert Uytterhoeven
@ 2022-04-28 12:23 ` Biju Das
0 siblings, 0 replies; 14+ messages in thread
From: Biju Das @ 2022-04-28 12:23 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Michael Turquette, Stephen Boyd, Linux-Renesas, linux-clk,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Geert,
Thanks for the feedback.
> Subject: Re: [PATCH 5/6] clk: renesas: r9a07g043: Add OSTM clock and reset
> entries
>
> Hi Biju,
>
> On Mon, Apr 25, 2022 at 11:53 AM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Add OSTM{0,1,2} clock and reset entries to CPG driver.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/drivers/clk/renesas/r9a07g043-cpg.c
> > +++ b/drivers/clk/renesas/r9a07g043-cpg.c
> > @@ -129,6 +129,12 @@ static struct rzg2l_mod_clk r9a07g043_mod_clks[] =
> {
> > 0x52c, 0),
> > DEF_MOD("dmac_pclk", R9A07G043_DMAC_PCLK, CLK_P1_DIV2,
> > 0x52c, 1),
> > + DEF_MOD("ostm0", R9A07G043_OSTM0_PCLK, R9A07G043_CLK_P0,
> > + 0x534, 0),
> > + DEF_MOD("ostm1", R9A07G043_OSTM1_PCLK, R9A07G043_CLK_P0,
> > + 0x534, 1),
> > + DEF_MOD("ostm2", R9A07G043_OSTM2_PCLK, R9A07G043_CLK_P0,
> > + 0x534, 2),
>
> Do you mind if I change the clock names to "ostm[012_pclk"
> while applying, for consistency with r9a07g044-cpg.c.
Thanks, Ok for me.
Cheers,
Biju
>
> Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be> i.e. will queue
> in renesas-clk-for-v5.19.
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-04-28 12:23 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-25 9:52 [PATCH 0/6] Add RZ/G2UL CLK and Reset entries for I2C,SSI,USB,CANFD,OSTM and WDT Biju Das
2022-04-25 9:52 ` [PATCH 1/6] clk: renesas: r9a07g043: Add I2C clocks/resets Biju Das
2022-04-28 12:21 ` Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 2/6] clk: renesas: r9a07g043: Add SSIF-2 clock and reset entries Biju Das
2022-04-28 12:21 ` Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 3/6] clk: renesas: r9a07g043: Add USB clocks/resets Biju Das
2022-04-28 12:21 ` Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 4/6] clk: renesas: r9a07g043: Add clock and reset entries for CANFD Biju Das
2022-04-28 12:20 ` Geert Uytterhoeven
2022-04-25 9:52 ` [PATCH 5/6] clk: renesas: r9a07g043: Add OSTM clock and reset entries Biju Das
2022-04-28 12:19 ` Geert Uytterhoeven
2022-04-28 12:23 ` Biju Das
2022-04-25 9:52 ` [PATCH 6/6] clk: renesas: r9a07g043: Add WDT " Biju Das
2022-04-28 12:18 ` Geert Uytterhoeven
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