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From: Mark Brown <broonie@kernel.org>
To: Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will@kernel.org>
Cc: Mark Rutland <mark.rutland@arm.com>,
	Marc Zyngier <maz@kernel.org>,
	Suzuki K Poulose <suzuki.poulose@arm.com>,
	linux-arm-kernel@lists.infradead.org,
	Mark Brown <broonie@kernel.org>
Subject: [PATCH v5 04/12] arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI
Date: Tue, 26 Apr 2022 19:16:56 +0100	[thread overview]
Message-ID: <20220426181704.2583494-5-broonie@kernel.org> (raw)
In-Reply-To: <20220426181704.2583494-1-broonie@kernel.org>

We already use lower case in some defines in sysreg.h, for consistency with
the architecture definition do so for SCTLR_EL1.nTWE and SCTLR_EL1.nTWI.

No functional change.

Signed-off-by: Mark Brown <broonie@kernel.org>
Acked-by: Mark Rutland <mark.rutland@arm.com>
---
 arch/arm64/include/asm/sysreg.h | 6 +++---
 1 file changed, 3 insertions(+), 3 deletions(-)

diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
index 732d84111d9f..7e9de3c87cd9 100644
--- a/arch/arm64/include/asm/sysreg.h
+++ b/arch/arm64/include/asm/sysreg.h
@@ -689,8 +689,8 @@
 #define SCTLR_EL1_UCI		(BIT(26))
 #define SCTLR_EL1_E0E		(BIT(24))
 #define SCTLR_EL1_SPAN		(BIT(23))
-#define SCTLR_EL1_NTWE		(BIT(18))
-#define SCTLR_EL1_NTWI		(BIT(16))
+#define SCTLR_EL1_nTWE		(BIT(18))
+#define SCTLR_EL1_nTWI		(BIT(16))
 #define SCTLR_EL1_UCT		(BIT(15))
 #define SCTLR_EL1_DZE		(BIT(14))
 #define SCTLR_EL1_UMA		(BIT(9))
@@ -714,7 +714,7 @@
 #define INIT_SCTLR_EL1_MMU_ON \
 	(SCTLR_ELx_M    | SCTLR_ELx_C    | SCTLR_ELx_SA   | SCTLR_EL1_SA0   | \
 	 SCTLR_EL1_SED  | SCTLR_ELx_I    | SCTLR_EL1_DZE  | SCTLR_EL1_UCT   | \
-	 SCTLR_EL1_NTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
+	 SCTLR_EL1_nTWE | SCTLR_ELx_IESB | SCTLR_EL1_SPAN | SCTLR_ELx_ITFSB | \
 	 ENDIAN_SET_EL1 | SCTLR_EL1_UCI  | SCTLR_EL1_EPAN | SCTLR_EL1_RES1)
 
 /* MAIR_ELx memory attributes (used by Linux) */
-- 
2.30.2


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  parent reply	other threads:[~2022-04-26 18:21 UTC|newest]

Thread overview: 17+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-26 18:16 [PATCH v5 00/12] arm64: Automatic system register definition generation Mark Brown
2022-04-26 18:16 ` [PATCH v5 01/12] arm64/sysreg: Introduce helpers for access to sysreg fields Mark Brown
2022-04-26 18:16 ` [PATCH v5 02/12] arm64/mte: Make TCF0 naming and field values more standard Mark Brown
2022-04-26 18:16 ` [PATCH v5 03/12] arm64/mte: Make TCF field values and naming " Mark Brown
2022-04-26 18:16 ` Mark Brown [this message]
2022-04-26 18:16 ` [PATCH v5 05/12] arm64/sysreg: Define bits for previously RES1 fields in SCTLR_EL1 Mark Brown
2022-04-26 18:16 ` [PATCH v5 06/12] arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARM Mark Brown
2022-04-28 13:31   ` Mark Rutland
2022-04-26 18:16 ` [PATCH v5 07/12] arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names Mark Brown
2022-04-26 18:17 ` [PATCH v5 08/12] arm64: Add sysreg header generation scripting Mark Brown
2022-04-26 18:17 ` [PATCH v5 09/12] arm64/sysreg: Enable automatic generation of system register definitions Mark Brown
2022-04-26 18:17 ` [PATCH v5 10/12] arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1 Mark Brown
2022-04-26 18:17 ` [PATCH v5 11/12] arm64/sysreg: Generate definitions for TTBRn_EL1 Mark Brown
2022-04-26 18:17 ` [PATCH v5 12/12] arm64/sysreg: Generate definitions for SCTLR_EL1 Mark Brown
2022-05-03 11:28 ` [PATCH v5 00/12] arm64: Automatic system register definition generation Catalin Marinas
2022-05-03 12:58   ` Mark Rutland
2022-05-03 16:32   ` Mark Brown

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