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* [PATCH v5 00/12] arm64: Automatic system register definition generation
@ 2022-04-26 18:16 Mark Brown
  2022-04-26 18:16 ` [PATCH v5 01/12] arm64/sysreg: Introduce helpers for access to sysreg fields Mark Brown
                   ` (12 more replies)
  0 siblings, 13 replies; 17+ messages in thread
From: Mark Brown @ 2022-04-26 18:16 UTC (permalink / raw)
  To: Catalin Marinas, Will Deacon
  Cc: Mark Rutland, Marc Zyngier, Suzuki K Poulose, linux-arm-kernel,
	Mark Brown

The arm64 kernel requires some metadata for each system register it may
need to access. Currently we have:

* A SYS_<regname> definition which sorresponds to a sys_reg() macro.
  This is used both to look up a sysreg by encoding (e.g. in KVM), and
  also to generate code to access a sysreg where the assembler is
  unaware of the specific sysreg encoding.

  Where assemblers support the S3_<op1>_C<crn>_C<crm>_<op2> syntax for
  system registers, we could use this rather than manually assembling
  the instructions. However, we don't have consistent definitions for
  these and we currently still need to handle toolchains that lack this
  feature.

* A set of <regname>_<fieldname>_SHIFT and <regname>_<fieldname>_MASK
  definitions, which can be used to extract fields from the register, or
  to construct a register from a set of fields.

  These do not follow the convention used by <linux/bitfield.h>, and the
  masks are not shifted into place, preventing their use in FIELD_PREP()
  and FIELD_GET(). We require the SHIFT definitions for inline assembly
  (and WIDTH definitions would be helpful for UBFX/SBFX), so we cannot
  only define a shifted MASK. Defining a SHIFT, WIDTH, shifted MASK and
  unshifted MASK is tedious and error-prone and life is much easier when
  they can be relied up to exist when writing code.

* A set of <regname>_<fieldname>_<valname> definitions for each
  enumerated value a field may hold. These are used when identifying the
  presence of features.

Atop of this, other code has to build up metadata at runtime (e.g. the
sets of RES0/RES1 bits in a register). This patch series introduces a
script which describes registers and the fields within them in a format
that is easy to cross reference with the architecture reference manual
and uses them to generate the constants we use in a standard format:

| #define REG_ID_AA64ISAR0_EL1                    S3_0_C0_C6_0
| #define SYS_ID_AA64ISAR0_EL1                    sys_reg(3, 0, 0, 6, 0)
| #define SYS_ID_AA64ISAR0_EL1_Op0                3
| #define SYS_ID_AA64ISAR0_EL1_Op1                0
| #define SYS_ID_AA64ISAR0_EL1_CRn                0
| #define SYS_ID_AA64ISAR0_EL1_CRm                6
| #define SYS_ID_AA64ISAR0_EL1_Op2                0

| #define ID_AA64ISAR0_EL1_RNDR                   GENMASK(63, 60)
| #define ID_AA64ISAR0_EL1_RNDR_MASK              GENMASK(63, 60)
| #define ID_AA64ISAR0_EL1_RNDR_SHIFT             60
| #define ID_AA64ISAR0_EL1_RNDR_WIDTH             4
| #define ID_AA64ISAR0_EL1_RNDR_NI                UL(0b0000)
| #define ID_AA64ISAR0_EL1_RNDR_IMP               UL(0b0001)

This should be particularly useful for the ID registers where we will be
able to specify just the register and field for more of the bitfield
information, simplifying ARM64_FTR_BITS() and providing helpers for use
in struct arm64_cpu_capabilities or for hwcaps.

For registers which have shared definitions (eg, registers that have
versions with identical layouts at multiple ELs) we support defining a
shared layout for those registers which is then referenced from the per
register definition.

At the moment this is only intended to express metadata from the
architecture, and does not handle policy imposed by the kernel, such as
values exposed to userspace or VMs. In future this could be extended to
express such information. This could also be extended to cover more
information such as the FTR_SIGNED/FTR_UNSIGNED distinction. There is
also currently no support for registers which change layout at runtime,
for example based on virtualisation settings - these could be manually
handled for the time being, or the script extended.

Rather than attempting to convert every register at once the current
series converts a few sample registers to provide some concrete examples
but allow for easier updating during review of the file format and the
script.  Handling a register at a time should also make review less
taxing so it seems like a sensible approach in general.

The generation script was originally written by Mark Rutland and
subsequently improved and integrated into the kernel build by me.

v5:
 - Introduce and use SYS_FIELD_PREP() and SYS_FIELD_PREP_ENUM().
 - Use helper macros for SCTLR_ELx.TCF as well as TCF0.
 - Rename sysreg-gen.h to sysreg-defs.h.
 - Use UL rather than ULL.
 - Implement a SharedLayout statement, currently as a noop.
 - Fix checks to ensure regexps only match in the correct block in the
   script.
 - Minor stylistic tweaks.
v4:
 - Rebase onto v5.18-rc3.
v3:
 - Rebase onto v5.18-rc1.
v2:
 - Fix issue with building bounds.s in an O= build by renaming the
   generated header.

Mark Brown (11):
  arm64/sysreg: Introduce helpers for access to sysreg fields
  arm64/mte: Make TCF0 naming and field values more standard
  arm64/mte: Make TCF field values and naming more standard
  arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI
  arm64/sysreg: Define bits for previously RES1 fields in SCTLR_EL1
  arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARM
  arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names
  arm64/sysreg: Enable automatic generation of system register
    definitions
  arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1
  arm64/sysreg: Generate definitions for TTBRn_EL1
  arm64/sysreg: Generate definitions for SCTLR_EL1

Mark Rutland (1):
  arm64: Add sysreg header generation scripting

 arch/arm64/include/asm/Kbuild                 |   1 +
 arch/arm64/include/asm/archrandom.h           |   2 +-
 arch/arm64/include/asm/sysreg.h               | 117 +++-----
 arch/arm64/kernel/cpufeature.c                |  70 ++---
 arch/arm64/kernel/mte.c                       |  15 +-
 .../arm64/kvm/hyp/include/nvhe/fixed_config.h |  28 +-
 arch/arm64/mm/fault.c                         |   3 +-
 arch/arm64/tools/Makefile                     |   8 +-
 arch/arm64/tools/gen-sysreg.awk               | 267 ++++++++++++++++++
 arch/arm64/tools/sysreg                       | 200 +++++++++++++
 10 files changed, 576 insertions(+), 135 deletions(-)
 create mode 100755 arch/arm64/tools/gen-sysreg.awk
 create mode 100644 arch/arm64/tools/sysreg


base-commit: b2d229d4ddb17db541098b83524d901257e93845
-- 
2.30.2


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^ permalink raw reply	[flat|nested] 17+ messages in thread
end of thread, other threads:[~2022-05-03 16:34 UTC | newest]

Thread overview: 17+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-04-26 18:16 [PATCH v5 00/12] arm64: Automatic system register definition generation Mark Brown
2022-04-26 18:16 ` [PATCH v5 01/12] arm64/sysreg: Introduce helpers for access to sysreg fields Mark Brown
2022-04-26 18:16 ` [PATCH v5 02/12] arm64/mte: Make TCF0 naming and field values more standard Mark Brown
2022-04-26 18:16 ` [PATCH v5 03/12] arm64/mte: Make TCF field values and naming " Mark Brown
2022-04-26 18:16 ` [PATCH v5 04/12] arm64/sysreg: Rename SCTLR_EL1_NTWE/TWI to SCTLR_EL1_nTWE/TWI Mark Brown
2022-04-26 18:16 ` [PATCH v5 05/12] arm64/sysreg: Define bits for previously RES1 fields in SCTLR_EL1 Mark Brown
2022-04-26 18:16 ` [PATCH v5 06/12] arm64: Update name of ID_AA64ISAR0_EL1_ATOMIC to reflect ARM Mark Brown
2022-04-28 13:31   ` Mark Rutland
2022-04-26 18:16 ` [PATCH v5 07/12] arm64/sysreg: Standardise ID_AA64ISAR0_EL1 macro names Mark Brown
2022-04-26 18:17 ` [PATCH v5 08/12] arm64: Add sysreg header generation scripting Mark Brown
2022-04-26 18:17 ` [PATCH v5 09/12] arm64/sysreg: Enable automatic generation of system register definitions Mark Brown
2022-04-26 18:17 ` [PATCH v5 10/12] arm64/sysreg: Generate definitions for ID_AA64ISAR0_EL1 Mark Brown
2022-04-26 18:17 ` [PATCH v5 11/12] arm64/sysreg: Generate definitions for TTBRn_EL1 Mark Brown
2022-04-26 18:17 ` [PATCH v5 12/12] arm64/sysreg: Generate definitions for SCTLR_EL1 Mark Brown
2022-05-03 11:28 ` [PATCH v5 00/12] arm64: Automatic system register definition generation Catalin Marinas
2022-05-03 12:58   ` Mark Rutland
2022-05-03 16:32   ` Mark Brown

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