* [PATCH v2 0/7] Add support for several new rk3566 SBCs
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip
Cc: heiko, Peter Geis, devicetree, linux-arm-kernel, linux-kernel
The following series adds support for the following single board
computers:
- Pine64 Quartz64 Model B
- Pine64 SoQuartz SoM with RPi CM4IO carrier board
- Firefly Station M2
Patches 1, 2, and 3 add the requisite dt-bindings.
Patch 4 adds support for the SFC to the rk356x device tree.
Patch 5 adds the Quartz64 Model B device tree.
Patch 6 adds the SoQuartz CM4IO device tree.
Patch 7 adds the Firefly Station M2 device tree.
Please review and apply at your convenience.
Very Respectfully,
Peter Geis
Changelog:
v2:
- squash Model B into Model A binding
- collect acks
Furkan Kardame (1):
arm64: dts: rockchip: add dts for Firefly Station M2 rk3566
Peter Geis (6):
dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B
dt-bindings: arm: rockchip: Add Pine64 SoQuartz SoM
dt-bindings: arm: rockchip: Add Firefly Station M2
arm64: dts: rockchip: add rk356x sfc support
arm64: dts: rockchip: add Pine64 Quartz64-B device tree
arm64: dts: rockchip: add SoQuartz CM4IO dts
.../devicetree/bindings/arm/rockchip.yaml | 18 +-
arch/arm64/boot/dts/rockchip/Makefile | 3 +
.../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
.../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 580 +++++++++++++++++
.../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 167 +++++
.../boot/dts/rockchip/rk3566-soquartz.dtsi | 607 +++++++++++++++++
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +
7 files changed, 1999 insertions(+), 2 deletions(-)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v2 0/7] Add support for several new rk3566 SBCs
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip
Cc: heiko, Peter Geis, devicetree, linux-arm-kernel, linux-kernel
The following series adds support for the following single board
computers:
- Pine64 Quartz64 Model B
- Pine64 SoQuartz SoM with RPi CM4IO carrier board
- Firefly Station M2
Patches 1, 2, and 3 add the requisite dt-bindings.
Patch 4 adds support for the SFC to the rk356x device tree.
Patch 5 adds the Quartz64 Model B device tree.
Patch 6 adds the SoQuartz CM4IO device tree.
Patch 7 adds the Firefly Station M2 device tree.
Please review and apply at your convenience.
Very Respectfully,
Peter Geis
Changelog:
v2:
- squash Model B into Model A binding
- collect acks
Furkan Kardame (1):
arm64: dts: rockchip: add dts for Firefly Station M2 rk3566
Peter Geis (6):
dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B
dt-bindings: arm: rockchip: Add Pine64 SoQuartz SoM
dt-bindings: arm: rockchip: Add Firefly Station M2
arm64: dts: rockchip: add rk356x sfc support
arm64: dts: rockchip: add Pine64 Quartz64-B device tree
arm64: dts: rockchip: add SoQuartz CM4IO dts
.../devicetree/bindings/arm/rockchip.yaml | 18 +-
arch/arm64/boot/dts/rockchip/Makefile | 3 +
.../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
.../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 580 +++++++++++++++++
.../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 167 +++++
.../boot/dts/rockchip/rk3566-soquartz.dtsi | 607 +++++++++++++++++
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +
7 files changed, 1999 insertions(+), 2 deletions(-)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v2 1/7] dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B
2022-04-29 11:52 ` Peter Geis
(?)
@ 2022-04-29 11:52 ` Peter Geis
-1 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel
The Quartz64 Model B is a compact single board computer from Pine64
based on the rk3566 SoC. It outputs on uart2 for the debug console.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index eece92f83a2d..beb5b0ac1a2a 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -502,9 +502,11 @@ properties:
- const: pine64,rockpro64
- const: rockchip,rk3399
- - description: Pine64 Quartz64 Model A
+ - description: Pine64 Quartz64 Model A/B
items:
- - const: pine64,quartz64-a
+ - enum:
+ - pine64,quartz64-a
+ - pine64,quartz64-b
- const: rockchip,rk3566
- description: Radxa Rock
--
2.25.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [PATCH v2 1/7] dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel
The Quartz64 Model B is a compact single board computer from Pine64
based on the rk3566 SoC. It outputs on uart2 for the debug console.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index eece92f83a2d..beb5b0ac1a2a 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -502,9 +502,11 @@ properties:
- const: pine64,rockpro64
- const: rockchip,rk3399
- - description: Pine64 Quartz64 Model A
+ - description: Pine64 Quartz64 Model A/B
items:
- - const: pine64,quartz64-a
+ - enum:
+ - pine64,quartz64-a
+ - pine64,quartz64-b
- const: rockchip,rk3566
- description: Radxa Rock
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread* [PATCH v2 1/7] dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel
The Quartz64 Model B is a compact single board computer from Pine64
based on the rk3566 SoC. It outputs on uart2 for the debug console.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 6 ++++--
1 file changed, 4 insertions(+), 2 deletions(-)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index eece92f83a2d..beb5b0ac1a2a 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -502,9 +502,11 @@ properties:
- const: pine64,rockpro64
- const: rockchip,rk3399
- - description: Pine64 Quartz64 Model A
+ - description: Pine64 Quartz64 Model A/B
items:
- - const: pine64,quartz64-a
+ - enum:
+ - pine64,quartz64-a
+ - pine64,quartz64-b
- const: rockchip,rk3566
- description: Radxa Rock
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [PATCH v2 1/7] dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B
2022-04-29 11:52 ` Peter Geis
(?)
@ 2022-05-01 8:13 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 62+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-01 8:13 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: devicetree, linux-arm-kernel, linux-kernel
On 29/04/2022 13:52, Peter Geis wrote:
> The Quartz64 Model B is a compact single board computer from Pine64
> based on the rk3566 SoC. It outputs on uart2 for the debug console.
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 1/7] dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B
@ 2022-05-01 8:13 ` Krzysztof Kozlowski
0 siblings, 0 replies; 62+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-01 8:13 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: devicetree, linux-arm-kernel, linux-kernel
On 29/04/2022 13:52, Peter Geis wrote:
> The Quartz64 Model B is a compact single board computer from Pine64
> based on the rk3566 SoC. It outputs on uart2 for the debug console.
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 1/7] dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B
@ 2022-05-01 8:13 ` Krzysztof Kozlowski
0 siblings, 0 replies; 62+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-01 8:13 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: devicetree, linux-arm-kernel, linux-kernel
On 29/04/2022 13:52, Peter Geis wrote:
> The Quartz64 Model B is a compact single board computer from Pine64
> based on the rk3566 SoC. It outputs on uart2 for the debug console.
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Best regards,
Krzysztof
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v2 2/7] dt-bindings: arm: rockchip: Add Pine64 SoQuartz SoM
2022-04-29 11:52 ` Peter Geis
(?)
@ 2022-04-29 11:52 ` Peter Geis
-1 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel,
Krzysztof Kozlowski
The SoQuartz system on module is designed to be pin compatible with the
RPi CM4 SoM. It is based on the rk3566 SoC and outputs on uart2 for
debug and console. The first carrier board supported is the CM4IO board
from RPi.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index beb5b0ac1a2a..b85a8e6c5e75 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -509,6 +509,13 @@ properties:
- pine64,quartz64-b
- const: rockchip,rk3566
+ - description: Pine64 SoQuartz SoM
+ items:
+ - enum:
+ - pine64,soquartz-cm4io
+ - const: pine64,soquartz
+ - const: rockchip,rk3566
+
- description: Radxa Rock
items:
- const: radxa,rock
--
2.25.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [PATCH v2 2/7] dt-bindings: arm: rockchip: Add Pine64 SoQuartz SoM
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel,
Krzysztof Kozlowski
The SoQuartz system on module is designed to be pin compatible with the
RPi CM4 SoM. It is based on the rk3566 SoC and outputs on uart2 for
debug and console. The first carrier board supported is the CM4IO board
from RPi.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index beb5b0ac1a2a..b85a8e6c5e75 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -509,6 +509,13 @@ properties:
- pine64,quartz64-b
- const: rockchip,rk3566
+ - description: Pine64 SoQuartz SoM
+ items:
+ - enum:
+ - pine64,soquartz-cm4io
+ - const: pine64,soquartz
+ - const: rockchip,rk3566
+
- description: Radxa Rock
items:
- const: radxa,rock
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread* [PATCH v2 2/7] dt-bindings: arm: rockchip: Add Pine64 SoQuartz SoM
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel,
Krzysztof Kozlowski
The SoQuartz system on module is designed to be pin compatible with the
RPi CM4 SoM. It is based on the rk3566 SoC and outputs on uart2 for
debug and console. The first carrier board supported is the CM4IO board
from RPi.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index beb5b0ac1a2a..b85a8e6c5e75 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -509,6 +509,13 @@ properties:
- pine64,quartz64-b
- const: rockchip,rk3566
+ - description: Pine64 SoQuartz SoM
+ items:
+ - enum:
+ - pine64,soquartz-cm4io
+ - const: pine64,soquartz
+ - const: rockchip,rk3566
+
- description: Radxa Rock
items:
- const: radxa,rock
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v2 3/7] dt-bindings: arm: rockchip: Add Firefly Station M2
2022-04-29 11:52 ` Peter Geis
(?)
@ 2022-04-29 11:52 ` Peter Geis
-1 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel,
Krzysztof Kozlowski
The Station M2 is a compact single board computer based on the rk3566
SoC. It outputs on uart2 for debug and console purposes.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index b85a8e6c5e75..288d044d48bc 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -133,6 +133,11 @@ properties:
- firefly,roc-rk3399-pc-plus
- const: rockchip,rk3399
+ - description: Firefly Station M2
+ items:
+ - const: firefly,rk3566-roc-pc
+ - const: rockchip,rk3566
+
- description: FriendlyElec NanoPi R2S
items:
- const: friendlyarm,nanopi-r2s
--
2.25.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [PATCH v2 3/7] dt-bindings: arm: rockchip: Add Firefly Station M2
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel,
Krzysztof Kozlowski
The Station M2 is a compact single board computer based on the rk3566
SoC. It outputs on uart2 for debug and console purposes.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index b85a8e6c5e75..288d044d48bc 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -133,6 +133,11 @@ properties:
- firefly,roc-rk3399-pc-plus
- const: rockchip,rk3399
+ - description: Firefly Station M2
+ items:
+ - const: firefly,rk3566-roc-pc
+ - const: rockchip,rk3566
+
- description: FriendlyElec NanoPi R2S
items:
- const: friendlyarm,nanopi-r2s
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread* [PATCH v2 3/7] dt-bindings: arm: rockchip: Add Firefly Station M2
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel,
Krzysztof Kozlowski
The Station M2 is a compact single board computer based on the rk3566
SoC. It outputs on uart2 for debug and console purposes.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
Acked-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
---
Documentation/devicetree/bindings/arm/rockchip.yaml | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/Documentation/devicetree/bindings/arm/rockchip.yaml b/Documentation/devicetree/bindings/arm/rockchip.yaml
index b85a8e6c5e75..288d044d48bc 100644
--- a/Documentation/devicetree/bindings/arm/rockchip.yaml
+++ b/Documentation/devicetree/bindings/arm/rockchip.yaml
@@ -133,6 +133,11 @@ properties:
- firefly,roc-rk3399-pc-plus
- const: rockchip,rk3399
+ - description: Firefly Station M2
+ items:
+ - const: firefly,rk3566-roc-pc
+ - const: rockchip,rk3566
+
- description: FriendlyElec NanoPi R2S
items:
- const: friendlyarm,nanopi-r2s
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v2 4/7] arm64: dts: rockchip: add rk356x sfc support
2022-04-29 11:52 ` Peter Geis
(?)
@ 2022-04-29 11:52 ` Peter Geis
-1 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel
Add the sfc node to the rk356x device tree. This enables spi flash
support for this soc.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index ca20d7b91fe5..61a6d9d4c8a0 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -750,6 +750,17 @@ sdmmc1: mmc@fe2c0000 {
status = "disabled";
};
+ sfc: spi@fe300000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xfe300000 0x0 0x4000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-0 = <&fspi_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
sdhci: mmc@fe310000 {
compatible = "rockchip,rk3568-dwcmshc";
reg = <0x0 0xfe310000 0x0 0x10000>;
--
2.25.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [PATCH v2 4/7] arm64: dts: rockchip: add rk356x sfc support
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel
Add the sfc node to the rk356x device tree. This enables spi flash
support for this soc.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index ca20d7b91fe5..61a6d9d4c8a0 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -750,6 +750,17 @@ sdmmc1: mmc@fe2c0000 {
status = "disabled";
};
+ sfc: spi@fe300000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xfe300000 0x0 0x4000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-0 = <&fspi_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
sdhci: mmc@fe310000 {
compatible = "rockchip,rk3568-dwcmshc";
reg = <0x0 0xfe310000 0x0 0x10000>;
--
2.25.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 62+ messages in thread* [PATCH v2 4/7] arm64: dts: rockchip: add rk356x sfc support
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel
Add the sfc node to the rk356x device tree. This enables spi flash
support for this soc.
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm64/boot/dts/rockchip/rk356x.dtsi | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/arch/arm64/boot/dts/rockchip/rk356x.dtsi b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
index ca20d7b91fe5..61a6d9d4c8a0 100644
--- a/arch/arm64/boot/dts/rockchip/rk356x.dtsi
+++ b/arch/arm64/boot/dts/rockchip/rk356x.dtsi
@@ -750,6 +750,17 @@ sdmmc1: mmc@fe2c0000 {
status = "disabled";
};
+ sfc: spi@fe300000 {
+ compatible = "rockchip,sfc";
+ reg = <0x0 0xfe300000 0x0 0x4000>;
+ interrupts = <GIC_SPI 101 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cru SCLK_SFC>, <&cru HCLK_SFC>;
+ clock-names = "clk_sfc", "hclk_sfc";
+ pinctrl-0 = <&fspi_pins>;
+ pinctrl-names = "default";
+ status = "disabled";
+ };
+
sdhci: mmc@fe310000 {
compatible = "rockchip,rk3568-dwcmshc";
reg = <0x0 0xfe310000 0x0 0x10000>;
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread
* [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
2022-04-29 11:52 ` Peter Geis
(?)
@ 2022-04-29 11:52 ` Peter Geis
-1 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel
Add a device tree for the Pine64 Quartz64 Model B single board computer.
This board ouputs debug on uart2 and supports the following components:
Gigabit Ethernet
USB2 x2 (one port otg capable)
USB3
PCIe/SATA M2
HDMI
DSI (RPi compatible pinout)
CSI (RPi compatible pinout)
A/B/G/N WiFi
Bluetooth
SDMMC
eMMC
SPI Flash
PI-40 compatible pin header
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
2 files changed, 616 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 4ae9f35434b8..252ee47b8a1d 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
new file mode 100644
index 000000000000..184ab7e1d178
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
@@ -0,0 +1,615 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "Pine64 RK3566 Quartz64-B Board";
+ compatible = "pine64,quartz64-b", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ mmc2 = &sdmmc1;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-user {
+ label = "user-led";
+ default-state = "on";
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led_enable_h>;
+ retain-state-suspended;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ status = "okay";
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <5000000>;
+ };
+
+ vcc5v0_in: vcc5v0-in-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_in";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_in>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb30_host";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb30_host_en_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb_otg";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+ clock_in_out = "input";
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_clkinout
+ &gmac1m1_rgmii_bus>;
+ snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f, also works well here */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x4f>;
+ rx_delay = <0x24>;
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-boot-on;
+ regulator-name = "vcc_3v3";
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ };
+ };
+ };
+};
+
+/* i2c2_m1 exposed on csi port, pulled up to vcc_3v3 */
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m1_xfer>;
+ status = "okay";
+};
+
+/* i2c3_m1 exposed on dsi port, pulled up to vcc_3v3 */
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m1_xfer>;
+ status = "okay";
+};
+
+/* i2c4_m0 is exposed on PI40, pulled up to vcc_3v3
+ * pin 27 - i2c4_sda_m0
+ * pin 28 - i2c4_scl_m0
+ */
+&i2c4 {
+ status = "okay";
+};
+
+/* i2c5_m0 is exposed on PI40
+ * pin 29 - i2c5_scl_m0
+ * pin 31 - i2c5_sda_m0
+ */
+&i2c5 {
+ status = "disabled";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ };
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ user_led_enable_h: user-led-enable-h {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcca1v8_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcca1v8_pmu>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_3v3>;
+ vccio7-supply = <&vcc_3v3>;
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcca1v8_pmu>;
+ status = "okay";
+};
+
+&sfc {
+ pinctrl-0 = <&fspi_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+ status = "okay";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ clocks = <&rk809 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcca1v8_pmu>;
+ };
+};
+
+/* uart2_m0 is exposed on PI40
+ * pin 8 - uart2_tx_m0
+ * pin 10 - uart2_rx_m0
+ */
+&uart2 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel
Add a device tree for the Pine64 Quartz64 Model B single board computer.
This board ouputs debug on uart2 and supports the following components:
Gigabit Ethernet
USB2 x2 (one port otg capable)
USB3
PCIe/SATA M2
HDMI
DSI (RPi compatible pinout)
CSI (RPi compatible pinout)
A/B/G/N WiFi
Bluetooth
SDMMC
eMMC
SPI Flash
PI-40 compatible pin header
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
2 files changed, 616 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 4ae9f35434b8..252ee47b8a1d 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
new file mode 100644
index 000000000000..184ab7e1d178
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
@@ -0,0 +1,615 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "Pine64 RK3566 Quartz64-B Board";
+ compatible = "pine64,quartz64-b", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ mmc2 = &sdmmc1;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-user {
+ label = "user-led";
+ default-state = "on";
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led_enable_h>;
+ retain-state-suspended;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ status = "okay";
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <5000000>;
+ };
+
+ vcc5v0_in: vcc5v0-in-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_in";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_in>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb30_host";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb30_host_en_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb_otg";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+ clock_in_out = "input";
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_clkinout
+ &gmac1m1_rgmii_bus>;
+ snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f, also works well here */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x4f>;
+ rx_delay = <0x24>;
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-boot-on;
+ regulator-name = "vcc_3v3";
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ };
+ };
+ };
+};
+
+/* i2c2_m1 exposed on csi port, pulled up to vcc_3v3 */
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m1_xfer>;
+ status = "okay";
+};
+
+/* i2c3_m1 exposed on dsi port, pulled up to vcc_3v3 */
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m1_xfer>;
+ status = "okay";
+};
+
+/* i2c4_m0 is exposed on PI40, pulled up to vcc_3v3
+ * pin 27 - i2c4_sda_m0
+ * pin 28 - i2c4_scl_m0
+ */
+&i2c4 {
+ status = "okay";
+};
+
+/* i2c5_m0 is exposed on PI40
+ * pin 29 - i2c5_scl_m0
+ * pin 31 - i2c5_sda_m0
+ */
+&i2c5 {
+ status = "disabled";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ };
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ user_led_enable_h: user-led-enable-h {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcca1v8_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcca1v8_pmu>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_3v3>;
+ vccio7-supply = <&vcc_3v3>;
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcca1v8_pmu>;
+ status = "okay";
+};
+
+&sfc {
+ pinctrl-0 = <&fspi_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+ status = "okay";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ clocks = <&rk809 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcca1v8_pmu>;
+ };
+};
+
+/* uart2_m0 is exposed on PI40
+ * pin 8 - uart2_tx_m0
+ * pin 10 - uart2_rx_m0
+ */
+&uart2 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
--
2.25.1
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^ permalink raw reply related [flat|nested] 62+ messages in thread* [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel
Add a device tree for the Pine64 Quartz64 Model B single board computer.
This board ouputs debug on uart2 and supports the following components:
Gigabit Ethernet
USB2 x2 (one port otg capable)
USB3
PCIe/SATA M2
HDMI
DSI (RPi compatible pinout)
CSI (RPi compatible pinout)
A/B/G/N WiFi
Bluetooth
SDMMC
eMMC
SPI Flash
PI-40 compatible pin header
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
2 files changed, 616 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 4ae9f35434b8..252ee47b8a1d 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
new file mode 100644
index 000000000000..184ab7e1d178
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
@@ -0,0 +1,615 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+/*
+ *
+ */
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "Pine64 RK3566 Quartz64-B Board";
+ compatible = "pine64,quartz64-b", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ mmc2 = &sdmmc1;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-user {
+ label = "user-led";
+ default-state = "on";
+ gpios = <&gpio0 RK_PA0 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led_enable_h>;
+ retain-state-suspended;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ status = "okay";
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+ post-power-on-delay-ms = <100>;
+ power-off-delay-us = <5000000>;
+ };
+
+ vcc5v0_in: vcc5v0-in-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_in";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_in>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb30_host";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb30_host_en_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb_otg";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+ clock_in_out = "input";
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m1_miim
+ &gmac1m1_tx_bus2
+ &gmac1m1_rx_bus2
+ &gmac1m1_rgmii_clk
+ &gmac1m1_clkinout
+ &gmac1m1_rgmii_bus>;
+ snps,reset-gpio = <&gpio3 RK_PC0 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f, also works well here */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x4f>;
+ rx_delay = <0x24>;
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-boot-on;
+ regulator-name = "vcc_3v3";
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ };
+ };
+ };
+};
+
+/* i2c2_m1 exposed on csi port, pulled up to vcc_3v3 */
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m1_xfer>;
+ status = "okay";
+};
+
+/* i2c3_m1 exposed on dsi port, pulled up to vcc_3v3 */
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m1_xfer>;
+ status = "okay";
+};
+
+/* i2c4_m0 is exposed on PI40, pulled up to vcc_3v3
+ * pin 27 - i2c4_sda_m0
+ * pin 28 - i2c4_scl_m0
+ */
+&i2c4 {
+ status = "okay";
+};
+
+/* i2c5_m0 is exposed on PI40
+ * pin 29 - i2c5_scl_m0
+ * pin 31 - i2c5_sda_m0
+ */
+&i2c5 {
+ status = "disabled";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x1>;
+ };
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ user_led_enable_h: user-led-enable-h {
+ rockchip,pins = <0 RK_PA0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcca1v8_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcca1v8_pmu>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_3v3>;
+ vccio7-supply = <&vcc_3v3>;
+};
+
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "okay";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcca1v8_pmu>;
+ status = "okay";
+};
+
+&sfc {
+ pinctrl-0 = <&fspi_pins>;
+ pinctrl-names = "default";
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "okay";
+
+ flash@0 {
+ compatible = "jedec,spi-nor";
+ reg = <0>;
+ spi-max-frequency = <24000000>;
+ spi-rx-bus-width = <4>;
+ spi-tx-bus-width = <1>;
+ };
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+ status = "okay";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm4345c5";
+ clocks = <&rk809 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio0 RK_PB4 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio0 RK_PB3 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcca1v8_pmu>;
+ };
+};
+
+/* uart2_m0 is exposed on PI40
+ * pin 8 - uart2_tx_m0
+ * pin 10 - uart2_rx_m0
+ */
+&uart2 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
2022-04-29 11:52 ` Peter Geis
(?)
@ 2022-04-30 0:16 ` kernel test robot
-1 siblings, 0 replies; 62+ messages in thread
From: kernel test robot @ 2022-04-30 0:16 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: llvm, kbuild-all, Peter Geis, devicetree, linux-arm-kernel, linux-kernel
Hi Peter,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
[cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204300850.X97CRcO6-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/d933bfeea016da20a99bce012bbf071f9d86e2bf
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
git checkout d933bfeea016da20a99bce012bbf071f9d86e2bf
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:601.1-16 Label or path usb_host0_xhci not found
>> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:605.1-16 Label or path usb_host1_xhci not found
FATAL ERROR: Syntax error parsing input tree
--
0-DAY CI Kernel Test Service
https://01.org/lkp
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-04-30 0:16 ` kernel test robot
0 siblings, 0 replies; 62+ messages in thread
From: kernel test robot @ 2022-04-30 0:16 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: llvm, kbuild-all, Peter Geis, devicetree, linux-arm-kernel, linux-kernel
Hi Peter,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
[cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204300850.X97CRcO6-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/d933bfeea016da20a99bce012bbf071f9d86e2bf
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
git checkout d933bfeea016da20a99bce012bbf071f9d86e2bf
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:601.1-16 Label or path usb_host0_xhci not found
>> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:605.1-16 Label or path usb_host1_xhci not found
FATAL ERROR: Syntax error parsing input tree
--
0-DAY CI Kernel Test Service
https://01.org/lkp
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-04-30 0:16 ` kernel test robot
0 siblings, 0 replies; 62+ messages in thread
From: kernel test robot @ 2022-04-30 0:16 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: llvm, kbuild-all, Peter Geis, devicetree, linux-arm-kernel, linux-kernel
Hi Peter,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
[cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204300850.X97CRcO6-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/d933bfeea016da20a99bce012bbf071f9d86e2bf
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
git checkout d933bfeea016da20a99bce012bbf071f9d86e2bf
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:601.1-16 Label or path usb_host0_xhci not found
>> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:605.1-16 Label or path usb_host1_xhci not found
FATAL ERROR: Syntax error parsing input tree
--
0-DAY CI Kernel Test Service
https://01.org/lkp
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
2022-04-30 0:16 ` kernel test robot
(?)
(?)
@ 2022-04-30 14:46 ` Peter Geis
-1 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-30 14:46 UTC (permalink / raw)
To: kernel test robot
Cc: open list:ARM/Rockchip SoC...,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, llvm,
kbuild-all, devicetree, arm-mail-list, Linux Kernel Mailing List
On Fri, Apr 29, 2022 at 8:17 PM kernel test robot <lkp@intel.com> wrote:
>
> Hi Peter,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on robh/for-next]
> [also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
> [cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
The three new device trees are dependent on my usb series which was
accepted through Heiko's tree.
I can drop the xhci dependency, but this will just happen again adding
it back in if it's done in this RC series.
>
> url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204300850.X97CRcO6-lkp@intel.com/config)
> compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # install arm64 cross compiling tool for clang build
> # apt-get install binutils-aarch64-linux-gnu
> # https://github.com/intel-lab-lkp/linux/commit/d933bfeea016da20a99bce012bbf071f9d86e2bf
> git remote add linux-review https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> git checkout d933bfeea016da20a99bce012bbf071f9d86e2bf
> # save the config file
> mkdir build_dir && cp config build_dir/.config
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All errors (new ones prefixed by >>):
>
> >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:601.1-16 Label or path usb_host0_xhci not found
> >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:605.1-16 Label or path usb_host1_xhci not found
> FATAL ERROR: Syntax error parsing input tree
>
> --
> 0-DAY CI Kernel Test Service
> https://01.org/lkp
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-04-30 14:46 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-30 14:46 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 2644 bytes --]
On Fri, Apr 29, 2022 at 8:17 PM kernel test robot <lkp@intel.com> wrote:
>
> Hi Peter,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on robh/for-next]
> [also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
> [cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
The three new device trees are dependent on my usb series which was
accepted through Heiko's tree.
I can drop the xhci dependency, but this will just happen again adding
it back in if it's done in this RC series.
>
> url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204300850.X97CRcO6-lkp(a)intel.com/config)
> compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # install arm64 cross compiling tool for clang build
> # apt-get install binutils-aarch64-linux-gnu
> # https://github.com/intel-lab-lkp/linux/commit/d933bfeea016da20a99bce012bbf071f9d86e2bf
> git remote add linux-review https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> git checkout d933bfeea016da20a99bce012bbf071f9d86e2bf
> # save the config file
> mkdir build_dir && cp config build_dir/.config
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All errors (new ones prefixed by >>):
>
> >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:601.1-16 Label or path usb_host0_xhci not found
> >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:605.1-16 Label or path usb_host1_xhci not found
> FATAL ERROR: Syntax error parsing input tree
>
> --
> 0-DAY CI Kernel Test Service
> https://01.org/lkp
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-04-30 14:46 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-30 14:46 UTC (permalink / raw)
To: kernel test robot
Cc: open list:ARM/Rockchip SoC...,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, llvm,
kbuild-all, devicetree, arm-mail-list, Linux Kernel Mailing List
On Fri, Apr 29, 2022 at 8:17 PM kernel test robot <lkp@intel.com> wrote:
>
> Hi Peter,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on robh/for-next]
> [also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
> [cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
The three new device trees are dependent on my usb series which was
accepted through Heiko's tree.
I can drop the xhci dependency, but this will just happen again adding
it back in if it's done in this RC series.
>
> url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204300850.X97CRcO6-lkp@intel.com/config)
> compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # install arm64 cross compiling tool for clang build
> # apt-get install binutils-aarch64-linux-gnu
> # https://github.com/intel-lab-lkp/linux/commit/d933bfeea016da20a99bce012bbf071f9d86e2bf
> git remote add linux-review https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> git checkout d933bfeea016da20a99bce012bbf071f9d86e2bf
> # save the config file
> mkdir build_dir && cp config build_dir/.config
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All errors (new ones prefixed by >>):
>
> >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:601.1-16 Label or path usb_host0_xhci not found
> >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:605.1-16 Label or path usb_host1_xhci not found
> FATAL ERROR: Syntax error parsing input tree
>
> --
> 0-DAY CI Kernel Test Service
> https://01.org/lkp
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-04-30 14:46 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-30 14:46 UTC (permalink / raw)
To: kernel test robot
Cc: open list:ARM/Rockchip SoC...,
Rob Herring, Krzysztof Kozlowski, Heiko Stuebner, llvm,
kbuild-all, devicetree, arm-mail-list, Linux Kernel Mailing List
On Fri, Apr 29, 2022 at 8:17 PM kernel test robot <lkp@intel.com> wrote:
>
> Hi Peter,
>
> I love your patch! Yet something to improve:
>
> [auto build test ERROR on robh/for-next]
> [also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
> [cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
> [If your patch is applied to the wrong git tree, kindly drop us a note.
> And when submitting patch, we suggest to use '--base' as documented in
> https://git-scm.com/docs/git-format-patch]
The three new device trees are dependent on my usb series which was
accepted through Heiko's tree.
I can drop the xhci dependency, but this will just happen again adding
it back in if it's done in this RC series.
>
> url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204300850.X97CRcO6-lkp@intel.com/config)
> compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
> reproduce (this is a W=1 build):
> wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> chmod +x ~/bin/make.cross
> # install arm64 cross compiling tool for clang build
> # apt-get install binutils-aarch64-linux-gnu
> # https://github.com/intel-lab-lkp/linux/commit/d933bfeea016da20a99bce012bbf071f9d86e2bf
> git remote add linux-review https://github.com/intel-lab-lkp/linux
> git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> git checkout d933bfeea016da20a99bce012bbf071f9d86e2bf
> # save the config file
> mkdir build_dir && cp config build_dir/.config
> COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
>
> If you fix the issue, kindly add following tag as appropriate
> Reported-by: kernel test robot <lkp@intel.com>
>
> All errors (new ones prefixed by >>):
>
> >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:601.1-16 Label or path usb_host0_xhci not found
> >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:605.1-16 Label or path usb_host1_xhci not found
> FATAL ERROR: Syntax error parsing input tree
>
> --
> 0-DAY CI Kernel Test Service
> https://01.org/lkp
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
2022-04-30 14:46 ` Peter Geis
(?)
(?)
@ 2022-04-30 16:57 ` Heiko Stübner
-1 siblings, 0 replies; 62+ messages in thread
From: Heiko Stübner @ 2022-04-30 16:57 UTC (permalink / raw)
To: kernel test robot, Peter Geis, Krzysztof Kozlowski
Cc: open list:ARM/Rockchip SoC...,
Rob Herring, llvm, kbuild-all, devicetree, arm-mail-list,
Linux Kernel Mailing List
Am Samstag, 30. April 2022, 16:46:31 CEST schrieb Peter Geis:
> On Fri, Apr 29, 2022 at 8:17 PM kernel test robot <lkp@intel.com> wrote:
> >
> > Hi Peter,
> >
> > I love your patch! Yet something to improve:
> >
> > [auto build test ERROR on robh/for-next]
> > [also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
> > [cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
> > [If your patch is applied to the wrong git tree, kindly drop us a note.
> > And when submitting patch, we suggest to use '--base' as documented in
> > https://git-scm.com/docs/git-format-patch]
>
> The three new device trees are dependent on my usb series which was
> accepted through Heiko's tree.
> I can drop the xhci dependency, but this will just happen again adding
> it back in if it's done in this RC series.
Of course dropping that part is not necessary :-)
I.e. the dependency is in my tree and this stuff will go on top.
I'm just not sure if I should give Krzysztof more time for patch1.
The binding of course looks great now already, I guess I'll let the
Quartz-B sit some days more.
Heiko
>
> >
> > url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> > base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> > config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204300850.X97CRcO6-lkp@intel.com/config)
> > compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
> > reproduce (this is a W=1 build):
> > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> > chmod +x ~/bin/make.cross
> > # install arm64 cross compiling tool for clang build
> > # apt-get install binutils-aarch64-linux-gnu
> > # https://github.com/intel-lab-lkp/linux/commit/d933bfeea016da20a99bce012bbf071f9d86e2bf
> > git remote add linux-review https://github.com/intel-lab-lkp/linux
> > git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> > git checkout d933bfeea016da20a99bce012bbf071f9d86e2bf
> > # save the config file
> > mkdir build_dir && cp config build_dir/.config
> > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
> >
> > If you fix the issue, kindly add following tag as appropriate
> > Reported-by: kernel test robot <lkp@intel.com>
> >
> > All errors (new ones prefixed by >>):
> >
> > >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:601.1-16 Label or path usb_host0_xhci not found
> > >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:605.1-16 Label or path usb_host1_xhci not found
> > FATAL ERROR: Syntax error parsing input tree
> >
> > --
> > 0-DAY CI Kernel Test Service
> > https://01.org/lkp
>
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-04-30 16:57 ` Heiko Stübner
0 siblings, 0 replies; 62+ messages in thread
From: Heiko Stübner @ 2022-04-30 16:57 UTC (permalink / raw)
To: kbuild-all
[-- Attachment #1: Type: text/plain, Size: 3116 bytes --]
Am Samstag, 30. April 2022, 16:46:31 CEST schrieb Peter Geis:
> On Fri, Apr 29, 2022 at 8:17 PM kernel test robot <lkp@intel.com> wrote:
> >
> > Hi Peter,
> >
> > I love your patch! Yet something to improve:
> >
> > [auto build test ERROR on robh/for-next]
> > [also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
> > [cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
> > [If your patch is applied to the wrong git tree, kindly drop us a note.
> > And when submitting patch, we suggest to use '--base' as documented in
> > https://git-scm.com/docs/git-format-patch]
>
> The three new device trees are dependent on my usb series which was
> accepted through Heiko's tree.
> I can drop the xhci dependency, but this will just happen again adding
> it back in if it's done in this RC series.
Of course dropping that part is not necessary :-)
I.e. the dependency is in my tree and this stuff will go on top.
I'm just not sure if I should give Krzysztof more time for patch1.
The binding of course looks great now already, I guess I'll let the
Quartz-B sit some days more.
Heiko
>
> >
> > url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> > base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> > config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204300850.X97CRcO6-lkp(a)intel.com/config)
> > compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
> > reproduce (this is a W=1 build):
> > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> > chmod +x ~/bin/make.cross
> > # install arm64 cross compiling tool for clang build
> > # apt-get install binutils-aarch64-linux-gnu
> > # https://github.com/intel-lab-lkp/linux/commit/d933bfeea016da20a99bce012bbf071f9d86e2bf
> > git remote add linux-review https://github.com/intel-lab-lkp/linux
> > git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> > git checkout d933bfeea016da20a99bce012bbf071f9d86e2bf
> > # save the config file
> > mkdir build_dir && cp config build_dir/.config
> > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
> >
> > If you fix the issue, kindly add following tag as appropriate
> > Reported-by: kernel test robot <lkp@intel.com>
> >
> > All errors (new ones prefixed by >>):
> >
> > >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:601.1-16 Label or path usb_host0_xhci not found
> > >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:605.1-16 Label or path usb_host1_xhci not found
> > FATAL ERROR: Syntax error parsing input tree
> >
> > --
> > 0-DAY CI Kernel Test Service
> > https://01.org/lkp
>
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-04-30 16:57 ` Heiko Stübner
0 siblings, 0 replies; 62+ messages in thread
From: Heiko Stübner @ 2022-04-30 16:57 UTC (permalink / raw)
To: kernel test robot, Peter Geis, Krzysztof Kozlowski
Cc: open list:ARM/Rockchip SoC...,
Rob Herring, llvm, kbuild-all, devicetree, arm-mail-list,
Linux Kernel Mailing List
Am Samstag, 30. April 2022, 16:46:31 CEST schrieb Peter Geis:
> On Fri, Apr 29, 2022 at 8:17 PM kernel test robot <lkp@intel.com> wrote:
> >
> > Hi Peter,
> >
> > I love your patch! Yet something to improve:
> >
> > [auto build test ERROR on robh/for-next]
> > [also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
> > [cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
> > [If your patch is applied to the wrong git tree, kindly drop us a note.
> > And when submitting patch, we suggest to use '--base' as documented in
> > https://git-scm.com/docs/git-format-patch]
>
> The three new device trees are dependent on my usb series which was
> accepted through Heiko's tree.
> I can drop the xhci dependency, but this will just happen again adding
> it back in if it's done in this RC series.
Of course dropping that part is not necessary :-)
I.e. the dependency is in my tree and this stuff will go on top.
I'm just not sure if I should give Krzysztof more time for patch1.
The binding of course looks great now already, I guess I'll let the
Quartz-B sit some days more.
Heiko
>
> >
> > url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> > base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> > config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204300850.X97CRcO6-lkp@intel.com/config)
> > compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
> > reproduce (this is a W=1 build):
> > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> > chmod +x ~/bin/make.cross
> > # install arm64 cross compiling tool for clang build
> > # apt-get install binutils-aarch64-linux-gnu
> > # https://github.com/intel-lab-lkp/linux/commit/d933bfeea016da20a99bce012bbf071f9d86e2bf
> > git remote add linux-review https://github.com/intel-lab-lkp/linux
> > git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> > git checkout d933bfeea016da20a99bce012bbf071f9d86e2bf
> > # save the config file
> > mkdir build_dir && cp config build_dir/.config
> > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
> >
> > If you fix the issue, kindly add following tag as appropriate
> > Reported-by: kernel test robot <lkp@intel.com>
> >
> > All errors (new ones prefixed by >>):
> >
> > >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:601.1-16 Label or path usb_host0_xhci not found
> > >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:605.1-16 Label or path usb_host1_xhci not found
> > FATAL ERROR: Syntax error parsing input tree
> >
> > --
> > 0-DAY CI Kernel Test Service
> > https://01.org/lkp
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-04-30 16:57 ` Heiko Stübner
0 siblings, 0 replies; 62+ messages in thread
From: Heiko Stübner @ 2022-04-30 16:57 UTC (permalink / raw)
To: kernel test robot, Peter Geis, Krzysztof Kozlowski
Cc: open list:ARM/Rockchip SoC...,
Rob Herring, llvm, kbuild-all, devicetree, arm-mail-list,
Linux Kernel Mailing List
Am Samstag, 30. April 2022, 16:46:31 CEST schrieb Peter Geis:
> On Fri, Apr 29, 2022 at 8:17 PM kernel test robot <lkp@intel.com> wrote:
> >
> > Hi Peter,
> >
> > I love your patch! Yet something to improve:
> >
> > [auto build test ERROR on robh/for-next]
> > [also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
> > [cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
> > [If your patch is applied to the wrong git tree, kindly drop us a note.
> > And when submitting patch, we suggest to use '--base' as documented in
> > https://git-scm.com/docs/git-format-patch]
>
> The three new device trees are dependent on my usb series which was
> accepted through Heiko's tree.
> I can drop the xhci dependency, but this will just happen again adding
> it back in if it's done in this RC series.
Of course dropping that part is not necessary :-)
I.e. the dependency is in my tree and this stuff will go on top.
I'm just not sure if I should give Krzysztof more time for patch1.
The binding of course looks great now already, I guess I'll let the
Quartz-B sit some days more.
Heiko
>
> >
> > url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> > base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
> > config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204300850.X97CRcO6-lkp@intel.com/config)
> > compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
> > reproduce (this is a W=1 build):
> > wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
> > chmod +x ~/bin/make.cross
> > # install arm64 cross compiling tool for clang build
> > # apt-get install binutils-aarch64-linux-gnu
> > # https://github.com/intel-lab-lkp/linux/commit/d933bfeea016da20a99bce012bbf071f9d86e2bf
> > git remote add linux-review https://github.com/intel-lab-lkp/linux
> > git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
> > git checkout d933bfeea016da20a99bce012bbf071f9d86e2bf
> > # save the config file
> > mkdir build_dir && cp config build_dir/.config
> > COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
> >
> > If you fix the issue, kindly add following tag as appropriate
> > Reported-by: kernel test robot <lkp@intel.com>
> >
> > All errors (new ones prefixed by >>):
> >
> > >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:601.1-16 Label or path usb_host0_xhci not found
> > >> Error: arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts:605.1-16 Label or path usb_host1_xhci not found
> > FATAL ERROR: Syntax error parsing input tree
> >
> > --
> > 0-DAY CI Kernel Test Service
> > https://01.org/lkp
>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
2022-04-29 11:52 ` Peter Geis
(?)
@ 2022-05-01 7:06 ` Johan Jonker
-1 siblings, 0 replies; 62+ messages in thread
From: Johan Jonker @ 2022-05-01 7:06 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: devicetree, linux-arm-kernel, linux-kernel
On 4/29/22 13:52, Peter Geis wrote:
> Add a device tree for the Pine64 Quartz64 Model B single board computer.
> This board ouputs debug on uart2 and supports the following components:
> Gigabit Ethernet
> USB2 x2 (one port otg capable)
> USB3
> PCIe/SATA M2
> HDMI
> DSI (RPi compatible pinout)
> CSI (RPi compatible pinout)
> A/B/G/N WiFi
> Bluetooth
> SDMMC
> eMMC
> SPI Flash
> PI-40 compatible pin header
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
> arch/arm64/boot/dts/rockchip/Makefile | 1 +
> .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
> 2 files changed, 616 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
>
> diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> index 4ae9f35434b8..252ee47b8a1d 100644
> --- a/arch/arm64/boot/dts/rockchip/Makefile
> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
> diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> new file mode 100644
> index 000000000000..184ab7e1d178
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> @@ -0,0 +1,615 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pinctrl/rockchip.h>
> +#include "rk3566.dtsi"
> +
> +/ {
> + model = "Pine64 RK3566 Quartz64-B Board";
> + compatible = "pine64,quartz64-b", "rockchip,rk3566";
> +
[..]
> +
> +&mdio1 {
> + rgmii_phy1: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0x1>;
Hi,
The reg value doesn't match the node name.
Other 2 boards use "reg = <0>" with label "rgmii_phy1".
Could you check?
Johan
> + };
> +};
> +
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-05-01 7:06 ` Johan Jonker
0 siblings, 0 replies; 62+ messages in thread
From: Johan Jonker @ 2022-05-01 7:06 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: devicetree, linux-arm-kernel, linux-kernel
On 4/29/22 13:52, Peter Geis wrote:
> Add a device tree for the Pine64 Quartz64 Model B single board computer.
> This board ouputs debug on uart2 and supports the following components:
> Gigabit Ethernet
> USB2 x2 (one port otg capable)
> USB3
> PCIe/SATA M2
> HDMI
> DSI (RPi compatible pinout)
> CSI (RPi compatible pinout)
> A/B/G/N WiFi
> Bluetooth
> SDMMC
> eMMC
> SPI Flash
> PI-40 compatible pin header
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
> arch/arm64/boot/dts/rockchip/Makefile | 1 +
> .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
> 2 files changed, 616 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
>
> diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> index 4ae9f35434b8..252ee47b8a1d 100644
> --- a/arch/arm64/boot/dts/rockchip/Makefile
> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
> diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> new file mode 100644
> index 000000000000..184ab7e1d178
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> @@ -0,0 +1,615 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pinctrl/rockchip.h>
> +#include "rk3566.dtsi"
> +
> +/ {
> + model = "Pine64 RK3566 Quartz64-B Board";
> + compatible = "pine64,quartz64-b", "rockchip,rk3566";
> +
[..]
> +
> +&mdio1 {
> + rgmii_phy1: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0x1>;
Hi,
The reg value doesn't match the node name.
Other 2 boards use "reg = <0>" with label "rgmii_phy1".
Could you check?
Johan
> + };
> +};
> +
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-05-01 7:06 ` Johan Jonker
0 siblings, 0 replies; 62+ messages in thread
From: Johan Jonker @ 2022-05-01 7:06 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: devicetree, linux-arm-kernel, linux-kernel
On 4/29/22 13:52, Peter Geis wrote:
> Add a device tree for the Pine64 Quartz64 Model B single board computer.
> This board ouputs debug on uart2 and supports the following components:
> Gigabit Ethernet
> USB2 x2 (one port otg capable)
> USB3
> PCIe/SATA M2
> HDMI
> DSI (RPi compatible pinout)
> CSI (RPi compatible pinout)
> A/B/G/N WiFi
> Bluetooth
> SDMMC
> eMMC
> SPI Flash
> PI-40 compatible pin header
>
> Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> ---
> arch/arm64/boot/dts/rockchip/Makefile | 1 +
> .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
> 2 files changed, 616 insertions(+)
> create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
>
> diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> index 4ae9f35434b8..252ee47b8a1d 100644
> --- a/arch/arm64/boot/dts/rockchip/Makefile
> +++ b/arch/arm64/boot/dts/rockchip/Makefile
> @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
> +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
> dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
> diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> new file mode 100644
> index 000000000000..184ab7e1d178
> --- /dev/null
> +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> @@ -0,0 +1,615 @@
> +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> +/*
> + *
> + */
> +
> +/dts-v1/;
> +
> +#include <dt-bindings/gpio/gpio.h>
> +#include <dt-bindings/pinctrl/rockchip.h>
> +#include "rk3566.dtsi"
> +
> +/ {
> + model = "Pine64 RK3566 Quartz64-B Board";
> + compatible = "pine64,quartz64-b", "rockchip,rk3566";
> +
[..]
> +
> +&mdio1 {
> + rgmii_phy1: ethernet-phy@0 {
> + compatible = "ethernet-phy-ieee802.3-c22";
> + reg = <0x1>;
Hi,
The reg value doesn't match the node name.
Other 2 boards use "reg = <0>" with label "rgmii_phy1".
Could you check?
Johan
> + };
> +};
> +
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
2022-05-01 7:06 ` Johan Jonker
(?)
@ 2022-05-01 11:31 ` Heiko Stübner
-1 siblings, 0 replies; 62+ messages in thread
From: Heiko Stübner @ 2022-05-01 11:31 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Johan Jonker
Cc: devicetree, linux-arm-kernel, linux-kernel
Am Sonntag, 1. Mai 2022, 09:06:33 CEST schrieb Johan Jonker:
>
> On 4/29/22 13:52, Peter Geis wrote:
> > Add a device tree for the Pine64 Quartz64 Model B single board computer.
> > This board ouputs debug on uart2 and supports the following components:
> > Gigabit Ethernet
> > USB2 x2 (one port otg capable)
> > USB3
> > PCIe/SATA M2
> > HDMI
> > DSI (RPi compatible pinout)
> > CSI (RPi compatible pinout)
> > A/B/G/N WiFi
> > Bluetooth
> > SDMMC
> > eMMC
> > SPI Flash
> > PI-40 compatible pin header
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> > arch/arm64/boot/dts/rockchip/Makefile | 1 +
> > .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
> > 2 files changed, 616 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> > index 4ae9f35434b8..252ee47b8a1d 100644
> > --- a/arch/arm64/boot/dts/rockchip/Makefile
> > +++ b/arch/arm64/boot/dts/rockchip/Makefile
> > @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
> > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > new file mode 100644
> > index 000000000000..184ab7e1d178
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > @@ -0,0 +1,615 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + *
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/pinctrl/rockchip.h>
> > +#include "rk3566.dtsi"
> > +
> > +/ {
> > + model = "Pine64 RK3566 Quartz64-B Board";
> > + compatible = "pine64,quartz64-b", "rockchip,rk3566";
> > +
>
> [..]
>
> > +
> > +&mdio1 {
>
> > + rgmii_phy1: ethernet-phy@0 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <0x1>;
>
> Hi,
>
> The reg value doesn't match the node name.
> Other 2 boards use "reg = <0>" with label "rgmii_phy1".
> Could you check?
I do have an older Quartz-B in my boardfarm and in that older
devicetree the phy-reg also is "0" instead of the "1" used here.
Is that a hardware-change?
Thanks
Heiko
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-05-01 11:31 ` Heiko Stübner
0 siblings, 0 replies; 62+ messages in thread
From: Heiko Stübner @ 2022-05-01 11:31 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Johan Jonker
Cc: devicetree, linux-arm-kernel, linux-kernel
Am Sonntag, 1. Mai 2022, 09:06:33 CEST schrieb Johan Jonker:
>
> On 4/29/22 13:52, Peter Geis wrote:
> > Add a device tree for the Pine64 Quartz64 Model B single board computer.
> > This board ouputs debug on uart2 and supports the following components:
> > Gigabit Ethernet
> > USB2 x2 (one port otg capable)
> > USB3
> > PCIe/SATA M2
> > HDMI
> > DSI (RPi compatible pinout)
> > CSI (RPi compatible pinout)
> > A/B/G/N WiFi
> > Bluetooth
> > SDMMC
> > eMMC
> > SPI Flash
> > PI-40 compatible pin header
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> > arch/arm64/boot/dts/rockchip/Makefile | 1 +
> > .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
> > 2 files changed, 616 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> > index 4ae9f35434b8..252ee47b8a1d 100644
> > --- a/arch/arm64/boot/dts/rockchip/Makefile
> > +++ b/arch/arm64/boot/dts/rockchip/Makefile
> > @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
> > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > new file mode 100644
> > index 000000000000..184ab7e1d178
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > @@ -0,0 +1,615 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + *
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/pinctrl/rockchip.h>
> > +#include "rk3566.dtsi"
> > +
> > +/ {
> > + model = "Pine64 RK3566 Quartz64-B Board";
> > + compatible = "pine64,quartz64-b", "rockchip,rk3566";
> > +
>
> [..]
>
> > +
> > +&mdio1 {
>
> > + rgmii_phy1: ethernet-phy@0 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <0x1>;
>
> Hi,
>
> The reg value doesn't match the node name.
> Other 2 boards use "reg = <0>" with label "rgmii_phy1".
> Could you check?
I do have an older Quartz-B in my boardfarm and in that older
devicetree the phy-reg also is "0" instead of the "1" used here.
Is that a hardware-change?
Thanks
Heiko
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-05-01 11:31 ` Heiko Stübner
0 siblings, 0 replies; 62+ messages in thread
From: Heiko Stübner @ 2022-05-01 11:31 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Johan Jonker
Cc: devicetree, linux-arm-kernel, linux-kernel
Am Sonntag, 1. Mai 2022, 09:06:33 CEST schrieb Johan Jonker:
>
> On 4/29/22 13:52, Peter Geis wrote:
> > Add a device tree for the Pine64 Quartz64 Model B single board computer.
> > This board ouputs debug on uart2 and supports the following components:
> > Gigabit Ethernet
> > USB2 x2 (one port otg capable)
> > USB3
> > PCIe/SATA M2
> > HDMI
> > DSI (RPi compatible pinout)
> > CSI (RPi compatible pinout)
> > A/B/G/N WiFi
> > Bluetooth
> > SDMMC
> > eMMC
> > SPI Flash
> > PI-40 compatible pin header
> >
> > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > ---
> > arch/arm64/boot/dts/rockchip/Makefile | 1 +
> > .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
> > 2 files changed, 616 insertions(+)
> > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> >
> > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> > index 4ae9f35434b8..252ee47b8a1d 100644
> > --- a/arch/arm64/boot/dts/rockchip/Makefile
> > +++ b/arch/arm64/boot/dts/rockchip/Makefile
> > @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
> > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
> > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
> > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > new file mode 100644
> > index 000000000000..184ab7e1d178
> > --- /dev/null
> > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > @@ -0,0 +1,615 @@
> > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > +/*
> > + *
> > + */
> > +
> > +/dts-v1/;
> > +
> > +#include <dt-bindings/gpio/gpio.h>
> > +#include <dt-bindings/pinctrl/rockchip.h>
> > +#include "rk3566.dtsi"
> > +
> > +/ {
> > + model = "Pine64 RK3566 Quartz64-B Board";
> > + compatible = "pine64,quartz64-b", "rockchip,rk3566";
> > +
>
> [..]
>
> > +
> > +&mdio1 {
>
> > + rgmii_phy1: ethernet-phy@0 {
> > + compatible = "ethernet-phy-ieee802.3-c22";
> > + reg = <0x1>;
>
> Hi,
>
> The reg value doesn't match the node name.
> Other 2 boards use "reg = <0>" with label "rgmii_phy1".
> Could you check?
I do have an older Quartz-B in my boardfarm and in that older
devicetree the phy-reg also is "0" instead of the "1" used here.
Is that a hardware-change?
Thanks
Heiko
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
2022-05-01 11:31 ` Heiko Stübner
(?)
@ 2022-05-01 11:48 ` Peter Geis
-1 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-05-01 11:48 UTC (permalink / raw)
To: Heiko Stübner
Cc: open list:ARM/Rockchip SoC...,
Rob Herring, Krzysztof Kozlowski, Johan Jonker, devicetree,
arm-mail-list, Linux Kernel Mailing List
On Sun, May 1, 2022 at 7:31 AM Heiko Stübner <heiko@sntech.de> wrote:
>
> Am Sonntag, 1. Mai 2022, 09:06:33 CEST schrieb Johan Jonker:
> >
> > On 4/29/22 13:52, Peter Geis wrote:
> > > Add a device tree for the Pine64 Quartz64 Model B single board computer.
> > > This board ouputs debug on uart2 and supports the following components:
> > > Gigabit Ethernet
> > > USB2 x2 (one port otg capable)
> > > USB3
> > > PCIe/SATA M2
> > > HDMI
> > > DSI (RPi compatible pinout)
> > > CSI (RPi compatible pinout)
> > > A/B/G/N WiFi
> > > Bluetooth
> > > SDMMC
> > > eMMC
> > > SPI Flash
> > > PI-40 compatible pin header
> > >
> > > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > > ---
> > > arch/arm64/boot/dts/rockchip/Makefile | 1 +
> > > .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
> > > 2 files changed, 616 insertions(+)
> > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > >
> > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> > > index 4ae9f35434b8..252ee47b8a1d 100644
> > > --- a/arch/arm64/boot/dts/rockchip/Makefile
> > > +++ b/arch/arm64/boot/dts/rockchip/Makefile
> > > @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
> > > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > new file mode 100644
> > > index 000000000000..184ab7e1d178
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > @@ -0,0 +1,615 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > +/*
> > > + *
> > > + */
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +#include <dt-bindings/pinctrl/rockchip.h>
> > > +#include "rk3566.dtsi"
> > > +
> > > +/ {
> > > + model = "Pine64 RK3566 Quartz64-B Board";
> > > + compatible = "pine64,quartz64-b", "rockchip,rk3566";
> > > +
> >
> > [..]
> >
> > > +
> > > +&mdio1 {
> >
> > > + rgmii_phy1: ethernet-phy@0 {
> > > + compatible = "ethernet-phy-ieee802.3-c22";
> > > + reg = <0x1>;
> >
> > Hi,
> >
> > The reg value doesn't match the node name.
> > Other 2 boards use "reg = <0>" with label "rgmii_phy1".
> > Could you check?
>
> I do have an older Quartz-B in my boardfarm and in that older
> devicetree the phy-reg also is "0" instead of the "1" used here.
>
> Is that a hardware-change?
The ethernet maintainers previously brought up that 0x0 is the
broadcast address for the mdio-bus. They requested we put the actual
bus id of the phy even on single phy busses. This is the first one
I've confirmed the bus address on.
Though I realized ethernet-phy@0 should be ethernet-phy@1 since you
mentioned this. Strange dtbs-check doesn't catch this, would you fix
it in line Heiko or do you want another revision?
>
> Thanks
> Heiko
>
>
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-05-01 11:48 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-05-01 11:48 UTC (permalink / raw)
To: Heiko Stübner
Cc: open list:ARM/Rockchip SoC...,
Rob Herring, Krzysztof Kozlowski, Johan Jonker, devicetree,
arm-mail-list, Linux Kernel Mailing List
On Sun, May 1, 2022 at 7:31 AM Heiko Stübner <heiko@sntech.de> wrote:
>
> Am Sonntag, 1. Mai 2022, 09:06:33 CEST schrieb Johan Jonker:
> >
> > On 4/29/22 13:52, Peter Geis wrote:
> > > Add a device tree for the Pine64 Quartz64 Model B single board computer.
> > > This board ouputs debug on uart2 and supports the following components:
> > > Gigabit Ethernet
> > > USB2 x2 (one port otg capable)
> > > USB3
> > > PCIe/SATA M2
> > > HDMI
> > > DSI (RPi compatible pinout)
> > > CSI (RPi compatible pinout)
> > > A/B/G/N WiFi
> > > Bluetooth
> > > SDMMC
> > > eMMC
> > > SPI Flash
> > > PI-40 compatible pin header
> > >
> > > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > > ---
> > > arch/arm64/boot/dts/rockchip/Makefile | 1 +
> > > .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
> > > 2 files changed, 616 insertions(+)
> > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > >
> > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> > > index 4ae9f35434b8..252ee47b8a1d 100644
> > > --- a/arch/arm64/boot/dts/rockchip/Makefile
> > > +++ b/arch/arm64/boot/dts/rockchip/Makefile
> > > @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
> > > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > new file mode 100644
> > > index 000000000000..184ab7e1d178
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > @@ -0,0 +1,615 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > +/*
> > > + *
> > > + */
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +#include <dt-bindings/pinctrl/rockchip.h>
> > > +#include "rk3566.dtsi"
> > > +
> > > +/ {
> > > + model = "Pine64 RK3566 Quartz64-B Board";
> > > + compatible = "pine64,quartz64-b", "rockchip,rk3566";
> > > +
> >
> > [..]
> >
> > > +
> > > +&mdio1 {
> >
> > > + rgmii_phy1: ethernet-phy@0 {
> > > + compatible = "ethernet-phy-ieee802.3-c22";
> > > + reg = <0x1>;
> >
> > Hi,
> >
> > The reg value doesn't match the node name.
> > Other 2 boards use "reg = <0>" with label "rgmii_phy1".
> > Could you check?
>
> I do have an older Quartz-B in my boardfarm and in that older
> devicetree the phy-reg also is "0" instead of the "1" used here.
>
> Is that a hardware-change?
The ethernet maintainers previously brought up that 0x0 is the
broadcast address for the mdio-bus. They requested we put the actual
bus id of the phy even on single phy busses. This is the first one
I've confirmed the bus address on.
Though I realized ethernet-phy@0 should be ethernet-phy@1 since you
mentioned this. Strange dtbs-check doesn't catch this, would you fix
it in line Heiko or do you want another revision?
>
> Thanks
> Heiko
>
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-05-01 11:48 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-05-01 11:48 UTC (permalink / raw)
To: Heiko Stübner
Cc: open list:ARM/Rockchip SoC...,
Rob Herring, Krzysztof Kozlowski, Johan Jonker, devicetree,
arm-mail-list, Linux Kernel Mailing List
On Sun, May 1, 2022 at 7:31 AM Heiko Stübner <heiko@sntech.de> wrote:
>
> Am Sonntag, 1. Mai 2022, 09:06:33 CEST schrieb Johan Jonker:
> >
> > On 4/29/22 13:52, Peter Geis wrote:
> > > Add a device tree for the Pine64 Quartz64 Model B single board computer.
> > > This board ouputs debug on uart2 and supports the following components:
> > > Gigabit Ethernet
> > > USB2 x2 (one port otg capable)
> > > USB3
> > > PCIe/SATA M2
> > > HDMI
> > > DSI (RPi compatible pinout)
> > > CSI (RPi compatible pinout)
> > > A/B/G/N WiFi
> > > Bluetooth
> > > SDMMC
> > > eMMC
> > > SPI Flash
> > > PI-40 compatible pin header
> > >
> > > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > > ---
> > > arch/arm64/boot/dts/rockchip/Makefile | 1 +
> > > .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
> > > 2 files changed, 616 insertions(+)
> > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > >
> > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> > > index 4ae9f35434b8..252ee47b8a1d 100644
> > > --- a/arch/arm64/boot/dts/rockchip/Makefile
> > > +++ b/arch/arm64/boot/dts/rockchip/Makefile
> > > @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
> > > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
> > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
> > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > new file mode 100644
> > > index 000000000000..184ab7e1d178
> > > --- /dev/null
> > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > @@ -0,0 +1,615 @@
> > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > +/*
> > > + *
> > > + */
> > > +
> > > +/dts-v1/;
> > > +
> > > +#include <dt-bindings/gpio/gpio.h>
> > > +#include <dt-bindings/pinctrl/rockchip.h>
> > > +#include "rk3566.dtsi"
> > > +
> > > +/ {
> > > + model = "Pine64 RK3566 Quartz64-B Board";
> > > + compatible = "pine64,quartz64-b", "rockchip,rk3566";
> > > +
> >
> > [..]
> >
> > > +
> > > +&mdio1 {
> >
> > > + rgmii_phy1: ethernet-phy@0 {
> > > + compatible = "ethernet-phy-ieee802.3-c22";
> > > + reg = <0x1>;
> >
> > Hi,
> >
> > The reg value doesn't match the node name.
> > Other 2 boards use "reg = <0>" with label "rgmii_phy1".
> > Could you check?
>
> I do have an older Quartz-B in my boardfarm and in that older
> devicetree the phy-reg also is "0" instead of the "1" used here.
>
> Is that a hardware-change?
The ethernet maintainers previously brought up that 0x0 is the
broadcast address for the mdio-bus. They requested we put the actual
bus id of the phy even on single phy busses. This is the first one
I've confirmed the bus address on.
Though I realized ethernet-phy@0 should be ethernet-phy@1 since you
mentioned this. Strange dtbs-check doesn't catch this, would you fix
it in line Heiko or do you want another revision?
>
> Thanks
> Heiko
>
>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
2022-05-01 11:48 ` Peter Geis
(?)
@ 2022-05-01 12:04 ` Heiko Stübner
-1 siblings, 0 replies; 62+ messages in thread
From: Heiko Stübner @ 2022-05-01 12:04 UTC (permalink / raw)
To: Peter Geis
Cc: open list:ARM/Rockchip SoC...,
Rob Herring, Krzysztof Kozlowski, Johan Jonker, devicetree,
arm-mail-list, Linux Kernel Mailing List
Am Sonntag, 1. Mai 2022, 13:48:02 CEST schrieb Peter Geis:
> On Sun, May 1, 2022 at 7:31 AM Heiko Stübner <heiko@sntech.de> wrote:
> >
> > Am Sonntag, 1. Mai 2022, 09:06:33 CEST schrieb Johan Jonker:
> > >
> > > On 4/29/22 13:52, Peter Geis wrote:
> > > > Add a device tree for the Pine64 Quartz64 Model B single board computer.
> > > > This board ouputs debug on uart2 and supports the following components:
> > > > Gigabit Ethernet
> > > > USB2 x2 (one port otg capable)
> > > > USB3
> > > > PCIe/SATA M2
> > > > HDMI
> > > > DSI (RPi compatible pinout)
> > > > CSI (RPi compatible pinout)
> > > > A/B/G/N WiFi
> > > > Bluetooth
> > > > SDMMC
> > > > eMMC
> > > > SPI Flash
> > > > PI-40 compatible pin header
> > > >
> > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > > > ---
> > > > arch/arm64/boot/dts/rockchip/Makefile | 1 +
> > > > .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
> > > > 2 files changed, 616 insertions(+)
> > > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > >
> > > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> > > > index 4ae9f35434b8..252ee47b8a1d 100644
> > > > --- a/arch/arm64/boot/dts/rockchip/Makefile
> > > > +++ b/arch/arm64/boot/dts/rockchip/Makefile
> > > > @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
> > > > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
> > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > > new file mode 100644
> > > > index 000000000000..184ab7e1d178
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > > @@ -0,0 +1,615 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > > +/*
> > > > + *
> > > > + */
> > > > +
> > > > +/dts-v1/;
> > > > +
> > > > +#include <dt-bindings/gpio/gpio.h>
> > > > +#include <dt-bindings/pinctrl/rockchip.h>
> > > > +#include "rk3566.dtsi"
> > > > +
> > > > +/ {
> > > > + model = "Pine64 RK3566 Quartz64-B Board";
> > > > + compatible = "pine64,quartz64-b", "rockchip,rk3566";
> > > > +
> > >
> > > [..]
> > >
> > > > +
> > > > +&mdio1 {
> > >
> > > > + rgmii_phy1: ethernet-phy@0 {
> > > > + compatible = "ethernet-phy-ieee802.3-c22";
> > > > + reg = <0x1>;
> > >
> > > Hi,
> > >
> > > The reg value doesn't match the node name.
> > > Other 2 boards use "reg = <0>" with label "rgmii_phy1".
> > > Could you check?
> >
> > I do have an older Quartz-B in my boardfarm and in that older
> > devicetree the phy-reg also is "0" instead of the "1" used here.
> >
> > Is that a hardware-change?
>
> The ethernet maintainers previously brought up that 0x0 is the
> broadcast address for the mdio-bus. They requested we put the actual
> bus id of the phy even on single phy busses. This is the first one
> I've confirmed the bus address on.
>
> Though I realized ethernet-phy@0 should be ethernet-phy@1 since you
> mentioned this. Strange dtbs-check doesn't catch this, would you fix
> it in line Heiko
no that's ok, I can fix that up. Just wanted to clarify what the intention
was first :-)
> or do you want another revision?
>
> >
> > Thanks
> > Heiko
> >
> >
>
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-05-01 12:04 ` Heiko Stübner
0 siblings, 0 replies; 62+ messages in thread
From: Heiko Stübner @ 2022-05-01 12:04 UTC (permalink / raw)
To: Peter Geis
Cc: open list:ARM/Rockchip SoC...,
Rob Herring, Krzysztof Kozlowski, Johan Jonker, devicetree,
arm-mail-list, Linux Kernel Mailing List
Am Sonntag, 1. Mai 2022, 13:48:02 CEST schrieb Peter Geis:
> On Sun, May 1, 2022 at 7:31 AM Heiko Stübner <heiko@sntech.de> wrote:
> >
> > Am Sonntag, 1. Mai 2022, 09:06:33 CEST schrieb Johan Jonker:
> > >
> > > On 4/29/22 13:52, Peter Geis wrote:
> > > > Add a device tree for the Pine64 Quartz64 Model B single board computer.
> > > > This board ouputs debug on uart2 and supports the following components:
> > > > Gigabit Ethernet
> > > > USB2 x2 (one port otg capable)
> > > > USB3
> > > > PCIe/SATA M2
> > > > HDMI
> > > > DSI (RPi compatible pinout)
> > > > CSI (RPi compatible pinout)
> > > > A/B/G/N WiFi
> > > > Bluetooth
> > > > SDMMC
> > > > eMMC
> > > > SPI Flash
> > > > PI-40 compatible pin header
> > > >
> > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > > > ---
> > > > arch/arm64/boot/dts/rockchip/Makefile | 1 +
> > > > .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
> > > > 2 files changed, 616 insertions(+)
> > > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > >
> > > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> > > > index 4ae9f35434b8..252ee47b8a1d 100644
> > > > --- a/arch/arm64/boot/dts/rockchip/Makefile
> > > > +++ b/arch/arm64/boot/dts/rockchip/Makefile
> > > > @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
> > > > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
> > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > > new file mode 100644
> > > > index 000000000000..184ab7e1d178
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > > @@ -0,0 +1,615 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > > +/*
> > > > + *
> > > > + */
> > > > +
> > > > +/dts-v1/;
> > > > +
> > > > +#include <dt-bindings/gpio/gpio.h>
> > > > +#include <dt-bindings/pinctrl/rockchip.h>
> > > > +#include "rk3566.dtsi"
> > > > +
> > > > +/ {
> > > > + model = "Pine64 RK3566 Quartz64-B Board";
> > > > + compatible = "pine64,quartz64-b", "rockchip,rk3566";
> > > > +
> > >
> > > [..]
> > >
> > > > +
> > > > +&mdio1 {
> > >
> > > > + rgmii_phy1: ethernet-phy@0 {
> > > > + compatible = "ethernet-phy-ieee802.3-c22";
> > > > + reg = <0x1>;
> > >
> > > Hi,
> > >
> > > The reg value doesn't match the node name.
> > > Other 2 boards use "reg = <0>" with label "rgmii_phy1".
> > > Could you check?
> >
> > I do have an older Quartz-B in my boardfarm and in that older
> > devicetree the phy-reg also is "0" instead of the "1" used here.
> >
> > Is that a hardware-change?
>
> The ethernet maintainers previously brought up that 0x0 is the
> broadcast address for the mdio-bus. They requested we put the actual
> bus id of the phy even on single phy busses. This is the first one
> I've confirmed the bus address on.
>
> Though I realized ethernet-phy@0 should be ethernet-phy@1 since you
> mentioned this. Strange dtbs-check doesn't catch this, would you fix
> it in line Heiko
no that's ok, I can fix that up. Just wanted to clarify what the intention
was first :-)
> or do you want another revision?
>
> >
> > Thanks
> > Heiko
> >
> >
>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
@ 2022-05-01 12:04 ` Heiko Stübner
0 siblings, 0 replies; 62+ messages in thread
From: Heiko Stübner @ 2022-05-01 12:04 UTC (permalink / raw)
To: Peter Geis
Cc: open list:ARM/Rockchip SoC...,
Rob Herring, Krzysztof Kozlowski, Johan Jonker, devicetree,
arm-mail-list, Linux Kernel Mailing List
Am Sonntag, 1. Mai 2022, 13:48:02 CEST schrieb Peter Geis:
> On Sun, May 1, 2022 at 7:31 AM Heiko Stübner <heiko@sntech.de> wrote:
> >
> > Am Sonntag, 1. Mai 2022, 09:06:33 CEST schrieb Johan Jonker:
> > >
> > > On 4/29/22 13:52, Peter Geis wrote:
> > > > Add a device tree for the Pine64 Quartz64 Model B single board computer.
> > > > This board ouputs debug on uart2 and supports the following components:
> > > > Gigabit Ethernet
> > > > USB2 x2 (one port otg capable)
> > > > USB3
> > > > PCIe/SATA M2
> > > > HDMI
> > > > DSI (RPi compatible pinout)
> > > > CSI (RPi compatible pinout)
> > > > A/B/G/N WiFi
> > > > Bluetooth
> > > > SDMMC
> > > > eMMC
> > > > SPI Flash
> > > > PI-40 compatible pin header
> > > >
> > > > Signed-off-by: Peter Geis <pgwipeout@gmail.com>
> > > > ---
> > > > arch/arm64/boot/dts/rockchip/Makefile | 1 +
> > > > .../boot/dts/rockchip/rk3566-quartz64-b.dts | 615 ++++++++++++++++++
> > > > 2 files changed, 616 insertions(+)
> > > > create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > >
> > > > diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
> > > > index 4ae9f35434b8..252ee47b8a1d 100644
> > > > --- a/arch/arm64/boot/dts/rockchip/Makefile
> > > > +++ b/arch/arm64/boot/dts/rockchip/Makefile
> > > > @@ -59,5 +59,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3399pro-rock-pi-n10.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
> > > > +dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
> > > > dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
> > > > diff --git a/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > > new file mode 100644
> > > > index 000000000000..184ab7e1d178
> > > > --- /dev/null
> > > > +++ b/arch/arm64/boot/dts/rockchip/rk3566-quartz64-b.dts
> > > > @@ -0,0 +1,615 @@
> > > > +// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
> > > > +/*
> > > > + *
> > > > + */
> > > > +
> > > > +/dts-v1/;
> > > > +
> > > > +#include <dt-bindings/gpio/gpio.h>
> > > > +#include <dt-bindings/pinctrl/rockchip.h>
> > > > +#include "rk3566.dtsi"
> > > > +
> > > > +/ {
> > > > + model = "Pine64 RK3566 Quartz64-B Board";
> > > > + compatible = "pine64,quartz64-b", "rockchip,rk3566";
> > > > +
> > >
> > > [..]
> > >
> > > > +
> > > > +&mdio1 {
> > >
> > > > + rgmii_phy1: ethernet-phy@0 {
> > > > + compatible = "ethernet-phy-ieee802.3-c22";
> > > > + reg = <0x1>;
> > >
> > > Hi,
> > >
> > > The reg value doesn't match the node name.
> > > Other 2 boards use "reg = <0>" with label "rgmii_phy1".
> > > Could you check?
> >
> > I do have an older Quartz-B in my boardfarm and in that older
> > devicetree the phy-reg also is "0" instead of the "1" used here.
> >
> > Is that a hardware-change?
>
> The ethernet maintainers previously brought up that 0x0 is the
> broadcast address for the mdio-bus. They requested we put the actual
> bus id of the phy even on single phy busses. This is the first one
> I've confirmed the bus address on.
>
> Though I realized ethernet-phy@0 should be ethernet-phy@1 since you
> mentioned this. Strange dtbs-check doesn't catch this, would you fix
> it in line Heiko
no that's ok, I can fix that up. Just wanted to clarify what the intention
was first :-)
> or do you want another revision?
>
> >
> > Thanks
> > Heiko
> >
> >
>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v2 6/7] arm64: dts: rockchip: add SoQuartz CM4IO dts
2022-04-29 11:52 ` Peter Geis
(?)
@ 2022-04-29 11:52 ` Peter Geis
-1 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel
This is the initial SoQuartz SoM device tree on a CM4IO carrier board.
This board outputs debug on uart2 and supports the following components:
Gigabit Ethernet
USB2 (OTG/Host shared)
PCIe 2.0 x1
HDMI (HDMI Port 0)
eDP (HDMI Port 1)
DSI (RPi compatible pinout)
CSI (RPi compatible pinout)
A/B/G/N WiFi
Bluetooth
SDMMC
eMMC
SPI NOR Flash (Not placed)
PI-40 compatible pin header
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 167 +++++
.../boot/dts/rockchip/rk3566-soquartz.dtsi | 607 ++++++++++++++++++
3 files changed, 775 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 252ee47b8a1d..23a2a0c111ac 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -60,5 +60,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
new file mode 100644
index 000000000000..fa470a587e2b
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-soquartz.dtsi"
+
+/ {
+ model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board";
+ compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566";
+
+ /* labeled +12v in schematic */
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ /* labeled +5v in schematic */
+ vcc_5v: vcc-5v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+};
+
+/* i2c1 is exposed on CM1 / Module1A
+ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
+ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
+ */
+&i2c1 {
+ status = "okay";
+
+ /* the rtc interrupt is tied to PMIC_PWRON,
+ * it will force reset the board if triggered.
+ */
+ pcf85063: rtc@51 {
+ compatible = "nxp,pcf85063";
+ reg = <0x51>;
+ };
+};
+
+/* i2c2 is exposed on CM1 / Module1A - to PI40
+ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
+ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
+ */
+&i2c2 {
+ status = "disabled";
+};
+
+/* i2c3 is exposed on CM1 / Module1A - to PI40
+ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
+ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+ status = "disabled";
+};
+
+/* i2c4 is exposed on CM2 / Module1B - to PI40
+ * pin 45 - GPIO24 - i2c4_scl_m1
+ * pin 47 - GPIO23 - i2c4_sda_m1
+ */
+&i2c4 {
+ status = "disabled";
+};
+
+/* i2s1_8ch is exposed on CM1 / Module1A - to PI40
+ * pin 24 - GPIO26 - i2s1_sdi1_m1
+ * pin 25 - GPIO21 - i2s1_sdo0_m1
+ * pin 26 - GPIO19 - i2s1_lrck_tx_m1
+ * pin 27 - GPIO20 - i2s1_sdi0_m1
+ * pin 29 - GPIO16 - i2s1_sdi3_m1
+ * pin 30 - GPIO6 - i2s1_sdi2_m1
+ * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
+ * pin 41 - GPIO25 - i2s1_sdo2_m1
+ * pin 49 - GPIO18 - i2s1_sclk_tx_m1
+ * pin 50 - GPIO17 - i2s1_mclk_m1
+ * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
+ */
+&i2s1_8ch {
+ status = "disabled";
+};
+
+&led_diy {
+ status = "okay";
+};
+
+&led_work {
+ status = "okay";
+};
+
+&rgmii_phy1 {
+ status = "okay";
+};
+
+/* saradc is exposed on CM1 / Module1A - to J2
+ * pin 94 - AIN1 - saradc_vin3
+ * pin 96 - AIN0 - saradc_vin2
+ */
+&saradc {
+ status = "disabled";
+};
+
+&sdmmc0 {
+ vmmc-supply = <&sdmmc_pwr>;
+ status = "okay";
+};
+
+&sdmmc_pwr {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ status = "okay";
+};
+
+/* spi3 is exposed on CM1 / Module1A - to PI40
+ * pin 37 - GPIO7 - spi3_cs1_m0
+ * pin 38 - GPIO11 - spi3_clk_m0
+ * pin 39 - GPIO8 - spi3_cs0_m0
+ * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
+ * pin 44 - GPIO10 - spi3_mosi_m0
+ */
+&spi3 {
+ status = "disabled";
+};
+
+/* uart2 is exposed on CM1 / Module1A - to PI40
+ * pin 51 - GPIO15 - uart2_rx_m0
+ * pin 55 - GPIO14 - uart2_tx_m0
+ */
+&uart2 {
+ status = "okay";
+};
+
+/* uart7 is exposed on CM1 / Module1A - to PI40
+ * pin 46 - GPIO22 - uart7_tx_m2
+ * pin 47 - GPIO23 - uart7_rx_m2
+ */
+&uart7 {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc_5v>;
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&vbus {
+ vin-supply = <&vcc_5v>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
new file mode 100644
index 000000000000..9ebb2afe7e82
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
@@ -0,0 +1,607 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "Pine64 RK3566 SoQuartz SOM";
+ compatible = "pine64,soquartz", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ mmc2 = &sdmmc1;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_diy: led-diy {
+ label = "diy-led";
+ default-state = "on";
+ gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&diy_led_enable_h>;
+ retain-state-suspended;
+ status = "disabled";
+ };
+
+ led_work: led-work {
+ label = "work-led";
+ default-state = "off";
+ gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&work_led_enable_h>;
+ retain-state-suspended;
+ status = "disabled";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ status = "okay";
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+
+ vbus: vbus-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ /* sourced from vbus, vbus is provided by the carrier board */
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vbus>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ sdmmc_pwr: sdmmc-pwr-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwr_h>;
+ regulator-name = "sdmmc_pwr";
+ status = "disabled";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_3v3>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m0_miim
+ &gmac1m0_tx_bus2
+ &gmac1m0_rx_bus2
+ &gmac1m0_rgmii_clk
+ &gmac1m0_clkinout
+ &gmac1m0_rgmii_bus>;
+ snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f, also works well here */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ phy-handle = <&rgmii_phy1>;
+ status = "disabled";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_npu";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda0v9_image";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda_0v9";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda0v9_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_acodec";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca_1v8";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pmu";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_image";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ status = "disabled";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ };
+ };
+};
+
+/* i2c1 is exposed on CM1 / Module1A
+ * pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu
+ * pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu
+ */
+&i2c1 {
+ status = "disabled";
+};
+
+/* i2c2 is exposed on CM1 / Module1A
+ * pin 56 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
+ * pin 58 - i2c2_sda_m1, pullup to vcc_3v3
+ */
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m1_xfer>;
+ status = "disabled";
+};
+
+/* i2c3 is exposed on CM1 / Module1A
+ * pin 35 - i2c3_scl_m0, pullup to vcc_3v3
+ * pin 36 - i2c3_sda_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+ status = "disabled";
+};
+
+/* i2c4 is exposed on CM2 / Module1B
+ * pin 45 - i2c4_scl_m1
+ * pin 47 - i2c4_sda_m1
+ */
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m1_xfer>;
+ status = "disabled";
+};
+
+/* i2s1_8ch is exposed on CM1 / Module1A
+ * pin 24 - i2s1_sdi1_m1
+ * pin 25 - i2s1_sdo0_m1
+ * pin 26 - i2s1_lrck_tx_m1
+ * pin 27 - i2s1_sdi0_m1
+ * pin 29 - i2s1_sdi3_m1
+ * pin 30 - i2s1_sdi2_m1
+ * pin 40 - i2s1_sdo1_m1, shared with spi3
+ * pin 41 - i2s1_sdo2_m1
+ * pin 49 - i2s1_sclk_tx_m1
+ * pin 50 - i2s1_mclk_m1
+ * pin 56 - i2s1_sdo3_m1, shared with i2c2
+ */
+&i2s1_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx
+ &i2s1m1_lrcktx &i2s1m1_lrckrx
+ &i2s1m1_sdi0 &i2s1m1_sdi1
+ &i2s1m1_sdi2 &i2s1m1_sdi3
+ &i2s1m1_sdo0 &i2s1m1_sdo1
+ &i2s1m1_sdo2 &i2s1m1_sdo3>;
+ status = "disabled";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ status = "disabled";
+ };
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ work_led_enable_h: work-led-enable-h {
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ diy_led_enable_h: diy-led-enable-h {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc-pwr {
+ sdmmc_pwr_h: sdmmc-pwr-h {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vcc_3v3>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_3v3>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+/* saradc is exposed on CM1 / Module1A
+ * pin 94 - saradc_vin3
+ * pin 96 - saradc_vin2
+ */
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "disabled";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ broken-cd;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "disabled";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+/* spi3 is exposed on CM1 / Module1A
+ * pin 37 - spi3_cs1_m0
+ * pin 38 - spi3_clk_m0
+ * pin 39 - spi3_cs0_m0
+ * pin 40 - spi3_miso_m0, shared with i2s1_8ch
+ * pin 44 - spi3_mosi_m0
+ */
+&spi3 {
+ status = "disabled";
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk809 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcca1v8_pmu>;
+ };
+};
+
+/* uart2 is exposed on CM1 / Module1A
+ * pin 51 - uart2_rx_m0
+ * pin 55 - uart2_tx_m0
+ */
+&uart2 {
+ status = "disabled";
+};
+
+/* uart7 is exposed on CM1 / Module1A
+ * pin 46 - uart7_tx_m2
+ * pin 47 - uart7_rx_m2
+ */
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7m2_xfer>;
+ status = "disabled";
+};
+
+/* dwc3_otg is the only usb port available */
+&usb2phy0 {
+ status = "disabled";
+};
+
+&usb2phy0_otg {
+ status = "disabled";
+};
+
+&usb_host0_xhci {
+ status = "disabled";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [PATCH v2 6/7] arm64: dts: rockchip: add SoQuartz CM4IO dts
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel
This is the initial SoQuartz SoM device tree on a CM4IO carrier board.
This board outputs debug on uart2 and supports the following components:
Gigabit Ethernet
USB2 (OTG/Host shared)
PCIe 2.0 x1
HDMI (HDMI Port 0)
eDP (HDMI Port 1)
DSI (RPi compatible pinout)
CSI (RPi compatible pinout)
A/B/G/N WiFi
Bluetooth
SDMMC
eMMC
SPI NOR Flash (Not placed)
PI-40 compatible pin header
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 167 +++++
.../boot/dts/rockchip/rk3566-soquartz.dtsi | 607 ++++++++++++++++++
3 files changed, 775 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 252ee47b8a1d..23a2a0c111ac 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -60,5 +60,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
new file mode 100644
index 000000000000..fa470a587e2b
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-soquartz.dtsi"
+
+/ {
+ model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board";
+ compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566";
+
+ /* labeled +12v in schematic */
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ /* labeled +5v in schematic */
+ vcc_5v: vcc-5v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+};
+
+/* i2c1 is exposed on CM1 / Module1A
+ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
+ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
+ */
+&i2c1 {
+ status = "okay";
+
+ /* the rtc interrupt is tied to PMIC_PWRON,
+ * it will force reset the board if triggered.
+ */
+ pcf85063: rtc@51 {
+ compatible = "nxp,pcf85063";
+ reg = <0x51>;
+ };
+};
+
+/* i2c2 is exposed on CM1 / Module1A - to PI40
+ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
+ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
+ */
+&i2c2 {
+ status = "disabled";
+};
+
+/* i2c3 is exposed on CM1 / Module1A - to PI40
+ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
+ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+ status = "disabled";
+};
+
+/* i2c4 is exposed on CM2 / Module1B - to PI40
+ * pin 45 - GPIO24 - i2c4_scl_m1
+ * pin 47 - GPIO23 - i2c4_sda_m1
+ */
+&i2c4 {
+ status = "disabled";
+};
+
+/* i2s1_8ch is exposed on CM1 / Module1A - to PI40
+ * pin 24 - GPIO26 - i2s1_sdi1_m1
+ * pin 25 - GPIO21 - i2s1_sdo0_m1
+ * pin 26 - GPIO19 - i2s1_lrck_tx_m1
+ * pin 27 - GPIO20 - i2s1_sdi0_m1
+ * pin 29 - GPIO16 - i2s1_sdi3_m1
+ * pin 30 - GPIO6 - i2s1_sdi2_m1
+ * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
+ * pin 41 - GPIO25 - i2s1_sdo2_m1
+ * pin 49 - GPIO18 - i2s1_sclk_tx_m1
+ * pin 50 - GPIO17 - i2s1_mclk_m1
+ * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
+ */
+&i2s1_8ch {
+ status = "disabled";
+};
+
+&led_diy {
+ status = "okay";
+};
+
+&led_work {
+ status = "okay";
+};
+
+&rgmii_phy1 {
+ status = "okay";
+};
+
+/* saradc is exposed on CM1 / Module1A - to J2
+ * pin 94 - AIN1 - saradc_vin3
+ * pin 96 - AIN0 - saradc_vin2
+ */
+&saradc {
+ status = "disabled";
+};
+
+&sdmmc0 {
+ vmmc-supply = <&sdmmc_pwr>;
+ status = "okay";
+};
+
+&sdmmc_pwr {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ status = "okay";
+};
+
+/* spi3 is exposed on CM1 / Module1A - to PI40
+ * pin 37 - GPIO7 - spi3_cs1_m0
+ * pin 38 - GPIO11 - spi3_clk_m0
+ * pin 39 - GPIO8 - spi3_cs0_m0
+ * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
+ * pin 44 - GPIO10 - spi3_mosi_m0
+ */
+&spi3 {
+ status = "disabled";
+};
+
+/* uart2 is exposed on CM1 / Module1A - to PI40
+ * pin 51 - GPIO15 - uart2_rx_m0
+ * pin 55 - GPIO14 - uart2_tx_m0
+ */
+&uart2 {
+ status = "okay";
+};
+
+/* uart7 is exposed on CM1 / Module1A - to PI40
+ * pin 46 - GPIO22 - uart7_tx_m2
+ * pin 47 - GPIO23 - uart7_rx_m2
+ */
+&uart7 {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc_5v>;
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&vbus {
+ vin-supply = <&vcc_5v>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
new file mode 100644
index 000000000000..9ebb2afe7e82
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
@@ -0,0 +1,607 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "Pine64 RK3566 SoQuartz SOM";
+ compatible = "pine64,soquartz", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ mmc2 = &sdmmc1;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_diy: led-diy {
+ label = "diy-led";
+ default-state = "on";
+ gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&diy_led_enable_h>;
+ retain-state-suspended;
+ status = "disabled";
+ };
+
+ led_work: led-work {
+ label = "work-led";
+ default-state = "off";
+ gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&work_led_enable_h>;
+ retain-state-suspended;
+ status = "disabled";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ status = "okay";
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+
+ vbus: vbus-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ /* sourced from vbus, vbus is provided by the carrier board */
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vbus>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ sdmmc_pwr: sdmmc-pwr-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwr_h>;
+ regulator-name = "sdmmc_pwr";
+ status = "disabled";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_3v3>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m0_miim
+ &gmac1m0_tx_bus2
+ &gmac1m0_rx_bus2
+ &gmac1m0_rgmii_clk
+ &gmac1m0_clkinout
+ &gmac1m0_rgmii_bus>;
+ snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f, also works well here */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ phy-handle = <&rgmii_phy1>;
+ status = "disabled";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_npu";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda0v9_image";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda_0v9";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda0v9_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_acodec";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca_1v8";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pmu";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_image";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ status = "disabled";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ };
+ };
+};
+
+/* i2c1 is exposed on CM1 / Module1A
+ * pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu
+ * pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu
+ */
+&i2c1 {
+ status = "disabled";
+};
+
+/* i2c2 is exposed on CM1 / Module1A
+ * pin 56 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
+ * pin 58 - i2c2_sda_m1, pullup to vcc_3v3
+ */
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m1_xfer>;
+ status = "disabled";
+};
+
+/* i2c3 is exposed on CM1 / Module1A
+ * pin 35 - i2c3_scl_m0, pullup to vcc_3v3
+ * pin 36 - i2c3_sda_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+ status = "disabled";
+};
+
+/* i2c4 is exposed on CM2 / Module1B
+ * pin 45 - i2c4_scl_m1
+ * pin 47 - i2c4_sda_m1
+ */
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m1_xfer>;
+ status = "disabled";
+};
+
+/* i2s1_8ch is exposed on CM1 / Module1A
+ * pin 24 - i2s1_sdi1_m1
+ * pin 25 - i2s1_sdo0_m1
+ * pin 26 - i2s1_lrck_tx_m1
+ * pin 27 - i2s1_sdi0_m1
+ * pin 29 - i2s1_sdi3_m1
+ * pin 30 - i2s1_sdi2_m1
+ * pin 40 - i2s1_sdo1_m1, shared with spi3
+ * pin 41 - i2s1_sdo2_m1
+ * pin 49 - i2s1_sclk_tx_m1
+ * pin 50 - i2s1_mclk_m1
+ * pin 56 - i2s1_sdo3_m1, shared with i2c2
+ */
+&i2s1_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx
+ &i2s1m1_lrcktx &i2s1m1_lrckrx
+ &i2s1m1_sdi0 &i2s1m1_sdi1
+ &i2s1m1_sdi2 &i2s1m1_sdi3
+ &i2s1m1_sdo0 &i2s1m1_sdo1
+ &i2s1m1_sdo2 &i2s1m1_sdo3>;
+ status = "disabled";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ status = "disabled";
+ };
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ work_led_enable_h: work-led-enable-h {
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ diy_led_enable_h: diy-led-enable-h {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc-pwr {
+ sdmmc_pwr_h: sdmmc-pwr-h {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vcc_3v3>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_3v3>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+/* saradc is exposed on CM1 / Module1A
+ * pin 94 - saradc_vin3
+ * pin 96 - saradc_vin2
+ */
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "disabled";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ broken-cd;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "disabled";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+/* spi3 is exposed on CM1 / Module1A
+ * pin 37 - spi3_cs1_m0
+ * pin 38 - spi3_clk_m0
+ * pin 39 - spi3_cs0_m0
+ * pin 40 - spi3_miso_m0, shared with i2s1_8ch
+ * pin 44 - spi3_mosi_m0
+ */
+&spi3 {
+ status = "disabled";
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk809 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcca1v8_pmu>;
+ };
+};
+
+/* uart2 is exposed on CM1 / Module1A
+ * pin 51 - uart2_rx_m0
+ * pin 55 - uart2_tx_m0
+ */
+&uart2 {
+ status = "disabled";
+};
+
+/* uart7 is exposed on CM1 / Module1A
+ * pin 46 - uart7_tx_m2
+ * pin 47 - uart7_rx_m2
+ */
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7m2_xfer>;
+ status = "disabled";
+};
+
+/* dwc3_otg is the only usb port available */
+&usb2phy0 {
+ status = "disabled";
+};
+
+&usb2phy0_otg {
+ status = "disabled";
+};
+
+&usb_host0_xhci {
+ status = "disabled";
+};
--
2.25.1
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^ permalink raw reply related [flat|nested] 62+ messages in thread* [PATCH v2 6/7] arm64: dts: rockchip: add SoQuartz CM4IO dts
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Peter Geis, devicetree, linux-arm-kernel, linux-kernel
This is the initial SoQuartz SoM device tree on a CM4IO carrier board.
This board outputs debug on uart2 and supports the following components:
Gigabit Ethernet
USB2 (OTG/Host shared)
PCIe 2.0 x1
HDMI (HDMI Port 0)
eDP (HDMI Port 1)
DSI (RPi compatible pinout)
CSI (RPi compatible pinout)
A/B/G/N WiFi
Bluetooth
SDMMC
eMMC
SPI NOR Flash (Not placed)
PI-40 compatible pin header
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../boot/dts/rockchip/rk3566-soquartz-cm4.dts | 167 +++++
.../boot/dts/rockchip/rk3566-soquartz.dtsi | 607 ++++++++++++++++++
3 files changed, 775 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 252ee47b8a1d..23a2a0c111ac 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -60,5 +60,6 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
new file mode 100644
index 000000000000..fa470a587e2b
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts
@@ -0,0 +1,167 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include "rk3566-soquartz.dtsi"
+
+/ {
+ model = "Pine64 RK3566 SoQuartz with CM4-IO Carrier Board";
+ compatible = "pine64,soquartz-cm4io", "pine64,soquartz", "rockchip,rk3566";
+
+ /* labeled +12v in schematic */
+ vcc12v_dcin: vcc12v-dcin-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc12v_dcin";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <12000000>;
+ regulator-max-microvolt = <12000000>;
+ };
+
+ /* labeled +5v in schematic */
+ vcc_5v: vcc-5v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc12v_dcin>;
+ };
+};
+
+&gmac1 {
+ status = "okay";
+};
+
+/* i2c1 is exposed on CM1 / Module1A
+ * pin 80 - SCL0 - i2c1_scl_m0, pullup to vcc3v3_pmu
+ * pin 82 - SDA0 - i2c1_sda_m0, pullup to vcc3v3_pmu
+ */
+&i2c1 {
+ status = "okay";
+
+ /* the rtc interrupt is tied to PMIC_PWRON,
+ * it will force reset the board if triggered.
+ */
+ pcf85063: rtc@51 {
+ compatible = "nxp,pcf85063";
+ reg = <0x51>;
+ };
+};
+
+/* i2c2 is exposed on CM1 / Module1A - to PI40
+ * pin 56 - GPIO3 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
+ * pin 58 - GPIO2 - i2c2_sda_m1, pullup to vcc_3v3
+ */
+&i2c2 {
+ status = "disabled";
+};
+
+/* i2c3 is exposed on CM1 / Module1A - to PI40
+ * pin 35 - ID_SC(GPIO28) - i2c3_scl_m0, pullup to vcc_3v3
+ * pin 36 - ID_SD(GPIO27) - i2c3_sda_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+ status = "disabled";
+};
+
+/* i2c4 is exposed on CM2 / Module1B - to PI40
+ * pin 45 - GPIO24 - i2c4_scl_m1
+ * pin 47 - GPIO23 - i2c4_sda_m1
+ */
+&i2c4 {
+ status = "disabled";
+};
+
+/* i2s1_8ch is exposed on CM1 / Module1A - to PI40
+ * pin 24 - GPIO26 - i2s1_sdi1_m1
+ * pin 25 - GPIO21 - i2s1_sdo0_m1
+ * pin 26 - GPIO19 - i2s1_lrck_tx_m1
+ * pin 27 - GPIO20 - i2s1_sdi0_m1
+ * pin 29 - GPIO16 - i2s1_sdi3_m1
+ * pin 30 - GPIO6 - i2s1_sdi2_m1
+ * pin 40 - GPIO9 - i2s1_sdo1_m1, shared with spi3
+ * pin 41 - GPIO25 - i2s1_sdo2_m1
+ * pin 49 - GPIO18 - i2s1_sclk_tx_m1
+ * pin 50 - GPIO17 - i2s1_mclk_m1
+ * pin 56 - GPIO3 - i2s1_sdo3_m1, shared with i2c2
+ */
+&i2s1_8ch {
+ status = "disabled";
+};
+
+&led_diy {
+ status = "okay";
+};
+
+&led_work {
+ status = "okay";
+};
+
+&rgmii_phy1 {
+ status = "okay";
+};
+
+/* saradc is exposed on CM1 / Module1A - to J2
+ * pin 94 - AIN1 - saradc_vin3
+ * pin 96 - AIN0 - saradc_vin2
+ */
+&saradc {
+ status = "disabled";
+};
+
+&sdmmc0 {
+ vmmc-supply = <&sdmmc_pwr>;
+ status = "okay";
+};
+
+&sdmmc_pwr {
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ status = "okay";
+};
+
+/* spi3 is exposed on CM1 / Module1A - to PI40
+ * pin 37 - GPIO7 - spi3_cs1_m0
+ * pin 38 - GPIO11 - spi3_clk_m0
+ * pin 39 - GPIO8 - spi3_cs0_m0
+ * pin 40 - GPIO9 - spi3_miso_m0, shared with i2s1_8ch
+ * pin 44 - GPIO10 - spi3_mosi_m0
+ */
+&spi3 {
+ status = "disabled";
+};
+
+/* uart2 is exposed on CM1 / Module1A - to PI40
+ * pin 51 - GPIO15 - uart2_rx_m0
+ * pin 55 - GPIO14 - uart2_tx_m0
+ */
+&uart2 {
+ status = "okay";
+};
+
+/* uart7 is exposed on CM1 / Module1A - to PI40
+ * pin 46 - GPIO22 - uart7_tx_m2
+ * pin 47 - GPIO23 - uart7_rx_m2
+ */
+&uart7 {
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc_5v>;
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&vbus {
+ vin-supply = <&vcc_5v>;
+};
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
new file mode 100644
index 000000000000..9ebb2afe7e82
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi
@@ -0,0 +1,607 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "Pine64 RK3566 SoQuartz SOM";
+ compatible = "pine64,soquartz", "rockchip,rk3566";
+
+ aliases {
+ ethernet0 = &gmac1;
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ mmc2 = &sdmmc1;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led_diy: led-diy {
+ label = "diy-led";
+ default-state = "on";
+ gpios = <&gpio0 RK_PC1 GPIO_ACTIVE_LOW>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&diy_led_enable_h>;
+ retain-state-suspended;
+ status = "disabled";
+ };
+
+ led_work: led-work {
+ label = "work-led";
+ default-state = "off";
+ gpios = <&gpio0 RK_PC0 GPIO_ACTIVE_LOW>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&work_led_enable_h>;
+ retain-state-suspended;
+ status = "disabled";
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ status = "okay";
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio2 RK_PC2 GPIO_ACTIVE_LOW>;
+ };
+
+ vbus: vbus-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vbus";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ /* sourced from vbus, vbus is provided by the carrier board */
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vbus>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ sdmmc_pwr: sdmmc-pwr-regulator {
+ compatible = "regulator-fixed";
+ enable-active-high;
+ gpio = <&gpio0 RK_PA5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc_pwr_h>;
+ regulator-name = "sdmmc_pwr";
+ status = "disabled";
+ };
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+ clock_in_out = "input";
+ phy-supply = <&vcc_3v3>;
+ phy-mode = "rgmii";
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m0_miim
+ &gmac1m0_tx_bus2
+ &gmac1m0_rx_bus2
+ &gmac1m0_rgmii_clk
+ &gmac1m0_clkinout
+ &gmac1m0_rgmii_bus>;
+ snps,reset-gpio = <&gpio0 RK_PC3 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f, also works well here */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x30>;
+ rx_delay = <0x10>;
+ phy-handle = <&rgmii_phy1>;
+ status = "disabled";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA3 IRQ_TYPE_LEVEL_LOW>;
+ #clock-cells = <1>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int_l>;
+ rockchip,system-power-controller;
+ wakeup-source;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+
+ regulators {
+ vdd_logic: DCDC_REG1 {
+ regulator-name = "vdd_logic";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vcc_ddr";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-initial-mode = <0x2>;
+ regulator-name = "vdd_npu";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda0v9_image";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda_0v9";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-name = "vdda0v9_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_acodec";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vccio_sd";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-name = "vcc3v3_pmu";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca_1v8";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_pmu";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+ regulator-name = "vcca1v8_image";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-name = "vcc_3v3";
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ status = "disabled";
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ };
+ };
+};
+
+/* i2c1 is exposed on CM1 / Module1A
+ * pin 80 - i2c1_scl_m0, pullup to vcc3v3_pmu
+ * pin 82 - i2c1_sda_m0, pullup to vcc3v3_pmu
+ */
+&i2c1 {
+ status = "disabled";
+};
+
+/* i2c2 is exposed on CM1 / Module1A
+ * pin 56 - i2c2_scl_m1, pullup to vcc_3v3, shared with i2s1_8ch
+ * pin 58 - i2c2_sda_m1, pullup to vcc_3v3
+ */
+&i2c2 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c2m1_xfer>;
+ status = "disabled";
+};
+
+/* i2c3 is exposed on CM1 / Module1A
+ * pin 35 - i2c3_scl_m0, pullup to vcc_3v3
+ * pin 36 - i2c3_sda_m0, pullup to vcc_3v3
+ */
+&i2c3 {
+ status = "disabled";
+};
+
+/* i2c4 is exposed on CM2 / Module1B
+ * pin 45 - i2c4_scl_m1
+ * pin 47 - i2c4_sda_m1
+ */
+&i2c4 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c4m1_xfer>;
+ status = "disabled";
+};
+
+/* i2s1_8ch is exposed on CM1 / Module1A
+ * pin 24 - i2s1_sdi1_m1
+ * pin 25 - i2s1_sdo0_m1
+ * pin 26 - i2s1_lrck_tx_m1
+ * pin 27 - i2s1_sdi0_m1
+ * pin 29 - i2s1_sdi3_m1
+ * pin 30 - i2s1_sdi2_m1
+ * pin 40 - i2s1_sdo1_m1, shared with spi3
+ * pin 41 - i2s1_sdo2_m1
+ * pin 49 - i2s1_sclk_tx_m1
+ * pin 50 - i2s1_mclk_m1
+ * pin 56 - i2s1_sdo3_m1, shared with i2c2
+ */
+&i2s1_8ch {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2s1m1_sclktx &i2s1m1_sclkrx
+ &i2s1m1_lrcktx &i2s1m1_lrckrx
+ &i2s1m1_sdi0 &i2s1m1_sdi1
+ &i2s1m1_sdi2 &i2s1m1_sdi3
+ &i2s1m1_sdo0 &i2s1m1_sdo1
+ &i2s1m1_sdo2 &i2s1m1_sdo3>;
+ status = "disabled";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0>;
+ status = "disabled";
+ };
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <2 RK_PB7 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <2 RK_PC0 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <2 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ work_led_enable_h: work-led-enable-h {
+ rockchip,pins = <0 RK_PC0 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ diy_led_enable_h: diy-led-enable-h {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int_l: pmic-int-l {
+ rockchip,pins = <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <2 RK_PC2 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ sdmmc-pwr {
+ sdmmc_pwr_h: sdmmc-pwr-h {
+ rockchip,pins = <0 RK_PA5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vcc_3v3>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_3v3>;
+ vccio7-supply = <&vcc_3v3>;
+ status = "okay";
+};
+
+/* saradc is exposed on CM1 / Module1A
+ * pin 94 - saradc_vin3
+ * pin 96 - saradc_vin2
+ */
+&saradc {
+ vref-supply = <&vcca_1v8>;
+ status = "disabled";
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ broken-cd;
+ bus-width = <4>;
+ cap-sd-highspeed;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "disabled";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ non-removable;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+/* spi3 is exposed on CM1 / Module1A
+ * pin 37 - spi3_cs1_m0
+ * pin 38 - spi3_clk_m0
+ * pin 39 - spi3_cs0_m0
+ * pin 40 - spi3_miso_m0, shared with i2s1_8ch
+ * pin 44 - spi3_mosi_m0
+ */
+&spi3 {
+ status = "disabled";
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn &uart1m0_rtsn>;
+ uart-has-rtscts;
+ status = "okay";
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk809 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcca1v8_pmu>;
+ };
+};
+
+/* uart2 is exposed on CM1 / Module1A
+ * pin 51 - uart2_rx_m0
+ * pin 55 - uart2_tx_m0
+ */
+&uart2 {
+ status = "disabled";
+};
+
+/* uart7 is exposed on CM1 / Module1A
+ * pin 46 - uart7_tx_m2
+ * pin 47 - uart7_rx_m2
+ */
+&uart7 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart7m2_xfer>;
+ status = "disabled";
+};
+
+/* dwc3_otg is the only usb port available */
+&usb2phy0 {
+ status = "disabled";
+};
+
+&usb2phy0_otg {
+ status = "disabled";
+};
+
+&usb_host0_xhci {
+ status = "disabled";
+};
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [PATCH v2 6/7] arm64: dts: rockchip: add SoQuartz CM4IO dts
2022-04-29 11:52 ` Peter Geis
(?)
@ 2022-04-30 5:42 ` kernel test robot
-1 siblings, 0 replies; 62+ messages in thread
From: kernel test robot @ 2022-04-30 5:42 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: llvm, kbuild-all, Peter Geis, devicetree, linux-arm-kernel, linux-kernel
Hi Peter,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
[cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204301300.XpbFVL82-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/9c1ec04920cfad39477824908a540d7547dbed23
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
git checkout 9c1ec04920cfad39477824908a540d7547dbed23
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi:605.1-16 Label or path usb_host0_xhci not found
>> Error: arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts:161.1-16 Label or path usb_host0_xhci not found
FATAL ERROR: Syntax error parsing input tree
--
0-DAY CI Kernel Test Service
https://01.org/lkp
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 6/7] arm64: dts: rockchip: add SoQuartz CM4IO dts
@ 2022-04-30 5:42 ` kernel test robot
0 siblings, 0 replies; 62+ messages in thread
From: kernel test robot @ 2022-04-30 5:42 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: llvm, kbuild-all, Peter Geis, devicetree, linux-arm-kernel, linux-kernel
Hi Peter,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
[cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204301300.XpbFVL82-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/9c1ec04920cfad39477824908a540d7547dbed23
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
git checkout 9c1ec04920cfad39477824908a540d7547dbed23
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi:605.1-16 Label or path usb_host0_xhci not found
>> Error: arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts:161.1-16 Label or path usb_host0_xhci not found
FATAL ERROR: Syntax error parsing input tree
--
0-DAY CI Kernel Test Service
https://01.org/lkp
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 6/7] arm64: dts: rockchip: add SoQuartz CM4IO dts
@ 2022-04-30 5:42 ` kernel test robot
0 siblings, 0 replies; 62+ messages in thread
From: kernel test robot @ 2022-04-30 5:42 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: llvm, kbuild-all, Peter Geis, devicetree, linux-arm-kernel, linux-kernel
Hi Peter,
I love your patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
[cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204301300.XpbFVL82-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/9c1ec04920cfad39477824908a540d7547dbed23
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
git checkout 9c1ec04920cfad39477824908a540d7547dbed23
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/rockchip/rk3566-soquartz.dtsi:605.1-16 Label or path usb_host0_xhci not found
>> Error: arch/arm64/boot/dts/rockchip/rk3566-soquartz-cm4.dts:161.1-16 Label or path usb_host0_xhci not found
FATAL ERROR: Syntax error parsing input tree
--
0-DAY CI Kernel Test Service
https://01.org/lkp
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 62+ messages in thread
* [PATCH v2 7/7] arm64: dts: rockchip: add dts for Firefly Station M2 rk3566
2022-04-29 11:52 ` Peter Geis
(?)
@ 2022-04-29 11:52 ` Peter Geis
-1 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Furkan Kardame, devicetree, linux-arm-kernel, linux-kernel, Peter Geis
From: Furkan Kardame <f.kardame@manjaro.org>
Add dts for Firefly Station M2.
Working IO:
* UART
* LED
* LAN
* Wifi
* SD Card
* eMMC
* USB2
Signed-off-by: Furkan Kardame <f.kardame@manjaro.org>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 580 ++++++++++++++++++
2 files changed, 581 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 23a2a0c111ac..617915c17ca8 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
new file mode 100644
index 000000000000..1ede01b46e1c
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
@@ -0,0 +1,580 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "Firefly Station M2";
+ compatible = "firefly,rk3566-roc-pc", "rockchip,rk3566";
+
+ aliases {
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ mmc2 = &sdmmc1;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-user {
+ label = "user-led";
+ default-state = "on";
+ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led_enable_h>;
+ retain-state-suspended;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ status = "okay";
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+ };
+
+ usb_5v: usb-5v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&usb_5v>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb30_host";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb30_host_en_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb_otg";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+ clock_in_out = "input";
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m0_miim
+ &gmac1m0_tx_bus2
+ &gmac1m0_rx_bus2
+ &gmac1m0_rgmii_clk
+ &gmac1m0_clkinout
+ &gmac1m0_rgmii_bus>;
+ snps,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x4f>;
+ rx_delay = <0x24>;
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-boot-on;
+ regulator-name = "vcc3v3";
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m1_xfer>;
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ };
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ user_led_enable_h: user-led-enable-h {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcca1v8_pmu>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ status = "okay";
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
+ status = "okay";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk809 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcca1v8_pmu>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
--
2.25.1
^ permalink raw reply related [flat|nested] 62+ messages in thread* [PATCH v2 7/7] arm64: dts: rockchip: add dts for Firefly Station M2 rk3566
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Furkan Kardame, devicetree, linux-arm-kernel, linux-kernel, Peter Geis
From: Furkan Kardame <f.kardame@manjaro.org>
Add dts for Firefly Station M2.
Working IO:
* UART
* LED
* LAN
* Wifi
* SD Card
* eMMC
* USB2
Signed-off-by: Furkan Kardame <f.kardame@manjaro.org>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 580 ++++++++++++++++++
2 files changed, 581 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 23a2a0c111ac..617915c17ca8 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
new file mode 100644
index 000000000000..1ede01b46e1c
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
@@ -0,0 +1,580 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "Firefly Station M2";
+ compatible = "firefly,rk3566-roc-pc", "rockchip,rk3566";
+
+ aliases {
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ mmc2 = &sdmmc1;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-user {
+ label = "user-led";
+ default-state = "on";
+ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led_enable_h>;
+ retain-state-suspended;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ status = "okay";
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+ };
+
+ usb_5v: usb-5v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&usb_5v>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb30_host";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb30_host_en_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb_otg";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+ clock_in_out = "input";
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m0_miim
+ &gmac1m0_tx_bus2
+ &gmac1m0_rx_bus2
+ &gmac1m0_rgmii_clk
+ &gmac1m0_clkinout
+ &gmac1m0_rgmii_bus>;
+ snps,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x4f>;
+ rx_delay = <0x24>;
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-boot-on;
+ regulator-name = "vcc3v3";
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m1_xfer>;
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ };
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ user_led_enable_h: user-led-enable-h {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcca1v8_pmu>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ status = "okay";
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
+ status = "okay";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk809 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcca1v8_pmu>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
--
2.25.1
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^ permalink raw reply related [flat|nested] 62+ messages in thread* [PATCH v2 7/7] arm64: dts: rockchip: add dts for Firefly Station M2 rk3566
@ 2022-04-29 11:52 ` Peter Geis
0 siblings, 0 replies; 62+ messages in thread
From: Peter Geis @ 2022-04-29 11:52 UTC (permalink / raw)
To: linux-rockchip, Rob Herring, Krzysztof Kozlowski, Heiko Stuebner
Cc: Furkan Kardame, devicetree, linux-arm-kernel, linux-kernel, Peter Geis
From: Furkan Kardame <f.kardame@manjaro.org>
Add dts for Firefly Station M2.
Working IO:
* UART
* LED
* LAN
* Wifi
* SD Card
* eMMC
* USB2
Signed-off-by: Furkan Kardame <f.kardame@manjaro.org>
Signed-off-by: Peter Geis <pgwipeout@gmail.com>
---
arch/arm64/boot/dts/rockchip/Makefile | 1 +
.../arm64/boot/dts/rockchip/rk3566-roc-pc.dts | 580 ++++++++++++++++++
2 files changed, 581 insertions(+)
create mode 100644 arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
diff --git a/arch/arm64/boot/dts/rockchip/Makefile b/arch/arm64/boot/dts/rockchip/Makefile
index 23a2a0c111ac..617915c17ca8 100644
--- a/arch/arm64/boot/dts/rockchip/Makefile
+++ b/arch/arm64/boot/dts/rockchip/Makefile
@@ -60,6 +60,7 @@ dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.1.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-pinenote-v1.2.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-a.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-quartz64-b.dtb
+dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-roc-pc.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3566-soquartz-cm4.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-evb1-v10.dtb
dtb-$(CONFIG_ARCH_ROCKCHIP) += rk3568-bpi-r2-pro.dtb
diff --git a/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
new file mode 100644
index 000000000000..1ede01b46e1c
--- /dev/null
+++ b/arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts
@@ -0,0 +1,580 @@
+// SPDX-License-Identifier: (GPL-2.0+ OR MIT)
+
+/dts-v1/;
+
+#include <dt-bindings/gpio/gpio.h>
+#include <dt-bindings/pinctrl/rockchip.h>
+#include "rk3566.dtsi"
+
+/ {
+ model = "Firefly Station M2";
+ compatible = "firefly,rk3566-roc-pc", "rockchip,rk3566";
+
+ aliases {
+ mmc0 = &sdmmc0;
+ mmc1 = &sdhci;
+ mmc2 = &sdmmc1;
+ };
+
+ chosen: chosen {
+ stdout-path = "serial2:1500000n8";
+ };
+
+ gmac1_clkin: external-gmac1-clock {
+ compatible = "fixed-clock";
+ clock-frequency = <125000000>;
+ clock-output-names = "gmac1_clkin";
+ #clock-cells = <0>;
+ };
+
+ leds {
+ compatible = "gpio-leds";
+
+ led-user {
+ label = "user-led";
+ default-state = "on";
+ gpios = <&gpio0 RK_PD3 GPIO_ACTIVE_HIGH>;
+ linux,default-trigger = "heartbeat";
+ pinctrl-names = "default";
+ pinctrl-0 = <&user_led_enable_h>;
+ retain-state-suspended;
+ };
+ };
+
+ sdio_pwrseq: sdio-pwrseq {
+ status = "okay";
+ compatible = "mmc-pwrseq-simple";
+ clocks = <&rk809 1>;
+ clock-names = "ext_clock";
+ pinctrl-names = "default";
+ pinctrl-0 = <&wifi_enable_h>;
+ reset-gpios = <&gpio2 RK_PB1 GPIO_ACTIVE_LOW>;
+ };
+
+ usb_5v: usb-5v-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "usb_5v";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ };
+
+ vcc5v0_sys: vcc5v0-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_sys";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&usb_5v>;
+ };
+
+ vcc3v3_sys: vcc3v3-sys-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc3v3_sys";
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+ regulator-always-on;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb30_host: vcc5v0-usb30-host-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb30_host";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC5 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb30_host_en_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+
+ vcc5v0_usb_otg: vcc5v0-usb-otg-regulator {
+ compatible = "regulator-fixed";
+ regulator-name = "vcc5v0_usb_otg";
+ enable-active-high;
+ gpio = <&gpio0 RK_PC6 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&vcc5v0_usb_otg_en_h>;
+ regulator-always-on;
+ regulator-min-microvolt = <5000000>;
+ regulator-max-microvolt = <5000000>;
+ vin-supply = <&vcc5v0_sys>;
+ };
+};
+
+&combphy1 {
+ status = "okay";
+};
+
+&cpu0 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu1 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu2 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&cpu3 {
+ cpu-supply = <&vdd_cpu>;
+};
+
+&gmac1 {
+ assigned-clocks = <&cru SCLK_GMAC1_RX_TX>, <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>;
+ assigned-clock-parents = <&cru SCLK_GMAC1_RGMII_SPEED>, <&cru SCLK_GMAC1>, <&gmac1_clkin>;
+ clock_in_out = "input";
+ phy-mode = "rgmii-id";
+ phy-supply = <&vcc_3v3>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&gmac1m0_miim
+ &gmac1m0_tx_bus2
+ &gmac1m0_rx_bus2
+ &gmac1m0_rgmii_clk
+ &gmac1m0_clkinout
+ &gmac1m0_rgmii_bus>;
+ snps,reset-gpio = <&gpio0 RK_PB7 GPIO_ACTIVE_LOW>;
+ snps,reset-active-low;
+ /* Reset time is 20ms, 100ms for rtl8211f */
+ snps,reset-delays-us = <0 20000 100000>;
+ tx_delay = <0x4f>;
+ rx_delay = <0x24>;
+ phy-handle = <&rgmii_phy1>;
+ status = "okay";
+};
+
+&i2c0 {
+ status = "okay";
+
+ vdd_cpu: regulator@1c {
+ compatible = "tcs,tcs4525";
+ reg = <0x1c>;
+ fcs,suspend-voltage-selector = <1>;
+ regulator-name = "vdd_cpu";
+ regulator-min-microvolt = <800000>;
+ regulator-max-microvolt = <1150000>;
+ regulator-ramp-delay = <2300>;
+ regulator-always-on;
+ regulator-boot-on;
+ vin-supply = <&vcc5v0_sys>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ rk809: pmic@20 {
+ compatible = "rockchip,rk809";
+ reg = <0x20>;
+ interrupt-parent = <&gpio0>;
+ interrupts = <RK_PA7 IRQ_TYPE_LEVEL_LOW>;
+ clock-output-names = "rk808-clkout1", "rk808-clkout2";
+
+ pinctrl-names = "default";
+ pinctrl-0 = <&pmic_int>;
+ rockchip,system-power-controller;
+ wakeup-source;
+ #clock-cells = <1>;
+
+ vcc1-supply = <&vcc3v3_sys>;
+ vcc2-supply = <&vcc3v3_sys>;
+ vcc3-supply = <&vcc3v3_sys>;
+ vcc4-supply = <&vcc3v3_sys>;
+ vcc5-supply = <&vcc3v3_sys>;
+ vcc6-supply = <&vcc3v3_sys>;
+ vcc7-supply = <&vcc3v3_sys>;
+ vcc8-supply = <&vcc3v3_sys>;
+ vcc9-supply = <&vcc3v3_sys>;
+
+ regulators {
+ vdd_log: DCDC_REG1 {
+ regulator-name = "vdd_log";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <500000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdd_gpu: DCDC_REG2 {
+ regulator-name = "vdd_gpu";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-init-microvolt = <900000>;
+ regulator-ramp-delay = <6001>;
+
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vcc_ddr: DCDC_REG3 {
+ regulator-name = "vcc_ddr";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1100000>;
+ regulator-max-microvolt = <1100000>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ };
+ };
+
+ vdd_npu: DCDC_REG4 {
+ regulator-name = "vdd_npu";
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <1350000>;
+ regulator-initial-mode = <0x2>;
+ regulator-state-mem {
+ regulator-off-in-suspend;
+ };
+ };
+
+ vcc_1v8: DCDC_REG5 {
+ regulator-name = "vcc_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vdda0v9_image: LDO_REG1 {
+ regulator-name = "vdda0v9_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda_0v9: LDO_REG2 {
+ regulator-name = "vdda_0v9";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vdda0v9_pmu: LDO_REG3 {
+ regulator-name = "vdda0v9_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <900000>;
+ regulator-max-microvolt = <900000>;
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <900000>;
+ };
+ };
+
+ vccio_acodec: LDO_REG4 {
+ regulator-name = "vccio_acodec";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+
+ };
+ };
+
+ vccio_sd: LDO_REG5 {
+ regulator-name = "vccio_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcc3v3_pmu: LDO_REG6 {
+ regulator-name = "vcc3v3_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <3300000>;
+ regulator-max-microvolt = <3300000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <3300000>;
+ };
+ };
+
+ vcca_1v8: LDO_REG7 {
+ regulator-name = "vcca_1v8";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_pmu: LDO_REG8 {
+ regulator-name = "vcca1v8_pmu";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcca1v8_image: LDO_REG9 {
+ regulator-name = "vcca1v8_image";
+ regulator-always-on;
+ regulator-boot-on;
+ regulator-min-microvolt = <1800000>;
+ regulator-max-microvolt = <1800000>;
+
+ regulator-state-mem {
+ regulator-on-in-suspend;
+ regulator-suspend-microvolt = <1800000>;
+ };
+ };
+
+ vcc_3v3: SWITCH_REG1 {
+ regulator-boot-on;
+ regulator-name = "vcc3v3";
+ };
+
+ vcc3v3_sd: SWITCH_REG2 {
+ regulator-name = "vcc3v3_sd";
+ regulator-always-on;
+ regulator-boot-on;
+ };
+ };
+ };
+};
+
+
+&i2c1 {
+ status = "okay";
+};
+
+&i2c2 {
+ status = "okay";
+};
+
+&i2c3 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&i2c3m1_xfer>;
+ status = "okay";
+};
+
+&i2c5 {
+ status = "okay";
+};
+
+&mdio1 {
+ rgmii_phy1: ethernet-phy@0 {
+ compatible = "ethernet-phy-ieee802.3-c22";
+ reg = <0x0>;
+ };
+};
+
+&pinctrl {
+ bt {
+ bt_enable_h: bt-enable-h {
+ rockchip,pins = <0 RK_PC1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ bt_host_wake_l: bt-host-wake-l {
+ rockchip,pins = <0 RK_PB3 RK_FUNC_GPIO &pcfg_pull_down>;
+ };
+
+ bt_wake_l: bt-wake-l {
+ rockchip,pins = <0 RK_PB4 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ leds {
+ user_led_enable_h: user-led-enable-h {
+ rockchip,pins = <0 RK_PD3 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ pmic {
+ pmic_int: pmic_int {
+ rockchip,pins =
+ <0 RK_PA3 RK_FUNC_GPIO &pcfg_pull_up>;
+ };
+ };
+
+ sdio-pwrseq {
+ wifi_enable_h: wifi-enable-h {
+ rockchip,pins = <2 RK_PB1 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+
+ usb {
+ vcc5v0_usb30_host_en_h: vcc5v0-usb30-host-en_h {
+ rockchip,pins = <0 RK_PC5 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+
+ vcc5v0_usb_otg_en_h: vcc5v0-usb-otg-en_h {
+ rockchip,pins = <0 RK_PC6 RK_FUNC_GPIO &pcfg_pull_none>;
+ };
+ };
+};
+
+&pmu_io_domains {
+ status = "okay";
+ pmuio1-supply = <&vcc3v3_pmu>;
+ pmuio2-supply = <&vcc3v3_pmu>;
+ vccio1-supply = <&vccio_acodec>;
+ vccio2-supply = <&vcc_1v8>;
+ vccio3-supply = <&vccio_sd>;
+ vccio4-supply = <&vcc_1v8>;
+ vccio5-supply = <&vcc_3v3>;
+ vccio6-supply = <&vcc_1v8>;
+ vccio7-supply = <&vcc_3v3>;
+};
+
+&sdhci {
+ bus-width = <8>;
+ mmc-hs200-1_8v;
+ non-removable;
+ vmmc-supply = <&vcc_3v3>;
+ vqmmc-supply = <&vcc_1v8>;
+ status = "okay";
+};
+
+&sdmmc0 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cd-gpios = <&gpio0 RK_PA4 GPIO_ACTIVE_LOW>;
+ disable-wp;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc0_bus4 &sdmmc0_clk &sdmmc0_cmd &sdmmc0_det>;
+ sd-uhs-sdr104;
+ vmmc-supply = <&vcc3v3_sd>;
+ vqmmc-supply = <&vccio_sd>;
+ status = "okay";
+};
+
+&sdmmc1 {
+ bus-width = <4>;
+ cap-sd-highspeed;
+ cap-sdio-irq;
+ keep-power-in-suspend;
+ mmc-pwrseq = <&sdio_pwrseq>;
+ vmmc-supply = <&vcc3v3_sys>;
+ vqmmc-supply = <&vcca1v8_pmu>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&sdmmc1_bus4 &sdmmc1_cmd &sdmmc1_clk>;
+ status = "okay";
+};
+
+&tsadc {
+ status = "okay";
+};
+
+&uart0 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart0_xfer>;
+ status = "okay";
+};
+
+&uart1 {
+ pinctrl-names = "default";
+ pinctrl-0 = <&uart1m0_xfer &uart1m0_ctsn>;
+ status = "okay";
+ uart-has-rtscts;
+
+ bluetooth {
+ compatible = "brcm,bcm43438-bt";
+ clocks = <&rk809 1>;
+ clock-names = "lpo";
+ device-wakeup-gpios = <&gpio2 RK_PC1 GPIO_ACTIVE_HIGH>;
+ host-wakeup-gpios = <&gpio2 RK_PC0 GPIO_ACTIVE_HIGH>;
+ shutdown-gpios = <&gpio2 RK_PB7 GPIO_ACTIVE_HIGH>;
+ pinctrl-names = "default";
+ pinctrl-0 = <&bt_host_wake_l &bt_wake_l &bt_enable_h>;
+ vbat-supply = <&vcc3v3_sys>;
+ vddio-supply = <&vcca1v8_pmu>;
+ };
+};
+
+&uart2 {
+ status = "okay";
+};
+
+&usb2phy0_host {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy0_otg {
+ phy-supply = <&vcc5v0_usb_otg>;
+ status = "okay";
+};
+
+&usb2phy1_otg {
+ phy-supply = <&vcc5v0_usb30_host>;
+ status = "okay";
+};
+
+&usb2phy0 {
+ status = "okay";
+};
+
+&usb2phy1 {
+ status = "okay";
+};
+
+&usb_host0_xhci {
+ status = "okay";
+};
+
+&usb_host1_xhci {
+ status = "okay";
+};
+
+&usb_host0_ehci {
+ status = "okay";
+};
+
+&usb_host0_ohci {
+ status = "okay";
+};
--
2.25.1
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply related [flat|nested] 62+ messages in thread* Re: [PATCH v2 7/7] arm64: dts: rockchip: add dts for Firefly Station M2 rk3566
2022-04-29 11:52 ` Peter Geis
(?)
@ 2022-04-30 11:06 ` kernel test robot
-1 siblings, 0 replies; 62+ messages in thread
From: kernel test robot @ 2022-04-30 11:06 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: llvm, kbuild-all, Furkan Kardame, devicetree, linux-arm-kernel,
linux-kernel, Peter Geis
Hi Peter,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
[cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204301929.bZ7P8lrZ-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/8e40f3685ab414fc5e5e003d51b62065a3880b6c
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
git checkout 8e40f3685ab414fc5e5e003d51b62065a3880b6c
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts:566.1-16 Label or path usb_host0_xhci not found
>> Error: arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts:570.1-16 Label or path usb_host1_xhci not found
FATAL ERROR: Syntax error parsing input tree
--
0-DAY CI Kernel Test Service
https://01.org/lkp
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 7/7] arm64: dts: rockchip: add dts for Firefly Station M2 rk3566
@ 2022-04-30 11:06 ` kernel test robot
0 siblings, 0 replies; 62+ messages in thread
From: kernel test robot @ 2022-04-30 11:06 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: llvm, kbuild-all, Furkan Kardame, devicetree, linux-arm-kernel,
linux-kernel, Peter Geis
Hi Peter,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
[cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204301929.bZ7P8lrZ-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/8e40f3685ab414fc5e5e003d51b62065a3880b6c
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
git checkout 8e40f3685ab414fc5e5e003d51b62065a3880b6c
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts:566.1-16 Label or path usb_host0_xhci not found
>> Error: arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts:570.1-16 Label or path usb_host1_xhci not found
FATAL ERROR: Syntax error parsing input tree
--
0-DAY CI Kernel Test Service
https://01.org/lkp
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: [PATCH v2 7/7] arm64: dts: rockchip: add dts for Firefly Station M2 rk3566
@ 2022-04-30 11:06 ` kernel test robot
0 siblings, 0 replies; 62+ messages in thread
From: kernel test robot @ 2022-04-30 11:06 UTC (permalink / raw)
To: Peter Geis, linux-rockchip, Rob Herring, Krzysztof Kozlowski,
Heiko Stuebner
Cc: llvm, kbuild-all, Furkan Kardame, devicetree, linux-arm-kernel,
linux-kernel, Peter Geis
Hi Peter,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on robh/for-next]
[also build test ERROR on arm/for-next arm64/for-next/core clk/clk-next kvmarm/next shawnguo/for-next soc/for-next v5.18-rc4]
[cannot apply to rockchip/for-next xilinx-xlnx/master keystone/next next-20220429]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
base: https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
config: arm64-randconfig-r021-20220428 (https://download.01.org/0day-ci/archive/20220430/202204301929.bZ7P8lrZ-lkp@intel.com/config)
compiler: clang version 15.0.0 (https://github.com/llvm/llvm-project 400775649969b9baf3bc2a510266e7912bb16ae9)
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# install arm64 cross compiling tool for clang build
# apt-get install binutils-aarch64-linux-gnu
# https://github.com/intel-lab-lkp/linux/commit/8e40f3685ab414fc5e5e003d51b62065a3880b6c
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Peter-Geis/Add-support-for-several-new-rk3566-SBCs/20220429-195433
git checkout 8e40f3685ab414fc5e5e003d51b62065a3880b6c
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=clang make.cross W=1 O=build_dir ARCH=arm64 SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> Error: arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts:566.1-16 Label or path usb_host0_xhci not found
>> Error: arch/arm64/boot/dts/rockchip/rk3566-roc-pc.dts:570.1-16 Label or path usb_host1_xhci not found
FATAL ERROR: Syntax error parsing input tree
--
0-DAY CI Kernel Test Service
https://01.org/lkp
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: (subset) [PATCH v2 0/7] Add support for several new rk3566 SBCs
2022-04-29 11:52 ` Peter Geis
(?)
@ 2022-04-30 14:05 ` Heiko Stuebner
-1 siblings, 0 replies; 62+ messages in thread
From: Heiko Stuebner @ 2022-04-30 14:05 UTC (permalink / raw)
To: linux-rockchip, Peter Geis
Cc: Heiko Stuebner, linux-kernel, linux-arm-kernel, devicetree
On Fri, 29 Apr 2022 07:52:45 -0400, Peter Geis wrote:
> The following series adds support for the following single board
> computers:
> - Pine64 Quartz64 Model B
> - Pine64 SoQuartz SoM with RPi CM4IO carrier board
> - Firefly Station M2
>
> Patches 1, 2, and 3 add the requisite dt-bindings.
> Patch 4 adds support for the SFC to the rk356x device tree.
> Patch 5 adds the Quartz64 Model B device tree.
> Patch 6 adds the SoQuartz CM4IO device tree.
> Patch 7 adds the Firefly Station M2 device tree.
>
> [...]
Applied, thanks!
[4/7] arm64: dts: rockchip: add rk356x sfc support
commit: 13e0ee34f39c01948a7bbaab0b3c225d9b00a5bb
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: (subset) [PATCH v2 0/7] Add support for several new rk3566 SBCs
@ 2022-04-30 14:05 ` Heiko Stuebner
0 siblings, 0 replies; 62+ messages in thread
From: Heiko Stuebner @ 2022-04-30 14:05 UTC (permalink / raw)
To: linux-rockchip, Peter Geis
Cc: Heiko Stuebner, linux-kernel, linux-arm-kernel, devicetree
On Fri, 29 Apr 2022 07:52:45 -0400, Peter Geis wrote:
> The following series adds support for the following single board
> computers:
> - Pine64 Quartz64 Model B
> - Pine64 SoQuartz SoM with RPi CM4IO carrier board
> - Firefly Station M2
>
> Patches 1, 2, and 3 add the requisite dt-bindings.
> Patch 4 adds support for the SFC to the rk356x device tree.
> Patch 5 adds the Quartz64 Model B device tree.
> Patch 6 adds the SoQuartz CM4IO device tree.
> Patch 7 adds the Firefly Station M2 device tree.
>
> [...]
Applied, thanks!
[4/7] arm64: dts: rockchip: add rk356x sfc support
commit: 13e0ee34f39c01948a7bbaab0b3c225d9b00a5bb
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: (subset) [PATCH v2 0/7] Add support for several new rk3566 SBCs
@ 2022-04-30 14:05 ` Heiko Stuebner
0 siblings, 0 replies; 62+ messages in thread
From: Heiko Stuebner @ 2022-04-30 14:05 UTC (permalink / raw)
To: linux-rockchip, Peter Geis
Cc: Heiko Stuebner, linux-kernel, linux-arm-kernel, devicetree
On Fri, 29 Apr 2022 07:52:45 -0400, Peter Geis wrote:
> The following series adds support for the following single board
> computers:
> - Pine64 Quartz64 Model B
> - Pine64 SoQuartz SoM with RPi CM4IO carrier board
> - Firefly Station M2
>
> Patches 1, 2, and 3 add the requisite dt-bindings.
> Patch 4 adds support for the SFC to the rk356x device tree.
> Patch 5 adds the Quartz64 Model B device tree.
> Patch 6 adds the SoQuartz CM4IO device tree.
> Patch 7 adds the Firefly Station M2 device tree.
>
> [...]
Applied, thanks!
[4/7] arm64: dts: rockchip: add rk356x sfc support
commit: 13e0ee34f39c01948a7bbaab0b3c225d9b00a5bb
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 62+ messages in thread
* Re: (subset) [PATCH v2 0/7] Add support for several new rk3566 SBCs
2022-04-29 11:52 ` Peter Geis
(?)
@ 2022-05-01 13:05 ` Heiko Stuebner
-1 siblings, 0 replies; 62+ messages in thread
From: Heiko Stuebner @ 2022-05-01 13:05 UTC (permalink / raw)
To: linux-rockchip, Peter Geis
Cc: Heiko Stuebner, linux-kernel, linux-arm-kernel, devicetree
On Fri, 29 Apr 2022 07:52:45 -0400, Peter Geis wrote:
> The following series adds support for the following single board
> computers:
> - Pine64 Quartz64 Model B
> - Pine64 SoQuartz SoM with RPi CM4IO carrier board
> - Firefly Station M2
>
> Patches 1, 2, and 3 add the requisite dt-bindings.
> Patch 4 adds support for the SFC to the rk356x device tree.
> Patch 5 adds the Quartz64 Model B device tree.
> Patch 6 adds the SoQuartz CM4IO device tree.
> Patch 7 adds the Firefly Station M2 device tree.
>
> [...]
Applied, thanks!
[1/7] dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B
commit: c37415f55bdadffe5b4c0e7981e9fc7e8b96beea
[2/7] dt-bindings: arm: rockchip: Add Pine64 SoQuartz SoM
commit: c466828fb3ba8cb7f5c3bf28766da9b70bf9745e
[3/7] dt-bindings: arm: rockchip: Add Firefly Station M2
commit: e52ded5543708e0382f236ce35372a63f4568341
[5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
commit: dcc8c66bef79befa6c9ebe7d7d62b0ce66983c20
[6/7] arm64: dts: rockchip: add SoQuartz CM4IO dts
commit: 5859b5a9c3ac92d831bed164374cb837519524ad
[7/7] arm64: dts: rockchip: add dts for Firefly Station M2 rk3566
commit: 30ac9b4e25d8cece00d32c7419f9d919f55421fe
I've adjusted the styling of comments a bit, also dropped one double
newline as well as fixed the node name for the ethernet-phy for QuartzB.
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: (subset) [PATCH v2 0/7] Add support for several new rk3566 SBCs
@ 2022-05-01 13:05 ` Heiko Stuebner
0 siblings, 0 replies; 62+ messages in thread
From: Heiko Stuebner @ 2022-05-01 13:05 UTC (permalink / raw)
To: linux-rockchip, Peter Geis
Cc: Heiko Stuebner, linux-kernel, linux-arm-kernel, devicetree
On Fri, 29 Apr 2022 07:52:45 -0400, Peter Geis wrote:
> The following series adds support for the following single board
> computers:
> - Pine64 Quartz64 Model B
> - Pine64 SoQuartz SoM with RPi CM4IO carrier board
> - Firefly Station M2
>
> Patches 1, 2, and 3 add the requisite dt-bindings.
> Patch 4 adds support for the SFC to the rk356x device tree.
> Patch 5 adds the Quartz64 Model B device tree.
> Patch 6 adds the SoQuartz CM4IO device tree.
> Patch 7 adds the Firefly Station M2 device tree.
>
> [...]
Applied, thanks!
[1/7] dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B
commit: c37415f55bdadffe5b4c0e7981e9fc7e8b96beea
[2/7] dt-bindings: arm: rockchip: Add Pine64 SoQuartz SoM
commit: c466828fb3ba8cb7f5c3bf28766da9b70bf9745e
[3/7] dt-bindings: arm: rockchip: Add Firefly Station M2
commit: e52ded5543708e0382f236ce35372a63f4568341
[5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
commit: dcc8c66bef79befa6c9ebe7d7d62b0ce66983c20
[6/7] arm64: dts: rockchip: add SoQuartz CM4IO dts
commit: 5859b5a9c3ac92d831bed164374cb837519524ad
[7/7] arm64: dts: rockchip: add dts for Firefly Station M2 rk3566
commit: 30ac9b4e25d8cece00d32c7419f9d919f55421fe
I've adjusted the styling of comments a bit, also dropped one double
newline as well as fixed the node name for the ethernet-phy for QuartzB.
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 62+ messages in thread* Re: (subset) [PATCH v2 0/7] Add support for several new rk3566 SBCs
@ 2022-05-01 13:05 ` Heiko Stuebner
0 siblings, 0 replies; 62+ messages in thread
From: Heiko Stuebner @ 2022-05-01 13:05 UTC (permalink / raw)
To: linux-rockchip, Peter Geis
Cc: Heiko Stuebner, linux-kernel, linux-arm-kernel, devicetree
On Fri, 29 Apr 2022 07:52:45 -0400, Peter Geis wrote:
> The following series adds support for the following single board
> computers:
> - Pine64 Quartz64 Model B
> - Pine64 SoQuartz SoM with RPi CM4IO carrier board
> - Firefly Station M2
>
> Patches 1, 2, and 3 add the requisite dt-bindings.
> Patch 4 adds support for the SFC to the rk356x device tree.
> Patch 5 adds the Quartz64 Model B device tree.
> Patch 6 adds the SoQuartz CM4IO device tree.
> Patch 7 adds the Firefly Station M2 device tree.
>
> [...]
Applied, thanks!
[1/7] dt-bindings: arm: rockchip: Add Pine64 Quartz64 Model B
commit: c37415f55bdadffe5b4c0e7981e9fc7e8b96beea
[2/7] dt-bindings: arm: rockchip: Add Pine64 SoQuartz SoM
commit: c466828fb3ba8cb7f5c3bf28766da9b70bf9745e
[3/7] dt-bindings: arm: rockchip: Add Firefly Station M2
commit: e52ded5543708e0382f236ce35372a63f4568341
[5/7] arm64: dts: rockchip: add Pine64 Quartz64-B device tree
commit: dcc8c66bef79befa6c9ebe7d7d62b0ce66983c20
[6/7] arm64: dts: rockchip: add SoQuartz CM4IO dts
commit: 5859b5a9c3ac92d831bed164374cb837519524ad
[7/7] arm64: dts: rockchip: add dts for Firefly Station M2 rk3566
commit: 30ac9b4e25d8cece00d32c7419f9d919f55421fe
I've adjusted the styling of comments a bit, also dropped one double
newline as well as fixed the node name for the ethernet-phy for QuartzB.
Best regards,
--
Heiko Stuebner <heiko@sntech.de>
_______________________________________________
Linux-rockchip mailing list
Linux-rockchip@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-rockchip
^ permalink raw reply [flat|nested] 62+ messages in thread