* [PATCH 1/2] clk: hisilicon: add CRG driver Hi3521a SoC
[not found] <20220501051020.2432338-1-hanetzer@startmail.com>
@ 2022-05-01 5:10 ` Marty E. Plummer
2022-05-01 8:35 ` Krzysztof Kozlowski
2022-05-01 5:10 ` Marty E. Plummer
1 sibling, 1 reply; 13+ messages in thread
From: Marty E. Plummer @ 2022-05-01 5:10 UTC (permalink / raw)
To: Michael Turquette, Stephen Boyd, Rob Herring, Krzysztof Kozlowski
Cc: Marty E. Plummer, linux-kernel, linux-clk, devicetree
Add CRG driver for Hi3521A SoC. CRG (Clock and Reset Generator) module
generates clock and reset signals used by other module blocks on SoC.
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
---
drivers/clk/hisilicon/Kconfig | 8 ++
drivers/clk/hisilicon/Makefile | 1 +
drivers/clk/hisilicon/crg-hi3521a.c | 141 ++++++++++++++++++++++
include/dt-bindings/clock/hi3521a-clock.h | 34 ++++++
4 files changed, 184 insertions(+)
create mode 100644 drivers/clk/hisilicon/crg-hi3521a.c
create mode 100644 include/dt-bindings/clock/hi3521a-clock.h
diff --git a/drivers/clk/hisilicon/Kconfig b/drivers/clk/hisilicon/Kconfig
index c1ec75aa4ccd..72435c06bf4d 100644
--- a/drivers/clk/hisilicon/Kconfig
+++ b/drivers/clk/hisilicon/Kconfig
@@ -15,6 +15,14 @@ config COMMON_CLK_HI3519
help
Build the clock driver for hi3519.
+config COMMON_CLK_HI3521A
+ tristate "Hi3521a Clock Driver"
+ depends on ARCH_HISI || COMPILE_TEST
+ select RESET_HISI
+ default ARCH_HISI
+ help
+ Build the clock driver for hi3521a.
+
config COMMON_CLK_HI3559A
bool "Hi3559A Clock Driver"
depends on ARCH_HISI || COMPILE_TEST
diff --git a/drivers/clk/hisilicon/Makefile b/drivers/clk/hisilicon/Makefile
index 2978e56cb876..dc27acc5b885 100644
--- a/drivers/clk/hisilicon/Makefile
+++ b/drivers/clk/hisilicon/Makefile
@@ -10,6 +10,7 @@ obj-$(CONFIG_ARCH_HIP04) += clk-hip04.o
obj-$(CONFIG_ARCH_HIX5HD2) += clk-hix5hd2.o
obj-$(CONFIG_COMMON_CLK_HI3516CV300) += crg-hi3516cv300.o
obj-$(CONFIG_COMMON_CLK_HI3519) += clk-hi3519.o
+obj-$(CONFIG_COMMON_CLK_HI3521A) += crg-hi3521a.o
obj-$(CONFIG_COMMON_CLK_HI3559A) += clk-hi3559a.o
obj-$(CONFIG_COMMON_CLK_HI3660) += clk-hi3660.o
obj-$(CONFIG_COMMON_CLK_HI3670) += clk-hi3670.o
diff --git a/drivers/clk/hisilicon/crg-hi3521a.c b/drivers/clk/hisilicon/crg-hi3521a.c
new file mode 100644
index 000000000000..42d8ff440f07
--- /dev/null
+++ b/drivers/clk/hisilicon/crg-hi3521a.c
@@ -0,0 +1,141 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2017-2022 Marty E. Plummer <hanetzer@startmail.com>
+ */
+#include <linux/clk-provider.h>
+#include <linux/kernel.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+
+#include <dt-bindings/clock/hi3521a-clock.h>
+
+#include "clk.h"
+#include "crg.h"
+#include "reset.h"
+
+#define HI3521A_INNER_CLK_OFFSET 64
+#define HI3521A_FIXED_2M 65
+#define HI3521A_FIXED_24M 66
+#define HI3521A_FIXED_50M 67
+#define HI3521A_FIXED_83M 68
+#define HI3521A_FIXED_100M 69
+#define HI3521A_FIXED_150M 70
+#define HI3521A_FIXED_202P5M 71
+#define HI3521A_FIXED_250M 72
+#define HI3521A_SYSAXI_MUX 73
+#define HI3521A_FMC_MUX 74
+#define HI3521A_UART_MUX 75
+#define HI3521A_SP804_CLK 76
+
+#define HI3521A_NR_CLKS 128
+
+static const struct hisi_fixed_rate_clock hi3521a_fixed_rate_clks[] = {
+ { HI3521A_FIXED_2M, "2m", NULL, 0, 2000000, },
+ { HI3521A_FIXED_3M, "3m", NULL, 0, 3000000, },
+ { HI3521A_FIXED_24M, "24m", NULL, 0, 24000000, },
+ { HI3521A_FIXED_50M, "50m", NULL, 0, 50000000, },
+ { HI3521A_FIXED_83M, "83m", NULL, 0, 83000000, },
+ { HI3521A_FIXED_100M, "100m", NULL, 0, 100000000, },
+ { HI3521A_FIXED_150M, "150m", NULL, 0, 150000000, },
+ { HI3521A_FIXED_202P5M, "202p5m", NULL, 0, 202500000, },
+ { HI3521A_FIXED_250M, "250m", NULL, 0, 250000000, },
+};
+
+static const char *const sysaxi_mux_p[] = { "24m", "250m", "202p5m", };
+static const char *const uart_mux_p[] = { "apb", "2m", "24m", };
+static const char *const fmc_mux_p[] = { "24m", "83m", "150m", };
+static const char *const timer_mux_p[] = { "3m", "clk_sp804", };
+
+static const u32 sysaxi_mux_table[] = {0, 1, 2};
+static const u32 uart_mux_table[] = {0, 1, 2};
+static const u32 fmc_mux_table[] = {0, 1, 2};
+static const u32 timer_mux_table[] = {0, 1};
+
+static const struct hisi_mux_clock hi3521a_mux_clks[] = {
+ { HI3521A_APB_CLK, "apb", sysaxi_mux_p, ARRAY_SIZE(sysaxi_mux_p),
+ CLK_SET_RATE_PARENT, 0x34, 12, 2, 0, sysaxi_mux_table, },
+ { HI3521A_UART_MUX, "uart_mux", uart_mux_p, ARRAY_SIZE(uart_mux_p),
+ CLK_SET_RATE_PARENT, 0x84, 18, 2, 0, uart_mux_table, },
+ { HI3521A_FMC_MUX, "fmc_mux", fmc_mux_p, ARRAY_SIZE(fmc_mux_p),
+ CLK_SET_RATE_PARENT, 0x74, 2, 2, 0, fmc_mux_table, },
+};
+
+static const struct hisi_gate_clock hi3521a_gate_clks[] = {
+ { HI3521A_FMC_CLK, "clk_fmc", "fmc_mux", CLK_SET_RATE_PARENT,
+ 0x74, 1, 0, },
+ { HI3521A_ETH_CLK, "clk_eth", NULL, 0, 0x78, 1, 0, },
+ { HI3521A_ETH_MACIF_CLK, "clk_eth_macif", NULL, 0x78, 3, 0, },
+ { HI3521A_DMAC_CLK, "clk_dmac", NULL, 0, 0x80, 5, 0, },
+ { HI3521A_UART0_CLK, "clk_uart0", "uart_mux", CLK_SET_RATE_PARENT,
+ 0x84, 15, 0, },
+ { HI3521A_UART1_CLK, "clk_uart1", "uart_mux", CLK_SET_RATE_PARENT,
+ 0x84, 16, 0, },
+ { HI3521A_UART2_CLK, "clk_uart2", "uart_mux", CLK_SET_RATE_PARENT,
+ 0x84, 17, 0, },
+ { HI3521A_SPI0_CLK, "clk_spi0", "50m", CLK_SET_RATE_PARENT,
+ 0x84, 13, 0, },
+};
+
+static const struct hisi_fixed_factor_clock hi3521a_fixed_factor_clks[] = {
+ { HI3521A_SP804_CLK, "clk_sp804", "apb", 1, 4, CLK_SET_RATE_PARENT },
+};
+
+static void __init hi3521a_crg_init(struct device_node *np)
+{
+ struct hisi_clock_data *clk_data;
+
+ clk_data = hisi_clk_init(np, HI3521A_NR_CLKS);
+ if (!clk_data)
+ return;
+
+ hisi_clk_register_fixed_rate(hi3521a_fixed_rate_clks,
+ ARRAY_SIZE(hi3521a_fixed_rate_clks),
+ clk_data);
+ hisi_clk_register_mux(hi3521a_mux_clks,
+ ARRAY_SIZE(hi3521a_mux_clks),
+ clk_data);
+ hisi_clk_register_gate(hi3521a_gate_clks,
+ ARRAY_SIZE(hi3521a_gate_clks),
+ clk_data);
+ hisi_clk_register_fixed_factor(hi3521a_fixed_factor_clks,
+ ARRAY_SIZE(hi3521a_fixed_factor_clks),
+ clk_data);
+}
+CLK_OF_DECLARE(hi3521a_clk, "hisilicon,hi3521a-crg", hi3521a_crg_init);
+
+#define HI3521A_SYSCTRL_NR_CLKS 16
+
+static const struct hisi_mux_clock hi3521a_sysctrl_mux_clks[] = {
+ { HI3521A_TIMER0_CLK, "clk_timer0", timer_mux_p, ARRAY_SIZE(timer_mux_p),
+ CLK_SET_RATE_PARENT, 0, 16, 1, 0, timer_mux_table, },
+ { HI3521A_TIMER1_CLK, "clk_timer1", timer_mux_p, ARRAY_SIZE(timer_mux_p),
+ CLK_SET_RATE_PARENT, 0, 18, 1, 0, timer_mux_table, },
+ { HI3521A_TIMER2_CLK, "clk_timer2", timer_mux_p, ARRAY_SIZE(timer_mux_p),
+ CLK_SET_RATE_PARENT, 0, 20, 1, 0, timer_mux_table, },
+ { HI3521A_TIMER3_CLK, "clk_timer3", timer_mux_p, ARRAY_SIZE(timer_mux_p),
+ CLK_SET_RATE_PARENT, 0, 22, 1, 0, timer_mux_table, },
+ { HI3521A_TIMER4_CLK, "clk_timer4", timer_mux_p, ARRAY_SIZE(timer_mux_p),
+ CLK_SET_RATE_PARENT, 0, 25, 1, 0, timer_mux_table, },
+ { HI3521A_TIMER5_CLK, "clk_timer5", timer_mux_p, ARRAY_SIZE(timer_mux_p),
+ CLK_SET_RATE_PARENT, 0, 27, 1, 0, timer_mux_table, },
+ { HI3521A_TIMER6_CLK, "clk_timer6", timer_mux_p, ARRAY_SIZE(timer_mux_p),
+ CLK_SET_RATE_PARENT, 0, 29, 1, 0, timer_mux_table, },
+ { HI3521A_TIMER7_CLK, "clk_timer7", timer_mux_p, ARRAY_SIZE(timer_mux_p),
+ CLK_SET_RATE_PARENT, 0, 31, 1, 0, timer_mux_table, },
+};
+
+static void __init hi3521a_sysctrl_init(struct device_node *np)
+{
+ struct hisi_clock_data *clk_data;
+
+ clk_data = hisi_clk_init(np, HI3521A_SYSCTRL_NR_CLKS);
+ if (!clk_data)
+ return;
+
+ hisi_clk_register_mux(hi3521a_sysctrl_mux_clks,
+ ARRAY_SIZE(hi3521a_sysctrl_mux_clks),
+ clk_data);
+}
+CLK_OF_DECLARE(hi3521a_sysctrl, "hisilicon,hi3521a-sysctrl", hi3521a_sysctrl_init);
diff --git a/include/dt-bindings/clock/hi3521a-clock.h b/include/dt-bindings/clock/hi3521a-clock.h
new file mode 100644
index 000000000000..416a08079002
--- /dev/null
+++ b/include/dt-bindings/clock/hi3521a-clock.h
@@ -0,0 +1,34 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later */
+/*
+ * Copyright (C) 2017-2022 Marty E. Plummer <hanetzer@startmail.com>
+ */
+
+#ifndef __DTS_HI3521A_CLOCK_H
+#define __DTS_HI3521A_CLOCK_H
+
+/* clocks provided by the crg */
+#define HI3521A_FIXED_3M 1
+#define HI3521A_FMC_CLK 2
+#define HI3521A_SPI0_CLK 3
+#define HI3521A_UART0_CLK 4
+#define HI3521A_UART1_CLK 5
+#define HI3521A_UART2_CLK 6
+#define HI3521A_DMAC_CLK 7
+#define HI3521A_IR_CLK 8
+#define HI3521A_ETH_CLK 9
+#define HI3521A_ETH_MACIF_CLK 10
+#define HI3521A_USB2_BUS_CLK 11
+#define HI3521A_USB2_PORT_CLK 12
+#define HI3521A_APB_CLK 13
+
+/* clocks provided by the sysctrl */
+#define HI3521A_TIMER0_CLK 1
+#define HI3521A_TIMER1_CLK 2
+#define HI3521A_TIMER2_CLK 3
+#define HI3521A_TIMER3_CLK 4
+#define HI3521A_TIMER4_CLK 5
+#define HI3521A_TIMER5_CLK 6
+#define HI3521A_TIMER6_CLK 7
+#define HI3521A_TIMER7_CLK 8
+
+#endif /* __DTS_HI3521A_CLK_H */
--
2.35.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/2] arm: hisi: enable Hi3521a soc
[not found] <20220501051020.2432338-1-hanetzer@startmail.com>
@ 2022-05-01 5:10 ` Marty E. Plummer
2022-05-01 5:10 ` Marty E. Plummer
1 sibling, 0 replies; 13+ messages in thread
From: Marty E. Plummer @ 2022-05-01 5:10 UTC (permalink / raw)
To: Arnd Bergmann, Olof Johansson, soc, Rob Herring,
Krzysztof Kozlowski, Wei Xu, Russell King
Cc: Marty E. Plummer, linux-arm-kernel, devicetree, linux-kernel
Enable Hisilicon Hi3521A/Hi3520DCV300 SoC. This SoC series includes
hardware mutlimedia codec cores, commonly used in consumer cctv/dvr
security systems and ipcameras. The arm core is a Cortex A7.
Add hi3521a.dtsi and hi3521a-rs-dm290e.dts for RaySharp CCTV systems,
marketed under the name Samsung SDR-B74301N.
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
---
arch/arm/boot/dts/Makefile | 2 ++
arch/arm/mach-hisi/Kconfig | 9 +++++++++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7c16f8a2b738..535cef3b14ab 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -242,6 +242,8 @@ dtb-$(CONFIG_ARCH_GEMINI) += \
gemini-ssi1328.dtb \
gemini-wbd111.dtb \
gemini-wbd222.dtb
+dtb-$(CONFIG_ARCH_HI3521A) += \
+ hi3521a-rs-dm290e.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += \
hi3620-hi4511.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += \
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index 2e980f834a6a..165ffb972157 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -13,6 +13,15 @@ if ARCH_HISI
menu "Hisilicon platform type"
+config ARCH_HI3521A
+ bool "Hisilicon Hi3521a/Hi3520dcv300 family"
+ depends on ARCH_MULTI_V7
+ select CACHE_L2X0
+ select PINCTRL
+ select PINCTRL_SINGLE
+ help
+ Hisilicon Hi3521a/Hi3520dcv300 family
+
config ARCH_HI3xxx
bool "Hisilicon Hi36xx family"
depends on ARCH_MULTI_V7
--
2.35.1
^ permalink raw reply related [flat|nested] 13+ messages in thread
* [PATCH 2/2] arm: hisi: enable Hi3521a soc
@ 2022-05-01 5:10 ` Marty E. Plummer
0 siblings, 0 replies; 13+ messages in thread
From: Marty E. Plummer @ 2022-05-01 5:10 UTC (permalink / raw)
To: Arnd Bergmann, Olof Johansson, soc, Rob Herring,
Krzysztof Kozlowski, Wei Xu, Russell King
Cc: Marty E. Plummer, linux-arm-kernel, devicetree, linux-kernel
Enable Hisilicon Hi3521A/Hi3520DCV300 SoC. This SoC series includes
hardware mutlimedia codec cores, commonly used in consumer cctv/dvr
security systems and ipcameras. The arm core is a Cortex A7.
Add hi3521a.dtsi and hi3521a-rs-dm290e.dts for RaySharp CCTV systems,
marketed under the name Samsung SDR-B74301N.
Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
---
arch/arm/boot/dts/Makefile | 2 ++
arch/arm/mach-hisi/Kconfig | 9 +++++++++
2 files changed, 11 insertions(+)
diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
index 7c16f8a2b738..535cef3b14ab 100644
--- a/arch/arm/boot/dts/Makefile
+++ b/arch/arm/boot/dts/Makefile
@@ -242,6 +242,8 @@ dtb-$(CONFIG_ARCH_GEMINI) += \
gemini-ssi1328.dtb \
gemini-wbd111.dtb \
gemini-wbd222.dtb
+dtb-$(CONFIG_ARCH_HI3521A) += \
+ hi3521a-rs-dm290e.dtb
dtb-$(CONFIG_ARCH_HI3xxx) += \
hi3620-hi4511.dtb
dtb-$(CONFIG_ARCH_HIGHBANK) += \
diff --git a/arch/arm/mach-hisi/Kconfig b/arch/arm/mach-hisi/Kconfig
index 2e980f834a6a..165ffb972157 100644
--- a/arch/arm/mach-hisi/Kconfig
+++ b/arch/arm/mach-hisi/Kconfig
@@ -13,6 +13,15 @@ if ARCH_HISI
menu "Hisilicon platform type"
+config ARCH_HI3521A
+ bool "Hisilicon Hi3521a/Hi3520dcv300 family"
+ depends on ARCH_MULTI_V7
+ select CACHE_L2X0
+ select PINCTRL
+ select PINCTRL_SINGLE
+ help
+ Hisilicon Hi3521a/Hi3520dcv300 family
+
config ARCH_HI3xxx
bool "Hisilicon Hi36xx family"
depends on ARCH_MULTI_V7
--
2.35.1
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm: hisi: enable Hi3521a soc
2022-05-01 5:10 ` Marty E. Plummer
@ 2022-05-01 8:32 ` kernel test robot
-1 siblings, 0 replies; 13+ messages in thread
From: kernel test robot @ 2022-05-01 8:32 UTC (permalink / raw)
To: Marty E. Plummer, Arnd Bergmann, Olof Johansson, soc,
Rob Herring, Krzysztof Kozlowski, Wei Xu, Russell King
Cc: kbuild-all, Marty E. Plummer, linux-arm-kernel, devicetree, linux-kernel
Hi "Marty,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on clk/clk-next]
[also build test ERROR on soc/for-next robh/for-next krzk/for-next krzk-mem-ctrl/for-next v5.18-rc4 next-20220429]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Marty-E-Plummer/clk-hisilicon-add-CRG-driver-Hi3521a-SoC/20220501-141036
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arm-randconfig-r001-20220501 (https://download.01.org/0day-ci/archive/20220501/202205011637.T9bZyDaL-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/6677e373bf0fbceb87ba267fa934df2f4b7dc0ad
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Marty-E-Plummer/clk-hisilicon-add-CRG-driver-Hi3521a-SoC/20220501-141036
git checkout 6677e373bf0fbceb87ba267fa934df2f4b7dc0ad
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> make[2]: *** No rule to make target 'arch/arm/boot/dts/hi3521a-rs-dm290e.dtb', needed by '__build'.
make[2]: Target '__build' not remade because of errors.
--
0-DAY CI Kernel Test Service
https://01.org/lkp
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm: hisi: enable Hi3521a soc
@ 2022-05-01 8:32 ` kernel test robot
0 siblings, 0 replies; 13+ messages in thread
From: kernel test robot @ 2022-05-01 8:32 UTC (permalink / raw)
To: Marty E. Plummer, Arnd Bergmann, Olof Johansson, soc,
Rob Herring, Krzysztof Kozlowski, Wei Xu, Russell King
Cc: kbuild-all, Marty E. Plummer, linux-arm-kernel, devicetree, linux-kernel
Hi "Marty,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on clk/clk-next]
[also build test ERROR on soc/for-next robh/for-next krzk/for-next krzk-mem-ctrl/for-next v5.18-rc4 next-20220429]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch]
url: https://github.com/intel-lab-lkp/linux/commits/Marty-E-Plummer/clk-hisilicon-add-CRG-driver-Hi3521a-SoC/20220501-141036
base: https://git.kernel.org/pub/scm/linux/kernel/git/clk/linux.git clk-next
config: arm-randconfig-r001-20220501 (https://download.01.org/0day-ci/archive/20220501/202205011637.T9bZyDaL-lkp@intel.com/config)
compiler: arm-linux-gnueabi-gcc (GCC) 11.3.0
reproduce (this is a W=1 build):
wget https://raw.githubusercontent.com/intel/lkp-tests/master/sbin/make.cross -O ~/bin/make.cross
chmod +x ~/bin/make.cross
# https://github.com/intel-lab-lkp/linux/commit/6677e373bf0fbceb87ba267fa934df2f4b7dc0ad
git remote add linux-review https://github.com/intel-lab-lkp/linux
git fetch --no-tags linux-review Marty-E-Plummer/clk-hisilicon-add-CRG-driver-Hi3521a-SoC/20220501-141036
git checkout 6677e373bf0fbceb87ba267fa934df2f4b7dc0ad
# save the config file
mkdir build_dir && cp config build_dir/.config
COMPILER_INSTALL_PATH=$HOME/0day COMPILER=gcc-11.3.0 make.cross W=1 O=build_dir ARCH=arm SHELL=/bin/bash
If you fix the issue, kindly add following tag as appropriate
Reported-by: kernel test robot <lkp@intel.com>
All errors (new ones prefixed by >>):
>> make[2]: *** No rule to make target 'arch/arm/boot/dts/hi3521a-rs-dm290e.dtb', needed by '__build'.
make[2]: Target '__build' not remade because of errors.
--
0-DAY CI Kernel Test Service
https://01.org/lkp
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] clk: hisilicon: add CRG driver Hi3521a SoC
2022-05-01 5:10 ` [PATCH 1/2] clk: hisilicon: add CRG driver Hi3521a SoC Marty E. Plummer
@ 2022-05-01 8:35 ` Krzysztof Kozlowski
2022-05-01 11:36 ` Marty E. Plummer
0 siblings, 1 reply; 13+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-01 8:35 UTC (permalink / raw)
To: Marty E. Plummer, Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski
Cc: linux-kernel, linux-clk, devicetree
On 01/05/2022 07:10, Marty E. Plummer wrote:
> Add CRG driver for Hi3521A SoC. CRG (Clock and Reset Generator) module
> generates clock and reset signals used by other module blocks on SoC.
>
>
(...)
> + return;
> +
> + hisi_clk_register_mux(hi3521a_sysctrl_mux_clks,
> + ARRAY_SIZE(hi3521a_sysctrl_mux_clks),
> + clk_data);
> +}
> +CLK_OF_DECLARE(hi3521a_sysctrl, "hisilicon,hi3521a-sysctrl", hi3521a_sysctrl_init);
Missing bindings.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm: hisi: enable Hi3521a soc
2022-05-01 5:10 ` Marty E. Plummer
@ 2022-05-01 8:36 ` Krzysztof Kozlowski
-1 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-01 8:36 UTC (permalink / raw)
To: Marty E. Plummer, Arnd Bergmann, Olof Johansson, soc,
Rob Herring, Krzysztof Kozlowski, Wei Xu, Russell King
Cc: linux-arm-kernel, devicetree, linux-kernel
On 01/05/2022 07:10, Marty E. Plummer wrote:
> Enable Hisilicon Hi3521A/Hi3520DCV300 SoC. This SoC series includes
> hardware mutlimedia codec cores, commonly used in consumer cctv/dvr
> security systems and ipcameras. The arm core is a Cortex A7.
>
> Add hi3521a.dtsi and hi3521a-rs-dm290e.dts for RaySharp CCTV systems,
> marketed under the name Samsung SDR-B74301N.
Where?
>
> Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> ---
> arch/arm/boot/dts/Makefile | 2 ++
> arch/arm/mach-hisi/Kconfig | 9 +++++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 7c16f8a2b738..535cef3b14ab 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -242,6 +242,8 @@ dtb-$(CONFIG_ARCH_GEMINI) += \
> gemini-ssi1328.dtb \
> gemini-wbd111.dtb \
> gemini-wbd222.dtb
> +dtb-$(CONFIG_ARCH_HI3521A) += \
> + hi3521a-rs-dm290e.dtb
There is no such DTS.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm: hisi: enable Hi3521a soc
@ 2022-05-01 8:36 ` Krzysztof Kozlowski
0 siblings, 0 replies; 13+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-01 8:36 UTC (permalink / raw)
To: Marty E. Plummer, Arnd Bergmann, Olof Johansson, soc,
Rob Herring, Krzysztof Kozlowski, Wei Xu, Russell King
Cc: linux-arm-kernel, devicetree, linux-kernel
On 01/05/2022 07:10, Marty E. Plummer wrote:
> Enable Hisilicon Hi3521A/Hi3520DCV300 SoC. This SoC series includes
> hardware mutlimedia codec cores, commonly used in consumer cctv/dvr
> security systems and ipcameras. The arm core is a Cortex A7.
>
> Add hi3521a.dtsi and hi3521a-rs-dm290e.dts for RaySharp CCTV systems,
> marketed under the name Samsung SDR-B74301N.
Where?
>
> Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> ---
> arch/arm/boot/dts/Makefile | 2 ++
> arch/arm/mach-hisi/Kconfig | 9 +++++++++
> 2 files changed, 11 insertions(+)
>
> diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> index 7c16f8a2b738..535cef3b14ab 100644
> --- a/arch/arm/boot/dts/Makefile
> +++ b/arch/arm/boot/dts/Makefile
> @@ -242,6 +242,8 @@ dtb-$(CONFIG_ARCH_GEMINI) += \
> gemini-ssi1328.dtb \
> gemini-wbd111.dtb \
> gemini-wbd222.dtb
> +dtb-$(CONFIG_ARCH_HI3521A) += \
> + hi3521a-rs-dm290e.dtb
There is no such DTS.
Best regards,
Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] clk: hisilicon: add CRG driver Hi3521a SoC
2022-05-01 8:35 ` Krzysztof Kozlowski
@ 2022-05-01 11:36 ` Marty E. Plummer
2022-05-03 9:41 ` Krzysztof Kozlowski
0 siblings, 1 reply; 13+ messages in thread
From: Marty E. Plummer @ 2022-05-01 11:36 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, linux-kernel, linux-clk, devicetree
On Sun, May 01, 2022 at 10:35:37AM +0200, Krzysztof Kozlowski wrote:
> On 01/05/2022 07:10, Marty E. Plummer wrote:
> > Add CRG driver for Hi3521A SoC. CRG (Clock and Reset Generator) module
> > generates clock and reset signals used by other module blocks on SoC.
> >
> >
> (...)
>
> > + return;
> > +
> > + hisi_clk_register_mux(hi3521a_sysctrl_mux_clks,
> > + ARRAY_SIZE(hi3521a_sysctrl_mux_clks),
> > + clk_data);
> > +}
> > +CLK_OF_DECLARE(hi3521a_sysctrl, "hisilicon,hi3521a-sysctrl", hi3521a_sysctrl_init);
> Missing bindings.
>
Assume you mean the Documentation/dt/binding/... file? Will do. I
probably should have prefixed it with RFC, as I'm mostly hoping to get
the attention of the hisi people to see what's the deal with the mtd
reads being borked.
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm: hisi: enable Hi3521a soc
2022-05-01 8:36 ` Krzysztof Kozlowski
@ 2022-05-01 11:37 ` Marty E. Plummer
-1 siblings, 0 replies; 13+ messages in thread
From: Marty E. Plummer @ 2022-05-01 11:37 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Arnd Bergmann, Olof Johansson, soc, Rob Herring,
Krzysztof Kozlowski, Wei Xu, Russell King, linux-arm-kernel,
devicetree, linux-kernel
On Sun, May 01, 2022 at 10:36:17AM +0200, Krzysztof Kozlowski wrote:
> On 01/05/2022 07:10, Marty E. Plummer wrote:
> > Enable Hisilicon Hi3521A/Hi3520DCV300 SoC. This SoC series includes
> > hardware mutlimedia codec cores, commonly used in consumer cctv/dvr
> > security systems and ipcameras. The arm core is a Cortex A7.
> >
> > Add hi3521a.dtsi and hi3521a-rs-dm290e.dts for RaySharp CCTV systems,
> > marketed under the name Samsung SDR-B74301N.
>
> Where?
>
> >
> > Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> > ---
> > arch/arm/boot/dts/Makefile | 2 ++
> > arch/arm/mach-hisi/Kconfig | 9 +++++++++
> > 2 files changed, 11 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 7c16f8a2b738..535cef3b14ab 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -242,6 +242,8 @@ dtb-$(CONFIG_ARCH_GEMINI) += \
> > gemini-ssi1328.dtb \
> > gemini-wbd111.dtb \
> > gemini-wbd222.dtb
> > +dtb-$(CONFIG_ARCH_HI3521A) += \
> > + hi3521a-rs-dm290e.dtb
>
> There is no such DTS.
>
Ugh. Sorry, I've been fighting this for a while and must have missed it
out of exaustion. will resend.
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 2/2] arm: hisi: enable Hi3521a soc
@ 2022-05-01 11:37 ` Marty E. Plummer
0 siblings, 0 replies; 13+ messages in thread
From: Marty E. Plummer @ 2022-05-01 11:37 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Arnd Bergmann, Olof Johansson, soc, Rob Herring,
Krzysztof Kozlowski, Wei Xu, Russell King, linux-arm-kernel,
devicetree, linux-kernel
On Sun, May 01, 2022 at 10:36:17AM +0200, Krzysztof Kozlowski wrote:
> On 01/05/2022 07:10, Marty E. Plummer wrote:
> > Enable Hisilicon Hi3521A/Hi3520DCV300 SoC. This SoC series includes
> > hardware mutlimedia codec cores, commonly used in consumer cctv/dvr
> > security systems and ipcameras. The arm core is a Cortex A7.
> >
> > Add hi3521a.dtsi and hi3521a-rs-dm290e.dts for RaySharp CCTV systems,
> > marketed under the name Samsung SDR-B74301N.
>
> Where?
>
> >
> > Signed-off-by: Marty E. Plummer <hanetzer@startmail.com>
> > ---
> > arch/arm/boot/dts/Makefile | 2 ++
> > arch/arm/mach-hisi/Kconfig | 9 +++++++++
> > 2 files changed, 11 insertions(+)
> >
> > diff --git a/arch/arm/boot/dts/Makefile b/arch/arm/boot/dts/Makefile
> > index 7c16f8a2b738..535cef3b14ab 100644
> > --- a/arch/arm/boot/dts/Makefile
> > +++ b/arch/arm/boot/dts/Makefile
> > @@ -242,6 +242,8 @@ dtb-$(CONFIG_ARCH_GEMINI) += \
> > gemini-ssi1328.dtb \
> > gemini-wbd111.dtb \
> > gemini-wbd222.dtb
> > +dtb-$(CONFIG_ARCH_HI3521A) += \
> > + hi3521a-rs-dm290e.dtb
>
> There is no such DTS.
>
Ugh. Sorry, I've been fighting this for a while and must have missed it
out of exaustion. will resend.
>
> Best regards,
> Krzysztof
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] clk: hisilicon: add CRG driver Hi3521a SoC
2022-05-01 11:36 ` Marty E. Plummer
@ 2022-05-03 9:41 ` Krzysztof Kozlowski
2022-05-03 10:08 ` Marty E. Plummer
0 siblings, 1 reply; 13+ messages in thread
From: Krzysztof Kozlowski @ 2022-05-03 9:41 UTC (permalink / raw)
To: Marty E. Plummer
Cc: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, linux-kernel, linux-clk, devicetree
On 01/05/2022 13:36, Marty E. Plummer wrote:
> On Sun, May 01, 2022 at 10:35:37AM +0200, Krzysztof Kozlowski wrote:
>> On 01/05/2022 07:10, Marty E. Plummer wrote:
>>> Add CRG driver for Hi3521A SoC. CRG (Clock and Reset Generator) module
>>> generates clock and reset signals used by other module blocks on SoC.
>>>
>>>
>> (...)
>>
>>> + return;
>>> +
>>> + hisi_clk_register_mux(hi3521a_sysctrl_mux_clks,
>>> + ARRAY_SIZE(hi3521a_sysctrl_mux_clks),
>>> + clk_data);
>>> +}
>>> +CLK_OF_DECLARE(hi3521a_sysctrl, "hisilicon,hi3521a-sysctrl", hi3521a_sysctrl_init);
>> Missing bindings.
>>
> Assume you mean the Documentation/dt/binding/... file? Will do. I
> probably should have prefixed it with RFC, as I'm mostly hoping to get
> the attention of the hisi people to see what's the deal with the mtd
> reads being borked.
Then just don't Cc devicetree folks and put in cover letter disclaimer
that this was intentionally omitted and will be later fixed.
It is a waste of time of reviewers to look/filter/organize such email,
if it is intentionally not for us.
Best regards,
Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
* Re: [PATCH 1/2] clk: hisilicon: add CRG driver Hi3521a SoC
2022-05-03 9:41 ` Krzysztof Kozlowski
@ 2022-05-03 10:08 ` Marty E. Plummer
0 siblings, 0 replies; 13+ messages in thread
From: Marty E. Plummer @ 2022-05-03 10:08 UTC (permalink / raw)
To: Krzysztof Kozlowski
Cc: Michael Turquette, Stephen Boyd, Rob Herring,
Krzysztof Kozlowski, linux-kernel, linux-clk, devicetree
On Tue, May 03, 2022 at 11:41:49AM +0200, Krzysztof Kozlowski wrote:
> On 01/05/2022 13:36, Marty E. Plummer wrote:
> > On Sun, May 01, 2022 at 10:35:37AM +0200, Krzysztof Kozlowski wrote:
> >> On 01/05/2022 07:10, Marty E. Plummer wrote:
> >>> Add CRG driver for Hi3521A SoC. CRG (Clock and Reset Generator) module
> >>> generates clock and reset signals used by other module blocks on SoC.
> >>>
> >>>
> >> (...)
> >>
> >>> + return;
> >>> +
> >>> + hisi_clk_register_mux(hi3521a_sysctrl_mux_clks,
> >>> + ARRAY_SIZE(hi3521a_sysctrl_mux_clks),
> >>> + clk_data);
> >>> +}
> >>> +CLK_OF_DECLARE(hi3521a_sysctrl, "hisilicon,hi3521a-sysctrl", hi3521a_sysctrl_init);
> >> Missing bindings.
> >>
> > Assume you mean the Documentation/dt/binding/... file? Will do. I
> > probably should have prefixed it with RFC, as I'm mostly hoping to get
> > the attention of the hisi people to see what's the deal with the mtd
> > reads being borked.
>
> Then just don't Cc devicetree folks and put in cover letter disclaimer
> that this was intentionally omitted and will be later fixed.
>
Yes, I should have disclaimered it, but I didn't intentionally cc dt
folks, just what getmaintainer popped out.
> It is a waste of time of reviewers to look/filter/organize such email,
> if it is intentionally not for us.
>
> Best regards,
> Krzysztof
^ permalink raw reply [flat|nested] 13+ messages in thread
end of thread, other threads:[~2022-05-03 10:08 UTC | newest]
Thread overview: 13+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
[not found] <20220501051020.2432338-1-hanetzer@startmail.com>
2022-05-01 5:10 ` [PATCH 1/2] clk: hisilicon: add CRG driver Hi3521a SoC Marty E. Plummer
2022-05-01 8:35 ` Krzysztof Kozlowski
2022-05-01 11:36 ` Marty E. Plummer
2022-05-03 9:41 ` Krzysztof Kozlowski
2022-05-03 10:08 ` Marty E. Plummer
2022-05-01 5:10 ` [PATCH 2/2] arm: hisi: enable Hi3521a soc Marty E. Plummer
2022-05-01 5:10 ` Marty E. Plummer
2022-05-01 8:32 ` kernel test robot
2022-05-01 8:32 ` kernel test robot
2022-05-01 8:36 ` Krzysztof Kozlowski
2022-05-01 8:36 ` Krzysztof Kozlowski
2022-05-01 11:37 ` Marty E. Plummer
2022-05-01 11:37 ` Marty E. Plummer
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