* [PATCH 0/6] Add OPP, TSU, RSPI and SPI Multi I/O Bus controller node
@ 2022-05-01 11:29 Biju Das
2022-05-01 11:29 ` [PATCH 1/6] arm64: dts: renesas: r9a07g043: Add " Biju Das
` (5 more replies)
0 siblings, 6 replies; 14+ messages in thread
From: Biju Das @ 2022-05-01 11:29 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
This patch series aims to add support for OPP, TSU, RSPI and
SPI Multi I/O Bus controller on RZ/G2UL SoC.
This patch series depend upon [1]
[1] https://patchwork.kernel.org/project/linux-renesas-soc/list/?series=637371
Biju Das (6):
arm64: dts: renesas: r9a07g043: Add SPI Multi I/O Bus controller node
arm64: dts: renesas: r9a07g043: Add RSPI{0,1,2} nodes
arm64: dts: renesas: r9a07g043: Add OPP table
arm64: dts: renesas: r9a07g043: Add TSU node
arm64: dts: renesas: r9a07g043: Create thermal zone to support IPA
arm64: dts: renesas: r9a07g043: Add ADC node
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 144 ++++++++++++++++++++-
1 file changed, 141 insertions(+), 3 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 14+ messages in thread
* [PATCH 1/6] arm64: dts: renesas: r9a07g043: Add SPI Multi I/O Bus controller node
2022-05-01 11:29 [PATCH 0/6] Add OPP, TSU, RSPI and SPI Multi I/O Bus controller node Biju Das
@ 2022-05-01 11:29 ` Biju Das
2022-05-02 16:00 ` Geert Uytterhoeven
2022-05-01 11:29 ` [PATCH 2/6] arm64: dts: renesas: r9a07g043: Add RSPI{0,1,2} nodes Biju Das
` (4 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-05-01 11:29 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add SPI Multi I/O Bus controller node to R9A07G043 (RZ/G2UL) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 15335e9ca06b..55bf4b72304f 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -418,12 +418,20 @@ adc: adc@10059000 {
};
sbc: spi@10060000 {
+ compatible = "renesas,r9a07g043-rpc-if",
+ "renesas,rzg2l-rpc-if";
reg = <0 0x10060000 0 0x10000>,
<0 0x20000000 0 0x10000000>,
<0 0x10070000 0 0x10000>;
+ reg-names = "regs", "dirmap", "wbuf";
+ interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
+ clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>,
+ <&cpg CPG_MOD R9A07G043_SPI_CLK>;
+ resets = <&cpg R9A07G043_SPI_RST>;
+ power-domains = <&cpg>;
#address-cells = <1>;
#size-cells = <0>;
- /* place holder */
+ status = "disabled";
};
cpg: clock-controller@11010000 {
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 2/6] arm64: dts: renesas: r9a07g043: Add RSPI{0,1,2} nodes
2022-05-01 11:29 [PATCH 0/6] Add OPP, TSU, RSPI and SPI Multi I/O Bus controller node Biju Das
2022-05-01 11:29 ` [PATCH 1/6] arm64: dts: renesas: r9a07g043: Add " Biju Das
@ 2022-05-01 11:29 ` Biju Das
2022-05-02 16:09 ` Geert Uytterhoeven
2022-05-01 11:29 ` [PATCH 3/6] arm64: dts: renesas: r9a07g043: Add OPP table Biju Das
` (3 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-05-01 11:29 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add RSPI{0,1,2} nodes to R9A07G043 (RZ/G2UL) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 43 +++++++++++++++++++++-
1 file changed, 42 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 55bf4b72304f..4d17c8814a8d 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -158,11 +158,52 @@ ssi3: ssi@1004a800 {
status = "disabled";
};
+ spi0: spi@1004ac00 {
+ compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
+ reg = <0 0x1004ac00 0 0x400>;
+ interrupts = <GIC_SPI 415 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 413 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 414 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&cpg CPG_MOD R9A07G043_RSPI0_CLKB>;
+ resets = <&cpg R9A07G043_RSPI0_RST>;
+ power-domains = <&cpg>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
+ };
+
spi1: spi@1004b000 {
+ compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
reg = <0 0x1004b000 0 0x400>;
+ interrupts = <GIC_SPI 418 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 416 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 417 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&cpg CPG_MOD R9A07G043_RSPI1_CLKB>;
+ resets = <&cpg R9A07G043_RSPI1_RST>;
+ power-domains = <&cpg>;
+ num-cs = <1>;
#address-cells = <1>;
#size-cells = <0>;
- /* place holder */
+ status = "disabled";
+ };
+
+ spi2: spi@1004b400 {
+ compatible = "renesas,r9a07g043-rspi", "renesas,rspi-rz";
+ reg = <0 0x1004b400 0 0x400>;
+ interrupts = <GIC_SPI 421 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 419 IRQ_TYPE_LEVEL_HIGH>,
+ <GIC_SPI 420 IRQ_TYPE_LEVEL_HIGH>;
+ interrupt-names = "error", "rx", "tx";
+ clocks = <&cpg CPG_MOD R9A07G043_RSPI2_CLKB>;
+ resets = <&cpg R9A07G043_RSPI2_RST>;
+ power-domains = <&cpg>;
+ num-cs = <1>;
+ #address-cells = <1>;
+ #size-cells = <0>;
+ status = "disabled";
};
scif0: serial@1004b800 {
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 3/6] arm64: dts: renesas: r9a07g043: Add OPP table
2022-05-01 11:29 [PATCH 0/6] Add OPP, TSU, RSPI and SPI Multi I/O Bus controller node Biju Das
2022-05-01 11:29 ` [PATCH 1/6] arm64: dts: renesas: r9a07g043: Add " Biju Das
2022-05-01 11:29 ` [PATCH 2/6] arm64: dts: renesas: r9a07g043: Add RSPI{0,1,2} nodes Biju Das
@ 2022-05-01 11:29 ` Biju Das
2022-05-02 16:57 ` Geert Uytterhoeven
2022-05-01 11:29 ` [PATCH 4/6] arm64: dts: renesas: r9a07g043: Add TSU node Biju Das
` (2 subsequent siblings)
5 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-05-01 11:29 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add OPP table for RZ/G2UL SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 28 ++++++++++++++++++++++
1 file changed, 28 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 4d17c8814a8d..49f549587bdf 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -42,6 +42,33 @@ extal_clk: extal-clk {
clock-frequency = <0>;
};
+ cluster0_opp: opp-table-0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-125000000 {
+ opp-hz = /bits/ 64 <125000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-250000000 {
+ opp-hz = /bits/ 64 <250000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ };
+ opp-1000000000 {
+ opp-hz = /bits/ 64 <1000000000>;
+ opp-microvolt = <1100000>;
+ clock-latency-ns = <300000>;
+ opp-suspend;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -53,6 +80,7 @@ cpu0: cpu@0 {
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
+ operating-points-v2 = <&cluster0_opp>;
};
L3_CA55: cache-controller-0 {
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 4/6] arm64: dts: renesas: r9a07g043: Add TSU node
2022-05-01 11:29 [PATCH 0/6] Add OPP, TSU, RSPI and SPI Multi I/O Bus controller node Biju Das
` (2 preceding siblings ...)
2022-05-01 11:29 ` [PATCH 3/6] arm64: dts: renesas: r9a07g043: Add OPP table Biju Das
@ 2022-05-01 11:29 ` Biju Das
2022-05-02 16:10 ` Geert Uytterhoeven
2022-05-01 11:29 ` [PATCH 5/6] arm64: dts: renesas: r9a07g043: Create thermal zone to support IPA Biju Das
2022-05-01 11:29 ` [PATCH 6/6] arm64: dts: renesas: r9a07g043: Add ADC node Biju Das
5 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-05-01 11:29 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add TSU node to RZ/G2UL SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 26 ++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 49f549587bdf..c0a57055af49 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -486,6 +486,16 @@ adc: adc@10059000 {
/* place holder */
};
+ tsu: thermal@10059400 {
+ compatible = "renesas,r9a07g043-tsu",
+ "renesas,rzg2l-tsu";
+ reg = <0 0x10059400 0 0x400>;
+ clocks = <&cpg CPG_MOD R9A07G043_TSU_PCLK>;
+ resets = <&cpg R9A07G043_TSU_PRESETN>;
+ power-domains = <&cpg>;
+ #thermal-sensor-cells = <1>;
+ };
+
sbc: spi@10060000 {
compatible = "renesas,r9a07g043-rpc-if",
"renesas,rzg2l-rpc-if";
@@ -834,6 +844,22 @@ ostm2: timer@12801800 {
};
};
+ thermal-zones {
+ cpu-thermal {
+ polling-delay-passive = <250>;
+ polling-delay = <1000>;
+ thermal-sensors = <&tsu 0>;
+
+ trips {
+ sensor_crit: sensor-crit {
+ temperature = <125000>;
+ hysteresis = <1000>;
+ type = "critical";
+ };
+ };
+ };
+ };
+
timer {
compatible = "arm,armv8-timer";
interrupts-extended = <&gic GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(1) | IRQ_TYPE_LEVEL_LOW)>,
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 5/6] arm64: dts: renesas: r9a07g043: Create thermal zone to support IPA
2022-05-01 11:29 [PATCH 0/6] Add OPP, TSU, RSPI and SPI Multi I/O Bus controller node Biju Das
` (3 preceding siblings ...)
2022-05-01 11:29 ` [PATCH 4/6] arm64: dts: renesas: r9a07g043: Add TSU node Biju Das
@ 2022-05-01 11:29 ` Biju Das
2022-05-02 16:14 ` Geert Uytterhoeven
2022-05-01 11:29 ` [PATCH 6/6] arm64: dts: renesas: r9a07g043: Add ADC node Biju Das
5 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-05-01 11:29 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Setup a thermal zone driven by SoC temperature sensor.
Create passive trip points and bind them to CPUFreq cooling
device that supports power extension.
Based on the work done by Dien Pham <dien.pham.ry@renesas.com>
and others for r8a77990 SoC.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index c0a57055af49..55081071293f 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -77,6 +77,7 @@ cpu0: cpu@0 {
compatible = "arm,cortex-a55";
reg = <0>;
device_type = "cpu";
+ #cooling-cells = <2>;
next-level-cache = <&L3_CA55>;
enable-method = "psci";
clocks = <&cpg CPG_CORE R9A07G043_CLK_I>;
@@ -849,6 +850,15 @@ cpu-thermal {
polling-delay-passive = <250>;
polling-delay = <1000>;
thermal-sensors = <&tsu 0>;
+ sustainable-power = <717>;
+
+ cooling-maps {
+ map0 {
+ trip = <&target>;
+ cooling-device = <&cpu0 0 2>;
+ contribution = <1024>;
+ };
+ };
trips {
sensor_crit: sensor-crit {
@@ -856,6 +866,12 @@ sensor_crit: sensor-crit {
hysteresis = <1000>;
type = "critical";
};
+
+ target: trip-point {
+ temperature = <100000>;
+ hysteresis = <1000>;
+ type = "passive";
+ };
};
};
};
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PATCH 6/6] arm64: dts: renesas: r9a07g043: Add ADC node
2022-05-01 11:29 [PATCH 0/6] Add OPP, TSU, RSPI and SPI Multi I/O Bus controller node Biju Das
` (4 preceding siblings ...)
2022-05-01 11:29 ` [PATCH 5/6] arm64: dts: renesas: r9a07g043: Create thermal zone to support IPA Biju Das
@ 2022-05-01 11:29 ` Biju Das
5 siblings, 0 replies; 14+ messages in thread
From: Biju Das @ 2022-05-01 11:29 UTC (permalink / raw)
To: Rob Herring, Krzysztof Kozlowski
Cc: Biju Das, Geert Uytterhoeven, Magnus Damm, linux-renesas-soc,
devicetree, Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Add ADC node to R9A07G043 (RZ/G2UL) SoC DTSI.
Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
---
This patch depend upon[1]
[1] https://patchwork.kernel.org/project/linux-renesas-soc/patch/20220501081523.22479-1-biju.das.jz@bp.renesas.com/
---
arch/arm64/boot/dts/renesas/r9a07g043.dtsi | 21 ++++++++++++++++++++-
1 file changed, 20 insertions(+), 1 deletion(-)
diff --git a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
index 55081071293f..15086f5945a2 100644
--- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
+++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
@@ -483,8 +483,27 @@ i2c3: i2c@10058c00 {
};
adc: adc@10059000 {
+ compatible = "renesas,r9a07g043-adc";
reg = <0 0x10059000 0 0x400>;
- /* place holder */
+ interrupts = <GIC_SPI 347 IRQ_TYPE_EDGE_RISING>;
+ clocks = <&cpg CPG_MOD R9A07G043_ADC_ADCLK>,
+ <&cpg CPG_MOD R9A07G043_ADC_PCLK>;
+ clock-names = "adclk", "pclk";
+ resets = <&cpg R9A07G043_ADC_PRESETN>,
+ <&cpg R9A07G043_ADC_ADRST_N>;
+ reset-names = "presetn", "adrst-n";
+ power-domains = <&cpg>;
+ status = "disabled";
+
+ #address-cells = <1>;
+ #size-cells = <0>;
+
+ channel@0 {
+ reg = <0>;
+ };
+ channel@1 {
+ reg = <1>;
+ };
};
tsu: thermal@10059400 {
--
2.25.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PATCH 1/6] arm64: dts: renesas: r9a07g043: Add SPI Multi I/O Bus controller node
2022-05-01 11:29 ` [PATCH 1/6] arm64: dts: renesas: r9a07g043: Add " Biju Das
@ 2022-05-02 16:00 ` Geert Uytterhoeven
2022-05-02 16:18 ` Biju Das
0 siblings, 1 reply; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-05-02 16:00 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Biju,
On Sun, May 1, 2022 at 1:29 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add SPI Multi I/O Bus controller node to R9A07G043 (RZ/G2UL) SoC DTSI.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Thanks for your patch!
> --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> @@ -418,12 +418,20 @@ adc: adc@10059000 {
> };
>
> sbc: spi@10060000 {
> + compatible = "renesas,r9a07g043-rpc-if",
> + "renesas,rzg2l-rpc-if";
> reg = <0 0x10060000 0 0x10000>,
> <0 0x20000000 0 0x10000000>,
> <0 0x10070000 0 0x10000>;
> + reg-names = "regs", "dirmap", "wbuf";
> + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
LGTM, but this interrupt is not documented in the RZ/G2UL Hardware
User's Manual (Rev. 0.51 and 1.00)?
> + clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>,
> + <&cpg CPG_MOD R9A07G043_SPI_CLK>;
> + resets = <&cpg R9A07G043_SPI_RST>;
> + power-domains = <&cpg>;
> #address-cells = <1>;
> #size-cells = <0>;
> - /* place holder */
> + status = "disabled";
> };
>
> cpg: clock-controller@11010000 {
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 2/6] arm64: dts: renesas: r9a07g043: Add RSPI{0,1,2} nodes
2022-05-01 11:29 ` [PATCH 2/6] arm64: dts: renesas: r9a07g043: Add RSPI{0,1,2} nodes Biju Das
@ 2022-05-02 16:09 ` Geert Uytterhoeven
0 siblings, 0 replies; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-05-02 16:09 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Sun, May 1, 2022 at 1:29 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add RSPI{0,1,2} nodes to R9A07G043 (RZ/G2UL) SoC DTSI.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 4/6] arm64: dts: renesas: r9a07g043: Add TSU node
2022-05-01 11:29 ` [PATCH 4/6] arm64: dts: renesas: r9a07g043: Add TSU node Biju Das
@ 2022-05-02 16:10 ` Geert Uytterhoeven
0 siblings, 0 replies; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-05-02 16:10 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Sun, May 1, 2022 at 1:29 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add TSU node to RZ/G2UL SoC DTSI.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 5/6] arm64: dts: renesas: r9a07g043: Create thermal zone to support IPA
2022-05-01 11:29 ` [PATCH 5/6] arm64: dts: renesas: r9a07g043: Create thermal zone to support IPA Biju Das
@ 2022-05-02 16:14 ` Geert Uytterhoeven
0 siblings, 0 replies; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-05-02 16:14 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Sun, May 1, 2022 at 1:29 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Setup a thermal zone driven by SoC temperature sensor.
> Create passive trip points and bind them to CPUFreq cooling
> device that supports power extension.
>
> Based on the work done by Dien Pham <dien.pham.ry@renesas.com>
> and others for r8a77990 SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
LGTM, so
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
* RE: [PATCH 1/6] arm64: dts: renesas: r9a07g043: Add SPI Multi I/O Bus controller node
2022-05-02 16:00 ` Geert Uytterhoeven
@ 2022-05-02 16:18 ` Biju Das
2022-05-02 16:53 ` Geert Uytterhoeven
0 siblings, 1 reply; 14+ messages in thread
From: Biju Das @ 2022-05-02 16:18 UTC (permalink / raw)
To: Geert Uytterhoeven
Cc: Rob Herring, Krzysztof Kozlowski, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Geert Uytterhoeven,
Thanks for the feedback.
> Subject: Re: [PATCH 1/6] arm64: dts: renesas: r9a07g043: Add SPI Multi I/O
> Bus controller node
>
> Hi Biju,
>
> On Sun, May 1, 2022 at 1:29 PM Biju Das <biju.das.jz@bp.renesas.com>
> wrote:
> > Add SPI Multi I/O Bus controller node to R9A07G043 (RZ/G2UL) SoC DTSI.
> >
> > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
>
> Thanks for your patch!
>
> > --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > @@ -418,12 +418,20 @@ adc: adc@10059000 {
> > };
> >
> > sbc: spi@10060000 {
> > + compatible = "renesas,r9a07g043-rpc-if",
> > + "renesas,rzg2l-rpc-if";
> > reg = <0 0x10060000 0 0x10000>,
> > <0 0x20000000 0 0x10000000>,
> > <0 0x10070000 0 0x10000>;
> > + reg-names = "regs", "dirmap", "wbuf";
> > + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
>
> LGTM, but this interrupt is not documented in the RZ/G2UL Hardware User's
> Manual (Rev. 0.51 and 1.00)?
You are correct. As per Table25.1 and Table 8.2, QSPI_INT# is not available on
RZ/G2UL.
Will Fix this in next version. Maybe we need to make interrupt as optional in bindings with driver changes?
Cheers,
Biju
>
> > + clocks = <&cpg CPG_MOD R9A07G043_SPI_CLK2>,
> > + <&cpg CPG_MOD R9A07G043_SPI_CLK>;
> > + resets = <&cpg R9A07G043_SPI_RST>;
> > + power-domains = <&cpg>;
> > #address-cells = <1>;
> > #size-cells = <0>;
> > - /* place holder */
> > + status = "disabled";
> > };
> >
> > cpg: clock-controller@11010000 {
>
> Gr{oetje,eeting}s,
>
> Geert
>
> --
> Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-
> m68k.org
>
> In personal conversations with technical people, I call myself a hacker.
> But when I'm talking to journalists I just say "programmer" or something
> like that.
> -- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 1/6] arm64: dts: renesas: r9a07g043: Add SPI Multi I/O Bus controller node
2022-05-02 16:18 ` Biju Das
@ 2022-05-02 16:53 ` Geert Uytterhoeven
0 siblings, 0 replies; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-05-02 16:53 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
Hi Biju,
On Mon, May 2, 2022 at 6:18 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> > Subject: Re: [PATCH 1/6] arm64: dts: renesas: r9a07g043: Add SPI Multi I/O
> > Bus controller node
> > On Sun, May 1, 2022 at 1:29 PM Biju Das <biju.das.jz@bp.renesas.com>
> > wrote:
> > > Add SPI Multi I/O Bus controller node to R9A07G043 (RZ/G2UL) SoC DTSI.
> > >
> > > Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
> > > --- a/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > > +++ b/arch/arm64/boot/dts/renesas/r9a07g043.dtsi
> > > @@ -418,12 +418,20 @@ adc: adc@10059000 {
> > > };
> > >
> > > sbc: spi@10060000 {
> > > + compatible = "renesas,r9a07g043-rpc-if",
> > > + "renesas,rzg2l-rpc-if";
> > > reg = <0 0x10060000 0 0x10000>,
> > > <0 0x20000000 0 0x10000000>,
> > > <0 0x10070000 0 0x10000>;
> > > + reg-names = "regs", "dirmap", "wbuf";
> > > + interrupts = <GIC_SPI 41 IRQ_TYPE_LEVEL_HIGH>;
> >
> > LGTM, but this interrupt is not documented in the RZ/G2UL Hardware User's
> > Manual (Rev. 0.51 and 1.00)?
>
> You are correct. As per Table25.1 and Table 8.2, QSPI_INT# is not available on
> RZ/G2UL.
>
> Will Fix this in next version. Maybe we need to make interrupt as optional in bindings with driver changes?
It's already optional, and the driver doesn't seem to use it at all.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PATCH 3/6] arm64: dts: renesas: r9a07g043: Add OPP table
2022-05-01 11:29 ` [PATCH 3/6] arm64: dts: renesas: r9a07g043: Add OPP table Biju Das
@ 2022-05-02 16:57 ` Geert Uytterhoeven
0 siblings, 0 replies; 14+ messages in thread
From: Geert Uytterhoeven @ 2022-05-02 16:57 UTC (permalink / raw)
To: Biju Das
Cc: Rob Herring, Krzysztof Kozlowski, Magnus Damm, Linux-Renesas,
open list:OPEN FIRMWARE AND FLATTENED DEVICE TREE BINDINGS,
Chris Paterson, Biju Das, Prabhakar Mahadev Lad
On Sun, May 1, 2022 at 1:29 PM Biju Das <biju.das.jz@bp.renesas.com> wrote:
> Add OPP table for RZ/G2UL SoC.
>
> Signed-off-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Geert Uytterhoeven <geert+renesas@glider.be>
i.e. will queue in renesas-devel for v5.19.
Gr{oetje,eeting}s,
Geert
--
Geert Uytterhoeven -- There's lots of Linux beyond ia32 -- geert@linux-m68k.org
In personal conversations with technical people, I call myself a hacker. But
when I'm talking to journalists I just say "programmer" or something like that.
-- Linus Torvalds
^ permalink raw reply [flat|nested] 14+ messages in thread
end of thread, other threads:[~2022-05-02 16:57 UTC | newest]
Thread overview: 14+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-01 11:29 [PATCH 0/6] Add OPP, TSU, RSPI and SPI Multi I/O Bus controller node Biju Das
2022-05-01 11:29 ` [PATCH 1/6] arm64: dts: renesas: r9a07g043: Add " Biju Das
2022-05-02 16:00 ` Geert Uytterhoeven
2022-05-02 16:18 ` Biju Das
2022-05-02 16:53 ` Geert Uytterhoeven
2022-05-01 11:29 ` [PATCH 2/6] arm64: dts: renesas: r9a07g043: Add RSPI{0,1,2} nodes Biju Das
2022-05-02 16:09 ` Geert Uytterhoeven
2022-05-01 11:29 ` [PATCH 3/6] arm64: dts: renesas: r9a07g043: Add OPP table Biju Das
2022-05-02 16:57 ` Geert Uytterhoeven
2022-05-01 11:29 ` [PATCH 4/6] arm64: dts: renesas: r9a07g043: Add TSU node Biju Das
2022-05-02 16:10 ` Geert Uytterhoeven
2022-05-01 11:29 ` [PATCH 5/6] arm64: dts: renesas: r9a07g043: Create thermal zone to support IPA Biju Das
2022-05-02 16:14 ` Geert Uytterhoeven
2022-05-01 11:29 ` [PATCH 6/6] arm64: dts: renesas: r9a07g043: Add ADC node Biju Das
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