* [PATCH 0/6] board: freescale: p1_p2_rdb_pc: Fix sizes of LBC peripherals
@ 2022-05-01 14:23 Pali Rohár
2022-05-01 14:23 ` [PATCH 1/6] Revert "Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig" Pali Rohár
` (5 more replies)
0 siblings, 6 replies; 16+ messages in thread
From: Pali Rohár @ 2022-05-01 14:23 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On LBC (Local Bus Controller) are connected memory peripherals (NOR,
NAND, CPLD). Fix size mappings of all these peripherals. Size needs to
be correctly set in TLB, LAW and LBC OR registers. Use named macros for
human readable configuration.
Pali Rohár (6):
Revert "Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig"
Revert "p1_p2_rdb: Remove CONFIG_CPLD_[BO]R_PRELIM"
mpc85xx: Replace magic values in BR/OR PRELIM config options by proper
C macros
board: freescale: p1_p2_rdb_pc: Fix size of CPLD mapping
board: freescale: p1_p2_rdb_pc: Fix size of FLASH NOR mapping
board: freescale: p1_p2_rdb_pc: Fix size of NAND mapping
README | 11 ++
arch/powerpc/cpu/mpc83xx/elbc/elbc.h | 170 +++++++++++++++++++
arch/powerpc/cpu/mpc8xx/Kconfig | 85 ++++++++++
board/freescale/p1_p2_rdb_pc/law.c | 10 +-
board/freescale/p1_p2_rdb_pc/tlb.c | 20 ++-
configs/M5272C3_defconfig | 24 ---
configs/MCR3000_defconfig | 47 +++--
configs/MPC837XERDB_defconfig | 9 -
configs/MPC8548CDS_36BIT_defconfig | 12 --
configs/MPC8548CDS_defconfig | 12 --
configs/MPC8548CDS_legacy_defconfig | 12 --
configs/P1020RDB-PC_36BIT_NAND_defconfig | 12 --
configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 9 -
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 9 -
configs/P1020RDB-PC_36BIT_defconfig | 9 -
configs/P1020RDB-PC_NAND_defconfig | 12 --
configs/P1020RDB-PC_SDCARD_defconfig | 9 -
configs/P1020RDB-PC_SPIFLASH_defconfig | 9 -
configs/P1020RDB-PC_defconfig | 9 -
configs/P1020RDB-PD_NAND_defconfig | 12 --
configs/P1020RDB-PD_SDCARD_defconfig | 9 -
configs/P1020RDB-PD_SPIFLASH_defconfig | 9 -
configs/P1020RDB-PD_defconfig | 9 -
configs/P2020RDB-PC_36BIT_NAND_defconfig | 12 --
configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 9 -
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 9 -
configs/P2020RDB-PC_36BIT_defconfig | 9 -
configs/P2020RDB-PC_NAND_defconfig | 12 --
configs/P2020RDB-PC_SDCARD_defconfig | 9 -
configs/P2020RDB-PC_SPIFLASH_defconfig | 9 -
configs/P2020RDB-PC_defconfig | 9 -
configs/P2041RDB_NAND_defconfig | 9 -
configs/P2041RDB_SDCARD_defconfig | 6 -
configs/P2041RDB_SPIFLASH_defconfig | 6 -
configs/P2041RDB_defconfig | 6 -
configs/P3041DS_NAND_defconfig | 12 --
configs/P3041DS_SDCARD_defconfig | 9 -
configs/P3041DS_SPIFLASH_defconfig | 9 -
configs/P3041DS_defconfig | 9 -
configs/P4080DS_SDCARD_defconfig | 9 -
configs/P4080DS_SPIFLASH_defconfig | 9 -
configs/P4080DS_defconfig | 9 -
configs/P5040DS_NAND_defconfig | 12 --
configs/P5040DS_SDCARD_defconfig | 9 -
configs/P5040DS_SPIFLASH_defconfig | 9 -
configs/P5040DS_defconfig | 9 -
configs/cobra5272_defconfig | 24 ---
configs/gazerbeam_defconfig | 9 -
configs/ids8313_defconfig | 12 --
configs/kmcoge5ne_defconfig | 12 --
configs/kmeter1_defconfig | 9 -
configs/kmopti2_defconfig | 12 --
configs/kmsupx5_defconfig | 9 -
configs/kmtegr1_defconfig | 9 -
configs/kmtepr2_defconfig | 12 --
configs/socrates_defconfig | 12 --
configs/tuge1_defconfig | 9 -
configs/tuxx1_defconfig | 12 --
drivers/ddr/fsl/Kconfig | 92 ----------
include/configs/M5272C3.h | 20 +++
include/configs/MPC8548CDS.h | 17 ++
include/configs/P2041RDB.h | 25 ++-
include/configs/cobra5272.h | 30 ++++
include/configs/corenet_ds.h | 30 +++-
include/configs/p1_p2_rdb_pc.h | 46 ++++-
include/configs/socrates.h | 9 +
scripts/config_whitelist.txt | 18 ++
67 files changed, 498 insertions(+), 669 deletions(-)
--
2.20.1
^ permalink raw reply [flat|nested] 16+ messages in thread
* [PATCH 1/6] Revert "Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig"
2022-05-01 14:23 [PATCH 0/6] board: freescale: p1_p2_rdb_pc: Fix sizes of LBC peripherals Pali Rohár
@ 2022-05-01 14:23 ` Pali Rohár
2022-05-01 14:39 ` Tom Rini
2022-05-01 14:23 ` [PATCH 2/6] Revert "p1_p2_rdb: Remove CONFIG_CPLD_[BO]R_PRELIM" Pali Rohár
` (4 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Pali Rohár @ 2022-05-01 14:23 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
This reverts commit c7fad78ec0ee41b72a58bebb61959570eb937ab1.
This commit made configuration, understanding, maintenance, debugging and
future development of the powerpc/mpc85xx Local Bus Controller on P1/P2
boards impossible.
All preliminary Base and Option registers depends on other code and C
macros generated at C compile time and they comes from the other macros.
For example, NOR base address and NOR options are set via macros
CONFIG_SYS_FLASH_BR_PRELIM and CONFIG_SYS_FLASH_OR_PRELIM. And then based
on other logic are filled correct values in to the correct macros
CONFIG_SYS_BR*_PRELIM and CONFIG_SYS_OR*_PRELIM.
These config options are not user configurable options and therefore
should not appear in menuconfig. Moreover for P1/P2 boards they have
nothing with DDR driver, so they should not appear in drivers/ddr.
This change was completely wrong direction, so revert it. It allows to
start fixing issues with FLASH, NOR, NAND and CPLD LBC configuration.
In current state it is impossible.
See also thread for more details:
https://lore.kernel.org/u-boot/20220426181740.o2n7xfg46ytljcdx@pali/t/#u
Signed-off-by: Pali Rohár <pali@kernel.org>
---
README | 11 ++
arch/powerpc/cpu/mpc83xx/elbc/elbc.h | 170 +++++++++++++++++++
arch/powerpc/cpu/mpc8xx/Kconfig | 85 ++++++++++
configs/M5272C3_defconfig | 24 ---
configs/MCR3000_defconfig | 47 +++--
configs/MPC837XERDB_defconfig | 9 -
configs/MPC8548CDS_36BIT_defconfig | 12 --
configs/MPC8548CDS_defconfig | 12 --
configs/MPC8548CDS_legacy_defconfig | 12 --
configs/P1020RDB-PC_36BIT_NAND_defconfig | 12 --
configs/P1020RDB-PC_36BIT_SDCARD_defconfig | 9 -
configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig | 9 -
configs/P1020RDB-PC_36BIT_defconfig | 9 -
configs/P1020RDB-PC_NAND_defconfig | 12 --
configs/P1020RDB-PC_SDCARD_defconfig | 9 -
configs/P1020RDB-PC_SPIFLASH_defconfig | 9 -
configs/P1020RDB-PC_defconfig | 9 -
configs/P1020RDB-PD_NAND_defconfig | 12 --
configs/P1020RDB-PD_SDCARD_defconfig | 9 -
configs/P1020RDB-PD_SPIFLASH_defconfig | 9 -
configs/P1020RDB-PD_defconfig | 9 -
configs/P2020RDB-PC_36BIT_NAND_defconfig | 12 --
configs/P2020RDB-PC_36BIT_SDCARD_defconfig | 9 -
configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig | 9 -
configs/P2020RDB-PC_36BIT_defconfig | 9 -
configs/P2020RDB-PC_NAND_defconfig | 12 --
configs/P2020RDB-PC_SDCARD_defconfig | 9 -
configs/P2020RDB-PC_SPIFLASH_defconfig | 9 -
configs/P2020RDB-PC_defconfig | 9 -
configs/P2041RDB_NAND_defconfig | 9 -
configs/P2041RDB_SDCARD_defconfig | 6 -
configs/P2041RDB_SPIFLASH_defconfig | 6 -
configs/P2041RDB_defconfig | 6 -
configs/P3041DS_NAND_defconfig | 12 --
configs/P3041DS_SDCARD_defconfig | 9 -
configs/P3041DS_SPIFLASH_defconfig | 9 -
configs/P3041DS_defconfig | 9 -
configs/P4080DS_SDCARD_defconfig | 9 -
configs/P4080DS_SPIFLASH_defconfig | 9 -
configs/P4080DS_defconfig | 9 -
configs/P5040DS_NAND_defconfig | 12 --
configs/P5040DS_SDCARD_defconfig | 9 -
configs/P5040DS_SPIFLASH_defconfig | 9 -
configs/P5040DS_defconfig | 9 -
configs/cobra5272_defconfig | 24 ---
configs/gazerbeam_defconfig | 9 -
configs/ids8313_defconfig | 12 --
configs/kmcoge5ne_defconfig | 12 --
configs/kmeter1_defconfig | 9 -
configs/kmopti2_defconfig | 12 --
configs/kmsupx5_defconfig | 9 -
configs/kmtegr1_defconfig | 9 -
configs/kmtepr2_defconfig | 12 --
configs/socrates_defconfig | 12 --
configs/tuge1_defconfig | 9 -
configs/tuxx1_defconfig | 12 --
drivers/ddr/fsl/Kconfig | 92 ----------
include/configs/M5272C3.h | 20 +++
include/configs/MPC8548CDS.h | 17 ++
include/configs/P2041RDB.h | 18 ++
include/configs/cobra5272.h | 30 ++++
include/configs/corenet_ds.h | 22 +++
include/configs/p1_p2_rdb_pc.h | 19 +++
include/configs/socrates.h | 9 +
scripts/config_whitelist.txt | 18 ++
65 files changed, 442 insertions(+), 653 deletions(-)
diff --git a/README b/README
index b7ab6e50708d..dbea360bbf70 100644
--- a/README
+++ b/README
@@ -2233,6 +2233,17 @@ Low Level (hardware related) configuration options:
- CONFIG_SYS_MAMR_PTA:
periodic timer for refresh
+- FLASH_BASE0_PRELIM, FLASH_BASE1_PRELIM, CONFIG_SYS_REMAP_OR_AM,
+ CONFIG_SYS_PRELIM_OR_AM, CONFIG_SYS_OR_TIMING_FLASH, CONFIG_SYS_OR0_REMAP,
+ CONFIG_SYS_OR0_PRELIM, CONFIG_SYS_BR0_PRELIM, CONFIG_SYS_OR1_REMAP, CONFIG_SYS_OR1_PRELIM,
+ CONFIG_SYS_BR1_PRELIM:
+ Memory Controller Definitions: BR0/1 and OR0/1 (FLASH)
+
+- SDRAM_BASE2_PRELIM, SDRAM_BASE3_PRELIM, SDRAM_MAX_SIZE,
+ CONFIG_SYS_OR_TIMING_SDRAM, CONFIG_SYS_OR2_PRELIM, CONFIG_SYS_BR2_PRELIM,
+ CONFIG_SYS_OR3_PRELIM, CONFIG_SYS_BR3_PRELIM:
+ Memory Controller Definitions: BR2/3 and OR2/3 (SDRAM)
+
- CONFIG_SYS_SRIO:
Chip has SRIO or not
diff --git a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
index e795cd10cb95..245fe7c6fb79 100644
--- a/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
+++ b/arch/powerpc/cpu/mpc83xx/elbc/elbc.h
@@ -1,3 +1,173 @@
+#ifdef CONFIG_ELBC_BR0_OR0
+#define CONFIG_SYS_BR0_PRELIM (\
+ CONFIG_BR0_OR0_BASE |\
+ CONFIG_BR0_PORTSIZE |\
+ CONFIG_BR0_ERRORCHECKING |\
+ CONFIG_BR0_WRITE_PROTECT_BIT |\
+ CONFIG_BR0_MACHINE |\
+ CONFIG_BR0_ATOMIC |\
+ CONFIG_BR0_VALID_BIT \
+)
+#define CONFIG_SYS_OR0_PRELIM (\
+ CONFIG_OR0_AM |\
+ CONFIG_OR0_XAM |\
+ CONFIG_OR0_BCTLD |\
+ CONFIG_OR0_BI |\
+ CONFIG_OR0_COLS |\
+ CONFIG_OR0_ROWS |\
+ CONFIG_OR0_PMSEL |\
+ CONFIG_OR0_SCY |\
+ CONFIG_OR0_PGS |\
+ CONFIG_OR0_CSCT |\
+ CONFIG_OR0_CST |\
+ CONFIG_OR0_CHT |\
+ CONFIG_OR0_RST |\
+ CONFIG_OR0_CSNT |\
+ CONFIG_OR0_ACS |\
+ CONFIG_OR0_XACS |\
+ CONFIG_OR0_SETA |\
+ CONFIG_OR0_TRLX |\
+ CONFIG_OR0_EHTR |\
+ CONFIG_OR0_EAD \
+)
+#endif /* CONFIG_ELBC_BR0_OR0 */
+
+#ifdef CONFIG_ELBC_BR1_OR1
+#define CONFIG_SYS_BR1_PRELIM (\
+ CONFIG_BR1_OR1_BASE |\
+ CONFIG_BR1_PORTSIZE |\
+ CONFIG_BR1_ERRORCHECKING |\
+ CONFIG_BR1_WRITE_PROTECT_BIT |\
+ CONFIG_BR1_MACHINE |\
+ CONFIG_BR1_ATOMIC |\
+ CONFIG_BR1_VALID_BIT \
+)
+#define CONFIG_SYS_OR1_PRELIM (\
+ CONFIG_OR1_AM |\
+ CONFIG_OR1_XAM |\
+ CONFIG_OR1_BCTLD |\
+ CONFIG_OR1_BI |\
+ CONFIG_OR1_COLS |\
+ CONFIG_OR1_ROWS |\
+ CONFIG_OR1_PMSEL |\
+ CONFIG_OR1_SCY |\
+ CONFIG_OR1_PGS |\
+ CONFIG_OR1_CSCT |\
+ CONFIG_OR1_CST |\
+ CONFIG_OR1_CHT |\
+ CONFIG_OR1_RST |\
+ CONFIG_OR1_CSNT |\
+ CONFIG_OR1_ACS |\
+ CONFIG_OR1_XACS |\
+ CONFIG_OR1_SETA |\
+ CONFIG_OR1_TRLX |\
+ CONFIG_OR1_EHTR |\
+ CONFIG_OR1_EAD \
+)
+#endif /* CONFIG_ELBC_BR1_OR1 */
+
+#ifdef CONFIG_ELBC_BR2_OR2
+#define CONFIG_SYS_BR2_PRELIM (\
+ CONFIG_BR2_OR2_BASE |\
+ CONFIG_BR2_PORTSIZE |\
+ CONFIG_BR2_ERRORCHECKING |\
+ CONFIG_BR2_WRITE_PROTECT_BIT |\
+ CONFIG_BR2_MACHINE |\
+ CONFIG_BR2_ATOMIC |\
+ CONFIG_BR2_VALID_BIT \
+)
+#define CONFIG_SYS_OR2_PRELIM (\
+ CONFIG_OR2_AM |\
+ CONFIG_OR2_XAM |\
+ CONFIG_OR2_BCTLD |\
+ CONFIG_OR2_BI |\
+ CONFIG_OR2_COLS |\
+ CONFIG_OR2_ROWS |\
+ CONFIG_OR2_PMSEL |\
+ CONFIG_OR2_SCY |\
+ CONFIG_OR2_PGS |\
+ CONFIG_OR2_CSCT |\
+ CONFIG_OR2_CST |\
+ CONFIG_OR2_CHT |\
+ CONFIG_OR2_RST |\
+ CONFIG_OR2_CSNT |\
+ CONFIG_OR2_ACS |\
+ CONFIG_OR2_XACS |\
+ CONFIG_OR2_SETA |\
+ CONFIG_OR2_TRLX |\
+ CONFIG_OR2_EHTR |\
+ CONFIG_OR2_EAD \
+)
+#endif /* CONFIG_ELBC_BR2_OR2 */
+
+#ifdef CONFIG_ELBC_BR3_OR3
+#define CONFIG_SYS_BR3_PRELIM (\
+ CONFIG_BR3_OR3_BASE |\
+ CONFIG_BR3_PORTSIZE |\
+ CONFIG_BR3_ERRORCHECKING |\
+ CONFIG_BR3_WRITE_PROTECT_BIT |\
+ CONFIG_BR3_MACHINE |\
+ CONFIG_BR3_ATOMIC |\
+ CONFIG_BR3_VALID_BIT \
+)
+#define CONFIG_SYS_OR3_PRELIM (\
+ CONFIG_OR3_AM |\
+ CONFIG_OR3_XAM |\
+ CONFIG_OR3_BCTLD |\
+ CONFIG_OR3_BI |\
+ CONFIG_OR3_COLS |\
+ CONFIG_OR3_ROWS |\
+ CONFIG_OR3_PMSEL |\
+ CONFIG_OR3_SCY |\
+ CONFIG_OR3_PGS |\
+ CONFIG_OR3_CSCT |\
+ CONFIG_OR3_CST |\
+ CONFIG_OR3_CHT |\
+ CONFIG_OR3_RST |\
+ CONFIG_OR3_CSNT |\
+ CONFIG_OR3_ACS |\
+ CONFIG_OR3_XACS |\
+ CONFIG_OR3_SETA |\
+ CONFIG_OR3_TRLX |\
+ CONFIG_OR3_EHTR |\
+ CONFIG_OR3_EAD \
+)
+#endif /* CONFIG_ELBC_BR3_OR3 */
+
+#ifdef CONFIG_ELBC_BR4_OR4
+#define CONFIG_SYS_BR4_PRELIM (\
+ CONFIG_BR4_OR4_BASE |\
+ CONFIG_BR4_PORTSIZE |\
+ CONFIG_BR4_ERRORCHECKING |\
+ CONFIG_BR4_WRITE_PROTECT_BIT |\
+ CONFIG_BR4_MACHINE |\
+ CONFIG_BR4_ATOMIC |\
+ CONFIG_BR4_VALID_BIT \
+)
+#define CONFIG_SYS_OR4_PRELIM (\
+ CONFIG_OR4_AM |\
+ CONFIG_OR4_XAM |\
+ CONFIG_OR4_BCTLD |\
+ CONFIG_OR4_BI |\
+ CONFIG_OR4_COLS |\
+ CONFIG_OR4_ROWS |\
+ CONFIG_OR4_PMSEL |\
+ CONFIG_OR4_SCY |\
+ CONFIG_OR4_PGS |\
+ CONFIG_OR4_CSCT |\
+ CONFIG_OR4_CST |\
+ CONFIG_OR4_CHT |\
+ CONFIG_OR4_RST |\
+ CONFIG_OR4_CSNT |\
+ CONFIG_OR4_ACS |\
+ CONFIG_OR4_XACS |\
+ CONFIG_OR4_SETA |\
+ CONFIG_OR4_TRLX |\
+ CONFIG_OR4_EHTR |\
+ CONFIG_OR4_EAD \
+)
+#endif /* CONFIG_ELBC_BR4_OR4 */
+
#if defined(CONFIG_ELBC_BR_OR_NAND_PRELIM_0)
#define CONFIG_SYS_NAND_BR_PRELIM CONFIG_SYS_BR0_PRELIM
#define CONFIG_SYS_NAND_OR_PRELIM CONFIG_SYS_OR0_PRELIM
diff --git a/arch/powerpc/cpu/mpc8xx/Kconfig b/arch/powerpc/cpu/mpc8xx/Kconfig
index d63071104c4d..2f844ea78677 100644
--- a/arch/powerpc/cpu/mpc8xx/Kconfig
+++ b/arch/powerpc/cpu/mpc8xx/Kconfig
@@ -84,6 +84,91 @@ config SYS_DER
help
Debug Event Register (37-47)
+comment "Memory mapping"
+
+config SYS_BR0_PRELIM
+ hex "Preliminary value for BR0"
+
+config SYS_OR0_PRELIM
+ hex "Preliminary value for OR0"
+
+config SYS_BR1_PRELIM_BOOL
+ bool "Define Bank 1"
+
+config SYS_BR1_PRELIM
+ hex "Preliminary value for BR1"
+ depends on SYS_BR1_PRELIM_BOOL
+
+config SYS_OR1_PRELIM
+ hex "Preliminary value for OR1"
+ depends on SYS_BR1_PRELIM_BOOL
+
+config SYS_BR2_PRELIM_BOOL
+ bool "Define Bank 2"
+
+config SYS_BR2_PRELIM
+ hex "Preliminary value for BR2"
+ depends on SYS_BR2_PRELIM_BOOL
+
+config SYS_OR2_PRELIM
+ hex "Preliminary value for OR2"
+ depends on SYS_BR2_PRELIM_BOOL
+
+config SYS_BR3_PRELIM_BOOL
+ bool "Define Bank 3"
+
+config SYS_BR3_PRELIM
+ hex "Preliminary value for BR3"
+ depends on SYS_BR3_PRELIM_BOOL
+
+config SYS_OR3_PRELIM
+ hex "Preliminary value for OR3"
+ depends on SYS_BR3_PRELIM_BOOL
+
+config SYS_BR4_PRELIM_BOOL
+ bool "Define Bank 4"
+
+config SYS_BR4_PRELIM
+ hex "Preliminary value for BR4"
+ depends on SYS_BR4_PRELIM_BOOL
+
+config SYS_OR4_PRELIM
+ hex "Preliminary value for OR4"
+ depends on SYS_BR4_PRELIM_BOOL
+
+config SYS_BR5_PRELIM_BOOL
+ bool "Define Bank 5"
+
+config SYS_BR5_PRELIM
+ hex "Preliminary value for BR5"
+ depends on SYS_BR5_PRELIM_BOOL
+
+config SYS_OR5_PRELIM
+ hex "Preliminary value for OR5"
+ depends on SYS_BR5_PRELIM_BOOL
+
+config SYS_BR6_PRELIM_BOOL
+ bool "Define Bank 6"
+
+config SYS_BR6_PRELIM
+ hex "Preliminary value for BR6"
+ depends on SYS_BR6_PRELIM_BOOL
+
+config SYS_OR6_PRELIM
+ hex "Preliminary value for OR6"
+ depends on SYS_BR6_PRELIM_BOOL
+
+config SYS_BR7_PRELIM_BOOL
+ bool "Define Bank 7"
+
+config SYS_BR7_PRELIM
+ hex "Preliminary value for BR7"
+ depends on SYS_BR7_PRELIM_BOOL
+
+config SYS_OR7_PRELIM
+ hex "Preliminary value for OR7"
+ depends on SYS_BR7_PRELIM_BOOL
+
source "board/cssi/MCR3000/Kconfig"
endmenu
diff --git a/configs/M5272C3_defconfig b/configs/M5272C3_defconfig
index ed48264ed9ca..7ae4d3fab00d 100644
--- a/configs/M5272C3_defconfig
+++ b/configs/M5272C3_defconfig
@@ -26,30 +26,6 @@ CONFIG_CMD_CACHE=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SYS_RX_ETH_BUFFER=8
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFFE00201
-CONFIG_SYS_OR0_PRELIM=0xFFE00014
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0x0
-CONFIG_SYS_OR1_PRELIM=0x0
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0x30000001
-CONFIG_SYS_OR2_PRELIM=0xFFF80000
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0x0
-CONFIG_SYS_OR3_PRELIM=0x0
-CONFIG_SYS_BR4_PRELIM_BOOL=y
-CONFIG_SYS_BR4_PRELIM=0x0
-CONFIG_SYS_OR4_PRELIM=0x0
-CONFIG_SYS_BR5_PRELIM_BOOL=y
-CONFIG_SYS_BR5_PRELIM=0x0
-CONFIG_SYS_OR5_PRELIM=0x0
-CONFIG_SYS_BR6_PRELIM_BOOL=y
-CONFIG_SYS_BR6_PRELIM=0x0
-CONFIG_SYS_OR6_PRELIM=0x0
-CONFIG_SYS_BR7_PRELIM_BOOL=y
-CONFIG_SYS_BR7_PRELIM=0x701
-CONFIG_SYS_OR7_PRELIM=0xFFC0007C
CONFIG_MTD_NOR_FLASH=y
CONFIG_FLASH_CFI_DRIVER=y
CONFIG_SYS_FLASH_PROTECTION=y
diff --git a/configs/MCR3000_defconfig b/configs/MCR3000_defconfig
index f99a830b546a..ec7a27fb8692 100644
--- a/configs/MCR3000_defconfig
+++ b/configs/MCR3000_defconfig
@@ -18,6 +18,29 @@ CONFIG_SYS_PLPRCR=0x00460004
CONFIG_SYS_SCCR=0x00C20000
CONFIG_SYS_SCCR_MASK=0x60000000
CONFIG_SYS_DER=0x2002000F
+CONFIG_SYS_BR0_PRELIM=0x04000801
+CONFIG_SYS_OR0_PRELIM=0xFFC00926
+CONFIG_SYS_BR1_PRELIM_BOOL=y
+CONFIG_SYS_BR1_PRELIM=0x00000081
+CONFIG_SYS_OR1_PRELIM=0xFE000E00
+CONFIG_SYS_BR2_PRELIM_BOOL=y
+CONFIG_SYS_BR2_PRELIM=0x08000801
+CONFIG_SYS_OR2_PRELIM=0xFFFF8F2A
+CONFIG_SYS_BR3_PRELIM_BOOL=y
+CONFIG_SYS_BR3_PRELIM=0x0C000401
+CONFIG_SYS_OR3_PRELIM=0xFFFF8142
+CONFIG_SYS_BR4_PRELIM_BOOL=y
+CONFIG_SYS_BR4_PRELIM=0x10000801
+CONFIG_SYS_OR4_PRELIM=0xFFFF8D08
+CONFIG_SYS_BR5_PRELIM_BOOL=y
+CONFIG_SYS_BR5_PRELIM=0x14000801
+CONFIG_SYS_OR5_PRELIM=0xFFFF8916
+CONFIG_SYS_BR6_PRELIM_BOOL=y
+CONFIG_SYS_BR6_PRELIM=0x18000801
+CONFIG_SYS_OR6_PRELIM=0xFFFF0908
+CONFIG_SYS_BR7_PRELIM_BOOL=y
+CONFIG_SYS_BR7_PRELIM=0x1C000001
+CONFIG_SYS_OR7_PRELIM=0xFFFF810A
CONFIG_OF_BOARD_SETUP=y
CONFIG_SYS_MONITOR_BASE=0x04000000
CONFIG_BOOTDELAY=5
@@ -52,30 +75,6 @@ CONFIG_ENV_OVERWRITE=y
CONFIG_ENV_IS_IN_FLASH=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_DM=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0x4000801
-CONFIG_SYS_OR0_PRELIM=0xFFC00926
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0x81
-CONFIG_SYS_OR1_PRELIM=0xFE000E00
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0x8000801
-CONFIG_SYS_OR2_PRELIM=0xFFFF8F2A
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xC000401
-CONFIG_SYS_OR3_PRELIM=0xFFFF8142
-CONFIG_SYS_BR4_PRELIM_BOOL=y
-CONFIG_SYS_BR4_PRELIM=0x10000801
-CONFIG_SYS_OR4_PRELIM=0xFFFF8D08
-CONFIG_SYS_BR5_PRELIM_BOOL=y
-CONFIG_SYS_BR5_PRELIM=0x14000801
-CONFIG_SYS_OR5_PRELIM=0xFFFF8916
-CONFIG_SYS_BR6_PRELIM_BOOL=y
-CONFIG_SYS_BR6_PRELIM=0x18000801
-CONFIG_SYS_OR6_PRELIM=0xFFFF0908
-CONFIG_SYS_BR7_PRELIM_BOOL=y
-CONFIG_SYS_BR7_PRELIM=0x1C000001
-CONFIG_SYS_OR7_PRELIM=0xFFFF810A
# CONFIG_MMC is not set
CONFIG_MTD=y
CONFIG_MTD_NOR_FLASH=y
diff --git a/configs/MPC837XERDB_defconfig b/configs/MPC837XERDB_defconfig
index 4a9db732f92e..dc6d847d9437 100644
--- a/configs/MPC837XERDB_defconfig
+++ b/configs/MPC837XERDB_defconfig
@@ -175,15 +175,6 @@ CONFIG_ETHPRIME="TSEC0"
CONFIG_DM=y
CONFIG_FSL_SATA=y
CONFIG_SYS_SATA_MAX_DEVICE=2
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFE001001
-CONFIG_SYS_OR0_PRELIM=0xFF800193
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE0600C21
-CONFIG_SYS_OR1_PRELIM=0xFFFF8396
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xF0000801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
diff --git a/configs/MPC8548CDS_36BIT_defconfig b/configs/MPC8548CDS_36BIT_defconfig
index 6933699771fb..f63bf06ac6c9 100644
--- a/configs/MPC8548CDS_36BIT_defconfig
+++ b/configs/MPC8548CDS_36BIT_defconfig
@@ -39,18 +39,6 @@ CONFIG_DM=y
CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF807001
-CONFIG_SYS_OR0_PRELIM=0xFF806E65
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xFF007001
-CONFIG_SYS_OR1_PRELIM=0xFF806E65
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xF0007861
-CONFIG_SYS_OR2_PRELIM=0xFC006901
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xF8006801
-CONFIG_SYS_OR3_PRELIM=0xFFF00FF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/MPC8548CDS_defconfig b/configs/MPC8548CDS_defconfig
index ee9c14880c6e..63ef36fad625 100644
--- a/configs/MPC8548CDS_defconfig
+++ b/configs/MPC8548CDS_defconfig
@@ -38,18 +38,6 @@ CONFIG_DM=y
CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF801001
-CONFIG_SYS_OR0_PRELIM=0xFF806E65
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xFF001001
-CONFIG_SYS_OR1_PRELIM=0xFF806E65
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xF0001861
-CONFIG_SYS_OR2_PRELIM=0xFC006901
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xF8000801
-CONFIG_SYS_OR3_PRELIM=0xFFF00FF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/MPC8548CDS_legacy_defconfig b/configs/MPC8548CDS_legacy_defconfig
index 97f641d71cdf..25d347bd7855 100644
--- a/configs/MPC8548CDS_legacy_defconfig
+++ b/configs/MPC8548CDS_legacy_defconfig
@@ -38,18 +38,6 @@ CONFIG_DM=y
CONFIG_CHIP_SELECTS_PER_CTRL=2
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF801001
-CONFIG_SYS_OR0_PRELIM=0xFF806E65
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xFF001001
-CONFIG_SYS_OR1_PRELIM=0xFF806E65
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xF0001861
-CONFIG_SYS_OR2_PRELIM=0xFC006901
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xF8000801
-CONFIG_SYS_OR3_PRELIM=0xFFF00FF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P1020RDB-PC_36BIT_NAND_defconfig b/configs/P1020RDB-PC_36BIT_NAND_defconfig
index 56b984e5ae68..015ce7257f3a 100644
--- a/configs/P1020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P1020RDB-PC_36BIT_NAND_defconfig
@@ -60,18 +60,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF800C21
-CONFIG_SYS_OR0_PRELIM=0xFFFF8396
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xEF001001
-CONFIG_SYS_OR1_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
index 4407a02a7d97..f6efdf1c9967 100644
--- a/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SDCARD_defconfig
@@ -56,15 +56,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
index ee0fdd6657d1..926b5ac928c9 100644
--- a/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -59,15 +59,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P1020RDB-PC_36BIT_defconfig b/configs/P1020RDB-PC_36BIT_defconfig
index bbfc4a5bcff9..a807e272e046 100644
--- a/configs/P1020RDB-PC_36BIT_defconfig
+++ b/configs/P1020RDB-PC_36BIT_defconfig
@@ -45,15 +45,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P1020RDB-PC_NAND_defconfig b/configs/P1020RDB-PC_NAND_defconfig
index 00d847d50af2..cf46268981e5 100644
--- a/configs/P1020RDB-PC_NAND_defconfig
+++ b/configs/P1020RDB-PC_NAND_defconfig
@@ -59,18 +59,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF800C21
-CONFIG_SYS_OR0_PRELIM=0xFFFF8396
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xEF001001
-CONFIG_SYS_OR1_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1020RDB-PC_SDCARD_defconfig b/configs/P1020RDB-PC_SDCARD_defconfig
index feb00ea91615..e640e48e6fbd 100644
--- a/configs/P1020RDB-PC_SDCARD_defconfig
+++ b/configs/P1020RDB-PC_SDCARD_defconfig
@@ -55,15 +55,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P1020RDB-PC_SPIFLASH_defconfig b/configs/P1020RDB-PC_SPIFLASH_defconfig
index f18f4b2ce150..6e11abebca56 100644
--- a/configs/P1020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PC_SPIFLASH_defconfig
@@ -58,15 +58,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P1020RDB-PC_defconfig b/configs/P1020RDB-PC_defconfig
index aec0d47acb7c..069b21885fa4 100644
--- a/configs/P1020RDB-PC_defconfig
+++ b/configs/P1020RDB-PC_defconfig
@@ -44,15 +44,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P1020RDB-PD_NAND_defconfig b/configs/P1020RDB-PD_NAND_defconfig
index 0d713624d488..867e6328564b 100644
--- a/configs/P1020RDB-PD_NAND_defconfig
+++ b/configs/P1020RDB-PD_NAND_defconfig
@@ -62,18 +62,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=2
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF800C21
-CONFIG_SYS_OR0_PRELIM=0xFFFF8796
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xEC001001
-CONFIG_SYS_OR1_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y
diff --git a/configs/P1020RDB-PD_SDCARD_defconfig b/configs/P1020RDB-PD_SDCARD_defconfig
index b50dfcbc392c..799e2442644e 100644
--- a/configs/P1020RDB-PD_SDCARD_defconfig
+++ b/configs/P1020RDB-PD_SDCARD_defconfig
@@ -58,15 +58,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=2
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEC001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P1020RDB-PD_SPIFLASH_defconfig b/configs/P1020RDB-PD_SPIFLASH_defconfig
index 6649f5b2feaf..907ad57ef5df 100644
--- a/configs/P1020RDB-PD_SPIFLASH_defconfig
+++ b/configs/P1020RDB-PD_SPIFLASH_defconfig
@@ -61,15 +61,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=2
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEC001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P1020RDB-PD_defconfig b/configs/P1020RDB-PD_defconfig
index cbbdb0fb113a..b9f48a45fd19 100644
--- a/configs/P1020RDB-PD_defconfig
+++ b/configs/P1020RDB-PD_defconfig
@@ -47,15 +47,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=2
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEC001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P2020RDB-PC_36BIT_NAND_defconfig b/configs/P2020RDB-PC_36BIT_NAND_defconfig
index e167468ed385..f256d5303a94 100644
--- a/configs/P2020RDB-PC_36BIT_NAND_defconfig
+++ b/configs/P2020RDB-PC_36BIT_NAND_defconfig
@@ -64,18 +64,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF800C21
-CONFIG_SYS_OR0_PRELIM=0xFFFF8396
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xEF001001
-CONFIG_SYS_OR1_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y
diff --git a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
index 1e15552edc70..5ea88e071c8a 100644
--- a/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SDCARD_defconfig
@@ -60,15 +60,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
index cf0ae5da3cfa..99fe986e0969 100644
--- a/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_36BIT_SPIFLASH_defconfig
@@ -63,15 +63,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P2020RDB-PC_36BIT_defconfig b/configs/P2020RDB-PC_36BIT_defconfig
index bd189b965b00..d9dec63ad13a 100644
--- a/configs/P2020RDB-PC_36BIT_defconfig
+++ b/configs/P2020RDB-PC_36BIT_defconfig
@@ -49,15 +49,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P2020RDB-PC_NAND_defconfig b/configs/P2020RDB-PC_NAND_defconfig
index 29d90c91400e..5e055ebc4e25 100644
--- a/configs/P2020RDB-PC_NAND_defconfig
+++ b/configs/P2020RDB-PC_NAND_defconfig
@@ -63,18 +63,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF800C21
-CONFIG_SYS_OR0_PRELIM=0xFFFF8396
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xEF001001
-CONFIG_SYS_OR1_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_TPL_SYS_I2C_LEGACY=y
diff --git a/configs/P2020RDB-PC_SDCARD_defconfig b/configs/P2020RDB-PC_SDCARD_defconfig
index 540999bef21d..73651a6b4d89 100644
--- a/configs/P2020RDB-PC_SDCARD_defconfig
+++ b/configs/P2020RDB-PC_SDCARD_defconfig
@@ -59,15 +59,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P2020RDB-PC_SPIFLASH_defconfig b/configs/P2020RDB-PC_SPIFLASH_defconfig
index 0881e35476ac..8a5b7c9f115d 100644
--- a/configs/P2020RDB-PC_SPIFLASH_defconfig
+++ b/configs/P2020RDB-PC_SPIFLASH_defconfig
@@ -62,15 +62,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P2020RDB-PC_defconfig b/configs/P2020RDB-PC_defconfig
index eba11d340acb..30897e11d02b 100644
--- a/configs/P2020RDB-PC_defconfig
+++ b/configs/P2020RDB-PC_defconfig
@@ -48,15 +48,6 @@ CONFIG_ETHPRIME="eTSEC1"
CONFIG_DM=y
CONFIG_DDR_CLK_FREQ=66666666
CONFIG_CHIP_SELECTS_PER_CTRL=1
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xEF001001
-CONFIG_SYS_OR0_PRELIM=0xFC000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xFFB00801
-CONFIG_SYS_OR2_PRELIM=0xFFFE09FF
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFA00801
-CONFIG_SYS_OR3_PRELIM=0xFFF009F7
CONFIG_DM_I2C=y
CONFIG_SPL_SYS_I2C_LEGACY=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
diff --git a/configs/P2041RDB_NAND_defconfig b/configs/P2041RDB_NAND_defconfig
index 9717f50834ad..97e67db39ef4 100644
--- a/configs/P2041RDB_NAND_defconfig
+++ b/configs/P2041RDB_NAND_defconfig
@@ -47,15 +47,6 @@ CONFIG_ETHPRIME="FM1@DTSEC1"
CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFFA00C21
-CONFIG_SYS_OR0_PRELIM=0xFFFC0796
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE8001001
-CONFIG_SYS_OR1_PRELIM=0xF8000F85
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P2041RDB_SDCARD_defconfig b/configs/P2041RDB_SDCARD_defconfig
index 50065c4a9672..1142d563c56e 100644
--- a/configs/P2041RDB_SDCARD_defconfig
+++ b/configs/P2041RDB_SDCARD_defconfig
@@ -47,12 +47,6 @@ CONFIG_ETHPRIME="FM1@DTSEC1"
CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xE8001001
-CONFIG_SYS_OR0_PRELIM=0xF8000F85
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P2041RDB_SPIFLASH_defconfig b/configs/P2041RDB_SPIFLASH_defconfig
index 25f32c03c149..c74c1c60e8f4 100644
--- a/configs/P2041RDB_SPIFLASH_defconfig
+++ b/configs/P2041RDB_SPIFLASH_defconfig
@@ -49,12 +49,6 @@ CONFIG_ETHPRIME="FM1@DTSEC1"
CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xE8001001
-CONFIG_SYS_OR0_PRELIM=0xF8000F85
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P2041RDB_defconfig b/configs/P2041RDB_defconfig
index 29e94fcd094c..421eefc7df28 100644
--- a/configs/P2041RDB_defconfig
+++ b/configs/P2041RDB_defconfig
@@ -44,12 +44,6 @@ CONFIG_ETHPRIME="FM1@DTSEC1"
CONFIG_DM=y
CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xE8001001
-CONFIG_SYS_OR0_PRELIM=0xF8000F85
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P3041DS_NAND_defconfig b/configs/P3041DS_NAND_defconfig
index 638b409b9635..66dbffc2d198 100644
--- a/configs/P3041DS_NAND_defconfig
+++ b/configs/P3041DS_NAND_defconfig
@@ -47,18 +47,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFFA00C21
-CONFIG_SYS_OR0_PRELIM=0xFFFC0796
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE0001001
-CONFIG_SYS_OR1_PRELIM=0xF8000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xE8001001
-CONFIG_SYS_OR2_PRELIM=0xF8000F85
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P3041DS_SDCARD_defconfig b/configs/P3041DS_SDCARD_defconfig
index e05ea44d2c2a..aec5e6019191 100644
--- a/configs/P3041DS_SDCARD_defconfig
+++ b/configs/P3041DS_SDCARD_defconfig
@@ -47,15 +47,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xE8001001
-CONFIG_SYS_OR0_PRELIM=0xF8000F85
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE0001001
-CONFIG_SYS_OR1_PRELIM=0xF8000FF7
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P3041DS_SPIFLASH_defconfig b/configs/P3041DS_SPIFLASH_defconfig
index 9bfde175420f..53612ce2be63 100644
--- a/configs/P3041DS_SPIFLASH_defconfig
+++ b/configs/P3041DS_SPIFLASH_defconfig
@@ -49,15 +49,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xE8001001
-CONFIG_SYS_OR0_PRELIM=0xF8000F85
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE0001001
-CONFIG_SYS_OR1_PRELIM=0xF8000FF7
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P3041DS_defconfig b/configs/P3041DS_defconfig
index d62a200871ab..1b4a85344a69 100644
--- a/configs/P3041DS_defconfig
+++ b/configs/P3041DS_defconfig
@@ -44,15 +44,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xE8001001
-CONFIG_SYS_OR0_PRELIM=0xF8000F85
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE0001001
-CONFIG_SYS_OR1_PRELIM=0xF8000FF7
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P4080DS_SDCARD_defconfig b/configs/P4080DS_SDCARD_defconfig
index 63f8e6aa9d49..715a049f679c 100644
--- a/configs/P4080DS_SDCARD_defconfig
+++ b/configs/P4080DS_SDCARD_defconfig
@@ -46,15 +46,6 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xE8001001
-CONFIG_SYS_OR0_PRELIM=0xF8000F85
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE0001001
-CONFIG_SYS_OR1_PRELIM=0xF8000FF7
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P4080DS_SPIFLASH_defconfig b/configs/P4080DS_SPIFLASH_defconfig
index 56da9d80b73f..b06cf949f1d2 100644
--- a/configs/P4080DS_SPIFLASH_defconfig
+++ b/configs/P4080DS_SPIFLASH_defconfig
@@ -48,15 +48,6 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xE8001001
-CONFIG_SYS_OR0_PRELIM=0xF8000F85
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE0001001
-CONFIG_SYS_OR1_PRELIM=0xF8000FF7
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P4080DS_defconfig b/configs/P4080DS_defconfig
index ec5d2f9ac6c3..0c4251369059 100644
--- a/configs/P4080DS_defconfig
+++ b/configs/P4080DS_defconfig
@@ -43,15 +43,6 @@ CONFIG_DM=y
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xE8001001
-CONFIG_SYS_OR0_PRELIM=0xF8000F85
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE0001001
-CONFIG_SYS_OR1_PRELIM=0xF8000FF7
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P5040DS_NAND_defconfig b/configs/P5040DS_NAND_defconfig
index 2ac298a43141..f4234723bc67 100644
--- a/configs/P5040DS_NAND_defconfig
+++ b/configs/P5040DS_NAND_defconfig
@@ -48,18 +48,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFFA00C21
-CONFIG_SYS_OR0_PRELIM=0xFFFC0796
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE0001001
-CONFIG_SYS_OR1_PRELIM=0xF8000FF7
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xE8001001
-CONFIG_SYS_OR2_PRELIM=0xF8000F85
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P5040DS_SDCARD_defconfig b/configs/P5040DS_SDCARD_defconfig
index a1ddca57750c..a7bef5db0dcc 100644
--- a/configs/P5040DS_SDCARD_defconfig
+++ b/configs/P5040DS_SDCARD_defconfig
@@ -47,15 +47,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xE8001001
-CONFIG_SYS_OR0_PRELIM=0xF8000F85
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE0001001
-CONFIG_SYS_OR1_PRELIM=0xF8000FF7
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P5040DS_SPIFLASH_defconfig b/configs/P5040DS_SPIFLASH_defconfig
index 32fec67e949e..0e18933e6ab5 100644
--- a/configs/P5040DS_SPIFLASH_defconfig
+++ b/configs/P5040DS_SPIFLASH_defconfig
@@ -49,15 +49,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xE8001001
-CONFIG_SYS_OR0_PRELIM=0xF8000F85
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE0001001
-CONFIG_SYS_OR1_PRELIM=0xF8000FF7
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/P5040DS_defconfig b/configs/P5040DS_defconfig
index 48bd2b6f1bf1..927eb12b5a41 100644
--- a/configs/P5040DS_defconfig
+++ b/configs/P5040DS_defconfig
@@ -44,15 +44,6 @@ CONFIG_SYS_SATA_MAX_DEVICE=2
CONFIG_FSL_CAAM=y
CONFIG_DDR_ECC=y
CONFIG_ECC_INIT_VIA_DDRCONTROLLER=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xE8001001
-CONFIG_SYS_OR0_PRELIM=0xF8000F85
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE0001001
-CONFIG_SYS_OR1_PRELIM=0xF8000FF7
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xFFDF0801
-CONFIG_SYS_OR3_PRELIM=0xFFFFEFF7
CONFIG_DM_I2C=y
CONFIG_I2C_SET_DEFAULT_BUS_NUM=y
CONFIG_SYS_I2C_FSL=y
diff --git a/configs/cobra5272_defconfig b/configs/cobra5272_defconfig
index eacfc6614339..da3a009ead59 100644
--- a/configs/cobra5272_defconfig
+++ b/configs/cobra5272_defconfig
@@ -23,30 +23,6 @@ CONFIG_CMD_PING=y
CONFIG_SYS_RELOC_GD_ENV_ADDR=y
CONFIG_SYS_FAULT_ECHO_LINK_DOWN=y
CONFIG_SYS_RX_ETH_BUFFER=8
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFFE00201
-CONFIG_SYS_OR0_PRELIM=0xFFE00014
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0x0
-CONFIG_SYS_OR1_PRELIM=0x0
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0x0
-CONFIG_SYS_OR2_PRELIM=0x0
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0x0
-CONFIG_SYS_OR3_PRELIM=0x0
-CONFIG_SYS_BR4_PRELIM_BOOL=y
-CONFIG_SYS_BR4_PRELIM=0x0
-CONFIG_SYS_OR4_PRELIM=0x0
-CONFIG_SYS_BR5_PRELIM_BOOL=y
-CONFIG_SYS_BR5_PRELIM=0x0
-CONFIG_SYS_OR5_PRELIM=0x0
-CONFIG_SYS_BR6_PRELIM_BOOL=y
-CONFIG_SYS_BR6_PRELIM=0x0
-CONFIG_SYS_OR6_PRELIM=0x0
-CONFIG_SYS_BR7_PRELIM_BOOL=y
-CONFIG_SYS_BR7_PRELIM=0x701
-CONFIG_SYS_OR7_PRELIM=0xFF00007C
CONFIG_MTD_NOR_FLASH=y
CONFIG_USE_SYS_MAX_FLASH_BANKS=y
CONFIG_DM_ETH=y
diff --git a/configs/gazerbeam_defconfig b/configs/gazerbeam_defconfig
index f2f0257071c2..9d585fb4c34f 100644
--- a/configs/gazerbeam_defconfig
+++ b/configs/gazerbeam_defconfig
@@ -162,15 +162,6 @@ CONFIG_CLK=y
CONFIG_CLK_ICS8N3QV01=y
CONFIG_CPU=y
CONFIG_CPU_MPC83XX=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFE001001
-CONFIG_SYS_OR0_PRELIM=0xFF800FF6
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE0601001
-CONFIG_SYS_OR1_PRELIM=0xFFF00850
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xE0701001
-CONFIG_SYS_OR2_PRELIM=0xFFF00850
CONFIG_DM_PCA953X=y
CONFIG_MPC8XXX_GPIO=y
CONFIG_DM_I2C=y
diff --git a/configs/ids8313_defconfig b/configs/ids8313_defconfig
index 7415b1158c6a..0740ba972a93 100644
--- a/configs/ids8313_defconfig
+++ b/configs/ids8313_defconfig
@@ -166,18 +166,6 @@ CONFIG_ETHPRIME="TSEC1"
CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_BOOTCOUNT_I2C=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFF800801
-CONFIG_SYS_OR0_PRELIM=0xFF8008A7
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE1000C21
-CONFIG_SYS_OR1_PRELIM=0xFFFF87CE
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xE2000801
-CONFIG_SYS_OR2_PRELIM=0xFFFE0C74
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xE3000801
-CONFIG_SYS_OR3_PRELIM=0xFFFF8814
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3100
diff --git a/configs/kmcoge5ne_defconfig b/configs/kmcoge5ne_defconfig
index 00c98483b303..c3b7770e0a3b 100644
--- a/configs/kmcoge5ne_defconfig
+++ b/configs/kmcoge5ne_defconfig
@@ -197,18 +197,6 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xF0001001
-CONFIG_SYS_OR0_PRELIM=0xF0000E55
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE8000801
-CONFIG_SYS_OR1_PRELIM=0xFC000E25
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xA0000801
-CONFIG_SYS_OR3_PRELIM=0xF0000E25
-CONFIG_SYS_BR4_PRELIM_BOOL=y
-CONFIG_SYS_BR4_PRELIM=0xB0000801
-CONFIG_SYS_OR4_PRELIM=0xF0000E25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
diff --git a/configs/kmeter1_defconfig b/configs/kmeter1_defconfig
index ae29991c492d..a869597bf464 100644
--- a/configs/kmeter1_defconfig
+++ b/configs/kmeter1_defconfig
@@ -166,15 +166,6 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xF0001001
-CONFIG_SYS_OR0_PRELIM=0xF0000E55
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE8000801
-CONFIG_SYS_OR1_PRELIM=0xFC000E25
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xA0000801
-CONFIG_SYS_OR3_PRELIM=0xF0000E25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
diff --git a/configs/kmopti2_defconfig b/configs/kmopti2_defconfig
index 45bc3eb3b4d5..d06ccce0c612 100644
--- a/configs/kmopti2_defconfig
+++ b/configs/kmopti2_defconfig
@@ -178,18 +178,6 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xF0001001
-CONFIG_SYS_OR0_PRELIM=0xF0000E55
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE8000801
-CONFIG_SYS_OR1_PRELIM=0xF8000E25
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xA0000801
-CONFIG_SYS_OR2_PRELIM=0xF0000C25
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xB0001001
-CONFIG_SYS_OR3_PRELIM=0xF0000040
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
diff --git a/configs/kmsupx5_defconfig b/configs/kmsupx5_defconfig
index 08d217986d74..03a86275482c 100644
--- a/configs/kmsupx5_defconfig
+++ b/configs/kmsupx5_defconfig
@@ -157,15 +157,6 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xF0001001
-CONFIG_SYS_OR0_PRELIM=0xF0000E55
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE8000801
-CONFIG_SYS_OR1_PRELIM=0xF8000E25
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xA0000801
-CONFIG_SYS_OR2_PRELIM=0xF0000C25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
diff --git a/configs/kmtegr1_defconfig b/configs/kmtegr1_defconfig
index a752672ead19..dbf20a1757c2 100644
--- a/configs/kmtegr1_defconfig
+++ b/configs/kmtegr1_defconfig
@@ -158,15 +158,6 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xF0001001
-CONFIG_SYS_OR0_PRELIM=0xF0000E55
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE8000801
-CONFIG_SYS_OR1_PRELIM=0xF8000E25
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xB0001001
-CONFIG_SYS_OR3_PRELIM=0xF0000050
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
diff --git a/configs/kmtepr2_defconfig b/configs/kmtepr2_defconfig
index a0cca5b9f280..942161bcce26 100644
--- a/configs/kmtepr2_defconfig
+++ b/configs/kmtepr2_defconfig
@@ -177,18 +177,6 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xF0001001
-CONFIG_SYS_OR0_PRELIM=0xF0000E55
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE8000801
-CONFIG_SYS_OR1_PRELIM=0xF8000E25
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xA0000801
-CONFIG_SYS_OR2_PRELIM=0xF0000C25
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xB0001001
-CONFIG_SYS_OR3_PRELIM=0xF0000040
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
diff --git a/configs/socrates_defconfig b/configs/socrates_defconfig
index 2abb81c53b49..d0001045c4dd 100644
--- a/configs/socrates_defconfig
+++ b/configs/socrates_defconfig
@@ -51,18 +51,6 @@ CONFIG_USE_ETHPRIME=y
CONFIG_ETHPRIME="TSEC0"
CONFIG_DM=y
CONFIG_CHIP_SELECTS_PER_CTRL=2
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xFE001001
-CONFIG_SYS_OR0_PRELIM=0xFE000030
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xFC001001
-CONFIG_SYS_OR1_PRELIM=0xFE000030
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xC80018A1
-CONFIG_SYS_OR2_PRELIM=0xFC000000
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xC0001881
-CONFIG_SYS_OR3_PRELIM=0xFFF00000
CONFIG_DM_I2C=y
CONFIG_SYS_I2C_FSL=y
# CONFIG_MMC is not set
diff --git a/configs/tuge1_defconfig b/configs/tuge1_defconfig
index 11f8b5b10516..ec9b3108f9c9 100644
--- a/configs/tuge1_defconfig
+++ b/configs/tuge1_defconfig
@@ -157,15 +157,6 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xF0001001
-CONFIG_SYS_OR0_PRELIM=0xF0000E55
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE8000801
-CONFIG_SYS_OR1_PRELIM=0xF8000E25
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xA0000801
-CONFIG_SYS_OR2_PRELIM=0xF0000C25
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
diff --git a/configs/tuxx1_defconfig b/configs/tuxx1_defconfig
index c25366406219..b16936b43ae7 100644
--- a/configs/tuxx1_defconfig
+++ b/configs/tuxx1_defconfig
@@ -179,18 +179,6 @@ CONFIG_VERSION_VARIABLE=y
CONFIG_BOOTCOUNT_LIMIT=y
CONFIG_DM_BOOTCOUNT=y
CONFIG_BOOTCOUNT_MEM=y
-CONFIG_SYS_BR0_PRELIM_BOOL=y
-CONFIG_SYS_BR0_PRELIM=0xF0001001
-CONFIG_SYS_OR0_PRELIM=0xF0000E55
-CONFIG_SYS_BR1_PRELIM_BOOL=y
-CONFIG_SYS_BR1_PRELIM=0xE8000801
-CONFIG_SYS_OR1_PRELIM=0xF8000E25
-CONFIG_SYS_BR2_PRELIM_BOOL=y
-CONFIG_SYS_BR2_PRELIM=0xA0000801
-CONFIG_SYS_OR2_PRELIM=0xF0000C25
-CONFIG_SYS_BR3_PRELIM_BOOL=y
-CONFIG_SYS_BR3_PRELIM=0xB0000801
-CONFIG_SYS_OR3_PRELIM=0xF0000E24
CONFIG_SYS_I2C_LEGACY=y
CONFIG_SYS_I2C_FSL=y
CONFIG_SYS_FSL_I2C_OFFSET=0x3000
diff --git a/drivers/ddr/fsl/Kconfig b/drivers/ddr/fsl/Kconfig
index 5925fe9e287c..4c6d2929967e 100644
--- a/drivers/ddr/fsl/Kconfig
+++ b/drivers/ddr/fsl/Kconfig
@@ -171,98 +171,6 @@ config ECC_INIT_VIA_DDRCONTROLLER
endif
-menu "PowerPC / M68K initial memory controller definitions (FLASH, SDRAM, etc)"
- depends on MCF52x2 || MPC8xx || MPC83xx || MPC85xx
-
-config SYS_BR0_PRELIM_BOOL
- bool "Define Bank 0"
-
-config SYS_BR0_PRELIM
- hex "Preliminary value for BR0"
- depends on SYS_BR0_PRELIM_BOOL
-
-config SYS_OR0_PRELIM
- hex "Preliminary value for OR0"
- depends on SYS_BR0_PRELIM_BOOL
-
-config SYS_BR1_PRELIM_BOOL
- bool "Define Bank 1"
-
-config SYS_BR1_PRELIM
- hex "Preliminary value for BR1"
- depends on SYS_BR1_PRELIM_BOOL
-
-config SYS_OR1_PRELIM
- hex "Preliminary value for OR1"
- depends on SYS_BR1_PRELIM_BOOL
-
-config SYS_BR2_PRELIM_BOOL
- bool "Define Bank 2"
-
-config SYS_BR2_PRELIM
- hex "Preliminary value for BR2"
- depends on SYS_BR2_PRELIM_BOOL
-
-config SYS_OR2_PRELIM
- hex "Preliminary value for OR2"
- depends on SYS_BR2_PRELIM_BOOL
-
-config SYS_BR3_PRELIM_BOOL
- bool "Define Bank 3"
-
-config SYS_BR3_PRELIM
- hex "Preliminary value for BR3"
- depends on SYS_BR3_PRELIM_BOOL
-
-config SYS_OR3_PRELIM
- hex "Preliminary value for OR3"
- depends on SYS_BR3_PRELIM_BOOL
-
-config SYS_BR4_PRELIM_BOOL
- bool "Define Bank 4"
-
-config SYS_BR4_PRELIM
- hex "Preliminary value for BR4"
- depends on SYS_BR4_PRELIM_BOOL
-
-config SYS_OR4_PRELIM
- hex "Preliminary value for OR4"
- depends on SYS_BR4_PRELIM_BOOL
-
-config SYS_BR5_PRELIM_BOOL
- bool "Define Bank 5"
-
-config SYS_BR5_PRELIM
- hex "Preliminary value for BR5"
- depends on SYS_BR5_PRELIM_BOOL
-
-config SYS_OR5_PRELIM
- hex "Preliminary value for OR5"
- depends on SYS_BR5_PRELIM_BOOL
-
-config SYS_BR6_PRELIM_BOOL
- bool "Define Bank 6"
-
-config SYS_BR6_PRELIM
- hex "Preliminary value for BR6"
- depends on SYS_BR6_PRELIM_BOOL
-
-config SYS_OR6_PRELIM
- hex "Preliminary value for OR6"
- depends on SYS_BR6_PRELIM_BOOL
-
-config SYS_BR7_PRELIM_BOOL
- bool "Define Bank 7"
-
-config SYS_BR7_PRELIM
- hex "Preliminary value for BR7"
- depends on SYS_BR7_PRELIM_BOOL
-
-config SYS_OR7_PRELIM
- hex "Preliminary value for OR7"
- depends on SYS_BR7_PRELIM_BOOL
-endmenu
-
config SYS_FSL_ERRATUM_A008378
bool
diff --git a/include/configs/M5272C3.h b/include/configs/M5272C3.h
index b8918680c14a..6c271e1b3358 100644
--- a/include/configs/M5272C3.h
+++ b/include/configs/M5272C3.h
@@ -124,6 +124,26 @@
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ */
+#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
+#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
+#define CONFIG_SYS_BR1_PRELIM 0
+#define CONFIG_SYS_OR1_PRELIM 0
+#define CONFIG_SYS_BR2_PRELIM 0x30000001
+#define CONFIG_SYS_OR2_PRELIM 0xFFF80000
+#define CONFIG_SYS_BR3_PRELIM 0
+#define CONFIG_SYS_OR3_PRELIM 0
+#define CONFIG_SYS_BR4_PRELIM 0
+#define CONFIG_SYS_OR4_PRELIM 0
+#define CONFIG_SYS_BR5_PRELIM 0
+#define CONFIG_SYS_OR5_PRELIM 0
+#define CONFIG_SYS_BR6_PRELIM 0
+#define CONFIG_SYS_OR6_PRELIM 0
+#define CONFIG_SYS_BR7_PRELIM 0x00000701
+#define CONFIG_SYS_OR7_PRELIM 0xFFC0007C
+
/*-----------------------------------------------------------------------
* Port configuration
*/
diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h
index 244f811ff65b..46b651c7f54e 100644
--- a/include/configs/MPC8548CDS.h
+++ b/include/configs/MPC8548CDS.h
@@ -127,6 +127,14 @@
#define CONFIG_SYS_FLASH_BASE_PHYS CONFIG_SYS_FLASH_BASE
#endif
+#define CONFIG_SYS_BR0_PRELIM \
+ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x800000) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_BR1_PRELIM \
+ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+
+#define CONFIG_SYS_OR0_PRELIM 0xff806e65
+#define CONFIG_SYS_OR1_PRELIM 0xff806e65
+
#define CONFIG_SYS_FLASH_BANKS_LIST \
{CONFIG_SYS_FLASH_BASE_PHYS + 0x800000, CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_MAX_FLASH_SECT 128 /* sectors per device */
@@ -167,6 +175,10 @@
* FIXME: the top 17 bits of BR2.
*/
+#define CONFIG_SYS_BR2_PRELIM \
+ (BR_PHYS_ADDR(CONFIG_SYS_LBC_SDRAM_BASE_PHYS) \
+ | BR_PS_32 | (3<<BR_MSEL_SHIFT) | BR_V)
+
/*
* The SDRAM size in MB, CONFIG_SYS_LBC_SDRAM_SIZE, is 64.
*
@@ -181,6 +193,8 @@
* 1111 1100 0000 0000 0110 1001 0000 0001 = fc006901
*/
+#define CONFIG_SYS_OR2_PRELIM 0xfc006901
+
#define CONFIG_SYS_LBC_LCRR 0x00030004 /* LB clock ratio reg */
#define CONFIG_SYS_LBC_LBCR 0x00000000 /* LB config reg */
#define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
@@ -239,6 +253,9 @@
#else
#define CADMUS_BASE_ADDR_PHYS CADMUS_BASE_ADDR
#endif
+#define CONFIG_SYS_BR3_PRELIM \
+ (BR_PHYS_ADDR(CADMUS_BASE_ADDR_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM 0xfff00ff7
#define CONFIG_SYS_INIT_RAM_LOCK 1
#define CONFIG_SYS_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 3d9e3e1c78b7..687b88bd2abd 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -129,6 +129,9 @@
#define CPLD_BASE_PHYS CPLD_BASE
#endif
+#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(CPLD_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
+
#define PIXIS_LBMAP_SWITCH 7
#define PIXIS_LBMAP_MASK 0xf0
#define PIXIS_LBMAP_SHIFT 4
@@ -171,6 +174,21 @@
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
+
+#ifdef CONFIG_MTD_RAW_NAND
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+#else
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_SYS_FLASH_EMPTY_INFO
diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h
index 1822ce5120ac..3d49a15232b5 100644
--- a/include/configs/cobra5272.h
+++ b/include/configs/cobra5272.h
@@ -222,6 +222,36 @@ enter a valid image address in flash */
CF_CACR_CEIB | CF_CACR_DCM | \
CF_CACR_EUSP)
+/*-----------------------------------------------------------------------
+ * Memory bank definitions
+ *
+ * Please refer also to Motorola Coldfire user manual - Chapter XXX
+ * <http://e-www.motorola.com/files/dsp/doc/ref_manual/MCF5272UM.pdf>
+ */
+#define CONFIG_SYS_BR0_PRELIM 0xFFE00201
+#define CONFIG_SYS_OR0_PRELIM 0xFFE00014
+
+#define CONFIG_SYS_BR1_PRELIM 0
+#define CONFIG_SYS_OR1_PRELIM 0
+
+#define CONFIG_SYS_BR2_PRELIM 0
+#define CONFIG_SYS_OR2_PRELIM 0
+
+#define CONFIG_SYS_BR3_PRELIM 0
+#define CONFIG_SYS_OR3_PRELIM 0
+
+#define CONFIG_SYS_BR4_PRELIM 0
+#define CONFIG_SYS_OR4_PRELIM 0
+
+#define CONFIG_SYS_BR5_PRELIM 0
+#define CONFIG_SYS_OR5_PRELIM 0
+
+#define CONFIG_SYS_BR6_PRELIM 0
+#define CONFIG_SYS_OR6_PRELIM 0
+
+#define CONFIG_SYS_BR7_PRELIM 0x00000701
+#define CONFIG_SYS_OR7_PRELIM 0xFF00007C
+
/*-----------------------------------------------------------------------
* LED config
*/
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 121963fe5ce5..9108f206b696 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -120,6 +120,10 @@
#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
+#define CONFIG_SYS_BR1_PRELIM \
+ (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) | BR_PS_16 | BR_V)
+#define CONFIG_SYS_OR1_PRELIM 0xf8000ff7
+
#define PIXIS_BASE 0xffdf0000 /* PIXIS registers */
#ifdef CONFIG_PHYS_64BIT
#define PIXIS_BASE_PHYS 0xfffdf0000ull
@@ -127,6 +131,9 @@
#define PIXIS_BASE_PHYS PIXIS_BASE
#endif
+#define CONFIG_SYS_BR3_PRELIM (BR_PHYS_ADDR(PIXIS_BASE_PHYS) | BR_PS_8 | BR_V)
+#define CONFIG_SYS_OR3_PRELIM 0xffffeff7 /* 32KB but only 4k mapped */
+
#define PIXIS_LBMAP_SWITCH 7
#define PIXIS_LBMAP_MASK 0xf0
#define PIXIS_LBMAP_SHIFT 4
@@ -169,6 +176,21 @@
| OR_FCM_SCY_1 \
| OR_FCM_TRLX \
| OR_FCM_EHTR)
+
+#ifdef CONFIG_MTD_RAW_NAND
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
+#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Address */
+#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+#else
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_FLASH_OR_PRELIM /* NOR Options */
#endif /* CONFIG_NAND_FSL_ELBC */
#define CONFIG_SYS_FLASH_EMPTY_INFO
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index f6ecf2a7a8b8..648d941c59b2 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -332,6 +332,22 @@
OR_GPCM_SCY | OR_GPCM_TRLX | OR_GPCM_EHTR | \
OR_GPCM_EAD)
+#ifdef CONFIG_MTD_RAW_NAND
+#define CONFIG_SYS_BR0_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#define CONFIG_SYS_BR1_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR1_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
+#else
+#define CONFIG_SYS_BR0_PRELIM CONFIG_FLASH_BR_PRELIM /* NOR Base Address */
+#define CONFIG_SYS_OR0_PRELIM CONFIG_FLASH_OR_PRELIM /* NOR Options */
+#ifdef CONFIG_NAND_FSL_ELBC
+#define CONFIG_SYS_BR1_PRELIM CONFIG_SYS_NAND_BR_PRELIM /* NAND Base Addr */
+#define CONFIG_SYS_OR1_PRELIM CONFIG_SYS_NAND_OR_PRELIM /* NAND Options */
+#endif
+#endif
+#define CONFIG_SYS_BR3_PRELIM CONFIG_CPLD_BR_PRELIM /* CPLD Base Address */
+#define CONFIG_SYS_OR3_PRELIM CONFIG_CPLD_OR_PRELIM /* CPLD Options */
+
/* Vsc7385 switch */
#ifdef CONFIG_VSC7385_ENET
#define __VSCFW_ADDR "vscfw_addr=ef000000\0"
@@ -349,6 +365,9 @@
OR_GPCM_XACS | OR_GPCM_SCY_15 | OR_GPCM_SETA | \
OR_GPCM_TRLX | OR_GPCM_EHTR | OR_GPCM_EAD)
+#define CONFIG_SYS_BR2_PRELIM CONFIG_SYS_VSC7385_BR_PRELIM
+#define CONFIG_SYS_OR2_PRELIM CONFIG_SYS_VSC7385_OR_PRELIM
+
/* The size of the VSC7385 firmware image */
#define CONFIG_VSC7385_IMAGE_SIZE 8192
#endif
diff --git a/include/configs/socrates.h b/include/configs/socrates.h
index daba8278c6a3..2644fca25573 100644
--- a/include/configs/socrates.h
+++ b/include/configs/socrates.h
@@ -89,6 +89,11 @@
#define CONFIG_SYS_LBC_FLASH_BASE CONFIG_SYS_FLASH1 /* Localbus flash start */
#define CONFIG_SYS_FLASH_BASE CONFIG_SYS_LBC_FLASH_BASE /* start of FLASH */
+#define CONFIG_SYS_BR0_PRELIM 0xfe001001 /* port size 16bit */
+#define CONFIG_SYS_OR0_PRELIM 0xfe000030 /* 32MB Flash */
+#define CONFIG_SYS_BR1_PRELIM 0xfc001001 /* port size 16bit */
+#define CONFIG_SYS_OR1_PRELIM 0xfe000030 /* 32MB Flash */
+
#define CONFIG_SYS_MAX_FLASH_SECT 256 /* sectors per device */
#undef CONFIG_SYS_FLASH_CHECKSUM
#define CONFIG_SYS_FLASH_ERASE_TOUT 60000 /* Flash Erase Timeout (ms) */
@@ -112,6 +117,8 @@
#define CONFIG_SYS_FPGA_BASE 0xc0000000
#define CONFIG_SYS_FPGA_SIZE 0x00100000 /* 1 MB */
#define CONFIG_SYS_HMI_BASE 0xc0010000
+#define CONFIG_SYS_BR3_PRELIM 0xc0001881 /* UPMA, 32-bit */
+#define CONFIG_SYS_OR3_PRELIM 0xfff00000 /* 1 MB */
#define CONFIG_SYS_NAND_BASE (CONFIG_SYS_FPGA_BASE + 0x70)
#define CONFIG_SYS_MAX_NAND_DEVICE 1
@@ -119,6 +126,8 @@
/* LIME GDC */
#define CONFIG_SYS_LIME_BASE 0xc8000000
#define CONFIG_SYS_LIME_SIZE 0x04000000 /* 64 MB */
+#define CONFIG_SYS_BR2_PRELIM 0xc80018a1 /* UPMB, 32-bit */
+#define CONFIG_SYS_OR2_PRELIM 0xfc000000 /* 64 MB */
#define CONFIG_SYS_SPD_BUS_NUM 0
diff --git a/scripts/config_whitelist.txt b/scripts/config_whitelist.txt
index 5b882b2670ca..f11b764d8b11 100644
--- a/scripts/config_whitelist.txt
+++ b/scripts/config_whitelist.txt
@@ -13,6 +13,8 @@ CONFIG_BS_HDR_ADDR_RAM
CONFIG_BS_HDR_SIZE
CONFIG_BS_SIZE
CONFIG_CHAIN_BOOT_CMD
+CONFIG_CPLD_BR_PRELIM
+CONFIG_CPLD_OR_PRELIM
CONFIG_DEFAULT
CONFIG_DFU_ALT
CONFIG_DFU_ALT_BOOT_EMMC
@@ -659,6 +661,14 @@ CONFIG_SYS_BOOTM_LEN
CONFIG_SYS_BOOTPARAMS_LEN
CONFIG_SYS_BOOT_BLOCK
CONFIG_SYS_BOOT_RAMDISK_HIGH
+CONFIG_SYS_BR0_PRELIM
+CONFIG_SYS_BR1_PRELIM
+CONFIG_SYS_BR2_PRELIM
+CONFIG_SYS_BR3_PRELIM
+CONFIG_SYS_BR4_PRELIM
+CONFIG_SYS_BR5_PRELIM
+CONFIG_SYS_BR6_PRELIM
+CONFIG_SYS_BR7_PRELIM
CONFIG_SYS_CACHE_ACR0
CONFIG_SYS_CACHE_ACR1
CONFIG_SYS_CACHE_ACR2
@@ -1413,6 +1423,14 @@ CONFIG_SYS_OHCI_SWAP_REG_ACCESS
CONFIG_SYS_OMAP_ABE_SYSCK
CONFIG_SYS_ONENAND_BASE
CONFIG_SYS_ONENAND_BLOCK_SIZE
+CONFIG_SYS_OR0_PRELIM
+CONFIG_SYS_OR1_PRELIM
+CONFIG_SYS_OR2_PRELIM
+CONFIG_SYS_OR3_PRELIM
+CONFIG_SYS_OR4_PRELIM
+CONFIG_SYS_OR5_PRELIM
+CONFIG_SYS_OR6_PRELIM
+CONFIG_SYS_OR7_PRELIM
CONFIG_SYS_OR_TIMING_MRAM
CONFIG_SYS_OSCIN_FREQ
CONFIG_SYS_OSPR_OFFSET
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 2/6] Revert "p1_p2_rdb: Remove CONFIG_CPLD_[BO]R_PRELIM"
2022-05-01 14:23 [PATCH 0/6] board: freescale: p1_p2_rdb_pc: Fix sizes of LBC peripherals Pali Rohár
2022-05-01 14:23 ` [PATCH 1/6] Revert "Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig" Pali Rohár
@ 2022-05-01 14:23 ` Pali Rohár
2022-05-01 14:38 ` Tom Rini
2022-05-01 14:23 ` [PATCH 3/6] mpc85xx: Replace magic values in BR/OR PRELIM config options by proper C macros Pali Rohár
` (3 subsequent siblings)
5 siblings, 1 reply; 16+ messages in thread
From: Pali Rohár @ 2022-05-01 14:23 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
This reverts commit 53f2222c71df0fce21d403400a9bc1532e08107c.
These macros and their values are required for configuring CPLD memory
mapping in LBC. So revert them back.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
include/configs/p1_p2_rdb_pc.h | 3 +++
1 file changed, 3 insertions(+)
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 648d941c59b2..9726ef3077f7 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -323,6 +323,9 @@
#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
#endif
/* CPLD config size: 1Mb */
+#define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
+ BR_PS_8 | BR_V)
+#define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
#define CONFIG_SYS_PMC_BASE 0xff980000
#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 3/6] mpc85xx: Replace magic values in BR/OR PRELIM config options by proper C macros
2022-05-01 14:23 [PATCH 0/6] board: freescale: p1_p2_rdb_pc: Fix sizes of LBC peripherals Pali Rohár
2022-05-01 14:23 ` [PATCH 1/6] Revert "Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig" Pali Rohár
2022-05-01 14:23 ` [PATCH 2/6] Revert "p1_p2_rdb: Remove CONFIG_CPLD_[BO]R_PRELIM" Pali Rohár
@ 2022-05-01 14:23 ` Pali Rohár
2022-05-01 14:23 ` [PATCH 4/6] board: freescale: p1_p2_rdb_pc: Fix size of CPLD mapping Pali Rohár
` (2 subsequent siblings)
5 siblings, 0 replies; 16+ messages in thread
From: Pali Rohár @ 2022-05-01 14:23 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
This change allows to understand how are Preliminary Base and Option
registers configured and later fix improper configuration.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
include/configs/P2041RDB.h | 7 ++++---
include/configs/corenet_ds.h | 8 +++++---
include/configs/p1_p2_rdb_pc.h | 11 ++++++++---
3 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/include/configs/P2041RDB.h b/include/configs/P2041RDB.h
index 687b88bd2abd..c2d7c76f6063 100644
--- a/include/configs/P2041RDB.h
+++ b/include/configs/P2041RDB.h
@@ -118,7 +118,8 @@
(BR_PHYS_ADDR((CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000)) | \
BR_PS_16 | BR_V)
#define CONFIG_SYS_FLASH_OR_PRELIM \
- ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
+ (OR_AM_128MB | OR_GPCM_CSNT | OR_GPCM_ACS_DIV2 \
+ | OR_GPCM_XACS | OR_GPCM_TRLX | OR_GPCM_EAD \
| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
#define CONFIG_FSL_CPLD
@@ -162,11 +163,11 @@
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_DECC_CHK_GEN /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
diff --git a/include/configs/corenet_ds.h b/include/configs/corenet_ds.h
index 9108f206b696..c908269b24c7 100644
--- a/include/configs/corenet_ds.h
+++ b/include/configs/corenet_ds.h
@@ -117,7 +117,9 @@
#define CONFIG_SYS_FLASH_BR_PRELIM \
(BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS + 0x8000000) \
| BR_PS_16 | BR_V)
-#define CONFIG_SYS_FLASH_OR_PRELIM ((0xf8000ff7 & ~OR_GPCM_SCY & ~OR_GPCM_EHTR) \
+#define CONFIG_SYS_FLASH_OR_PRELIM (OR_AM_128MB | OR_GPCM_CSNT | \
+ | OR_GPCM_ACS_DIV2 | OR_GPCM_XACS \
+ | OR_GPCM_TRLX | OR_GPCM_EAD \
| OR_GPCM_SCY_8 | OR_GPCM_EHTR_CLEAR)
#define CONFIG_SYS_BR1_PRELIM \
@@ -164,11 +166,11 @@
/* NAND flash config */
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_DECC_CHK_GEN /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
-#define CONFIG_SYS_NAND_OR_PRELIM (0xFFFC0000 /* length 256K */ \
+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB /* length 256K */ \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 9726ef3077f7..b567eb1a03cc 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -243,7 +243,10 @@
#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
| BR_PS_16 | BR_V)
-#define CONFIG_FLASH_OR_PRELIM 0xfc000ff7
+#define CONFIG_FLASH_OR_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | \
+ OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | \
+ OR_GPCM_SCY_15 | OR_GPCM_TRLX | \
+ OR_GPCM_EHTR | OR_GPCM_EAD)
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_QUIET_TEST
@@ -268,7 +271,7 @@
#define CONFIG_SYS_MAX_NAND_DEVICE 1
#define CONFIG_SYS_NAND_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_NAND_BASE_PHYS) \
- | (2<<BR_DECC_SHIFT) /* Use HW ECC */ \
+ | BR_DECC_CHK_GEN /* Use HW ECC */ \
| BR_PS_8 /* Port Size = 8 bit */ \
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
@@ -325,7 +328,9 @@
/* CPLD config size: 1Mb */
#define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
BR_PS_8 | BR_V)
-#define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
+#define CONFIG_CPLD_OR_PRELIM (OR_AM_1MB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+ OR_GPCM_SCY_15 | OR_GPCM_TRLX | \
+ OR_GPCM_EHTR | OR_GPCM_EAD)
#define CONFIG_SYS_PMC_BASE 0xff980000
#define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 4/6] board: freescale: p1_p2_rdb_pc: Fix size of CPLD mapping
2022-05-01 14:23 [PATCH 0/6] board: freescale: p1_p2_rdb_pc: Fix sizes of LBC peripherals Pali Rohár
` (2 preceding siblings ...)
2022-05-01 14:23 ` [PATCH 3/6] mpc85xx: Replace magic values in BR/OR PRELIM config options by proper C macros Pali Rohár
@ 2022-05-01 14:23 ` Pali Rohár
2022-05-01 14:23 ` [PATCH 5/6] board: freescale: p1_p2_rdb_pc: Fix size of FLASH NOR mapping Pali Rohár
2022-05-01 14:23 ` [PATCH 6/6] board: freescale: p1_p2_rdb_pc: Fix size of NAND mapping Pali Rohár
5 siblings, 0 replies; 16+ messages in thread
From: Pali Rohár @ 2022-05-01 14:23 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
Per Freescale P1021RDB Combo board CPLD Specification V4.2, CPLD memory
space on all these P1/P2 RDB-PC boards, which use Lattice FPGA for CPLD
implementation, is only 128 kB long.
So decrease mapping size from 1 MB to 128 kB.
Note that E500 core, which is on P1/P2 boards does not support Book-E page
size of 128 kB. It ignores lowest bit in size definition, so macro
BOOKE_PAGESZ_128K has same effect as BOOKE_PAGESZ_64K. Therefore for TLB
entry use BOOKE_PAGESZ_256K to cover whole 128 kB of CPLD memory space.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
board/freescale/p1_p2_rdb_pc/law.c | 2 +-
board/freescale/p1_p2_rdb_pc/tlb.c | 3 ++-
include/configs/p1_p2_rdb_pc.h | 6 +++---
3 files changed, 6 insertions(+), 5 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
index 5f4d713ca569..901145ded3b0 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -8,7 +8,7 @@
#include <asm/mmu.h>
struct law_entry law_table[] = {
- SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
+ SET_LAW(CONFIG_SYS_CPLD_BASE_PHYS, LAW_SIZE_128K, LAW_TRGT_IF_LBC),
SET_LAW(CONFIG_SYS_PMC_BASE_PHYS, LAW_SIZE_64K, LAW_TRGT_IF_LBC),
#ifdef CONFIG_VSC7385_ENET
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 5931ec650bd8..ca47e15067a4 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -62,9 +62,10 @@ struct fsl_e_tlb_entry tlb_table[] = {
0, 5, BOOKE_PAGESZ_1M, 1),
#endif
+ /* *I*G - CPLD 256K (effective only 128K; e500 does not support BOOKE_PAGESZ_128K) */
SET_TLB_ENTRY(1, CONFIG_SYS_CPLD_BASE, CONFIG_SYS_CPLD_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 6, BOOKE_PAGESZ_1M, 1),
+ 0, 6, BOOKE_PAGESZ_256K, 1),
SET_TLB_ENTRY(1, CONFIG_SYS_PMC_BASE, CONFIG_SYS_PMC_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
0, 10, BOOKE_PAGESZ_64K, 1),
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index b567eb1a03cc..69fbb4ad8fe4 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -216,7 +216,7 @@
* (early boot only)
* 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
* 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
- * 0xffa0_0000 0xffaf_ffff CPLD 1M non-cacheable CS3
+ * 0xffa0_0000 0xffa1_ffff CPLD 128K non-cacheable CS3
* 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
* 0xffc0_0000 0xffc3_ffff PCI IO range 256k non-cacheable
* 0xffd0_0000 0xffd0_3fff L1 for stack 16K cacheable
@@ -325,10 +325,10 @@
#else
#define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
#endif
-/* CPLD config size: 1Mb */
+/* CPLD config size: 128 kB */
#define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
BR_PS_8 | BR_V)
-#define CONFIG_CPLD_OR_PRELIM (OR_AM_1MB | OR_GPCM_CSNT | OR_GPCM_XACS | \
+#define CONFIG_CPLD_OR_PRELIM (OR_AM_128KB | OR_GPCM_CSNT | OR_GPCM_XACS | \
OR_GPCM_SCY_15 | OR_GPCM_TRLX | \
OR_GPCM_EHTR | OR_GPCM_EAD)
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 5/6] board: freescale: p1_p2_rdb_pc: Fix size of FLASH NOR mapping
2022-05-01 14:23 [PATCH 0/6] board: freescale: p1_p2_rdb_pc: Fix sizes of LBC peripherals Pali Rohár
` (3 preceding siblings ...)
2022-05-01 14:23 ` [PATCH 4/6] board: freescale: p1_p2_rdb_pc: Fix size of CPLD mapping Pali Rohár
@ 2022-05-01 14:23 ` Pali Rohár
2022-05-01 14:23 ` [PATCH 6/6] board: freescale: p1_p2_rdb_pc: Fix size of NAND mapping Pali Rohár
5 siblings, 0 replies; 16+ messages in thread
From: Pali Rohár @ 2022-05-01 14:23 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
FLASH NOR on P1020RDB-PD has size of 64 MB. On all other P1/P2 RDB boards
it has only size of 16 MB. So fix this size in TLB, LAW and LBC OR
registers.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
board/freescale/p1_p2_rdb_pc/law.c | 4 ++++
board/freescale/p1_p2_rdb_pc/tlb.c | 6 ++++++
include/configs/p1_p2_rdb_pc.h | 7 +++++++
3 files changed, 17 insertions(+)
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
index 901145ded3b0..80adf21a1183 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -13,7 +13,11 @@ struct law_entry law_table[] = {
#ifdef CONFIG_VSC7385_ENET
SET_LAW(CONFIG_SYS_VSC7385_BASE_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_LBC),
#endif
+#ifdef CONFIG_TARGET_P1020RDB_PD
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_64M, LAW_TRGT_IF_LBC),
+#else
+ SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
+#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
#endif
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index ca47e15067a4..5bbeae302ad0 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -39,9 +39,15 @@ struct fsl_e_tlb_entry tlb_table[] = {
#ifndef CONFIG_SPL_BUILD
/* W**G* - Flash/promjet, localbus */
/* This will be changed to *I*G* after relocation to RAM. */
+#ifdef CONFIG_TARGET_P1020RDB_PD
SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
0, 2, BOOKE_PAGESZ_64M, 1),
+#else
+ SET_TLB_ENTRY(1, CONFIG_SYS_FLASH_BASE, CONFIG_SYS_FLASH_BASE_PHYS,
+ MAS3_SX|MAS3_SR, MAS2_W|MAS2_G,
+ 0, 2, BOOKE_PAGESZ_16M, 1),
+#endif
#ifdef CONFIG_PCI
/* *I*G* - PCI memory 1.5G */
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index 69fbb4ad8fe4..cf84f4045538 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -243,10 +243,17 @@
#define CONFIG_FLASH_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_FLASH_BASE_PHYS) \
| BR_PS_16 | BR_V)
+#if defined(CONFIG_TARGET_P1020RDB_PD)
#define CONFIG_FLASH_OR_PRELIM (OR_AM_64MB | OR_GPCM_CSNT | \
OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | \
OR_GPCM_SCY_15 | OR_GPCM_TRLX | \
OR_GPCM_EHTR | OR_GPCM_EAD)
+#else
+#define CONFIG_FLASH_OR_PRELIM (OR_AM_16MB | OR_GPCM_CSNT | \
+ OR_GPCM_ACS_DIV2 | OR_GPCM_XACS | \
+ OR_GPCM_SCY_15 | OR_GPCM_TRLX | \
+ OR_GPCM_EHTR | OR_GPCM_EAD)
+#endif
#define CONFIG_SYS_FLASH_BANKS_LIST {CONFIG_SYS_FLASH_BASE_PHYS}
#define CONFIG_SYS_FLASH_QUIET_TEST
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* [PATCH 6/6] board: freescale: p1_p2_rdb_pc: Fix size of NAND mapping
2022-05-01 14:23 [PATCH 0/6] board: freescale: p1_p2_rdb_pc: Fix sizes of LBC peripherals Pali Rohár
` (4 preceding siblings ...)
2022-05-01 14:23 ` [PATCH 5/6] board: freescale: p1_p2_rdb_pc: Fix size of FLASH NOR mapping Pali Rohár
@ 2022-05-01 14:23 ` Pali Rohár
5 siblings, 0 replies; 16+ messages in thread
From: Pali Rohár @ 2022-05-01 14:23 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
P1020RDB-PD has NAND with large page. All other P1/P2 RDB boards have NAND
with small page. According to P1/P2 RM documentation, for NAND with large
page it is needed to use 256 kB mapping and for small page just 32 kB.
Currenly in p1_p2_rdb_pc board code there is a mix of 32 kB and 1 MB
settings which effetively restrict to just 32 kB. Fix this issue and set
TLB, LAW and LBC OR registers which correct mapping size based on the
selected board.
Note that E500 core does not support Book-E page of 32 kB, so choose 64 kB
settings for TLB.
Signed-off-by: Pali Rohár <pali@kernel.org>
---
board/freescale/p1_p2_rdb_pc/law.c | 4 ++++
board/freescale/p1_p2_rdb_pc/tlb.c | 11 +++++++++--
include/configs/p1_p2_rdb_pc.h | 4 ++--
3 files changed, 15 insertions(+), 4 deletions(-)
diff --git a/board/freescale/p1_p2_rdb_pc/law.c b/board/freescale/p1_p2_rdb_pc/law.c
index 80adf21a1183..60672d34e11c 100644
--- a/board/freescale/p1_p2_rdb_pc/law.c
+++ b/board/freescale/p1_p2_rdb_pc/law.c
@@ -19,8 +19,12 @@ struct law_entry law_table[] = {
SET_LAW(CONFIG_SYS_FLASH_BASE_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_LBC),
#endif
#ifdef CONFIG_SYS_NAND_BASE_PHYS
+#ifdef CONFIG_TARGET_P1020RDB_PD
+ SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_256K, LAW_TRGT_IF_LBC),
+#else
SET_LAW(CONFIG_SYS_NAND_BASE_PHYS, LAW_SIZE_32K, LAW_TRGT_IF_LBC),
#endif
+#endif
};
int num_law_entries = ARRAY_SIZE(law_table);
diff --git a/board/freescale/p1_p2_rdb_pc/tlb.c b/board/freescale/p1_p2_rdb_pc/tlb.c
index 5bbeae302ad0..a5b80762f0fc 100644
--- a/board/freescale/p1_p2_rdb_pc/tlb.c
+++ b/board/freescale/p1_p2_rdb_pc/tlb.c
@@ -78,10 +78,17 @@ struct fsl_e_tlb_entry tlb_table[] = {
#endif /* not SPL */
#ifdef CONFIG_SYS_NAND_BASE
- /* *I*G - NAND */
+#ifdef CONFIG_TARGET_P1020RDB_PD
+ /* *I*G - NAND large page 256K */
SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
- 0, 7, BOOKE_PAGESZ_1M, 1),
+ 0, 7, BOOKE_PAGESZ_256K, 1),
+#else
+ /* *I*G - NAND small page 64K (effective only 32K; e500 does not support BOOKE_PAGESZ_32K) */
+ SET_TLB_ENTRY(1, CONFIG_SYS_NAND_BASE, CONFIG_SYS_NAND_BASE_PHYS,
+ MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G,
+ 0, 7, BOOKE_PAGESZ_64K, 1),
+#endif
#endif
#if defined(CONFIG_SYS_RAMBOOT) || \
diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
index cf84f4045538..2ddf768f2c82 100644
--- a/include/configs/p1_p2_rdb_pc.h
+++ b/include/configs/p1_p2_rdb_pc.h
@@ -214,7 +214,7 @@
* 0xec00_0000 0xefff_ffff NOR flash Up to 64M non-cacheable CS0/1
* 0xf8f8_0000 0xf8ff_ffff L2 SRAM Up to 512K cacheable
* (early boot only)
- * 0xff80_0000 0xff80_7fff NAND flash 32K non-cacheable CS1/0
+ * 0xff80_0000 0xff83_ffff NAND flash 32K/256K non-cacheable CS1/0
* 0xff98_0000 0xff98_ffff PMC 64K non-cacheable CS2
* 0xffa0_0000 0xffa1_ffff CPLD 128K non-cacheable CS3
* 0xffb0_0000 0xffbf_ffff VSC7385 switch 1M non-cacheable CS2
@@ -283,7 +283,7 @@
| BR_MS_FCM /* MSEL = FCM */ \
| BR_V) /* valid */
#if defined(CONFIG_TARGET_P1020RDB_PD)
-#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_32KB \
+#define CONFIG_SYS_NAND_OR_PRELIM (OR_AM_256KB \
| OR_FCM_PGS /* Large Page*/ \
| OR_FCM_CSCT \
| OR_FCM_CST \
--
2.20.1
^ permalink raw reply related [flat|nested] 16+ messages in thread
* Re: [PATCH 2/6] Revert "p1_p2_rdb: Remove CONFIG_CPLD_[BO]R_PRELIM"
2022-05-01 14:23 ` [PATCH 2/6] Revert "p1_p2_rdb: Remove CONFIG_CPLD_[BO]R_PRELIM" Pali Rohár
@ 2022-05-01 14:38 ` Tom Rini
2022-05-01 14:40 ` Pali Rohár
0 siblings, 1 reply; 16+ messages in thread
From: Tom Rini @ 2022-05-01 14:38 UTC (permalink / raw)
To: Pali Rohár; +Cc: u-boot
[-- Attachment #1: Type: text/plain, Size: 1101 bytes --]
On Sun, May 01, 2022 at 04:23:53PM +0200, Pali Rohár wrote:
> This reverts commit 53f2222c71df0fce21d403400a9bc1532e08107c.
>
> These macros and their values are required for configuring CPLD memory
> mapping in LBC. So revert them back.
>
> Signed-off-by: Pali Rohár <pali@kernel.org>
> ---
> include/configs/p1_p2_rdb_pc.h | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
> index 648d941c59b2..9726ef3077f7 100644
> --- a/include/configs/p1_p2_rdb_pc.h
> +++ b/include/configs/p1_p2_rdb_pc.h
> @@ -323,6 +323,9 @@
> #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
> #endif
> /* CPLD config size: 1Mb */
> +#define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
> + BR_PS_8 | BR_V)
> +#define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
>
> #define CONFIG_SYS_PMC_BASE 0xff980000
> #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
I'm missing something. I don't see anything when I "git grep
CPLD_.R_PRELIM" so where / how are they referenced?
--
Tom
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/6] Revert "Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig"
2022-05-01 14:23 ` [PATCH 1/6] Revert "Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig" Pali Rohár
@ 2022-05-01 14:39 ` Tom Rini
2022-05-01 14:44 ` Pali Rohár
0 siblings, 1 reply; 16+ messages in thread
From: Tom Rini @ 2022-05-01 14:39 UTC (permalink / raw)
To: Pali Rohár; +Cc: u-boot
[-- Attachment #1: Type: text/plain, Size: 1441 bytes --]
On Sun, May 01, 2022 at 04:23:52PM +0200, Pali Rohár wrote:
> This reverts commit c7fad78ec0ee41b72a58bebb61959570eb937ab1.
>
> This commit made configuration, understanding, maintenance, debugging and
> future development of the powerpc/mpc85xx Local Bus Controller on P1/P2
> boards impossible.
>
> All preliminary Base and Option registers depends on other code and C
> macros generated at C compile time and they comes from the other macros.
>
> For example, NOR base address and NOR options are set via macros
> CONFIG_SYS_FLASH_BR_PRELIM and CONFIG_SYS_FLASH_OR_PRELIM. And then based
> on other logic are filled correct values in to the correct macros
> CONFIG_SYS_BR*_PRELIM and CONFIG_SYS_OR*_PRELIM.
>
> These config options are not user configurable options and therefore
> should not appear in menuconfig. Moreover for P1/P2 boards they have
> nothing with DDR driver, so they should not appear in drivers/ddr.
>
> This change was completely wrong direction, so revert it. It allows to
> start fixing issues with FLASH, NOR, NAND and CPLD LBC configuration.
> In current state it is impossible.
>
> See also thread for more details:
> https://lore.kernel.org/u-boot/20220426181740.o2n7xfg46ytljcdx@pali/t/#u
>
> Signed-off-by: Pali Rohár <pali@kernel.org>
NAK. We are not moving things back in to board config headers under
CONFIG namespace. Some other solution is required.
--
Tom
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 2/6] Revert "p1_p2_rdb: Remove CONFIG_CPLD_[BO]R_PRELIM"
2022-05-01 14:38 ` Tom Rini
@ 2022-05-01 14:40 ` Pali Rohár
0 siblings, 0 replies; 16+ messages in thread
From: Pali Rohár @ 2022-05-01 14:40 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On Sunday 01 May 2022 10:38:31 Tom Rini wrote:
> On Sun, May 01, 2022 at 04:23:53PM +0200, Pali Rohár wrote:
>
> > This reverts commit 53f2222c71df0fce21d403400a9bc1532e08107c.
> >
> > These macros and their values are required for configuring CPLD memory
> > mapping in LBC. So revert them back.
> >
> > Signed-off-by: Pali Rohár <pali@kernel.org>
> > ---
> > include/configs/p1_p2_rdb_pc.h | 3 +++
> > 1 file changed, 3 insertions(+)
> >
> > diff --git a/include/configs/p1_p2_rdb_pc.h b/include/configs/p1_p2_rdb_pc.h
> > index 648d941c59b2..9726ef3077f7 100644
> > --- a/include/configs/p1_p2_rdb_pc.h
> > +++ b/include/configs/p1_p2_rdb_pc.h
> > @@ -323,6 +323,9 @@
> > #define CONFIG_SYS_CPLD_BASE_PHYS CONFIG_SYS_CPLD_BASE
> > #endif
> > /* CPLD config size: 1Mb */
> > +#define CONFIG_CPLD_BR_PRELIM (BR_PHYS_ADDR(CONFIG_SYS_CPLD_BASE_PHYS) | \
> > + BR_PS_8 | BR_V)
> > +#define CONFIG_CPLD_OR_PRELIM (0xfff009f7)
> >
> > #define CONFIG_SYS_PMC_BASE 0xff980000
> > #define CONFIG_SYS_PMC_BASE_PHYS CONFIG_SYS_PMC_BASE
>
> I'm missing something. I don't see anything when I "git grep
> CPLD_.R_PRELIM" so where / how are they referenced?
See other patches in this series. These two macros are used for defining other BR/OR macros.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/6] Revert "Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig"
2022-05-01 14:39 ` Tom Rini
@ 2022-05-01 14:44 ` Pali Rohár
2022-05-01 15:14 ` Tom Rini
0 siblings, 1 reply; 16+ messages in thread
From: Pali Rohár @ 2022-05-01 14:44 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On Sunday 01 May 2022 10:39:39 Tom Rini wrote:
> On Sun, May 01, 2022 at 04:23:52PM +0200, Pali Rohár wrote:
>
> > This reverts commit c7fad78ec0ee41b72a58bebb61959570eb937ab1.
> >
> > This commit made configuration, understanding, maintenance, debugging and
> > future development of the powerpc/mpc85xx Local Bus Controller on P1/P2
> > boards impossible.
> >
> > All preliminary Base and Option registers depends on other code and C
> > macros generated at C compile time and they comes from the other macros.
> >
> > For example, NOR base address and NOR options are set via macros
> > CONFIG_SYS_FLASH_BR_PRELIM and CONFIG_SYS_FLASH_OR_PRELIM. And then based
> > on other logic are filled correct values in to the correct macros
> > CONFIG_SYS_BR*_PRELIM and CONFIG_SYS_OR*_PRELIM.
> >
> > These config options are not user configurable options and therefore
> > should not appear in menuconfig. Moreover for P1/P2 boards they have
> > nothing with DDR driver, so they should not appear in drivers/ddr.
> >
> > This change was completely wrong direction, so revert it. It allows to
> > start fixing issues with FLASH, NOR, NAND and CPLD LBC configuration.
> > In current state it is impossible.
> >
> > See also thread for more details:
> > https://lore.kernel.org/u-boot/20220426181740.o2n7xfg46ytljcdx@pali/t/#u
> >
> > Signed-off-by: Pali Rohár <pali@kernel.org>
>
> NAK. We are not moving things back in to board config headers under
> CONFIG namespace. Some other solution is required.
I spend time on this and I do not see any other solution. As explained
that commit just introduced more issues then what it brought, so it was
step backward, not forward. So please show other solution, if you do not
like this one.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/6] Revert "Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig"
2022-05-01 14:44 ` Pali Rohár
@ 2022-05-01 15:14 ` Tom Rini
2022-05-01 15:33 ` Pali Rohár
0 siblings, 1 reply; 16+ messages in thread
From: Tom Rini @ 2022-05-01 15:14 UTC (permalink / raw)
To: Pali Rohár; +Cc: u-boot
[-- Attachment #1: Type: text/plain, Size: 2282 bytes --]
On Sun, May 01, 2022 at 04:44:16PM +0200, Pali Rohár wrote:
> On Sunday 01 May 2022 10:39:39 Tom Rini wrote:
> > On Sun, May 01, 2022 at 04:23:52PM +0200, Pali Rohár wrote:
> >
> > > This reverts commit c7fad78ec0ee41b72a58bebb61959570eb937ab1.
> > >
> > > This commit made configuration, understanding, maintenance, debugging and
> > > future development of the powerpc/mpc85xx Local Bus Controller on P1/P2
> > > boards impossible.
> > >
> > > All preliminary Base and Option registers depends on other code and C
> > > macros generated at C compile time and they comes from the other macros.
> > >
> > > For example, NOR base address and NOR options are set via macros
> > > CONFIG_SYS_FLASH_BR_PRELIM and CONFIG_SYS_FLASH_OR_PRELIM. And then based
> > > on other logic are filled correct values in to the correct macros
> > > CONFIG_SYS_BR*_PRELIM and CONFIG_SYS_OR*_PRELIM.
> > >
> > > These config options are not user configurable options and therefore
> > > should not appear in menuconfig. Moreover for P1/P2 boards they have
> > > nothing with DDR driver, so they should not appear in drivers/ddr.
> > >
> > > This change was completely wrong direction, so revert it. It allows to
> > > start fixing issues with FLASH, NOR, NAND and CPLD LBC configuration.
> > > In current state it is impossible.
> > >
> > > See also thread for more details:
> > > https://lore.kernel.org/u-boot/20220426181740.o2n7xfg46ytljcdx@pali/t/#u
> > >
> > > Signed-off-by: Pali Rohár <pali@kernel.org>
> >
> > NAK. We are not moving things back in to board config headers under
> > CONFIG namespace. Some other solution is required.
>
> I spend time on this and I do not see any other solution. As explained
> that commit just introduced more issues then what it brought, so it was
> step backward, not forward. So please show other solution, if you do not
> like this one.
Anything that I suggested in the previous thread about moving to board
Kconfig files. Or move it to some other header and out of CONFIG
namespace. Or if dtoc (doc/develop/driver-model/of-plat.rst) isn't
sufficient today to pull out the infos to use at build time, expand it
to cover this case as it would be useful for large numbers of other
cases.
--
Tom
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 659 bytes --]
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/6] Revert "Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig"
2022-05-01 15:14 ` Tom Rini
@ 2022-05-01 15:33 ` Pali Rohár
2022-05-01 16:17 ` Tom Rini
0 siblings, 1 reply; 16+ messages in thread
From: Pali Rohár @ 2022-05-01 15:33 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On Sunday 01 May 2022 11:14:21 Tom Rini wrote:
> On Sun, May 01, 2022 at 04:44:16PM +0200, Pali Rohár wrote:
> > On Sunday 01 May 2022 10:39:39 Tom Rini wrote:
> > > On Sun, May 01, 2022 at 04:23:52PM +0200, Pali Rohár wrote:
> > >
> > > > This reverts commit c7fad78ec0ee41b72a58bebb61959570eb937ab1.
> > > >
> > > > This commit made configuration, understanding, maintenance, debugging and
> > > > future development of the powerpc/mpc85xx Local Bus Controller on P1/P2
> > > > boards impossible.
> > > >
> > > > All preliminary Base and Option registers depends on other code and C
> > > > macros generated at C compile time and they comes from the other macros.
> > > >
> > > > For example, NOR base address and NOR options are set via macros
> > > > CONFIG_SYS_FLASH_BR_PRELIM and CONFIG_SYS_FLASH_OR_PRELIM. And then based
> > > > on other logic are filled correct values in to the correct macros
> > > > CONFIG_SYS_BR*_PRELIM and CONFIG_SYS_OR*_PRELIM.
> > > >
> > > > These config options are not user configurable options and therefore
> > > > should not appear in menuconfig. Moreover for P1/P2 boards they have
> > > > nothing with DDR driver, so they should not appear in drivers/ddr.
> > > >
> > > > This change was completely wrong direction, so revert it. It allows to
> > > > start fixing issues with FLASH, NOR, NAND and CPLD LBC configuration.
> > > > In current state it is impossible.
> > > >
> > > > See also thread for more details:
> > > > https://lore.kernel.org/u-boot/20220426181740.o2n7xfg46ytljcdx@pali/t/#u
> > > >
> > > > Signed-off-by: Pali Rohár <pali@kernel.org>
> > >
> > > NAK. We are not moving things back in to board config headers under
> > > CONFIG namespace. Some other solution is required.
> >
> > I spend time on this and I do not see any other solution. As explained
> > that commit just introduced more issues then what it brought, so it was
> > step backward, not forward. So please show other solution, if you do not
> > like this one.
>
> Anything that I suggested in the previous thread about moving to board
> Kconfig files.
Kconfig does not support evaluating C macros from C header files. So it
would not work.
> Or move it to some other header and out of CONFIG namespace.
This is board specific setting, used by drivers and arch code. So it
needs to be in some board location, like the config header file.
> Or if dtoc (doc/develop/driver-model/of-plat.rst) isn't
> sufficient today to pull out the infos to use at build time, expand it
> to cover this case as it would be useful for large numbers of other
> cases.
This would mean to rewrite completely everything about LBC configuration
and its peripherals. I really do not have energy nor time for it.
There are issues which needs to be fixed first, then some "code cleanup"
and "non-functional" changes could be done.
But that your commit c7fad78ec0ee41b72a58bebb61959570eb937ab1 make it
impossible to do anything with LBC, neither new development, nor doing
bug fixes. So it is in the worst state in which it can be.
That commit has same effect as conservation of the code and putting it
into the state to disallow future development in this area. Because
everybody who wants to touch it, has to first do what you wrote above.
But this is such giant work which nobody is going to do, just for fixing
small bug, which is completely unrelated to that work. And that work is
only refactor/code cleanup which does not bring any functional value.
Nothing so fancy, that somebody would do in spare time.
So I hope that this was not your intension.
^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/6] Revert "Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig"
2022-05-01 15:33 ` Pali Rohár
@ 2022-05-01 16:17 ` Tom Rini
2022-05-12 16:01 ` Tom Rini
0 siblings, 1 reply; 16+ messages in thread
From: Tom Rini @ 2022-05-01 16:17 UTC (permalink / raw)
To: Pali Rohár; +Cc: u-boot
[-- Attachment #1: Type: text/plain, Size: 5177 bytes --]
On Sun, May 01, 2022 at 05:33:19PM +0200, Pali Rohár wrote:
> On Sunday 01 May 2022 11:14:21 Tom Rini wrote:
> > On Sun, May 01, 2022 at 04:44:16PM +0200, Pali Rohár wrote:
> > > On Sunday 01 May 2022 10:39:39 Tom Rini wrote:
> > > > On Sun, May 01, 2022 at 04:23:52PM +0200, Pali Rohár wrote:
> > > >
> > > > > This reverts commit c7fad78ec0ee41b72a58bebb61959570eb937ab1.
> > > > >
> > > > > This commit made configuration, understanding, maintenance, debugging and
> > > > > future development of the powerpc/mpc85xx Local Bus Controller on P1/P2
> > > > > boards impossible.
> > > > >
> > > > > All preliminary Base and Option registers depends on other code and C
> > > > > macros generated at C compile time and they comes from the other macros.
> > > > >
> > > > > For example, NOR base address and NOR options are set via macros
> > > > > CONFIG_SYS_FLASH_BR_PRELIM and CONFIG_SYS_FLASH_OR_PRELIM. And then based
> > > > > on other logic are filled correct values in to the correct macros
> > > > > CONFIG_SYS_BR*_PRELIM and CONFIG_SYS_OR*_PRELIM.
> > > > >
> > > > > These config options are not user configurable options and therefore
> > > > > should not appear in menuconfig. Moreover for P1/P2 boards they have
> > > > > nothing with DDR driver, so they should not appear in drivers/ddr.
> > > > >
> > > > > This change was completely wrong direction, so revert it. It allows to
> > > > > start fixing issues with FLASH, NOR, NAND and CPLD LBC configuration.
> > > > > In current state it is impossible.
> > > > >
> > > > > See also thread for more details:
> > > > > https://lore.kernel.org/u-boot/20220426181740.o2n7xfg46ytljcdx@pali/t/#u
> > > > >
> > > > > Signed-off-by: Pali Rohár <pali@kernel.org>
> > > >
> > > > NAK. We are not moving things back in to board config headers under
> > > > CONFIG namespace. Some other solution is required.
> > >
> > > I spend time on this and I do not see any other solution. As explained
> > > that commit just introduced more issues then what it brought, so it was
> > > step backward, not forward. So please show other solution, if you do not
> > > like this one.
> >
> > Anything that I suggested in the previous thread about moving to board
> > Kconfig files.
>
> Kconfig does not support evaluating C macros from C header files. So it
> would not work.
Document how to derive them using tools like 'printf' when adding more
boards, which should not be a common case anyhow.
> > Or move it to some other header and out of CONFIG namespace.
>
> This is board specific setting, used by drivers and arch code. So it
> needs to be in some board location, like the config header file.
But all include/config/*.h files are destined to be removed, so they
cannot live there. Everything in the CONFIG namespace needs to be in
Kconfig. Nothing outside of CONFIG namespace belongs under
include/configs/.
> > Or if dtoc (doc/develop/driver-model/of-plat.rst) isn't
> > sufficient today to pull out the infos to use at build time, expand it
> > to cover this case as it would be useful for large numbers of other
> > cases.
>
> This would mean to rewrite completely everything about LBC configuration
> and its peripherals. I really do not have energy nor time for it.
Neither apparently has anyone else for the last far far too long.
> There are issues which needs to be fixed first, then some "code cleanup"
> and "non-functional" changes could be done.
>
> But that your commit c7fad78ec0ee41b72a58bebb61959570eb937ab1 make it
> impossible to do anything with LBC, neither new development, nor doing
> bug fixes. So it is in the worst state in which it can be.
How? Derive the correct hex value and put it in.
> That commit has same effect as conservation of the code and putting it
> into the state to disallow future development in this area. Because
> everybody who wants to touch it, has to first do what you wrote above.
Yes. The code is sub-standard and needs improvement.
> But this is such giant work which nobody is going to do, just for fixing
> small bug, which is completely unrelated to that work. And that work is
> only refactor/code cleanup which does not bring any functional value.
> Nothing so fancy, that somebody would do in spare time.
>
> So I hope that this was not your intension.
My intention is to get the PowerPC code up to modern U-Boot standards.
Or, to get it removed since there's not enough interest in maintaining
and updating it.
To re-iterate, I agree that it would be good to construct the values at
build time using macros. No one likes looking at raw magic values. But
for an otherwise dead end platform, documenting how these magic values
are constructed (something under doc/arch/ or doc/board/) for anyone in
the future doing more work is Good Enough for me. Alternatively,
re-working things so that instead of being pulled from
include/configs/board-config.h they come from board/.../something.h is
Good Enough, so long as they are NOT using the CONFIG prefix. They can
use CFG_ or just LBC_ or anything else that makes sense.
--
Tom
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/6] Revert "Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig"
2022-05-01 16:17 ` Tom Rini
@ 2022-05-12 16:01 ` Tom Rini
2022-05-12 16:05 ` Pali Rohár
0 siblings, 1 reply; 16+ messages in thread
From: Tom Rini @ 2022-05-12 16:01 UTC (permalink / raw)
To: Pali Rohár; +Cc: u-boot
[-- Attachment #1: Type: text/plain, Size: 5811 bytes --]
On Sun, May 01, 2022 at 12:17:51PM -0400, Tom Rini wrote:
> On Sun, May 01, 2022 at 05:33:19PM +0200, Pali Rohár wrote:
> > On Sunday 01 May 2022 11:14:21 Tom Rini wrote:
> > > On Sun, May 01, 2022 at 04:44:16PM +0200, Pali Rohár wrote:
> > > > On Sunday 01 May 2022 10:39:39 Tom Rini wrote:
> > > > > On Sun, May 01, 2022 at 04:23:52PM +0200, Pali Rohár wrote:
> > > > >
> > > > > > This reverts commit c7fad78ec0ee41b72a58bebb61959570eb937ab1.
> > > > > >
> > > > > > This commit made configuration, understanding, maintenance, debugging and
> > > > > > future development of the powerpc/mpc85xx Local Bus Controller on P1/P2
> > > > > > boards impossible.
> > > > > >
> > > > > > All preliminary Base and Option registers depends on other code and C
> > > > > > macros generated at C compile time and they comes from the other macros.
> > > > > >
> > > > > > For example, NOR base address and NOR options are set via macros
> > > > > > CONFIG_SYS_FLASH_BR_PRELIM and CONFIG_SYS_FLASH_OR_PRELIM. And then based
> > > > > > on other logic are filled correct values in to the correct macros
> > > > > > CONFIG_SYS_BR*_PRELIM and CONFIG_SYS_OR*_PRELIM.
> > > > > >
> > > > > > These config options are not user configurable options and therefore
> > > > > > should not appear in menuconfig. Moreover for P1/P2 boards they have
> > > > > > nothing with DDR driver, so they should not appear in drivers/ddr.
> > > > > >
> > > > > > This change was completely wrong direction, so revert it. It allows to
> > > > > > start fixing issues with FLASH, NOR, NAND and CPLD LBC configuration.
> > > > > > In current state it is impossible.
> > > > > >
> > > > > > See also thread for more details:
> > > > > > https://lore.kernel.org/u-boot/20220426181740.o2n7xfg46ytljcdx@pali/t/#u
> > > > > >
> > > > > > Signed-off-by: Pali Rohár <pali@kernel.org>
> > > > >
> > > > > NAK. We are not moving things back in to board config headers under
> > > > > CONFIG namespace. Some other solution is required.
> > > >
> > > > I spend time on this and I do not see any other solution. As explained
> > > > that commit just introduced more issues then what it brought, so it was
> > > > step backward, not forward. So please show other solution, if you do not
> > > > like this one.
> > >
> > > Anything that I suggested in the previous thread about moving to board
> > > Kconfig files.
> >
> > Kconfig does not support evaluating C macros from C header files. So it
> > would not work.
>
> Document how to derive them using tools like 'printf' when adding more
> boards, which should not be a common case anyhow.
>
> > > Or move it to some other header and out of CONFIG namespace.
> >
> > This is board specific setting, used by drivers and arch code. So it
> > needs to be in some board location, like the config header file.
>
> But all include/config/*.h files are destined to be removed, so they
> cannot live there. Everything in the CONFIG namespace needs to be in
> Kconfig. Nothing outside of CONFIG namespace belongs under
> include/configs/.
>
> > > Or if dtoc (doc/develop/driver-model/of-plat.rst) isn't
> > > sufficient today to pull out the infos to use at build time, expand it
> > > to cover this case as it would be useful for large numbers of other
> > > cases.
> >
> > This would mean to rewrite completely everything about LBC configuration
> > and its peripherals. I really do not have energy nor time for it.
>
> Neither apparently has anyone else for the last far far too long.
>
> > There are issues which needs to be fixed first, then some "code cleanup"
> > and "non-functional" changes could be done.
> >
> > But that your commit c7fad78ec0ee41b72a58bebb61959570eb937ab1 make it
> > impossible to do anything with LBC, neither new development, nor doing
> > bug fixes. So it is in the worst state in which it can be.
>
> How? Derive the correct hex value and put it in.
>
> > That commit has same effect as conservation of the code and putting it
> > into the state to disallow future development in this area. Because
> > everybody who wants to touch it, has to first do what you wrote above.
>
> Yes. The code is sub-standard and needs improvement.
>
> > But this is such giant work which nobody is going to do, just for fixing
> > small bug, which is completely unrelated to that work. And that work is
> > only refactor/code cleanup which does not bring any functional value.
> > Nothing so fancy, that somebody would do in spare time.
> >
> > So I hope that this was not your intension.
>
> My intention is to get the PowerPC code up to modern U-Boot standards.
> Or, to get it removed since there's not enough interest in maintaining
> and updating it.
>
> To re-iterate, I agree that it would be good to construct the values at
> build time using macros. No one likes looking at raw magic values. But
> for an otherwise dead end platform, documenting how these magic values
> are constructed (something under doc/arch/ or doc/board/) for anyone in
> the future doing more work is Good Enough for me. Alternatively,
> re-working things so that instead of being pulled from
> include/configs/board-config.h they come from board/.../something.h is
> Good Enough, so long as they are NOT using the CONFIG prefix. They can
> use CFG_ or just LBC_ or anything else that makes sense.
Getting back to this. I see 13 more "LBC" CONFIG symbols that need
something done to them. I'm sure most or all of them are in the same
situation as the PRELIM ones in this thread. Have you attempted to move
them out of the CONFIG namespace by chance? If not, I might start
looking soon at where to move them to, rather than migrate to Kconfig.
Thanks.
--
Tom
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^ permalink raw reply [flat|nested] 16+ messages in thread
* Re: [PATCH 1/6] Revert "Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig"
2022-05-12 16:01 ` Tom Rini
@ 2022-05-12 16:05 ` Pali Rohár
0 siblings, 0 replies; 16+ messages in thread
From: Pali Rohár @ 2022-05-12 16:05 UTC (permalink / raw)
To: Tom Rini; +Cc: u-boot
On Thursday 12 May 2022 12:01:26 Tom Rini wrote:
> On Sun, May 01, 2022 at 12:17:51PM -0400, Tom Rini wrote:
> > On Sun, May 01, 2022 at 05:33:19PM +0200, Pali Rohár wrote:
> > > On Sunday 01 May 2022 11:14:21 Tom Rini wrote:
> > > > On Sun, May 01, 2022 at 04:44:16PM +0200, Pali Rohár wrote:
> > > > > On Sunday 01 May 2022 10:39:39 Tom Rini wrote:
> > > > > > On Sun, May 01, 2022 at 04:23:52PM +0200, Pali Rohár wrote:
> > > > > >
> > > > > > > This reverts commit c7fad78ec0ee41b72a58bebb61959570eb937ab1.
> > > > > > >
> > > > > > > This commit made configuration, understanding, maintenance, debugging and
> > > > > > > future development of the powerpc/mpc85xx Local Bus Controller on P1/P2
> > > > > > > boards impossible.
> > > > > > >
> > > > > > > All preliminary Base and Option registers depends on other code and C
> > > > > > > macros generated at C compile time and they comes from the other macros.
> > > > > > >
> > > > > > > For example, NOR base address and NOR options are set via macros
> > > > > > > CONFIG_SYS_FLASH_BR_PRELIM and CONFIG_SYS_FLASH_OR_PRELIM. And then based
> > > > > > > on other logic are filled correct values in to the correct macros
> > > > > > > CONFIG_SYS_BR*_PRELIM and CONFIG_SYS_OR*_PRELIM.
> > > > > > >
> > > > > > > These config options are not user configurable options and therefore
> > > > > > > should not appear in menuconfig. Moreover for P1/P2 boards they have
> > > > > > > nothing with DDR driver, so they should not appear in drivers/ddr.
> > > > > > >
> > > > > > > This change was completely wrong direction, so revert it. It allows to
> > > > > > > start fixing issues with FLASH, NOR, NAND and CPLD LBC configuration.
> > > > > > > In current state it is impossible.
> > > > > > >
> > > > > > > See also thread for more details:
> > > > > > > https://lore.kernel.org/u-boot/20220426181740.o2n7xfg46ytljcdx@pali/t/#u
> > > > > > >
> > > > > > > Signed-off-by: Pali Rohár <pali@kernel.org>
> > > > > >
> > > > > > NAK. We are not moving things back in to board config headers under
> > > > > > CONFIG namespace. Some other solution is required.
> > > > >
> > > > > I spend time on this and I do not see any other solution. As explained
> > > > > that commit just introduced more issues then what it brought, so it was
> > > > > step backward, not forward. So please show other solution, if you do not
> > > > > like this one.
> > > >
> > > > Anything that I suggested in the previous thread about moving to board
> > > > Kconfig files.
> > >
> > > Kconfig does not support evaluating C macros from C header files. So it
> > > would not work.
> >
> > Document how to derive them using tools like 'printf' when adding more
> > boards, which should not be a common case anyhow.
> >
> > > > Or move it to some other header and out of CONFIG namespace.
> > >
> > > This is board specific setting, used by drivers and arch code. So it
> > > needs to be in some board location, like the config header file.
> >
> > But all include/config/*.h files are destined to be removed, so they
> > cannot live there. Everything in the CONFIG namespace needs to be in
> > Kconfig. Nothing outside of CONFIG namespace belongs under
> > include/configs/.
> >
> > > > Or if dtoc (doc/develop/driver-model/of-plat.rst) isn't
> > > > sufficient today to pull out the infos to use at build time, expand it
> > > > to cover this case as it would be useful for large numbers of other
> > > > cases.
> > >
> > > This would mean to rewrite completely everything about LBC configuration
> > > and its peripherals. I really do not have energy nor time for it.
> >
> > Neither apparently has anyone else for the last far far too long.
> >
> > > There are issues which needs to be fixed first, then some "code cleanup"
> > > and "non-functional" changes could be done.
> > >
> > > But that your commit c7fad78ec0ee41b72a58bebb61959570eb937ab1 make it
> > > impossible to do anything with LBC, neither new development, nor doing
> > > bug fixes. So it is in the worst state in which it can be.
> >
> > How? Derive the correct hex value and put it in.
> >
> > > That commit has same effect as conservation of the code and putting it
> > > into the state to disallow future development in this area. Because
> > > everybody who wants to touch it, has to first do what you wrote above.
> >
> > Yes. The code is sub-standard and needs improvement.
> >
> > > But this is such giant work which nobody is going to do, just for fixing
> > > small bug, which is completely unrelated to that work. And that work is
> > > only refactor/code cleanup which does not bring any functional value.
> > > Nothing so fancy, that somebody would do in spare time.
> > >
> > > So I hope that this was not your intension.
> >
> > My intention is to get the PowerPC code up to modern U-Boot standards.
> > Or, to get it removed since there's not enough interest in maintaining
> > and updating it.
> >
> > To re-iterate, I agree that it would be good to construct the values at
> > build time using macros. No one likes looking at raw magic values. But
> > for an otherwise dead end platform, documenting how these magic values
> > are constructed (something under doc/arch/ or doc/board/) for anyone in
> > the future doing more work is Good Enough for me. Alternatively,
> > re-working things so that instead of being pulled from
> > include/configs/board-config.h they come from board/.../something.h is
> > Good Enough, so long as they are NOT using the CONFIG prefix. They can
> > use CFG_ or just LBC_ or anything else that makes sense.
>
> Getting back to this. I see 13 more "LBC" CONFIG symbols that need
> something done to them. I'm sure most or all of them are in the same
> situation as the PRELIM ones in this thread. Have you attempted to move
> them out of the CONFIG namespace by chance? If not, I might start
> looking soon at where to move them to, rather than migrate to Kconfig.
> Thanks.
No, have not looked at this. I was fixing SDHC issues (patches are now on ML).
^ permalink raw reply [flat|nested] 16+ messages in thread
end of thread, other threads:[~2022-05-12 16:06 UTC | newest]
Thread overview: 16+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-01 14:23 [PATCH 0/6] board: freescale: p1_p2_rdb_pc: Fix sizes of LBC peripherals Pali Rohár
2022-05-01 14:23 ` [PATCH 1/6] Revert "Convert CONFIG_SYS_BR0_PRELIM et al to Kconfig" Pali Rohár
2022-05-01 14:39 ` Tom Rini
2022-05-01 14:44 ` Pali Rohár
2022-05-01 15:14 ` Tom Rini
2022-05-01 15:33 ` Pali Rohár
2022-05-01 16:17 ` Tom Rini
2022-05-12 16:01 ` Tom Rini
2022-05-12 16:05 ` Pali Rohár
2022-05-01 14:23 ` [PATCH 2/6] Revert "p1_p2_rdb: Remove CONFIG_CPLD_[BO]R_PRELIM" Pali Rohár
2022-05-01 14:38 ` Tom Rini
2022-05-01 14:40 ` Pali Rohár
2022-05-01 14:23 ` [PATCH 3/6] mpc85xx: Replace magic values in BR/OR PRELIM config options by proper C macros Pali Rohár
2022-05-01 14:23 ` [PATCH 4/6] board: freescale: p1_p2_rdb_pc: Fix size of CPLD mapping Pali Rohár
2022-05-01 14:23 ` [PATCH 5/6] board: freescale: p1_p2_rdb_pc: Fix size of FLASH NOR mapping Pali Rohár
2022-05-01 14:23 ` [PATCH 6/6] board: freescale: p1_p2_rdb_pc: Fix size of NAND mapping Pali Rohár
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