* [PATCH] drm/amd/pm: enable ac/dc switching for SMU 13.0.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable power profile setting " Alex Deucher
` (22 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Lijo Lazar, Alex Deucher, Evan Quan, Hawking Zhang
From: Evan Quan <evan.quan@amd.com>
Fulfill the ->set_power_source interface which notifies
PMFW the current system power source(AC/DC).
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index f4184ea90e86..2bebc69d6f62 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -115,6 +115,7 @@ static struct cmn2asic_msg_mapping smu_v13_0_0_message_map[SMU_MSG_MAX_COUNT] =
MSG_MAP(DisallowGfxOff, PPSMC_MSG_DisallowGfxOff, 0),
MSG_MAP(SetMGpuFanBoostLimitRpm, PPSMC_MSG_SetMGpuFanBoostLimitRpm, 0),
MSG_MAP(GetPptLimit, PPSMC_MSG_GetPptLimit, 0),
+ MSG_MAP(NotifyPowerSource, PPSMC_MSG_NotifyPowerSource, 0),
};
static struct cmn2asic_mapping smu_v13_0_0_clk_map[SMU_CLK_COUNT] = {
@@ -1393,6 +1394,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.enable_mgpu_fan_boost = smu_v13_0_0_enable_mgpu_fan_boost,
.get_power_limit = smu_v13_0_0_get_power_limit,
.set_power_limit = smu_v13_0_set_power_limit,
+ .set_power_source = smu_v13_0_set_power_source,
};
void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amd/pm: enable power profile setting for SMU 13.0.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable ac/dc switching " Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable RunDcBtc support " Alex Deucher
` (21 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Lijo Lazar, Alex Deucher, Evan Quan, Hawking Zhang
From: Evan Quan <evan.quan@amd.com>
Fulfill the interfaces for retrieving and setting power profile
mode on SMU 13.0.0.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 154 ++++++++++++++++++
1 file changed, 154 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 2bebc69d6f62..ea549b9b01f4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1345,6 +1345,158 @@ static int smu_v13_0_0_get_power_limit(struct smu_context *smu,
return 0;
}
+static int smu_v13_0_0_get_power_profile_mode(struct smu_context *smu,
+ char *buf)
+{
+ DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
+ DpmActivityMonitorCoeffInt_t *activity_monitor =
+ &(activity_monitor_external.DpmActivityMonitorCoeffInt);
+ static const char *title[] = {
+ "PROFILE_INDEX(NAME)",
+ "CLOCK_TYPE(NAME)",
+ "FPS",
+ "MinActiveFreqType",
+ "MinActiveFreq",
+ "BoosterFreqType",
+ "BoosterFreq",
+ "PD_Data_limit_c",
+ "PD_Data_error_coeff",
+ "PD_Data_error_rate_coeff"};
+ int16_t workload_type = 0;
+ uint32_t i, size = 0;
+ int result = 0;
+
+ if (!buf)
+ return -EINVAL;
+
+ size += sysfs_emit_at(buf, size, "%16s %s %s %s %s %s %s %s %s %s\n",
+ title[0], title[1], title[2], title[3], title[4], title[5],
+ title[6], title[7], title[8], title[9]);
+
+ for (i = 0; i <= PP_SMC_POWER_PROFILE_CUSTOM; i++) {
+ /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
+ workload_type = smu_cmn_to_asic_specific_index(smu,
+ CMN2ASIC_MAPPING_WORKLOAD,
+ i);
+ if (workload_type < 0)
+ return -EINVAL;
+
+ result = smu_cmn_update_table(smu,
+ SMU_TABLE_ACTIVITY_MONITOR_COEFF,
+ workload_type,
+ (void *)(&activity_monitor_external),
+ false);
+ if (result) {
+ dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
+ return result;
+ }
+
+ size += sysfs_emit_at(buf, size, "%2d %14s%s:\n",
+ i, amdgpu_pp_profile_name[i], (i == smu->power_profile_mode) ? "*" : " ");
+
+ size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
+ " ",
+ 0,
+ "GFXCLK",
+ activity_monitor->Gfx_FPS,
+ activity_monitor->Gfx_MinActiveFreqType,
+ activity_monitor->Gfx_MinActiveFreq,
+ activity_monitor->Gfx_BoosterFreqType,
+ activity_monitor->Gfx_BoosterFreq,
+ activity_monitor->Gfx_PD_Data_limit_c,
+ activity_monitor->Gfx_PD_Data_error_coeff,
+ activity_monitor->Gfx_PD_Data_error_rate_coeff);
+
+ size += sysfs_emit_at(buf, size, "%19s %d(%13s) %7d %7d %7d %7d %7d %7d %7d %7d\n",
+ " ",
+ 1,
+ "FCLK",
+ activity_monitor->Fclk_FPS,
+ activity_monitor->Fclk_MinActiveFreqType,
+ activity_monitor->Fclk_MinActiveFreq,
+ activity_monitor->Fclk_BoosterFreqType,
+ activity_monitor->Fclk_BoosterFreq,
+ activity_monitor->Fclk_PD_Data_limit_c,
+ activity_monitor->Fclk_PD_Data_error_coeff,
+ activity_monitor->Fclk_PD_Data_error_rate_coeff);
+ }
+
+ return size;
+}
+
+static int smu_v13_0_0_set_power_profile_mode(struct smu_context *smu,
+ long *input,
+ uint32_t size)
+{
+ DpmActivityMonitorCoeffIntExternal_t activity_monitor_external;
+ DpmActivityMonitorCoeffInt_t *activity_monitor =
+ &(activity_monitor_external.DpmActivityMonitorCoeffInt);
+ int workload_type, ret = 0;
+
+ smu->power_profile_mode = input[size];
+
+ if (smu->power_profile_mode > PP_SMC_POWER_PROFILE_CUSTOM) {
+ dev_err(smu->adev->dev, "Invalid power profile mode %d\n", smu->power_profile_mode);
+ return -EINVAL;
+ }
+
+ if (smu->power_profile_mode == PP_SMC_POWER_PROFILE_CUSTOM) {
+ ret = smu_cmn_update_table(smu,
+ SMU_TABLE_ACTIVITY_MONITOR_COEFF,
+ WORKLOAD_PPLIB_CUSTOM_BIT,
+ (void *)(&activity_monitor_external),
+ false);
+ if (ret) {
+ dev_err(smu->adev->dev, "[%s] Failed to get activity monitor!", __func__);
+ return ret;
+ }
+
+ switch (input[0]) {
+ case 0: /* Gfxclk */
+ activity_monitor->Gfx_FPS = input[1];
+ activity_monitor->Gfx_MinActiveFreqType = input[2];
+ activity_monitor->Gfx_MinActiveFreq = input[3];
+ activity_monitor->Gfx_BoosterFreqType = input[4];
+ activity_monitor->Gfx_BoosterFreq = input[5];
+ activity_monitor->Gfx_PD_Data_limit_c = input[6];
+ activity_monitor->Gfx_PD_Data_error_coeff = input[7];
+ activity_monitor->Gfx_PD_Data_error_rate_coeff = input[8];
+ break;
+ case 1: /* Fclk */
+ activity_monitor->Fclk_FPS = input[1];
+ activity_monitor->Fclk_MinActiveFreqType = input[2];
+ activity_monitor->Fclk_MinActiveFreq = input[3];
+ activity_monitor->Fclk_BoosterFreqType = input[4];
+ activity_monitor->Fclk_BoosterFreq = input[5];
+ activity_monitor->Fclk_PD_Data_limit_c = input[6];
+ activity_monitor->Fclk_PD_Data_error_coeff = input[7];
+ activity_monitor->Fclk_PD_Data_error_rate_coeff = input[8];
+ break;
+ }
+
+ ret = smu_cmn_update_table(smu,
+ SMU_TABLE_ACTIVITY_MONITOR_COEFF,
+ WORKLOAD_PPLIB_CUSTOM_BIT,
+ (void *)(&activity_monitor_external),
+ true);
+ if (ret) {
+ dev_err(smu->adev->dev, "[%s] Failed to set activity monitor!", __func__);
+ return ret;
+ }
+ }
+
+ /* conv PP_SMC_POWER_PROFILE* to WORKLOAD_PPLIB_*_BIT */
+ workload_type = smu_cmn_to_asic_specific_index(smu,
+ CMN2ASIC_MAPPING_WORKLOAD,
+ smu->power_profile_mode);
+ if (workload_type < 0)
+ return -EINVAL;
+
+ return smu_cmn_send_smc_msg_with_param(smu,
+ SMU_MSG_SetWorkloadMask,
+ 1 << workload_type,
+ NULL);
+}
static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.get_allowed_feature_mask = smu_v13_0_0_get_allowed_feature_mask,
@@ -1395,6 +1547,8 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.get_power_limit = smu_v13_0_0_get_power_limit,
.set_power_limit = smu_v13_0_set_power_limit,
.set_power_source = smu_v13_0_set_power_source,
+ .get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
+ .set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
};
void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amd/pm: enable RunDcBtc support for SMU 13.0.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable ac/dc switching " Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable power profile setting " Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable ppfeature mask setting " Alex Deucher
` (20 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Lijo Lazar, Alex Deucher, Evan Quan, Hawking Zhang
From: Evan Quan <evan.quan@amd.com>
Fulfill the RunDcBtc for SMU 13.0.0.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 2 ++
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 11 +++++++++++
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 +
3 files changed, 14 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index f55f701e4681..f05ae0fe86e8 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -273,5 +273,7 @@ int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
int smu_v13_0_init_pptable_microcode(struct smu_context *smu);
+int smu_v13_0_run_btc(struct smu_context *smu);
+
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index 8651f275bc68..eea7aee06af4 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2100,3 +2100,14 @@ int smu_v13_0_set_jpeg_enable(struct smu_context *smu,
SMU_MSG_PowerUpJpeg : SMU_MSG_PowerDownJpeg,
0, NULL);
}
+
+int smu_v13_0_run_btc(struct smu_context *smu)
+{
+ int res;
+
+ res = smu_cmn_send_smc_msg(smu, SMU_MSG_RunDcBtc, NULL);
+ if (res)
+ dev_err(smu->adev->dev, "RunDcBtc failed!\n");
+
+ return res;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index ea549b9b01f4..b4c693d322a0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1549,6 +1549,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.set_power_source = smu_v13_0_set_power_source,
.get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
.set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
+ .run_btc = smu_v13_0_run_btc,
};
void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amd/pm: enable ppfeature mask setting for SMU 13.0.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (2 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable RunDcBtc support " Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable PMLOG support " Alex Deucher
` (19 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Lijo Lazar, Alex Deucher, Evan Quan, Hawking Zhang
From: Evan Quan <evan.quan@amd.com>
Fulfill the interfaces for retrieving and setting ppfeature
masks on SMU 13.0.0.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index b4c693d322a0..b9a6dcccc0b0 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1550,6 +1550,8 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.get_power_profile_mode = smu_v13_0_0_get_power_profile_mode,
.set_power_profile_mode = smu_v13_0_0_set_power_profile_mode,
.run_btc = smu_v13_0_run_btc,
+ .get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
+ .set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
};
void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amd/pm: enable PMLOG support for SMU 13.0.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (3 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable ppfeature mask setting " Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable df cstate feature " Alex Deucher
` (18 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Lijo Lazar, Alex Deucher, Evan Quan, Hawking Zhang
From: Evan Quan <evan.quan@amd.com>
Fulfill the interface for setting PMLOG DramAddr
on SMU 13.0.0.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index b9a6dcccc0b0..e3c31ac7a63f 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -1552,6 +1552,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.run_btc = smu_v13_0_run_btc,
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
+ .set_tool_table_location = smu_v13_0_set_tool_table_location,
};
void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amd/pm: enable df cstate feature for SMU 13.0.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (4 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable PMLOG support " Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amdgpu: enable more GFX clockgating features for GC 11.0.0 Alex Deucher
` (17 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Lijo Lazar, Alex Deucher, Evan Quan, Hawking Zhang
From: Evan Quan <evan.quan@amd.com>
As the feature is ready with 78.29.0 PMFW.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Reviewed-by: Lijo Lazar <lijo.lazar@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index e3c31ac7a63f..74d7fa3dc00d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -223,6 +223,8 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_THROTTLERS_BIT);
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_FAN_CONTROL_BIT);
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT);
+
return 0;
}
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu: enable more GFX clockgating features for GC 11.0.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (5 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable df cstate feature " Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amd/pm: support more DPM features for SMU 13.0.0 Alex Deucher
` (16 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Evan Quan
From: Evan Quan <evan.quan@amd.com>
Support more GFX clockgating features(3D_CGCG, 3D_CGLS, MGCG,
FGCG and PERF_CLK).
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c | 100 +++++++++++++++++++----
drivers/gpu/drm/amd/amdgpu/soc21.c | 5 ++
drivers/gpu/drm/amd/include/amd_shared.h | 1 +
drivers/gpu/drm/amd/pm/amdgpu_pm.c | 2 +-
4 files changed, 93 insertions(+), 15 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
index 184bf554acca..8a1c0f783a2a 100644
--- a/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gfx_v11_0.c
@@ -4888,6 +4888,44 @@ static void gfx_v11_0_unset_safe_mode(struct amdgpu_device *adev)
WREG32_SOC15(GC, 0, regRLC_SAFE_MODE, RLC_SAFE_MODE__CMD_MASK);
}
+static void gfx_v11_0_update_perf_clk(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t def, data;
+
+ if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_PERF_CLK))
+ return;
+
+ def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
+
+ if (enable)
+ data &= ~RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
+ else
+ data |= RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK;
+
+ if (def != data)
+ WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
+}
+
+static void gfx_v11_0_update_sram_fgcg(struct amdgpu_device *adev,
+ bool enable)
+{
+ uint32_t def, data;
+
+ if (!(adev->cg_flags & AMD_CG_SUPPORT_GFX_FGCG))
+ return;
+
+ def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
+
+ if (enable)
+ data &= ~RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
+ else
+ data |= RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK;
+
+ if (def != data)
+ WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
+}
+
static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev,
bool enable)
{
@@ -4907,19 +4945,40 @@ static void gfx_v11_0_update_repeater_fgcg(struct amdgpu_device *adev,
WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
}
-#if 0
static void gfx_v11_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
- bool enable)
+ bool enable)
{
- /* TODO: add power related feature later. */
-}
+ uint32_t data, def;
-static void gfx_v11_0_update_3d_clock_gating(struct amdgpu_device *adev,
- bool enable)
-{
- /* TODO: add power related feature later. */
+ if (!(adev->cg_flags & (AMD_CG_SUPPORT_GFX_MGCG | AMD_CG_SUPPORT_GFX_MGLS)))
+ return;
+
+ /* It is disabled by HW by default */
+ if (enable) {
+ if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
+ /* 1 - RLC_CGTT_MGCG_OVERRIDE */
+ def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
+
+ data &= ~(RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
+ RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
+ RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
+
+ if (def != data)
+ WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
+ }
+ } else {
+ if (adev->cg_flags & AMD_CG_SUPPORT_GFX_MGCG) {
+ def = data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
+
+ data |= (RLC_CGTT_MGCG_OVERRIDE__RLC_CGTT_SCLK_OVERRIDE_MASK |
+ RLC_CGTT_MGCG_OVERRIDE__GRBM_CGTT_SCLK_OVERRIDE_MASK |
+ RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK);
+
+ if (def != data)
+ WREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE, data);
+ }
+ }
}
-#endif
static void gfx_v11_0_update_coarse_grain_clock_gating(struct amdgpu_device *adev,
bool enable)
@@ -5050,8 +5109,14 @@ static int gfx_v11_0_update_gfx_clock_gating(struct amdgpu_device *adev,
gfx_v11_0_update_coarse_grain_clock_gating(adev, enable);
+ gfx_v11_0_update_medium_grain_clock_gating(adev, enable);
+
gfx_v11_0_update_repeater_fgcg(adev, enable);
+ gfx_v11_0_update_sram_fgcg(adev, enable);
+
+ gfx_v11_0_update_perf_clk(adev, enable);
+
if (adev->cg_flags &
(AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_GFX_CGLS |
@@ -5144,16 +5209,23 @@ static void gfx_v11_0_get_clockgating_state(void *handle, u64 *flags)
struct amdgpu_device *adev = (struct amdgpu_device *)handle;
int data;
- /* AMD_CG_SUPPORT_GFX_FGCG */
- data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
- if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
- *flags |= AMD_CG_SUPPORT_GFX_FGCG;
-
/* AMD_CG_SUPPORT_GFX_MGCG */
data = RREG32_SOC15(GC, 0, regRLC_CGTT_MGCG_OVERRIDE);
if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_MGCG_OVERRIDE_MASK))
*flags |= AMD_CG_SUPPORT_GFX_MGCG;
+ /* AMD_CG_SUPPORT_REPEATER_FGCG */
+ if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_REPEATER_FGCG_OVERRIDE_MASK))
+ *flags |= AMD_CG_SUPPORT_REPEATER_FGCG;
+
+ /* AMD_CG_SUPPORT_GFX_FGCG */
+ if (!(data & RLC_CGTT_MGCG_OVERRIDE__GFXIP_FGCG_OVERRIDE_MASK))
+ *flags |= AMD_CG_SUPPORT_GFX_FGCG;
+
+ /* AMD_CG_SUPPORT_GFX_PERF_CLK */
+ if (!(data & RLC_CGTT_MGCG_OVERRIDE__PERFMON_CLOCK_STATE_MASK))
+ *flags |= AMD_CG_SUPPORT_GFX_PERF_CLK;
+
/* AMD_CG_SUPPORT_GFX_CGCG */
data = RREG32_SOC15(GC, 0, regRLC_CGCG_CGLS_CTRL);
if (data & RLC_CGCG_CGLS_CTRL__CGCG_EN_MASK)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 9e689a1f2ea4..c618f2b8ece8 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -526,7 +526,12 @@ static int soc21_common_early_init(void *handle)
case IP_VERSION(11, 0, 0):
adev->cg_flags = AMD_CG_SUPPORT_GFX_CGCG |
AMD_CG_SUPPORT_GFX_CGLS |
+ AMD_CG_SUPPORT_GFX_3D_CGCG |
+ AMD_CG_SUPPORT_GFX_3D_CGLS |
+ AMD_CG_SUPPORT_GFX_MGCG |
AMD_CG_SUPPORT_REPEATER_FGCG |
+ AMD_CG_SUPPORT_GFX_FGCG |
+ AMD_CG_SUPPORT_GFX_PERF_CLK |
AMD_CG_SUPPORT_VCN_MGCG |
AMD_CG_SUPPORT_JPEG_MGCG;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
diff --git a/drivers/gpu/drm/amd/include/amd_shared.h b/drivers/gpu/drm/amd/include/amd_shared.h
index 9ae4060a9d0f..bcdf7453a403 100644
--- a/drivers/gpu/drm/amd/include/amd_shared.h
+++ b/drivers/gpu/drm/amd/include/amd_shared.h
@@ -149,6 +149,7 @@ enum amd_powergating_state {
#define AMD_CG_SUPPORT_JPEG_MGCG (1ULL << 30)
#define AMD_CG_SUPPORT_GFX_FGCG (1ULL << 31)
#define AMD_CG_SUPPORT_REPEATER_FGCG (1ULL << 32)
+#define AMD_CG_SUPPORT_GFX_PERF_CLK (1ULL << 33)
/* PG flags */
#define AMD_PG_SUPPORT_GFX_PG (1 << 0)
#define AMD_PG_SUPPORT_GFX_SMG (1 << 1)
diff --git a/drivers/gpu/drm/amd/pm/amdgpu_pm.c b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
index e92d07f88048..6e40e9ba9ff0 100644
--- a/drivers/gpu/drm/amd/pm/amdgpu_pm.c
+++ b/drivers/gpu/drm/amd/pm/amdgpu_pm.c
@@ -67,7 +67,7 @@ static const struct cg_flag_name clocks[] = {
{AMD_CG_SUPPORT_IH_CG, "Interrupt Handler Clock Gating"},
{AMD_CG_SUPPORT_JPEG_MGCG, "JPEG Medium Grain Clock Gating"},
{AMD_CG_SUPPORT_REPEATER_FGCG, "Repeater Fine Grain Clock Gating"},
-
+ {AMD_CG_SUPPORT_GFX_PERF_CLK, "Perfmon Clock Gating"},
{AMD_CG_SUPPORT_ATHUB_MGCG, "Address Translation Hub Medium Grain Clock Gating"},
{AMD_CG_SUPPORT_ATHUB_LS, "Address Translation Hub Light Sleep"},
{0, NULL},
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amd/pm: support more DPM features for SMU 13.0.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (6 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amdgpu: enable more GFX clockgating features for GC 11.0.0 Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable deep sleep features control " Alex Deucher
` (15 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Evan Quan
From: Evan Quan <evan.quan@amd.com>
To pair with 78.30.0 PMFW, support more dpm features:
- UCLK DPM (disabled temporarily)
- VMEMP Scaling (disabled temporarily)
- VDDIO Scaling (disabled temporarily)
- GFXCLK DS
- SOCCLK DS
- MPCLK Deep Sleep on VDD_SOC
- MPCLK Deep Sleep on VDD_BACO
- Memory Temperature Reading (disabled temporarily)
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 16 ++++++++++++++++
1 file changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index 74d7fa3dc00d..b43884cf939c 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -225,6 +225,22 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DF_CSTATE_BIT);
+#if 0
+ if (adev->pm.pp_feature & PP_MCLK_DPM_MASK) {
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_UCLK_BIT);
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VMEMP_SCALING_BIT);
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_VDDIO_MEM_SCALING_BIT);
+ }
+
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_MEM_TEMP_READ_BIT);
+#endif
+
+ if (adev->pm.pp_feature & PP_SCLK_DEEP_SLEEP_MASK)
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_GFXCLK_BIT);
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_SOCCLK_BIT);
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT);
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
+
return 0;
}
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amd/pm: enable deep sleep features control for SMU 13.0.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (7 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amd/pm: support more DPM features for SMU 13.0.0 Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable gfx ulv feature " Alex Deucher
` (14 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Evan Quan
From: Evan Quan <evan.quan@amd.com>
Fulfill the interface for deep sleep features control.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 3 +
.../gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 73 +++++++++++++++++++
.../drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 9 +++
3 files changed, 85 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index f05ae0fe86e8..e33686a12df2 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -275,5 +275,8 @@ int smu_v13_0_init_pptable_microcode(struct smu_context *smu);
int smu_v13_0_run_btc(struct smu_context *smu);
+int smu_v13_0_deep_sleep_control(struct smu_context *smu,
+ bool enablement);
+
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index eea7aee06af4..da458e146252 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2111,3 +2111,76 @@ int smu_v13_0_run_btc(struct smu_context *smu)
return res;
}
+
+int smu_v13_0_deep_sleep_control(struct smu_context *smu,
+ bool enablement)
+{
+ struct amdgpu_device *adev = smu->adev;
+ int ret = 0;
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_GFXCLK_BIT)) {
+ ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_GFXCLK_BIT, enablement);
+ if (ret) {
+ dev_err(adev->dev, "Failed to %s GFXCLK DS!\n", enablement ? "enable" : "disable");
+ return ret;
+ }
+ }
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_UCLK_BIT)) {
+ ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_UCLK_BIT, enablement);
+ if (ret) {
+ dev_err(adev->dev, "Failed to %s UCLK DS!\n", enablement ? "enable" : "disable");
+ return ret;
+ }
+ }
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_FCLK_BIT)) {
+ ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_FCLK_BIT, enablement);
+ if (ret) {
+ dev_err(adev->dev, "Failed to %s FCLK DS!\n", enablement ? "enable" : "disable");
+ return ret;
+ }
+ }
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_SOCCLK_BIT)) {
+ ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_SOCCLK_BIT, enablement);
+ if (ret) {
+ dev_err(adev->dev, "Failed to %s SOCCLK DS!\n", enablement ? "enable" : "disable");
+ return ret;
+ }
+ }
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_LCLK_BIT)) {
+ ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_LCLK_BIT, enablement);
+ if (ret) {
+ dev_err(adev->dev, "Failed to %s LCLK DS!\n", enablement ? "enable" : "disable");
+ return ret;
+ }
+ }
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_VCN_BIT)) {
+ ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_VCN_BIT, enablement);
+ if (ret) {
+ dev_err(adev->dev, "Failed to %s VCN DS!\n", enablement ? "enable" : "disable");
+ return ret;
+ }
+ }
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP0CLK_BIT)) {
+ ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP0CLK_BIT, enablement);
+ if (ret) {
+ dev_err(adev->dev, "Failed to %s MP0/MPIOCLK DS!\n", enablement ? "enable" : "disable");
+ return ret;
+ }
+ }
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_DS_MP1CLK_BIT)) {
+ ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_DS_MP1CLK_BIT, enablement);
+ if (ret) {
+ dev_err(adev->dev, "Failed to %s MP1CLK DS!\n", enablement ? "enable" : "disable");
+ return ret;
+ }
+ }
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index b43884cf939c..eda0f59f07ae 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -141,6 +141,14 @@ static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] =
[SMU_FEATURE_DPM_DCLK_BIT] = {1, FEATURE_MM_DPM_BIT},
[SMU_FEATURE_FAN_CONTROL_BIT] = {1, FEATURE_FAN_CONTROL_BIT},
[SMU_FEATURE_PPT_BIT] = {1, FEATURE_THROTTLERS_BIT},
+ [SMU_FEATURE_DS_GFXCLK_BIT] = {1, FEATURE_DS_GFXCLK_BIT},
+ [SMU_FEATURE_DS_SOCCLK_BIT] = {1, FEATURE_DS_SOCCLK_BIT},
+ [SMU_FEATURE_DS_UCLK_BIT] = {1, FEATURE_DS_UCLK_BIT},
+ [SMU_FEATURE_DS_FCLK_BIT] = {1, FEATURE_DS_FCLK_BIT},
+ [SMU_FEATURE_DS_LCLK_BIT] = {1, FEATURE_DS_LCLK_BIT},
+ [SMU_FEATURE_DS_VCN_BIT] = {1, FEATURE_DS_VCN_BIT},
+ [SMU_FEATURE_DS_MP0CLK_BIT] = {1, FEATURE_SOC_MPCLK_DS_BIT},
+ [SMU_FEATURE_DS_MP1CLK_BIT] = {1, FEATURE_BACO_MPCLK_DS_BIT},
};
static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
@@ -1571,6 +1579,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.get_pp_feature_mask = smu_cmn_get_pp_feature_mask,
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.set_tool_table_location = smu_v13_0_set_tool_table_location,
+ .deep_sleep_control = smu_v13_0_deep_sleep_control,
};
void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amd/pm: enable gfx ulv feature control for SMU 13.0.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (8 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable deep sleep features control " Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable more dpm features to pair with PMFW 78.31.0 Alex Deucher
` (13 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Likun Gao, Evan Quan
From: Evan Quan <evan.quan@amd.com>
Fulfill the interface for gfx ulv control.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Likun Gao <Likun.Gao@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h | 3 +++
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c | 11 +++++++++++
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 2 ++
3 files changed, 16 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
index e33686a12df2..39b51f7a2c1d 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
+++ b/drivers/gpu/drm/amd/pm/swsmu/inc/smu_v13_0.h
@@ -278,5 +278,8 @@ int smu_v13_0_run_btc(struct smu_context *smu);
int smu_v13_0_deep_sleep_control(struct smu_context *smu,
bool enablement);
+int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
+ bool enablement);
+
#endif
#endif
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
index da458e146252..4729cdcdb210 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0.c
@@ -2184,3 +2184,14 @@ int smu_v13_0_deep_sleep_control(struct smu_context *smu,
return ret;
}
+
+int smu_v13_0_gfx_ulv_control(struct smu_context *smu,
+ bool enablement)
+{
+ int ret = 0;
+
+ if (smu_cmn_feature_is_supported(smu, SMU_FEATURE_GFX_ULV_BIT))
+ ret = smu_cmn_feature_set_enabled(smu, SMU_FEATURE_GFX_ULV_BIT, enablement);
+
+ return ret;
+}
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index eda0f59f07ae..b410420178ae 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -149,6 +149,7 @@ static struct cmn2asic_mapping smu_v13_0_0_feature_mask_map[SMU_FEATURE_COUNT] =
[SMU_FEATURE_DS_VCN_BIT] = {1, FEATURE_DS_VCN_BIT},
[SMU_FEATURE_DS_MP0CLK_BIT] = {1, FEATURE_SOC_MPCLK_DS_BIT},
[SMU_FEATURE_DS_MP1CLK_BIT] = {1, FEATURE_BACO_MPCLK_DS_BIT},
+ [SMU_FEATURE_GFX_ULV_BIT] = {1, FEATURE_GFX_ULV_BIT},
};
static struct cmn2asic_mapping smu_v13_0_0_table_map[SMU_TABLE_COUNT] = {
@@ -1580,6 +1581,7 @@ static const struct pptable_funcs smu_v13_0_0_ppt_funcs = {
.set_pp_feature_mask = smu_cmn_set_pp_feature_mask,
.set_tool_table_location = smu_v13_0_set_tool_table_location,
.deep_sleep_control = smu_v13_0_deep_sleep_control,
+ .gfx_ulv_control = smu_v13_0_gfx_ulv_control,
};
void smu_v13_0_0_set_ppt_funcs(struct smu_context *smu)
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amd/pm: enable more dpm features to pair with PMFW 78.31.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (9 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable gfx ulv feature " Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amdgpu: enable MGCG and LS for ATHUB 3.0 Alex Deucher
` (12 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Evan Quan, Hawking Zhang
From: Evan Quan <evan.quan@amd.com>
Enables the support for DCN DPM and DCFCLK DS features.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c | 6 ++++++
1 file changed, 6 insertions(+)
diff --git a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
index b410420178ae..b595497e9bf5 100644
--- a/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
+++ b/drivers/gpu/drm/amd/pm/swsmu/smu13/smu_v13_0_0_ppt.c
@@ -250,6 +250,12 @@ smu_v13_0_0_get_allowed_feature_mask(struct smu_context *smu,
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_SOC_MPCLK_DS_BIT);
*(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_BACO_MPCLK_DS_BIT);
+#if 0
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_FCLK_BIT);
+#endif
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DPM_DCN_BIT);
+ *(uint64_t *)feature_mask |= FEATURE_MASK(FEATURE_DS_DCFCLK_BIT);
+
return 0;
}
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu: enable MGCG and LS for ATHUB 3.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (10 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amd/pm: enable more dpm features to pair with PMFW 78.31.0 Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amdgpu: enable MGCG and LS for MMHUB 3.0 Alex Deucher
` (11 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Evan Quan, Hawking Zhang
From: Evan Quan <evan.quan@amd.com>
Enable ATHUB 3.0 MGCG and LS features.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/athub_v3_0.c | 5 ++---
drivers/gpu/drm/amd/amdgpu/soc21.c | 4 +++-
2 files changed, 5 insertions(+), 4 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c
index 20ff228a8b4a..eda07cfe92bb 100644
--- a/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c
@@ -36,7 +36,7 @@ athub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
def = data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);
- if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG))
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_MGCG))
data |= ATHUB_MISC_CNTL__CG_ENABLE_MASK;
else
data &= ~ATHUB_MISC_CNTL__CG_ENABLE_MASK;
@@ -53,8 +53,7 @@ athub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
def = data = RREG32_SOC15(ATHUB, 0, regATHUB_MISC_CNTL);
- if (enable && (adev->cg_flags & AMD_CG_SUPPORT_MC_LS) &&
- (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS))
+ if (enable && (adev->cg_flags & AMD_CG_SUPPORT_ATHUB_LS))
data |= ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
else
data &= ~ATHUB_MISC_CNTL__CG_MEM_LS_ENABLE_MASK;
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index c618f2b8ece8..815b9cc8f9ff 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -533,7 +533,9 @@ static int soc21_common_early_init(void *handle)
AMD_CG_SUPPORT_GFX_FGCG |
AMD_CG_SUPPORT_GFX_PERF_CLK |
AMD_CG_SUPPORT_VCN_MGCG |
- AMD_CG_SUPPORT_JPEG_MGCG;
+ AMD_CG_SUPPORT_JPEG_MGCG |
+ AMD_CG_SUPPORT_ATHUB_MGCG |
+ AMD_CG_SUPPORT_ATHUB_LS;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_JPEG |
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu: enable MGCG and LS for MMHUB 3.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (11 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amdgpu: enable MGCG and LS for ATHUB 3.0 Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amdgpu: enable clock gating for IH 6.0 Alex Deucher
` (10 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Evan Quan, Hawking Zhang
From: Evan Quan <evan.quan@amd.com>
Enable MMHUB 3.0 MGCG and LS features.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c | 96 +++++++++++++++++++++++--
drivers/gpu/drm/amd/amdgpu/soc21.c | 4 +-
2 files changed, 92 insertions(+), 8 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
index 08a85a0cd334..682d7842aea1 100644
--- a/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/mmhub_v3_0.c
@@ -538,13 +538,78 @@ static u64 mmhub_v3_0_get_mc_fb_offset(struct amdgpu_device *adev)
static void mmhub_v3_0_update_medium_grain_clock_gating(struct amdgpu_device *adev,
bool enable)
{
- //TODO
+ uint32_t def, data;
+#if 0
+ uint32_t def1, data1, def2 = 0, data2 = 0;
+#endif
+
+ def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
+#if 0
+ def1 = data1 = RREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2);
+ def2 = data2 = RREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2);
+#endif
+
+ if (enable) {
+ data |= MM_ATC_L2_MISC_CG__ENABLE_MASK;
+#if 0
+ data1 &= ~(DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+
+ data2 &= ~(DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+#endif
+ } else {
+ data &= ~MM_ATC_L2_MISC_CG__ENABLE_MASK;
+#if 0
+ data1 |= (DAGB0_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+ DAGB0_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+
+ data2 |= (DAGB1_CNTL_MISC2__DISABLE_WRREQ_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_WRRET_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_RDREQ_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_RDRET_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_TLBWR_CG_MASK |
+ DAGB1_CNTL_MISC2__DISABLE_TLBRD_CG_MASK);
+#endif
+ }
+
+ if (def != data)
+ WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);
+#if 0
+ if (def1 != data1)
+ WREG32_SOC15(MMHUB, 0, regDAGB0_CNTL_MISC2, data1);
+
+ if (def2 != data2)
+ WREG32_SOC15(MMHUB, 0, regDAGB1_CNTL_MISC2, data2);
+#endif
}
static void mmhub_v3_0_update_medium_grain_light_sleep(struct amdgpu_device *adev,
bool enable)
{
- //TODO
+ uint32_t def, data;
+
+ def = data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
+
+ if (enable)
+ data |= MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
+ else
+ data &= ~MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK;
+
+ if (def != data)
+ WREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG, data);
}
static int mmhub_v3_0_set_clockgating(struct amdgpu_device *adev,
@@ -553,16 +618,33 @@ static int mmhub_v3_0_set_clockgating(struct amdgpu_device *adev,
if (amdgpu_sriov_vf(adev))
return 0;
- mmhub_v3_0_update_medium_grain_clock_gating(adev,
- state == AMD_CG_STATE_GATE);
- mmhub_v3_0_update_medium_grain_light_sleep(adev,
- state == AMD_CG_STATE_GATE);
+ if (adev->cg_flags & AMD_CG_SUPPORT_MC_MGCG)
+ mmhub_v3_0_update_medium_grain_clock_gating(adev,
+ state == AMD_CG_STATE_GATE);
+
+ if (adev->cg_flags & AMD_CG_SUPPORT_MC_LS)
+ mmhub_v3_0_update_medium_grain_light_sleep(adev,
+ state == AMD_CG_STATE_GATE);
+
return 0;
}
static void mmhub_v3_0_get_clockgating(struct amdgpu_device *adev, u64 *flags)
{
- //TODO
+ int data;
+
+ if (amdgpu_sriov_vf(adev))
+ *flags = 0;
+
+ data = RREG32_SOC15(MMHUB, 0, regMM_ATC_L2_MISC_CG);
+
+ /* AMD_CG_SUPPORT_MC_MGCG */
+ if (data & MM_ATC_L2_MISC_CG__ENABLE_MASK)
+ *flags |= AMD_CG_SUPPORT_MC_MGCG;
+
+ /* AMD_CG_SUPPORT_MC_LS */
+ if (data & MM_ATC_L2_MISC_CG__MEM_LS_ENABLE_MASK)
+ *flags |= AMD_CG_SUPPORT_MC_LS;
}
const struct amdgpu_mmhub_funcs mmhub_v3_0_funcs = {
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 815b9cc8f9ff..2497e2f8b118 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -535,7 +535,9 @@ static int soc21_common_early_init(void *handle)
AMD_CG_SUPPORT_VCN_MGCG |
AMD_CG_SUPPORT_JPEG_MGCG |
AMD_CG_SUPPORT_ATHUB_MGCG |
- AMD_CG_SUPPORT_ATHUB_LS;
+ AMD_CG_SUPPORT_ATHUB_LS |
+ AMD_CG_SUPPORT_MC_MGCG |
+ AMD_CG_SUPPORT_MC_LS;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_JPEG |
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu: enable clock gating for IH 6.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (12 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amdgpu: enable MGCG and LS for MMHUB 3.0 Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amdgpu: enable clock gating for HDP 6.0 Alex Deucher
` (9 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Evan Quan, Hawking Zhang
From: Evan Quan <evan.quan@amd.com>
Enable IH 6.0 clock gating.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 3 ++-
1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 2497e2f8b118..24ba5e36378f 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -537,7 +537,8 @@ static int soc21_common_early_init(void *handle)
AMD_CG_SUPPORT_ATHUB_MGCG |
AMD_CG_SUPPORT_ATHUB_LS |
AMD_CG_SUPPORT_MC_MGCG |
- AMD_CG_SUPPORT_MC_LS;
+ AMD_CG_SUPPORT_MC_LS |
+ AMD_CG_SUPPORT_IH_CG;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_JPEG |
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu: enable clock gating for HDP 6.0
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (13 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amdgpu: enable clock gating for IH 6.0 Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amdgpu/gmc11: avoid cpu accessing registers to flush VM Alex Deucher
` (8 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Evan Quan, Hawking Zhang
From: Evan Quan <evan.quan@amd.com>
Enable HDP 6.0 clock gating.
Signed-off-by: Evan Quan <evan.quan@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c | 100 ++++++++++++++++++--------
drivers/gpu/drm/amd/amdgpu/soc21.c | 3 +-
2 files changed, 73 insertions(+), 30 deletions(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
index 1dab8f3fcbad..063eba619f2f 100644
--- a/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/hdp_v6_0.c
@@ -38,33 +38,85 @@ static void hdp_v6_0_flush_hdp(struct amdgpu_device *adev,
}
static void hdp_v6_0_update_clock_gating(struct amdgpu_device *adev,
- bool enable)
+ bool enable)
{
- uint32_t hdp_clk_cntl;
+ uint32_t hdp_clk_cntl, hdp_clk_cntl1;
+ uint32_t hdp_mem_pwr_cntl;
- if (!(adev->cg_flags & AMD_CG_SUPPORT_HDP_MGCG))
+ if (!(adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS |
+ AMD_CG_SUPPORT_HDP_DS |
+ AMD_CG_SUPPORT_HDP_SD)))
return;
- hdp_clk_cntl = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
+ hdp_clk_cntl = hdp_clk_cntl1 = RREG32_SOC15(HDP, 0,regHDP_CLK_CNTL);
+ hdp_mem_pwr_cntl = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
+ /* Before doing clock/power mode switch,
+ * forced on IPH & RC clock */
+ hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
+ RC_MEM_CLK_SOFT_OVERRIDE, 1);
+ WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
+
+ /* disable clock and power gating before any changing */
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
+ ATOMIC_MEM_POWER_CTRL_EN, 0);
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
+ ATOMIC_MEM_POWER_LS_EN, 0);
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
+ ATOMIC_MEM_POWER_DS_EN, 0);
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
+ ATOMIC_MEM_POWER_SD_EN, 0);
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
+ RC_MEM_POWER_CTRL_EN, 0);
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
+ RC_MEM_POWER_LS_EN, 0);
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
+ RC_MEM_POWER_DS_EN, 0);
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
+ RC_MEM_POWER_SD_EN, 0);
+ WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
+
+ /* Already disabled above. The actions below are for "enabled" only */
if (enable) {
- hdp_clk_cntl &=
- ~(uint32_t)
- (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK);
- } else {
- hdp_clk_cntl |= HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK;
+ /* only one clock gating mode (LS/DS/SD) can be enabled */
+ if (adev->cg_flags & AMD_CG_SUPPORT_HDP_SD) {
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
+ HDP_MEM_POWER_CTRL,
+ ATOMIC_MEM_POWER_SD_EN, 1);
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
+ HDP_MEM_POWER_CTRL,
+ RC_MEM_POWER_SD_EN, 1);
+ } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_LS) {
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
+ HDP_MEM_POWER_CTRL,
+ ATOMIC_MEM_POWER_LS_EN, 1);
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
+ HDP_MEM_POWER_CTRL,
+ RC_MEM_POWER_LS_EN, 1);
+ } else if (adev->cg_flags & AMD_CG_SUPPORT_HDP_DS) {
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
+ HDP_MEM_POWER_CTRL,
+ ATOMIC_MEM_POWER_DS_EN, 1);
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl,
+ HDP_MEM_POWER_CTRL,
+ RC_MEM_POWER_DS_EN, 1);
+ }
+
+ /* confirmed that IPH_MEM_POWER_CTRL_EN and RC_MEM_POWER_CTRL_EN have to
+ * be set for SRAM LS/DS/SD */
+ if (adev->cg_flags & (AMD_CG_SUPPORT_HDP_LS | AMD_CG_SUPPORT_HDP_DS |
+ AMD_CG_SUPPORT_HDP_SD)) {
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
+ ATOMIC_MEM_POWER_CTRL_EN, 1);
+ hdp_mem_pwr_cntl = REG_SET_FIELD(hdp_mem_pwr_cntl, HDP_MEM_POWER_CTRL,
+ RC_MEM_POWER_CTRL_EN, 1);
+ WREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL, hdp_mem_pwr_cntl);
+ }
}
+ /* disable IPH & RC clock override after clock/power mode changing */
+ hdp_clk_cntl = REG_SET_FIELD(hdp_clk_cntl, HDP_CLK_CNTL,
+ RC_MEM_CLK_SOFT_OVERRIDE, 0);
WREG32_SOC15(HDP, 0, regHDP_CLK_CNTL, hdp_clk_cntl);
}
@@ -73,16 +125,6 @@ static void hdp_v6_0_get_clockgating_state(struct amdgpu_device *adev,
{
uint32_t tmp;
- /* AMD_CG_SUPPORT_HDP_MGCG */
- tmp = RREG32_SOC15(HDP, 0, regHDP_CLK_CNTL);
- if (!(tmp & (HDP_CLK_CNTL__ATOMIC_MEM_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__RC_MEM_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__DBUS_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__DYN_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__XDP_REG_CLK_SOFT_OVERRIDE_MASK |
- HDP_CLK_CNTL__HDP_REG_CLK_SOFT_OVERRIDE_MASK)))
- *flags |= AMD_CG_SUPPORT_HDP_MGCG;
-
/* AMD_CG_SUPPORT_HDP_LS/DS/SD */
tmp = RREG32_SOC15(HDP, 0, regHDP_MEM_POWER_CTRL);
if (tmp & HDP_MEM_POWER_CTRL__ATOMIC_MEM_POWER_LS_EN_MASK)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 24ba5e36378f..7804f95b790b 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -538,7 +538,8 @@ static int soc21_common_early_init(void *handle)
AMD_CG_SUPPORT_ATHUB_LS |
AMD_CG_SUPPORT_MC_MGCG |
AMD_CG_SUPPORT_MC_LS |
- AMD_CG_SUPPORT_IH_CG;
+ AMD_CG_SUPPORT_IH_CG |
+ AMD_CG_SUPPORT_HDP_SD;
adev->pg_flags = AMD_PG_SUPPORT_VCN |
AMD_PG_SUPPORT_VCN_DPG |
AMD_PG_SUPPORT_JPEG |
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu/gmc11: avoid cpu accessing registers to flush VM
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (14 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amdgpu: enable clock gating for HDP 6.0 Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-04 6:25 ` Christian König
2022-05-03 20:08 ` [PATCH] drm/amdgpu: add soc21 support for GC 11.0.2 Alex Deucher
` (7 subsequent siblings)
23 siblings, 1 reply; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Jack Xiao, Hawking Zhang
From: Jack Xiao <Jack.Xiao@amd.com>
Due to gfxoff on, cpu accessing registers is not expected.
Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 51 +++++++++++++++++++++++++-
1 file changed, 50 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
index 61db2a378008..032414d7429d 100644
--- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
@@ -265,6 +265,12 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
uint32_t vmhub, uint32_t flush_type)
{
+ struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
+ struct dma_fence *fence;
+ struct amdgpu_job *job;
+
+ int r;
+
if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron)
return;
@@ -288,8 +294,51 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
}
mutex_lock(&adev->mman.gtt_window_lock);
- gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0);
+
+ if (vmhub == AMDGPU_MMHUB_0) {
+ gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
+ mutex_unlock(&adev->mman.gtt_window_lock);
+ return;
+ }
+
+ BUG_ON(vmhub != AMDGPU_GFXHUB_0);
+
+ if (!adev->mman.buffer_funcs_enabled ||
+ !adev->ib_pool_ready ||
+ amdgpu_in_reset(adev) ||
+ ring->sched.ready == false) {
+ gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
+ mutex_unlock(&adev->mman.gtt_window_lock);
+ return;
+ }
+
+ r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
+ &job);
+ if (r)
+ goto error_alloc;
+
+ job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
+ job->vm_needs_flush = true;
+ job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
+ amdgpu_ring_pad_ib(ring, &job->ibs[0]);
+ r = amdgpu_job_submit(job, &adev->mman.entity,
+ AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
+ if (r)
+ goto error_submit;
+
+ mutex_unlock(&adev->mman.gtt_window_lock);
+
+ dma_fence_wait(fence, false);
+ dma_fence_put(fence);
+
+ return;
+
+error_submit:
+ amdgpu_job_free(job);
+
+error_alloc:
mutex_unlock(&adev->mman.gtt_window_lock);
+ DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
return;
}
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* Re: [PATCH] drm/amdgpu/gmc11: avoid cpu accessing registers to flush VM
2022-05-03 20:08 ` [PATCH] drm/amdgpu/gmc11: avoid cpu accessing registers to flush VM Alex Deucher
@ 2022-05-04 6:25 ` Christian König
0 siblings, 0 replies; 26+ messages in thread
From: Christian König @ 2022-05-04 6:25 UTC (permalink / raw)
To: Alex Deucher, amd-gfx; +Cc: Jack Xiao, Hawking Zhang
Am 03.05.22 um 22:08 schrieb Alex Deucher:
> From: Jack Xiao <Jack.Xiao@amd.com>
>
> Due to gfxoff on, cpu accessing registers is not expected.
>
> Signed-off-by: Jack Xiao <Jack.Xiao@amd.com>
> Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
> Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
> ---
> drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c | 51 +++++++++++++++++++++++++-
> 1 file changed, 50 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> index 61db2a378008..032414d7429d 100644
> --- a/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> +++ b/drivers/gpu/drm/amd/amdgpu/gmc_v11_0.c
> @@ -265,6 +265,12 @@ static void gmc_v11_0_flush_vm_hub(struct amdgpu_device *adev, uint32_t vmid,
> static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
> uint32_t vmhub, uint32_t flush_type)
> {
> + struct amdgpu_ring *ring = adev->mman.buffer_funcs_ring;
> + struct dma_fence *fence;
> + struct amdgpu_job *job;
> +
> + int r;
> +
> if ((vmhub == AMDGPU_GFXHUB_0) && !adev->gfx.is_poweron)
> return;
>
> @@ -288,8 +294,51 @@ static void gmc_v11_0_flush_gpu_tlb(struct amdgpu_device *adev, uint32_t vmid,
> }
>
> mutex_lock(&adev->mman.gtt_window_lock);
> - gmc_v11_0_flush_vm_hub(adev, vmid, vmhub, 0);
> +
> + if (vmhub == AMDGPU_MMHUB_0) {
> + gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_MMHUB_0, 0);
> + mutex_unlock(&adev->mman.gtt_window_lock);
> + return;
> + }
> +
> + BUG_ON(vmhub != AMDGPU_GFXHUB_0);
I've already responded on the internal review that this BUG_ON is not
justified.
We should rather change the "if (vmhub ==..." above to make sure that
all other HUBs don't use the gfxoff workaround.
Christian.
> +
> + if (!adev->mman.buffer_funcs_enabled ||
> + !adev->ib_pool_ready ||
> + amdgpu_in_reset(adev) ||
> + ring->sched.ready == false) {
> + gmc_v11_0_flush_vm_hub(adev, vmid, AMDGPU_GFXHUB_0, 0);
> + mutex_unlock(&adev->mman.gtt_window_lock);
> + return;
> + }
> +
> + r = amdgpu_job_alloc_with_ib(adev, 16 * 4, AMDGPU_IB_POOL_IMMEDIATE,
> + &job);
> + if (r)
> + goto error_alloc;
> +
> + job->vm_pd_addr = amdgpu_gmc_pd_addr(adev->gart.bo);
> + job->vm_needs_flush = true;
> + job->ibs->ptr[job->ibs->length_dw++] = ring->funcs->nop;
> + amdgpu_ring_pad_ib(ring, &job->ibs[0]);
> + r = amdgpu_job_submit(job, &adev->mman.entity,
> + AMDGPU_FENCE_OWNER_UNDEFINED, &fence);
> + if (r)
> + goto error_submit;
> +
> + mutex_unlock(&adev->mman.gtt_window_lock);
> +
> + dma_fence_wait(fence, false);
> + dma_fence_put(fence);
> +
> + return;
> +
> +error_submit:
> + amdgpu_job_free(job);
> +
> +error_alloc:
> mutex_unlock(&adev->mman.gtt_window_lock);
> + DRM_ERROR("Error flushing GPU TLB using the SDMA (%d)!\n", r);
> return;
> }
>
^ permalink raw reply [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu: add soc21 support for GC 11.0.2
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (15 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amdgpu/gmc11: avoid cpu accessing registers to flush VM Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amdgpu/discovery: " Alex Deucher
` (6 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Flora Cui, Hawking Zhang
From: Flora Cui <flora.cui@amd.com>
Add initial soc21 support.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/soc21.c | 5 +++++
1 file changed, 5 insertions(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/soc21.c b/drivers/gpu/drm/amd/amdgpu/soc21.c
index 7804f95b790b..d91bd70028b5 100644
--- a/drivers/gpu/drm/amd/amdgpu/soc21.c
+++ b/drivers/gpu/drm/amd/amdgpu/soc21.c
@@ -547,6 +547,11 @@ static int soc21_common_early_init(void *handle)
AMD_PG_SUPPORT_MMHUB;
adev->external_rev_id = adev->rev_id + 0x1; // TODO: need update
break;
+ case IP_VERSION(11, 0, 2):
+ adev->cg_flags = 0;
+ adev->pg_flags = 0;
+ adev->external_rev_id = adev->rev_id + 0x10;
+ break;
default:
/* FIXME: not supported yet */
return -EINVAL;
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu/discovery: add soc21 support for GC 11.0.2
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (16 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amdgpu: add soc21 support for GC 11.0.2 Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amdgpu: add support for ATHUB 3.0.2 Alex Deucher
` (5 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Flora Cui, Hawking Zhang
From: Flora Cui <flora.cui@amd.com>
Enable soc21 common soc support.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 0e0382a82b22..c8ce9588665d 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1479,6 +1479,7 @@ static int amdgpu_discovery_set_common_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &nv_common_ip_block);
break;
case IP_VERSION(11, 0, 0):
+ case IP_VERSION(11, 0, 2):
amdgpu_device_ip_block_add(adev, &soc21_common_ip_block);
break;
default:
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu: add support for ATHUB 3.0.2
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (17 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amdgpu/discovery: " Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amdgpu/discovery: add ih6 support for IH 6.0.2 Alex Deucher
` (4 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Flora Cui, Hawking Zhang
From: Flora Cui <flora.cui@amd.com>
Add support 3.0.2 to the ATHUB 3.0 code.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/athub_v3_0.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c b/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c
index eda07cfe92bb..33a8a7365aef 100644
--- a/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c
+++ b/drivers/gpu/drm/amd/amdgpu/athub_v3_0.c
@@ -70,6 +70,7 @@ int athub_v3_0_set_clockgating(struct amdgpu_device *adev,
switch (adev->ip_versions[ATHUB_HWIP][0]) {
case IP_VERSION(3, 0, 0):
+ case IP_VERSION(3, 0, 2):
athub_v3_0_update_medium_grain_clock_gating(adev,
state == AMD_CG_STATE_GATE);
athub_v3_0_update_medium_grain_light_sleep(adev,
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu/discovery: add ih6 support for IH 6.0.2
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (18 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amdgpu: add support for ATHUB 3.0.2 Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amdgpu/discovery: add smu13 support for MP1 13.0.7 Alex Deucher
` (3 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Flora Cui, Hawking Zhang
From: Flora Cui <flora.cui@amd.com>
Enable Interrupt Handler v6 support.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index c8ce9588665d..fb30c31b5d92 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1556,6 +1556,7 @@ static int amdgpu_discovery_set_ih_ip_blocks(struct amdgpu_device *adev)
amdgpu_device_ip_block_add(adev, &navi10_ih_ip_block);
break;
case IP_VERSION(6, 0, 0):
+ case IP_VERSION(6, 0, 2):
amdgpu_device_ip_block_add(adev, &ih_v6_0_ip_block);
break;
default:
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu/discovery: add smu13 support for MP1 13.0.7
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (19 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amdgpu/discovery: add ih6 support for IH 6.0.2 Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amdgpu/discovery: add nbio 4.3 support for NBIO 4.3.1 Alex Deucher
` (2 subsequent siblings)
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Flora Cui, Hawking Zhang
From: Flora Cui <flora.cui@amd.com>
Enable System Management Unit support.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index fb30c31b5d92..5263f94ff182 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -1646,6 +1646,7 @@ static int amdgpu_discovery_set_smu_ip_blocks(struct amdgpu_device *adev)
case IP_VERSION(13, 0, 2):
case IP_VERSION(13, 0, 3):
case IP_VERSION(13, 0, 5):
+ case IP_VERSION(13, 0, 7):
case IP_VERSION(13, 0, 8):
amdgpu_device_ip_block_add(adev, &smu_v13_0_ip_block);
break;
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu/discovery: add nbio 4.3 support for NBIO 4.3.1
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (20 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amdgpu/discovery: add smu13 support for MP1 13.0.7 Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amdgpu/discovery: add hdp6 support for HDP 6.0.1 Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amdgpu/discovery: add SMUIO_13_0_8 func support Alex Deucher
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Flora Cui, Hawking Zhang
From: Flora Cui <flora.cui@amd.com>
Enable nbio 4.3 support.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 5263f94ff182..26ed3ff8e7d2 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2189,6 +2189,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
adev->nbio.hdp_flush_reg = &nbio_v2_3_hdp_flush_reg_sc;
break;
case IP_VERSION(4, 3, 0):
+ case IP_VERSION(4, 3, 1):
adev->nbio.funcs = &nbio_v4_3_funcs;
adev->nbio.hdp_flush_reg = &nbio_v4_3_hdp_flush_reg;
break;
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu/discovery: add hdp6 support for HDP 6.0.1
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (21 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amdgpu/discovery: add nbio 4.3 support for NBIO 4.3.1 Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
2022-05-03 20:08 ` [PATCH] drm/amdgpu/discovery: add SMUIO_13_0_8 func support Alex Deucher
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Flora Cui, Hawking Zhang
From: Flora Cui <flora.cui@amd.com>
Enable Host Data Path support.
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Flora Cui <flora.cui@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 26ed3ff8e7d2..45383c1b4dc7 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2217,6 +2217,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
adev->hdp.funcs = &hdp_v5_0_funcs;
break;
case IP_VERSION(6, 0, 0):
+ case IP_VERSION(6, 0, 1):
adev->hdp.funcs = &hdp_v6_0_funcs;
break;
default:
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread
* [PATCH] drm/amdgpu/discovery: add SMUIO_13_0_8 func support
2022-05-03 20:08 [PATCH] drm/amd/pm: enable power limit retrieving and setting for SMU 13.0.0 Alex Deucher
` (22 preceding siblings ...)
2022-05-03 20:08 ` [PATCH] drm/amdgpu/discovery: add hdp6 support for HDP 6.0.1 Alex Deucher
@ 2022-05-03 20:08 ` Alex Deucher
23 siblings, 0 replies; 26+ messages in thread
From: Alex Deucher @ 2022-05-03 20:08 UTC (permalink / raw)
To: amd-gfx; +Cc: Alex Deucher, Chengming Gui, Hawking Zhang
From: Chengming Gui <Jack.Gui@amd.com>
Add SMUIO funcs for SMUIO_13_0_8.
Signed-off-by: Chengming Gui <Jack.Gui@amd.com>
Reviewed-by: Hawking Zhang <Hawking.Zhang@amd.com>
Signed-off-by: Alex Deucher <alexander.deucher@amd.com>
---
drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c | 1 +
1 file changed, 1 insertion(+)
diff --git a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
index 45383c1b4dc7..02583b34b996 100644
--- a/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
+++ b/drivers/gpu/drm/amd/amdgpu/amdgpu_discovery.c
@@ -2270,6 +2270,7 @@ int amdgpu_discovery_set_ip_blocks(struct amdgpu_device *adev)
adev->smuio.funcs = &smuio_v13_0_funcs;
break;
case IP_VERSION(13, 0, 6):
+ case IP_VERSION(13, 0, 8):
adev->smuio.funcs = &smuio_v13_0_6_funcs;
break;
default:
--
2.35.1
^ permalink raw reply related [flat|nested] 26+ messages in thread