* [PATCH v3 00/21] target/ppc: Remove hidden usages of *env
@ 2022-05-03 20:24 Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 01/21] target/ppc: Remove fpscr_* macros from cpu.h Víctor Colombo
` (21 more replies)
0 siblings, 22 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
By running the grep command `git grep -nr 'define \(fpscr\|msr\)_[a-z0-9]\+\>'`
we can find multiple macros that use `env->fpscr` and `env->msr` but doesn't
take *env as a parameter.
Richard Henderson said [1] that these macros hiding the usage of *env "are evil".
This patch series remove them and substitute with an explicit usage of *env by
using registerfields API.
Patch 20 (target/ppc: Add unused msr bits FIELDs) declares unused FIELDs, the
same that were removed in patch 02 (target/ppc: Remove unused msr_* macros). I
did that to keep the changes consistent with what was already present before.
Patch 21 (target/ppc: Change MSR_* to follow POWER ISA numbering convention)
changes the MSR_* bit number to match POWER ISA by adding a new macro to
'invert' the ordering. (added in v2)
[1]: https://lists.gnu.org/archive/html/qemu-ppc/2021-11/msg00280.html
Patches requiring review: 11, 14, 15, 16, 17, 21
Patch 17 was reviewed before, but I created a macro to extract both FE0
and FE1, so decided to drop the R-b for you to take a look at the
new version. Thanks
v2:
- Abandon the ideia to add an M_MSR_* macro
- Instead, use registerfields API as suggested by Richard
- Add patch 21 to invert MSR_* values to match ISA ordering
v3:
- Add macro to extract both FE0 and FE1. Use it to simplify the
conditionals in patch 17
- Fix the checks that should be a xor
- Fix incorrect parameter in FIELD_EX64 (was env->msr should be value)
in patch 16
- Fix patch 13 title
Víctor Colombo (21):
target/ppc: Remove fpscr_* macros from cpu.h
target/ppc: Remove unused msr_* macros
target/ppc: Remove msr_pr macro
target/ppc: Remove msr_le macro
target/ppc: Remove msr_ds macro
target/ppc: Remove msr_ile macro
target/ppc: Remove msr_ee macro
target/ppc: Remove msr_ce macro
target/ppc: Remove msr_pow macro
target/ppc: Remove msr_me macro
target/ppc: Remove msr_gs macro
target/ppc: Remove msr_fp macro
target/ppc: Remove msr_cm macro
target/ppc: Remove msr_ir macro
target/ppc: Remove msr_dr macro
target/ppc: Remove msr_ep macro
target/ppc: Remove msr_fe0 and msr_fe1 macros
target/ppc: Remove msr_ts macro
target/ppc: Remove msr_hv macro
target/ppc: Add unused msr bits FIELDs
target/ppc: Change MSR_* to follow POWER ISA numbering convention
hw/ppc/pegasos2.c | 2 +-
hw/ppc/spapr.c | 2 +-
target/ppc/cpu.c | 2 +-
target/ppc/cpu.h | 219 ++++++++++++++++++---------------------
target/ppc/cpu_init.c | 23 ++--
target/ppc/excp_helper.c | 54 +++++-----
target/ppc/fpu_helper.c | 28 ++---
target/ppc/gdbstub.c | 2 +-
target/ppc/helper_regs.c | 11 +-
target/ppc/kvm.c | 7 +-
target/ppc/machine.c | 2 +-
target/ppc/mem_helper.c | 23 ++--
target/ppc/misc_helper.c | 2 +-
target/ppc/mmu-radix64.c | 11 +-
target/ppc/mmu_common.c | 40 +++----
target/ppc/mmu_helper.c | 6 +-
16 files changed, 217 insertions(+), 217 deletions(-)
--
2.25.1
^ permalink raw reply [flat|nested] 29+ messages in thread
* [PATCH v3 01/21] target/ppc: Remove fpscr_* macros from cpu.h
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 02/21] target/ppc: Remove unused msr_* macros Víctor Colombo
` (20 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
fpscr_* defined macros are hiding the usage of *env behind them.
Substitute the usage of these macros with `env->fpscr & FP_*` to make
the code cleaner.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/cpu.c | 2 +-
target/ppc/cpu.h | 29 -----------------------------
target/ppc/fpu_helper.c | 28 ++++++++++++++--------------
3 files changed, 15 insertions(+), 44 deletions(-)
diff --git a/target/ppc/cpu.c b/target/ppc/cpu.c
index d7b42bae52..401b6f9e63 100644
--- a/target/ppc/cpu.c
+++ b/target/ppc/cpu.c
@@ -88,7 +88,7 @@ static inline void fpscr_set_rounding_mode(CPUPPCState *env)
int rnd_type;
/* Set rounding mode */
- switch (fpscr_rn) {
+ switch (env->fpscr & FP_RN) {
case 0:
/* Best approximation (round to nearest) */
rnd_type = float_round_nearest_even;
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index c2b6c987c0..ad31e51d69 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -713,41 +713,12 @@ enum {
#define FPSCR_NI 2 /* Floating-point non-IEEE mode */
#define FPSCR_RN1 1
#define FPSCR_RN0 0 /* Floating-point rounding control */
-#define fpscr_drn (((env->fpscr) & FP_DRN) >> FPSCR_DRN0)
-#define fpscr_fex (((env->fpscr) >> FPSCR_FEX) & 0x1)
-#define fpscr_vx (((env->fpscr) >> FPSCR_VX) & 0x1)
-#define fpscr_ox (((env->fpscr) >> FPSCR_OX) & 0x1)
-#define fpscr_ux (((env->fpscr) >> FPSCR_UX) & 0x1)
-#define fpscr_zx (((env->fpscr) >> FPSCR_ZX) & 0x1)
-#define fpscr_xx (((env->fpscr) >> FPSCR_XX) & 0x1)
-#define fpscr_vxsnan (((env->fpscr) >> FPSCR_VXSNAN) & 0x1)
-#define fpscr_vxisi (((env->fpscr) >> FPSCR_VXISI) & 0x1)
-#define fpscr_vxidi (((env->fpscr) >> FPSCR_VXIDI) & 0x1)
-#define fpscr_vxzdz (((env->fpscr) >> FPSCR_VXZDZ) & 0x1)
-#define fpscr_vximz (((env->fpscr) >> FPSCR_VXIMZ) & 0x1)
-#define fpscr_vxvc (((env->fpscr) >> FPSCR_VXVC) & 0x1)
-#define fpscr_fpcc (((env->fpscr) >> FPSCR_FPCC) & 0xF)
-#define fpscr_vxsoft (((env->fpscr) >> FPSCR_VXSOFT) & 0x1)
-#define fpscr_vxsqrt (((env->fpscr) >> FPSCR_VXSQRT) & 0x1)
-#define fpscr_vxcvi (((env->fpscr) >> FPSCR_VXCVI) & 0x1)
-#define fpscr_ve (((env->fpscr) >> FPSCR_VE) & 0x1)
-#define fpscr_oe (((env->fpscr) >> FPSCR_OE) & 0x1)
-#define fpscr_ue (((env->fpscr) >> FPSCR_UE) & 0x1)
-#define fpscr_ze (((env->fpscr) >> FPSCR_ZE) & 0x1)
-#define fpscr_xe (((env->fpscr) >> FPSCR_XE) & 0x1)
-#define fpscr_ni (((env->fpscr) >> FPSCR_NI) & 0x1)
-#define fpscr_rn (((env->fpscr) >> FPSCR_RN0) & 0x3)
/* Invalid operation exception summary */
#define FPSCR_IX ((1 << FPSCR_VXSNAN) | (1 << FPSCR_VXISI) | \
(1 << FPSCR_VXIDI) | (1 << FPSCR_VXZDZ) | \
(1 << FPSCR_VXIMZ) | (1 << FPSCR_VXVC) | \
(1 << FPSCR_VXSOFT) | (1 << FPSCR_VXSQRT) | \
(1 << FPSCR_VXCVI))
-/* exception summary */
-#define fpscr_ex (((env->fpscr) >> FPSCR_XX) & 0x1F)
-/* enabled exception summary */
-#define fpscr_eex (((env->fpscr) >> FPSCR_XX) & ((env->fpscr) >> FPSCR_XE) & \
- 0x1F)
#define FP_DRN2 (1ull << FPSCR_DRN2)
#define FP_DRN1 (1ull << FPSCR_DRN1)
diff --git a/target/ppc/fpu_helper.c b/target/ppc/fpu_helper.c
index 99281cc37a..f6c8318a71 100644
--- a/target/ppc/fpu_helper.c
+++ b/target/ppc/fpu_helper.c
@@ -202,7 +202,7 @@ static void finish_invalid_op_excp(CPUPPCState *env, int op, uintptr_t retaddr)
env->fpscr |= FP_VX;
/* Update the floating-point exception summary */
env->fpscr |= FP_FX;
- if (fpscr_ve != 0) {
+ if (env->fpscr & FP_VE) {
/* Update the floating-point enabled exception summary */
env->fpscr |= FP_FEX;
if (fp_exceptions_enabled(env)) {
@@ -216,7 +216,7 @@ static void finish_invalid_op_arith(CPUPPCState *env, int op,
bool set_fpcc, uintptr_t retaddr)
{
env->fpscr &= ~(FP_FR | FP_FI);
- if (fpscr_ve == 0) {
+ if (!(env->fpscr & FP_VE)) {
if (set_fpcc) {
env->fpscr &= ~FP_FPCC;
env->fpscr |= (FP_C | FP_FU);
@@ -286,7 +286,7 @@ static void float_invalid_op_vxvc(CPUPPCState *env, bool set_fpcc,
/* Update the floating-point exception summary */
env->fpscr |= FP_FX;
/* We must update the target FPR before raising the exception */
- if (fpscr_ve != 0) {
+ if (env->fpscr & FP_VE) {
CPUState *cs = env_cpu(env);
cs->exception_index = POWERPC_EXCP_PROGRAM;
@@ -303,7 +303,7 @@ static void float_invalid_op_vxcvi(CPUPPCState *env, bool set_fpcc,
{
env->fpscr |= FP_VXCVI;
env->fpscr &= ~(FP_FR | FP_FI);
- if (fpscr_ve == 0) {
+ if (!(env->fpscr & FP_VE)) {
if (set_fpcc) {
env->fpscr &= ~FP_FPCC;
env->fpscr |= (FP_C | FP_FU);
@@ -318,7 +318,7 @@ static inline void float_zero_divide_excp(CPUPPCState *env, uintptr_t raddr)
env->fpscr &= ~(FP_FR | FP_FI);
/* Update the floating-point exception summary */
env->fpscr |= FP_FX;
- if (fpscr_ze != 0) {
+ if (env->fpscr & FP_ZE) {
/* Update the floating-point enabled exception summary */
env->fpscr |= FP_FEX;
if (fp_exceptions_enabled(env)) {
@@ -336,7 +336,7 @@ static inline void float_overflow_excp(CPUPPCState *env)
env->fpscr |= FP_OX;
/* Update the floating-point exception summary */
env->fpscr |= FP_FX;
- if (fpscr_oe != 0) {
+ if (env->fpscr & FP_OE) {
/* XXX: should adjust the result */
/* Update the floating-point enabled exception summary */
env->fpscr |= FP_FEX;
@@ -356,7 +356,7 @@ static inline void float_underflow_excp(CPUPPCState *env)
env->fpscr |= FP_UX;
/* Update the floating-point exception summary */
env->fpscr |= FP_FX;
- if (fpscr_ue != 0) {
+ if (env->fpscr & FP_UE) {
/* XXX: should adjust the result */
/* Update the floating-point enabled exception summary */
env->fpscr |= FP_FEX;
@@ -374,7 +374,7 @@ static inline void float_inexact_excp(CPUPPCState *env)
env->fpscr |= FP_XX;
/* Update the floating-point exception summary */
env->fpscr |= FP_FX;
- if (fpscr_xe != 0) {
+ if (env->fpscr & FP_XE) {
/* Update the floating-point enabled exception summary */
env->fpscr |= FP_FEX;
/* We must update the target FPR before raising the exception */
@@ -2274,7 +2274,7 @@ VSX_MADDQ(XSNMSUBQPO, NMSUB_FLGS, 0)
vxvc = svxvc; \
if (flags & float_flag_invalid_snan) { \
float_invalid_op_vxsnan(env, GETPC()); \
- vxvc &= fpscr_ve == 0; \
+ vxvc &= !(env->fpscr & FP_VE); \
} \
if (vxvc) { \
float_invalid_op_vxvc(env, 0, GETPC()); \
@@ -2375,7 +2375,7 @@ static inline void do_scalar_cmp(CPUPPCState *env, ppc_vsr_t *xa, ppc_vsr_t *xb,
if (float64_is_signaling_nan(xa->VsrD(0), &env->fp_status) ||
float64_is_signaling_nan(xb->VsrD(0), &env->fp_status)) {
vxsnan_flag = true;
- if (fpscr_ve == 0 && ordered) {
+ if (!(env->fpscr & FP_VE) && ordered) {
vxvc_flag = true;
}
} else if (float64_is_quiet_nan(xa->VsrD(0), &env->fp_status) ||
@@ -2440,7 +2440,7 @@ static inline void do_scalar_cmpq(CPUPPCState *env, ppc_vsr_t *xa,
if (float128_is_signaling_nan(xa->f128, &env->fp_status) ||
float128_is_signaling_nan(xb->f128, &env->fp_status)) {
vxsnan_flag = true;
- if (fpscr_ve == 0 && ordered) {
+ if (!(env->fpscr & FP_VE) && ordered) {
vxvc_flag = true;
}
} else if (float128_is_quiet_nan(xa->f128, &env->fp_status) ||
@@ -2590,7 +2590,7 @@ void helper_##name(CPUPPCState *env, \
t.VsrD(0) = xb->VsrD(0); \
} \
\
- vex_flag = fpscr_ve & vxsnan_flag; \
+ vex_flag = (env->fpscr & FP_VE) && vxsnan_flag; \
if (vxsnan_flag) { \
float_invalid_op_vxsnan(env, GETPC()); \
} \
@@ -3320,7 +3320,7 @@ void helper_xsrqpi(CPUPPCState *env, uint32_t opcode,
if (r == 0 && rmc == 0) {
rmode = float_round_ties_away;
} else if (r == 0 && rmc == 0x3) {
- rmode = fpscr_rn;
+ rmode = env->fpscr & FP_RN;
} else if (r == 1) {
switch (rmc) {
case 0:
@@ -3374,7 +3374,7 @@ void helper_xsrqpxp(CPUPPCState *env, uint32_t opcode,
if (r == 0 && rmc == 0) {
rmode = float_round_ties_away;
} else if (r == 0 && rmc == 0x3) {
- rmode = fpscr_rn;
+ rmode = env->fpscr & FP_RN;
} else if (r == 1) {
switch (rmc) {
case 0:
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 02/21] target/ppc: Remove unused msr_* macros
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 01/21] target/ppc: Remove fpscr_* macros from cpu.h Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 03/21] target/ppc: Remove msr_pr macro Víctor Colombo
` (19 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
Some msr_* macros are not used anywhere. Remove them as part of
the work to remove all hidden usage of *env.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/cpu.h | 21 ---------------------
1 file changed, 21 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index ad31e51d69..106b555b86 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -463,23 +463,14 @@ typedef enum {
#define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
#define HFSCR_IC_MSGP 0xA
-#define msr_sf ((env->msr >> MSR_SF) & 1)
-#define msr_isf ((env->msr >> MSR_ISF) & 1)
#if defined(TARGET_PPC64)
#define msr_hv ((env->msr >> MSR_HV) & 1)
#else
#define msr_hv (0)
#endif
#define msr_cm ((env->msr >> MSR_CM) & 1)
-#define msr_icm ((env->msr >> MSR_ICM) & 1)
#define msr_gs ((env->msr >> MSR_GS) & 1)
-#define msr_ucle ((env->msr >> MSR_UCLE) & 1)
-#define msr_vr ((env->msr >> MSR_VR) & 1)
-#define msr_spe ((env->msr >> MSR_SPE) & 1)
-#define msr_vsx ((env->msr >> MSR_VSX) & 1)
-#define msr_key ((env->msr >> MSR_KEY) & 1)
#define msr_pow ((env->msr >> MSR_POW) & 1)
-#define msr_tgpr ((env->msr >> MSR_TGPR) & 1)
#define msr_ce ((env->msr >> MSR_CE) & 1)
#define msr_ile ((env->msr >> MSR_ILE) & 1)
#define msr_ee ((env->msr >> MSR_EE) & 1)
@@ -487,25 +478,13 @@ typedef enum {
#define msr_fp ((env->msr >> MSR_FP) & 1)
#define msr_me ((env->msr >> MSR_ME) & 1)
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
-#define msr_se ((env->msr >> MSR_SE) & 1)
-#define msr_dwe ((env->msr >> MSR_DWE) & 1)
-#define msr_uble ((env->msr >> MSR_UBLE) & 1)
-#define msr_be ((env->msr >> MSR_BE) & 1)
-#define msr_de ((env->msr >> MSR_DE) & 1)
#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
-#define msr_al ((env->msr >> MSR_AL) & 1)
#define msr_ep ((env->msr >> MSR_EP) & 1)
#define msr_ir ((env->msr >> MSR_IR) & 1)
#define msr_dr ((env->msr >> MSR_DR) & 1)
-#define msr_is ((env->msr >> MSR_IS) & 1)
#define msr_ds ((env->msr >> MSR_DS) & 1)
-#define msr_pe ((env->msr >> MSR_PE) & 1)
-#define msr_px ((env->msr >> MSR_PX) & 1)
-#define msr_pmm ((env->msr >> MSR_PMM) & 1)
-#define msr_ri ((env->msr >> MSR_RI) & 1)
#define msr_le ((env->msr >> MSR_LE) & 1)
#define msr_ts ((env->msr >> MSR_TS1) & 3)
-#define msr_tm ((env->msr >> MSR_TM) & 1)
#define DBCR0_ICMP (1 << 27)
#define DBCR0_BRT (1 << 26)
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 03/21] target/ppc: Remove msr_pr macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 01/21] target/ppc: Remove fpscr_* macros from cpu.h Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 02/21] target/ppc: Remove unused msr_* macros Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 04/21] target/ppc: Remove msr_le macro Víctor Colombo
` (18 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_pr macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
hw/ppc/pegasos2.c | 2 +-
hw/ppc/spapr.c | 2 +-
target/ppc/cpu.h | 4 +++-
target/ppc/cpu_init.c | 4 ++--
target/ppc/excp_helper.c | 8 +++++---
target/ppc/mem_helper.c | 5 +++--
target/ppc/mmu-radix64.c | 5 +++--
target/ppc/mmu_common.c | 23 ++++++++++++-----------
8 files changed, 30 insertions(+), 23 deletions(-)
diff --git a/hw/ppc/pegasos2.c b/hw/ppc/pegasos2.c
index 56bf203dfd..9411ca6b16 100644
--- a/hw/ppc/pegasos2.c
+++ b/hw/ppc/pegasos2.c
@@ -461,7 +461,7 @@ static void pegasos2_hypercall(PPCVirtualHypervisor *vhyp, PowerPCCPU *cpu)
/* The TCG path should also be holding the BQL at this point */
g_assert(qemu_mutex_iothread_locked());
- if (msr_pr) {
+ if (FIELD_EX64(env->msr, MSR, PR)) {
qemu_log_mask(LOG_GUEST_ERROR, "Hypercall made with MSR[PR]=1\n");
env->gpr[3] = H_PRIVILEGE;
} else if (env->gpr[3] == KVMPPC_H_RTAS) {
diff --git a/hw/ppc/spapr.c b/hw/ppc/spapr.c
index 22569305d2..fe9937e811 100644
--- a/hw/ppc/spapr.c
+++ b/hw/ppc/spapr.c
@@ -1269,7 +1269,7 @@ static void emulate_spapr_hypercall(PPCVirtualHypervisor *vhyp,
g_assert(!vhyp_cpu_in_nested(cpu));
- if (msr_pr) {
+ if (FIELD_EX64(env->msr, MSR, PR)) {
hcall_dprintf("Hypercall made with MSR[PR]=1\n");
env->gpr[3] = H_PRIVILEGE;
} else {
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 106b555b86..21d1f14381 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -25,6 +25,7 @@
#include "exec/cpu-defs.h"
#include "cpu-qom.h"
#include "qom/object.h"
+#include "hw/registerfields.h"
#define TCG_GUEST_DEFAULT_MO 0
@@ -353,6 +354,8 @@ typedef enum {
#define MSR_RI 1 /* Recoverable interrupt 1 */
#define MSR_LE 0 /* Little-endian mode 1 hflags */
+FIELD(MSR, PR, MSR_PR, 1)
+
/* PMU bits */
#define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
#define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Ocurred */
@@ -474,7 +477,6 @@ typedef enum {
#define msr_ce ((env->msr >> MSR_CE) & 1)
#define msr_ile ((env->msr >> MSR_ILE) & 1)
#define msr_ee ((env->msr >> MSR_EE) & 1)
-#define msr_pr ((env->msr >> MSR_PR) & 1)
#define msr_fp ((env->msr >> MSR_FP) & 1)
#define msr_me ((env->msr >> MSR_ME) & 1)
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index d42e2ba8e0..ac16a64846 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6303,7 +6303,7 @@ static bool cpu_has_work_POWER9(CPUState *cs)
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
(env->spr[SPR_LPCR] & LPCR_EEE)) {
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
- if (heic == 0 || !msr_hv || msr_pr) {
+ if (!heic || !msr_hv || FIELD_EX64(env->msr, MSR, PR)) {
return true;
}
}
@@ -6517,7 +6517,7 @@ static bool cpu_has_work_POWER10(CPUState *cs)
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
(env->spr[SPR_LPCR] & LPCR_EEE)) {
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
- if (heic == 0 || !msr_hv || msr_pr) {
+ if (!heic || !msr_hv || FIELD_EX64(env->msr, MSR, PR)) {
return true;
}
}
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index d3e2cfcd71..7e8e34ef06 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1738,7 +1738,8 @@ static void ppc_hw_interrupt(CPUPPCState *env)
bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
/* HEIC blocks delivery to the hypervisor */
- if ((async_deliver && !(heic && msr_hv && !msr_pr)) ||
+ if ((async_deliver && !(heic && msr_hv &&
+ !FIELD_EX64(env->msr, MSR, PR))) ||
(env->has_hv_mode && msr_hv == 0 && !lpes0)) {
if (books_vhyp_promotes_external_to_hvirt(cpu)) {
powerpc_excp(cpu, POWERPC_EXCP_HVIRT);
@@ -1818,7 +1819,8 @@ static void ppc_hw_interrupt(CPUPPCState *env)
* EBB exception must be taken in problem state and
* with BESCR_GE set.
*/
- if (msr_pr == 1 && env->spr[SPR_BESCR] & BESCR_GE) {
+ if (FIELD_EX64(env->msr, MSR, PR) &&
+ (env->spr[SPR_BESCR] & BESCR_GE)) {
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_EBB);
if (env->spr[SPR_BESCR] & BESCR_PMEO) {
@@ -2094,7 +2096,7 @@ static void do_ebb(CPUPPCState *env, int ebb_excp)
env->spr[SPR_BESCR] |= BESCR_EEO;
}
- if (msr_pr == 1) {
+ if (FIELD_EX64(env->msr, MSR, PR)) {
powerpc_excp(cpu, ebb_excp);
} else {
env->pending_interrupts |= 1 << PPC_INTERRUPT_EBB;
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index c4ff8fd632..fba7f84b7a 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -613,10 +613,11 @@ void helper_tbegin(CPUPPCState *env)
(1ULL << TEXASR_FAILURE_PERSISTENT) |
(1ULL << TEXASR_NESTING_OVERFLOW) |
(msr_hv << TEXASR_PRIVILEGE_HV) |
- (msr_pr << TEXASR_PRIVILEGE_PR) |
+ (FIELD_EX64(env->msr, MSR, PR) << TEXASR_PRIVILEGE_PR) |
(1ULL << TEXASR_FAILURE_SUMMARY) |
(1ULL << TEXASR_TFIAR_EXACT);
- env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) | msr_pr;
+ env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) |
+ FIELD_EX64(env->msr, MSR, PR);
env->spr[SPR_TFHAR] = env->nip + 4;
env->crf[0] = 0xB; /* 0b1010 = transaction failure */
}
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index 5414fd63c1..e88f51fd34 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -191,12 +191,13 @@ static bool ppc_radix64_check_prot(PowerPCCPU *cpu, MMUAccessType access_type,
}
/* Determine permissions allowed by Encoded Access Authority */
- if (!partition_scoped && (pte & R_PTE_EAA_PRIV) && msr_pr) {
+ if (!partition_scoped && (pte & R_PTE_EAA_PRIV) &&
+ FIELD_EX64(env->msr, MSR, PR)) {
*prot = 0;
} else if (mmuidx_pr(mmu_idx) || (pte & R_PTE_EAA_PRIV) ||
partition_scoped) {
*prot = ppc_radix64_get_prot_eaa(pte);
- } else { /* !msr_pr && !(pte & R_PTE_EAA_PRIV) && !partition_scoped */
+ } else { /* !MSR_PR && !(pte & R_PTE_EAA_PRIV) && !partition_scoped */
*prot = ppc_radix64_get_prot_eaa(pte);
*prot &= ppc_radix64_get_prot_amr(cpu); /* Least combined permissions */
}
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index e9c5b14c0f..6ef8b1c00d 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -273,8 +273,8 @@ static inline void bat_size_prot(CPUPPCState *env, target_ulong *blp,
bl = (*BATu & 0x00001FFC) << 15;
valid = 0;
prot = 0;
- if (((msr_pr == 0) && (*BATu & 0x00000002)) ||
- ((msr_pr != 0) && (*BATu & 0x00000001))) {
+ if ((!FIELD_EX64(env->msr, MSR, PR) && (*BATu & 0x00000002)) ||
+ (FIELD_EX64(env->msr, MSR, PR) && (*BATu & 0x00000001))) {
valid = 1;
pp = *BATl & 0x00000003;
if (pp != 0) {
@@ -368,16 +368,17 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
PowerPCCPU *cpu = env_archcpu(env);
hwaddr hash;
target_ulong vsid;
- int ds, pr, target_page_bits;
+ int ds, target_page_bits;
+ bool pr;
int ret;
target_ulong sr, pgidx;
- pr = msr_pr;
+ pr = FIELD_EX64(env->msr, MSR, PR);
ctx->eaddr = eaddr;
sr = env->sr[eaddr >> 28];
- ctx->key = (((sr & 0x20000000) && (pr != 0)) ||
- ((sr & 0x40000000) && (pr == 0))) ? 1 : 0;
+ ctx->key = (((sr & 0x20000000) && pr) ||
+ ((sr & 0x40000000) && !pr)) ? 1 : 0;
ds = sr & 0x80000000 ? 1 : 0;
ctx->nx = sr & 0x10000000 ? 1 : 0;
vsid = sr & 0x00FFFFFF;
@@ -386,8 +387,8 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
"Check segment v=" TARGET_FMT_lx " %d " TARGET_FMT_lx
" nip=" TARGET_FMT_lx " lr=" TARGET_FMT_lx
" ir=%d dr=%d pr=%d %d t=%d\n",
- eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr, (int)msr_ir,
- (int)msr_dr, pr != 0 ? 1 : 0,
+ eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr,
+ (int)msr_ir, (int)msr_dr, pr ? 1 : 0,
access_type == MMU_DATA_STORE, type);
pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
hash = vsid ^ pgidx;
@@ -530,7 +531,7 @@ static int mmu40x_get_physical_address(CPUPPCState *env, mmu_ctx_t *ctx,
ret = -1;
raddr = (hwaddr)-1ULL;
- pr = msr_pr;
+ pr = FIELD_EX64(env->msr, MSR, PR);
for (i = 0; i < env->nb_tlb; i++) {
tlb = &env->tlb.tlbe[i];
if (ppcemb_tlb_check(env, tlb, &raddr, address,
@@ -618,7 +619,7 @@ static int mmubooke_check_tlb(CPUPPCState *env, ppcemb_tlb_t *tlb,
found_tlb:
- if (msr_pr != 0) {
+ if (FIELD_EX64(env->msr, MSR, PR)) {
prot2 = tlb->prot & 0xF;
} else {
prot2 = (tlb->prot >> 4) & 0xF;
@@ -768,7 +769,7 @@ static bool mmubooke206_get_as(CPUPPCState *env,
return true;
} else {
*as_out = msr_ds;
- *pr_out = msr_pr;
+ *pr_out = FIELD_EX64(env->msr, MSR, PR);
return false;
}
}
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 04/21] target/ppc: Remove msr_le macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (2 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 03/21] target/ppc: Remove msr_pr macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 05/21] target/ppc: Remove msr_ds macro Víctor Colombo
` (17 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_le macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 2 +-
target/ppc/cpu_init.c | 2 +-
target/ppc/gdbstub.c | 2 +-
target/ppc/mem_helper.c | 16 ++++++++--------
4 files changed, 11 insertions(+), 11 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 21d1f14381..932c5f4bdd 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -355,6 +355,7 @@ typedef enum {
#define MSR_LE 0 /* Little-endian mode 1 hflags */
FIELD(MSR, PR, MSR_PR, 1)
+FIELD(MSR, LE, MSR_LE, 1)
/* PMU bits */
#define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
@@ -485,7 +486,6 @@ FIELD(MSR, PR, MSR_PR, 1)
#define msr_ir ((env->msr >> MSR_IR) & 1)
#define msr_dr ((env->msr >> MSR_DR) & 1)
#define msr_ds ((env->msr >> MSR_DS) & 1)
-#define msr_le ((env->msr >> MSR_LE) & 1)
#define msr_ts ((env->msr >> MSR_TS1) & 3)
#define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index ac16a64846..0c6b83406e 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -7210,7 +7210,7 @@ static bool ppc_cpu_is_big_endian(CPUState *cs)
cpu_synchronize_state(cs);
- return !msr_le;
+ return !FIELD_EX64(env->msr, MSR, LE);
}
#ifdef CONFIG_TCG
diff --git a/target/ppc/gdbstub.c b/target/ppc/gdbstub.c
index 1252429a2a..1a0b9ca82c 100644
--- a/target/ppc/gdbstub.c
+++ b/target/ppc/gdbstub.c
@@ -95,7 +95,7 @@ static int ppc_gdb_register_len(int n)
void ppc_maybe_bswap_register(CPUPPCState *env, uint8_t *mem_buf, int len)
{
#ifndef CONFIG_USER_ONLY
- if (!msr_le) {
+ if (!FIELD_EX64(env->msr, MSR, LE)) {
/* do nothing */
} else if (len == 4) {
bswap32s((uint32_t *)mem_buf);
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index fba7f84b7a..9af135e88e 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -33,9 +33,9 @@
static inline bool needs_byteswap(const CPUPPCState *env)
{
#if TARGET_BIG_ENDIAN
- return msr_le;
+ return FIELD_EX64(env->msr, MSR, LE);
#else
- return !msr_le;
+ return !FIELD_EX64(env->msr, MSR, LE);
#endif
}
@@ -470,8 +470,8 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr,
#endif
/*
- * We use msr_le to determine index ordering in a vector. However,
- * byteswapping is not simply controlled by msr_le. We also need to
+ * We use MSR_LE to determine index ordering in a vector. However,
+ * byteswapping is not simply controlled by MSR_LE. We also need to
* take into account endianness of the target. This is done for the
* little-endian PPC64 user-mode target.
*/
@@ -484,7 +484,7 @@ uint32_t helper_stqcx_be_parallel(CPUPPCState *env, target_ulong addr,
int adjust = HI_IDX * (n_elems - 1); \
int sh = sizeof(r->element[0]) >> 1; \
int index = (addr & 0xf) >> sh; \
- if (msr_le) { \
+ if (FIELD_EX64(env->msr, MSR, LE)) { \
index = n_elems - index - 1; \
} \
\
@@ -511,7 +511,7 @@ LVE(lvewx, cpu_ldl_data_ra, bswap32, u32)
int adjust = HI_IDX * (n_elems - 1); \
int sh = sizeof(r->element[0]) >> 1; \
int index = (addr & 0xf) >> sh; \
- if (msr_le) { \
+ if (FIELD_EX64(env->msr, MSR, LE)) { \
index = n_elems - index - 1; \
} \
\
@@ -545,7 +545,7 @@ void helper_##name(CPUPPCState *env, target_ulong addr, \
t.s128 = int128_zero(); \
if (nb) { \
nb = (nb >= 16) ? 16 : nb; \
- if (msr_le && !lj) { \
+ if (FIELD_EX64(env->msr, MSR, LE) && !lj) { \
for (i = 16; i > 16 - nb; i--) { \
t.VsrB(i - 1) = cpu_ldub_data_ra(env, addr, GETPC()); \
addr = addr_add(env, addr, 1); \
@@ -576,7 +576,7 @@ void helper_##name(CPUPPCState *env, target_ulong addr, \
} \
\
nb = (nb >= 16) ? 16 : nb; \
- if (msr_le && !lj) { \
+ if (FIELD_EX64(env->msr, MSR, LE) && !lj) { \
for (i = 16; i > 16 - nb; i--) { \
cpu_stb_data_ra(env, addr, xt->VsrB(i - 1), GETPC()); \
addr = addr_add(env, addr, 1); \
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 05/21] target/ppc: Remove msr_ds macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (3 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 04/21] target/ppc: Remove msr_le macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 06/21] target/ppc: Remove msr_ile macro Víctor Colombo
` (16 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_ds macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 2 +-
target/ppc/mmu_common.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 932c5f4bdd..8aff6f1faf 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -355,6 +355,7 @@ typedef enum {
#define MSR_LE 0 /* Little-endian mode 1 hflags */
FIELD(MSR, PR, MSR_PR, 1)
+FIELD(MSR, DS, MSR_DS, 1)
FIELD(MSR, LE, MSR_LE, 1)
/* PMU bits */
@@ -485,7 +486,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#define msr_ep ((env->msr >> MSR_EP) & 1)
#define msr_ir ((env->msr >> MSR_IR) & 1)
#define msr_dr ((env->msr >> MSR_DR) & 1)
-#define msr_ds ((env->msr >> MSR_DS) & 1)
#define msr_ts ((env->msr >> MSR_TS1) & 3)
#define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 6ef8b1c00d..7e77b9b84a 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -768,7 +768,7 @@ static bool mmubooke206_get_as(CPUPPCState *env,
*pr_out = !!(epidr & EPID_EPR);
return true;
} else {
- *as_out = msr_ds;
+ *as_out = FIELD_EX64(env->msr, MSR, DS);
*pr_out = FIELD_EX64(env->msr, MSR, PR);
return false;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 06/21] target/ppc: Remove msr_ile macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (4 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 05/21] target/ppc: Remove msr_ds macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 07/21] target/ppc: Remove msr_ee macro Víctor Colombo
` (15 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_ile macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 8aff6f1faf..d4a0d7e082 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -354,6 +354,7 @@ typedef enum {
#define MSR_RI 1 /* Recoverable interrupt 1 */
#define MSR_LE 0 /* Little-endian mode 1 hflags */
+FIELD(MSR, ILE, MSR_ILE, 1)
FIELD(MSR, PR, MSR_PR, 1)
FIELD(MSR, DS, MSR_DS, 1)
FIELD(MSR, LE, MSR_LE, 1)
@@ -477,7 +478,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#define msr_gs ((env->msr >> MSR_GS) & 1)
#define msr_pow ((env->msr >> MSR_POW) & 1)
#define msr_ce ((env->msr >> MSR_CE) & 1)
-#define msr_ile ((env->msr >> MSR_ILE) & 1)
#define msr_ee ((env->msr >> MSR_EE) & 1)
#define msr_fp ((env->msr >> MSR_FP) & 1)
#define msr_me ((env->msr >> MSR_ME) & 1)
@@ -2678,7 +2678,7 @@ static inline bool ppc_interrupts_little_endian(PowerPCCPU *cpu, bool hv)
} else if (pcc->lpcr_mask & LPCR_ILE) {
ile = !!(env->spr[SPR_LPCR] & LPCR_ILE);
} else {
- ile = !!(msr_ile);
+ ile = FIELD_EX64(env->msr, MSR, ILE);
}
return ile;
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 07/21] target/ppc: Remove msr_ee macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (5 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 06/21] target/ppc: Remove msr_ile macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 08/21] target/ppc: Remove msr_ce macro Víctor Colombo
` (14 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_ee macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 2 +-
target/ppc/cpu_init.c | 15 ++++++++++-----
target/ppc/excp_helper.c | 2 +-
target/ppc/kvm.c | 3 ++-
4 files changed, 14 insertions(+), 8 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index d4a0d7e082..51db67ff92 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -355,6 +355,7 @@ typedef enum {
#define MSR_LE 0 /* Little-endian mode 1 hflags */
FIELD(MSR, ILE, MSR_ILE, 1)
+FIELD(MSR, EE, MSR_EE, 1)
FIELD(MSR, PR, MSR_PR, 1)
FIELD(MSR, DS, MSR_DS, 1)
FIELD(MSR, LE, MSR_LE, 1)
@@ -478,7 +479,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#define msr_gs ((env->msr >> MSR_GS) & 1)
#define msr_pow ((env->msr >> MSR_POW) & 1)
#define msr_ce ((env->msr >> MSR_CE) & 1)
-#define msr_ee ((env->msr >> MSR_EE) & 1)
#define msr_fp ((env->msr >> MSR_FP) & 1)
#define msr_me ((env->msr >> MSR_ME) & 1)
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 0c6b83406e..10e7c41bc9 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -5949,7 +5949,8 @@ static bool cpu_has_work_POWER7(CPUState *cs)
}
return false;
} else {
- return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+ return FIELD_EX64(env->msr, MSR, EE) &&
+ (cs->interrupt_request & CPU_INTERRUPT_HARD);
}
}
@@ -6120,7 +6121,8 @@ static bool cpu_has_work_POWER8(CPUState *cs)
}
return false;
} else {
- return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+ return FIELD_EX64(env->msr, MSR, EE) &&
+ (cs->interrupt_request & CPU_INTERRUPT_HARD);
}
}
@@ -6337,7 +6339,8 @@ static bool cpu_has_work_POWER9(CPUState *cs)
}
return false;
} else {
- return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+ return FIELD_EX64(env->msr, MSR, EE) &&
+ (cs->interrupt_request & CPU_INTERRUPT_HARD);
}
}
@@ -6551,7 +6554,8 @@ static bool cpu_has_work_POWER10(CPUState *cs)
}
return false;
} else {
- return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+ return FIELD_EX64(env->msr, MSR, EE) &&
+ (cs->interrupt_request & CPU_INTERRUPT_HARD);
}
}
@@ -7119,7 +7123,8 @@ static bool ppc_cpu_has_work(CPUState *cs)
PowerPCCPU *cpu = POWERPC_CPU(cs);
CPUPPCState *env = &cpu->env;
- return msr_ee && (cs->interrupt_request & CPU_INTERRUPT_HARD);
+ return FIELD_EX64(env->msr, MSR, EE) &&
+ (cs->interrupt_request & CPU_INTERRUPT_HARD);
}
static void ppc_cpu_reset(DeviceState *dev)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 7e8e34ef06..4c206ba209 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1709,7 +1709,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
* clear when coming out of some power management states (in order
* for them to become a 0x100).
*/
- async_deliver = (msr_ee != 0) || env->resume_as_sreset;
+ async_deliver = FIELD_EX64(env->msr, MSR, EE) || env->resume_as_sreset;
/* Hypervisor decrementer exception */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index a3c31b4e48..8276326de9 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -1351,7 +1351,8 @@ static int kvmppc_handle_halt(PowerPCCPU *cpu)
CPUState *cs = CPU(cpu);
CPUPPCState *env = &cpu->env;
- if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) && (msr_ee)) {
+ if (!(cs->interrupt_request & CPU_INTERRUPT_HARD) &&
+ FIELD_EX64(env->msr, MSR, EE)) {
cs->halted = 1;
cs->exception_index = EXCP_HLT;
}
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 08/21] target/ppc: Remove msr_ce macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (6 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 07/21] target/ppc: Remove msr_ee macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 09/21] target/ppc: Remove msr_pow macro Víctor Colombo
` (13 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_ce macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 2 +-
target/ppc/excp_helper.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 51db67ff92..65cb457e6f 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -354,6 +354,7 @@ typedef enum {
#define MSR_RI 1 /* Recoverable interrupt 1 */
#define MSR_LE 0 /* Little-endian mode 1 hflags */
+FIELD(MSR, CE, MSR_CE, 1)
FIELD(MSR, ILE, MSR_ILE, 1)
FIELD(MSR, EE, MSR_EE, 1)
FIELD(MSR, PR, MSR_PR, 1)
@@ -478,7 +479,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#define msr_cm ((env->msr >> MSR_CM) & 1)
#define msr_gs ((env->msr >> MSR_GS) & 1)
#define msr_pow ((env->msr >> MSR_POW) & 1)
-#define msr_ce ((env->msr >> MSR_CE) & 1)
#define msr_fp ((env->msr >> MSR_FP) & 1)
#define msr_me ((env->msr >> MSR_ME) & 1)
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 4c206ba209..ca80c1ed63 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1749,7 +1749,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
return;
}
}
- if (msr_ce != 0) {
+ if (FIELD_EX64(env->msr, MSR, CE)) {
/* External critical interrupt */
if (env->pending_interrupts & (1 << PPC_INTERRUPT_CEXT)) {
powerpc_excp(cpu, POWERPC_EXCP_CRITICAL);
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 09/21] target/ppc: Remove msr_pow macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (7 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 08/21] target/ppc: Remove msr_ce macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 10/21] target/ppc: Remove msr_me macro Víctor Colombo
` (12 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_pow macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 2 +-
target/ppc/excp_helper.c | 12 ++++++------
target/ppc/helper_regs.c | 2 +-
3 files changed, 8 insertions(+), 8 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 65cb457e6f..f283292863 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -354,6 +354,7 @@ typedef enum {
#define MSR_RI 1 /* Recoverable interrupt 1 */
#define MSR_LE 0 /* Little-endian mode 1 hflags */
+FIELD(MSR, POW, MSR_POW, 1)
FIELD(MSR, CE, MSR_CE, 1)
FIELD(MSR, ILE, MSR_ILE, 1)
FIELD(MSR, EE, MSR_EE, 1)
@@ -478,7 +479,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#endif
#define msr_cm ((env->msr >> MSR_CM) & 1)
#define msr_gs ((env->msr >> MSR_GS) & 1)
-#define msr_pow ((env->msr >> MSR_POW) & 1)
#define msr_fp ((env->msr >> MSR_FP) & 1)
#define msr_me ((env->msr >> MSR_ME) & 1)
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index ca80c1ed63..ee63641dd0 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -661,7 +661,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_ITLB: /* Instruction TLB error */
break;
case POWERPC_EXCP_RESET: /* System reset exception */
- if (msr_pow) {
+ if (FIELD_EX64(env->msr, MSR, POW)) {
cpu_abort(cs, "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
@@ -853,7 +853,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_DECR: /* Decrementer exception */
break;
case POWERPC_EXCP_RESET: /* System reset exception */
- if (msr_pow) {
+ if (FIELD_EX64(env->msr, MSR, POW)) {
cpu_abort(cs, "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
@@ -1038,7 +1038,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_DECR: /* Decrementer exception */
break;
case POWERPC_EXCP_RESET: /* System reset exception */
- if (msr_pow) {
+ if (FIELD_EX64(env->msr, MSR, POW)) {
cpu_abort(cs, "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
@@ -1248,7 +1248,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
env->spr[SPR_BOOKE_ESR] = ESR_SPV;
break;
case POWERPC_EXCP_RESET: /* System reset exception */
- if (msr_pow) {
+ if (FIELD_EX64(env->msr, MSR, POW)) {
cpu_abort(cs, "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
@@ -1507,7 +1507,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
break;
case POWERPC_EXCP_RESET: /* System reset exception */
/* A power-saving exception sets ME, otherwise it is unchanged */
- if (msr_pow) {
+ if (FIELD_EX64(env->msr, MSR, POW)) {
/* indicate that we resumed from power save mode */
msr |= 0x10000;
new_msr |= ((target_ulong)1 << MSR_ME);
@@ -1519,7 +1519,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
*/
new_msr |= (target_ulong)MSR_HVB;
} else {
- if (msr_pow) {
+ if (FIELD_EX64(env->msr, MSR, POW)) {
cpu_abort(cs, "Trying to deliver power-saving system reset "
"exception %d with no HV support\n", excp);
}
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 9a691d6833..940f0207a0 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -261,7 +261,7 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
env->msr = value;
hreg_compute_hflags(env);
#if !defined(CONFIG_USER_ONLY)
- if (unlikely(msr_pow == 1)) {
+ if (unlikely(FIELD_EX64(env->msr, MSR, POW))) {
if (!env->pending_interrupts && (*env->check_pow)(env)) {
cs->halted = 1;
excp = EXCP_HALTED;
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 10/21] target/ppc: Remove msr_me macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (8 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 09/21] target/ppc: Remove msr_pow macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 11/21] target/ppc: Remove msr_gs macro Víctor Colombo
` (11 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_me macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 2 +-
target/ppc/excp_helper.c | 12 ++++++------
2 files changed, 7 insertions(+), 7 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f283292863..059a00ed65 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -359,6 +359,7 @@ FIELD(MSR, CE, MSR_CE, 1)
FIELD(MSR, ILE, MSR_ILE, 1)
FIELD(MSR, EE, MSR_EE, 1)
FIELD(MSR, PR, MSR_PR, 1)
+FIELD(MSR, ME, MSR_ME, 1)
FIELD(MSR, DS, MSR_DS, 1)
FIELD(MSR, LE, MSR_LE, 1)
@@ -480,7 +481,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#define msr_cm ((env->msr >> MSR_CM) & 1)
#define msr_gs ((env->msr >> MSR_GS) & 1)
#define msr_fp ((env->msr >> MSR_FP) & 1)
-#define msr_me ((env->msr >> MSR_ME) & 1)
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
#define msr_ep ((env->msr >> MSR_EP) & 1)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index ee63641dd0..e254ae806c 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -444,7 +444,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
srr1 = SPR_40x_SRR3;
break;
case POWERPC_EXCP_MCHECK: /* Machine check exception */
- if (msr_me == 0) {
+ if (!FIELD_EX64(env->msr, MSR, ME)) {
/*
* Machine check exception is not enabled. Enter
* checkstop state.
@@ -575,7 +575,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_CRITICAL: /* Critical input */
break;
case POWERPC_EXCP_MCHECK: /* Machine check exception */
- if (msr_me == 0) {
+ if (!FIELD_EX64(env->msr, MSR, ME)) {
/*
* Machine check exception is not enabled. Enter
* checkstop state.
@@ -748,7 +748,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
switch (excp) {
case POWERPC_EXCP_MCHECK: /* Machine check exception */
- if (msr_me == 0) {
+ if (!FIELD_EX64(env->msr, MSR, ME)) {
/*
* Machine check exception is not enabled. Enter
* checkstop state.
@@ -933,7 +933,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
switch (excp) {
case POWERPC_EXCP_MCHECK: /* Machine check exception */
- if (msr_me == 0) {
+ if (!FIELD_EX64(env->msr, MSR, ME)) {
/*
* Machine check exception is not enabled. Enter
* checkstop state.
@@ -1128,7 +1128,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
srr1 = SPR_BOOKE_CSRR1;
break;
case POWERPC_EXCP_MCHECK: /* Machine check exception */
- if (msr_me == 0) {
+ if (!FIELD_EX64(env->msr, MSR, ME)) {
/*
* Machine check exception is not enabled. Enter
* checkstop state.
@@ -1366,7 +1366,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
switch (excp) {
case POWERPC_EXCP_MCHECK: /* Machine check exception */
- if (msr_me == 0) {
+ if (!FIELD_EX64(env->msr, MSR, ME)) {
/*
* Machine check exception is not enabled. Enter
* checkstop state.
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 11/21] target/ppc: Remove msr_gs macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (9 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 10/21] target/ppc: Remove msr_me macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-04 2:03 ` Richard Henderson
2022-05-03 20:24 ` [PATCH v3 12/21] target/ppc: Remove msr_fp macro Víctor Colombo
` (10 subsequent siblings)
21 siblings, 1 reply; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_gs macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
v3: Fix
!(value & env->msr & R_MSR_GS_MASK) -> (value ^ env->msr) & R_MSR_GS_MASK
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/cpu.h | 2 +-
target/ppc/helper_regs.c | 2 +-
target/ppc/mmu_helper.c | 4 ++--
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 059a00ed65..4b69cd666d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -354,6 +354,7 @@ typedef enum {
#define MSR_RI 1 /* Recoverable interrupt 1 */
#define MSR_LE 0 /* Little-endian mode 1 hflags */
+FIELD(MSR, GS, MSR_GS, 1)
FIELD(MSR, POW, MSR_POW, 1)
FIELD(MSR, CE, MSR_CE, 1)
FIELD(MSR, ILE, MSR_ILE, 1)
@@ -479,7 +480,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#define msr_hv (0)
#endif
#define msr_cm ((env->msr >> MSR_CM) & 1)
-#define msr_gs ((env->msr >> MSR_GS) & 1)
#define msr_fp ((env->msr >> MSR_FP) & 1)
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 940f0207a0..d75c80482e 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -233,7 +233,7 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
}
if ((env->mmu_model == POWERPC_MMU_BOOKE ||
env->mmu_model == POWERPC_MMU_BOOKE206) &&
- ((value >> MSR_GS) & 1) != msr_gs) {
+ ((value ^ env->msr) & R_MSR_GS_MASK)) {
cpu_interrupt_exittb(cs);
}
if (unlikely((env->flags & POWERPC_FLAG_TGPR) &&
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 142a717255..5bb5c71038 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -935,7 +935,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
}
if (((env->spr[SPR_BOOKE_MAS0] & MAS0_ATSEL) == MAS0_ATSEL_LRAT) &&
- !msr_gs) {
+ !FIELD_EX64(env->msr, MSR, GS)) {
/* XXX we don't support direct LRAT setting yet */
fprintf(stderr, "cpu: don't support LRAT setting yet\n");
return;
@@ -962,7 +962,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
POWERPC_EXCP_INVAL_INVAL, GETPC());
}
- if (msr_gs) {
+ if (FIELD_EX64(env->msr, MSR, GS)) {
cpu_abort(env_cpu(env), "missing HV implementation\n");
}
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 12/21] target/ppc: Remove msr_fp macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (10 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 11/21] target/ppc: Remove msr_gs macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 13/21] target/ppc: Remove msr_cm macro Víctor Colombo
` (9 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_fp macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 2 +-
target/ppc/excp_helper.c | 18 ++++++++++++------
2 files changed, 13 insertions(+), 7 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 4b69cd666d..294c61c9dc 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -360,6 +360,7 @@ FIELD(MSR, CE, MSR_CE, 1)
FIELD(MSR, ILE, MSR_ILE, 1)
FIELD(MSR, EE, MSR_EE, 1)
FIELD(MSR, PR, MSR_PR, 1)
+FIELD(MSR, FP, MSR_FP, 1)
FIELD(MSR, ME, MSR_ME, 1)
FIELD(MSR, DS, MSR_DS, 1)
FIELD(MSR, LE, MSR_LE, 1)
@@ -480,7 +481,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#define msr_hv (0)
#endif
#define msr_cm ((env->msr >> MSR_CM) & 1)
-#define msr_fp ((env->msr >> MSR_FP) & 1)
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
#define msr_ep ((env->msr >> MSR_EP) & 1)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index e254ae806c..30baad0489 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -478,7 +478,8 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+ if ((msr_fe0 == 0 && msr_fe1 == 0) ||
+ !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -615,7 +616,8 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+ if ((msr_fe0 == 0 && msr_fe1 == 0) ||
+ !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -788,7 +790,8 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+ if ((msr_fe0 == 0 && msr_fe1 == 0) ||
+ !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -973,7 +976,8 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+ if ((msr_fe0 == 0 && msr_fe1 == 0) ||
+ !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -1171,7 +1175,8 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+ if ((msr_fe0 == 0 && msr_fe1 == 0) ||
+ !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -1434,7 +1439,8 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) || msr_fp == 0) {
+ if ((msr_fe0 == 0 && msr_fe1 == 0) ||
+ !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 13/21] target/ppc: Remove msr_cm macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (11 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 12/21] target/ppc: Remove msr_fp macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 14/21] target/ppc: Remove msr_ir macro Víctor Colombo
` (8 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_cm macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
v3: fix this patch's name (msr_ce --> msr_cm)
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/cpu.h | 2 +-
target/ppc/mmu_common.c | 2 +-
target/ppc/mmu_helper.c | 2 +-
3 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 294c61c9dc..8e652691cf 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -354,6 +354,7 @@ typedef enum {
#define MSR_RI 1 /* Recoverable interrupt 1 */
#define MSR_LE 0 /* Little-endian mode 1 hflags */
+FIELD(MSR, CM, MSR_CM, 1)
FIELD(MSR, GS, MSR_GS, 1)
FIELD(MSR, POW, MSR_POW, 1)
FIELD(MSR, CE, MSR_CE, 1)
@@ -480,7 +481,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#else
#define msr_hv (0)
#endif
-#define msr_cm ((env->msr >> MSR_CM) & 1)
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
#define msr_ep ((env->msr >> MSR_EP) & 1)
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 7e77b9b84a..031bb4493b 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -692,7 +692,7 @@ int ppcmas_tlb_check(CPUPPCState *env, ppcmas_tlb_t *tlb,
hwaddr mask;
uint32_t tlb_pid;
- if (!msr_cm) {
+ if (!FIELD_EX64(env->msr, MSR, CM)) {
/* In 32bit mode we can only address 32bit EAs */
address = (uint32_t)address;
}
diff --git a/target/ppc/mmu_helper.c b/target/ppc/mmu_helper.c
index 5bb5c71038..15239dc95b 100644
--- a/target/ppc/mmu_helper.c
+++ b/target/ppc/mmu_helper.c
@@ -1003,7 +1003,7 @@ void helper_booke206_tlbwe(CPUPPCState *env)
/* Add a mask for page attributes */
mask |= MAS2_ACM | MAS2_VLE | MAS2_W | MAS2_I | MAS2_M | MAS2_G | MAS2_E;
- if (!msr_cm) {
+ if (!FIELD_EX64(env->msr, MSR, CM)) {
/*
* Executing a tlbwe instruction in 32-bit mode will set bits
* 0:31 of the TLB EPN field to zero.
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 14/21] target/ppc: Remove msr_ir macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (12 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 13/21] target/ppc: Remove msr_cm macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-04 2:05 ` Richard Henderson
2022-05-03 20:24 ` [PATCH v3 15/21] target/ppc: Remove msr_dr macro Víctor Colombo
` (7 subsequent siblings)
21 siblings, 1 reply; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_ir macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
v3: Fix the difference check to use a xor
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/cpu.h | 2 +-
target/ppc/helper_regs.c | 2 +-
target/ppc/mmu_common.c | 11 ++++++-----
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 8e652691cf..18d41e7af4 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -363,6 +363,7 @@ FIELD(MSR, EE, MSR_EE, 1)
FIELD(MSR, PR, MSR_PR, 1)
FIELD(MSR, FP, MSR_FP, 1)
FIELD(MSR, ME, MSR_ME, 1)
+FIELD(MSR, IR, MSR_IR, 1)
FIELD(MSR, DS, MSR_DS, 1)
FIELD(MSR, LE, MSR_LE, 1)
@@ -484,7 +485,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
#define msr_ep ((env->msr >> MSR_EP) & 1)
-#define msr_ir ((env->msr >> MSR_IR) & 1)
#define msr_dr ((env->msr >> MSR_DR) & 1)
#define msr_ts ((env->msr >> MSR_TS1) & 3)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index d75c80482e..6cd7b5ece3 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -227,7 +227,7 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
value &= ~MSR_HVB;
value |= env->msr & MSR_HVB;
}
- if (((value >> MSR_IR) & 1) != msr_ir ||
+ if (((value ^ env->msr) & R_MSR_IR_MASK) ||
((value >> MSR_DR) & 1) != msr_dr) {
cpu_interrupt_exittb(cs);
}
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 031bb4493b..30deca0425 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -388,7 +388,7 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
" nip=" TARGET_FMT_lx " lr=" TARGET_FMT_lx
" ir=%d dr=%d pr=%d %d t=%d\n",
eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr,
- (int)msr_ir, (int)msr_dr, pr ? 1 : 0,
+ (int)FIELD_EX64(env->msr, MSR, IR), (int)msr_dr, pr ? 1 : 0,
access_type == MMU_DATA_STORE, type);
pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
hash = vsid ^ pgidx;
@@ -626,7 +626,8 @@ found_tlb:
}
/* Check the address space */
- if ((access_type == MMU_INST_FETCH ? msr_ir : msr_dr) != (tlb->attr & 1)) {
+ if ((access_type == MMU_INST_FETCH ?
+ FIELD_EX64(env->msr, MSR, IR) : msr_dr) != (tlb->attr & 1)) {
qemu_log_mask(CPU_LOG_MMU, "%s: AS doesn't match\n", __func__);
return -1;
}
@@ -839,7 +840,7 @@ found_tlb:
if (access_type == MMU_INST_FETCH) {
/* There is no way to fetch code using epid load */
assert(!use_epid);
- as = msr_ir;
+ as = FIELD_EX64(env->msr, MSR, IR);
}
if (as != ((tlb->mas1 & MAS1_TS) >> MAS1_TS_SHIFT)) {
@@ -1169,7 +1170,7 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
int mmu_idx)
{
int ret = -1;
- bool real_mode = (type == ACCESS_CODE && msr_ir == 0)
+ bool real_mode = (type == ACCESS_CODE && !FIELD_EX64(env->msr, MSR, IR))
|| (type != ACCESS_CODE && msr_dr == 0);
switch (env->mmu_model) {
@@ -1231,7 +1232,7 @@ static void booke206_update_mas_tlb_miss(CPUPPCState *env, target_ulong address,
bool use_epid = mmubooke206_get_as(env, mmu_idx, &epid, &as, &pr);
if (access_type == MMU_INST_FETCH) {
- as = msr_ir;
+ as = FIELD_EX64(env->msr, MSR, IR);
}
env->spr[SPR_BOOKE_MAS0] = env->spr[SPR_BOOKE_MAS4] & MAS4_TLBSELD_MASK;
env->spr[SPR_BOOKE_MAS1] = env->spr[SPR_BOOKE_MAS4] & MAS4_TSIZED_MASK;
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 15/21] target/ppc: Remove msr_dr macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (13 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 14/21] target/ppc: Remove msr_ir macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-04 2:07 ` Richard Henderson
2022-05-03 20:24 ` [PATCH v3 16/21] target/ppc: Remove msr_ep macro Víctor Colombo
` (6 subsequent siblings)
21 siblings, 1 reply; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_dr macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
v3: Fix the difference check to use a xor
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/cpu.h | 2 +-
target/ppc/helper_regs.c | 3 +--
target/ppc/mmu_common.c | 10 ++++++----
3 files changed, 8 insertions(+), 7 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 18d41e7af4..ff52eef304 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -364,6 +364,7 @@ FIELD(MSR, PR, MSR_PR, 1)
FIELD(MSR, FP, MSR_FP, 1)
FIELD(MSR, ME, MSR_ME, 1)
FIELD(MSR, IR, MSR_IR, 1)
+FIELD(MSR, DR, MSR_DR, 1)
FIELD(MSR, DS, MSR_DS, 1)
FIELD(MSR, LE, MSR_LE, 1)
@@ -485,7 +486,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
#define msr_ep ((env->msr >> MSR_EP) & 1)
-#define msr_dr ((env->msr >> MSR_DR) & 1)
#define msr_ts ((env->msr >> MSR_TS1) & 3)
#define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 6cd7b5ece3..555ea73dc1 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -227,8 +227,7 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
value &= ~MSR_HVB;
value |= env->msr & MSR_HVB;
}
- if (((value ^ env->msr) & R_MSR_IR_MASK) ||
- ((value >> MSR_DR) & 1) != msr_dr) {
+ if ((value ^ env->msr) & (R_MSR_IR_MASK | R_MSR_DR_MASK)) {
cpu_interrupt_exittb(cs);
}
if ((env->mmu_model == POWERPC_MMU_BOOKE ||
diff --git a/target/ppc/mmu_common.c b/target/ppc/mmu_common.c
index 30deca0425..89107a6af2 100644
--- a/target/ppc/mmu_common.c
+++ b/target/ppc/mmu_common.c
@@ -388,7 +388,8 @@ static int get_segment_6xx_tlb(CPUPPCState *env, mmu_ctx_t *ctx,
" nip=" TARGET_FMT_lx " lr=" TARGET_FMT_lx
" ir=%d dr=%d pr=%d %d t=%d\n",
eaddr, (int)(eaddr >> 28), sr, env->nip, env->lr,
- (int)FIELD_EX64(env->msr, MSR, IR), (int)msr_dr, pr ? 1 : 0,
+ (int)FIELD_EX64(env->msr, MSR, IR),
+ (int)FIELD_EX64(env->msr, MSR, DR), pr ? 1 : 0,
access_type == MMU_DATA_STORE, type);
pgidx = (eaddr & ~SEGMENT_MASK_256M) >> target_page_bits;
hash = vsid ^ pgidx;
@@ -627,7 +628,8 @@ found_tlb:
/* Check the address space */
if ((access_type == MMU_INST_FETCH ?
- FIELD_EX64(env->msr, MSR, IR) : msr_dr) != (tlb->attr & 1)) {
+ FIELD_EX64(env->msr, MSR, IR) :
+ FIELD_EX64(env->msr, MSR, DR)) != (tlb->attr & 1)) {
qemu_log_mask(CPU_LOG_MMU, "%s: AS doesn't match\n", __func__);
return -1;
}
@@ -1170,8 +1172,8 @@ int get_physical_address_wtlb(CPUPPCState *env, mmu_ctx_t *ctx,
int mmu_idx)
{
int ret = -1;
- bool real_mode = (type == ACCESS_CODE && !FIELD_EX64(env->msr, MSR, IR))
- || (type != ACCESS_CODE && msr_dr == 0);
+ bool real_mode = (type == ACCESS_CODE && !FIELD_EX64(env->msr, MSR, IR)) ||
+ (type != ACCESS_CODE && !FIELD_EX64(env->msr, MSR, DR));
switch (env->mmu_model) {
case POWERPC_MMU_SOFT_6xx:
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 16/21] target/ppc: Remove msr_ep macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (14 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 15/21] target/ppc: Remove msr_dr macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-04 2:08 ` Richard Henderson
2022-05-03 20:24 ` [PATCH v3 17/21] target/ppc: Remove msr_fe0 and msr_fe1 macros Víctor Colombo
` (5 subsequent siblings)
21 siblings, 1 reply; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_ep macro hides the usage of env->msr, which is a bad behavior
Substitute it with FIELD_EX64 calls that explicitly use env->msr
as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
v3: Fix the difference check to use a xor
fix incorrect "FIELD_EX64(env->msr, ..." -> "FIELD_EX64(value, ..."
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/cpu.h | 2 +-
target/ppc/helper_regs.c | 4 ++--
2 files changed, 3 insertions(+), 3 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index ff52eef304..9683e6a359 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -363,6 +363,7 @@ FIELD(MSR, EE, MSR_EE, 1)
FIELD(MSR, PR, MSR_PR, 1)
FIELD(MSR, FP, MSR_FP, 1)
FIELD(MSR, ME, MSR_ME, 1)
+FIELD(MSR, EP, MSR_EP, 1)
FIELD(MSR, IR, MSR_IR, 1)
FIELD(MSR, DR, MSR_DR, 1)
FIELD(MSR, DS, MSR_DS, 1)
@@ -485,7 +486,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#endif
#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
-#define msr_ep ((env->msr >> MSR_EP) & 1)
#define msr_ts ((env->msr >> MSR_TS1) & 3)
#define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/helper_regs.c b/target/ppc/helper_regs.c
index 555ea73dc1..27f0c0968c 100644
--- a/target/ppc/helper_regs.c
+++ b/target/ppc/helper_regs.c
@@ -240,8 +240,8 @@ int hreg_store_msr(CPUPPCState *env, target_ulong value, int alter_hv)
/* Swap temporary saved registers with GPRs */
hreg_swap_gpr_tgpr(env);
}
- if (unlikely((value >> MSR_EP) & 1) != msr_ep) {
- env->excp_prefix = ((value >> MSR_EP) & 1) * 0xFFF00000;
+ if (unlikely((value ^ env->msr) & R_MSR_EP_MASK)) {
+ env->excp_prefix = FIELD_EX64(value, MSR, EP) * 0xFFF00000;
}
/*
* If PR=1 then EE, IR and DR must be 1
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 17/21] target/ppc: Remove msr_fe0 and msr_fe1 macros
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (15 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 16/21] target/ppc: Remove msr_ep macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-04 2:08 ` Richard Henderson
2022-05-03 20:24 ` [PATCH v3 18/21] target/ppc: Remove msr_ts macro Víctor Colombo
` (4 subsequent siblings)
21 siblings, 1 reply; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_fe0 and msr_fe1 macros hide the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
v3: Added a combined macro for FE0 and FE1. Use it to simplify
conditionals. Removed Richard's R-b because of this change.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/cpu.h | 11 +++++++++--
target/ppc/excp_helper.c | 18 ++++++------------
2 files changed, 15 insertions(+), 14 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 9683e6a359..cc7ca1d47d 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -363,12 +363,21 @@ FIELD(MSR, EE, MSR_EE, 1)
FIELD(MSR, PR, MSR_PR, 1)
FIELD(MSR, FP, MSR_FP, 1)
FIELD(MSR, ME, MSR_ME, 1)
+FIELD(MSR, FE0, MSR_FE0, 1)
+FIELD(MSR, FE1, MSR_FE1, 1)
FIELD(MSR, EP, MSR_EP, 1)
FIELD(MSR, IR, MSR_IR, 1)
FIELD(MSR, DR, MSR_DR, 1)
FIELD(MSR, DS, MSR_DS, 1)
FIELD(MSR, LE, MSR_LE, 1)
+/*
+ * FE0 and FE1 bits are not side-by-side
+ * so we can't combine them using FIELD()
+ */
+#define FIELD_EX64_FE(msr) \
+ ((FIELD_EX64(msr, MSR, FE0) << 1) | FIELD_EX64(msr, MSR, FE1))
+
/* PMU bits */
#define MMCR0_FC PPC_BIT(32) /* Freeze Counters */
#define MMCR0_PMAO PPC_BIT(56) /* Perf Monitor Alert Ocurred */
@@ -484,8 +493,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#else
#define msr_hv (0)
#endif
-#define msr_fe0 ((env->msr >> MSR_FE0) & 1)
-#define msr_fe1 ((env->msr >> MSR_FE1) & 1)
#define msr_ts ((env->msr >> MSR_TS1) & 3)
#define DBCR0_ICMP (1 << 27)
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index 30baad0489..aa201c63c6 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -478,8 +478,7 @@ static void powerpc_excp_40x(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
- !FIELD_EX64(env->msr, MSR, FP)) {
+ if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -616,8 +615,7 @@ static void powerpc_excp_6xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
- !FIELD_EX64(env->msr, MSR, FP)) {
+ if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -790,8 +788,7 @@ static void powerpc_excp_7xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
- !FIELD_EX64(env->msr, MSR, FP)) {
+ if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -976,8 +973,7 @@ static void powerpc_excp_74xx(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
- !FIELD_EX64(env->msr, MSR, FP)) {
+ if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -1175,8 +1171,7 @@ static void powerpc_excp_booke(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
- !FIELD_EX64(env->msr, MSR, FP)) {
+ if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
@@ -1439,8 +1434,7 @@ static void powerpc_excp_books(PowerPCCPU *cpu, int excp)
case POWERPC_EXCP_PROGRAM: /* Program exception */
switch (env->error_code & ~0xF) {
case POWERPC_EXCP_FP:
- if ((msr_fe0 == 0 && msr_fe1 == 0) ||
- !FIELD_EX64(env->msr, MSR, FP)) {
+ if (!FIELD_EX64_FE(env->msr) || !FIELD_EX64(env->msr, MSR, FP)) {
trace_ppc_excp_fp_ignore();
powerpc_reset_excp_state(cpu);
return;
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 18/21] target/ppc: Remove msr_ts macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (16 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 17/21] target/ppc: Remove msr_fe0 and msr_fe1 macros Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 19/21] target/ppc: Remove msr_hv macro Víctor Colombo
` (3 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_ts macro hides the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 2 +-
target/ppc/kvm.c | 4 ++--
target/ppc/machine.c | 2 +-
3 files changed, 4 insertions(+), 4 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index cc7ca1d47d..daf1204a6a 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -354,6 +354,7 @@ typedef enum {
#define MSR_RI 1 /* Recoverable interrupt 1 */
#define MSR_LE 0 /* Little-endian mode 1 hflags */
+FIELD(MSR, TS, MSR_TS0, 2)
FIELD(MSR, CM, MSR_CM, 1)
FIELD(MSR, GS, MSR_GS, 1)
FIELD(MSR, POW, MSR_POW, 1)
@@ -493,7 +494,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#else
#define msr_hv (0)
#endif
-#define msr_ts ((env->msr >> MSR_TS1) & 3)
#define DBCR0_ICMP (1 << 27)
#define DBCR0_BRT (1 << 26)
diff --git a/target/ppc/kvm.c b/target/ppc/kvm.c
index 8276326de9..59db1b9227 100644
--- a/target/ppc/kvm.c
+++ b/target/ppc/kvm.c
@@ -973,7 +973,7 @@ int kvm_arch_put_registers(CPUState *cs, int level)
}
#ifdef TARGET_PPC64
- if (msr_ts) {
+ if (FIELD_EX64(env->msr, MSR, TS)) {
for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
kvm_set_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
}
@@ -1281,7 +1281,7 @@ int kvm_arch_get_registers(CPUState *cs)
}
#ifdef TARGET_PPC64
- if (msr_ts) {
+ if (FIELD_EX64(env->msr, MSR, TS)) {
for (i = 0; i < ARRAY_SIZE(env->tm_gpr); i++) {
kvm_get_one_reg(cs, KVM_REG_PPC_TM_GPR(i), &env->tm_gpr[i]);
}
diff --git a/target/ppc/machine.c b/target/ppc/machine.c
index e673944597..7104a5c67e 100644
--- a/target/ppc/machine.c
+++ b/target/ppc/machine.c
@@ -417,7 +417,7 @@ static bool tm_needed(void *opaque)
{
PowerPCCPU *cpu = opaque;
CPUPPCState *env = &cpu->env;
- return msr_ts;
+ return FIELD_EX64(env->msr, MSR, TS);
}
static const VMStateDescription vmstate_tm = {
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 19/21] target/ppc: Remove msr_hv macro
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (17 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 18/21] target/ppc: Remove msr_ts macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 20/21] target/ppc: Add unused msr bits FIELDs Víctor Colombo
` (2 subsequent siblings)
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
msr_hv macro hides the usage of env->msr, which is a bad
behavior. Substitute it with FIELD_EX64 calls that explicitly use
env->msr as a parameter.
Suggested-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 12 ++++++------
target/ppc/cpu_init.c | 6 ++++--
target/ppc/excp_helper.c | 8 ++++----
target/ppc/mem_helper.c | 4 ++--
target/ppc/misc_helper.c | 2 +-
target/ppc/mmu-radix64.c | 6 +++---
6 files changed, 20 insertions(+), 18 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index daf1204a6a..f16a56fc55 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -354,6 +354,12 @@ typedef enum {
#define MSR_RI 1 /* Recoverable interrupt 1 */
#define MSR_LE 0 /* Little-endian mode 1 hflags */
+#if defined(TARGET_PPC64)
+FIELD(MSR, HV, MSR_HV, 1)
+#define FIELD_EX64_HV(storage) FIELD_EX64(storage, MSR, HV)
+#else
+#define FIELD_EX64_HV(storage) 0
+#endif
FIELD(MSR, TS, MSR_TS0, 2)
FIELD(MSR, CM, MSR_CM, 1)
FIELD(MSR, GS, MSR_GS, 1)
@@ -489,12 +495,6 @@ FIELD(MSR, LE, MSR_LE, 1)
#define HFSCR_MSGP PPC_BIT(53) /* Privileged Message Send Facilities */
#define HFSCR_IC_MSGP 0xA
-#if defined(TARGET_PPC64)
-#define msr_hv ((env->msr >> MSR_HV) & 1)
-#else
-#define msr_hv (0)
-#endif
-
#define DBCR0_ICMP (1 << 27)
#define DBCR0_BRT (1 << 26)
#define DBSR_ICMP (1 << 27)
diff --git a/target/ppc/cpu_init.c b/target/ppc/cpu_init.c
index 10e7c41bc9..d4c7813de5 100644
--- a/target/ppc/cpu_init.c
+++ b/target/ppc/cpu_init.c
@@ -6305,7 +6305,8 @@ static bool cpu_has_work_POWER9(CPUState *cs)
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
(env->spr[SPR_LPCR] & LPCR_EEE)) {
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
- if (!heic || !msr_hv || FIELD_EX64(env->msr, MSR, PR)) {
+ if (!heic || !FIELD_EX64_HV(env->msr) ||
+ FIELD_EX64(env->msr, MSR, PR)) {
return true;
}
}
@@ -6520,7 +6521,8 @@ static bool cpu_has_work_POWER10(CPUState *cs)
if ((env->pending_interrupts & (1u << PPC_INTERRUPT_EXT)) &&
(env->spr[SPR_LPCR] & LPCR_EEE)) {
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
- if (!heic || !msr_hv || FIELD_EX64(env->msr, MSR, PR)) {
+ if (!heic || !FIELD_EX64_HV(env->msr) ||
+ FIELD_EX64(env->msr, MSR, PR)) {
return true;
}
}
diff --git a/target/ppc/excp_helper.c b/target/ppc/excp_helper.c
index aa201c63c6..cb752b184a 100644
--- a/target/ppc/excp_helper.c
+++ b/target/ppc/excp_helper.c
@@ -1715,7 +1715,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
if (env->pending_interrupts & (1 << PPC_INTERRUPT_HDECR)) {
/* LPCR will be clear when not supported so this will work */
bool hdice = !!(env->spr[SPR_LPCR] & LPCR_HDICE);
- if ((async_deliver || msr_hv == 0) && hdice) {
+ if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hdice) {
/* HDEC clears on delivery */
env->pending_interrupts &= ~(1 << PPC_INTERRUPT_HDECR);
powerpc_excp(cpu, POWERPC_EXCP_HDECR);
@@ -1727,7 +1727,7 @@ static void ppc_hw_interrupt(CPUPPCState *env)
if (env->pending_interrupts & (1 << PPC_INTERRUPT_HVIRT)) {
/* LPCR will be clear when not supported so this will work */
bool hvice = !!(env->spr[SPR_LPCR] & LPCR_HVICE);
- if ((async_deliver || msr_hv == 0) && hvice) {
+ if ((async_deliver || !FIELD_EX64_HV(env->msr)) && hvice) {
powerpc_excp(cpu, POWERPC_EXCP_HVIRT);
return;
}
@@ -1738,9 +1738,9 @@ static void ppc_hw_interrupt(CPUPPCState *env)
bool lpes0 = !!(env->spr[SPR_LPCR] & LPCR_LPES0);
bool heic = !!(env->spr[SPR_LPCR] & LPCR_HEIC);
/* HEIC blocks delivery to the hypervisor */
- if ((async_deliver && !(heic && msr_hv &&
+ if ((async_deliver && !(heic && FIELD_EX64_HV(env->msr) &&
!FIELD_EX64(env->msr, MSR, PR))) ||
- (env->has_hv_mode && msr_hv == 0 && !lpes0)) {
+ (env->has_hv_mode && !FIELD_EX64_HV(env->msr) && !lpes0)) {
if (books_vhyp_promotes_external_to_hvirt(cpu)) {
powerpc_excp(cpu, POWERPC_EXCP_HVIRT);
} else {
diff --git a/target/ppc/mem_helper.c b/target/ppc/mem_helper.c
index 9af135e88e..d1163f316c 100644
--- a/target/ppc/mem_helper.c
+++ b/target/ppc/mem_helper.c
@@ -612,11 +612,11 @@ void helper_tbegin(CPUPPCState *env)
env->spr[SPR_TEXASR] =
(1ULL << TEXASR_FAILURE_PERSISTENT) |
(1ULL << TEXASR_NESTING_OVERFLOW) |
- (msr_hv << TEXASR_PRIVILEGE_HV) |
+ (FIELD_EX64_HV(env->msr) << TEXASR_PRIVILEGE_HV) |
(FIELD_EX64(env->msr, MSR, PR) << TEXASR_PRIVILEGE_PR) |
(1ULL << TEXASR_FAILURE_SUMMARY) |
(1ULL << TEXASR_TFIAR_EXACT);
- env->spr[SPR_TFIAR] = env->nip | (msr_hv << 1) |
+ env->spr[SPR_TFIAR] = env->nip | (FIELD_EX64_HV(env->msr) << 1) |
FIELD_EX64(env->msr, MSR, PR);
env->spr[SPR_TFHAR] = env->nip + 4;
env->crf[0] = 0xB; /* 0b1010 = transaction failure */
diff --git a/target/ppc/misc_helper.c b/target/ppc/misc_helper.c
index 06aa716cab..b0a5e7ce76 100644
--- a/target/ppc/misc_helper.c
+++ b/target/ppc/misc_helper.c
@@ -73,7 +73,7 @@ void helper_hfscr_facility_check(CPUPPCState *env, uint32_t bit,
const char *caller, uint32_t cause)
{
#ifdef TARGET_PPC64
- if ((env->msr_mask & MSR_HVB) && !msr_hv &&
+ if ((env->msr_mask & MSR_HVB) && !FIELD_EX64(env->msr, MSR, HV) &&
!(env->spr[SPR_HFSCR] & (1UL << bit))) {
raise_hv_fu_exception(env, bit, caller, cause, GETPC());
}
diff --git a/target/ppc/mmu-radix64.c b/target/ppc/mmu-radix64.c
index e88f51fd34..21ac958e48 100644
--- a/target/ppc/mmu-radix64.c
+++ b/target/ppc/mmu-radix64.c
@@ -37,7 +37,7 @@ static bool ppc_radix64_get_fully_qualified_addr(const CPUPPCState *env,
return false;
}
- if (msr_hv) { /* MSR[HV] -> Hypervisor/bare metal */
+ if (FIELD_EX64(env->msr, MSR, HV)) { /* MSR[HV] -> Hypervisor/bare metal */
switch (eaddr & R_EADDR_QUADRANT) {
case R_EADDR_QUADRANT0:
*lpid = 0;
@@ -306,7 +306,7 @@ static bool validate_pate(PowerPCCPU *cpu, uint64_t lpid, ppc_v3_pate_t *pate)
if (!(pate->dw0 & PATE0_HR)) {
return false;
}
- if (lpid == 0 && !msr_hv) {
+ if (lpid == 0 && !FIELD_EX64(env->msr, MSR, HV)) {
return false;
}
if ((pate->dw0 & PATE1_R_PRTS) < 5) {
@@ -431,7 +431,7 @@ static int ppc_radix64_process_scoped_xlate(PowerPCCPU *cpu,
*g_page_size = PRTBE_R_GET_RTS(prtbe0);
base_addr = prtbe0 & PRTBE_R_RPDB;
nls = prtbe0 & PRTBE_R_RPDS;
- if (msr_hv || vhyp_flat_addressing(cpu)) {
+ if (FIELD_EX64(env->msr, MSR, HV) || vhyp_flat_addressing(cpu)) {
/*
* Can treat process table addresses as real addresses
*/
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 20/21] target/ppc: Add unused msr bits FIELDs
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (18 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 19/21] target/ppc: Remove msr_hv macro Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 21/21] target/ppc: Change MSR_* to follow POWER ISA numbering convention Víctor Colombo
2022-05-04 20:33 ` [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Daniel Henrique Barboza
21 siblings, 0 replies; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
Add FIELDs macros for msr bits that had an unused msr_* before.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
Acked-by: Richard Henderson <richard.henderson@linaro.org>
---
target/ppc/cpu.h | 26 ++++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index f16a56fc55..1c40c7f0c6 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -354,16 +354,31 @@ typedef enum {
#define MSR_RI 1 /* Recoverable interrupt 1 */
#define MSR_LE 0 /* Little-endian mode 1 hflags */
+FIELD(MSR, SF, MSR_SF, 1)
+FIELD(MSR, TAG, MSR_TAG, 1)
+FIELD(MSR, ISF, MSR_ISF, 1)
#if defined(TARGET_PPC64)
FIELD(MSR, HV, MSR_HV, 1)
#define FIELD_EX64_HV(storage) FIELD_EX64(storage, MSR, HV)
#else
#define FIELD_EX64_HV(storage) 0
#endif
+FIELD(MSR, TS0, MSR_TS0, 1)
+FIELD(MSR, TS1, MSR_TS1, 1)
FIELD(MSR, TS, MSR_TS0, 2)
+FIELD(MSR, TM, MSR_TM, 1)
FIELD(MSR, CM, MSR_CM, 1)
+FIELD(MSR, ICM, MSR_ICM, 1)
FIELD(MSR, GS, MSR_GS, 1)
+FIELD(MSR, UCLE, MSR_UCLE, 1)
+FIELD(MSR, VR, MSR_VR, 1)
+FIELD(MSR, SPE, MSR_SPE, 1)
+FIELD(MSR, VSX, MSR_VSX, 1)
+FIELD(MSR, S, MSR_S, 1)
+FIELD(MSR, KEY, MSR_KEY, 1)
FIELD(MSR, POW, MSR_POW, 1)
+FIELD(MSR, WE, MSR_WE, 1)
+FIELD(MSR, TGPR, MSR_TGPR, 1)
FIELD(MSR, CE, MSR_CE, 1)
FIELD(MSR, ILE, MSR_ILE, 1)
FIELD(MSR, EE, MSR_EE, 1)
@@ -372,10 +387,21 @@ FIELD(MSR, FP, MSR_FP, 1)
FIELD(MSR, ME, MSR_ME, 1)
FIELD(MSR, FE0, MSR_FE0, 1)
FIELD(MSR, FE1, MSR_FE1, 1)
+FIELD(MSR, SE, MSR_SE, 1)
+FIELD(MSR, DWE, MSR_DWE, 1)
+FIELD(MSR, UBLE, MSR_UBLE, 1)
+FIELD(MSR, BE, MSR_BE, 1)
+FIELD(MSR, DE, MSR_DE, 1)
+FIELD(MSR, AL, MSR_AL, 1)
FIELD(MSR, EP, MSR_EP, 1)
FIELD(MSR, IR, MSR_IR, 1)
FIELD(MSR, DR, MSR_DR, 1)
+FIELD(MSR, IS, MSR_IS, 1)
FIELD(MSR, DS, MSR_DS, 1)
+FIELD(MSR, PE, MSR_PE, 1)
+FIELD(MSR, PX, MSR_PX, 1)
+FIELD(MSR, PMM, MSR_PMM, 1)
+FIELD(MSR, RI, MSR_RI, 1)
FIELD(MSR, LE, MSR_LE, 1)
/*
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* [PATCH v3 21/21] target/ppc: Change MSR_* to follow POWER ISA numbering convention
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (19 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 20/21] target/ppc: Add unused msr bits FIELDs Víctor Colombo
@ 2022-05-03 20:24 ` Víctor Colombo
2022-05-04 2:09 ` Richard Henderson
2022-05-04 20:33 ` [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Daniel Henrique Barboza
21 siblings, 1 reply; 29+ messages in thread
From: Víctor Colombo @ 2022-05-03 20:24 UTC (permalink / raw)
To: qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, richard.henderson, balaton,
victor.colombo
Today we have the issue where MSR_* values are the 'inverted order'
bit numbers from what the ISA specifies. e.g. MSR_LE is bit 63 but
is defined as 0 in QEMU.
Add a macro to be used to convert from QEMU order to ISA order.
This solution requires less changes than to use the already defined
PPC_BIT macro, which would turn MSR_* in masks instead of the numbers
itself.
Signed-off-by: Víctor Colombo <victor.colombo@eldorado.org.br>
---
target/ppc/cpu.h | 87 ++++++++++++++++++++++++------------------------
1 file changed, 44 insertions(+), 43 deletions(-)
diff --git a/target/ppc/cpu.h b/target/ppc/cpu.h
index 1c40c7f0c6..953357a02c 100644
--- a/target/ppc/cpu.h
+++ b/target/ppc/cpu.h
@@ -38,6 +38,7 @@
#define PPC_ELF_MACHINE EM_PPC
#endif
+#define PPC_BIT_NR(bit) (63 - (bit))
#define PPC_BIT(bit) (0x8000000000000000ULL >> (bit))
#define PPC_BIT32(bit) (0x80000000 >> (bit))
#define PPC_BIT8(bit) (0x80 >> (bit))
@@ -310,49 +311,49 @@ typedef enum {
/*****************************************************************************/
/* Machine state register bits definition */
-#define MSR_SF 63 /* Sixty-four-bit mode hflags */
-#define MSR_TAG 62 /* Tag-active mode (POWERx ?) */
-#define MSR_ISF 61 /* Sixty-four-bit interrupt mode on 630 */
-#define MSR_HV 60 /* hypervisor state hflags */
-#define MSR_TS0 34 /* Transactional state, 2 bits (Book3s) */
-#define MSR_TS1 33
-#define MSR_TM 32 /* Transactional Memory Available (Book3s) */
-#define MSR_CM 31 /* Computation mode for BookE hflags */
-#define MSR_ICM 30 /* Interrupt computation mode for BookE */
-#define MSR_GS 28 /* guest state for BookE */
-#define MSR_UCLE 26 /* User-mode cache lock enable for BookE */
-#define MSR_VR 25 /* altivec available x hflags */
-#define MSR_SPE 25 /* SPE enable for BookE x hflags */
-#define MSR_VSX 23 /* Vector Scalar Extension (ISA 2.06 and later) x hflags */
-#define MSR_S 22 /* Secure state */
-#define MSR_KEY 19 /* key bit on 603e */
-#define MSR_POW 18 /* Power management */
-#define MSR_WE 18 /* Wait State Enable on 405 */
-#define MSR_TGPR 17 /* TGPR usage on 602/603 x */
-#define MSR_CE 17 /* Critical interrupt enable on embedded PowerPC x */
-#define MSR_ILE 16 /* Interrupt little-endian mode */
-#define MSR_EE 15 /* External interrupt enable */
-#define MSR_PR 14 /* Problem state hflags */
-#define MSR_FP 13 /* Floating point available hflags */
-#define MSR_ME 12 /* Machine check interrupt enable */
-#define MSR_FE0 11 /* Floating point exception mode 0 */
-#define MSR_SE 10 /* Single-step trace enable x hflags */
-#define MSR_DWE 10 /* Debug wait enable on 405 x */
-#define MSR_UBLE 10 /* User BTB lock enable on e500 x */
-#define MSR_BE 9 /* Branch trace enable x hflags */
-#define MSR_DE 9 /* Debug interrupts enable on embedded PowerPC x */
-#define MSR_FE1 8 /* Floating point exception mode 1 */
-#define MSR_AL 7 /* AL bit on POWER */
-#define MSR_EP 6 /* Exception prefix on 601 */
-#define MSR_IR 5 /* Instruction relocate */
-#define MSR_DR 4 /* Data relocate */
-#define MSR_IS 5 /* Instruction address space (BookE) */
-#define MSR_DS 4 /* Data address space (BookE) */
-#define MSR_PE 3 /* Protection enable on 403 */
-#define MSR_PX 2 /* Protection exclusive on 403 x */
-#define MSR_PMM 2 /* Performance monitor mark on POWER x */
-#define MSR_RI 1 /* Recoverable interrupt 1 */
-#define MSR_LE 0 /* Little-endian mode 1 hflags */
+#define MSR_SF PPC_BIT_NR(0) /* Sixty-four-bit mode hflags */
+#define MSR_TAG PPC_BIT_NR(1) /* Tag-active mode (POWERx ?) */
+#define MSR_ISF PPC_BIT_NR(2) /* Sixty-four-bit interrupt mode on 630 */
+#define MSR_HV PPC_BIT_NR(3) /* hypervisor state hflags */
+#define MSR_TS0 PPC_BIT_NR(29) /* Transactional state, 2 bits (Book3s) */
+#define MSR_TS1 PPC_BIT_NR(30)
+#define MSR_TM PPC_BIT_NR(31) /* Transactional Memory Available (Book3s) */
+#define MSR_CM PPC_BIT_NR(32) /* Computation mode for BookE hflags */
+#define MSR_ICM PPC_BIT_NR(33) /* Interrupt computation mode for BookE */
+#define MSR_GS PPC_BIT_NR(35) /* guest state for BookE */
+#define MSR_UCLE PPC_BIT_NR(37) /* User-mode cache lock enable for BookE */
+#define MSR_VR PPC_BIT_NR(38) /* altivec available x hflags */
+#define MSR_SPE PPC_BIT_NR(38) /* SPE enable for BookE x hflags */
+#define MSR_VSX PPC_BIT_NR(40) /* Vector Scalar Extension (>= 2.06)x hflags */
+#define MSR_S PPC_BIT_NR(41) /* Secure state */
+#define MSR_KEY PPC_BIT_NR(44) /* key bit on 603e */
+#define MSR_POW PPC_BIT_NR(45) /* Power management */
+#define MSR_WE PPC_BIT_NR(45) /* Wait State Enable on 405 */
+#define MSR_TGPR PPC_BIT_NR(46) /* TGPR usage on 602/603 x */
+#define MSR_CE PPC_BIT_NR(46) /* Critical int. enable on embedded PPC x */
+#define MSR_ILE PPC_BIT_NR(47) /* Interrupt little-endian mode */
+#define MSR_EE PPC_BIT_NR(48) /* External interrupt enable */
+#define MSR_PR PPC_BIT_NR(49) /* Problem state hflags */
+#define MSR_FP PPC_BIT_NR(50) /* Floating point available hflags */
+#define MSR_ME PPC_BIT_NR(51) /* Machine check interrupt enable */
+#define MSR_FE0 PPC_BIT_NR(52) /* Floating point exception mode 0 */
+#define MSR_SE PPC_BIT_NR(53) /* Single-step trace enable x hflags */
+#define MSR_DWE PPC_BIT_NR(53) /* Debug wait enable on 405 x */
+#define MSR_UBLE PPC_BIT_NR(53) /* User BTB lock enable on e500 x */
+#define MSR_BE PPC_BIT_NR(54) /* Branch trace enable x hflags */
+#define MSR_DE PPC_BIT_NR(54) /* Debug int. enable on embedded PPC x */
+#define MSR_FE1 PPC_BIT_NR(55) /* Floating point exception mode 1 */
+#define MSR_AL PPC_BIT_NR(56) /* AL bit on POWER */
+#define MSR_EP PPC_BIT_NR(57) /* Exception prefix on 601 */
+#define MSR_IR PPC_BIT_NR(58) /* Instruction relocate */
+#define MSR_IS PPC_BIT_NR(58) /* Instruction address space (BookE) */
+#define MSR_DR PPC_BIT_NR(59) /* Data relocate */
+#define MSR_DS PPC_BIT_NR(59) /* Data address space (BookE) */
+#define MSR_PE PPC_BIT_NR(60) /* Protection enable on 403 */
+#define MSR_PX PPC_BIT_NR(61) /* Protection exclusive on 403 x */
+#define MSR_PMM PPC_BIT_NR(61) /* Performance monitor mark on POWER x */
+#define MSR_RI PPC_BIT_NR(62) /* Recoverable interrupt 1 */
+#define MSR_LE PPC_BIT_NR(63) /* Little-endian mode 1 hflags */
FIELD(MSR, SF, MSR_SF, 1)
FIELD(MSR, TAG, MSR_TAG, 1)
--
2.25.1
^ permalink raw reply related [flat|nested] 29+ messages in thread
* Re: [PATCH v3 11/21] target/ppc: Remove msr_gs macro
2022-05-03 20:24 ` [PATCH v3 11/21] target/ppc: Remove msr_gs macro Víctor Colombo
@ 2022-05-04 2:03 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2022-05-04 2:03 UTC (permalink / raw)
To: Víctor Colombo, qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, balaton
On 5/3/22 13:24, Víctor Colombo wrote:
> msr_gs macro hides the usage of env->msr, which is a bad behavior
> Substitute it with FIELD_EX64 calls that explicitly use env->msr
> as a parameter.
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
>
> ---
>
> v3: Fix
> !(value & env->msr & R_MSR_GS_MASK) -> (value ^ env->msr) & R_MSR_GS_MASK
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
> ---
> target/ppc/cpu.h | 2 +-
> target/ppc/helper_regs.c | 2 +-
> target/ppc/mmu_helper.c | 4 ++--
> 3 files changed, 4 insertions(+), 4 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 14/21] target/ppc: Remove msr_ir macro
2022-05-03 20:24 ` [PATCH v3 14/21] target/ppc: Remove msr_ir macro Víctor Colombo
@ 2022-05-04 2:05 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2022-05-04 2:05 UTC (permalink / raw)
To: Víctor Colombo, qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, balaton
On 5/3/22 13:24, Víctor Colombo wrote:
> msr_ir macro hides the usage of env->msr, which is a bad behavior
> Substitute it with FIELD_EX64 calls that explicitly use env->msr
> as a parameter.
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
>
> ---
>
> v3: Fix the difference check to use a xor
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
> ---
> target/ppc/cpu.h | 2 +-
> target/ppc/helper_regs.c | 2 +-
> target/ppc/mmu_common.c | 11 ++++++-----
> 3 files changed, 8 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 15/21] target/ppc: Remove msr_dr macro
2022-05-03 20:24 ` [PATCH v3 15/21] target/ppc: Remove msr_dr macro Víctor Colombo
@ 2022-05-04 2:07 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2022-05-04 2:07 UTC (permalink / raw)
To: Víctor Colombo, qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, balaton
On 5/3/22 13:24, Víctor Colombo wrote:
> msr_dr macro hides the usage of env->msr, which is a bad behavior
> Substitute it with FIELD_EX64 calls that explicitly use env->msr
> as a parameter.
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
>
> ---
>
> v3: Fix the difference check to use a xor
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
> ---
> target/ppc/cpu.h | 2 +-
> target/ppc/helper_regs.c | 3 +--
> target/ppc/mmu_common.c | 10 ++++++----
> 3 files changed, 8 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 16/21] target/ppc: Remove msr_ep macro
2022-05-03 20:24 ` [PATCH v3 16/21] target/ppc: Remove msr_ep macro Víctor Colombo
@ 2022-05-04 2:08 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2022-05-04 2:08 UTC (permalink / raw)
To: Víctor Colombo, qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, balaton
On 5/3/22 13:24, Víctor Colombo wrote:
> msr_ep macro hides the usage of env->msr, which is a bad behavior
> Substitute it with FIELD_EX64 calls that explicitly use env->msr
> as a parameter.
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
>
> ---
>
> v3: Fix the difference check to use a xor
> fix incorrect "FIELD_EX64(env->msr, ..." -> "FIELD_EX64(value, ..."
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
> ---
> target/ppc/cpu.h | 2 +-
> target/ppc/helper_regs.c | 4 ++--
> 2 files changed, 3 insertions(+), 3 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 17/21] target/ppc: Remove msr_fe0 and msr_fe1 macros
2022-05-03 20:24 ` [PATCH v3 17/21] target/ppc: Remove msr_fe0 and msr_fe1 macros Víctor Colombo
@ 2022-05-04 2:08 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2022-05-04 2:08 UTC (permalink / raw)
To: Víctor Colombo, qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, balaton
On 5/3/22 13:24, Víctor Colombo wrote:
> msr_fe0 and msr_fe1 macros hide the usage of env->msr, which is a bad
> behavior. Substitute it with FIELD_EX64 calls that explicitly use
> env->msr as a parameter.
>
> Suggested-by: Richard Henderson<richard.henderson@linaro.org>
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
>
> ---
>
> v3: Added a combined macro for FE0 and FE1. Use it to simplify
> conditionals. Removed Richard's R-b because of this change.
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
> ---
> target/ppc/cpu.h | 11 +++++++++--
> target/ppc/excp_helper.c | 18 ++++++------------
> 2 files changed, 15 insertions(+), 14 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 21/21] target/ppc: Change MSR_* to follow POWER ISA numbering convention
2022-05-03 20:24 ` [PATCH v3 21/21] target/ppc: Change MSR_* to follow POWER ISA numbering convention Víctor Colombo
@ 2022-05-04 2:09 ` Richard Henderson
0 siblings, 0 replies; 29+ messages in thread
From: Richard Henderson @ 2022-05-04 2:09 UTC (permalink / raw)
To: Víctor Colombo, qemu-devel, qemu-ppc
Cc: clg, danielhb413, david, groug, balaton
On 5/3/22 13:24, Víctor Colombo wrote:
> Today we have the issue where MSR_* values are the 'inverted order'
> bit numbers from what the ISA specifies. e.g. MSR_LE is bit 63 but
> is defined as 0 in QEMU.
>
> Add a macro to be used to convert from QEMU order to ISA order.
>
> This solution requires less changes than to use the already defined
> PPC_BIT macro, which would turn MSR_* in masks instead of the numbers
> itself.
>
> Signed-off-by: Víctor Colombo<victor.colombo@eldorado.org.br>
> ---
> target/ppc/cpu.h | 87 ++++++++++++++++++++++++------------------------
> 1 file changed, 44 insertions(+), 43 deletions(-)
Acked-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 29+ messages in thread
* Re: [PATCH v3 00/21] target/ppc: Remove hidden usages of *env
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
` (20 preceding siblings ...)
2022-05-03 20:24 ` [PATCH v3 21/21] target/ppc: Change MSR_* to follow POWER ISA numbering convention Víctor Colombo
@ 2022-05-04 20:33 ` Daniel Henrique Barboza
21 siblings, 0 replies; 29+ messages in thread
From: Daniel Henrique Barboza @ 2022-05-04 20:33 UTC (permalink / raw)
To: Víctor Colombo, qemu-devel, qemu-ppc
Cc: clg, david, groug, richard.henderson, balaton
I asked Victor to rebase this series on top of ppc-next at:
gitlab.com/danielhb/qemu/tree/ppc-next
Because of
"[PATCH v2] target/ppc: Fix BookE debug interrupt generation"
that added new occurrences of the msr_de macro that wasn't being handled.
I believe that the changes needed are not removing msr_de in patch 02 and
adding a new patch to handle the two existing msr_de instances.
After this series is fully reviewed I'll send a PR with it ASAP to avoid
further conflicts.
Thanks,
Daniel
On 5/3/22 17:24, Víctor Colombo wrote:
> By running the grep command `git grep -nr 'define \(fpscr\|msr\)_[a-z0-9]\+\>'`
> we can find multiple macros that use `env->fpscr` and `env->msr` but doesn't
> take *env as a parameter.
>
> Richard Henderson said [1] that these macros hiding the usage of *env "are evil".
> This patch series remove them and substitute with an explicit usage of *env by
> using registerfields API.
>
> Patch 20 (target/ppc: Add unused msr bits FIELDs) declares unused FIELDs, the
> same that were removed in patch 02 (target/ppc: Remove unused msr_* macros). I
> did that to keep the changes consistent with what was already present before.
>
> Patch 21 (target/ppc: Change MSR_* to follow POWER ISA numbering convention)
> changes the MSR_* bit number to match POWER ISA by adding a new macro to
> 'invert' the ordering. (added in v2)
>
> [1]: https://lists.gnu.org/archive/html/qemu-ppc/2021-11/msg00280.html
>
> Patches requiring review: 11, 14, 15, 16, 17, 21
> Patch 17 was reviewed before, but I created a macro to extract both FE0
> and FE1, so decided to drop the R-b for you to take a look at the
> new version. Thanks
>
> v2:
> - Abandon the ideia to add an M_MSR_* macro
> - Instead, use registerfields API as suggested by Richard
> - Add patch 21 to invert MSR_* values to match ISA ordering
>
> v3:
> - Add macro to extract both FE0 and FE1. Use it to simplify the
> conditionals in patch 17
> - Fix the checks that should be a xor
> - Fix incorrect parameter in FIELD_EX64 (was env->msr should be value)
> in patch 16
> - Fix patch 13 title
>
> Víctor Colombo (21):
> target/ppc: Remove fpscr_* macros from cpu.h
> target/ppc: Remove unused msr_* macros
> target/ppc: Remove msr_pr macro
> target/ppc: Remove msr_le macro
> target/ppc: Remove msr_ds macro
> target/ppc: Remove msr_ile macro
> target/ppc: Remove msr_ee macro
> target/ppc: Remove msr_ce macro
> target/ppc: Remove msr_pow macro
> target/ppc: Remove msr_me macro
> target/ppc: Remove msr_gs macro
> target/ppc: Remove msr_fp macro
> target/ppc: Remove msr_cm macro
> target/ppc: Remove msr_ir macro
> target/ppc: Remove msr_dr macro
> target/ppc: Remove msr_ep macro
> target/ppc: Remove msr_fe0 and msr_fe1 macros
> target/ppc: Remove msr_ts macro
> target/ppc: Remove msr_hv macro
> target/ppc: Add unused msr bits FIELDs
> target/ppc: Change MSR_* to follow POWER ISA numbering convention
>
> hw/ppc/pegasos2.c | 2 +-
> hw/ppc/spapr.c | 2 +-
> target/ppc/cpu.c | 2 +-
> target/ppc/cpu.h | 219 ++++++++++++++++++---------------------
> target/ppc/cpu_init.c | 23 ++--
> target/ppc/excp_helper.c | 54 +++++-----
> target/ppc/fpu_helper.c | 28 ++---
> target/ppc/gdbstub.c | 2 +-
> target/ppc/helper_regs.c | 11 +-
> target/ppc/kvm.c | 7 +-
> target/ppc/machine.c | 2 +-
> target/ppc/mem_helper.c | 23 ++--
> target/ppc/misc_helper.c | 2 +-
> target/ppc/mmu-radix64.c | 11 +-
> target/ppc/mmu_common.c | 40 +++----
> target/ppc/mmu_helper.c | 6 +-
> 16 files changed, 217 insertions(+), 217 deletions(-)
>
^ permalink raw reply [flat|nested] 29+ messages in thread
end of thread, other threads:[~2022-05-04 20:34 UTC | newest]
Thread overview: 29+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-03 20:24 [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 01/21] target/ppc: Remove fpscr_* macros from cpu.h Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 02/21] target/ppc: Remove unused msr_* macros Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 03/21] target/ppc: Remove msr_pr macro Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 04/21] target/ppc: Remove msr_le macro Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 05/21] target/ppc: Remove msr_ds macro Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 06/21] target/ppc: Remove msr_ile macro Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 07/21] target/ppc: Remove msr_ee macro Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 08/21] target/ppc: Remove msr_ce macro Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 09/21] target/ppc: Remove msr_pow macro Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 10/21] target/ppc: Remove msr_me macro Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 11/21] target/ppc: Remove msr_gs macro Víctor Colombo
2022-05-04 2:03 ` Richard Henderson
2022-05-03 20:24 ` [PATCH v3 12/21] target/ppc: Remove msr_fp macro Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 13/21] target/ppc: Remove msr_cm macro Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 14/21] target/ppc: Remove msr_ir macro Víctor Colombo
2022-05-04 2:05 ` Richard Henderson
2022-05-03 20:24 ` [PATCH v3 15/21] target/ppc: Remove msr_dr macro Víctor Colombo
2022-05-04 2:07 ` Richard Henderson
2022-05-03 20:24 ` [PATCH v3 16/21] target/ppc: Remove msr_ep macro Víctor Colombo
2022-05-04 2:08 ` Richard Henderson
2022-05-03 20:24 ` [PATCH v3 17/21] target/ppc: Remove msr_fe0 and msr_fe1 macros Víctor Colombo
2022-05-04 2:08 ` Richard Henderson
2022-05-03 20:24 ` [PATCH v3 18/21] target/ppc: Remove msr_ts macro Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 19/21] target/ppc: Remove msr_hv macro Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 20/21] target/ppc: Add unused msr bits FIELDs Víctor Colombo
2022-05-03 20:24 ` [PATCH v3 21/21] target/ppc: Change MSR_* to follow POWER ISA numbering convention Víctor Colombo
2022-05-04 2:09 ` Richard Henderson
2022-05-04 20:33 ` [PATCH v3 00/21] target/ppc: Remove hidden usages of *env Daniel Henrique Barboza
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