* [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
@ 2022-05-04 12:07 ` Tvrtko Ursulin
0 siblings, 0 replies; 18+ messages in thread
From: Tvrtko Ursulin @ 2022-05-04 12:07 UTC (permalink / raw)
To: Intel-gfx; +Cc: Jani Nikula, dri-devel, Tvrtko Ursulin
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
to exercise a certain code path, so in case of values coming from MMIO
reads we cannot be sure CI will have all the possible SKUs and parts.
Use drm_warn instead and move logging to init phase while at it.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 53307ca0eed0..c474e5c3ea5e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
* An mslice is unavailable only if both the meml3 for the slice is
* disabled *and* all of the DSS in the slice (quadrant) are disabled.
*/
- if (HAS_MSLICES(i915))
+ if (HAS_MSLICES(i915)) {
gt->info.mslice_mask =
slicemask(gt, GEN_DSS_PER_MSLICE) |
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN12_MEML3_EN_MASK);
+ if (!gt->info.mslice_mask) /* should be impossible! */
+ drm_warn(&i915->drm, "mslice mask all zero!\n");
+ }
if (IS_DG2(i915)) {
gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
@@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
gt->info.l3bank_mask =
~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN10_L3BANK_MASK;
+ if (!gt->info.l3bank_mask) /* should be impossible! */
+ drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
} else if (HAS_MSLICES(i915)) {
MISSING_CASE(INTEL_INFO(i915)->platform);
}
@@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
{
switch (type) {
case L3BANK:
- GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
-
*sliceid = 0; /* unused */
*subsliceid = __ffs(gt->info.l3bank_mask);
break;
case MSLICE:
- GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
-
*sliceid = __ffs(gt->info.mslice_mask);
*subsliceid = 0; /* unused */
break;
case LNCF:
- GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
-
/*
* An LNCF is always present if its mslice is present, so we
* can safely just steer to LNCF 0 in all cases.
--
2.32.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
@ 2022-05-04 12:07 ` Tvrtko Ursulin
0 siblings, 0 replies; 18+ messages in thread
From: Tvrtko Ursulin @ 2022-05-04 12:07 UTC (permalink / raw)
To: Intel-gfx; +Cc: Jani Nikula, dri-devel
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
to exercise a certain code path, so in case of values coming from MMIO
reads we cannot be sure CI will have all the possible SKUs and parts.
Use drm_warn instead and move logging to init phase while at it.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Matt Roper <matthew.d.roper@intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++++++-------
1 file changed, 6 insertions(+), 7 deletions(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
index 53307ca0eed0..c474e5c3ea5e 100644
--- a/drivers/gpu/drm/i915/gt/intel_gt.c
+++ b/drivers/gpu/drm/i915/gt/intel_gt.c
@@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
* An mslice is unavailable only if both the meml3 for the slice is
* disabled *and* all of the DSS in the slice (quadrant) are disabled.
*/
- if (HAS_MSLICES(i915))
+ if (HAS_MSLICES(i915)) {
gt->info.mslice_mask =
slicemask(gt, GEN_DSS_PER_MSLICE) |
(intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN12_MEML3_EN_MASK);
+ if (!gt->info.mslice_mask) /* should be impossible! */
+ drm_warn(&i915->drm, "mslice mask all zero!\n");
+ }
if (IS_DG2(i915)) {
gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
@@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
gt->info.l3bank_mask =
~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
GEN10_L3BANK_MASK;
+ if (!gt->info.l3bank_mask) /* should be impossible! */
+ drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
} else if (HAS_MSLICES(i915)) {
MISSING_CASE(INTEL_INFO(i915)->platform);
}
@@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
{
switch (type) {
case L3BANK:
- GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
-
*sliceid = 0; /* unused */
*subsliceid = __ffs(gt->info.l3bank_mask);
break;
case MSLICE:
- GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
-
*sliceid = __ffs(gt->info.mslice_mask);
*subsliceid = 0; /* unused */
break;
case LNCF:
- GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
-
/*
* An LNCF is always present if its mslice is present, so we
* can safely just steer to LNCF 0 in all cases.
--
2.32.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [PATCH 2/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for ring unexpectedly not idle
2022-05-04 12:07 ` [Intel-gfx] " Tvrtko Ursulin
@ 2022-05-04 12:07 ` Tvrtko Ursulin
-1 siblings, 0 replies; 18+ messages in thread
From: Tvrtko Ursulin @ 2022-05-04 12:07 UTC (permalink / raw)
To: Intel-gfx; +Cc: Jani Nikula, Mika Kuoppala, dri-devel, Tvrtko Ursulin
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
to exercise a certain code path, so in case of values coming from MMIO
reads we cannot be sure CI will have all the possible SKUs and parts, or
that it will catch all possible error conditions. Use drm_warn instead.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 5423bfd301ad..f8f279a195c0 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -117,7 +117,9 @@ static void flush_cs_tlb(struct intel_engine_cs *engine)
return;
/* ring should be idle before issuing a sync flush*/
- GEM_DEBUG_WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
+ if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0)
+ drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n",
+ engine->name);
ENGINE_WRITE_FW(engine, RING_INSTPM,
_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
--
2.32.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] [PATCH 2/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for ring unexpectedly not idle
@ 2022-05-04 12:07 ` Tvrtko Ursulin
0 siblings, 0 replies; 18+ messages in thread
From: Tvrtko Ursulin @ 2022-05-04 12:07 UTC (permalink / raw)
To: Intel-gfx; +Cc: Jani Nikula, dri-devel
From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
to exercise a certain code path, so in case of values coming from MMIO
reads we cannot be sure CI will have all the possible SKUs and parts, or
that it will catch all possible error conditions. Use drm_warn instead.
Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
Cc: Jani Nikula <jani.nikula@intel.com>
---
drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 +++-
1 file changed, 3 insertions(+), 1 deletion(-)
diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
index 5423bfd301ad..f8f279a195c0 100644
--- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
+++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
@@ -117,7 +117,9 @@ static void flush_cs_tlb(struct intel_engine_cs *engine)
return;
/* ring should be idle before issuing a sync flush*/
- GEM_DEBUG_WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
+ if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0)
+ drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n",
+ engine->name);
ENGINE_WRITE_FW(engine, RING_INSTPM,
_MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
--
2.32.0
^ permalink raw reply related [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
2022-05-04 12:07 ` [Intel-gfx] " Tvrtko Ursulin
(?)
(?)
@ 2022-05-04 13:59 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-05-04 13:59 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 14588 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
URL : https://patchwork.freedesktop.org/series/103536/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11602 -> Patchwork_103536v1
====================================================
Summary
-------
**SUCCESS**
No regressions found.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/index.html
Participating hosts (33 -> 43)
------------------------------
Additional (11): fi-rkl-11600 bat-dg1-6 bat-dg2-8 bat-adlm-1 fi-icl-u2 bat-adlp-6 bat-adln-1 bat-rpls-1 bat-rpls-2 bat-jsl-2 bat-jsl-1
Missing (1): fi-pnv-d510
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_103536v1:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@gt_contexts:
- {bat-adlm-1}: NOTRUN -> [INCOMPLETE][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-adlm-1/igt@i915_selftest@live@gt_contexts.html
Known issues
------------
Here are the changes found in Patchwork_103536v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-rkl-11600: NOTRUN -> [SKIP][2] ([i915#2190])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-rkl-11600/igt@gem_huc_copy@huc-copy.html
- fi-icl-u2: NOTRUN -> [SKIP][3] ([i915#2190])
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-icl-u2/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@parallel-random-engines:
- fi-icl-u2: NOTRUN -> [SKIP][4] ([i915#4613]) +3 similar issues
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-icl-u2/igt@gem_lmem_swapping@parallel-random-engines.html
- fi-rkl-11600: NOTRUN -> [SKIP][5] ([i915#4613]) +3 similar issues
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-rkl-11600/igt@gem_lmem_swapping@parallel-random-engines.html
* igt@gem_mmap@basic:
- bat-dg1-6: NOTRUN -> [SKIP][6] ([i915#4083])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@gem_mmap@basic.html
* igt@gem_tiled_blits@basic:
- bat-dg1-6: NOTRUN -> [SKIP][7] ([i915#4077]) +2 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@gem_tiled_blits@basic.html
* igt@gem_tiled_pread_basic:
- bat-dg1-6: NOTRUN -> [SKIP][8] ([i915#4079]) +1 similar issue
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@gem_tiled_pread_basic.html
- fi-rkl-11600: NOTRUN -> [SKIP][9] ([i915#3282])
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-rkl-11600/igt@gem_tiled_pread_basic.html
* igt@i915_pm_backlight@basic-brightness:
- fi-rkl-11600: NOTRUN -> [SKIP][10] ([i915#3012])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-rkl-11600/igt@i915_pm_backlight@basic-brightness.html
- bat-dg1-6: NOTRUN -> [SKIP][11] ([i915#1155])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_selftest@live@gt_engines:
- bat-dg1-6: NOTRUN -> [INCOMPLETE][12] ([i915#4418])
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@i915_selftest@live@gt_engines.html
* igt@kms_addfb_basic@addfb25-x-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][13] ([i915#4212]) +7 similar issues
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@kms_addfb_basic@addfb25-x-tiled-legacy.html
* igt@kms_addfb_basic@basic-y-tiled-legacy:
- bat-dg1-6: NOTRUN -> [SKIP][14] ([i915#4215])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@kms_addfb_basic@basic-y-tiled-legacy.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-snb-2600: NOTRUN -> [SKIP][15] ([fdo#109271] / [fdo#111827])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-snb-2600/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- fi-rkl-11600: NOTRUN -> [SKIP][16] ([fdo#111827]) +8 similar issues
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-rkl-11600/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@hdmi-edid-read:
- bat-dg1-6: NOTRUN -> [SKIP][17] ([fdo#111827]) +7 similar issues
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@kms_chamelium@hdmi-edid-read.html
* igt@kms_chamelium@hdmi-hpd-fast:
- fi-icl-u2: NOTRUN -> [SKIP][18] ([fdo#111827]) +8 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-icl-u2/igt@kms_chamelium@hdmi-hpd-fast.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic:
- fi-icl-u2: NOTRUN -> [SKIP][19] ([fdo#109278]) +2 similar issues
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-icl-u2/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- fi-rkl-11600: NOTRUN -> [SKIP][20] ([i915#4070] / [i915#4103]) +1 similar issue
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-rkl-11600/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
- bat-dg1-6: NOTRUN -> [SKIP][21] ([i915#4103] / [i915#4213]) +1 similar issue
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-atomic.html
* igt@kms_force_connector_basic@force-load-detect:
- bat-dg1-6: NOTRUN -> [SKIP][22] ([fdo#109285])
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@kms_force_connector_basic@force-load-detect.html
- fi-rkl-11600: NOTRUN -> [SKIP][23] ([fdo#109285] / [i915#4098])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-rkl-11600/igt@kms_force_connector_basic@force-load-detect.html
- fi-icl-u2: NOTRUN -> [SKIP][24] ([fdo#109285])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-icl-u2/igt@kms_force_connector_basic@force-load-detect.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-rkl-11600: NOTRUN -> [SKIP][25] ([i915#4070] / [i915#533])
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-rkl-11600/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@cursor_plane_move:
- bat-dg1-6: NOTRUN -> [SKIP][26] ([i915#1072] / [i915#4078]) +3 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@kms_psr@cursor_plane_move.html
* igt@kms_psr@primary_mmap_gtt:
- fi-rkl-11600: NOTRUN -> [SKIP][27] ([i915#1072]) +3 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-rkl-11600/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-icl-u2: NOTRUN -> [SKIP][28] ([i915#3555])
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-icl-u2/igt@kms_setmode@basic-clone-single-crtc.html
- bat-dg1-6: NOTRUN -> [SKIP][29] ([i915#3555])
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@kms_setmode@basic-clone-single-crtc.html
- fi-rkl-11600: NOTRUN -> [SKIP][30] ([i915#3555] / [i915#4098])
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-rkl-11600/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-flip:
- bat-dg1-6: NOTRUN -> [SKIP][31] ([i915#3708]) +3 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@prime_vgem@basic-fence-flip.html
* igt@prime_vgem@basic-gtt:
- bat-dg1-6: NOTRUN -> [SKIP][32] ([i915#3708] / [i915#4077]) +1 similar issue
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@prime_vgem@basic-gtt.html
* igt@prime_vgem@basic-userptr:
- fi-rkl-11600: NOTRUN -> [SKIP][33] ([i915#3301] / [i915#3708])
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-rkl-11600/igt@prime_vgem@basic-userptr.html
- fi-icl-u2: NOTRUN -> [SKIP][34] ([i915#3301])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-icl-u2/igt@prime_vgem@basic-userptr.html
- bat-dg1-6: NOTRUN -> [SKIP][35] ([i915#3708] / [i915#4873])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@prime_vgem@basic-userptr.html
* igt@prime_vgem@basic-write:
- fi-rkl-11600: NOTRUN -> [SKIP][36] ([i915#3291] / [i915#3708]) +2 similar issues
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-rkl-11600/igt@prime_vgem@basic-write.html
* igt@runner@aborted:
- bat-dg1-6: NOTRUN -> [FAIL][37] ([i915#4312] / [i915#5257])
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/bat-dg1-6/igt@runner@aborted.html
#### Possible fixes ####
* igt@gem_exec_suspend@basic-s0@smem:
- {fi-ehl-2}: [DMESG-WARN][38] ([i915#5122]) -> [PASS][39]
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-ehl-2/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][40] ([i915#3921]) -> [PASS][41]
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
* igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a:
- fi-hsw-4770: [SKIP][42] ([fdo#109271]) -> [PASS][43]
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/fi-hsw-4770/igt@kms_pipe_crc_basic@suspend-read-crc-pipe-a.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1155]: https://gitlab.freedesktop.org/drm/intel/issues/1155
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#3003]: https://gitlab.freedesktop.org/drm/intel/issues/3003
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3595]: https://gitlab.freedesktop.org/drm/intel/issues/3595
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4078]: https://gitlab.freedesktop.org/drm/intel/issues/4078
[i915#4079]: https://gitlab.freedesktop.org/drm/intel/issues/4079
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4213]: https://gitlab.freedesktop.org/drm/intel/issues/4213
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4418]: https://gitlab.freedesktop.org/drm/intel/issues/4418
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4873]: https://gitlab.freedesktop.org/drm/intel/issues/4873
[i915#4983]: https://gitlab.freedesktop.org/drm/intel/issues/4983
[i915#5087]: https://gitlab.freedesktop.org/drm/intel/issues/5087
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#5190]: https://gitlab.freedesktop.org/drm/intel/issues/5190
[i915#5257]: https://gitlab.freedesktop.org/drm/intel/issues/5257
[i915#5274]: https://gitlab.freedesktop.org/drm/intel/issues/5274
[i915#5275]: https://gitlab.freedesktop.org/drm/intel/issues/5275
[i915#5278]: https://gitlab.freedesktop.org/drm/intel/issues/5278
[i915#5329]: https://gitlab.freedesktop.org/drm/intel/issues/5329
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5354]: https://gitlab.freedesktop.org/drm/intel/issues/5354
[i915#5763]: https://gitlab.freedesktop.org/drm/intel/issues/5763
[i915#5869]: https://gitlab.freedesktop.org/drm/intel/issues/5869
[i915#5874]: https://gitlab.freedesktop.org/drm/intel/issues/5874
[i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885
Build changes
-------------
* Linux: CI_DRM_11602 -> Patchwork_103536v1
CI-20190529: 20190529
CI_DRM_11602: 4c7e3b6eee2669c87798d1303bca653b1b26d790 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6465: f6bb4399881a806fbff75ce3df89b60286d55917 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103536v1: 4c7e3b6eee2669c87798d1303bca653b1b26d790 @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
342926f79bf3 drm/i915: Don't use DRM_DEBUG_WARN_ON for ring unexpectedly not idle
f4aa594bf93e drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/index.html
[-- Attachment #2: Type: text/html, Size: 16303 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
2022-05-04 12:07 ` [Intel-gfx] " Tvrtko Ursulin
@ 2022-05-04 16:48 ` Matt Roper
-1 siblings, 0 replies; 18+ messages in thread
From: Matt Roper @ 2022-05-04 16:48 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Jani Nikula, Intel-gfx, dri-devel, Tvrtko Ursulin
On Wed, May 04, 2022 at 01:07:14PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
> to exercise a certain code path, so in case of values coming from MMIO
> reads we cannot be sure CI will have all the possible SKUs and parts.
>
> Use drm_warn instead and move logging to init phase while at it.
Changing to drm_warn looks good, although moving the location changes
the intent a bit; I think originally the idea was to warn if we were
trying to do a steering lookup for a type that we never initialized
(e.g., an LNCF lookup for a !HAS_MSLICES platform where we never even
read the register in the first place). But I don't think we've ever
made a mistake that would cause us to trip the warning, so it probably
isn't terribly important to keep it there.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++++++-------
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 53307ca0eed0..c474e5c3ea5e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> * An mslice is unavailable only if both the meml3 for the slice is
> * disabled *and* all of the DSS in the slice (quadrant) are disabled.
> */
> - if (HAS_MSLICES(i915))
> + if (HAS_MSLICES(i915)) {
> gt->info.mslice_mask =
> slicemask(gt, GEN_DSS_PER_MSLICE) |
> (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> GEN12_MEML3_EN_MASK);
> + if (!gt->info.mslice_mask) /* should be impossible! */
> + drm_warn(&i915->drm, "mslice mask all zero!\n");
> + }
>
> if (IS_DG2(i915)) {
> gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
> @@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> gt->info.l3bank_mask =
> ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> GEN10_L3BANK_MASK;
> + if (!gt->info.l3bank_mask) /* should be impossible! */
> + drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
> } else if (HAS_MSLICES(i915)) {
> MISSING_CASE(INTEL_INFO(i915)->platform);
> }
> @@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
> {
> switch (type) {
> case L3BANK:
> - GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
> -
> *sliceid = 0; /* unused */
> *subsliceid = __ffs(gt->info.l3bank_mask);
> break;
> case MSLICE:
> - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
> -
> *sliceid = __ffs(gt->info.mslice_mask);
> *subsliceid = 0; /* unused */
> break;
> case LNCF:
> - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
> -
> /*
> * An LNCF is always present if its mslice is present, so we
> * can safely just steer to LNCF 0 in all cases.
> --
> 2.32.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
@ 2022-05-04 16:48 ` Matt Roper
0 siblings, 0 replies; 18+ messages in thread
From: Matt Roper @ 2022-05-04 16:48 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Jani Nikula, Intel-gfx, dri-devel
On Wed, May 04, 2022 at 01:07:14PM +0100, Tvrtko Ursulin wrote:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
> to exercise a certain code path, so in case of values coming from MMIO
> reads we cannot be sure CI will have all the possible SKUs and parts.
>
> Use drm_warn instead and move logging to init phase while at it.
Changing to drm_warn looks good, although moving the location changes
the intent a bit; I think originally the idea was to warn if we were
trying to do a steering lookup for a type that we never initialized
(e.g., an LNCF lookup for a !HAS_MSLICES platform where we never even
read the register in the first place). But I don't think we've ever
made a mistake that would cause us to trip the warning, so it probably
isn't terribly important to keep it there.
Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Matt Roper <matthew.d.roper@intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++++++-------
> 1 file changed, 6 insertions(+), 7 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> index 53307ca0eed0..c474e5c3ea5e 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> @@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> * An mslice is unavailable only if both the meml3 for the slice is
> * disabled *and* all of the DSS in the slice (quadrant) are disabled.
> */
> - if (HAS_MSLICES(i915))
> + if (HAS_MSLICES(i915)) {
> gt->info.mslice_mask =
> slicemask(gt, GEN_DSS_PER_MSLICE) |
> (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> GEN12_MEML3_EN_MASK);
> + if (!gt->info.mslice_mask) /* should be impossible! */
> + drm_warn(&i915->drm, "mslice mask all zero!\n");
> + }
>
> if (IS_DG2(i915)) {
> gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
> @@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> gt->info.l3bank_mask =
> ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> GEN10_L3BANK_MASK;
> + if (!gt->info.l3bank_mask) /* should be impossible! */
> + drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
> } else if (HAS_MSLICES(i915)) {
> MISSING_CASE(INTEL_INFO(i915)->platform);
> }
> @@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
> {
> switch (type) {
> case L3BANK:
> - GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
> -
> *sliceid = 0; /* unused */
> *subsliceid = __ffs(gt->info.l3bank_mask);
> break;
> case MSLICE:
> - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
> -
> *sliceid = __ffs(gt->info.mslice_mask);
> *subsliceid = 0; /* unused */
> break;
> case LNCF:
> - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
> -
> /*
> * An LNCF is always present if its mslice is present, so we
> * can safely just steer to LNCF 0 in all cases.
> --
> 2.32.0
>
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
2022-05-04 16:48 ` [Intel-gfx] " Matt Roper
@ 2022-05-04 17:59 ` Tvrtko Ursulin
-1 siblings, 0 replies; 18+ messages in thread
From: Tvrtko Ursulin @ 2022-05-04 17:59 UTC (permalink / raw)
To: Matt Roper; +Cc: Jani Nikula, Intel-gfx, dri-devel, Tvrtko Ursulin
On 04/05/2022 17:48, Matt Roper wrote:
> On Wed, May 04, 2022 at 01:07:14PM +0100, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
>> to exercise a certain code path, so in case of values coming from MMIO
>> reads we cannot be sure CI will have all the possible SKUs and parts.
>>
>> Use drm_warn instead and move logging to init phase while at it.
>
> Changing to drm_warn looks good, although moving the location changes
> the intent a bit; I think originally the idea was to warn if we were
> trying to do a steering lookup for a type that we never initialized
> (e.g., an LNCF lookup for a !HAS_MSLICES platform where we never even
> read the register in the first place). But I don't think we've ever
> made a mistake that would cause us to trip the warning, so it probably
> isn't terribly important to keep it there.
Ah I see.. there we could put something like:
case MSLICE:
GEM_WARN_ON(!HAS_MSLICES(...));
?
Regards,
Tvrtko
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++++++-------
>> 1 file changed, 6 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>> index 53307ca0eed0..c474e5c3ea5e 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> @@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
>> * An mslice is unavailable only if both the meml3 for the slice is
>> * disabled *and* all of the DSS in the slice (quadrant) are disabled.
>> */
>> - if (HAS_MSLICES(i915))
>> + if (HAS_MSLICES(i915)) {
>> gt->info.mslice_mask =
>> slicemask(gt, GEN_DSS_PER_MSLICE) |
>> (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
>> GEN12_MEML3_EN_MASK);
>> + if (!gt->info.mslice_mask) /* should be impossible! */
>> + drm_warn(&i915->drm, "mslice mask all zero!\n");
>> + }
>>
>> if (IS_DG2(i915)) {
>> gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
>> @@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
>> gt->info.l3bank_mask =
>> ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
>> GEN10_L3BANK_MASK;
>> + if (!gt->info.l3bank_mask) /* should be impossible! */
>> + drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
>> } else if (HAS_MSLICES(i915)) {
>> MISSING_CASE(INTEL_INFO(i915)->platform);
>> }
>> @@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
>> {
>> switch (type) {
>> case L3BANK:
>> - GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
>> -
>> *sliceid = 0; /* unused */
>> *subsliceid = __ffs(gt->info.l3bank_mask);
>> break;
>> case MSLICE:
>> - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
>> -
>> *sliceid = __ffs(gt->info.mslice_mask);
>> *subsliceid = 0; /* unused */
>> break;
>> case LNCF:
>> - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
>> -
>> /*
>> * An LNCF is always present if its mslice is present, so we
>> * can safely just steer to LNCF 0 in all cases.
>> --
>> 2.32.0
>>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
@ 2022-05-04 17:59 ` Tvrtko Ursulin
0 siblings, 0 replies; 18+ messages in thread
From: Tvrtko Ursulin @ 2022-05-04 17:59 UTC (permalink / raw)
To: Matt Roper; +Cc: Jani Nikula, Intel-gfx, dri-devel
On 04/05/2022 17:48, Matt Roper wrote:
> On Wed, May 04, 2022 at 01:07:14PM +0100, Tvrtko Ursulin wrote:
>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>
>> DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
>> to exercise a certain code path, so in case of values coming from MMIO
>> reads we cannot be sure CI will have all the possible SKUs and parts.
>>
>> Use drm_warn instead and move logging to init phase while at it.
>
> Changing to drm_warn looks good, although moving the location changes
> the intent a bit; I think originally the idea was to warn if we were
> trying to do a steering lookup for a type that we never initialized
> (e.g., an LNCF lookup for a !HAS_MSLICES platform where we never even
> read the register in the first place). But I don't think we've ever
> made a mistake that would cause us to trip the warning, so it probably
> isn't terribly important to keep it there.
Ah I see.. there we could put something like:
case MSLICE:
GEM_WARN_ON(!HAS_MSLICES(...));
?
Regards,
Tvrtko
>
> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>
>>
>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>> Cc: Matt Roper <matthew.d.roper@intel.com>
>> Cc: Jani Nikula <jani.nikula@intel.com>
>> ---
>> drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++++++-------
>> 1 file changed, 6 insertions(+), 7 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>> index 53307ca0eed0..c474e5c3ea5e 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>> @@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
>> * An mslice is unavailable only if both the meml3 for the slice is
>> * disabled *and* all of the DSS in the slice (quadrant) are disabled.
>> */
>> - if (HAS_MSLICES(i915))
>> + if (HAS_MSLICES(i915)) {
>> gt->info.mslice_mask =
>> slicemask(gt, GEN_DSS_PER_MSLICE) |
>> (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
>> GEN12_MEML3_EN_MASK);
>> + if (!gt->info.mslice_mask) /* should be impossible! */
>> + drm_warn(&i915->drm, "mslice mask all zero!\n");
>> + }
>>
>> if (IS_DG2(i915)) {
>> gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
>> @@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
>> gt->info.l3bank_mask =
>> ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
>> GEN10_L3BANK_MASK;
>> + if (!gt->info.l3bank_mask) /* should be impossible! */
>> + drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
>> } else if (HAS_MSLICES(i915)) {
>> MISSING_CASE(INTEL_INFO(i915)->platform);
>> }
>> @@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
>> {
>> switch (type) {
>> case L3BANK:
>> - GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
>> -
>> *sliceid = 0; /* unused */
>> *subsliceid = __ffs(gt->info.l3bank_mask);
>> break;
>> case MSLICE:
>> - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
>> -
>> *sliceid = __ffs(gt->info.mslice_mask);
>> *subsliceid = 0; /* unused */
>> break;
>> case LNCF:
>> - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
>> -
>> /*
>> * An LNCF is always present if its mslice is present, so we
>> * can safely just steer to LNCF 0 in all cases.
>> --
>> 2.32.0
>>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
2022-05-04 17:59 ` [Intel-gfx] " Tvrtko Ursulin
@ 2022-05-04 18:17 ` Matt Roper
-1 siblings, 0 replies; 18+ messages in thread
From: Matt Roper @ 2022-05-04 18:17 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Jani Nikula, Intel-gfx, dri-devel, Tvrtko Ursulin
On Wed, May 04, 2022 at 06:59:32PM +0100, Tvrtko Ursulin wrote:
>
> On 04/05/2022 17:48, Matt Roper wrote:
> > On Wed, May 04, 2022 at 01:07:14PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > >
> > > DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
> > > to exercise a certain code path, so in case of values coming from MMIO
> > > reads we cannot be sure CI will have all the possible SKUs and parts.
> > >
> > > Use drm_warn instead and move logging to init phase while at it.
> >
> > Changing to drm_warn looks good, although moving the location changes
> > the intent a bit; I think originally the idea was to warn if we were
> > trying to do a steering lookup for a type that we never initialized
> > (e.g., an LNCF lookup for a !HAS_MSLICES platform where we never even
> > read the register in the first place). But I don't think we've ever
> > made a mistake that would cause us to trip the warning, so it probably
> > isn't terribly important to keep it there.
>
> Ah I see.. there we could put something like:
>
> case MSLICE:
> GEM_WARN_ON(!HAS_MSLICES(...));
>
Yeah, that would work for MSLICE and LNCF. Although L3BANK is a bit
stranger since we have multiple platforms that obtain the L3 bank mask
in completely different ways (Xe_HP reads it from XEHP_FUSE4, whereas
gen11/gen12 reads it from GEN10_MIRROR_FUSE3). We want to make sure
there that no matter which branch of init we take, we didn't forget to
initialize l3bank_mask somehow.
Matt
> ?
>
> Regards,
>
> Tvrtko
>
> >
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> >
> > >
> > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++++++-------
> > > 1 file changed, 6 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > index 53307ca0eed0..c474e5c3ea5e 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > @@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> > > * An mslice is unavailable only if both the meml3 for the slice is
> > > * disabled *and* all of the DSS in the slice (quadrant) are disabled.
> > > */
> > > - if (HAS_MSLICES(i915))
> > > + if (HAS_MSLICES(i915)) {
> > > gt->info.mslice_mask =
> > > slicemask(gt, GEN_DSS_PER_MSLICE) |
> > > (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> > > GEN12_MEML3_EN_MASK);
> > > + if (!gt->info.mslice_mask) /* should be impossible! */
> > > + drm_warn(&i915->drm, "mslice mask all zero!\n");
> > > + }
> > > if (IS_DG2(i915)) {
> > > gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
> > > @@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> > > gt->info.l3bank_mask =
> > > ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> > > GEN10_L3BANK_MASK;
> > > + if (!gt->info.l3bank_mask) /* should be impossible! */
> > > + drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
> > > } else if (HAS_MSLICES(i915)) {
> > > MISSING_CASE(INTEL_INFO(i915)->platform);
> > > }
> > > @@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
> > > {
> > > switch (type) {
> > > case L3BANK:
> > > - GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
> > > -
> > > *sliceid = 0; /* unused */
> > > *subsliceid = __ffs(gt->info.l3bank_mask);
> > > break;
> > > case MSLICE:
> > > - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
> > > -
> > > *sliceid = __ffs(gt->info.mslice_mask);
> > > *subsliceid = 0; /* unused */
> > > break;
> > > case LNCF:
> > > - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
> > > -
> > > /*
> > > * An LNCF is always present if its mslice is present, so we
> > > * can safely just steer to LNCF 0 in all cases.
> > > --
> > > 2.32.0
> > >
> >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
@ 2022-05-04 18:17 ` Matt Roper
0 siblings, 0 replies; 18+ messages in thread
From: Matt Roper @ 2022-05-04 18:17 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Jani Nikula, Intel-gfx, dri-devel
On Wed, May 04, 2022 at 06:59:32PM +0100, Tvrtko Ursulin wrote:
>
> On 04/05/2022 17:48, Matt Roper wrote:
> > On Wed, May 04, 2022 at 01:07:14PM +0100, Tvrtko Ursulin wrote:
> > > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > >
> > > DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
> > > to exercise a certain code path, so in case of values coming from MMIO
> > > reads we cannot be sure CI will have all the possible SKUs and parts.
> > >
> > > Use drm_warn instead and move logging to init phase while at it.
> >
> > Changing to drm_warn looks good, although moving the location changes
> > the intent a bit; I think originally the idea was to warn if we were
> > trying to do a steering lookup for a type that we never initialized
> > (e.g., an LNCF lookup for a !HAS_MSLICES platform where we never even
> > read the register in the first place). But I don't think we've ever
> > made a mistake that would cause us to trip the warning, so it probably
> > isn't terribly important to keep it there.
>
> Ah I see.. there we could put something like:
>
> case MSLICE:
> GEM_WARN_ON(!HAS_MSLICES(...));
>
Yeah, that would work for MSLICE and LNCF. Although L3BANK is a bit
stranger since we have multiple platforms that obtain the L3 bank mask
in completely different ways (Xe_HP reads it from XEHP_FUSE4, whereas
gen11/gen12 reads it from GEN10_MIRROR_FUSE3). We want to make sure
there that no matter which branch of init we take, we didn't forget to
initialize l3bank_mask somehow.
Matt
> ?
>
> Regards,
>
> Tvrtko
>
> >
> > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> >
> > >
> > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > ---
> > > drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++++++-------
> > > 1 file changed, 6 insertions(+), 7 deletions(-)
> > >
> > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > index 53307ca0eed0..c474e5c3ea5e 100644
> > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > @@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> > > * An mslice is unavailable only if both the meml3 for the slice is
> > > * disabled *and* all of the DSS in the slice (quadrant) are disabled.
> > > */
> > > - if (HAS_MSLICES(i915))
> > > + if (HAS_MSLICES(i915)) {
> > > gt->info.mslice_mask =
> > > slicemask(gt, GEN_DSS_PER_MSLICE) |
> > > (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> > > GEN12_MEML3_EN_MASK);
> > > + if (!gt->info.mslice_mask) /* should be impossible! */
> > > + drm_warn(&i915->drm, "mslice mask all zero!\n");
> > > + }
> > > if (IS_DG2(i915)) {
> > > gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
> > > @@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> > > gt->info.l3bank_mask =
> > > ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> > > GEN10_L3BANK_MASK;
> > > + if (!gt->info.l3bank_mask) /* should be impossible! */
> > > + drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
> > > } else if (HAS_MSLICES(i915)) {
> > > MISSING_CASE(INTEL_INFO(i915)->platform);
> > > }
> > > @@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
> > > {
> > > switch (type) {
> > > case L3BANK:
> > > - GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
> > > -
> > > *sliceid = 0; /* unused */
> > > *subsliceid = __ffs(gt->info.l3bank_mask);
> > > break;
> > > case MSLICE:
> > > - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
> > > -
> > > *sliceid = __ffs(gt->info.mslice_mask);
> > > *subsliceid = 0; /* unused */
> > > break;
> > > case LNCF:
> > > - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
> > > -
> > > /*
> > > * An LNCF is always present if its mslice is present, so we
> > > * can safely just steer to LNCF 0 in all cases.
> > > --
> > > 2.32.0
> > >
> >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 18+ messages in thread
* [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
2022-05-04 12:07 ` [Intel-gfx] " Tvrtko Ursulin
` (3 preceding siblings ...)
(?)
@ 2022-05-04 20:43 ` Patchwork
-1 siblings, 0 replies; 18+ messages in thread
From: Patchwork @ 2022-05-04 20:43 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 53263 bytes --]
== Series Details ==
Series: series starting with [1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
URL : https://patchwork.freedesktop.org/series/103536/
State : success
== Summary ==
CI Bug Log - changes from CI_DRM_11602_full -> Patchwork_103536v1_full
====================================================
Summary
-------
**SUCCESS**
No regressions found.
Participating hosts (13 -> 13)
------------------------------
No changes in participating hosts
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_103536v1_full:
### IGT changes ###
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@gem_exec_suspend@basic-s3@smem:
- {shard-dg1}: NOTRUN -> [INCOMPLETE][1] +1 similar issue
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-dg1-13/igt@gem_exec_suspend@basic-s3@smem.html
Known issues
------------
Here are the changes found in Patchwork_103536v1_full that come from known issues:
### CI changes ###
#### Issues hit ####
* boot:
- shard-glk: ([PASS][2], [PASS][3], [PASS][4], [PASS][5], [PASS][6], [PASS][7], [PASS][8], [PASS][9], [PASS][10], [PASS][11], [PASS][12], [PASS][13], [PASS][14], [PASS][15], [PASS][16], [PASS][17], [PASS][18], [PASS][19], [PASS][20], [PASS][21], [PASS][22], [PASS][23], [PASS][24], [PASS][25], [PASS][26]) -> ([PASS][27], [PASS][28], [PASS][29], [PASS][30], [PASS][31], [PASS][32], [PASS][33], [PASS][34], [PASS][35], [PASS][36], [PASS][37], [PASS][38], [PASS][39], [PASS][40], [PASS][41], [PASS][42], [PASS][43], [PASS][44], [PASS][45], [PASS][46], [PASS][47], [PASS][48], [FAIL][49], [PASS][50]) ([i915#4392])
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk9/boot.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk9/boot.html
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk9/boot.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk8/boot.html
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk8/boot.html
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk8/boot.html
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk7/boot.html
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk7/boot.html
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk7/boot.html
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk6/boot.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk6/boot.html
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk6/boot.html
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk5/boot.html
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk5/boot.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk5/boot.html
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk4/boot.html
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk4/boot.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk4/boot.html
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk3/boot.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk3/boot.html
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk2/boot.html
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk2/boot.html
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk2/boot.html
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk1/boot.html
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk1/boot.html
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk9/boot.html
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk9/boot.html
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk9/boot.html
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk8/boot.html
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk8/boot.html
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk8/boot.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk7/boot.html
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk7/boot.html
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk6/boot.html
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk6/boot.html
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk6/boot.html
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk5/boot.html
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk5/boot.html
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk4/boot.html
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk4/boot.html
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk4/boot.html
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk4/boot.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk3/boot.html
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk3/boot.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk2/boot.html
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk2/boot.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk1/boot.html
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk1/boot.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk1/boot.html
#### Possible fixes ####
* boot:
- shard-skl: ([PASS][51], [PASS][52], [PASS][53], [PASS][54], [PASS][55], [PASS][56], [PASS][57], [PASS][58], [PASS][59], [PASS][60], [PASS][61], [FAIL][62], [PASS][63], [PASS][64], [PASS][65], [PASS][66], [PASS][67], [PASS][68], [PASS][69], [PASS][70], [PASS][71]) ([i915#5032]) -> ([PASS][72], [PASS][73], [PASS][74], [PASS][75], [PASS][76], [PASS][77], [PASS][78], [PASS][79], [PASS][80], [PASS][81], [PASS][82], [PASS][83], [PASS][84], [PASS][85], [PASS][86], [PASS][87], [PASS][88], [PASS][89], [PASS][90], [PASS][91], [PASS][92], [PASS][93])
[51]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl5/boot.html
[52]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl10/boot.html
[53]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl10/boot.html
[54]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl9/boot.html
[55]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl9/boot.html
[56]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl7/boot.html
[57]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl7/boot.html
[58]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl6/boot.html
[59]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl6/boot.html
[60]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl6/boot.html
[61]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl5/boot.html
[62]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl5/boot.html
[63]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl4/boot.html
[64]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl4/boot.html
[65]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl4/boot.html
[66]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl3/boot.html
[67]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl2/boot.html
[68]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl2/boot.html
[69]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl1/boot.html
[70]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl1/boot.html
[71]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl1/boot.html
[72]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl3/boot.html
[73]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl9/boot.html
[74]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl9/boot.html
[75]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl9/boot.html
[76]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl7/boot.html
[77]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl7/boot.html
[78]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl6/boot.html
[79]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl6/boot.html
[80]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl6/boot.html
[81]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl5/boot.html
[82]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl5/boot.html
[83]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl4/boot.html
[84]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl10/boot.html
[85]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl4/boot.html
[86]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl10/boot.html
[87]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl10/boot.html
[88]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl1/boot.html
[89]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl4/boot.html
[90]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl1/boot.html
[91]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl3/boot.html
[92]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl2/boot.html
[93]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl2/boot.html
- shard-apl: ([PASS][94], [PASS][95], [PASS][96], [PASS][97], [PASS][98], [PASS][99], [PASS][100], [PASS][101], [PASS][102], [PASS][103], [PASS][104], [PASS][105], [PASS][106], [PASS][107], [PASS][108], [PASS][109], [PASS][110], [PASS][111], [PASS][112], [PASS][113], [PASS][114], [FAIL][115], [PASS][116], [PASS][117], [PASS][118]) ([i915#4386]) -> ([PASS][119], [PASS][120], [PASS][121], [PASS][122], [PASS][123], [PASS][124], [PASS][125], [PASS][126], [PASS][127], [PASS][128], [PASS][129], [PASS][130], [PASS][131], [PASS][132], [PASS][133], [PASS][134], [PASS][135], [PASS][136], [PASS][137], [PASS][138], [PASS][139], [PASS][140], [PASS][141], [PASS][142], [PASS][143])
[94]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl8/boot.html
[95]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl8/boot.html
[96]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl8/boot.html
[97]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl8/boot.html
[98]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl7/boot.html
[99]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl7/boot.html
[100]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl7/boot.html
[101]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl7/boot.html
[102]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl6/boot.html
[103]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl6/boot.html
[104]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl6/boot.html
[105]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl4/boot.html
[106]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl4/boot.html
[107]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl4/boot.html
[108]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl3/boot.html
[109]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl3/boot.html
[110]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl3/boot.html
[111]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl3/boot.html
[112]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl2/boot.html
[113]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl2/boot.html
[114]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl1/boot.html
[115]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl1/boot.html
[116]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl1/boot.html
[117]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl1/boot.html
[118]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl1/boot.html
[119]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl7/boot.html
[120]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl7/boot.html
[121]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl7/boot.html
[122]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl8/boot.html
[123]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl8/boot.html
[124]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl8/boot.html
[125]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl1/boot.html
[126]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl1/boot.html
[127]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl1/boot.html
[128]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl1/boot.html
[129]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl1/boot.html
[130]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl1/boot.html
[131]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl2/boot.html
[132]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl2/boot.html
[133]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl2/boot.html
[134]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl2/boot.html
[135]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl3/boot.html
[136]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl3/boot.html
[137]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl4/boot.html
[138]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl4/boot.html
[139]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl4/boot.html
[140]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl4/boot.html
[141]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl6/boot.html
[142]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl6/boot.html
[143]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl6/boot.html
### IGT changes ###
#### Issues hit ####
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-skl: NOTRUN -> [SKIP][144] ([fdo#109271]) +195 similar issues
[144]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl10/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none-share@rcs0:
- shard-glk: [PASS][145] -> [FAIL][146] ([i915#2842])
[145]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk9/igt@gem_exec_fair@basic-none-share@rcs0.html
[146]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk4/igt@gem_exec_fair@basic-none-share@rcs0.html
* igt@gem_exec_fair@basic-none-solo@rcs0:
- shard-apl: [PASS][147] -> [FAIL][148] ([i915#2842]) +1 similar issue
[147]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
[148]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl6/igt@gem_exec_fair@basic-none-solo@rcs0.html
* igt@gem_exec_fair@basic-none-vip@rcs0:
- shard-kbl: [PASS][149] -> [FAIL][150] ([i915#2842])
[149]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-kbl6/igt@gem_exec_fair@basic-none-vip@rcs0.html
[150]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-kbl7/igt@gem_exec_fair@basic-none-vip@rcs0.html
* igt@gem_exec_fair@basic-pace-share@rcs0:
- shard-tglb: [PASS][151] -> [FAIL][152] ([i915#2842]) +1 similar issue
[151]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-tglb2/igt@gem_exec_fair@basic-pace-share@rcs0.html
[152]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-tglb8/igt@gem_exec_fair@basic-pace-share@rcs0.html
* igt@gem_exec_flush@basic-uc-rw-default:
- shard-snb: [PASS][153] -> [SKIP][154] ([fdo#109271]) +1 similar issue
[153]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-snb2/igt@gem_exec_flush@basic-uc-rw-default.html
[154]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-snb6/igt@gem_exec_flush@basic-uc-rw-default.html
* igt@gem_lmem_swapping@heavy-multi:
- shard-iclb: NOTRUN -> [SKIP][155] ([i915#4613])
[155]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@gem_lmem_swapping@heavy-multi.html
* igt@gem_lmem_swapping@heavy-random:
- shard-apl: NOTRUN -> [SKIP][156] ([fdo#109271] / [i915#4613]) +1 similar issue
[156]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl2/igt@gem_lmem_swapping@heavy-random.html
* igt@gem_lmem_swapping@verify-random:
- shard-skl: NOTRUN -> [SKIP][157] ([fdo#109271] / [i915#4613]) +4 similar issues
[157]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl4/igt@gem_lmem_swapping@verify-random.html
* igt@gem_pread@exhaustion:
- shard-apl: NOTRUN -> [WARN][158] ([i915#2658])
[158]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl3/igt@gem_pread@exhaustion.html
* igt@gem_pwrite@basic-exhaustion:
- shard-iclb: NOTRUN -> [WARN][159] ([i915#2658])
[159]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@gem_pwrite@basic-exhaustion.html
* igt@gen9_exec_parse@allowed-all:
- shard-apl: [PASS][160] -> [DMESG-WARN][161] ([i915#5566] / [i915#716])
[160]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl2/igt@gen9_exec_parse@allowed-all.html
[161]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl8/igt@gen9_exec_parse@allowed-all.html
* igt@gen9_exec_parse@batch-zero-length:
- shard-iclb: NOTRUN -> [SKIP][162] ([i915#2856])
[162]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@gen9_exec_parse@batch-zero-length.html
* igt@i915_pm_dc@dc9-dpms:
- shard-iclb: [PASS][163] -> [SKIP][164] ([i915#4281])
[163]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-iclb6/igt@i915_pm_dc@dc9-dpms.html
[164]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb3/igt@i915_pm_dc@dc9-dpms.html
* igt@i915_selftest@live@gt_pm:
- shard-skl: NOTRUN -> [DMESG-FAIL][165] ([i915#1886])
[165]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl10/igt@i915_selftest@live@gt_pm.html
* igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip:
- shard-iclb: NOTRUN -> [SKIP][166] ([i915#5286])
[166]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@kms_big_fb@4-tiled-max-hw-stride-32bpp-rotate-180-async-flip.html
* igt@kms_big_fb@x-tiled-8bpp-rotate-90:
- shard-iclb: NOTRUN -> [SKIP][167] ([fdo#110725] / [fdo#111614]) +1 similar issue
[167]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@kms_big_fb@x-tiled-8bpp-rotate-90.html
* igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-skl: NOTRUN -> [SKIP][168] ([fdo#109271] / [i915#3886]) +8 similar issues
[168]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl7/igt@kms_ccs@pipe-a-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs:
- shard-iclb: NOTRUN -> [SKIP][169] ([fdo#109278] / [i915#3886]) +1 similar issue
[169]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@kms_ccs@pipe-b-random-ccs-data-y_tiled_gen12_mc_ccs.html
* igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc:
- shard-apl: NOTRUN -> [SKIP][170] ([fdo#109271] / [i915#3886]) +5 similar issues
[170]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl8/igt@kms_ccs@pipe-c-ccs-on-another-bo-y_tiled_gen12_rc_ccs_cc.html
* igt@kms_chamelium@vga-hpd-after-suspend:
- shard-skl: NOTRUN -> [SKIP][171] ([fdo#109271] / [fdo#111827]) +14 similar issues
[171]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl7/igt@kms_chamelium@vga-hpd-after-suspend.html
* igt@kms_chamelium@vga-hpd-enable-disable-mode:
- shard-iclb: NOTRUN -> [SKIP][172] ([fdo#109284] / [fdo#111827]) +2 similar issues
[172]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@kms_chamelium@vga-hpd-enable-disable-mode.html
* igt@kms_color_chamelium@pipe-d-ctm-0-25:
- shard-apl: NOTRUN -> [SKIP][173] ([fdo#109271] / [fdo#111827]) +11 similar issues
[173]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl2/igt@kms_color_chamelium@pipe-d-ctm-0-25.html
* igt@kms_color_chamelium@pipe-d-ctm-red-to-blue:
- shard-iclb: NOTRUN -> [SKIP][174] ([fdo#109278] / [fdo#109284] / [fdo#111827])
[174]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@kms_color_chamelium@pipe-d-ctm-red-to-blue.html
* igt@kms_content_protection@legacy:
- shard-iclb: NOTRUN -> [SKIP][175] ([fdo#109300] / [fdo#111066])
[175]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@kms_content_protection@legacy.html
* igt@kms_cursor_crc@pipe-d-cursor-256x85-rapid-movement:
- shard-iclb: NOTRUN -> [SKIP][176] ([fdo#109278]) +9 similar issues
[176]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@kms_cursor_crc@pipe-d-cursor-256x85-rapid-movement.html
* igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions:
- shard-skl: NOTRUN -> [FAIL][177] ([i915#2346])
[177]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl7/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
- shard-glk: [PASS][178] -> [FAIL][179] ([i915#2346])
[178]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk9/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
[179]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk4/igt@kms_cursor_legacy@flip-vs-cursor-atomic-transitions.html
* igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-4tiled:
- shard-iclb: NOTRUN -> [SKIP][180] ([i915#5287]) +1 similar issue
[180]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@kms_draw_crc@draw-method-xrgb2101010-mmap-cpu-4tiled.html
* igt@kms_flip@2x-plain-flip-ts-check-interruptible:
- shard-iclb: NOTRUN -> [SKIP][181] ([fdo#109274])
[181]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@kms_flip@2x-plain-flip-ts-check-interruptible.html
* igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1:
- shard-skl: [PASS][182] -> [FAIL][183] ([i915#79])
[182]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl7/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
[183]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl1/igt@kms_flip@flip-vs-expired-vblank-interruptible@a-edp1.html
* igt@kms_flip@flip-vs-suspend@b-dp1:
- shard-apl: [PASS][184] -> [DMESG-WARN][185] ([i915#180])
[184]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl7/igt@kms_flip@flip-vs-suspend@b-dp1.html
[185]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl6/igt@kms_flip@flip-vs-suspend@b-dp1.html
* igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a1:
- shard-glk: [PASS][186] -> [FAIL][187] ([i915#2122])
[186]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk4/igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a1.html
[187]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk9/igt@kms_flip@plain-flip-fb-recreate@a-hdmi-a1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling:
- shard-skl: NOTRUN -> [SKIP][188] ([fdo#109271] / [i915#3701])
[188]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl7/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-downscaling.html
* igt@kms_frontbuffer_tracking@fbc-tiling-4:
- shard-iclb: NOTRUN -> [SKIP][189] ([i915#5438])
[189]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@kms_frontbuffer_tracking@fbc-tiling-4.html
* igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc:
- shard-iclb: NOTRUN -> [SKIP][190] ([fdo#109280]) +7 similar issues
[190]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@kms_frontbuffer_tracking@fbcpsr-2p-scndscrn-spr-indfb-draw-mmap-wc.html
* igt@kms_pipe_crc_basic@hang-read-crc-pipe-d:
- shard-skl: NOTRUN -> [SKIP][191] ([fdo#109271] / [i915#533])
[191]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl3/igt@kms_pipe_crc_basic@hang-read-crc-pipe-d.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb:
- shard-skl: NOTRUN -> [FAIL][192] ([fdo#108145] / [i915#265])
[192]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl3/igt@kms_plane_alpha_blend@pipe-b-alpha-opaque-fb.html
* igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb:
- shard-apl: NOTRUN -> [FAIL][193] ([i915#265])
[193]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl2/igt@kms_plane_alpha_blend@pipe-b-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb:
- shard-skl: NOTRUN -> [FAIL][194] ([i915#265])
[194]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-alpha-transparent-fb.html
* igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max:
- shard-apl: NOTRUN -> [FAIL][195] ([fdo#108145] / [i915#265])
[195]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl2/igt@kms_plane_alpha_blend@pipe-c-constant-alpha-max.html
* igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale:
- shard-iclb: [PASS][196] -> [SKIP][197] ([i915#5235]) +2 similar issues
[196]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-iclb5/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
[197]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb2/igt@kms_plane_scaling@planes-unity-scaling-downscale-factor-0-5@pipe-a-edp-1-planes-upscale-downscale.html
* igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area:
- shard-apl: NOTRUN -> [SKIP][198] ([fdo#109271] / [i915#658]) +1 similar issue
[198]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl3/igt@kms_psr2_sf@overlay-primary-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-skl: NOTRUN -> [SKIP][199] ([fdo#109271] / [i915#658]) +2 similar issues
[199]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl3/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
* igt@kms_psr2_su@page_flip-nv12:
- shard-iclb: NOTRUN -> [SKIP][200] ([fdo#109642] / [fdo#111068] / [i915#658])
[200]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@kms_psr2_su@page_flip-nv12.html
* igt@kms_psr@psr2_sprite_mmap_cpu:
- shard-iclb: [PASS][201] -> [SKIP][202] ([fdo#109441])
[201]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-iclb2/igt@kms_psr@psr2_sprite_mmap_cpu.html
[202]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb4/igt@kms_psr@psr2_sprite_mmap_cpu.html
* igt@kms_vblank@pipe-d-ts-continuation-idle:
- shard-apl: NOTRUN -> [SKIP][203] ([fdo#109271]) +178 similar issues
[203]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl2/igt@kms_vblank@pipe-d-ts-continuation-idle.html
* igt@nouveau_crc@pipe-a-source-rg:
- shard-iclb: NOTRUN -> [SKIP][204] ([i915#2530])
[204]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@nouveau_crc@pipe-a-source-rg.html
* igt@prime_nv_api@i915_nv_double_export:
- shard-iclb: NOTRUN -> [SKIP][205] ([fdo#109291])
[205]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@prime_nv_api@i915_nv_double_export.html
* igt@sysfs_clients@recycle-many:
- shard-apl: NOTRUN -> [SKIP][206] ([fdo#109271] / [i915#2994]) +1 similar issue
[206]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl3/igt@sysfs_clients@recycle-many.html
* igt@sysfs_clients@sema-10:
- shard-skl: NOTRUN -> [SKIP][207] ([fdo#109271] / [i915#2994]) +2 similar issues
[207]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl7/igt@sysfs_clients@sema-10.html
#### Possible fixes ####
* igt@gem_eio@in-flight-contexts-1us:
- {shard-rkl}: [TIMEOUT][208] ([i915#3063]) -> [PASS][209] +1 similar issue
[208]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-rkl-1/igt@gem_eio@in-flight-contexts-1us.html
[209]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-rkl-4/igt@gem_eio@in-flight-contexts-1us.html
* igt@gem_exec_fair@basic-deadline:
- shard-kbl: [FAIL][210] ([i915#2846]) -> [PASS][211]
[210]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-kbl6/igt@gem_exec_fair@basic-deadline.html
[211]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-kbl4/igt@gem_exec_fair@basic-deadline.html
* igt@gem_exec_fair@basic-flow@rcs0:
- shard-tglb: [FAIL][212] ([i915#2842]) -> [PASS][213]
[212]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
[213]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-tglb6/igt@gem_exec_fair@basic-flow@rcs0.html
* igt@gem_exec_fair@basic-none@vcs0:
- shard-glk: [FAIL][214] ([i915#2842]) -> [PASS][215]
[214]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk9/igt@gem_exec_fair@basic-none@vcs0.html
[215]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk5/igt@gem_exec_fair@basic-none@vcs0.html
* igt@gem_exec_flush@basic-batch-kernel-default-uc:
- shard-snb: [SKIP][216] ([fdo#109271]) -> [PASS][217] +5 similar issues
[216]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-snb6/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
[217]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-snb4/igt@gem_exec_flush@basic-batch-kernel-default-uc.html
* igt@gen9_exec_parse@allowed-single:
- shard-skl: [DMESG-WARN][218] ([i915#5566] / [i915#716]) -> [PASS][219]
[218]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl4/igt@gen9_exec_parse@allowed-single.html
[219]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl2/igt@gen9_exec_parse@allowed-single.html
* igt@i915_pm_rpm@dpms-non-lpsp:
- {shard-dg1}: [SKIP][220] ([i915#1397]) -> [PASS][221]
[220]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-dg1-12/igt@i915_pm_rpm@dpms-non-lpsp.html
[221]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-dg1-18/igt@i915_pm_rpm@dpms-non-lpsp.html
* igt@i915_pm_rps@waitboost:
- {shard-rkl}: [FAIL][222] ([i915#4016]) -> [PASS][223] +1 similar issue
[222]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-rkl-1/igt@i915_pm_rps@waitboost.html
[223]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-rkl-5/igt@i915_pm_rps@waitboost.html
* igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding:
- {shard-rkl}: [SKIP][224] ([fdo#112022] / [i915#4070]) -> [PASS][225] +3 similar issues
[224]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-rkl-1/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
[225]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-rkl-6/igt@kms_cursor_crc@pipe-a-cursor-128x42-sliding.html
* igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge:
- {shard-rkl}: [SKIP][226] ([i915#1849] / [i915#4070] / [i915#4098]) -> [PASS][227]
[226]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-rkl-2/igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge.html
[227]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-rkl-6/igt@kms_cursor_edge_walk@pipe-b-128x128-left-edge.html
* igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size:
- {shard-rkl}: [SKIP][228] ([fdo#111825] / [i915#4070]) -> [PASS][229]
[228]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-rkl-4/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
[229]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-rkl-6/igt@kms_cursor_legacy@basic-flip-before-cursor-varying-size.html
* igt@kms_cursor_legacy@flip-vs-cursor-legacy:
- shard-skl: [FAIL][230] ([i915#2346]) -> [PASS][231]
[230]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl2/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
[231]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl3/igt@kms_cursor_legacy@flip-vs-cursor-legacy.html
* igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled:
- {shard-rkl}: [SKIP][232] ([fdo#111314] / [i915#4098] / [i915#4369]) -> [PASS][233] +1 similar issue
[232]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-rkl-2/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html
[233]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-rkl-6/igt@kms_draw_crc@draw-method-xrgb8888-mmap-wc-untiled.html
* igt@kms_flip@flip-vs-suspend-interruptible@c-dp1:
- shard-apl: [DMESG-WARN][234] ([i915#180]) -> [PASS][235] +4 similar issues
[234]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-apl6/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
[235]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-apl3/igt@kms_flip@flip-vs-suspend-interruptible@c-dp1.html
* igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling:
- {shard-rkl}: [SKIP][236] ([i915#3701]) -> [PASS][237]
[236]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-rkl-2/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
[237]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-rkl-6/igt@kms_flip_scaled_crc@flip-64bpp-ytile-to-16bpp-ytile-upscaling.html
* igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt:
- {shard-rkl}: [SKIP][238] ([i915#1849] / [i915#4098]) -> [PASS][239] +4 similar issues
[238]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-rkl-1/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt.html
[239]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-rkl-6/igt@kms_frontbuffer_tracking@fbcpsr-rgb565-draw-blt.html
* igt@kms_plane_alpha_blend@pipe-c-coverage-7efc:
- shard-skl: [FAIL][240] ([fdo#108145] / [i915#265]) -> [PASS][241]
[240]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl7/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
[241]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl1/igt@kms_plane_alpha_blend@pipe-c-coverage-7efc.html
* igt@kms_plane_cursor@pipe-b-viewport-size-64:
- {shard-rkl}: [SKIP][242] ([i915#1845] / [i915#4098]) -> [PASS][243] +3 similar issues
[242]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-rkl-1/igt@kms_plane_cursor@pipe-b-viewport-size-64.html
[243]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-rkl-6/igt@kms_plane_cursor@pipe-b-viewport-size-64.html
* igt@kms_plane_multiple@atomic-pipe-b-tiling-x:
- {shard-rkl}: [SKIP][244] ([i915#3558] / [i915#4070]) -> [PASS][245]
[244]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-rkl-1/igt@kms_plane_multiple@atomic-pipe-b-tiling-x.html
[245]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-rkl-6/igt@kms_plane_multiple@atomic-pipe-b-tiling-x.html
* igt@kms_psr@psr2_primary_mmap_cpu:
- shard-iclb: [SKIP][246] ([fdo#109441]) -> [PASS][247] +1 similar issue
[246]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-iclb5/igt@kms_psr@psr2_primary_mmap_cpu.html
[247]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb2/igt@kms_psr@psr2_primary_mmap_cpu.html
* igt@kms_universal_plane@universal-plane-pipe-b-sanity:
- {shard-rkl}: [SKIP][248] ([i915#1845] / [i915#4070] / [i915#4098]) -> [PASS][249]
[248]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-rkl-2/igt@kms_universal_plane@universal-plane-pipe-b-sanity.html
[249]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-rkl-6/igt@kms_universal_plane@universal-plane-pipe-b-sanity.html
* igt@perf@enable-disable:
- shard-skl: [FAIL][250] ([i915#1352]) -> [PASS][251]
[250]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-skl4/igt@perf@enable-disable.html
[251]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-skl2/igt@perf@enable-disable.html
#### Warnings ####
* igt@gem_exec_balancer@parallel-bb-first:
- shard-iclb: [SKIP][252] ([i915#4525]) -> [DMESG-WARN][253] ([i915#5614])
[252]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-iclb3/igt@gem_exec_balancer@parallel-bb-first.html
[253]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb1/igt@gem_exec_balancer@parallel-bb-first.html
* igt@gem_exec_balancer@parallel-contexts:
- shard-iclb: [DMESG-WARN][254] ([i915#5614]) -> [SKIP][255] ([i915#4525])
[254]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-iclb4/igt@gem_exec_balancer@parallel-contexts.html
[255]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb6/igt@gem_exec_balancer@parallel-contexts.html
* igt@gem_exec_fair@basic-none-rrul@rcs0:
- shard-iclb: [FAIL][256] ([i915#2842]) -> [FAIL][257] ([i915#2852])
[256]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-iclb1/igt@gem_exec_fair@basic-none-rrul@rcs0.html
[257]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb5/igt@gem_exec_fair@basic-none-rrul@rcs0.html
* igt@i915_pm_dc@dc3co-vpb-simulation:
- shard-iclb: [SKIP][258] ([i915#658]) -> [SKIP][259] ([i915#588])
[258]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-iclb5/igt@i915_pm_dc@dc3co-vpb-simulation.html
[259]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb2/igt@i915_pm_dc@dc3co-vpb-simulation.html
* igt@i915_pm_rc6_residency@rc6-idle:
- shard-iclb: [FAIL][260] ([i915#2680] / [i915#2684]) -> [WARN][261] ([i915#2684])
[260]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-iclb8/igt@i915_pm_rc6_residency@rc6-idle.html
[261]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb7/igt@i915_pm_rc6_residency@rc6-idle.html
* igt@kms_draw_crc@draw-method-rgb565-render-xtiled:
- shard-glk: [FAIL][262] ([i915#5160]) -> [DMESG-FAIL][263] ([i915#118])
[262]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-glk2/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
[263]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-glk6/igt@kms_draw_crc@draw-method-rgb565-render-xtiled.html
* igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][264] ([i915#2920]) -> [SKIP][265] ([fdo#111068] / [i915#658])
[264]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-iclb2/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
[265]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb4/igt@kms_psr2_sf@overlay-plane-update-sf-dmg-area.html
* igt@kms_psr2_sf@primary-plane-update-sf-dmg-area:
- shard-iclb: [SKIP][266] ([fdo#111068] / [i915#658]) -> [SKIP][267] ([i915#2920])
[266]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11602/shard-iclb5/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
[267]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/shard-iclb2/igt@kms_psr2_sf@primary-plane-update-sf-dmg-area.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#103375]: https://bugs.freedesktop.org/show_bug.cgi?id=103375
[fdo#108145]: https://bugs.freedesktop.org/show_bug.cgi?id=108145
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109274]: https://bugs.freedesktop.org/show_bug.cgi?id=109274
[fdo#109278]: https://bugs.freedesktop.org/show_bug.cgi?id=109278
[fdo#109279]: https://bugs.freedesktop.org/show_bug.cgi?id=109279
[fdo#109280]: https://bugs.freedesktop.org/show_bug.cgi?id=109280
[fdo#109283]: https://bugs.freedesktop.org/show_bug.cgi?id=109283
[fdo#109284]: https://bugs.freedesktop.org/show_bug.cgi?id=109284
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#109289]: https://bugs.freedesktop.org/show_bug.cgi?id=109289
[fdo#109291]: https://bugs.freedesktop.org/show_bug.cgi?id=109291
[fdo#109300]: https://bugs.freedesktop.org/show_bug.cgi?id=109300
[fdo#109302]: https://bugs.freedesktop.org/show_bug.cgi?id=109302
[fdo#109303]: https://bugs.freedesktop.org/show_bug.cgi?id=109303
[fdo#109308]: https://bugs.freedesktop.org/show_bug.cgi?id=109308
[fdo#109441]: https://bugs.freedesktop.org/show_bug.cgi?id=109441
[fdo#109506]: https://bugs.freedesktop.org/show_bug.cgi?id=109506
[fdo#109642]: https://bugs.freedesktop.org/show_bug.cgi?id=109642
[fdo#110189]: https://bugs.freedesktop.org/show_bug.cgi?id=110189
[fdo#110254]: https://bugs.freedesktop.org/show_bug.cgi?id=110254
[fdo#110723]: https://bugs.freedesktop.org/show_bug.cgi?id=110723
[fdo#110725]: https://bugs.freedesktop.org/show_bug.cgi?id=110725
[fdo#111066]: https://bugs.freedesktop.org/show_bug.cgi?id=111066
[fdo#111068]: https://bugs.freedesktop.org/show_bug.cgi?id=111068
[fdo#111314]: https://bugs.freedesktop.org/show_bug.cgi?id=111314
[fdo#111614]: https://bugs.freedesktop.org/show_bug.cgi?id=111614
[fdo#111615]: https://bugs.freedesktop.org/show_bug.cgi?id=111615
[fdo#111644]: https://bugs.freedesktop.org/show_bug.cgi?id=111644
[fdo#111825]: https://bugs.freedesktop.org/show_bug.cgi?id=111825
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[fdo#112022]: https://bugs.freedesktop.org/show_bug.cgi?id=112022
[fdo#112054]: https://bugs.freedesktop.org/show_bug.cgi?id=112054
[i915#1063]: https://gitlab.freedesktop.org/drm/intel/issues/1063
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1149]: https://gitlab.freedesktop.org/drm/intel/issues/1149
[i915#118]: https://gitlab.freedesktop.org/drm/intel/issues/118
[i915#132]: https://gitlab.freedesktop.org/drm/intel/issues/132
[i915#1352]: https://gitlab.freedesktop.org/drm/intel/issues/1352
[i915#1397]: https://gitlab.freedesktop.org/drm/intel/issues/1397
[i915#1722]: https://gitlab.freedesktop.org/drm/intel/issues/1722
[i915#1755]: https://gitlab.freedesktop.org/drm/intel/issues/1755
[i915#180]: https://gitlab.freedesktop.org/drm/intel/issues/180
[i915#1825]: https://gitlab.freedesktop.org/drm/intel/issues/1825
[i915#1839]: https://gitlab.freedesktop.org/drm/intel/issues/1839
[i915#1845]: https://gitlab.freedesktop.org/drm/intel/issues/1845
[i915#1849]: https://gitlab.freedesktop.org/drm/intel/issues/1849
[i915#1886]: https://gitlab.freedesktop.org/drm/intel/issues/1886
[i915#1902]: https://gitlab.freedesktop.org/drm/intel/issues/1902
[i915#2122]: https://gitlab.freedesktop.org/drm/intel/issues/2122
[i915#2346]: https://gitlab.freedesktop.org/drm/intel/issues/2346
[i915#2434]: https://gitlab.freedesktop.org/drm/intel/issues/2434
[i915#2437]: https://gitlab.freedesktop.org/drm/intel/issues/2437
[i915#2527]: https://gitlab.freedesktop.org/drm/intel/issues/2527
[i915#2530]: https://gitlab.freedesktop.org/drm/intel/issues/2530
[i915#2582]: https://gitlab.freedesktop.org/drm/intel/issues/2582
[i915#2587]: https://gitlab.freedesktop.org/drm/intel/issues/2587
[i915#265]: https://gitlab.freedesktop.org/drm/intel/issues/265
[i915#2658]: https://gitlab.freedesktop.org/drm/intel/issues/2658
[i915#2680]: https://gitlab.freedesktop.org/drm/intel/issues/2680
[i915#2681]: https://gitlab.freedesktop.org/drm/intel/issues/2681
[i915#2684]: https://gitlab.freedesktop.org/drm/intel/issues/2684
[i915#2705]: https://gitlab.freedesktop.org/drm/intel/issues/2705
[i915#280]: https://gitlab.freedesktop.org/drm/intel/issues/280
[i915#284]: https://gitlab.freedesktop.org/drm/intel/issues/284
[i915#2842]: https://gitlab.freedesktop.org/drm/intel/issues/2842
[i915#2846]: https://gitlab.freedesktop.org/drm/intel/issues/2846
[i915#2849]: https://gitlab.freedesktop.org/drm/intel/issues/2849
[i915#2852]: https://gitlab.freedesktop.org/drm/intel/issues/2852
[i915#2856]: https://gitlab.freedesktop.org/drm/intel/issues/2856
[i915#2920]: https://gitlab.freedesktop.org/drm/intel/issues/2920
[i915#2994]: https://gitlab.freedesktop.org/drm/intel/issues/2994
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3063]: https://gitlab.freedesktop.org/drm/intel/issues/3063
[i915#3116]: https://gitlab.freedesktop.org/drm/intel/issues/3116
[i915#3281]: https://gitlab.freedesktop.org/drm/intel/issues/3281
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3297]: https://gitlab.freedesktop.org/drm/intel/issues/3297
[i915#3299]: https://gitlab.freedesktop.org/drm/intel/issues/3299
[i915#3319]: https://gitlab.freedesktop.org/drm/intel/issues/3319
[i915#3359]: https://gitlab.freedesktop.org/drm/intel/issues/3359
[i915#3371]: https://gitlab.freedesktop.org/drm/intel/issues/3371
[i915#3458]: https://gitlab.freedesktop.org/drm/intel/issues/3458
[i915#3536]: https://gitlab.freedesktop.org/drm/intel/issues/3536
[i915#3539]: https://gitlab.freedesktop.org/drm/intel/issues/3539
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3558]: https://gitlab.freedesktop.org/drm/intel/issues/3558
[i915#3591]: https://gitlab.freedesktop.org/drm/intel/issues/3591
[i915#3637]: https://gitlab.freedesktop.org/drm/intel/issues/3637
[i915#3638]: https://gitlab.freedesktop.org/drm/intel/issues/3638
[i915#3689]: https://gitlab.freedesktop.org/drm/intel/issues/3689
[i915#3701]: https://gitlab.freedesktop.org/drm/intel/issues/3701
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3734]: https://gitlab.freedesktop.org/drm/intel/issues/3734
[i915#3742]: https://gitlab.freedesktop.org/drm/intel/issues/3742
[i915#3826]: https://gitlab.freedesktop.org/drm/intel/issues/3826
[i915#3886]: https://gitlab.freedesktop.org/drm/intel/issues/3886
[i915#3952]: https://gitlab.freedesktop.org/drm/intel/issues/3952
[i915#4016]: https://gitlab.freedesktop.org/drm/intel/issues/4016
[i915#404]: https://gitlab.freedesktop.org/drm/intel/issues/404
[i915#4070]: https://gitlab.freedesktop.org/drm/intel/issues/4070
[i915#4077]: https://gitlab.freedesktop.org/drm/intel/issues/4077
[i915#4083]: https://gitlab.freedesktop.org/drm/intel/issues/4083
[i915#4098]: https://gitlab.freedesktop.org/drm/intel/issues/4098
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4212]: https://gitlab.freedesktop.org/drm/intel/issues/4212
[i915#4215]: https://gitlab.freedesktop.org/drm/intel/issues/4215
[i915#4270]: https://gitlab.freedesktop.org/drm/intel/issues/4270
[i915#4278]: https://gitlab.freedesktop.org/drm/intel/issues/4278
[i915#4281]: https://gitlab.freedesktop.org/drm/intel/issues/4281
[i915#4349]: https://gitlab.freedesktop.org/drm/intel/issues/4349
[i915#4369]: https://gitlab.freedesktop.org/drm/intel/issues/4369
[i915#4386]: https://gitlab.freedesktop.org/drm/intel/issues/4386
[i915#4392]: https://gitlab.freedesktop.org/drm/intel/issues/4392
[i915#4525]: https://gitlab.freedesktop.org/drm/intel/issues/4525
[i915#4538]: https://gitlab.freedesktop.org/drm/intel/issues/4538
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4807]: https://gitlab.freedesktop.org/drm/intel/issues/4807
[i915#4812]: https://gitlab.freedesktop.org/drm/intel/issues/4812
[i915#4833]: https://gitlab.freedesktop.org/drm/intel/issues/4833
[i915#4842]: https://gitlab.freedesktop.org/drm/intel/issues/4842
[i915#4852]: https://gitlab.freedesktop.org/drm/intel/issues/4852
[i915#4853]: https://gitlab.freedesktop.org/drm/intel/issues/4853
[i915#4854]: https://gitlab.freedesktop.org/drm/intel/issues/4854
[i915#4855]: https://gitlab.freedesktop.org/drm/intel/issues/4855
[i915#4860]: https://gitlab.freedesktop.org/drm/intel/issues/4860
[i915#4877]: https://gitlab.freedesktop.org/drm/intel/issues/4877
[i915#4879]: https://gitlab.freedesktop.org/drm/intel/issues/4879
[i915#4893]: https://gitlab.freedesktop.org/drm/intel/issues/4893
[i915#4941]: https://gitlab.freedesktop.org/drm/intel/issues/4941
[i915#5032]: https://gitlab.freedesktop.org/drm/intel/issues/5032
[i915#5076]: https://gitlab.freedesktop.org/drm/intel/issues/5076
[i915#5098]: https://gitlab.freedesktop.org/drm/intel/issues/5098
[i915#5160]: https://gitlab.freedesktop.org/drm/intel/issues/5160
[i915#5235]: https://gitlab.freedesktop.org/drm/intel/issues/5235
[i915#5286]: https://gitlab.freedesktop.org/drm/intel/issues/5286
[i915#5287]: https://gitlab.freedesktop.org/drm/intel/issues/5287
[i915#5288]: https://gitlab.freedesktop.org/drm/intel/issues/5288
[i915#5289]: https://gitlab.freedesktop.org/drm/intel/issues/5289
[i915#5325]: https://gitlab.freedesktop.org/drm/intel/issues/5325
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5438]: https://gitlab.freedesktop.org/drm/intel/issues/5438
[i915#5461]: https://gitlab.freedesktop.org/drm/intel/issues/5461
[i915#5563]: https://gitlab.freedesktop.org/drm/intel/issues/5563
[i915#5566]: https://gitlab.freedesktop.org/drm/intel/issues/5566
[i915#5614]: https://gitlab.freedesktop.org/drm/intel/issues/5614
[i915#5639]: https://gitlab.freedesktop.org/drm/intel/issues/5639
[i915#5691]: https://gitlab.freedesktop.org/drm/intel/issues/5691
[i915#5723]: https://gitlab.freedesktop.org/drm/intel/issues/5723
[i915#5849]: https://gitlab.freedesktop.org/drm/intel/issues/5849
[i915#588]: https://gitlab.freedesktop.org/drm/intel/issues/588
[i915#658]: https://gitlab.freedesktop.org/drm/intel/issues/658
[i915#716]: https://gitlab.freedesktop.org/drm/intel/issues/716
[i915#79]: https://gitlab.freedesktop.org/drm/intel/issues/79
Build changes
-------------
* Linux: CI_DRM_11602 -> Patchwork_103536v1
CI-20190529: 20190529
CI_DRM_11602: 4c7e3b6eee2669c87798d1303bca653b1b26d790 @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6465: f6bb4399881a806fbff75ce3df89b60286d55917 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103536v1: 4c7e3b6eee2669c87798d1303bca653b1b26d790 @ git://anongit.freedesktop.org/gfx-ci/linux
piglit_4509: fdc5a4ca11124ab8413c7988896eec4c97336694 @ git://anongit.freedesktop.org/piglit
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103536v1/index.html
[-- Attachment #2: Type: text/html, Size: 54387 bytes --]
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 2/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for ring unexpectedly not idle
2022-05-04 12:07 ` [Intel-gfx] " Tvrtko Ursulin
@ 2022-05-05 8:02 ` Mika Kuoppala
-1 siblings, 0 replies; 18+ messages in thread
From: Mika Kuoppala @ 2022-05-05 8:02 UTC (permalink / raw)
To: Tvrtko Ursulin, Intel-gfx; +Cc: Jani Nikula, dri-devel, Tvrtko Ursulin
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> writes:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
> to exercise a certain code path, so in case of values coming from MMIO
> reads we cannot be sure CI will have all the possible SKUs and parts, or
> that it will catch all possible error conditions. Use drm_warn instead.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 5423bfd301ad..f8f279a195c0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -117,7 +117,9 @@ static void flush_cs_tlb(struct intel_engine_cs *engine)
> return;
>
> /* ring should be idle before issuing a sync flush*/
> - GEM_DEBUG_WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
> + if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0)
> + drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n",
> + engine->name);
>
> ENGINE_WRITE_FW(engine, RING_INSTPM,
> _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
> --
> 2.32.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 2/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for ring unexpectedly not idle
@ 2022-05-05 8:02 ` Mika Kuoppala
0 siblings, 0 replies; 18+ messages in thread
From: Mika Kuoppala @ 2022-05-05 8:02 UTC (permalink / raw)
To: Tvrtko Ursulin, Intel-gfx; +Cc: Jani Nikula, dri-devel
Tvrtko Ursulin <tvrtko.ursulin@linux.intel.com> writes:
> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>
> DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
> to exercise a certain code path, so in case of values coming from MMIO
> reads we cannot be sure CI will have all the possible SKUs and parts, or
> that it will catch all possible error conditions. Use drm_warn instead.
>
> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> Cc: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> Cc: Jani Nikula <jani.nikula@intel.com>
Reviewed-by: Mika Kuoppala <mika.kuoppala@linux.intel.com>
> ---
> drivers/gpu/drm/i915/gt/intel_ring_submission.c | 4 +++-
> 1 file changed, 3 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/gpu/drm/i915/gt/intel_ring_submission.c b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> index 5423bfd301ad..f8f279a195c0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> +++ b/drivers/gpu/drm/i915/gt/intel_ring_submission.c
> @@ -117,7 +117,9 @@ static void flush_cs_tlb(struct intel_engine_cs *engine)
> return;
>
> /* ring should be idle before issuing a sync flush*/
> - GEM_DEBUG_WARN_ON((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0);
> + if ((ENGINE_READ(engine, RING_MI_MODE) & MODE_IDLE) == 0)
> + drm_warn(&engine->i915->drm, "%s not idle before sync flush!\n",
> + engine->name);
>
> ENGINE_WRITE_FW(engine, RING_INSTPM,
> _MASKED_BIT_ENABLE(INSTPM_TLB_INVALIDATE |
> --
> 2.32.0
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
2022-05-04 18:17 ` [Intel-gfx] " Matt Roper
@ 2022-05-05 11:02 ` Tvrtko Ursulin
-1 siblings, 0 replies; 18+ messages in thread
From: Tvrtko Ursulin @ 2022-05-05 11:02 UTC (permalink / raw)
To: Matt Roper; +Cc: Jani Nikula, Intel-gfx, dri-devel, Tvrtko Ursulin
On 04/05/2022 19:17, Matt Roper wrote:
> On Wed, May 04, 2022 at 06:59:32PM +0100, Tvrtko Ursulin wrote:
>>
>> On 04/05/2022 17:48, Matt Roper wrote:
>>> On Wed, May 04, 2022 at 01:07:14PM +0100, Tvrtko Ursulin wrote:
>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>
>>>> DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
>>>> to exercise a certain code path, so in case of values coming from MMIO
>>>> reads we cannot be sure CI will have all the possible SKUs and parts.
>>>>
>>>> Use drm_warn instead and move logging to init phase while at it.
>>>
>>> Changing to drm_warn looks good, although moving the location changes
>>> the intent a bit; I think originally the idea was to warn if we were
>>> trying to do a steering lookup for a type that we never initialized
>>> (e.g., an LNCF lookup for a !HAS_MSLICES platform where we never even
>>> read the register in the first place). But I don't think we've ever
>>> made a mistake that would cause us to trip the warning, so it probably
>>> isn't terribly important to keep it there.
>>
>> Ah I see.. there we could put something like:
>>
>> case MSLICE:
>> GEM_WARN_ON(!HAS_MSLICES(...));
>>
>
> Yeah, that would work for MSLICE and LNCF. Although L3BANK is a bit
> stranger since we have multiple platforms that obtain the L3 bank mask
> in completely different ways (Xe_HP reads it from XEHP_FUSE4, whereas
> gen11/gen12 reads it from GEN10_MIRROR_FUSE3). We want to make sure
> there that no matter which branch of init we take, we didn't forget to
> initialize l3bank_mask somehow.
The two init paths are not something present in drm-tip at this point,
right? At least I couldn't find it. In which case it could be handled
later by moving the drm_warn to tail of intel_gt_init_mmio, give or take.
Anyway, I've sent v2 out with your r-b and GEM_WARN_ON for mslice/lncf.
I won't merge it though until you definitely are okay with it so please
have a look and confirm.
Regards,
Tvrtko
>
> Matt
>
>> ?
>>
>> Regards,
>>
>> Tvrtko
>>
>>>
>>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>>>
>>>>
>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++++++-------
>>>> 1 file changed, 6 insertions(+), 7 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>>>> index 53307ca0eed0..c474e5c3ea5e 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>>>> @@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
>>>> * An mslice is unavailable only if both the meml3 for the slice is
>>>> * disabled *and* all of the DSS in the slice (quadrant) are disabled.
>>>> */
>>>> - if (HAS_MSLICES(i915))
>>>> + if (HAS_MSLICES(i915)) {
>>>> gt->info.mslice_mask =
>>>> slicemask(gt, GEN_DSS_PER_MSLICE) |
>>>> (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
>>>> GEN12_MEML3_EN_MASK);
>>>> + if (!gt->info.mslice_mask) /* should be impossible! */
>>>> + drm_warn(&i915->drm, "mslice mask all zero!\n");
>>>> + }
>>>> if (IS_DG2(i915)) {
>>>> gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
>>>> @@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
>>>> gt->info.l3bank_mask =
>>>> ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
>>>> GEN10_L3BANK_MASK;
>>>> + if (!gt->info.l3bank_mask) /* should be impossible! */
>>>> + drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
>>>> } else if (HAS_MSLICES(i915)) {
>>>> MISSING_CASE(INTEL_INFO(i915)->platform);
>>>> }
>>>> @@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
>>>> {
>>>> switch (type) {
>>>> case L3BANK:
>>>> - GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
>>>> -
>>>> *sliceid = 0; /* unused */
>>>> *subsliceid = __ffs(gt->info.l3bank_mask);
>>>> break;
>>>> case MSLICE:
>>>> - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
>>>> -
>>>> *sliceid = __ffs(gt->info.mslice_mask);
>>>> *subsliceid = 0; /* unused */
>>>> break;
>>>> case LNCF:
>>>> - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
>>>> -
>>>> /*
>>>> * An LNCF is always present if its mslice is present, so we
>>>> * can safely just steer to LNCF 0 in all cases.
>>>> --
>>>> 2.32.0
>>>>
>>>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
@ 2022-05-05 11:02 ` Tvrtko Ursulin
0 siblings, 0 replies; 18+ messages in thread
From: Tvrtko Ursulin @ 2022-05-05 11:02 UTC (permalink / raw)
To: Matt Roper; +Cc: Jani Nikula, Intel-gfx, dri-devel
On 04/05/2022 19:17, Matt Roper wrote:
> On Wed, May 04, 2022 at 06:59:32PM +0100, Tvrtko Ursulin wrote:
>>
>> On 04/05/2022 17:48, Matt Roper wrote:
>>> On Wed, May 04, 2022 at 01:07:14PM +0100, Tvrtko Ursulin wrote:
>>>> From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>>
>>>> DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
>>>> to exercise a certain code path, so in case of values coming from MMIO
>>>> reads we cannot be sure CI will have all the possible SKUs and parts.
>>>>
>>>> Use drm_warn instead and move logging to init phase while at it.
>>>
>>> Changing to drm_warn looks good, although moving the location changes
>>> the intent a bit; I think originally the idea was to warn if we were
>>> trying to do a steering lookup for a type that we never initialized
>>> (e.g., an LNCF lookup for a !HAS_MSLICES platform where we never even
>>> read the register in the first place). But I don't think we've ever
>>> made a mistake that would cause us to trip the warning, so it probably
>>> isn't terribly important to keep it there.
>>
>> Ah I see.. there we could put something like:
>>
>> case MSLICE:
>> GEM_WARN_ON(!HAS_MSLICES(...));
>>
>
> Yeah, that would work for MSLICE and LNCF. Although L3BANK is a bit
> stranger since we have multiple platforms that obtain the L3 bank mask
> in completely different ways (Xe_HP reads it from XEHP_FUSE4, whereas
> gen11/gen12 reads it from GEN10_MIRROR_FUSE3). We want to make sure
> there that no matter which branch of init we take, we didn't forget to
> initialize l3bank_mask somehow.
The two init paths are not something present in drm-tip at this point,
right? At least I couldn't find it. In which case it could be handled
later by moving the drm_warn to tail of intel_gt_init_mmio, give or take.
Anyway, I've sent v2 out with your r-b and GEM_WARN_ON for mslice/lncf.
I won't merge it though until you definitely are okay with it so please
have a look and confirm.
Regards,
Tvrtko
>
> Matt
>
>> ?
>>
>> Regards,
>>
>> Tvrtko
>>
>>>
>>> Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
>>>
>>>>
>>>> Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
>>>> Cc: Matt Roper <matthew.d.roper@intel.com>
>>>> Cc: Jani Nikula <jani.nikula@intel.com>
>>>> ---
>>>> drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++++++-------
>>>> 1 file changed, 6 insertions(+), 7 deletions(-)
>>>>
>>>> diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
>>>> index 53307ca0eed0..c474e5c3ea5e 100644
>>>> --- a/drivers/gpu/drm/i915/gt/intel_gt.c
>>>> +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
>>>> @@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
>>>> * An mslice is unavailable only if both the meml3 for the slice is
>>>> * disabled *and* all of the DSS in the slice (quadrant) are disabled.
>>>> */
>>>> - if (HAS_MSLICES(i915))
>>>> + if (HAS_MSLICES(i915)) {
>>>> gt->info.mslice_mask =
>>>> slicemask(gt, GEN_DSS_PER_MSLICE) |
>>>> (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
>>>> GEN12_MEML3_EN_MASK);
>>>> + if (!gt->info.mslice_mask) /* should be impossible! */
>>>> + drm_warn(&i915->drm, "mslice mask all zero!\n");
>>>> + }
>>>> if (IS_DG2(i915)) {
>>>> gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
>>>> @@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
>>>> gt->info.l3bank_mask =
>>>> ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
>>>> GEN10_L3BANK_MASK;
>>>> + if (!gt->info.l3bank_mask) /* should be impossible! */
>>>> + drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
>>>> } else if (HAS_MSLICES(i915)) {
>>>> MISSING_CASE(INTEL_INFO(i915)->platform);
>>>> }
>>>> @@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
>>>> {
>>>> switch (type) {
>>>> case L3BANK:
>>>> - GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
>>>> -
>>>> *sliceid = 0; /* unused */
>>>> *subsliceid = __ffs(gt->info.l3bank_mask);
>>>> break;
>>>> case MSLICE:
>>>> - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
>>>> -
>>>> *sliceid = __ffs(gt->info.mslice_mask);
>>>> *subsliceid = 0; /* unused */
>>>> break;
>>>> case LNCF:
>>>> - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
>>>> -
>>>> /*
>>>> * An LNCF is always present if its mslice is present, so we
>>>> * can safely just steer to LNCF 0 in all cases.
>>>> --
>>>> 2.32.0
>>>>
>>>
>
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
2022-05-05 11:02 ` [Intel-gfx] " Tvrtko Ursulin
@ 2022-05-05 16:05 ` Matt Roper
-1 siblings, 0 replies; 18+ messages in thread
From: Matt Roper @ 2022-05-05 16:05 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Jani Nikula, Intel-gfx, dri-devel, Tvrtko Ursulin
On Thu, May 05, 2022 at 12:02:45PM +0100, Tvrtko Ursulin wrote:
>
> On 04/05/2022 19:17, Matt Roper wrote:
> > On Wed, May 04, 2022 at 06:59:32PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 04/05/2022 17:48, Matt Roper wrote:
> > > > On Wed, May 04, 2022 at 01:07:14PM +0100, Tvrtko Ursulin wrote:
> > > > > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > >
> > > > > DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
> > > > > to exercise a certain code path, so in case of values coming from MMIO
> > > > > reads we cannot be sure CI will have all the possible SKUs and parts.
> > > > >
> > > > > Use drm_warn instead and move logging to init phase while at it.
> > > >
> > > > Changing to drm_warn looks good, although moving the location changes
> > > > the intent a bit; I think originally the idea was to warn if we were
> > > > trying to do a steering lookup for a type that we never initialized
> > > > (e.g., an LNCF lookup for a !HAS_MSLICES platform where we never even
> > > > read the register in the first place). But I don't think we've ever
> > > > made a mistake that would cause us to trip the warning, so it probably
> > > > isn't terribly important to keep it there.
> > >
> > > Ah I see.. there we could put something like:
> > >
> > > case MSLICE:
> > > GEM_WARN_ON(!HAS_MSLICES(...));
> > >
> >
> > Yeah, that would work for MSLICE and LNCF. Although L3BANK is a bit
> > stranger since we have multiple platforms that obtain the L3 bank mask
> > in completely different ways (Xe_HP reads it from XEHP_FUSE4, whereas
> > gen11/gen12 reads it from GEN10_MIRROR_FUSE3). We want to make sure
> > there that no matter which branch of init we take, we didn't forget to
> > initialize l3bank_mask somehow.
>
> The two init paths are not something present in drm-tip at this point,
> right? At least I couldn't find it. In which case it could be handled later
> by moving the drm_warn to tail of intel_gt_init_mmio, give or take.
Oh, you're right. The new fuse register actually shows up on a future
platform rather than Xe_HP so the two init paths aren't present yet.
>
> Anyway, I've sent v2 out with your r-b and GEM_WARN_ON for mslice/lncf. I
> won't merge it though until you definitely are okay with it so please have a
> look and confirm.
Yeah, v2 looks fine. Thanks.
Matt
>
> Regards,
>
> Tvrtko
>
>
> >
> > Matt
> >
> > > ?
> > >
> > > Regards,
> > >
> > > Tvrtko
> > >
> > > >
> > > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> > > >
> > > > >
> > > > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++++++-------
> > > > > 1 file changed, 6 insertions(+), 7 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > index 53307ca0eed0..c474e5c3ea5e 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > @@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> > > > > * An mslice is unavailable only if both the meml3 for the slice is
> > > > > * disabled *and* all of the DSS in the slice (quadrant) are disabled.
> > > > > */
> > > > > - if (HAS_MSLICES(i915))
> > > > > + if (HAS_MSLICES(i915)) {
> > > > > gt->info.mslice_mask =
> > > > > slicemask(gt, GEN_DSS_PER_MSLICE) |
> > > > > (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> > > > > GEN12_MEML3_EN_MASK);
> > > > > + if (!gt->info.mslice_mask) /* should be impossible! */
> > > > > + drm_warn(&i915->drm, "mslice mask all zero!\n");
> > > > > + }
> > > > > if (IS_DG2(i915)) {
> > > > > gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
> > > > > @@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> > > > > gt->info.l3bank_mask =
> > > > > ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> > > > > GEN10_L3BANK_MASK;
> > > > > + if (!gt->info.l3bank_mask) /* should be impossible! */
> > > > > + drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
> > > > > } else if (HAS_MSLICES(i915)) {
> > > > > MISSING_CASE(INTEL_INFO(i915)->platform);
> > > > > }
> > > > > @@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
> > > > > {
> > > > > switch (type) {
> > > > > case L3BANK:
> > > > > - GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
> > > > > -
> > > > > *sliceid = 0; /* unused */
> > > > > *subsliceid = __ffs(gt->info.l3bank_mask);
> > > > > break;
> > > > > case MSLICE:
> > > > > - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
> > > > > -
> > > > > *sliceid = __ffs(gt->info.mslice_mask);
> > > > > *subsliceid = 0; /* unused */
> > > > > break;
> > > > > case LNCF:
> > > > > - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
> > > > > -
> > > > > /*
> > > > > * An LNCF is always present if its mslice is present, so we
> > > > > * can safely just steer to LNCF 0 in all cases.
> > > > > --
> > > > > 2.32.0
> > > > >
> > > >
> >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 18+ messages in thread
* Re: [Intel-gfx] [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config
@ 2022-05-05 16:05 ` Matt Roper
0 siblings, 0 replies; 18+ messages in thread
From: Matt Roper @ 2022-05-05 16:05 UTC (permalink / raw)
To: Tvrtko Ursulin; +Cc: Jani Nikula, Intel-gfx, dri-devel
On Thu, May 05, 2022 at 12:02:45PM +0100, Tvrtko Ursulin wrote:
>
> On 04/05/2022 19:17, Matt Roper wrote:
> > On Wed, May 04, 2022 at 06:59:32PM +0100, Tvrtko Ursulin wrote:
> > >
> > > On 04/05/2022 17:48, Matt Roper wrote:
> > > > On Wed, May 04, 2022 at 01:07:14PM +0100, Tvrtko Ursulin wrote:
> > > > > From: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > >
> > > > > DRM_DEBUG_WARN_ON should only be used when we are certain CI is guaranteed
> > > > > to exercise a certain code path, so in case of values coming from MMIO
> > > > > reads we cannot be sure CI will have all the possible SKUs and parts.
> > > > >
> > > > > Use drm_warn instead and move logging to init phase while at it.
> > > >
> > > > Changing to drm_warn looks good, although moving the location changes
> > > > the intent a bit; I think originally the idea was to warn if we were
> > > > trying to do a steering lookup for a type that we never initialized
> > > > (e.g., an LNCF lookup for a !HAS_MSLICES platform where we never even
> > > > read the register in the first place). But I don't think we've ever
> > > > made a mistake that would cause us to trip the warning, so it probably
> > > > isn't terribly important to keep it there.
> > >
> > > Ah I see.. there we could put something like:
> > >
> > > case MSLICE:
> > > GEM_WARN_ON(!HAS_MSLICES(...));
> > >
> >
> > Yeah, that would work for MSLICE and LNCF. Although L3BANK is a bit
> > stranger since we have multiple platforms that obtain the L3 bank mask
> > in completely different ways (Xe_HP reads it from XEHP_FUSE4, whereas
> > gen11/gen12 reads it from GEN10_MIRROR_FUSE3). We want to make sure
> > there that no matter which branch of init we take, we didn't forget to
> > initialize l3bank_mask somehow.
>
> The two init paths are not something present in drm-tip at this point,
> right? At least I couldn't find it. In which case it could be handled later
> by moving the drm_warn to tail of intel_gt_init_mmio, give or take.
Oh, you're right. The new fuse register actually shows up on a future
platform rather than Xe_HP so the two init paths aren't present yet.
>
> Anyway, I've sent v2 out with your r-b and GEM_WARN_ON for mslice/lncf. I
> won't merge it though until you definitely are okay with it so please have a
> look and confirm.
Yeah, v2 looks fine. Thanks.
Matt
>
> Regards,
>
> Tvrtko
>
>
> >
> > Matt
> >
> > > ?
> > >
> > > Regards,
> > >
> > > Tvrtko
> > >
> > > >
> > > > Reviewed-by: Matt Roper <matthew.d.roper@intel.com>
> > > >
> > > > >
> > > > > Signed-off-by: Tvrtko Ursulin <tvrtko.ursulin@intel.com>
> > > > > Cc: Matt Roper <matthew.d.roper@intel.com>
> > > > > Cc: Jani Nikula <jani.nikula@intel.com>
> > > > > ---
> > > > > drivers/gpu/drm/i915/gt/intel_gt.c | 13 ++++++-------
> > > > > 1 file changed, 6 insertions(+), 7 deletions(-)
> > > > >
> > > > > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > index 53307ca0eed0..c474e5c3ea5e 100644
> > > > > --- a/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c
> > > > > @@ -153,11 +153,14 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> > > > > * An mslice is unavailable only if both the meml3 for the slice is
> > > > > * disabled *and* all of the DSS in the slice (quadrant) are disabled.
> > > > > */
> > > > > - if (HAS_MSLICES(i915))
> > > > > + if (HAS_MSLICES(i915)) {
> > > > > gt->info.mslice_mask =
> > > > > slicemask(gt, GEN_DSS_PER_MSLICE) |
> > > > > (intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> > > > > GEN12_MEML3_EN_MASK);
> > > > > + if (!gt->info.mslice_mask) /* should be impossible! */
> > > > > + drm_warn(&i915->drm, "mslice mask all zero!\n");
> > > > > + }
> > > > > if (IS_DG2(i915)) {
> > > > > gt->steering_table[MSLICE] = xehpsdv_mslice_steering_table;
> > > > > @@ -171,6 +174,8 @@ int intel_gt_init_mmio(struct intel_gt *gt)
> > > > > gt->info.l3bank_mask =
> > > > > ~intel_uncore_read(gt->uncore, GEN10_MIRROR_FUSE3) &
> > > > > GEN10_L3BANK_MASK;
> > > > > + if (!gt->info.l3bank_mask) /* should be impossible! */
> > > > > + drm_warn(&i915->drm, "L3 bank mask is all zero!\n");
> > > > > } else if (HAS_MSLICES(i915)) {
> > > > > MISSING_CASE(INTEL_INFO(i915)->platform);
> > > > > }
> > > > > @@ -882,20 +887,14 @@ static void intel_gt_get_valid_steering(struct intel_gt *gt,
> > > > > {
> > > > > switch (type) {
> > > > > case L3BANK:
> > > > > - GEM_DEBUG_WARN_ON(!gt->info.l3bank_mask); /* should be impossible! */
> > > > > -
> > > > > *sliceid = 0; /* unused */
> > > > > *subsliceid = __ffs(gt->info.l3bank_mask);
> > > > > break;
> > > > > case MSLICE:
> > > > > - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
> > > > > -
> > > > > *sliceid = __ffs(gt->info.mslice_mask);
> > > > > *subsliceid = 0; /* unused */
> > > > > break;
> > > > > case LNCF:
> > > > > - GEM_DEBUG_WARN_ON(!gt->info.mslice_mask); /* should be impossible! */
> > > > > -
> > > > > /*
> > > > > * An LNCF is always present if its mslice is present, so we
> > > > > * can safely just steer to LNCF 0 in all cases.
> > > > > --
> > > > > 2.32.0
> > > > >
> > > >
> >
--
Matt Roper
Graphics Software Engineer
VTT-OSGC Platform Enablement
Intel Corporation
(916) 356-2795
^ permalink raw reply [flat|nested] 18+ messages in thread
end of thread, other threads:[~2022-05-05 16:06 UTC | newest]
Thread overview: 18+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-04 12:07 [PATCH 1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config Tvrtko Ursulin
2022-05-04 12:07 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-04 12:07 ` [PATCH 2/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for ring unexpectedly not idle Tvrtko Ursulin
2022-05-04 12:07 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-05 8:02 ` Mika Kuoppala
2022-05-05 8:02 ` [Intel-gfx] " Mika Kuoppala
2022-05-04 13:59 ` [Intel-gfx] ✓ Fi.CI.BAT: success for series starting with [1/2] drm/i915: Don't use DRM_DEBUG_WARN_ON for unexpected l3bank/mslice config Patchwork
2022-05-04 16:48 ` [PATCH 1/2] " Matt Roper
2022-05-04 16:48 ` [Intel-gfx] " Matt Roper
2022-05-04 17:59 ` Tvrtko Ursulin
2022-05-04 17:59 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-04 18:17 ` Matt Roper
2022-05-04 18:17 ` [Intel-gfx] " Matt Roper
2022-05-05 11:02 ` Tvrtko Ursulin
2022-05-05 11:02 ` [Intel-gfx] " Tvrtko Ursulin
2022-05-05 16:05 ` Matt Roper
2022-05-05 16:05 ` [Intel-gfx] " Matt Roper
2022-05-04 20:43 ` [Intel-gfx] ✓ Fi.CI.IGT: success for series starting with [1/2] " Patchwork
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.