From: guoren@kernel.org To: guoren@kernel.org, arnd@arndb.de, palmer@dabbelt.com, mark.rutland@arm.com, will@kernel.org, peterz@infradead.org, boqun.feng@gmail.com, dlustig@nvidia.com, parri.andrea@gmail.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren <guoren@linux.alibaba.com> Subject: [PATCH V4 2/5] riscv: atomic: Optimize dec_if_positive functions Date: Thu, 5 May 2022 11:55:23 +0800 [thread overview] Message-ID: <20220505035526.2974382-3-guoren@kernel.org> (raw) In-Reply-To: <20220505035526.2974382-1-guoren@kernel.org> From: Guo Ren <guoren@linux.alibaba.com> Current implementation wastes another register to pass the argument, but we only need addi to calculate the result. Optimize the code with minimize the usage of registers. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Dan Lustig <dlustig@nvidia.com> Cc: Andrea Parri <parri.andrea@gmail.com> --- arch/riscv/include/asm/atomic.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index ac9bdf4fc404..f3c6a6eac02a 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -310,47 +310,47 @@ ATOMIC_OPS() #undef ATOMIC_OPS #undef ATOMIC_OP -static __always_inline int arch_atomic_sub_if_positive(atomic_t *v, int offset) +static __always_inline int arch_atomic_dec_if_positive(atomic_t *v) { int prev, rc; __asm__ __volatile__ ( "0: lr.w %[p], %[c]\n" - " sub %[rc], %[p], %[o]\n" + " addi %[rc], %[p], -1\n" " bltz %[rc], 1f\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" " fence rw, rw\n" "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) - : [o]"r" (offset) + : : "memory"); - return prev - offset; + return prev - 1; } -#define arch_atomic_dec_if_positive(v) arch_atomic_sub_if_positive(v, 1) +#define arch_atomic_dec_if_positive arch_atomic_dec_if_positive #ifndef CONFIG_GENERIC_ATOMIC64 -static __always_inline s64 arch_atomic64_sub_if_positive(atomic64_t *v, s64 offset) +static __always_inline s64 arch_atomic64_dec_if_positive(atomic64_t *v) { s64 prev; long rc; __asm__ __volatile__ ( "0: lr.d %[p], %[c]\n" - " sub %[rc], %[p], %[o]\n" + " addi %[rc], %[p], -1\n" " bltz %[rc], 1f\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" " fence rw, rw\n" "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) - : [o]"r" (offset) + : : "memory"); - return prev - offset; + return prev - 1; } -#define arch_atomic64_dec_if_positive(v) arch_atomic64_sub_if_positive(v, 1) +#define arch_atomic64_dec_if_positive arch_atomic64_dec_if_positive #endif #endif /* _ASM_RISCV_ATOMIC_H */ -- 2.25.1
WARNING: multiple messages have this Message-ID (diff)
From: guoren@kernel.org To: guoren@kernel.org, arnd@arndb.de, palmer@dabbelt.com, mark.rutland@arm.com, will@kernel.org, peterz@infradead.org, boqun.feng@gmail.com, dlustig@nvidia.com, parri.andrea@gmail.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren <guoren@linux.alibaba.com> Subject: [PATCH V4 2/5] riscv: atomic: Optimize dec_if_positive functions Date: Thu, 5 May 2022 11:55:23 +0800 [thread overview] Message-ID: <20220505035526.2974382-3-guoren@kernel.org> (raw) In-Reply-To: <20220505035526.2974382-1-guoren@kernel.org> From: Guo Ren <guoren@linux.alibaba.com> Current implementation wastes another register to pass the argument, but we only need addi to calculate the result. Optimize the code with minimize the usage of registers. Signed-off-by: Guo Ren <guoren@linux.alibaba.com> Signed-off-by: Guo Ren <guoren@kernel.org> Cc: Palmer Dabbelt <palmer@dabbelt.com> Cc: Mark Rutland <mark.rutland@arm.com> Cc: Dan Lustig <dlustig@nvidia.com> Cc: Andrea Parri <parri.andrea@gmail.com> --- arch/riscv/include/asm/atomic.h | 20 ++++++++++---------- 1 file changed, 10 insertions(+), 10 deletions(-) diff --git a/arch/riscv/include/asm/atomic.h b/arch/riscv/include/asm/atomic.h index ac9bdf4fc404..f3c6a6eac02a 100644 --- a/arch/riscv/include/asm/atomic.h +++ b/arch/riscv/include/asm/atomic.h @@ -310,47 +310,47 @@ ATOMIC_OPS() #undef ATOMIC_OPS #undef ATOMIC_OP -static __always_inline int arch_atomic_sub_if_positive(atomic_t *v, int offset) +static __always_inline int arch_atomic_dec_if_positive(atomic_t *v) { int prev, rc; __asm__ __volatile__ ( "0: lr.w %[p], %[c]\n" - " sub %[rc], %[p], %[o]\n" + " addi %[rc], %[p], -1\n" " bltz %[rc], 1f\n" " sc.w.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" " fence rw, rw\n" "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) - : [o]"r" (offset) + : : "memory"); - return prev - offset; + return prev - 1; } -#define arch_atomic_dec_if_positive(v) arch_atomic_sub_if_positive(v, 1) +#define arch_atomic_dec_if_positive arch_atomic_dec_if_positive #ifndef CONFIG_GENERIC_ATOMIC64 -static __always_inline s64 arch_atomic64_sub_if_positive(atomic64_t *v, s64 offset) +static __always_inline s64 arch_atomic64_dec_if_positive(atomic64_t *v) { s64 prev; long rc; __asm__ __volatile__ ( "0: lr.d %[p], %[c]\n" - " sub %[rc], %[p], %[o]\n" + " addi %[rc], %[p], -1\n" " bltz %[rc], 1f\n" " sc.d.rl %[rc], %[rc], %[c]\n" " bnez %[rc], 0b\n" " fence rw, rw\n" "1:\n" : [p]"=&r" (prev), [rc]"=&r" (rc), [c]"+A" (v->counter) - : [o]"r" (offset) + : : "memory"); - return prev - offset; + return prev - 1; } -#define arch_atomic64_dec_if_positive(v) arch_atomic64_sub_if_positive(v, 1) +#define arch_atomic64_dec_if_positive arch_atomic64_dec_if_positive #endif #endif /* _ASM_RISCV_ATOMIC_H */ -- 2.25.1 _______________________________________________ linux-riscv mailing list linux-riscv@lists.infradead.org http://lists.infradead.org/mailman/listinfo/linux-riscv
next prev parent reply other threads:[~2022-05-05 3:56 UTC|newest] Thread overview: 48+ messages / expand[flat|nested] mbox.gz Atom feed top 2022-05-05 3:55 [PATCH V4 0/5] riscv: Optimize atomic implementation guoren 2022-05-05 3:55 ` guoren 2022-05-05 3:55 ` [PATCH V4 1/5] riscv: atomic: Cleanup unnecessary definition guoren 2022-05-05 3:55 ` guoren 2022-05-05 3:55 ` guoren [this message] 2022-05-05 3:55 ` [PATCH V4 2/5] riscv: atomic: Optimize dec_if_positive functions guoren 2022-05-05 3:55 ` [PATCH V4 3/5] riscv: atomic: Add custom conditional atomic operation implementation guoren 2022-05-05 3:55 ` guoren 2022-05-05 3:55 ` [PATCH V4 4/5] riscv: atomic: Optimize atomic_ops & xchg with .aq/rl annotation guoren 2022-05-05 3:55 ` guoren 2022-05-05 3:55 ` [PATCH V4 5/5] riscv: atomic: Optimize LRSC-pairs atomic ops with .aqrl annotation guoren 2022-05-05 3:55 ` guoren 2022-05-21 20:46 ` Palmer Dabbelt 2022-05-21 20:46 ` Palmer Dabbelt 2022-05-22 13:12 ` Guo Ren 2022-05-22 13:12 ` Guo Ren 2022-06-02 5:59 ` Palmer Dabbelt 2022-06-02 5:59 ` Palmer Dabbelt 2022-06-13 11:49 ` Guo Ren 2022-06-13 11:49 ` Guo Ren 2022-06-14 11:03 ` Andrea Parri 2022-06-14 11:03 ` Andrea Parri 2022-06-23 3:31 ` Boqun Feng 2022-06-23 3:31 ` Boqun Feng 2022-06-23 17:09 ` Dan Lustig 2022-06-23 17:09 ` Dan Lustig 2022-06-23 17:55 ` Boqun Feng 2022-06-23 17:55 ` Boqun Feng 2022-06-23 22:15 ` Palmer Dabbelt 2022-06-23 22:15 ` Palmer Dabbelt 2022-06-24 3:34 ` Guo Ren 2022-06-24 3:34 ` Guo Ren 2022-06-25 5:29 ` Guo Ren 2022-06-25 5:29 ` Guo Ren 2022-07-07 0:03 ` Boqun Feng 2022-07-07 0:03 ` Boqun Feng 2022-07-13 13:38 ` Dan Lustig 2022-07-13 13:38 ` Dan Lustig 2022-07-13 23:34 ` Guo Ren 2022-07-13 23:34 ` Guo Ren 2022-07-13 23:47 ` Guo Ren 2022-07-13 23:47 ` Guo Ren 2022-07-14 13:06 ` Dan Lustig 2022-07-14 13:06 ` Dan Lustig 2022-08-09 7:06 ` Guo Ren 2022-08-09 7:06 ` Guo Ren 2022-06-24 3:28 ` Guo Ren 2022-06-24 3:28 ` Guo Ren
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