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From: Tom Rini <trini@konsulko.com>
To: Sam Shih <sam.shih@mediatek.com>
Cc: Ryder Lee <ryder.lee@mediatek.com>,
	Weijie Gao <weijie.gao@mediatek.com>,
	Chunfeng Yun <chunfeng.yun@mediatek.com>,
	GSS_MTK_Uboot_upstream <GSS_MTK_Uboot_upstream@mediatek.com>,
	u-boot@lists.denx.de
Subject: Re: [PATCH v4 3/3] pinctrl: mediatek: add support for different types of IO pins
Date: Thu, 5 May 2022 14:52:51 -0400	[thread overview]
Message-ID: <20220505185251.GO3580959@bill-the-cat> (raw)
In-Reply-To: <20220421062353.12085-4-sam.shih@mediatek.com>

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On Thu, Apr 21, 2022 at 02:23:53PM +0800, Sam Shih wrote:

> There are many pins in an SoC, and register usage may vary by pins.
> This patch introduces a concept of "io type" and "io type group"
> to mediatek pinctrl drivers. This can provide different pinconf
> handlers implementation (eg: "bias-pull-up/down", "driving" and
> "input-enable") for IO pins that belong to different types.
> 
> Signed-off-by: Sam Shih <sam.shih@mediatek.com>

Applied to u-boot/master, thanks!

-- 
Tom

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      reply	other threads:[~2022-05-05 18:53 UTC|newest]

Thread overview: 7+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-04-21  6:23 [PATCH v4 0/3] Add support for different mediatek pinctrl designs Sam Shih
2022-04-21  6:23 ` [PATCH v4 1/3] pinctrl: mediatek: rewrite mtk_pinconf_set and related functions Sam Shih
2022-05-05 18:52   ` Tom Rini
2022-04-21  6:23 ` [PATCH v4 2/3] pinctrl: mediatek: introduce multiple memory bases support Sam Shih
2022-05-05 18:52   ` Tom Rini
2022-04-21  6:23 ` [PATCH v4 3/3] pinctrl: mediatek: add support for different types of IO pins Sam Shih
2022-05-05 18:52   ` Tom Rini [this message]

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