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From: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
To: Thomas Gleixner <tglx@linutronix.de>, x86@kernel.org
Cc: Tony Luck <tony.luck@intel.com>, Andi Kleen <ak@linux.intel.com>,
	Stephane Eranian <eranian@google.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	Joerg Roedel <joro@8bytes.org>,
	Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>,
	David Woodhouse <dwmw2@infradead.org>,
	Lu Baolu <baolu.lu@linux.intel.com>,
	Nicholas Piggin <npiggin@gmail.com>,
	"Ravi V. Shankar" <ravi.v.shankar@intel.com>,
	Ricardo Neri <ricardo.neri@intel.com>,
	iommu@lists.linux-foundation.org, linuxppc-dev@lists.ozlabs.org,
	linux-kernel@vger.kernel.org,
	Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
Subject: [PATCH v6 03/29] x86/apic/msi: Set the delivery mode individually for each IRQ
Date: Thu,  5 May 2022 16:59:42 -0700	[thread overview]
Message-ID: <20220506000008.30892-4-ricardo.neri-calderon@linux.intel.com> (raw)
In-Reply-To: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com>

There are no restrictions in hardware to set  MSI messages with its
own delivery mode. Use the mode specified in the provided IRQ hardware
configuration data. Since most of the IRQs are configured to use the
delivery mode of the APIC driver in use (set in all of them to
APIC_DELIVERY_MODE_FIXED), the only functional changes are where
IRQs are configured to use a specific delivery mode.

Changing the utility function __irq_msi_compose_msg() takes care of
implementing the change in the in the local APIC, PCI-MSI, and DMAR-MSI
irq_chips.

The IO-APIC irq_chip configures the entries in the interrupt redirection
table using the delivery mode specified in the corresponding MSI message.
Since the MSI message is composed by a higher irq_chip in the hierarchy,
it does not need to be updated.

Cc: Andi Kleen <ak@linux.intel.com>
Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: iommu@lists.linux-foundation.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: x86@kernel.org
Reviewed-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
---
Changes since v5:
 * Introduced this patch

Changes since v4:
 * N/A

Changes since v3:
 * N/A

Changes since v2:
 * N/A

Changes since v1:
 * N/A
---
 arch/x86/kernel/apic/apic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 189d3a5e471a..d1e12da1e9af 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -2528,7 +2528,7 @@ void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
 	msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical;
 	msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF;
 
-	msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED;
+	msg->arch_data.delivery_mode = cfg->delivery_mode;
 	msg->arch_data.vector = cfg->vector;
 
 	msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
-- 
2.17.1


WARNING: multiple messages have this Message-ID (diff)
From: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
To: Thomas Gleixner <tglx@linutronix.de>, x86@kernel.org
Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	linuxppc-dev@lists.ozlabs.org,
	Ricardo Neri <ricardo.neri@intel.com>,
	Stephane Eranian <eranian@google.com>,
	linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
	Tony Luck <tony.luck@intel.com>,
	Nicholas Piggin <npiggin@gmail.com>,
	Ricardo Neri <ricardo.neri-calderon@linux.intel.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	David Woodhouse <dwmw2@infradead.org>
Subject: [PATCH v6 03/29] x86/apic/msi: Set the delivery mode individually for each IRQ
Date: Thu,  5 May 2022 16:59:42 -0700	[thread overview]
Message-ID: <20220506000008.30892-4-ricardo.neri-calderon@linux.intel.com> (raw)
In-Reply-To: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com>

There are no restrictions in hardware to set  MSI messages with its
own delivery mode. Use the mode specified in the provided IRQ hardware
configuration data. Since most of the IRQs are configured to use the
delivery mode of the APIC driver in use (set in all of them to
APIC_DELIVERY_MODE_FIXED), the only functional changes are where
IRQs are configured to use a specific delivery mode.

Changing the utility function __irq_msi_compose_msg() takes care of
implementing the change in the in the local APIC, PCI-MSI, and DMAR-MSI
irq_chips.

The IO-APIC irq_chip configures the entries in the interrupt redirection
table using the delivery mode specified in the corresponding MSI message.
Since the MSI message is composed by a higher irq_chip in the hierarchy,
it does not need to be updated.

Cc: Andi Kleen <ak@linux.intel.com>
Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: iommu@lists.linux-foundation.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: x86@kernel.org
Reviewed-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
---
Changes since v5:
 * Introduced this patch

Changes since v4:
 * N/A

Changes since v3:
 * N/A

Changes since v2:
 * N/A

Changes since v1:
 * N/A
---
 arch/x86/kernel/apic/apic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 189d3a5e471a..d1e12da1e9af 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -2528,7 +2528,7 @@ void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
 	msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical;
 	msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF;
 
-	msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED;
+	msg->arch_data.delivery_mode = cfg->delivery_mode;
 	msg->arch_data.vector = cfg->vector;
 
 	msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
-- 
2.17.1

_______________________________________________
iommu mailing list
iommu@lists.linux-foundation.org
https://lists.linuxfoundation.org/mailman/listinfo/iommu

WARNING: multiple messages have this Message-ID (diff)
From: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
To: Thomas Gleixner <tglx@linutronix.de>, x86@kernel.org
Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com>,
	Andi Kleen <ak@linux.intel.com>,
	linuxppc-dev@lists.ozlabs.org, Joerg Roedel <joro@8bytes.org>,
	Ricardo Neri <ricardo.neri@intel.com>,
	Stephane Eranian <eranian@google.com>,
	linux-kernel@vger.kernel.org, iommu@lists.linux-foundation.org,
	Tony Luck <tony.luck@intel.com>,
	Nicholas Piggin <npiggin@gmail.com>,
	Suravee Suthikulpanit <Suravee.Suthikulpanit@amd.com>,
	Ricardo Neri <ricardo.neri-calderon@linux.intel.com>,
	Andrew Morton <akpm@linux-foundation.org>,
	David Woodhouse <dwmw2@infradead.org>,
	Lu Baolu <baolu.lu@linux.intel.com>
Subject: [PATCH v6 03/29] x86/apic/msi: Set the delivery mode individually for each IRQ
Date: Thu,  5 May 2022 16:59:42 -0700	[thread overview]
Message-ID: <20220506000008.30892-4-ricardo.neri-calderon@linux.intel.com> (raw)
In-Reply-To: <20220506000008.30892-1-ricardo.neri-calderon@linux.intel.com>

There are no restrictions in hardware to set  MSI messages with its
own delivery mode. Use the mode specified in the provided IRQ hardware
configuration data. Since most of the IRQs are configured to use the
delivery mode of the APIC driver in use (set in all of them to
APIC_DELIVERY_MODE_FIXED), the only functional changes are where
IRQs are configured to use a specific delivery mode.

Changing the utility function __irq_msi_compose_msg() takes care of
implementing the change in the in the local APIC, PCI-MSI, and DMAR-MSI
irq_chips.

The IO-APIC irq_chip configures the entries in the interrupt redirection
table using the delivery mode specified in the corresponding MSI message.
Since the MSI message is composed by a higher irq_chip in the hierarchy,
it does not need to be updated.

Cc: Andi Kleen <ak@linux.intel.com>
Cc: "Ravi V. Shankar" <ravi.v.shankar@intel.com>
Cc: Stephane Eranian <eranian@google.com>
Cc: iommu@lists.linux-foundation.org
Cc: linuxppc-dev@lists.ozlabs.org
Cc: x86@kernel.org
Reviewed-by: Tony Luck <tony.luck@intel.com>
Signed-off-by: Ricardo Neri <ricardo.neri-calderon@linux.intel.com>
---
Changes since v5:
 * Introduced this patch

Changes since v4:
 * N/A

Changes since v3:
 * N/A

Changes since v2:
 * N/A

Changes since v1:
 * N/A
---
 arch/x86/kernel/apic/apic.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/kernel/apic/apic.c b/arch/x86/kernel/apic/apic.c
index 189d3a5e471a..d1e12da1e9af 100644
--- a/arch/x86/kernel/apic/apic.c
+++ b/arch/x86/kernel/apic/apic.c
@@ -2528,7 +2528,7 @@ void __irq_msi_compose_msg(struct irq_cfg *cfg, struct msi_msg *msg,
 	msg->arch_addr_lo.dest_mode_logical = apic->dest_mode_logical;
 	msg->arch_addr_lo.destid_0_7 = cfg->dest_apicid & 0xFF;
 
-	msg->arch_data.delivery_mode = APIC_DELIVERY_MODE_FIXED;
+	msg->arch_data.delivery_mode = cfg->delivery_mode;
 	msg->arch_data.vector = cfg->vector;
 
 	msg->address_hi = X86_MSI_BASE_ADDRESS_HIGH;
-- 
2.17.1


  parent reply	other threads:[~2022-05-05 23:58 UTC|newest]

Thread overview: 207+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-05 23:59 [PATCH v6 00/29] x86: Implement an HPET-based hardlockup detector Ricardo Neri
2022-05-05 23:59 ` Ricardo Neri
2022-05-05 23:59 ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 01/29] irq/matrix: Expose functions to allocate the best CPU for new vectors Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-06 19:48   ` Thomas Gleixner
2022-05-06 19:48     ` Thomas Gleixner
2022-05-06 19:48     ` Thomas Gleixner
2022-05-12  0:09     ` Ricardo Neri
2022-05-12  0:09       ` Ricardo Neri
2022-05-12  0:09       ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 02/29] x86/apic: Add irq_cfg::delivery_mode Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-06 19:53   ` Thomas Gleixner
2022-05-06 19:53     ` Thomas Gleixner
2022-05-06 19:53     ` Thomas Gleixner
2022-05-12  0:26     ` Ricardo Neri
2022-05-12  0:26       ` Ricardo Neri
2022-05-12  0:26       ` Ricardo Neri
2022-05-05 23:59 ` Ricardo Neri [this message]
2022-05-05 23:59   ` [PATCH v6 03/29] x86/apic/msi: Set the delivery mode individually for each IRQ Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-06 20:05   ` Thomas Gleixner
2022-05-06 20:05     ` Thomas Gleixner
2022-05-06 20:05     ` Thomas Gleixner
2022-05-12  0:38     ` Ricardo Neri
2022-05-12  0:38       ` Ricardo Neri
2022-05-12  0:38       ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 04/29] x86/apic: Add the X86_IRQ_ALLOC_AS_NMI irq allocation flag Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 05/29] x86/apic/vector: Do not allocate vectors for NMIs Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-06 21:12   ` Thomas Gleixner
2022-05-06 21:12     ` Thomas Gleixner
2022-05-06 21:12     ` Thomas Gleixner
2022-05-13 18:03     ` Ricardo Neri
2022-05-13 18:03       ` Ricardo Neri
2022-05-13 18:03       ` Ricardo Neri
2022-05-13 20:50       ` Thomas Gleixner
2022-05-13 20:50         ` Thomas Gleixner
2022-05-13 20:50         ` Thomas Gleixner
2022-05-13 23:45         ` Ricardo Neri
2022-05-13 23:45           ` Ricardo Neri
2022-05-13 23:45           ` Ricardo Neri
2022-05-14  8:15           ` Thomas Gleixner
2022-05-14  8:15             ` Thomas Gleixner
2022-05-14  8:15             ` Thomas Gleixner
2022-05-05 23:59 ` [PATCH v6 06/29] x86/apic/vector: Implement support for NMI delivery mode Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 07/29] iommu/vt-d: Clear the redirection hint when the destination mode is physical Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 08/29] iommu/vt-d: Rework prepare_irte() to support per-IRQ delivery mode Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 09/29] iommu/vt-d: Set the IRTE delivery mode individually for each IRQ Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 10/29] iommu/vt-d: Implement minor tweaks for NMI irqs Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-06 21:23   ` Thomas Gleixner
2022-05-06 21:23     ` Thomas Gleixner
2022-05-06 21:23     ` Thomas Gleixner
2022-05-13 18:07     ` Ricardo Neri
2022-05-13 18:07       ` Ricardo Neri
2022-05-13 18:07       ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 11/29] iommu/amd: Expose [set|get]_dev_entry_bit() Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 12/29] iommu/amd: Enable NMIPass when allocating an NMI irq Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-06 21:26   ` Thomas Gleixner
2022-05-06 21:26     ` Thomas Gleixner
2022-05-06 21:26     ` Thomas Gleixner
2022-05-13 19:01     ` Ricardo Neri
2022-05-13 19:01       ` Ricardo Neri
2022-05-13 19:01       ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 13/29] iommu/amd: Compose MSI messages for NMI irqs in non-IR format Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-06 21:31   ` Thomas Gleixner
2022-05-06 21:31     ` Thomas Gleixner
2022-05-06 21:31     ` Thomas Gleixner
2022-05-13 19:03     ` Ricardo Neri
2022-05-13 19:03       ` Ricardo Neri
2022-05-13 19:03       ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 14/29] x86/hpet: Expose hpet_writel() in header Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 15/29] x86/hpet: Add helper function hpet_set_comparator_periodic() Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-06 21:41   ` Thomas Gleixner
2022-05-06 21:41     ` Thomas Gleixner
2022-05-06 21:41     ` Thomas Gleixner
2022-05-06 21:51     ` Thomas Gleixner
2022-05-06 21:51       ` Thomas Gleixner
2022-05-06 21:51       ` Thomas Gleixner
2022-05-13 21:29       ` Ricardo Neri
2022-05-13 21:29         ` Ricardo Neri
2022-05-13 21:29         ` Ricardo Neri
2022-05-13 21:19     ` Ricardo Neri
2022-05-13 21:19       ` Ricardo Neri
2022-05-13 21:19       ` Ricardo Neri
2022-05-14  8:17       ` Thomas Gleixner
2022-05-14  8:17         ` Thomas Gleixner
2022-05-14  8:17         ` Thomas Gleixner
2022-05-17 22:54         ` Ricardo Neri
2022-05-17 22:54           ` Ricardo Neri
2022-05-17 22:54           ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 16/29] x86/hpet: Prepare IRQ assignments to use the X86_ALLOC_AS_NMI flag Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 17/29] x86/hpet: Reserve an HPET channel for the hardlockup detector Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 18/29] watchdog/hardlockup: Define a generic function to detect hardlockups Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 19/29] watchdog/hardlockup: Decouple the hardlockup detector from perf Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59 ` [PATCH v6 20/29] init/main: Delay initialization of the lockup detector after smp_init() Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-05 23:59   ` Ricardo Neri
2022-05-10 10:38   ` Nicholas Piggin
2022-05-10 10:38     ` Nicholas Piggin
2022-05-10 10:38     ` Nicholas Piggin
2022-05-13 23:16     ` Ricardo Neri
2022-05-13 23:16       ` Ricardo Neri
2022-05-13 23:16       ` Ricardo Neri
2022-05-20  0:25       ` Nicholas Piggin
2022-05-20  0:25         ` Nicholas Piggin
2022-05-20  0:25         ` Nicholas Piggin
2022-05-06  0:00 ` [PATCH v6 21/29] x86/nmi: Add an NMI_WATCHDOG NMI handler category Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-09 13:59   ` Thomas Gleixner
2022-05-09 13:59     ` Thomas Gleixner
2022-05-09 13:59     ` Thomas Gleixner
2022-05-17 18:41     ` Ricardo Neri
2022-05-17 18:41       ` Ricardo Neri
2022-05-17 18:41       ` Ricardo Neri
2022-05-06  0:00 ` [PATCH v6 22/29] x86/watchdog/hardlockup: Add an HPET-based hardlockup detector Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-09 14:03   ` Thomas Gleixner
2022-05-09 14:03     ` Thomas Gleixner
2022-05-09 14:03     ` Thomas Gleixner
2022-05-13 22:16     ` Ricardo Neri
2022-05-13 22:16       ` Ricardo Neri
2022-05-13 22:16       ` Ricardo Neri
2022-05-14 14:04       ` Thomas Gleixner
2022-05-14 14:04         ` Thomas Gleixner
2022-05-14 14:04         ` Thomas Gleixner
2022-05-06  0:00 ` [PATCH v6 23/29] x86/watchdog/hardlockup/hpet: Determine if HPET timer caused NMI Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-06  0:00 ` [PATCH v6 24/29] watchdog/hardlockup: Use parse_option_str() to handle "nmi_watchdog" Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-10 10:46   ` Nicholas Piggin
2022-05-10 10:46     ` Nicholas Piggin
2022-05-10 10:46     ` Nicholas Piggin
2022-05-13 23:17     ` Ricardo Neri
2022-05-13 23:17       ` Ricardo Neri
2022-05-13 23:17       ` Ricardo Neri
2022-05-06  0:00 ` [PATCH v6 25/29] watchdog/hardlockup/hpet: Only enable the HPET watchdog via a boot parameter Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-06  0:00 ` [PATCH v6 26/29] x86/watchdog: Add a shim hardlockup detector Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-06  0:00 ` [PATCH v6 27/29] watchdog: Expose lockup_detector_reconfigure() Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-06  0:00 ` [PATCH v6 28/29] x86/tsc: Restart NMI watchdog after refining tsc_khz Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-10 11:16   ` Nicholas Piggin
2022-05-10 11:16     ` Nicholas Piggin
2022-05-10 11:16     ` Nicholas Piggin
2022-05-10 11:44     ` Thomas Gleixner
2022-05-10 11:44       ` Thomas Gleixner
2022-05-10 11:44       ` Thomas Gleixner
2022-05-17 22:53       ` Ricardo Neri
2022-05-17 22:53         ` Ricardo Neri
2022-05-17 22:53         ` Ricardo Neri
2022-05-17 22:08     ` Ricardo Neri
2022-05-17 22:08       ` Ricardo Neri
2022-05-17 22:08       ` Ricardo Neri
2022-05-06  0:00 ` [PATCH v6 29/29] x86/tsc: Switch to perf-based hardlockup detector if TSC become unstable Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-06  0:00   ` Ricardo Neri
2022-05-10 12:14   ` Nicholas Piggin
2022-05-10 12:14     ` Nicholas Piggin
2022-05-10 12:14     ` Nicholas Piggin
2022-05-17  3:09     ` Ricardo Neri
2022-05-17  3:09       ` Ricardo Neri
2022-05-17  3:09       ` Ricardo Neri

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