All of lore.kernel.org
 help / color / mirror / Atom feed
From: Conor Dooley <conor.dooley@microchip.com>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@rivosinc.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Cyril Jean <Cyril.Jean@microchip.com>,
	<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <heiko@sntech.de>,
	Arnd Bergmann <arnd@arndb.de>
Subject: [PATCH v5 10/10] riscv: dts: icicle: sort nodes alphabetically
Date: Mon, 9 May 2022 15:26:11 +0100	[thread overview]
Message-ID: <20220509142610.128590-11-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220509142610.128590-1-conor.dooley@microchip.com>

The icicle device tree is in a "random" order, so clean it up and sort
its elements alphabetically to match the newly added PolarBerry dts.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../boot/dts/microchip/mpfs-icicle-kit.dts    | 104 +++++++++---------
 1 file changed, 52 insertions(+), 52 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 9cd1a30edf2c..044982a11df5 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -43,23 +43,57 @@ ddrc_cache_hi: memory@1000000000 {
 	};
 };
 
-&refclk {
-	clock-frequency = <125000000>;
+&core_pwm0 {
+	status = "okay";
 };
 
-&mmuart1 {
+&gpio2 {
+	interrupts = <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>;
 	status = "okay";
 };
 
-&mmuart2 {
+&i2c0 {
 	status = "okay";
 };
 
-&mmuart3 {
+&i2c1 {
 	status = "okay";
 };
 
-&mmuart4 {
+&i2c2 {
+	status = "okay";
+};
+
+&mac0 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy0>;
+	status = "okay";
+};
+
+&mac1 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy1>;
+	status = "okay";
+
+	phy1: ethernet-phy@9 {
+		reg = <9>;
+		ti,fifo-depth = <0x1>;
+	};
+
+	phy0: ethernet-phy@8 {
+		reg = <8>;
+		ti,fifo-depth = <0x1>;
+	};
+};
+
+&mbox {
 	status = "okay";
 };
 
@@ -78,74 +112,43 @@ &mmc {
 	status = "okay";
 };
 
-&spi0 {
-	status = "okay";
-};
-
-&spi1 {
-	status = "okay";
-};
-
-&qspi {
+&mmuart1 {
 	status = "okay";
 };
 
-&i2c0 {
+&mmuart2 {
 	status = "okay";
 };
 
-&i2c1 {
+&mmuart3 {
 	status = "okay";
 };
 
-&i2c2 {
+&mmuart4 {
 	status = "okay";
 };
 
-&mac0 {
-	phy-mode = "sgmii";
-	phy-handle = <&phy0>;
+&pcie {
 	status = "okay";
 };
 
-&mac1 {
-	phy-mode = "sgmii";
-	phy-handle = <&phy1>;
+&qspi {
 	status = "okay";
-
-	phy1: ethernet-phy@9 {
-		reg = <9>;
-		ti,fifo-depth = <0x1>;
-	};
-
-	phy0: ethernet-phy@8 {
-		reg = <8>;
-		ti,fifo-depth = <0x1>;
-	};
 };
 
-&gpio2 {
-	interrupts = <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>;
-	status = "okay";
+&refclk {
+	clock-frequency = <125000000>;
 };
 
 &rtc {
 	status = "okay";
 };
 
-&usb {
+&spi0 {
 	status = "okay";
-	dr_mode = "host";
 };
 
-&mbox {
+&spi1 {
 	status = "okay";
 };
 
@@ -153,10 +156,7 @@ &syscontroller {
 	status = "okay";
 };
 
-&pcie {
-	status = "okay";
-};
-
-&core_pwm0 {
+&usb {
 	status = "okay";
+	dr_mode = "host";
 };
-- 
2.35.2


_______________________________________________
linux-riscv mailing list
linux-riscv@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-riscv

WARNING: multiple messages have this Message-ID (diff)
From: Conor Dooley <conor.dooley@microchip.com>
To: Rob Herring <robh+dt@kernel.org>,
	Krzysztof Kozlowski <krzk+dt@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>
Cc: Paul Walmsley <paul.walmsley@sifive.com>,
	Palmer Dabbelt <palmer@rivosinc.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Conor Dooley <conor.dooley@microchip.com>,
	Daire McNamara <daire.mcnamara@microchip.com>,
	Cyril Jean <Cyril.Jean@microchip.com>,
	<devicetree@vger.kernel.org>, <linux-riscv@lists.infradead.org>,
	<linux-kernel@vger.kernel.org>, <heiko@sntech.de>,
	Arnd Bergmann <arnd@arndb.de>
Subject: [PATCH v5 10/10] riscv: dts: icicle: sort nodes alphabetically
Date: Mon, 9 May 2022 15:26:11 +0100	[thread overview]
Message-ID: <20220509142610.128590-11-conor.dooley@microchip.com> (raw)
In-Reply-To: <20220509142610.128590-1-conor.dooley@microchip.com>

The icicle device tree is in a "random" order, so clean it up and sort
its elements alphabetically to match the newly added PolarBerry dts.

Signed-off-by: Conor Dooley <conor.dooley@microchip.com>
---
 .../boot/dts/microchip/mpfs-icicle-kit.dts    | 104 +++++++++---------
 1 file changed, 52 insertions(+), 52 deletions(-)

diff --git a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
index 9cd1a30edf2c..044982a11df5 100644
--- a/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
+++ b/arch/riscv/boot/dts/microchip/mpfs-icicle-kit.dts
@@ -43,23 +43,57 @@ ddrc_cache_hi: memory@1000000000 {
 	};
 };
 
-&refclk {
-	clock-frequency = <125000000>;
+&core_pwm0 {
+	status = "okay";
 };
 
-&mmuart1 {
+&gpio2 {
+	interrupts = <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>,
+		     <53>, <53>, <53>, <53>;
 	status = "okay";
 };
 
-&mmuart2 {
+&i2c0 {
 	status = "okay";
 };
 
-&mmuart3 {
+&i2c1 {
 	status = "okay";
 };
 
-&mmuart4 {
+&i2c2 {
+	status = "okay";
+};
+
+&mac0 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy0>;
+	status = "okay";
+};
+
+&mac1 {
+	phy-mode = "sgmii";
+	phy-handle = <&phy1>;
+	status = "okay";
+
+	phy1: ethernet-phy@9 {
+		reg = <9>;
+		ti,fifo-depth = <0x1>;
+	};
+
+	phy0: ethernet-phy@8 {
+		reg = <8>;
+		ti,fifo-depth = <0x1>;
+	};
+};
+
+&mbox {
 	status = "okay";
 };
 
@@ -78,74 +112,43 @@ &mmc {
 	status = "okay";
 };
 
-&spi0 {
-	status = "okay";
-};
-
-&spi1 {
-	status = "okay";
-};
-
-&qspi {
+&mmuart1 {
 	status = "okay";
 };
 
-&i2c0 {
+&mmuart2 {
 	status = "okay";
 };
 
-&i2c1 {
+&mmuart3 {
 	status = "okay";
 };
 
-&i2c2 {
+&mmuart4 {
 	status = "okay";
 };
 
-&mac0 {
-	phy-mode = "sgmii";
-	phy-handle = <&phy0>;
+&pcie {
 	status = "okay";
 };
 
-&mac1 {
-	phy-mode = "sgmii";
-	phy-handle = <&phy1>;
+&qspi {
 	status = "okay";
-
-	phy1: ethernet-phy@9 {
-		reg = <9>;
-		ti,fifo-depth = <0x1>;
-	};
-
-	phy0: ethernet-phy@8 {
-		reg = <8>;
-		ti,fifo-depth = <0x1>;
-	};
 };
 
-&gpio2 {
-	interrupts = <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>,
-		     <53>, <53>, <53>, <53>;
-	status = "okay";
+&refclk {
+	clock-frequency = <125000000>;
 };
 
 &rtc {
 	status = "okay";
 };
 
-&usb {
+&spi0 {
 	status = "okay";
-	dr_mode = "host";
 };
 
-&mbox {
+&spi1 {
 	status = "okay";
 };
 
@@ -153,10 +156,7 @@ &syscontroller {
 	status = "okay";
 };
 
-&pcie {
-	status = "okay";
-};
-
-&core_pwm0 {
+&usb {
 	status = "okay";
+	dr_mode = "host";
 };
-- 
2.35.2


  parent reply	other threads:[~2022-05-09 14:27 UTC|newest]

Thread overview: 34+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2022-05-09 14:26 [PATCH v5 00/10] PolarFire SoC dt for 5.19 Conor Dooley
2022-05-09 14:26 ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 01/10] riscv: dts: microchip: remove icicle memory clocks Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 02/10] riscv: dts: microchip: move sysctrlr out of soc bus Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 03/10] riscv: dts: microchip: remove soc vendor from filenames Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 04/10] dt-bindings: riscv: microchip: document icicle reference design Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-11 13:33   ` Rob Herring
2022-05-11 13:33     ` Rob Herring
2022-05-09 14:26 ` [PATCH v5 05/10] riscv: dts: microchip: make the fabric dtsi board specific Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 06/10] dt-bindings: vendor-prefixes: add Sundance DSP Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 07/10] dt-bindings: riscv: microchip: add polarberry compatible string Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 08/10] riscv: dts: microchip: add the sundance polarberry Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-09 14:26 ` [PATCH v5 09/10] riscv: microchip: icicle: readability fixes Conor Dooley
2022-05-09 14:26   ` Conor Dooley
2022-05-15 19:51   ` Heiko Stübner
2022-05-15 19:51     ` Heiko Stübner
2022-05-09 14:26 ` Conor Dooley [this message]
2022-05-09 14:26   ` [PATCH v5 10/10] riscv: dts: icicle: sort nodes alphabetically Conor Dooley
2022-05-15 19:51   ` Heiko Stübner
2022-05-15 19:51     ` Heiko Stübner
2022-05-23 11:47 ` [PATCH v5 00/10] PolarFire SoC dt for 5.19 Conor.Dooley
2022-05-23 11:47   ` Conor.Dooley
2022-06-02  2:07   ` Palmer Dabbelt
2022-06-02  2:07     ` Palmer Dabbelt
2022-06-02  4:39     ` Conor.Dooley
2022-06-02  4:39       ` Conor.Dooley

Reply instructions:

You may reply publicly to this message via plain-text email
using any one of the following methods:

* Save the following mbox file, import it into your mail client,
  and reply-to-all from there: mbox

  Avoid top-posting and favor interleaved quoting:
  https://en.wikipedia.org/wiki/Posting_style#Interleaved_style

* Reply using the --to, --cc, and --in-reply-to
  switches of git-send-email(1):

  git send-email \
    --in-reply-to=20220509142610.128590-11-conor.dooley@microchip.com \
    --to=conor.dooley@microchip.com \
    --cc=Cyril.Jean@microchip.com \
    --cc=aou@eecs.berkeley.edu \
    --cc=arnd@arndb.de \
    --cc=daire.mcnamara@microchip.com \
    --cc=devicetree@vger.kernel.org \
    --cc=heiko@sntech.de \
    --cc=krzk+dt@kernel.org \
    --cc=linux-kernel@vger.kernel.org \
    --cc=linux-riscv@lists.infradead.org \
    --cc=palmer@dabbelt.com \
    --cc=palmer@rivosinc.com \
    --cc=paul.walmsley@sifive.com \
    --cc=robh+dt@kernel.org \
    /path/to/YOUR_REPLY

  https://kernel.org/pub/software/scm/git/docs/git-send-email.html

* If your mail client supports setting the In-Reply-To header
  via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line before the message body. 
This is an external index of several public inboxes,
see mirroring instructions on how to clone and mirror
all data and code used by this external index.