* [PATCH v3 1/5] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC
2022-05-10 9:03 [PATCH v3 0/5] Add Renesas RZ/V2M Ethernet support Phil Edworthy
@ 2022-05-10 9:03 ` Phil Edworthy
2022-05-10 14:27 ` Sergey Shtylyov
2022-05-10 9:03 ` [PATCH v3 2/5] ravb: Separate handling of irq enable/disable regs into feature Phil Edworthy
` (3 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Phil Edworthy @ 2022-05-10 9:03 UTC (permalink / raw)
To: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni,
Rob Herring, Krzysztof Kozlowski
Cc: Phil Edworthy, Geert Uytterhoeven, Sergey Shtylyov,
Sergei Shtylyov, netdev, linux-renesas-soc, devicetree, Biju Das
Document the Ethernet AVB IP found on RZ/V2M SoC.
It includes the Ethernet controller (E-MAC) and Dedicated Direct memory
access controller (DMAC) for transferring transmitted Ethernet frames
to and received Ethernet frames from respective storage areas in the
RAM at high speed.
The AVB-DMAC is compliant with IEEE 802.1BA, IEEE 802.1AS timing and
synchronization protocol, IEEE 802.1Qav real-time transfer, and the
IEEE 802.1Qat stream reservation protocol.
R-Car has a pair of combined interrupt lines:
ch22 = Line0_DiA | Line1_A | Line2_A
ch23 = Line0_DiB | Line1_B | Line2_B
Line0 for descriptor interrupts (which we call dia and dib).
Line1 for error related interrupts (which we call err_a and err_b).
Line2 for management and gPTP related interrupts (mgmt_a and mgmt_b).
RZ/V2M hardware has separate interrupt lines for each of these.
It has 3 clocks; the main AXI clock, the AMBA CHI (Coherent Hub
Interface) clock and a gPTP reference clock.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v3:
- No change
v2:
- Instead of reusing ch22 and ch24 interupt names, use the proper names
---
.../bindings/net/renesas,etheravb.yaml | 82 ++++++++++++++-----
1 file changed, 61 insertions(+), 21 deletions(-)
diff --git a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
index ee2ccacc39ff..acf347f3cdbe 100644
--- a/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
+++ b/Documentation/devicetree/bindings/net/renesas,etheravb.yaml
@@ -43,6 +43,11 @@ properties:
- renesas,etheravb-r8a779a0 # R-Car V3U
- const: renesas,etheravb-rcar-gen3 # R-Car Gen3 and RZ/G2
+ - items:
+ - enum:
+ - renesas,etheravb-r9a09g011 # RZ/V2M
+ - const: renesas,etheravb-rzv2m # RZ/V2M compatible
+
- items:
- enum:
- renesas,r9a07g043-gbeth # RZ/G2UL
@@ -160,16 +165,33 @@ allOf:
- const: arp_ns
rx-internal-delay-ps: false
else:
- properties:
- interrupts:
- minItems: 25
- maxItems: 25
- interrupt-names:
- items:
- pattern: '^ch[0-9]+$'
- required:
- - interrupt-names
- - rx-internal-delay-ps
+ if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,etheravb-rzv2m
+ then:
+ properties:
+ interrupts:
+ minItems: 29
+ maxItems: 29
+ interrupt-names:
+ items:
+ pattern: '^(ch(1?)[0-9])|ch20|ch21|dia|dib|err_a|err_b|mgmt_a|mgmt_b|line3$'
+ rx-internal-delay-ps: false
+ required:
+ - interrupt-names
+ else:
+ properties:
+ interrupts:
+ minItems: 25
+ maxItems: 25
+ interrupt-names:
+ items:
+ pattern: '^ch[0-9]+$'
+ required:
+ - interrupt-names
+ - rx-internal-delay-ps
- if:
properties:
@@ -231,17 +253,35 @@ allOf:
- const: chi
- const: refclk
else:
- properties:
- clocks:
- minItems: 1
- items:
- - description: AVB functional clock
- - description: Optional TXC reference clock
- clock-names:
- minItems: 1
- items:
- - const: fck
- - const: refclk
+ if:
+ properties:
+ compatible:
+ contains:
+ const: renesas,etheravb-rzv2m
+ then:
+ properties:
+ clocks:
+ items:
+ - description: Main clock
+ - description: Coherent Hub Interface clock
+ - description: gPTP reference clock
+ clock-names:
+ items:
+ - const: axi
+ - const: chi
+ - const: gptp
+ else:
+ properties:
+ clocks:
+ minItems: 1
+ items:
+ - description: AVB functional clock
+ - description: Optional TXC reference clock
+ clock-names:
+ minItems: 1
+ items:
+ - const: fck
+ - const: refclk
additionalProperties: false
--
2.32.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 1/5] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC
2022-05-10 9:03 ` [PATCH v3 1/5] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC Phil Edworthy
@ 2022-05-10 14:27 ` Sergey Shtylyov
0 siblings, 0 replies; 11+ messages in thread
From: Sergey Shtylyov @ 2022-05-10 14:27 UTC (permalink / raw)
To: Phil Edworthy, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni, Rob Herring, Krzysztof Kozlowski
Cc: Geert Uytterhoeven, Sergei Shtylyov, netdev, linux-renesas-soc,
devicetree, Biju Das
On 5/10/22 12:03 PM, Phil Edworthy wrote:
> Document the Ethernet AVB IP found on RZ/V2M SoC.
> It includes the Ethernet controller (E-MAC) and Dedicated Direct memory
> access controller (DMAC) for transferring transmitted Ethernet frames
> to and received Ethernet frames from respective storage areas in the
> RAM at high speed.
> The AVB-DMAC is compliant with IEEE 802.1BA, IEEE 802.1AS timing and
> synchronization protocol, IEEE 802.1Qav real-time transfer, and the
> IEEE 802.1Qat stream reservation protocol.
>
> R-Car has a pair of combined interrupt lines:
> ch22 = Line0_DiA | Line1_A | Line2_A
> ch23 = Line0_DiB | Line1_B | Line2_B
> Line0 for descriptor interrupts (which we call dia and dib).
> Line1 for error related interrupts (which we call err_a and err_b).
> Line2 for management and gPTP related interrupts (mgmt_a and mgmt_b).
>
> RZ/V2M hardware has separate interrupt lines for each of these.
>
> It has 3 clocks; the main AXI clock, the AMBA CHI (Coherent Hub
> Interface) clock and a gPTP reference clock.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>
I'm not an expert in the DT bindings, though...
> ---
> v3:
> - No change
> v2:
> - Instead of reusing ch22 and ch24 interupt names, use the proper names
Interrupt. :-)
[...]
MBR, Sergey
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 2/5] ravb: Separate handling of irq enable/disable regs into feature
2022-05-10 9:03 [PATCH v3 0/5] Add Renesas RZ/V2M Ethernet support Phil Edworthy
2022-05-10 9:03 ` [PATCH v3 1/5] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC Phil Edworthy
@ 2022-05-10 9:03 ` Phil Edworthy
2022-05-10 14:05 ` Sergey Shtylyov
2022-05-10 9:03 ` [PATCH v3 3/5] ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs Phil Edworthy
` (2 subsequent siblings)
4 siblings, 1 reply; 11+ messages in thread
From: Phil Edworthy @ 2022-05-10 9:03 UTC (permalink / raw)
To: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni
Cc: Phil Edworthy, Geert Uytterhoeven, Sergey Shtylyov, Biju Das,
Lad Prabhakar, netdev, linux-renesas-soc
Currently, when the HW has a single interrupt, the driver uses the
GIC, TIC, RIC0 registers to enable and disable interrupts.
When the HW has multiple interrupts, it uses the GIE, GID, TIE, TID,
RIE0, RID0 registers.
However, other devices, e.g. RZ/V2M, have multiple irqs and only have
the GIC, TIC, RIC0 registers.
Therefore, split this into a separate feature.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
---
v3:
- Actually renamed irq_en_dis_regs to irq_en_dis this time
- Make ravb_ptp_extts() use irq_en_dis instead of multi_irqs
v2:
- Renamed irq_en_dis_regs to irq_en_dis
- Squashed use of GIC reg versus GIE/GID into this patch and got rid
of separate gptp_ptm_gic feature.
- Minor editing of the commit msg
---
drivers/net/ethernet/renesas/ravb.h | 1 +
drivers/net/ethernet/renesas/ravb_main.c | 5 +++--
drivers/net/ethernet/renesas/ravb_ptp.c | 6 +++---
3 files changed, 7 insertions(+), 5 deletions(-)
diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
index 08062d73df10..bb82efd222c7 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -1027,6 +1027,7 @@ struct ravb_hw_info {
unsigned tx_counters:1; /* E-MAC has TX counters */
unsigned carrier_counters:1; /* E-MAC has carrier counters */
unsigned multi_irqs:1; /* AVB-DMAC and E-MAC has multiple irqs */
+ unsigned irq_en_dis:1; /* Has separate irq enable and disable regs */
unsigned gptp:1; /* AVB-DMAC has gPTP support */
unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in config mode */
unsigned nc_queues:1; /* AVB-DMAC has RX and TX NC queues */
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index 525d66f71f02..e22c0e6ed0f3 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -1124,7 +1124,7 @@ static bool ravb_queue_interrupt(struct net_device *ndev, int q)
if (((ris0 & ric0) & BIT(q)) || ((tis & tic) & BIT(q))) {
if (napi_schedule_prep(&priv->napi[q])) {
/* Mask RX and TX interrupts */
- if (!info->multi_irqs) {
+ if (!info->irq_en_dis) {
ravb_write(ndev, ric0 & ~BIT(q), RIC0);
ravb_write(ndev, tic & ~BIT(q), TIC);
} else {
@@ -1306,7 +1306,7 @@ static int ravb_poll(struct napi_struct *napi, int budget)
/* Re-enable RX/TX interrupts */
spin_lock_irqsave(&priv->lock, flags);
- if (!info->multi_irqs) {
+ if (!info->irq_en_dis) {
ravb_modify(ndev, RIC0, mask, mask);
ravb_modify(ndev, TIC, mask, mask);
} else {
@@ -2410,6 +2410,7 @@ static const struct ravb_hw_info ravb_gen3_hw_info = {
.internal_delay = 1,
.tx_counters = 1,
.multi_irqs = 1,
+ .irq_en_dis = 1,
.ccc_gac = 1,
.nc_queues = 1,
.magic_pkt = 1,
diff --git a/drivers/net/ethernet/renesas/ravb_ptp.c b/drivers/net/ethernet/renesas/ravb_ptp.c
index c099656dd75b..87c4306d66ec 100644
--- a/drivers/net/ethernet/renesas/ravb_ptp.c
+++ b/drivers/net/ethernet/renesas/ravb_ptp.c
@@ -198,7 +198,7 @@ static int ravb_ptp_extts(struct ptp_clock_info *ptp,
priv->ptp.extts[req->index] = on;
spin_lock_irqsave(&priv->lock, flags);
- if (!info->multi_irqs)
+ if (!info->irq_en_dis)
ravb_modify(ndev, GIC, GIC_PTCE, on ? GIC_PTCE : 0);
else if (on)
ravb_write(ndev, GIE_PTCS, GIE);
@@ -254,7 +254,7 @@ static int ravb_ptp_perout(struct ptp_clock_info *ptp,
error = ravb_ptp_update_compare(priv, (u32)start_ns);
if (!error) {
/* Unmask interrupt */
- if (!info->multi_irqs)
+ if (!info->irq_en_dis)
ravb_modify(ndev, GIC, GIC_PTME, GIC_PTME);
else
ravb_write(ndev, GIE_PTMS0, GIE);
@@ -266,7 +266,7 @@ static int ravb_ptp_perout(struct ptp_clock_info *ptp,
perout->period = 0;
/* Mask interrupt */
- if (!info->multi_irqs)
+ if (!info->irq_en_dis)
ravb_modify(ndev, GIC, GIC_PTME, 0);
else
ravb_write(ndev, GID_PTMD0, GID);
--
2.32.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 2/5] ravb: Separate handling of irq enable/disable regs into feature
2022-05-10 9:03 ` [PATCH v3 2/5] ravb: Separate handling of irq enable/disable regs into feature Phil Edworthy
@ 2022-05-10 14:05 ` Sergey Shtylyov
0 siblings, 0 replies; 11+ messages in thread
From: Sergey Shtylyov @ 2022-05-10 14:05 UTC (permalink / raw)
To: Phil Edworthy, David S. Miller, Eric Dumazet, Jakub Kicinski,
Paolo Abeni
Cc: Geert Uytterhoeven, Biju Das, Lad Prabhakar, netdev, linux-renesas-soc
On 5/10/22 12:03 PM, Phil Edworthy wrote:
> Currently, when the HW has a single interrupt, the driver uses the
> GIC, TIC, RIC0 registers to enable and disable interrupts.
> When the HW has multiple interrupts, it uses the GIE, GID, TIE, TID,
> RIE0, RID0 registers.
>
> However, other devices, e.g. RZ/V2M, have multiple irqs and only have
> the GIC, TIC, RIC0 registers.
> Therefore, split this into a separate feature.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>
[...]
MBR, Sergey
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 3/5] ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs
2022-05-10 9:03 [PATCH v3 0/5] Add Renesas RZ/V2M Ethernet support Phil Edworthy
2022-05-10 9:03 ` [PATCH v3 1/5] dt-bindings: net: renesas,etheravb: Document RZ/V2M SoC Phil Edworthy
2022-05-10 9:03 ` [PATCH v3 2/5] ravb: Separate handling of irq enable/disable regs into feature Phil Edworthy
@ 2022-05-10 9:03 ` Phil Edworthy
2022-05-10 9:03 ` [PATCH v3 4/5] ravb: Use separate clock for gPTP Phil Edworthy
2022-05-10 9:03 ` [PATCH v3 5/5] ravb: Add support for RZ/V2M Phil Edworthy
4 siblings, 0 replies; 11+ messages in thread
From: Phil Edworthy @ 2022-05-10 9:03 UTC (permalink / raw)
To: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni
Cc: Phil Edworthy, Geert Uytterhoeven, Sergey Shtylyov, Biju Das,
Lad Prabhakar, netdev, linux-renesas-soc
R-Car has a combined interrupt line, ch22 = Line0_DiA | Line1_A | Line2_A.
RZ/V2M has separate interrupt lines for each of these, so add a feature
that allows the driver to get these interrupts and call the common handler.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>
---
v3:
- Added Reviewed-by tags
v2:
- Move err_mgmt_irqs code under multi_irqs
- Use dia, line3 irq names instead of ch22, ch24 when using err_mgmt_irqs
---
drivers/net/ethernet/renesas/ravb.h | 3 ++
drivers/net/ethernet/renesas/ravb_main.c | 56 +++++++++++++++++++++---
2 files changed, 53 insertions(+), 6 deletions(-)
diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
index bb82efd222c7..e505e8088445 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -1028,6 +1028,7 @@ struct ravb_hw_info {
unsigned carrier_counters:1; /* E-MAC has carrier counters */
unsigned multi_irqs:1; /* AVB-DMAC and E-MAC has multiple irqs */
unsigned irq_en_dis:1; /* Has separate irq enable and disable regs */
+ unsigned err_mgmt_irqs:1; /* Line1 (Err) and Line2 (Mgmt) irqs are separate */
unsigned gptp:1; /* AVB-DMAC has gPTP support */
unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in config mode */
unsigned nc_queues:1; /* AVB-DMAC has RX and TX NC queues */
@@ -1078,6 +1079,8 @@ struct ravb_private {
int msg_enable;
int speed;
int emac_irq;
+ int erra_irq;
+ int mgmta_irq;
int rx_irqs[NUM_RX_QUEUE];
int tx_irqs[NUM_TX_QUEUE];
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index e22c0e6ed0f3..8ccc817b8b5d 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -1798,12 +1798,23 @@ static int ravb_open(struct net_device *ndev)
ndev, dev, "ch19:tx_nc");
if (error)
goto out_free_irq_nc_rx;
+
+ if (info->err_mgmt_irqs) {
+ error = ravb_hook_irq(priv->erra_irq, ravb_multi_interrupt,
+ ndev, dev, "err_a");
+ if (error)
+ goto out_free_irq_nc_tx;
+ error = ravb_hook_irq(priv->mgmta_irq, ravb_multi_interrupt,
+ ndev, dev, "mgmt_a");
+ if (error)
+ goto out_free_irq_erra;
+ }
}
/* Device init */
error = ravb_dmac_init(ndev);
if (error)
- goto out_free_irq_nc_tx;
+ goto out_free_irq_mgmta;
ravb_emac_init(ndev);
/* Initialise PTP Clock driver */
@@ -1823,9 +1834,15 @@ static int ravb_open(struct net_device *ndev)
/* Stop PTP Clock driver */
if (info->gptp)
ravb_ptp_stop(ndev);
-out_free_irq_nc_tx:
+out_free_irq_mgmta:
if (!info->multi_irqs)
goto out_free_irq;
+ if (info->err_mgmt_irqs)
+ free_irq(priv->mgmta_irq, ndev);
+out_free_irq_erra:
+ if (info->err_mgmt_irqs)
+ free_irq(priv->erra_irq, ndev);
+out_free_irq_nc_tx:
free_irq(priv->tx_irqs[RAVB_NC], ndev);
out_free_irq_nc_rx:
free_irq(priv->rx_irqs[RAVB_NC], ndev);
@@ -2166,6 +2183,10 @@ static int ravb_close(struct net_device *ndev)
free_irq(priv->tx_irqs[RAVB_BE], ndev);
free_irq(priv->rx_irqs[RAVB_BE], ndev);
free_irq(priv->emac_irq, ndev);
+ if (info->err_mgmt_irqs) {
+ free_irq(priv->erra_irq, ndev);
+ free_irq(priv->mgmta_irq, ndev);
+ }
}
free_irq(ndev->irq, ndev);
@@ -2595,10 +2616,14 @@ static int ravb_probe(struct platform_device *pdev)
pm_runtime_enable(&pdev->dev);
pm_runtime_get_sync(&pdev->dev);
- if (info->multi_irqs)
- irq = platform_get_irq_byname(pdev, "ch22");
- else
+ if (info->multi_irqs) {
+ if (info->err_mgmt_irqs)
+ irq = platform_get_irq_byname(pdev, "dia");
+ else
+ irq = platform_get_irq_byname(pdev, "ch22");
+ } else {
irq = platform_get_irq(pdev, 0);
+ }
if (irq < 0) {
error = irq;
goto out_release;
@@ -2640,7 +2665,10 @@ static int ravb_probe(struct platform_device *pdev)
of_property_read_bool(np, "renesas,ether-link-active-low");
if (info->multi_irqs) {
- irq = platform_get_irq_byname(pdev, "ch24");
+ if (info->err_mgmt_irqs)
+ irq = platform_get_irq_byname(pdev, "line3");
+ else
+ irq = platform_get_irq_byname(pdev, "ch24");
if (irq < 0) {
error = irq;
goto out_release;
@@ -2662,6 +2690,22 @@ static int ravb_probe(struct platform_device *pdev)
}
priv->tx_irqs[i] = irq;
}
+
+ if (info->err_mgmt_irqs) {
+ irq = platform_get_irq_byname(pdev, "err_a");
+ if (irq < 0) {
+ error = irq;
+ goto out_release;
+ }
+ priv->erra_irq = irq;
+
+ irq = platform_get_irq_byname(pdev, "mgmt_a");
+ if (irq < 0) {
+ error = irq;
+ goto out_release;
+ }
+ priv->mgmta_irq = irq;
+ }
}
priv->clk = devm_clk_get(&pdev->dev, NULL);
--
2.32.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* [PATCH v3 4/5] ravb: Use separate clock for gPTP
2022-05-10 9:03 [PATCH v3 0/5] Add Renesas RZ/V2M Ethernet support Phil Edworthy
` (2 preceding siblings ...)
2022-05-10 9:03 ` [PATCH v3 3/5] ravb: Support separate Line0 (Desc), Line1 (Err) and Line2 (Mgmt) irqs Phil Edworthy
@ 2022-05-10 9:03 ` Phil Edworthy
2022-05-12 7:02 ` Paolo Abeni
2022-05-10 9:03 ` [PATCH v3 5/5] ravb: Add support for RZ/V2M Phil Edworthy
4 siblings, 1 reply; 11+ messages in thread
From: Phil Edworthy @ 2022-05-10 9:03 UTC (permalink / raw)
To: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni
Cc: Phil Edworthy, Geert Uytterhoeven, Sergey Shtylyov, Biju Das,
Lad Prabhakar, netdev, linux-renesas-soc
RZ/V2M has a separate gPTP reference clock that is used when the
AVB-DMAC Mode Register (CCC) gPTP Clock Select (CSEL) bits are
set to "01: High-speed peripheral bus clock".
Therefore, add a feature that allows this clock to be used for
gPTP.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>
---
v3:
- No change
v2:
- Added Reviewed-by tags
---
drivers/net/ethernet/renesas/ravb.h | 2 ++
drivers/net/ethernet/renesas/ravb_main.c | 15 ++++++++++++++-
2 files changed, 16 insertions(+), 1 deletion(-)
diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
index e505e8088445..b980bce763d3 100644
--- a/drivers/net/ethernet/renesas/ravb.h
+++ b/drivers/net/ethernet/renesas/ravb.h
@@ -1031,6 +1031,7 @@ struct ravb_hw_info {
unsigned err_mgmt_irqs:1; /* Line1 (Err) and Line2 (Mgmt) irqs are separate */
unsigned gptp:1; /* AVB-DMAC has gPTP support */
unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in config mode */
+ unsigned gptp_ref_clk:1; /* gPTP has separate reference clock */
unsigned nc_queues:1; /* AVB-DMAC has RX and TX NC queues */
unsigned magic_pkt:1; /* E-MAC supports magic packet detection */
unsigned half_duplex:1; /* E-MAC supports half duplex mode */
@@ -1042,6 +1043,7 @@ struct ravb_private {
void __iomem *addr;
struct clk *clk;
struct clk *refclk;
+ struct clk *gptp_clk;
struct mdiobb_ctrl mdiobb;
u32 num_rx_ring[NUM_RX_QUEUE];
u32 num_tx_ring[NUM_TX_QUEUE];
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index 8ccc817b8b5d..ef6967731263 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -2495,11 +2495,15 @@ MODULE_DEVICE_TABLE(of, ravb_match_table);
static int ravb_set_gti(struct net_device *ndev)
{
struct ravb_private *priv = netdev_priv(ndev);
+ const struct ravb_hw_info *info = priv->info;
struct device *dev = ndev->dev.parent;
unsigned long rate;
uint64_t inc;
- rate = clk_get_rate(priv->clk);
+ if (info->gptp_ref_clk)
+ rate = clk_get_rate(priv->gptp_clk);
+ else
+ rate = clk_get_rate(priv->clk);
if (!rate)
return -EINVAL;
@@ -2721,6 +2725,15 @@ static int ravb_probe(struct platform_device *pdev)
}
clk_prepare_enable(priv->refclk);
+ if (info->gptp_ref_clk) {
+ priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp");
+ if (IS_ERR(priv->gptp_clk)) {
+ error = PTR_ERR(priv->gptp_clk);
+ goto out_release;
+ }
+ clk_prepare_enable(priv->gptp_clk);
+ }
+
ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
ndev->min_mtu = ETH_MIN_MTU;
--
2.32.0
^ permalink raw reply related [flat|nested] 11+ messages in thread* Re: [PATCH v3 4/5] ravb: Use separate clock for gPTP
2022-05-10 9:03 ` [PATCH v3 4/5] ravb: Use separate clock for gPTP Phil Edworthy
@ 2022-05-12 7:02 ` Paolo Abeni
2022-05-12 7:59 ` Sergey Shtylyov
2022-05-12 10:12 ` Phil Edworthy
0 siblings, 2 replies; 11+ messages in thread
From: Paolo Abeni @ 2022-05-12 7:02 UTC (permalink / raw)
To: Phil Edworthy, David S. Miller, Eric Dumazet, Jakub Kicinski
Cc: Geert Uytterhoeven, Sergey Shtylyov, Biju Das, Lad Prabhakar,
netdev, linux-renesas-soc
On Tue, 2022-05-10 at 10:03 +0100, Phil Edworthy wrote:
> RZ/V2M has a separate gPTP reference clock that is used when the
> AVB-DMAC Mode Register (CCC) gPTP Clock Select (CSEL) bits are
> set to "01: High-speed peripheral bus clock".
> Therefore, add a feature that allows this clock to be used for
> gPTP.
>
> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>
> ---
> v3:
> - No change
> v2:
> - Added Reviewed-by tags
> ---
> drivers/net/ethernet/renesas/ravb.h | 2 ++
> drivers/net/ethernet/renesas/ravb_main.c | 15 ++++++++++++++-
> 2 files changed, 16 insertions(+), 1 deletion(-)
>
> diff --git a/drivers/net/ethernet/renesas/ravb.h b/drivers/net/ethernet/renesas/ravb.h
> index e505e8088445..b980bce763d3 100644
> --- a/drivers/net/ethernet/renesas/ravb.h
> +++ b/drivers/net/ethernet/renesas/ravb.h
> @@ -1031,6 +1031,7 @@ struct ravb_hw_info {
> unsigned err_mgmt_irqs:1; /* Line1 (Err) and Line2 (Mgmt) irqs are separate */
> unsigned gptp:1; /* AVB-DMAC has gPTP support */
> unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in config mode */
> + unsigned gptp_ref_clk:1; /* gPTP has separate reference clock */
> unsigned nc_queues:1; /* AVB-DMAC has RX and TX NC queues */
> unsigned magic_pkt:1; /* E-MAC supports magic packet detection */
> unsigned half_duplex:1; /* E-MAC supports half duplex mode */
> @@ -1042,6 +1043,7 @@ struct ravb_private {
> void __iomem *addr;
> struct clk *clk;
> struct clk *refclk;
> + struct clk *gptp_clk;
> struct mdiobb_ctrl mdiobb;
> u32 num_rx_ring[NUM_RX_QUEUE];
> u32 num_tx_ring[NUM_TX_QUEUE];
> diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
> index 8ccc817b8b5d..ef6967731263 100644
> --- a/drivers/net/ethernet/renesas/ravb_main.c
> +++ b/drivers/net/ethernet/renesas/ravb_main.c
> @@ -2495,11 +2495,15 @@ MODULE_DEVICE_TABLE(of, ravb_match_table);
> static int ravb_set_gti(struct net_device *ndev)
> {
> struct ravb_private *priv = netdev_priv(ndev);
> + const struct ravb_hw_info *info = priv->info;
> struct device *dev = ndev->dev.parent;
> unsigned long rate;
> uint64_t inc;
>
> - rate = clk_get_rate(priv->clk);
> + if (info->gptp_ref_clk)
> + rate = clk_get_rate(priv->gptp_clk);
> + else
> + rate = clk_get_rate(priv->clk);
> if (!rate)
> return -EINVAL;
>
> @@ -2721,6 +2725,15 @@ static int ravb_probe(struct platform_device *pdev)
> }
> clk_prepare_enable(priv->refclk);
>
> + if (info->gptp_ref_clk) {
> + priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp");
> + if (IS_ERR(priv->gptp_clk)) {
> + error = PTR_ERR(priv->gptp_clk);
> + goto out_release;
> + }
> + clk_prepare_enable(priv->gptp_clk);
> + }
> +
I guess you need to a conditional
clk_disable_unprepare(info->gptp_ref_clk)
in the error path? And even in ravb_remove()?
> ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN + ETH_FCS_LEN);
> ndev->min_mtu = ETH_MIN_MTU;
>
^ permalink raw reply [flat|nested] 11+ messages in thread* Re: [PATCH v3 4/5] ravb: Use separate clock for gPTP
2022-05-12 7:02 ` Paolo Abeni
@ 2022-05-12 7:59 ` Sergey Shtylyov
2022-05-12 10:12 ` Phil Edworthy
1 sibling, 0 replies; 11+ messages in thread
From: Sergey Shtylyov @ 2022-05-12 7:59 UTC (permalink / raw)
To: Paolo Abeni, Phil Edworthy, David S. Miller, Eric Dumazet,
Jakub Kicinski
Cc: Geert Uytterhoeven, Biju Das, Lad Prabhakar, netdev, linux-renesas-soc
On 5/12/22 10:02 AM, Paolo Abeni wrote:
>> RZ/V2M has a separate gPTP reference clock that is used when the
>> AVB-DMAC Mode Register (CCC) gPTP Clock Select (CSEL) bits are
>> set to "01: High-speed peripheral bus clock".
>> Therefore, add a feature that allows this clock to be used for
>> gPTP.
>>
>> Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
>> Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
>> Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>
[...]
>> diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
>> index 8ccc817b8b5d..ef6967731263 100644
>> --- a/drivers/net/ethernet/renesas/ravb_main.c
>> +++ b/drivers/net/ethernet/renesas/ravb_main.c
[...]
>> @@ -2721,6 +2725,15 @@ static int ravb_probe(struct platform_device *pdev)
>> }
>> clk_prepare_enable(priv->refclk);
>>
>> + if (info->gptp_ref_clk) {
>> + priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp");
>> + if (IS_ERR(priv->gptp_clk)) {
>> + error = PTR_ERR(priv->gptp_clk);
>> + goto out_release;
>> + }
>> + clk_prepare_enable(priv->gptp_clk);
>> + }
>> +
>
> I guess you need to a conditional
>
> clk_disable_unprepare(info->gptp_ref_clk)
>
> in the error path? And even in ravb_remove()?
Indeed! How could I miss it? :-/
[...]
MBR, Sergey
^ permalink raw reply [flat|nested] 11+ messages in thread* RE: [PATCH v3 4/5] ravb: Use separate clock for gPTP
2022-05-12 7:02 ` Paolo Abeni
2022-05-12 7:59 ` Sergey Shtylyov
@ 2022-05-12 10:12 ` Phil Edworthy
1 sibling, 0 replies; 11+ messages in thread
From: Phil Edworthy @ 2022-05-12 10:12 UTC (permalink / raw)
To: Paolo Abeni, David S. Miller, Eric Dumazet, Jakub Kicinski
Cc: Geert Uytterhoeven, Sergey Shtylyov, Biju Das,
Prabhakar Mahadev Lad, netdev, linux-renesas-soc
Hi Paolo,
On 12 May 2022 08:03 Paolo Abeni wrote:
> On Tue, 2022-05-10 at 10:03 +0100, Phil Edworthy wrote:
> > RZ/V2M has a separate gPTP reference clock that is used when the
> > AVB-DMAC Mode Register (CCC) gPTP Clock Select (CSEL) bits are set to
> > "01: High-speed peripheral bus clock".
> > Therefore, add a feature that allows this clock to be used for gPTP.
> >
> > Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
> > Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
> > Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>
> > ---
> > v3:
> > - No change
> > v2:
> > - Added Reviewed-by tags
> > ---
> > drivers/net/ethernet/renesas/ravb.h | 2 ++
> > drivers/net/ethernet/renesas/ravb_main.c | 15 ++++++++++++++-
> > 2 files changed, 16 insertions(+), 1 deletion(-)
> >
> > diff --git a/drivers/net/ethernet/renesas/ravb.h
> > b/drivers/net/ethernet/renesas/ravb.h
> > index e505e8088445..b980bce763d3 100644
> > --- a/drivers/net/ethernet/renesas/ravb.h
> > +++ b/drivers/net/ethernet/renesas/ravb.h
> > @@ -1031,6 +1031,7 @@ struct ravb_hw_info {
> > unsigned err_mgmt_irqs:1; /* Line1 (Err) and Line2 (Mgmt) irqs
> are separate */
> > unsigned gptp:1; /* AVB-DMAC has gPTP support */
> > unsigned ccc_gac:1; /* AVB-DMAC has gPTP support active in
> config mode */
> > + unsigned gptp_ref_clk:1; /* gPTP has separate reference clock
> */
> > unsigned nc_queues:1; /* AVB-DMAC has RX and TX NC queues */
> > unsigned magic_pkt:1; /* E-MAC supports magic packet
> detection */
> > unsigned half_duplex:1; /* E-MAC supports half duplex mode */
> > @@ -1042,6 +1043,7 @@ struct ravb_private {
> > void __iomem *addr;
> > struct clk *clk;
> > struct clk *refclk;
> > + struct clk *gptp_clk;
> > struct mdiobb_ctrl mdiobb;
> > u32 num_rx_ring[NUM_RX_QUEUE];
> > u32 num_tx_ring[NUM_TX_QUEUE];
> > diff --git a/drivers/net/ethernet/renesas/ravb_main.c
> > b/drivers/net/ethernet/renesas/ravb_main.c
> > index 8ccc817b8b5d..ef6967731263 100644
> > --- a/drivers/net/ethernet/renesas/ravb_main.c
> > +++ b/drivers/net/ethernet/renesas/ravb_main.c
> > @@ -2495,11 +2495,15 @@ MODULE_DEVICE_TABLE(of, ravb_match_table);
> > static int ravb_set_gti(struct net_device *ndev) {
> > struct ravb_private *priv = netdev_priv(ndev);
> > + const struct ravb_hw_info *info = priv->info;
> > struct device *dev = ndev->dev.parent;
> > unsigned long rate;
> > uint64_t inc;
> >
> > - rate = clk_get_rate(priv->clk);
> > + if (info->gptp_ref_clk)
> > + rate = clk_get_rate(priv->gptp_clk);
> > + else
> > + rate = clk_get_rate(priv->clk);
> > if (!rate)
> > return -EINVAL;
> >
> > @@ -2721,6 +2725,15 @@ static int ravb_probe(struct platform_device
> *pdev)
> > }
> > clk_prepare_enable(priv->refclk);
> >
> > + if (info->gptp_ref_clk) {
> > + priv->gptp_clk = devm_clk_get(&pdev->dev, "gptp");
> > + if (IS_ERR(priv->gptp_clk)) {
> > + error = PTR_ERR(priv->gptp_clk);
> > + goto out_release;
> > + }
> > + clk_prepare_enable(priv->gptp_clk);
> > + }
> > +
>
> I guess you need to a conditional
>
> clk_disable_unprepare(info->gptp_ref_clk)
>
> in the error path? And even in ravb_remove()?
Oops, how did I miss that?
Thanks
Phil
> > ndev->max_mtu = info->rx_max_buf_size - (ETH_HLEN + VLAN_HLEN +
> ETH_FCS_LEN);
> > ndev->min_mtu = ETH_MIN_MTU;
> >
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v3 5/5] ravb: Add support for RZ/V2M
2022-05-10 9:03 [PATCH v3 0/5] Add Renesas RZ/V2M Ethernet support Phil Edworthy
` (3 preceding siblings ...)
2022-05-10 9:03 ` [PATCH v3 4/5] ravb: Use separate clock for gPTP Phil Edworthy
@ 2022-05-10 9:03 ` Phil Edworthy
4 siblings, 0 replies; 11+ messages in thread
From: Phil Edworthy @ 2022-05-10 9:03 UTC (permalink / raw)
To: David S. Miller, Eric Dumazet, Jakub Kicinski, Paolo Abeni
Cc: Phil Edworthy, Geert Uytterhoeven, Sergey Shtylyov, Biju Das,
Lad Prabhakar, netdev, linux-renesas-soc
RZ/V2M Ethernet is very similar to R-Car Gen3 Ethernet-AVB, though
some small parts are the same as R-Car Gen2.
Other differences to R-Car Gen3 and Gen2 are:
* It has separate data (DI), error (Line 1) and management (Line 2) irqs
rather than one irq for all three.
* Instead of using the High-speed peripheral bus clock for gPTP, it has a
separate gPTP reference clock.
Signed-off-by: Phil Edworthy <phil.edworthy@renesas.com>
Reviewed-by: Biju Das <biju.das.jz@bp.renesas.com>
Reviewed-by: Sergey Shtylyov <s.shtylyov@omp.ru>
---
v3:
- Added Reviewed-by tags
v2:
- Removed gptp_ptm_gic feature that is no longer needed.
---
drivers/net/ethernet/renesas/ravb_main.c | 26 ++++++++++++++++++++++++
1 file changed, 26 insertions(+)
diff --git a/drivers/net/ethernet/renesas/ravb_main.c b/drivers/net/ethernet/renesas/ravb_main.c
index ef6967731263..6442b3f807af 100644
--- a/drivers/net/ethernet/renesas/ravb_main.c
+++ b/drivers/net/ethernet/renesas/ravb_main.c
@@ -2460,6 +2460,31 @@ static const struct ravb_hw_info ravb_gen2_hw_info = {
.magic_pkt = 1,
};
+static const struct ravb_hw_info ravb_rzv2m_hw_info = {
+ .rx_ring_free = ravb_rx_ring_free_rcar,
+ .rx_ring_format = ravb_rx_ring_format_rcar,
+ .alloc_rx_desc = ravb_alloc_rx_desc_rcar,
+ .receive = ravb_rx_rcar,
+ .set_rate = ravb_set_rate_rcar,
+ .set_feature = ravb_set_features_rcar,
+ .dmac_init = ravb_dmac_init_rcar,
+ .emac_init = ravb_emac_init_rcar,
+ .gstrings_stats = ravb_gstrings_stats,
+ .gstrings_size = sizeof(ravb_gstrings_stats),
+ .net_hw_features = NETIF_F_RXCSUM,
+ .net_features = NETIF_F_RXCSUM,
+ .stats_len = ARRAY_SIZE(ravb_gstrings_stats),
+ .max_rx_len = RX_BUF_SZ + RAVB_ALIGN - 1,
+ .tccr_mask = TCCR_TSRQ0 | TCCR_TSRQ1 | TCCR_TSRQ2 | TCCR_TSRQ3,
+ .rx_max_buf_size = SZ_2K,
+ .multi_irqs = 1,
+ .err_mgmt_irqs = 1,
+ .gptp = 1,
+ .gptp_ref_clk = 1,
+ .nc_queues = 1,
+ .magic_pkt = 1,
+};
+
static const struct ravb_hw_info gbeth_hw_info = {
.rx_ring_free = ravb_rx_ring_free_gbeth,
.rx_ring_format = ravb_rx_ring_format_gbeth,
@@ -2487,6 +2512,7 @@ static const struct of_device_id ravb_match_table[] = {
{ .compatible = "renesas,etheravb-rcar-gen2", .data = &ravb_gen2_hw_info },
{ .compatible = "renesas,etheravb-r8a7795", .data = &ravb_gen3_hw_info },
{ .compatible = "renesas,etheravb-rcar-gen3", .data = &ravb_gen3_hw_info },
+ { .compatible = "renesas,etheravb-rzv2m", .data = &ravb_rzv2m_hw_info },
{ .compatible = "renesas,rzg2l-gbeth", .data = &gbeth_hw_info },
{ }
};
--
2.32.0
^ permalink raw reply related [flat|nested] 11+ messages in thread