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* [PATCH v3 1/2] ns16550: reject IRQ above nr_irqs_gsi
@ 2022-05-10 15:58 Marek Marczykowski-Górecki
  2022-05-10 15:58 ` [PATCH v3 2/2] ns16550: Add more device IDs for Intel LPSS UART Marek Marczykowski-Górecki
  2022-05-11  7:20 ` [PATCH v3 1/2] ns16550: reject IRQ above nr_irqs_gsi Roger Pau Monné
  0 siblings, 2 replies; 4+ messages in thread
From: Marek Marczykowski-Górecki @ 2022-05-10 15:58 UTC (permalink / raw)
  To: xen-devel
  Cc: Marek Marczykowski-Górecki, Andrew Cooper, George Dunlap,
	Jan Beulich, Julien Grall, Stefano Stabellini, Wei Liu

Intel LPSS has INTERRUPT_LINE set to 0xff by default, that is declared
by the PCI Local Bus Specification Revision 3.0 (from 2004) as
"unknown"/"no connection". Fallback to poll mode in this case.

Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
---
Changes in v3:
 - change back to checking 0xff explicitly
 - adjust commit message, include spec reference
 - change warning to match the above
Changes in v2:
 - add log message
 - extend commit message
 - code style fix
---
 xen/drivers/char/ns16550.c | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
index fb75cee4a13a..b4434ad815e1 100644
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -1238,6 +1238,15 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx)
                             pci_conf_read8(PCI_SBDF(0, b, d, f),
                                            PCI_INTERRUPT_LINE) : 0;
 
+                if ( uart->irq == 0xff )
+                {
+                    printk(XENLOG_WARNING
+                           "ns16550: %02x:%02x.%u has no legacy IRQ %d, "
+                           "falling back to a poll mode\n",
+                           b, d, f, uart->irq);
+                    uart->irq = 0;
+                }
+
                 return 0;
             }
         }
-- 
2.35.1



^ permalink raw reply related	[flat|nested] 4+ messages in thread

* [PATCH v3 2/2] ns16550: Add more device IDs for Intel LPSS UART
  2022-05-10 15:58 [PATCH v3 1/2] ns16550: reject IRQ above nr_irqs_gsi Marek Marczykowski-Górecki
@ 2022-05-10 15:58 ` Marek Marczykowski-Górecki
  2022-05-11  7:20 ` [PATCH v3 1/2] ns16550: reject IRQ above nr_irqs_gsi Roger Pau Monné
  1 sibling, 0 replies; 4+ messages in thread
From: Marek Marczykowski-Górecki @ 2022-05-10 15:58 UTC (permalink / raw)
  To: xen-devel
  Cc: Marek Marczykowski-Górecki, Andrew Cooper, George Dunlap,
	Jan Beulich, Julien Grall, Stefano Stabellini, Wei Liu

This is purely based on the spec:
- Intel 500 Series PCH: 635218-006
- Intel 600 Series PCH: 691222-001, 648364-003

This is tested only on TGL-LP added initially, but according to the
spec, they should behave the same.

Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
Acked-by: Andrew Cooper <andrew.cooper3@citrix.com>
---
Changes in v2:
 - new patch, adding more IDs to the patch that went in already
---
 xen/drivers/char/ns16550.c | 80 +++++++++++++++++++++++++++++++++++++-
 1 file changed, 79 insertions(+), 1 deletion(-)

diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
index b4434ad815e1..72283c106514 100644
--- a/xen/drivers/char/ns16550.c
+++ b/xen/drivers/char/ns16550.c
@@ -1077,12 +1077,90 @@ static const struct ns16550_config __initconst uart_config[] =
         .dev_id = 0x0358,
         .param = param_exar_xr17v358
     },
-    /* Intel Corp. TGL-LP LPSS PCI */
+    /* Intel Corp. TGL-LP LPSS PCI UART #0 */
+    {
+        .vendor_id = PCI_VENDOR_ID_INTEL,
+        .dev_id = 0xa0a8,
+        .param = param_intel_lpss
+    },
+    /* Intel Corp. TGL-LP LPSS PCI UART #1 */
+    {
+        .vendor_id = PCI_VENDOR_ID_INTEL,
+        .dev_id = 0xa0a9,
+        .param = param_intel_lpss
+    },
+    /* Intel Corp. TGL-LP LPSS PCI UART #2 */
     {
         .vendor_id = PCI_VENDOR_ID_INTEL,
         .dev_id = 0xa0c7,
         .param = param_intel_lpss
     },
+    /* Intel Corp. TGL-H LPSS PCI UART #0 */
+    {
+        .vendor_id = PCI_VENDOR_ID_INTEL,
+        .dev_id = 0x43a8,
+        .param = param_intel_lpss
+    },
+    /* Intel Corp. TGL-H LPSS PCI UART #1 */
+    {
+        .vendor_id = PCI_VENDOR_ID_INTEL,
+        .dev_id = 0x43a9,
+        .param = param_intel_lpss
+    },
+    /* Intel Corp. TGL-H LPSS PCI UART #2 */
+    {
+        .vendor_id = PCI_VENDOR_ID_INTEL,
+        .dev_id = 0x43a7,
+        .param = param_intel_lpss
+    },
+    /* Intel Corp. ADL-P LPSS PCI UART #0 */
+    {
+        .vendor_id = PCI_VENDOR_ID_INTEL,
+        .dev_id = 0x51a8,
+        .param = param_intel_lpss
+    },
+    /* Intel Corp. ADL-P LPSS PCI UART #1 */
+    {
+        .vendor_id = PCI_VENDOR_ID_INTEL,
+        .dev_id = 0x51a9,
+        .param = param_intel_lpss
+    },
+    /* Intel Corp. ADL-P LPSS PCI UART #2 */
+    {
+        .vendor_id = PCI_VENDOR_ID_INTEL,
+        .dev_id = 0x51c7,
+        .param = param_intel_lpss
+    },
+    /* Intel Corp. ADL-P LPSS PCI UART #3 */
+    {
+        .vendor_id = PCI_VENDOR_ID_INTEL,
+        .dev_id = 0x51da,
+        .param = param_intel_lpss
+    },
+    /* Intel Corp. ADL-S LPSS PCI UART #0 */
+    {
+        .vendor_id = PCI_VENDOR_ID_INTEL,
+        .dev_id = 0x7aa8,
+        .param = param_intel_lpss
+    },
+    /* Intel Corp. ADL-S LPSS PCI UART #1 */
+    {
+        .vendor_id = PCI_VENDOR_ID_INTEL,
+        .dev_id = 0x7aa9,
+        .param = param_intel_lpss
+    },
+    /* Intel Corp. ADL-S LPSS PCI UART #2 */
+    {
+        .vendor_id = PCI_VENDOR_ID_INTEL,
+        .dev_id = 0x7afe,
+        .param = param_intel_lpss
+    },
+    /* Intel Corp. ADL-S LPSS PCI UART #3 */
+    {
+        .vendor_id = PCI_VENDOR_ID_INTEL,
+        .dev_id = 0x7adc,
+        .param = param_intel_lpss
+    },
 };
 
 static int __init
-- 
2.35.1



^ permalink raw reply related	[flat|nested] 4+ messages in thread

* Re: [PATCH v3 1/2] ns16550: reject IRQ above nr_irqs_gsi
  2022-05-10 15:58 [PATCH v3 1/2] ns16550: reject IRQ above nr_irqs_gsi Marek Marczykowski-Górecki
  2022-05-10 15:58 ` [PATCH v3 2/2] ns16550: Add more device IDs for Intel LPSS UART Marek Marczykowski-Górecki
@ 2022-05-11  7:20 ` Roger Pau Monné
  2022-05-11  7:57   ` Roger Pau Monné
  1 sibling, 1 reply; 4+ messages in thread
From: Roger Pau Monné @ 2022-05-11  7:20 UTC (permalink / raw)
  To: Marek Marczykowski-Górecki
  Cc: xen-devel, Andrew Cooper, George Dunlap, Jan Beulich,
	Julien Grall, Stefano Stabellini, Wei Liu

Subject line needs to be updated :).

On Tue, May 10, 2022 at 05:58:23PM +0200, Marek Marczykowski-Górecki wrote:
> Intel LPSS has INTERRUPT_LINE set to 0xff by default, that is declared
> by the PCI Local Bus Specification Revision 3.0 (from 2004) as
> "unknown"/"no connection". Fallback to poll mode in this case.
> 
> Signed-off-by: Marek Marczykowski-Górecki <marmarek@invisiblethingslab.com>
> ---
> Changes in v3:
>  - change back to checking 0xff explicitly
>  - adjust commit message, include spec reference
>  - change warning to match the above
> Changes in v2:
>  - add log message
>  - extend commit message
>  - code style fix
> ---
>  xen/drivers/char/ns16550.c | 9 +++++++++
>  1 file changed, 9 insertions(+)
> 
> diff --git a/xen/drivers/char/ns16550.c b/xen/drivers/char/ns16550.c
> index fb75cee4a13a..b4434ad815e1 100644
> --- a/xen/drivers/char/ns16550.c
> +++ b/xen/drivers/char/ns16550.c
> @@ -1238,6 +1238,15 @@ pci_uart_config(struct ns16550 *uart, bool_t skip_amt, unsigned int idx)
>                              pci_conf_read8(PCI_SBDF(0, b, d, f),
>                                             PCI_INTERRUPT_LINE) : 0;
>  
> +                if ( uart->irq == 0xff )
> +                {
> +                    printk(XENLOG_WARNING

XENLOG_INFO would be better, IMO this configuration is no reason to
warn the user.

> +                           "ns16550: %02x:%02x.%u has no legacy IRQ %d, "
> +                           "falling back to a poll mode\n",

Could you use %pp and then pass the parameter using &PCI_SBDF(0, b, d,
f)?

Also we try to avoid splitting printk format strings, what about
using:

"ns16550: %02x:%02x.%u no legacy IRQ, using poll mode\n"

TBH, we don't print a similar message if INTERRUPT_{PIN,LINE} is 0
(which also results in the console running in poll mode), so I wonder
if we should extend the printing of the message also to ->irq == 0 for
consistency.

Thanks, Roger.


^ permalink raw reply	[flat|nested] 4+ messages in thread

* Re: [PATCH v3 1/2] ns16550: reject IRQ above nr_irqs_gsi
  2022-05-11  7:20 ` [PATCH v3 1/2] ns16550: reject IRQ above nr_irqs_gsi Roger Pau Monné
@ 2022-05-11  7:57   ` Roger Pau Monné
  0 siblings, 0 replies; 4+ messages in thread
From: Roger Pau Monné @ 2022-05-11  7:57 UTC (permalink / raw)
  To: Marek Marczykowski-Górecki
  Cc: xen-devel, Andrew Cooper, George Dunlap, Jan Beulich,
	Julien Grall, Stefano Stabellini, Wei Liu

On Wed, May 11, 2022 at 09:20:46AM +0200, Roger Pau Monné wrote:
> Subject line needs to be updated :).
> 
> On Tue, May 10, 2022 at 05:58:23PM +0200, Marek Marczykowski-Górecki wrote:
> > Intel LPSS has INTERRUPT_LINE set to 0xff by default, that is declared
> > by the PCI Local Bus Specification Revision 3.0 (from 2004) as
> > "unknown"/"no connection". Fallback to poll mode in this case.

Forgot to comment: you should also mention that this 0xff special
handling is for x86 only, other arches can use other meanings for the
INTERRUPT_LINE register.

Likely this also implies that the 0xff check should be protected by
CONFIG_X86 (albeit I think that code is already only reachable from
x86 as Arm doesn't yet enable CONFIG_PCI).

Thanks, Roger.


^ permalink raw reply	[flat|nested] 4+ messages in thread

end of thread, other threads:[~2022-05-11  7:57 UTC | newest]

Thread overview: 4+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-10 15:58 [PATCH v3 1/2] ns16550: reject IRQ above nr_irqs_gsi Marek Marczykowski-Górecki
2022-05-10 15:58 ` [PATCH v3 2/2] ns16550: Add more device IDs for Intel LPSS UART Marek Marczykowski-Górecki
2022-05-11  7:20 ` [PATCH v3 1/2] ns16550: reject IRQ above nr_irqs_gsi Roger Pau Monné
2022-05-11  7:57   ` Roger Pau Monné

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