* [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode
@ 2022-05-11 14:22 Nirmoy Das
2022-05-11 14:26 ` Das, Nirmoy
` (2 more replies)
0 siblings, 3 replies; 7+ messages in thread
From: Nirmoy Das @ 2022-05-11 14:22 UTC (permalink / raw)
To: intel-gfx; +Cc: krishnaiah.bommu, matthew.auld
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Enable Tile4 tiling mode on platform that supports
Tile4 but no TileY like DG2.
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
---
.../i915/gem/selftests/i915_gem_client_blt.c | 238 ++++++++++++++----
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++
2 files changed, 214 insertions(+), 46 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index ddd0772fd828..71d7e4afa136 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -6,6 +6,7 @@
#include "i915_selftest.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt.h"
@@ -18,10 +19,71 @@
#include "huge_gem_object.h"
#include "mock_context.h"
+#define OW_SIZE 16 /* in bytes */
+#define F_SUBTILE_SIZE 64 /* in bytes */
+#define F_TILE_WIDTH 128 /* in bytes */
+#define F_TILE_HEIGHT 32 /* in pixels */
+#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */
+#define F_SUBTILE_HEIGHT 4 /* in pixels */
+
+static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp)
+{
+ int tile_base;
+ int tile_x, tile_y;
+ int swizzle, subtile;
+ int pixel_size = bpp / 8;
+ int pos;
+
+ /*
+ * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a
+ * so we can use the same table to tile and until.
+ */
+ static const u8 f_subtile_map[] = {
+ 0, 1, 2, 3, 8, 9, 10, 11,
+ 4, 5, 6, 7, 12, 13, 14, 15,
+ 16, 17, 18, 19, 24, 25, 26, 27,
+ 20, 21, 22, 23, 28, 29, 30, 31,
+ 32, 33, 34, 35, 40, 41, 42, 43,
+ 36, 37, 38, 39, 44, 45, 46, 47,
+ 48, 49, 50, 51, 56, 57, 58, 59,
+ 52, 53, 54, 55, 60, 61, 62, 63
+ };
+
+ x *= pixel_size;
+ /*
+ * Where does the 4k tile start (in bytes)? This is the same for Y and
+ * F so we can use the Y-tile algorithm to get to that point.
+ */
+ tile_base =
+ y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT +
+ x / F_TILE_WIDTH * 4096;
+
+ /* Find pixel within tile */
+ tile_x = x % F_TILE_WIDTH;
+ tile_y = y % F_TILE_HEIGHT;
+
+ /* And figure out the subtile within the 4k tile */
+ subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH;
+
+ /* Swizzle the subtile number according to the bspec diagram */
+ swizzle = f_subtile_map[subtile];
+
+ /* Calculate new position */
+ pos = tile_base +
+ swizzle * F_SUBTILE_SIZE +
+ tile_y % F_SUBTILE_HEIGHT * OW_SIZE +
+ tile_x % F_SUBTILE_WIDTH;
+
+ GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size));
+
+ return pos / pixel_size * 4;
+}
+
enum client_tiling {
CLIENT_TILING_LINEAR,
CLIENT_TILING_X,
CLIENT_TILING_Y,
+ CLIENT_TILING_4,
CLIENT_NUM_TILING_TYPES
};
@@ -45,6 +107,19 @@ struct tiled_blits {
u32 height;
};
+static bool fast_blit_ok(struct blit_buffer *buf)
+{
+ int gen = GRAPHICS_VER(buf->vma->vm->i915);
+
+ if (gen < 9)
+ return false;
+
+ if (gen < 12)
+ return true;
+
+ return !IS_DG1(buf->vma->vm->i915) || buf->tiling != CLIENT_TILING_X;
+}
+
static int prepare_blit(const struct tiled_blits *t,
struct blit_buffer *dst,
struct blit_buffer *src,
@@ -59,54 +134,109 @@ static int prepare_blit(const struct tiled_blits *t,
if (IS_ERR(cs))
return PTR_ERR(cs);
- *cs++ = MI_LOAD_REGISTER_IMM(1);
- *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
- cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
- if (src->tiling == CLIENT_TILING_Y)
- cmd |= BCS_SRC_Y;
- if (dst->tiling == CLIENT_TILING_Y)
- cmd |= BCS_DST_Y;
- *cs++ = cmd;
-
- cmd = MI_FLUSH_DW;
- if (ver >= 8)
- cmd++;
- *cs++ = cmd;
- *cs++ = 0;
- *cs++ = 0;
- *cs++ = 0;
-
- cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
- if (ver >= 8)
- cmd += 2;
-
- src_pitch = t->width * 4;
- if (src->tiling) {
- cmd |= XY_SRC_COPY_BLT_SRC_TILED;
- src_pitch /= 4;
- }
+ /*
+ * On GEN12+ X-tiled format support is removed from the fast blit
+ * command, so use the XY_SRC blit command for it instead.
+ */
+ if (fast_blit_ok(dst) && fast_blit_ok(src)) {
+ struct intel_gt *gt = t->ce->engine->gt;
+ u32 src_tiles = 0, dst_tiles = 0;
+ u32 src_4t = 0, dst_4t = 0;
+
+ /* Need to program BLIT_CCTL if it is not done previously
+ * before using XY_FAST_COPY_BLT
+ */
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));
+ *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) |
+ BLIT_CCTL_DST_MOCS(gt->mocs.uc_index));
+
+ src_pitch = t->width; /* in dwords */
+ if (src->tiling == CLIENT_TILING_4) {
+ src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
+ src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
+ } else if (src->tiling == CLIENT_TILING_Y) {
+ src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
+ } else if (src->tiling == CLIENT_TILING_X) {
+ src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
+ } else {
+ src_pitch *= 4; /* in bytes */
+ }
- dst_pitch = t->width * 4;
- if (dst->tiling) {
- cmd |= XY_SRC_COPY_BLT_DST_TILED;
- dst_pitch /= 4;
- }
+ dst_pitch = t->width; /* in dwords */
+ if (dst->tiling == CLIENT_TILING_4) {
+ dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
+ dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
+ } else if (dst->tiling == CLIENT_TILING_Y) {
+ dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
+ } else if (dst->tiling == CLIENT_TILING_X) {
+ dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
+ } else {
+ dst_pitch *= 4; /* in bytes */
+ }
- *cs++ = cmd;
- *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
- *cs++ = 0;
- *cs++ = t->height << 16 | t->width;
- *cs++ = lower_32_bits(dst->vma->node.start);
- if (use_64b_reloc)
+ *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) |
+ src_tiles | dst_tiles;
+ *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch;
+ *cs++ = 0;
+ *cs++ = t->height << 16 | t->width;
+ *cs++ = lower_32_bits(dst->vma->node.start);
*cs++ = upper_32_bits(dst->vma->node.start);
- *cs++ = 0;
- *cs++ = src_pitch;
- *cs++ = lower_32_bits(src->vma->node.start);
- if (use_64b_reloc)
+ *cs++ = 0;
+ *cs++ = src_pitch;
+ *cs++ = lower_32_bits(src->vma->node.start);
*cs++ = upper_32_bits(src->vma->node.start);
+ } else {
+ if (ver >= 6) {
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
+ cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
+ if (src->tiling == CLIENT_TILING_Y)
+ cmd |= BCS_SRC_Y;
+ if (dst->tiling == CLIENT_TILING_Y)
+ cmd |= BCS_DST_Y;
+ *cs++ = cmd;
+
+ cmd = MI_FLUSH_DW;
+ if (ver >= 8)
+ cmd++;
+ *cs++ = cmd;
+ *cs++ = 0;
+ *cs++ = 0;
+ *cs++ = 0;
+ }
- *cs++ = MI_BATCH_BUFFER_END;
+ cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
+ if (ver >= 8)
+ cmd += 2;
+
+ src_pitch = t->width * 4;
+ if (src->tiling) {
+ cmd |= XY_SRC_COPY_BLT_SRC_TILED;
+ src_pitch /= 4;
+ }
+
+ dst_pitch = t->width * 4;
+ if (dst->tiling) {
+ cmd |= XY_SRC_COPY_BLT_DST_TILED;
+ dst_pitch /= 4;
+ }
+
+ *cs++ = cmd;
+ *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
+ *cs++ = 0;
+ *cs++ = t->height << 16 | t->width;
+ *cs++ = lower_32_bits(dst->vma->node.start);
+ if (use_64b_reloc)
+ *cs++ = upper_32_bits(dst->vma->node.start);
+ *cs++ = 0;
+ *cs++ = src_pitch;
+ *cs++ = lower_32_bits(src->vma->node.start);
+ if (use_64b_reloc)
+ *cs++ = upper_32_bits(dst->vma->node.start);
+ }
+ *cs++ = MI_BATCH_BUFFER_END;
i915_gem_object_flush_map(batch);
i915_gem_object_unpin_map(batch);
@@ -181,7 +311,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
t->buffers[i].vma = vma;
t->buffers[i].tiling =
- i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
+ i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng);
+
+ /* Platforms support either TileY or Tile4, not both */
+ if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y)
+ t->buffers[i].tiling = CLIENT_TILING_4;
+ else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4)
+ t->buffers[i].tiling = CLIENT_TILING_Y;
}
return 0;
@@ -206,7 +342,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
static u64 tiled_offset(const struct intel_gt *gt,
u64 v,
unsigned int stride,
- enum client_tiling tiling)
+ enum client_tiling tiling,
+ int x_pos, int y_pos)
{
unsigned int swizzle;
u64 x, y;
@@ -216,7 +353,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
y = div64_u64_rem(v, stride, &x);
- if (tiling == CLIENT_TILING_X) {
+ if (tiling == CLIENT_TILING_4) {
+ v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
+
+ /* no swizzling for f-tiling */
+ swizzle = I915_BIT_6_SWIZZLE_NONE;
+ } else if (tiling == CLIENT_TILING_X) {
v = div64_u64_rem(y, 8, &y) * stride * 8;
v += y * 512;
v += div64_u64_rem(x, 512, &x) << 12;
@@ -259,6 +401,7 @@ static const char *repr_tiling(enum client_tiling tiling)
case CLIENT_TILING_LINEAR: return "linear";
case CLIENT_TILING_X: return "X";
case CLIENT_TILING_Y: return "Y";
+ case CLIENT_TILING_4: return "F";
default: return "unknown";
}
}
@@ -284,7 +427,7 @@ static int verify_buffer(const struct tiled_blits *t,
} else {
u64 v = tiled_offset(buf->vma->vm->gt,
p * 4, t->width * 4,
- buf->tiling);
+ buf->tiling, x, y);
if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p)
ret = -EINVAL;
@@ -504,6 +647,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)
if (err)
return err;
+ /* Simulating GTT eviction of the same buffer / layout */
+ t->buffers[2].tiling = t->buffers[0].tiling;
+
/* Reposition so that we overlap the old addresses, and slightly off */
err = tiled_blit(t,
&t->buffers[2], t->hole + t->align,
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 556bca3be804..e53db7c1bdc0 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -236,6 +236,28 @@
#define XY_FAST_COLOR_BLT_DW 16
#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
#define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
+
+#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20)
+#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13)
+#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \
+ REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)
+#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \
+ REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)
+#define LINEAR 0
+#define TILE_X 0x1
+#define XMAJOR 0x1
+#define YMAJOR 0x2
+#define TILE_64 0x3
+#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)
+#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)
+#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
+#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
+/* Note: MOCS value = (index << 1) */
+#define BLIT_CCTL_SRC_MOCS(idx) \
+ REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, idx << 1)
+#define BLIT_CCTL_DST_MOCS(idx) \
+ REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, idx << 1)
+
#define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
#define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
#define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22)
--
2.35.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode
2022-05-11 14:22 [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode Nirmoy Das
@ 2022-05-11 14:26 ` Das, Nirmoy
2022-05-11 17:04 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-05-11 17:28 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Das, Nirmoy @ 2022-05-11 14:26 UTC (permalink / raw)
To: intel-gfx; +Cc: krishnaiah.bommu, matthew.auld
This also:
Closes: https://gitlab.freedesktop.org/drm/intel/-/issues/5879
On 5/11/2022 4:22 PM, Nirmoy Das wrote:
> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>
> Enable Tile4 tiling mode on platform that supports
> Tile4 but no TileY like DG2.
>
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
> .../i915/gem/selftests/i915_gem_client_blt.c | 238 ++++++++++++++----
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++
> 2 files changed, 214 insertions(+), 46 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> index ddd0772fd828..71d7e4afa136 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> @@ -6,6 +6,7 @@
> #include "i915_selftest.h"
>
> #include "gt/intel_context.h"
> +#include "gt/intel_engine_regs.h"
> #include "gt/intel_engine_user.h"
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_gt.h"
> @@ -18,10 +19,71 @@
> #include "huge_gem_object.h"
> #include "mock_context.h"
>
> +#define OW_SIZE 16 /* in bytes */
> +#define F_SUBTILE_SIZE 64 /* in bytes */
> +#define F_TILE_WIDTH 128 /* in bytes */
> +#define F_TILE_HEIGHT 32 /* in pixels */
> +#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */
> +#define F_SUBTILE_HEIGHT 4 /* in pixels */
> +
> +static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp)
> +{
> + int tile_base;
> + int tile_x, tile_y;
> + int swizzle, subtile;
> + int pixel_size = bpp / 8;
> + int pos;
> +
> + /*
> + * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a
> + * so we can use the same table to tile and until.
> + */
> + static const u8 f_subtile_map[] = {
> + 0, 1, 2, 3, 8, 9, 10, 11,
> + 4, 5, 6, 7, 12, 13, 14, 15,
> + 16, 17, 18, 19, 24, 25, 26, 27,
> + 20, 21, 22, 23, 28, 29, 30, 31,
> + 32, 33, 34, 35, 40, 41, 42, 43,
> + 36, 37, 38, 39, 44, 45, 46, 47,
> + 48, 49, 50, 51, 56, 57, 58, 59,
> + 52, 53, 54, 55, 60, 61, 62, 63
> + };
> +
> + x *= pixel_size;
> + /*
> + * Where does the 4k tile start (in bytes)? This is the same for Y and
> + * F so we can use the Y-tile algorithm to get to that point.
> + */
> + tile_base =
> + y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT +
> + x / F_TILE_WIDTH * 4096;
> +
> + /* Find pixel within tile */
> + tile_x = x % F_TILE_WIDTH;
> + tile_y = y % F_TILE_HEIGHT;
> +
> + /* And figure out the subtile within the 4k tile */
> + subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH;
> +
> + /* Swizzle the subtile number according to the bspec diagram */
> + swizzle = f_subtile_map[subtile];
> +
> + /* Calculate new position */
> + pos = tile_base +
> + swizzle * F_SUBTILE_SIZE +
> + tile_y % F_SUBTILE_HEIGHT * OW_SIZE +
> + tile_x % F_SUBTILE_WIDTH;
> +
> + GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size));
> +
> + return pos / pixel_size * 4;
> +}
> +
> enum client_tiling {
> CLIENT_TILING_LINEAR,
> CLIENT_TILING_X,
> CLIENT_TILING_Y,
> + CLIENT_TILING_4,
> CLIENT_NUM_TILING_TYPES
> };
>
> @@ -45,6 +107,19 @@ struct tiled_blits {
> u32 height;
> };
>
> +static bool fast_blit_ok(struct blit_buffer *buf)
> +{
> + int gen = GRAPHICS_VER(buf->vma->vm->i915);
> +
> + if (gen < 9)
> + return false;
> +
> + if (gen < 12)
> + return true;
> +
> + return !IS_DG1(buf->vma->vm->i915) || buf->tiling != CLIENT_TILING_X;
> +}
> +
> static int prepare_blit(const struct tiled_blits *t,
> struct blit_buffer *dst,
> struct blit_buffer *src,
> @@ -59,54 +134,109 @@ static int prepare_blit(const struct tiled_blits *t,
> if (IS_ERR(cs))
> return PTR_ERR(cs);
>
> - *cs++ = MI_LOAD_REGISTER_IMM(1);
> - *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
> - cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
> - if (src->tiling == CLIENT_TILING_Y)
> - cmd |= BCS_SRC_Y;
> - if (dst->tiling == CLIENT_TILING_Y)
> - cmd |= BCS_DST_Y;
> - *cs++ = cmd;
> -
> - cmd = MI_FLUSH_DW;
> - if (ver >= 8)
> - cmd++;
> - *cs++ = cmd;
> - *cs++ = 0;
> - *cs++ = 0;
> - *cs++ = 0;
> -
> - cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
> - if (ver >= 8)
> - cmd += 2;
> -
> - src_pitch = t->width * 4;
> - if (src->tiling) {
> - cmd |= XY_SRC_COPY_BLT_SRC_TILED;
> - src_pitch /= 4;
> - }
> + /*
> + * On GEN12+ X-tiled format support is removed from the fast blit
> + * command, so use the XY_SRC blit command for it instead.
> + */
> + if (fast_blit_ok(dst) && fast_blit_ok(src)) {
> + struct intel_gt *gt = t->ce->engine->gt;
> + u32 src_tiles = 0, dst_tiles = 0;
> + u32 src_4t = 0, dst_4t = 0;
> +
> + /* Need to program BLIT_CCTL if it is not done previously
> + * before using XY_FAST_COPY_BLT
> + */
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));
> + *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) |
> + BLIT_CCTL_DST_MOCS(gt->mocs.uc_index));
> +
> + src_pitch = t->width; /* in dwords */
> + if (src->tiling == CLIENT_TILING_4) {
> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
> + src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
> + } else if (src->tiling == CLIENT_TILING_Y) {
> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
> + } else if (src->tiling == CLIENT_TILING_X) {
> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
> + } else {
> + src_pitch *= 4; /* in bytes */
> + }
>
> - dst_pitch = t->width * 4;
> - if (dst->tiling) {
> - cmd |= XY_SRC_COPY_BLT_DST_TILED;
> - dst_pitch /= 4;
> - }
> + dst_pitch = t->width; /* in dwords */
> + if (dst->tiling == CLIENT_TILING_4) {
> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
> + dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
> + } else if (dst->tiling == CLIENT_TILING_Y) {
> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
> + } else if (dst->tiling == CLIENT_TILING_X) {
> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
> + } else {
> + dst_pitch *= 4; /* in bytes */
> + }
>
> - *cs++ = cmd;
> - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
> - *cs++ = 0;
> - *cs++ = t->height << 16 | t->width;
> - *cs++ = lower_32_bits(dst->vma->node.start);
> - if (use_64b_reloc)
> + *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) |
> + src_tiles | dst_tiles;
> + *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch;
> + *cs++ = 0;
> + *cs++ = t->height << 16 | t->width;
> + *cs++ = lower_32_bits(dst->vma->node.start);
> *cs++ = upper_32_bits(dst->vma->node.start);
> - *cs++ = 0;
> - *cs++ = src_pitch;
> - *cs++ = lower_32_bits(src->vma->node.start);
> - if (use_64b_reloc)
> + *cs++ = 0;
> + *cs++ = src_pitch;
> + *cs++ = lower_32_bits(src->vma->node.start);
> *cs++ = upper_32_bits(src->vma->node.start);
> + } else {
> + if (ver >= 6) {
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
> + cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
> + if (src->tiling == CLIENT_TILING_Y)
> + cmd |= BCS_SRC_Y;
> + if (dst->tiling == CLIENT_TILING_Y)
> + cmd |= BCS_DST_Y;
> + *cs++ = cmd;
> +
> + cmd = MI_FLUSH_DW;
> + if (ver >= 8)
> + cmd++;
> + *cs++ = cmd;
> + *cs++ = 0;
> + *cs++ = 0;
> + *cs++ = 0;
> + }
>
> - *cs++ = MI_BATCH_BUFFER_END;
> + cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
> + if (ver >= 8)
> + cmd += 2;
> +
> + src_pitch = t->width * 4;
> + if (src->tiling) {
> + cmd |= XY_SRC_COPY_BLT_SRC_TILED;
> + src_pitch /= 4;
> + }
> +
> + dst_pitch = t->width * 4;
> + if (dst->tiling) {
> + cmd |= XY_SRC_COPY_BLT_DST_TILED;
> + dst_pitch /= 4;
> + }
> +
> + *cs++ = cmd;
> + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
> + *cs++ = 0;
> + *cs++ = t->height << 16 | t->width;
> + *cs++ = lower_32_bits(dst->vma->node.start);
> + if (use_64b_reloc)
> + *cs++ = upper_32_bits(dst->vma->node.start);
> + *cs++ = 0;
> + *cs++ = src_pitch;
> + *cs++ = lower_32_bits(src->vma->node.start);
> + if (use_64b_reloc)
> + *cs++ = upper_32_bits(dst->vma->node.start);
> + }
>
> + *cs++ = MI_BATCH_BUFFER_END;
> i915_gem_object_flush_map(batch);
> i915_gem_object_unpin_map(batch);
>
> @@ -181,7 +311,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
>
> t->buffers[i].vma = vma;
> t->buffers[i].tiling =
> - i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
> + i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng);
> +
> + /* Platforms support either TileY or Tile4, not both */
> + if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y)
> + t->buffers[i].tiling = CLIENT_TILING_4;
> + else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4)
> + t->buffers[i].tiling = CLIENT_TILING_Y;
> }
>
> return 0;
> @@ -206,7 +342,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
> static u64 tiled_offset(const struct intel_gt *gt,
> u64 v,
> unsigned int stride,
> - enum client_tiling tiling)
> + enum client_tiling tiling,
> + int x_pos, int y_pos)
> {
> unsigned int swizzle;
> u64 x, y;
> @@ -216,7 +353,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
>
> y = div64_u64_rem(v, stride, &x);
>
> - if (tiling == CLIENT_TILING_X) {
> + if (tiling == CLIENT_TILING_4) {
> + v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
> +
> + /* no swizzling for f-tiling */
> + swizzle = I915_BIT_6_SWIZZLE_NONE;
> + } else if (tiling == CLIENT_TILING_X) {
> v = div64_u64_rem(y, 8, &y) * stride * 8;
> v += y * 512;
> v += div64_u64_rem(x, 512, &x) << 12;
> @@ -259,6 +401,7 @@ static const char *repr_tiling(enum client_tiling tiling)
> case CLIENT_TILING_LINEAR: return "linear";
> case CLIENT_TILING_X: return "X";
> case CLIENT_TILING_Y: return "Y";
> + case CLIENT_TILING_4: return "F";
> default: return "unknown";
> }
> }
> @@ -284,7 +427,7 @@ static int verify_buffer(const struct tiled_blits *t,
> } else {
> u64 v = tiled_offset(buf->vma->vm->gt,
> p * 4, t->width * 4,
> - buf->tiling);
> + buf->tiling, x, y);
>
> if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p)
> ret = -EINVAL;
> @@ -504,6 +647,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)
> if (err)
> return err;
>
> + /* Simulating GTT eviction of the same buffer / layout */
> + t->buffers[2].tiling = t->buffers[0].tiling;
> +
> /* Reposition so that we overlap the old addresses, and slightly off */
> err = tiled_blit(t,
> &t->buffers[2], t->hole + t->align,
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 556bca3be804..e53db7c1bdc0 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -236,6 +236,28 @@
> #define XY_FAST_COLOR_BLT_DW 16
> #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
> #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
> +
> +#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20)
> +#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13)
> +#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \
> + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)
> +#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \
> + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)
> +#define LINEAR 0
> +#define TILE_X 0x1
> +#define XMAJOR 0x1
> +#define YMAJOR 0x2
> +#define TILE_64 0x3
> +#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)
> +#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)
> +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
> +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
> +/* Note: MOCS value = (index << 1) */
> +#define BLIT_CCTL_SRC_MOCS(idx) \
> + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, idx << 1)
> +#define BLIT_CCTL_DST_MOCS(idx) \
> + REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, idx << 1)
> +
> #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
> #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
> #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22)
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for drm/i915: Enable Tile4 tiling mode
2022-05-11 14:22 [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode Nirmoy Das
2022-05-11 14:26 ` Das, Nirmoy
@ 2022-05-11 17:04 ` Patchwork
2022-05-11 17:28 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-05-11 17:04 UTC (permalink / raw)
To: Nirmoy Das; +Cc: intel-gfx
== Series Details ==
Series: drm/i915: Enable Tile4 tiling mode
URL : https://patchwork.freedesktop.org/series/103881/
State : warning
== Summary ==
Error: dim checkpatch failed
aafe76362d88 drm/i915: Enable Tile4 tiling mode
-:360: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'idx' may be better as '(idx)' to avoid precedence issues
#360: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:256:
+#define BLIT_CCTL_SRC_MOCS(idx) \
+ REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, idx << 1)
-:362: CHECK:MACRO_ARG_PRECEDENCE: Macro argument 'idx' may be better as '(idx)' to avoid precedence issues
#362: FILE: drivers/gpu/drm/i915/gt/intel_gpu_commands.h:258:
+#define BLIT_CCTL_DST_MOCS(idx) \
+ REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, idx << 1)
total: 0 errors, 0 warnings, 2 checks, 336 lines checked
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] ✗ Fi.CI.BAT: failure for drm/i915: Enable Tile4 tiling mode
2022-05-11 14:22 [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode Nirmoy Das
2022-05-11 14:26 ` Das, Nirmoy
2022-05-11 17:04 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
@ 2022-05-11 17:28 ` Patchwork
2 siblings, 0 replies; 7+ messages in thread
From: Patchwork @ 2022-05-11 17:28 UTC (permalink / raw)
To: Nirmoy Das; +Cc: intel-gfx
[-- Attachment #1: Type: text/plain, Size: 14422 bytes --]
== Series Details ==
Series: drm/i915: Enable Tile4 tiling mode
URL : https://patchwork.freedesktop.org/series/103881/
State : failure
== Summary ==
CI Bug Log - changes from CI_DRM_11636 -> Patchwork_103881v1
====================================================
Summary
-------
**FAILURE**
Serious unknown changes coming with Patchwork_103881v1 absolutely need to be
verified manually.
If you think the reported changes have nothing to do with the changes
introduced in Patchwork_103881v1, please notify your bug team to allow them
to document this new failure mode, which will reduce false positives in CI.
External URL: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/index.html
Participating hosts (41 -> 41)
------------------------------
Additional (5): fi-hsw-g3258 bat-adlp-4 fi-hsw-4770 bat-jsl-2 fi-skl-6600u
Missing (5): bat-adlm-1 fi-bsw-cyan bat-dg2-9 fi-ctg-p8600 fi-bdw-samus
Possible new issues
-------------------
Here are the unknown changes that may have been introduced in Patchwork_103881v1:
### IGT changes ###
#### Possible regressions ####
* igt@i915_selftest@live@client:
- bat-adlp-4: NOTRUN -> [DMESG-FAIL][1]
[1]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/bat-adlp-4/igt@i915_selftest@live@client.html
- fi-adl-ddr5: [PASS][2] -> [DMESG-FAIL][3]
[2]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11636/fi-adl-ddr5/igt@i915_selftest@live@client.html
[3]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-adl-ddr5/igt@i915_selftest@live@client.html
#### Suppressed ####
The following results come from untrusted machines, tests, or statuses.
They do not affect the overall result.
* igt@i915_selftest@live@client:
- {fi-tgl-dsi}: [PASS][4] -> [DMESG-FAIL][5]
[4]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11636/fi-tgl-dsi/igt@i915_selftest@live@client.html
[5]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-tgl-dsi/igt@i915_selftest@live@client.html
Known issues
------------
Here are the changes found in Patchwork_103881v1 that come from known issues:
### IGT changes ###
#### Issues hit ####
* igt@gem_huc_copy@huc-copy:
- fi-skl-6600u: NOTRUN -> [SKIP][6] ([fdo#109271] / [i915#2190])
[6]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-skl-6600u/igt@gem_huc_copy@huc-copy.html
- fi-hsw-4770: NOTRUN -> [SKIP][7] ([fdo#109271]) +9 similar issues
[7]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-hsw-4770/igt@gem_huc_copy@huc-copy.html
* igt@gem_lmem_swapping@basic:
- bat-adlp-4: NOTRUN -> [SKIP][8] ([i915#4613]) +3 similar issues
[8]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/bat-adlp-4/igt@gem_lmem_swapping@basic.html
* igt@gem_lmem_swapping@verify-random:
- fi-skl-6600u: NOTRUN -> [SKIP][9] ([fdo#109271] / [i915#4613]) +3 similar issues
[9]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-skl-6600u/igt@gem_lmem_swapping@verify-random.html
* igt@gem_tiled_pread_basic:
- bat-adlp-4: NOTRUN -> [SKIP][10] ([i915#3282])
[10]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/bat-adlp-4/igt@gem_tiled_pread_basic.html
* igt@i915_module_load@reload:
- fi-kbl-soraka: [PASS][11] -> [DMESG-WARN][12] ([i915#1982])
[11]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11636/fi-kbl-soraka/igt@i915_module_load@reload.html
[12]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-kbl-soraka/igt@i915_module_load@reload.html
* igt@i915_pm_backlight@basic-brightness:
- fi-hsw-4770: NOTRUN -> [SKIP][13] ([fdo#109271] / [i915#3012])
[13]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-hsw-4770/igt@i915_pm_backlight@basic-brightness.html
- fi-hsw-g3258: NOTRUN -> [SKIP][14] ([fdo#109271] / [i915#3012])
[14]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-hsw-g3258/igt@i915_pm_backlight@basic-brightness.html
* igt@i915_pm_rpm@module-reload:
- fi-cfl-8109u: [PASS][15] -> [DMESG-FAIL][16] ([i915#62])
[15]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11636/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
[16]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-cfl-8109u/igt@i915_pm_rpm@module-reload.html
* igt@i915_selftest@live@hangcheck:
- fi-bdw-5557u: NOTRUN -> [INCOMPLETE][17] ([i915#3921])
[17]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-bdw-5557u/igt@i915_selftest@live@hangcheck.html
* igt@i915_selftest@live@memory_region:
- fi-cfl-8109u: [PASS][18] -> [DMESG-WARN][19] ([i915#5904]) +11 similar issues
[18]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11636/fi-cfl-8109u/igt@i915_selftest@live@memory_region.html
[19]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-cfl-8109u/igt@i915_selftest@live@memory_region.html
* igt@i915_selftest@live@requests:
- fi-blb-e6850: [PASS][20] -> [DMESG-FAIL][21] ([i915#4528])
[20]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11636/fi-blb-e6850/igt@i915_selftest@live@requests.html
[21]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-blb-e6850/igt@i915_selftest@live@requests.html
* igt@kms_chamelium@common-hpd-after-suspend:
- fi-hsw-4770: NOTRUN -> [SKIP][22] ([fdo#109271] / [fdo#111827]) +8 similar issues
[22]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-hsw-4770/igt@kms_chamelium@common-hpd-after-suspend.html
- fi-bsw-kefka: NOTRUN -> [SKIP][23] ([fdo#109271] / [fdo#111827])
[23]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-bsw-kefka/igt@kms_chamelium@common-hpd-after-suspend.html
- fi-snb-2600: NOTRUN -> [SKIP][24] ([fdo#109271] / [fdo#111827])
[24]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-snb-2600/igt@kms_chamelium@common-hpd-after-suspend.html
* igt@kms_chamelium@dp-crc-fast:
- bat-adlp-4: NOTRUN -> [SKIP][25] ([fdo#111827]) +8 similar issues
[25]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/bat-adlp-4/igt@kms_chamelium@dp-crc-fast.html
* igt@kms_chamelium@vga-edid-read:
- fi-skl-6600u: NOTRUN -> [SKIP][26] ([fdo#109271] / [fdo#111827]) +8 similar issues
[26]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-skl-6600u/igt@kms_chamelium@vga-edid-read.html
- fi-hsw-g3258: NOTRUN -> [SKIP][27] ([fdo#109271] / [fdo#111827]) +8 similar issues
[27]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-hsw-g3258/igt@kms_chamelium@vga-edid-read.html
* igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy:
- fi-skl-6600u: NOTRUN -> [SKIP][28] ([fdo#109271]) +6 similar issues
[28]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-skl-6600u/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
- bat-adlp-4: NOTRUN -> [SKIP][29] ([i915#4103]) +1 similar issue
[29]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/bat-adlp-4/igt@kms_cursor_legacy@basic-busy-flip-before-cursor-legacy.html
* igt@kms_flip@basic-flip-vs-modeset@b-edp1:
- bat-adlp-4: NOTRUN -> [DMESG-WARN][30] ([i915#3576]) +3 similar issues
[30]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/bat-adlp-4/igt@kms_flip@basic-flip-vs-modeset@b-edp1.html
* igt@kms_force_connector_basic@prune-stale-modes:
- bat-adlp-4: NOTRUN -> [SKIP][31] ([i915#4093]) +3 similar issues
[31]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/bat-adlp-4/igt@kms_force_connector_basic@prune-stale-modes.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b:
- fi-cfl-8109u: [PASS][32] -> [DMESG-WARN][33] ([i915#62]) +14 similar issues
[32]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11636/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
[33]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-cfl-8109u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-b.html
* igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d:
- fi-hsw-g3258: NOTRUN -> [SKIP][34] ([fdo#109271] / [i915#533])
[34]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-hsw-g3258/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-hsw-4770: NOTRUN -> [SKIP][35] ([fdo#109271] / [i915#533])
[35]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-hsw-4770/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
- fi-skl-6600u: NOTRUN -> [SKIP][36] ([fdo#109271] / [i915#533])
[36]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-skl-6600u/igt@kms_pipe_crc_basic@compare-crc-sanitycheck-pipe-d.html
* igt@kms_psr@primary_mmap_gtt:
- fi-hsw-g3258: NOTRUN -> [SKIP][37] ([fdo#109271] / [i915#1072]) +3 similar issues
[37]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-hsw-g3258/igt@kms_psr@primary_mmap_gtt.html
- fi-hsw-4770: NOTRUN -> [SKIP][38] ([fdo#109271] / [i915#1072]) +3 similar issues
[38]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-hsw-4770/igt@kms_psr@primary_mmap_gtt.html
* igt@kms_setmode@basic-clone-single-crtc:
- fi-hsw-g3258: NOTRUN -> [SKIP][39] ([fdo#109271]) +9 similar issues
[39]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-hsw-g3258/igt@kms_setmode@basic-clone-single-crtc.html
- bat-adlp-4: NOTRUN -> [SKIP][40] ([i915#3555] / [i915#4579])
[40]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/bat-adlp-4/igt@kms_setmode@basic-clone-single-crtc.html
* igt@prime_vgem@basic-fence-read:
- bat-adlp-4: NOTRUN -> [SKIP][41] ([i915#3291] / [i915#3708]) +2 similar issues
[41]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/bat-adlp-4/igt@prime_vgem@basic-fence-read.html
* igt@prime_vgem@basic-userptr:
- bat-adlp-4: NOTRUN -> [SKIP][42] ([i915#3301] / [i915#3708])
[42]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/bat-adlp-4/igt@prime_vgem@basic-userptr.html
#### Possible fixes ####
* igt@core_hotunplug@unbind-rebind:
- {bat-rpls-2}: [DMESG-WARN][43] ([i915#4391]) -> [PASS][44]
[43]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11636/bat-rpls-2/igt@core_hotunplug@unbind-rebind.html
[44]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/bat-rpls-2/igt@core_hotunplug@unbind-rebind.html
* igt@gem_exec_suspend@basic-s0@smem:
- fi-bsw-kefka: [INCOMPLETE][45] ([i915#4831]) -> [PASS][46]
[45]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11636/fi-bsw-kefka/igt@gem_exec_suspend@basic-s0@smem.html
[46]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-bsw-kefka/igt@gem_exec_suspend@basic-s0@smem.html
* igt@i915_selftest@live@coherency:
- fi-bdw-5557u: [INCOMPLETE][47] ([i915#5674] / [i915#5685]) -> [PASS][48]
[47]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11636/fi-bdw-5557u/igt@i915_selftest@live@coherency.html
[48]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-bdw-5557u/igt@i915_selftest@live@coherency.html
* igt@i915_selftest@live@hangcheck:
- fi-snb-2600: [INCOMPLETE][49] ([i915#3921]) -> [PASS][50]
[49]: https://intel-gfx-ci.01.org/tree/drm-tip/CI_DRM_11636/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
[50]: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/fi-snb-2600/igt@i915_selftest@live@hangcheck.html
{name}: This element is suppressed. This means it is ignored when computing
the status of the difference (SUCCESS, WARNING, or FAILURE).
[fdo#109271]: https://bugs.freedesktop.org/show_bug.cgi?id=109271
[fdo#109285]: https://bugs.freedesktop.org/show_bug.cgi?id=109285
[fdo#111827]: https://bugs.freedesktop.org/show_bug.cgi?id=111827
[i915#1072]: https://gitlab.freedesktop.org/drm/intel/issues/1072
[i915#1982]: https://gitlab.freedesktop.org/drm/intel/issues/1982
[i915#2190]: https://gitlab.freedesktop.org/drm/intel/issues/2190
[i915#3012]: https://gitlab.freedesktop.org/drm/intel/issues/3012
[i915#3282]: https://gitlab.freedesktop.org/drm/intel/issues/3282
[i915#3291]: https://gitlab.freedesktop.org/drm/intel/issues/3291
[i915#3301]: https://gitlab.freedesktop.org/drm/intel/issues/3301
[i915#3555]: https://gitlab.freedesktop.org/drm/intel/issues/3555
[i915#3576]: https://gitlab.freedesktop.org/drm/intel/issues/3576
[i915#3708]: https://gitlab.freedesktop.org/drm/intel/issues/3708
[i915#3921]: https://gitlab.freedesktop.org/drm/intel/issues/3921
[i915#4093]: https://gitlab.freedesktop.org/drm/intel/issues/4093
[i915#4103]: https://gitlab.freedesktop.org/drm/intel/issues/4103
[i915#4312]: https://gitlab.freedesktop.org/drm/intel/issues/4312
[i915#4391]: https://gitlab.freedesktop.org/drm/intel/issues/4391
[i915#4528]: https://gitlab.freedesktop.org/drm/intel/issues/4528
[i915#4579]: https://gitlab.freedesktop.org/drm/intel/issues/4579
[i915#4613]: https://gitlab.freedesktop.org/drm/intel/issues/4613
[i915#4831]: https://gitlab.freedesktop.org/drm/intel/issues/4831
[i915#5122]: https://gitlab.freedesktop.org/drm/intel/issues/5122
[i915#533]: https://gitlab.freedesktop.org/drm/intel/issues/533
[i915#5674]: https://gitlab.freedesktop.org/drm/intel/issues/5674
[i915#5685]: https://gitlab.freedesktop.org/drm/intel/issues/5685
[i915#5885]: https://gitlab.freedesktop.org/drm/intel/issues/5885
[i915#5904]: https://gitlab.freedesktop.org/drm/intel/issues/5904
[i915#62]: https://gitlab.freedesktop.org/drm/intel/issues/62
Build changes
-------------
* Linux: CI_DRM_11636 -> Patchwork_103881v1
CI-20190529: 20190529
CI_DRM_11636: 33aecbb0608df8e3e541c2cd8e43f1a87d1aca7c @ git://anongit.freedesktop.org/gfx-ci/linux
IGT_6471: 1d6816f1200520f936a799b7b0ef2e6f396abb16 @ https://gitlab.freedesktop.org/drm/igt-gpu-tools.git
Patchwork_103881v1: 33aecbb0608df8e3e541c2cd8e43f1a87d1aca7c @ git://anongit.freedesktop.org/gfx-ci/linux
### Linux commits
b68defbdb9a5 drm/i915: Enable Tile4 tiling mode
== Logs ==
For more details see: https://intel-gfx-ci.01.org/tree/drm-tip/Patchwork_103881v1/index.html
[-- Attachment #2: Type: text/html, Size: 17612 bytes --]
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode
2022-05-13 5:47 ` Zbigniew Kempczyński
@ 2022-05-13 7:50 ` Das, Nirmoy
0 siblings, 0 replies; 7+ messages in thread
From: Das, Nirmoy @ 2022-05-13 7:50 UTC (permalink / raw)
To: Zbigniew Kempczyński
Cc: krishnaiah.bommu, intel-gfx, matthew.auld, chris.p.wilson
On 5/13/2022 7:47 AM, Zbigniew Kempczyński wrote:
> On Thu, May 12, 2022 at 03:26:00PM +0200, Nirmoy Das wrote:
>> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>>
>> Enable Tile4 tiling mode on platform that supports
>> Tile4 but no TileY like DG2.
>>
>> v2: disable X-tile for iGPU in fastblit
>> fix checkpath --strict warnings
>>
>> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>> Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
>> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
>> ---
>> .../i915/gem/selftests/i915_gem_client_blt.c | 235 ++++++++++++++----
>> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++
>> 2 files changed, 212 insertions(+), 45 deletions(-)
>>
>> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
>> index ddd0772fd828..e16661029c78 100644
>> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
>> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
>> @@ -6,6 +6,7 @@
>> #include "i915_selftest.h"
>>
>> #include "gt/intel_context.h"
>> +#include "gt/intel_engine_regs.h"
>> #include "gt/intel_engine_user.h"
>> #include "gt/intel_gpu_commands.h"
>> #include "gt/intel_gt.h"
>> @@ -18,10 +19,71 @@
>> #include "huge_gem_object.h"
>> #include "mock_context.h"
>>
>> +#define OW_SIZE 16 /* in bytes */
>> +#define F_SUBTILE_SIZE 64 /* in bytes */
>> +#define F_TILE_WIDTH 128 /* in bytes */
>> +#define F_TILE_HEIGHT 32 /* in pixels */
>> +#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */
>> +#define F_SUBTILE_HEIGHT 4 /* in pixels */
>> +
>> +static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp)
>> +{
>> + int tile_base;
>> + int tile_x, tile_y;
>> + int swizzle, subtile;
>> + int pixel_size = bpp / 8;
>> + int pos;
>> +
>> + /*
>> + * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a
>> + * so we can use the same table to tile and until.
>> + */
>> + static const u8 f_subtile_map[] = {
>> + 0, 1, 2, 3, 8, 9, 10, 11,
>> + 4, 5, 6, 7, 12, 13, 14, 15,
>> + 16, 17, 18, 19, 24, 25, 26, 27,
>> + 20, 21, 22, 23, 28, 29, 30, 31,
>> + 32, 33, 34, 35, 40, 41, 42, 43,
>> + 36, 37, 38, 39, 44, 45, 46, 47,
>> + 48, 49, 50, 51, 56, 57, 58, 59,
>> + 52, 53, 54, 55, 60, 61, 62, 63
>> + };
>> +
>> + x *= pixel_size;
>> + /*
>> + * Where does the 4k tile start (in bytes)? This is the same for Y and
>> + * F so we can use the Y-tile algorithm to get to that point.
>> + */
>> + tile_base =
>> + y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT +
>> + x / F_TILE_WIDTH * 4096;
>> +
>> + /* Find pixel within tile */
>> + tile_x = x % F_TILE_WIDTH;
>> + tile_y = y % F_TILE_HEIGHT;
>> +
>> + /* And figure out the subtile within the 4k tile */
>> + subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH;
>> +
>> + /* Swizzle the subtile number according to the bspec diagram */
>> + swizzle = f_subtile_map[subtile];
>> +
>> + /* Calculate new position */
>> + pos = tile_base +
>> + swizzle * F_SUBTILE_SIZE +
>> + tile_y % F_SUBTILE_HEIGHT * OW_SIZE +
>> + tile_x % F_SUBTILE_WIDTH;
>> +
>> + GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size));
>> +
>> + return pos / pixel_size * 4;
>> +}
>> +
>> enum client_tiling {
>> CLIENT_TILING_LINEAR,
>> CLIENT_TILING_X,
>> CLIENT_TILING_Y,
>> + CLIENT_TILING_4,
>> CLIENT_NUM_TILING_TYPES
>> };
>>
>> @@ -45,6 +107,21 @@ struct tiled_blits {
>> u32 height;
>> };
>>
>> +static bool fast_blit_ok(struct blit_buffer *buf)
>> +{
>> + int gen = GRAPHICS_VER(buf->vma->vm->i915);
>> +
>> + if (gen < 9)
>> + return false;
>> +
>> + if (gen < 12)
>> + return true;
>> +
>> + /* filter out platforms with unsupported X-tile support(iGPUs and DG1) in fastblit */
>> + return !((IS_DG1(buf->vma->vm->i915) || (gen == 12 && !HAS_LMEM(buf->vma->vm->i915))) &&
>> + buf->tiling == CLIENT_TILING_X);
>> +}
>> +
> What would you say for this:
>
> static bool supports_x_tiling(const struct drm_i915_private *i915)
> {
> int gen = GRAPHICS_VER(i915);
>
> if (gen < 12)
> return true;
>
> if (!HAS_LMEM(i915) || IS_DG1(i915))
> return false;
>
> return true;
> }
>
> static bool fast_blit_ok(const struct blit_buffer *buf)
> {
> int gen = GRAPHICS_VER(buf->vma->vm->i915);
>
> if (gen < 9)
> return false;
>
> if (gen < 12)
> return true;
>
> /* filter out platforms with unsupported X-tile support in fastblit */
> if (buf->tiling == CLIENT_TILING_X && !supports_x_tiling(buf->vma->vm->i915))
> return false;
>
> return true;
> }
Looks better, I resend with that.
Thanks,
Nirmoy
>
> Rest code looks good to me.
>
> --
> Zbigniew
>
>> static int prepare_blit(const struct tiled_blits *t,
>> struct blit_buffer *dst,
>> struct blit_buffer *src,
>> @@ -59,51 +136,103 @@ static int prepare_blit(const struct tiled_blits *t,
>> if (IS_ERR(cs))
>> return PTR_ERR(cs);
>>
>> - *cs++ = MI_LOAD_REGISTER_IMM(1);
>> - *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
>> - cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
>> - if (src->tiling == CLIENT_TILING_Y)
>> - cmd |= BCS_SRC_Y;
>> - if (dst->tiling == CLIENT_TILING_Y)
>> - cmd |= BCS_DST_Y;
>> - *cs++ = cmd;
>> -
>> - cmd = MI_FLUSH_DW;
>> - if (ver >= 8)
>> - cmd++;
>> - *cs++ = cmd;
>> - *cs++ = 0;
>> - *cs++ = 0;
>> - *cs++ = 0;
>> -
>> - cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
>> - if (ver >= 8)
>> - cmd += 2;
>> -
>> - src_pitch = t->width * 4;
>> - if (src->tiling) {
>> - cmd |= XY_SRC_COPY_BLT_SRC_TILED;
>> - src_pitch /= 4;
>> - }
>> + if (fast_blit_ok(dst) && fast_blit_ok(src)) {
>> + struct intel_gt *gt = t->ce->engine->gt;
>> + u32 src_tiles = 0, dst_tiles = 0;
>> + u32 src_4t = 0, dst_4t = 0;
>> +
>> + /* Need to program BLIT_CCTL if it is not done previously
>> + * before using XY_FAST_COPY_BLT
>> + */
>> + *cs++ = MI_LOAD_REGISTER_IMM(1);
>> + *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));
>> + *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) |
>> + BLIT_CCTL_DST_MOCS(gt->mocs.uc_index));
>> +
>> + src_pitch = t->width; /* in dwords */
>> + if (src->tiling == CLIENT_TILING_4) {
>> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
>> + src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
>> + } else if (src->tiling == CLIENT_TILING_Y) {
>> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
>> + } else if (src->tiling == CLIENT_TILING_X) {
>> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
>> + } else {
>> + src_pitch *= 4; /* in bytes */
>> + }
>>
>> - dst_pitch = t->width * 4;
>> - if (dst->tiling) {
>> - cmd |= XY_SRC_COPY_BLT_DST_TILED;
>> - dst_pitch /= 4;
>> - }
>> + dst_pitch = t->width; /* in dwords */
>> + if (dst->tiling == CLIENT_TILING_4) {
>> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
>> + dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
>> + } else if (dst->tiling == CLIENT_TILING_Y) {
>> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
>> + } else if (dst->tiling == CLIENT_TILING_X) {
>> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
>> + } else {
>> + dst_pitch *= 4; /* in bytes */
>> + }
>>
>> - *cs++ = cmd;
>> - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
>> - *cs++ = 0;
>> - *cs++ = t->height << 16 | t->width;
>> - *cs++ = lower_32_bits(dst->vma->node.start);
>> - if (use_64b_reloc)
>> + *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) |
>> + src_tiles | dst_tiles;
>> + *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch;
>> + *cs++ = 0;
>> + *cs++ = t->height << 16 | t->width;
>> + *cs++ = lower_32_bits(dst->vma->node.start);
>> *cs++ = upper_32_bits(dst->vma->node.start);
>> - *cs++ = 0;
>> - *cs++ = src_pitch;
>> - *cs++ = lower_32_bits(src->vma->node.start);
>> - if (use_64b_reloc)
>> + *cs++ = 0;
>> + *cs++ = src_pitch;
>> + *cs++ = lower_32_bits(src->vma->node.start);
>> *cs++ = upper_32_bits(src->vma->node.start);
>> + } else {
>> + if (ver >= 6) {
>> + *cs++ = MI_LOAD_REGISTER_IMM(1);
>> + *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
>> + cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
>> + if (src->tiling == CLIENT_TILING_Y)
>> + cmd |= BCS_SRC_Y;
>> + if (dst->tiling == CLIENT_TILING_Y)
>> + cmd |= BCS_DST_Y;
>> + *cs++ = cmd;
>> +
>> + cmd = MI_FLUSH_DW;
>> + if (ver >= 8)
>> + cmd++;
>> + *cs++ = cmd;
>> + *cs++ = 0;
>> + *cs++ = 0;
>> + *cs++ = 0;
>> + }
>> +
>> + cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
>> + if (ver >= 8)
>> + cmd += 2;
>> +
>> + src_pitch = t->width * 4;
>> + if (src->tiling) {
>> + cmd |= XY_SRC_COPY_BLT_SRC_TILED;
>> + src_pitch /= 4;
>> + }
>> +
>> + dst_pitch = t->width * 4;
>> + if (dst->tiling) {
>> + cmd |= XY_SRC_COPY_BLT_DST_TILED;
>> + dst_pitch /= 4;
>> + }
>> +
>> + *cs++ = cmd;
>> + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
>> + *cs++ = 0;
>> + *cs++ = t->height << 16 | t->width;
>> + *cs++ = lower_32_bits(dst->vma->node.start);
>> + if (use_64b_reloc)
>> + *cs++ = upper_32_bits(dst->vma->node.start);
>> + *cs++ = 0;
>> + *cs++ = src_pitch;
>> + *cs++ = lower_32_bits(src->vma->node.start);
>> + if (use_64b_reloc)
>> + *cs++ = upper_32_bits(src->vma->node.start);
>> + }
>>
>> *cs++ = MI_BATCH_BUFFER_END;
>>
>> @@ -181,7 +310,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
>>
>> t->buffers[i].vma = vma;
>> t->buffers[i].tiling =
>> - i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
>> + i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng);
>> +
>> + /* Platforms support either TileY or Tile4, not both */
>> + if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y)
>> + t->buffers[i].tiling = CLIENT_TILING_4;
>> + else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4)
>> + t->buffers[i].tiling = CLIENT_TILING_Y;
>> }
>>
>> return 0;
>> @@ -206,7 +341,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
>> static u64 tiled_offset(const struct intel_gt *gt,
>> u64 v,
>> unsigned int stride,
>> - enum client_tiling tiling)
>> + enum client_tiling tiling,
>> + int x_pos, int y_pos)
>> {
>> unsigned int swizzle;
>> u64 x, y;
>> @@ -216,7 +352,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
>>
>> y = div64_u64_rem(v, stride, &x);
>>
>> - if (tiling == CLIENT_TILING_X) {
>> + if (tiling == CLIENT_TILING_4) {
>> + v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
>> +
>> + /* no swizzling for f-tiling */
>> + swizzle = I915_BIT_6_SWIZZLE_NONE;
>> + } else if (tiling == CLIENT_TILING_X) {
>> v = div64_u64_rem(y, 8, &y) * stride * 8;
>> v += y * 512;
>> v += div64_u64_rem(x, 512, &x) << 12;
>> @@ -259,6 +400,7 @@ static const char *repr_tiling(enum client_tiling tiling)
>> case CLIENT_TILING_LINEAR: return "linear";
>> case CLIENT_TILING_X: return "X";
>> case CLIENT_TILING_Y: return "Y";
>> + case CLIENT_TILING_4: return "F";
>> default: return "unknown";
>> }
>> }
>> @@ -284,7 +426,7 @@ static int verify_buffer(const struct tiled_blits *t,
>> } else {
>> u64 v = tiled_offset(buf->vma->vm->gt,
>> p * 4, t->width * 4,
>> - buf->tiling);
>> + buf->tiling, x, y);
>>
>> if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p)
>> ret = -EINVAL;
>> @@ -504,6 +646,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)
>> if (err)
>> return err;
>>
>> + /* Simulating GTT eviction of the same buffer / layout */
>> + t->buffers[2].tiling = t->buffers[0].tiling;
>> +
>> /* Reposition so that we overlap the old addresses, and slightly off */
>> err = tiled_blit(t,
>> &t->buffers[2], t->hole + t->align,
>> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>> index 556bca3be804..246ab8f7bf57 100644
>> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
>> @@ -236,6 +236,28 @@
>> #define XY_FAST_COLOR_BLT_DW 16
>> #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
>> #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
>> +
>> +#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20)
>> +#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13)
>> +#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \
>> + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)
>> +#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \
>> + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)
>> +#define LINEAR 0
>> +#define TILE_X 0x1
>> +#define XMAJOR 0x1
>> +#define YMAJOR 0x2
>> +#define TILE_64 0x3
>> +#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)
>> +#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)
>> +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
>> +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
>> +/* Note: MOCS value = (index << 1) */
>> +#define BLIT_CCTL_SRC_MOCS(idx) \
>> + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1)
>> +#define BLIT_CCTL_DST_MOCS(idx) \
>> + REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1)
>> +
>> #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
>> #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
>> #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22)
>> --
>> 2.35.1
>>
^ permalink raw reply [flat|nested] 7+ messages in thread
* Re: [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode
2022-05-12 13:26 [Intel-gfx] [PATCH] " Nirmoy Das
@ 2022-05-13 5:47 ` Zbigniew Kempczyński
2022-05-13 7:50 ` Das, Nirmoy
0 siblings, 1 reply; 7+ messages in thread
From: Zbigniew Kempczyński @ 2022-05-13 5:47 UTC (permalink / raw)
To: Nirmoy Das; +Cc: krishnaiah.bommu, intel-gfx, matthew.auld, chris.p.wilson
On Thu, May 12, 2022 at 03:26:00PM +0200, Nirmoy Das wrote:
> From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
>
> Enable Tile4 tiling mode on platform that supports
> Tile4 but no TileY like DG2.
>
> v2: disable X-tile for iGPU in fastblit
> fix checkpath --strict warnings
>
> Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
> Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
> Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
> ---
> .../i915/gem/selftests/i915_gem_client_blt.c | 235 ++++++++++++++----
> drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++
> 2 files changed, 212 insertions(+), 45 deletions(-)
>
> diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> index ddd0772fd828..e16661029c78 100644
> --- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> +++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
> @@ -6,6 +6,7 @@
> #include "i915_selftest.h"
>
> #include "gt/intel_context.h"
> +#include "gt/intel_engine_regs.h"
> #include "gt/intel_engine_user.h"
> #include "gt/intel_gpu_commands.h"
> #include "gt/intel_gt.h"
> @@ -18,10 +19,71 @@
> #include "huge_gem_object.h"
> #include "mock_context.h"
>
> +#define OW_SIZE 16 /* in bytes */
> +#define F_SUBTILE_SIZE 64 /* in bytes */
> +#define F_TILE_WIDTH 128 /* in bytes */
> +#define F_TILE_HEIGHT 32 /* in pixels */
> +#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */
> +#define F_SUBTILE_HEIGHT 4 /* in pixels */
> +
> +static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp)
> +{
> + int tile_base;
> + int tile_x, tile_y;
> + int swizzle, subtile;
> + int pixel_size = bpp / 8;
> + int pos;
> +
> + /*
> + * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a
> + * so we can use the same table to tile and until.
> + */
> + static const u8 f_subtile_map[] = {
> + 0, 1, 2, 3, 8, 9, 10, 11,
> + 4, 5, 6, 7, 12, 13, 14, 15,
> + 16, 17, 18, 19, 24, 25, 26, 27,
> + 20, 21, 22, 23, 28, 29, 30, 31,
> + 32, 33, 34, 35, 40, 41, 42, 43,
> + 36, 37, 38, 39, 44, 45, 46, 47,
> + 48, 49, 50, 51, 56, 57, 58, 59,
> + 52, 53, 54, 55, 60, 61, 62, 63
> + };
> +
> + x *= pixel_size;
> + /*
> + * Where does the 4k tile start (in bytes)? This is the same for Y and
> + * F so we can use the Y-tile algorithm to get to that point.
> + */
> + tile_base =
> + y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT +
> + x / F_TILE_WIDTH * 4096;
> +
> + /* Find pixel within tile */
> + tile_x = x % F_TILE_WIDTH;
> + tile_y = y % F_TILE_HEIGHT;
> +
> + /* And figure out the subtile within the 4k tile */
> + subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH;
> +
> + /* Swizzle the subtile number according to the bspec diagram */
> + swizzle = f_subtile_map[subtile];
> +
> + /* Calculate new position */
> + pos = tile_base +
> + swizzle * F_SUBTILE_SIZE +
> + tile_y % F_SUBTILE_HEIGHT * OW_SIZE +
> + tile_x % F_SUBTILE_WIDTH;
> +
> + GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size));
> +
> + return pos / pixel_size * 4;
> +}
> +
> enum client_tiling {
> CLIENT_TILING_LINEAR,
> CLIENT_TILING_X,
> CLIENT_TILING_Y,
> + CLIENT_TILING_4,
> CLIENT_NUM_TILING_TYPES
> };
>
> @@ -45,6 +107,21 @@ struct tiled_blits {
> u32 height;
> };
>
> +static bool fast_blit_ok(struct blit_buffer *buf)
> +{
> + int gen = GRAPHICS_VER(buf->vma->vm->i915);
> +
> + if (gen < 9)
> + return false;
> +
> + if (gen < 12)
> + return true;
> +
> + /* filter out platforms with unsupported X-tile support(iGPUs and DG1) in fastblit */
> + return !((IS_DG1(buf->vma->vm->i915) || (gen == 12 && !HAS_LMEM(buf->vma->vm->i915))) &&
> + buf->tiling == CLIENT_TILING_X);
> +}
> +
What would you say for this:
static bool supports_x_tiling(const struct drm_i915_private *i915)
{
int gen = GRAPHICS_VER(i915);
if (gen < 12)
return true;
if (!HAS_LMEM(i915) || IS_DG1(i915))
return false;
return true;
}
static bool fast_blit_ok(const struct blit_buffer *buf)
{
int gen = GRAPHICS_VER(buf->vma->vm->i915);
if (gen < 9)
return false;
if (gen < 12)
return true;
/* filter out platforms with unsupported X-tile support in fastblit */
if (buf->tiling == CLIENT_TILING_X && !supports_x_tiling(buf->vma->vm->i915))
return false;
return true;
}
Rest code looks good to me.
--
Zbigniew
> static int prepare_blit(const struct tiled_blits *t,
> struct blit_buffer *dst,
> struct blit_buffer *src,
> @@ -59,51 +136,103 @@ static int prepare_blit(const struct tiled_blits *t,
> if (IS_ERR(cs))
> return PTR_ERR(cs);
>
> - *cs++ = MI_LOAD_REGISTER_IMM(1);
> - *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
> - cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
> - if (src->tiling == CLIENT_TILING_Y)
> - cmd |= BCS_SRC_Y;
> - if (dst->tiling == CLIENT_TILING_Y)
> - cmd |= BCS_DST_Y;
> - *cs++ = cmd;
> -
> - cmd = MI_FLUSH_DW;
> - if (ver >= 8)
> - cmd++;
> - *cs++ = cmd;
> - *cs++ = 0;
> - *cs++ = 0;
> - *cs++ = 0;
> -
> - cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
> - if (ver >= 8)
> - cmd += 2;
> -
> - src_pitch = t->width * 4;
> - if (src->tiling) {
> - cmd |= XY_SRC_COPY_BLT_SRC_TILED;
> - src_pitch /= 4;
> - }
> + if (fast_blit_ok(dst) && fast_blit_ok(src)) {
> + struct intel_gt *gt = t->ce->engine->gt;
> + u32 src_tiles = 0, dst_tiles = 0;
> + u32 src_4t = 0, dst_4t = 0;
> +
> + /* Need to program BLIT_CCTL if it is not done previously
> + * before using XY_FAST_COPY_BLT
> + */
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));
> + *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) |
> + BLIT_CCTL_DST_MOCS(gt->mocs.uc_index));
> +
> + src_pitch = t->width; /* in dwords */
> + if (src->tiling == CLIENT_TILING_4) {
> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
> + src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
> + } else if (src->tiling == CLIENT_TILING_Y) {
> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
> + } else if (src->tiling == CLIENT_TILING_X) {
> + src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
> + } else {
> + src_pitch *= 4; /* in bytes */
> + }
>
> - dst_pitch = t->width * 4;
> - if (dst->tiling) {
> - cmd |= XY_SRC_COPY_BLT_DST_TILED;
> - dst_pitch /= 4;
> - }
> + dst_pitch = t->width; /* in dwords */
> + if (dst->tiling == CLIENT_TILING_4) {
> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
> + dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
> + } else if (dst->tiling == CLIENT_TILING_Y) {
> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
> + } else if (dst->tiling == CLIENT_TILING_X) {
> + dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
> + } else {
> + dst_pitch *= 4; /* in bytes */
> + }
>
> - *cs++ = cmd;
> - *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
> - *cs++ = 0;
> - *cs++ = t->height << 16 | t->width;
> - *cs++ = lower_32_bits(dst->vma->node.start);
> - if (use_64b_reloc)
> + *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) |
> + src_tiles | dst_tiles;
> + *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch;
> + *cs++ = 0;
> + *cs++ = t->height << 16 | t->width;
> + *cs++ = lower_32_bits(dst->vma->node.start);
> *cs++ = upper_32_bits(dst->vma->node.start);
> - *cs++ = 0;
> - *cs++ = src_pitch;
> - *cs++ = lower_32_bits(src->vma->node.start);
> - if (use_64b_reloc)
> + *cs++ = 0;
> + *cs++ = src_pitch;
> + *cs++ = lower_32_bits(src->vma->node.start);
> *cs++ = upper_32_bits(src->vma->node.start);
> + } else {
> + if (ver >= 6) {
> + *cs++ = MI_LOAD_REGISTER_IMM(1);
> + *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
> + cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
> + if (src->tiling == CLIENT_TILING_Y)
> + cmd |= BCS_SRC_Y;
> + if (dst->tiling == CLIENT_TILING_Y)
> + cmd |= BCS_DST_Y;
> + *cs++ = cmd;
> +
> + cmd = MI_FLUSH_DW;
> + if (ver >= 8)
> + cmd++;
> + *cs++ = cmd;
> + *cs++ = 0;
> + *cs++ = 0;
> + *cs++ = 0;
> + }
> +
> + cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
> + if (ver >= 8)
> + cmd += 2;
> +
> + src_pitch = t->width * 4;
> + if (src->tiling) {
> + cmd |= XY_SRC_COPY_BLT_SRC_TILED;
> + src_pitch /= 4;
> + }
> +
> + dst_pitch = t->width * 4;
> + if (dst->tiling) {
> + cmd |= XY_SRC_COPY_BLT_DST_TILED;
> + dst_pitch /= 4;
> + }
> +
> + *cs++ = cmd;
> + *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
> + *cs++ = 0;
> + *cs++ = t->height << 16 | t->width;
> + *cs++ = lower_32_bits(dst->vma->node.start);
> + if (use_64b_reloc)
> + *cs++ = upper_32_bits(dst->vma->node.start);
> + *cs++ = 0;
> + *cs++ = src_pitch;
> + *cs++ = lower_32_bits(src->vma->node.start);
> + if (use_64b_reloc)
> + *cs++ = upper_32_bits(src->vma->node.start);
> + }
>
> *cs++ = MI_BATCH_BUFFER_END;
>
> @@ -181,7 +310,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
>
> t->buffers[i].vma = vma;
> t->buffers[i].tiling =
> - i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
> + i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng);
> +
> + /* Platforms support either TileY or Tile4, not both */
> + if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y)
> + t->buffers[i].tiling = CLIENT_TILING_4;
> + else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4)
> + t->buffers[i].tiling = CLIENT_TILING_Y;
> }
>
> return 0;
> @@ -206,7 +341,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
> static u64 tiled_offset(const struct intel_gt *gt,
> u64 v,
> unsigned int stride,
> - enum client_tiling tiling)
> + enum client_tiling tiling,
> + int x_pos, int y_pos)
> {
> unsigned int swizzle;
> u64 x, y;
> @@ -216,7 +352,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
>
> y = div64_u64_rem(v, stride, &x);
>
> - if (tiling == CLIENT_TILING_X) {
> + if (tiling == CLIENT_TILING_4) {
> + v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
> +
> + /* no swizzling for f-tiling */
> + swizzle = I915_BIT_6_SWIZZLE_NONE;
> + } else if (tiling == CLIENT_TILING_X) {
> v = div64_u64_rem(y, 8, &y) * stride * 8;
> v += y * 512;
> v += div64_u64_rem(x, 512, &x) << 12;
> @@ -259,6 +400,7 @@ static const char *repr_tiling(enum client_tiling tiling)
> case CLIENT_TILING_LINEAR: return "linear";
> case CLIENT_TILING_X: return "X";
> case CLIENT_TILING_Y: return "Y";
> + case CLIENT_TILING_4: return "F";
> default: return "unknown";
> }
> }
> @@ -284,7 +426,7 @@ static int verify_buffer(const struct tiled_blits *t,
> } else {
> u64 v = tiled_offset(buf->vma->vm->gt,
> p * 4, t->width * 4,
> - buf->tiling);
> + buf->tiling, x, y);
>
> if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p)
> ret = -EINVAL;
> @@ -504,6 +646,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)
> if (err)
> return err;
>
> + /* Simulating GTT eviction of the same buffer / layout */
> + t->buffers[2].tiling = t->buffers[0].tiling;
> +
> /* Reposition so that we overlap the old addresses, and slightly off */
> err = tiled_blit(t,
> &t->buffers[2], t->hole + t->align,
> diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> index 556bca3be804..246ab8f7bf57 100644
> --- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> +++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
> @@ -236,6 +236,28 @@
> #define XY_FAST_COLOR_BLT_DW 16
> #define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
> #define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
> +
> +#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20)
> +#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13)
> +#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \
> + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)
> +#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \
> + REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)
> +#define LINEAR 0
> +#define TILE_X 0x1
> +#define XMAJOR 0x1
> +#define YMAJOR 0x2
> +#define TILE_64 0x3
> +#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)
> +#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)
> +#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
> +#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
> +/* Note: MOCS value = (index << 1) */
> +#define BLIT_CCTL_SRC_MOCS(idx) \
> + REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1)
> +#define BLIT_CCTL_DST_MOCS(idx) \
> + REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1)
> +
> #define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
> #define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
> #define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22)
> --
> 2.35.1
>
^ permalink raw reply [flat|nested] 7+ messages in thread
* [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode
@ 2022-05-12 13:26 Nirmoy Das
2022-05-13 5:47 ` Zbigniew Kempczyński
0 siblings, 1 reply; 7+ messages in thread
From: Nirmoy Das @ 2022-05-12 13:26 UTC (permalink / raw)
To: intel-gfx; +Cc: krishnaiah.bommu, matthew.auld, chris.p.wilson
From: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Enable Tile4 tiling mode on platform that supports
Tile4 but no TileY like DG2.
v2: disable X-tile for iGPU in fastblit
fix checkpath --strict warnings
Signed-off-by: Bommu Krishnaiah <krishnaiah.bommu@intel.com>
Co-developed-by: Nirmoy Das <nirmoy.das@intel.com>
Signed-off-by: Nirmoy Das <nirmoy.das@intel.com>
---
.../i915/gem/selftests/i915_gem_client_blt.c | 235 ++++++++++++++----
drivers/gpu/drm/i915/gt/intel_gpu_commands.h | 22 ++
2 files changed, 212 insertions(+), 45 deletions(-)
diff --git a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
index ddd0772fd828..e16661029c78 100644
--- a/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
+++ b/drivers/gpu/drm/i915/gem/selftests/i915_gem_client_blt.c
@@ -6,6 +6,7 @@
#include "i915_selftest.h"
#include "gt/intel_context.h"
+#include "gt/intel_engine_regs.h"
#include "gt/intel_engine_user.h"
#include "gt/intel_gpu_commands.h"
#include "gt/intel_gt.h"
@@ -18,10 +19,71 @@
#include "huge_gem_object.h"
#include "mock_context.h"
+#define OW_SIZE 16 /* in bytes */
+#define F_SUBTILE_SIZE 64 /* in bytes */
+#define F_TILE_WIDTH 128 /* in bytes */
+#define F_TILE_HEIGHT 32 /* in pixels */
+#define F_SUBTILE_WIDTH OW_SIZE /* in bytes */
+#define F_SUBTILE_HEIGHT 4 /* in pixels */
+
+static int linear_x_y_to_ftiled_pos(int x, int y, u32 stride, int bpp)
+{
+ int tile_base;
+ int tile_x, tile_y;
+ int swizzle, subtile;
+ int pixel_size = bpp / 8;
+ int pos;
+
+ /*
+ * Subtile remapping for F tile. Note that map[a]==b implies map[b]==a
+ * so we can use the same table to tile and until.
+ */
+ static const u8 f_subtile_map[] = {
+ 0, 1, 2, 3, 8, 9, 10, 11,
+ 4, 5, 6, 7, 12, 13, 14, 15,
+ 16, 17, 18, 19, 24, 25, 26, 27,
+ 20, 21, 22, 23, 28, 29, 30, 31,
+ 32, 33, 34, 35, 40, 41, 42, 43,
+ 36, 37, 38, 39, 44, 45, 46, 47,
+ 48, 49, 50, 51, 56, 57, 58, 59,
+ 52, 53, 54, 55, 60, 61, 62, 63
+ };
+
+ x *= pixel_size;
+ /*
+ * Where does the 4k tile start (in bytes)? This is the same for Y and
+ * F so we can use the Y-tile algorithm to get to that point.
+ */
+ tile_base =
+ y / F_TILE_HEIGHT * stride * F_TILE_HEIGHT +
+ x / F_TILE_WIDTH * 4096;
+
+ /* Find pixel within tile */
+ tile_x = x % F_TILE_WIDTH;
+ tile_y = y % F_TILE_HEIGHT;
+
+ /* And figure out the subtile within the 4k tile */
+ subtile = tile_y / F_SUBTILE_HEIGHT * 8 + tile_x / F_SUBTILE_WIDTH;
+
+ /* Swizzle the subtile number according to the bspec diagram */
+ swizzle = f_subtile_map[subtile];
+
+ /* Calculate new position */
+ pos = tile_base +
+ swizzle * F_SUBTILE_SIZE +
+ tile_y % F_SUBTILE_HEIGHT * OW_SIZE +
+ tile_x % F_SUBTILE_WIDTH;
+
+ GEM_BUG_ON(!IS_ALIGNED(pos, pixel_size));
+
+ return pos / pixel_size * 4;
+}
+
enum client_tiling {
CLIENT_TILING_LINEAR,
CLIENT_TILING_X,
CLIENT_TILING_Y,
+ CLIENT_TILING_4,
CLIENT_NUM_TILING_TYPES
};
@@ -45,6 +107,21 @@ struct tiled_blits {
u32 height;
};
+static bool fast_blit_ok(struct blit_buffer *buf)
+{
+ int gen = GRAPHICS_VER(buf->vma->vm->i915);
+
+ if (gen < 9)
+ return false;
+
+ if (gen < 12)
+ return true;
+
+ /* filter out platforms with unsupported X-tile support(iGPUs and DG1) in fastblit */
+ return !((IS_DG1(buf->vma->vm->i915) || (gen == 12 && !HAS_LMEM(buf->vma->vm->i915))) &&
+ buf->tiling == CLIENT_TILING_X);
+}
+
static int prepare_blit(const struct tiled_blits *t,
struct blit_buffer *dst,
struct blit_buffer *src,
@@ -59,51 +136,103 @@ static int prepare_blit(const struct tiled_blits *t,
if (IS_ERR(cs))
return PTR_ERR(cs);
- *cs++ = MI_LOAD_REGISTER_IMM(1);
- *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
- cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
- if (src->tiling == CLIENT_TILING_Y)
- cmd |= BCS_SRC_Y;
- if (dst->tiling == CLIENT_TILING_Y)
- cmd |= BCS_DST_Y;
- *cs++ = cmd;
-
- cmd = MI_FLUSH_DW;
- if (ver >= 8)
- cmd++;
- *cs++ = cmd;
- *cs++ = 0;
- *cs++ = 0;
- *cs++ = 0;
-
- cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
- if (ver >= 8)
- cmd += 2;
-
- src_pitch = t->width * 4;
- if (src->tiling) {
- cmd |= XY_SRC_COPY_BLT_SRC_TILED;
- src_pitch /= 4;
- }
+ if (fast_blit_ok(dst) && fast_blit_ok(src)) {
+ struct intel_gt *gt = t->ce->engine->gt;
+ u32 src_tiles = 0, dst_tiles = 0;
+ u32 src_4t = 0, dst_4t = 0;
+
+ /* Need to program BLIT_CCTL if it is not done previously
+ * before using XY_FAST_COPY_BLT
+ */
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(BLIT_CCTL(t->ce->engine->mmio_base));
+ *cs++ = (BLIT_CCTL_SRC_MOCS(gt->mocs.uc_index) |
+ BLIT_CCTL_DST_MOCS(gt->mocs.uc_index));
+
+ src_pitch = t->width; /* in dwords */
+ if (src->tiling == CLIENT_TILING_4) {
+ src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
+ src_4t = XY_FAST_COPY_BLT_D1_SRC_TILE4;
+ } else if (src->tiling == CLIENT_TILING_Y) {
+ src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(YMAJOR);
+ } else if (src->tiling == CLIENT_TILING_X) {
+ src_tiles = XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(TILE_X);
+ } else {
+ src_pitch *= 4; /* in bytes */
+ }
- dst_pitch = t->width * 4;
- if (dst->tiling) {
- cmd |= XY_SRC_COPY_BLT_DST_TILED;
- dst_pitch /= 4;
- }
+ dst_pitch = t->width; /* in dwords */
+ if (dst->tiling == CLIENT_TILING_4) {
+ dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
+ dst_4t = XY_FAST_COPY_BLT_D1_DST_TILE4;
+ } else if (dst->tiling == CLIENT_TILING_Y) {
+ dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(YMAJOR);
+ } else if (dst->tiling == CLIENT_TILING_X) {
+ dst_tiles = XY_FAST_COPY_BLT_D0_DST_TILE_MODE(TILE_X);
+ } else {
+ dst_pitch *= 4; /* in bytes */
+ }
- *cs++ = cmd;
- *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
- *cs++ = 0;
- *cs++ = t->height << 16 | t->width;
- *cs++ = lower_32_bits(dst->vma->node.start);
- if (use_64b_reloc)
+ *cs++ = GEN9_XY_FAST_COPY_BLT_CMD | (10 - 2) |
+ src_tiles | dst_tiles;
+ *cs++ = src_4t | dst_4t | BLT_DEPTH_32 | dst_pitch;
+ *cs++ = 0;
+ *cs++ = t->height << 16 | t->width;
+ *cs++ = lower_32_bits(dst->vma->node.start);
*cs++ = upper_32_bits(dst->vma->node.start);
- *cs++ = 0;
- *cs++ = src_pitch;
- *cs++ = lower_32_bits(src->vma->node.start);
- if (use_64b_reloc)
+ *cs++ = 0;
+ *cs++ = src_pitch;
+ *cs++ = lower_32_bits(src->vma->node.start);
*cs++ = upper_32_bits(src->vma->node.start);
+ } else {
+ if (ver >= 6) {
+ *cs++ = MI_LOAD_REGISTER_IMM(1);
+ *cs++ = i915_mmio_reg_offset(BCS_SWCTRL);
+ cmd = (BCS_SRC_Y | BCS_DST_Y) << 16;
+ if (src->tiling == CLIENT_TILING_Y)
+ cmd |= BCS_SRC_Y;
+ if (dst->tiling == CLIENT_TILING_Y)
+ cmd |= BCS_DST_Y;
+ *cs++ = cmd;
+
+ cmd = MI_FLUSH_DW;
+ if (ver >= 8)
+ cmd++;
+ *cs++ = cmd;
+ *cs++ = 0;
+ *cs++ = 0;
+ *cs++ = 0;
+ }
+
+ cmd = XY_SRC_COPY_BLT_CMD | BLT_WRITE_RGBA | (8 - 2);
+ if (ver >= 8)
+ cmd += 2;
+
+ src_pitch = t->width * 4;
+ if (src->tiling) {
+ cmd |= XY_SRC_COPY_BLT_SRC_TILED;
+ src_pitch /= 4;
+ }
+
+ dst_pitch = t->width * 4;
+ if (dst->tiling) {
+ cmd |= XY_SRC_COPY_BLT_DST_TILED;
+ dst_pitch /= 4;
+ }
+
+ *cs++ = cmd;
+ *cs++ = BLT_DEPTH_32 | BLT_ROP_SRC_COPY | dst_pitch;
+ *cs++ = 0;
+ *cs++ = t->height << 16 | t->width;
+ *cs++ = lower_32_bits(dst->vma->node.start);
+ if (use_64b_reloc)
+ *cs++ = upper_32_bits(dst->vma->node.start);
+ *cs++ = 0;
+ *cs++ = src_pitch;
+ *cs++ = lower_32_bits(src->vma->node.start);
+ if (use_64b_reloc)
+ *cs++ = upper_32_bits(src->vma->node.start);
+ }
*cs++ = MI_BATCH_BUFFER_END;
@@ -181,7 +310,13 @@ static int tiled_blits_create_buffers(struct tiled_blits *t,
t->buffers[i].vma = vma;
t->buffers[i].tiling =
- i915_prandom_u32_max_state(CLIENT_TILING_Y + 1, prng);
+ i915_prandom_u32_max_state(CLIENT_NUM_TILING_TYPES, prng);
+
+ /* Platforms support either TileY or Tile4, not both */
+ if (HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_Y)
+ t->buffers[i].tiling = CLIENT_TILING_4;
+ else if (!HAS_4TILE(i915) && t->buffers[i].tiling == CLIENT_TILING_4)
+ t->buffers[i].tiling = CLIENT_TILING_Y;
}
return 0;
@@ -206,7 +341,8 @@ static u64 swizzle_bit(unsigned int bit, u64 offset)
static u64 tiled_offset(const struct intel_gt *gt,
u64 v,
unsigned int stride,
- enum client_tiling tiling)
+ enum client_tiling tiling,
+ int x_pos, int y_pos)
{
unsigned int swizzle;
u64 x, y;
@@ -216,7 +352,12 @@ static u64 tiled_offset(const struct intel_gt *gt,
y = div64_u64_rem(v, stride, &x);
- if (tiling == CLIENT_TILING_X) {
+ if (tiling == CLIENT_TILING_4) {
+ v = linear_x_y_to_ftiled_pos(x_pos, y_pos, stride, 32);
+
+ /* no swizzling for f-tiling */
+ swizzle = I915_BIT_6_SWIZZLE_NONE;
+ } else if (tiling == CLIENT_TILING_X) {
v = div64_u64_rem(y, 8, &y) * stride * 8;
v += y * 512;
v += div64_u64_rem(x, 512, &x) << 12;
@@ -259,6 +400,7 @@ static const char *repr_tiling(enum client_tiling tiling)
case CLIENT_TILING_LINEAR: return "linear";
case CLIENT_TILING_X: return "X";
case CLIENT_TILING_Y: return "Y";
+ case CLIENT_TILING_4: return "F";
default: return "unknown";
}
}
@@ -284,7 +426,7 @@ static int verify_buffer(const struct tiled_blits *t,
} else {
u64 v = tiled_offset(buf->vma->vm->gt,
p * 4, t->width * 4,
- buf->tiling);
+ buf->tiling, x, y);
if (vaddr[v / sizeof(*vaddr)] != buf->start_val + p)
ret = -EINVAL;
@@ -504,6 +646,9 @@ static int tiled_blits_bounce(struct tiled_blits *t, struct rnd_state *prng)
if (err)
return err;
+ /* Simulating GTT eviction of the same buffer / layout */
+ t->buffers[2].tiling = t->buffers[0].tiling;
+
/* Reposition so that we overlap the old addresses, and slightly off */
err = tiled_blit(t,
&t->buffers[2], t->hole + t->align,
diff --git a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
index 556bca3be804..246ab8f7bf57 100644
--- a/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
+++ b/drivers/gpu/drm/i915/gt/intel_gpu_commands.h
@@ -236,6 +236,28 @@
#define XY_FAST_COLOR_BLT_DW 16
#define XY_FAST_COLOR_BLT_MOCS_MASK GENMASK(27, 21)
#define XY_FAST_COLOR_BLT_MEM_TYPE_SHIFT 31
+
+#define XY_FAST_COPY_BLT_D0_SRC_TILING_MASK REG_GENMASK(21, 20)
+#define XY_FAST_COPY_BLT_D0_DST_TILING_MASK REG_GENMASK(14, 13)
+#define XY_FAST_COPY_BLT_D0_SRC_TILE_MODE(mode) \
+ REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_SRC_TILING_MASK, mode)
+#define XY_FAST_COPY_BLT_D0_DST_TILE_MODE(mode) \
+ REG_FIELD_PREP(XY_FAST_COPY_BLT_D0_DST_TILING_MASK, mode)
+#define LINEAR 0
+#define TILE_X 0x1
+#define XMAJOR 0x1
+#define YMAJOR 0x2
+#define TILE_64 0x3
+#define XY_FAST_COPY_BLT_D1_SRC_TILE4 REG_BIT(31)
+#define XY_FAST_COPY_BLT_D1_DST_TILE4 REG_BIT(30)
+#define BLIT_CCTL_SRC_MOCS_MASK REG_GENMASK(6, 0)
+#define BLIT_CCTL_DST_MOCS_MASK REG_GENMASK(14, 8)
+/* Note: MOCS value = (index << 1) */
+#define BLIT_CCTL_SRC_MOCS(idx) \
+ REG_FIELD_PREP(BLIT_CCTL_SRC_MOCS_MASK, (idx) << 1)
+#define BLIT_CCTL_DST_MOCS(idx) \
+ REG_FIELD_PREP(BLIT_CCTL_DST_MOCS_MASK, (idx) << 1)
+
#define SRC_COPY_BLT_CMD (2 << 29 | 0x43 << 22)
#define GEN9_XY_FAST_COPY_BLT_CMD (2 << 29 | 0x42 << 22)
#define XY_SRC_COPY_BLT_CMD (2 << 29 | 0x53 << 22)
--
2.35.1
^ permalink raw reply related [flat|nested] 7+ messages in thread
end of thread, other threads:[~2022-05-13 7:50 UTC | newest]
Thread overview: 7+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2022-05-11 14:22 [Intel-gfx] [PATCH] drm/i915: Enable Tile4 tiling mode Nirmoy Das
2022-05-11 14:26 ` Das, Nirmoy
2022-05-11 17:04 ` [Intel-gfx] ✗ Fi.CI.CHECKPATCH: warning for " Patchwork
2022-05-11 17:28 ` [Intel-gfx] ✗ Fi.CI.BAT: failure " Patchwork
2022-05-12 13:26 [Intel-gfx] [PATCH] " Nirmoy Das
2022-05-13 5:47 ` Zbigniew Kempczyński
2022-05-13 7:50 ` Das, Nirmoy
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