* [RESEND v4 0/2] Introduce MediaTek CCI devfreq driver
@ 2022-05-13 3:28 ` Johnson Wang
0 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-13 3:28 UTC (permalink / raw)
To: cw00.choi, krzk+dt, robh+dt, kyungmin.park
Cc: djakov, khilman, linux-pm, linux-kernel, devicetree,
linux-arm-kernel, linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group, Johnson Wang
The Cache Coherent Interconnect (CCI) is the management of cache
coherency by hardware. CCI DEVFREQ is DVFS driver for power saving by
scaling clock frequency and supply voltage of CCI. CCI uses the same
input clock source and power rail as LITTLE CPUs on Mediatek SoCs.
This series depends on:
Chanwoo's repo: kernel/git/chanwoo/linux.git
branch: devfreq-testing
[1]: PM / devfreq: Export devfreq_get_freq_range symbol within devfreq
[2]: PM / devfreq: Add cpu based scaling support to passive governor
[3]: PM / devfreq: passive: Reduce duplicate code when passive_devfreq case
[4]: PM / devfreq: passive: Update frequency when start governor
Resend v4:
- CC interconnect maintainer.
- Change sign-off sequence in commit message.
Changes in v4:
- Add a maintainer in the binding document.
- Modify clock description.
- Add binding document into MAINTAINERS.
- Replace format specifier %d with %ld.
Changes in v3:
- Move binding document to 'interconnect' and rename it.
- Add COMPILE_TEST dependence symbol.
- Remove need_voltage_tracking variable.
- Move mtk_ccifreq_voltage_tracking() code into mtk_ccifreq_set_voltage().
- Add an interation limit in the while() loop.
- Replace 'cci_dev' with 'dev'
- Replace old_* with pre_*
- Remove of_match_ptr()
- Use module_platform_driver()
Changes in v2:
- Take MT8183 as example in binding document.
- Use dev_err() instead of pr_err().
- Use 'goto' statement to handle error case.
- Clean up driver code.
Johnson Wang (2):
dt-bindings: interconnect: Add MediaTek CCI dt-bindings
PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
.../bindings/interconnect/mediatek,cci.yaml | 140 ++++++
MAINTAINERS | 1 +
drivers/devfreq/Kconfig | 10 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/mtk-cci-devfreq.c | 474 ++++++++++++++++++
5 files changed, 626 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
--
2.18.0
^ permalink raw reply [flat|nested] 30+ messages in thread
* [RESEND v4 0/2] Introduce MediaTek CCI devfreq driver
@ 2022-05-13 3:28 ` Johnson Wang
0 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-13 3:28 UTC (permalink / raw)
To: cw00.choi, krzk+dt, robh+dt, kyungmin.park
Cc: djakov, khilman, linux-pm, linux-kernel, devicetree,
linux-arm-kernel, linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group, Johnson Wang
The Cache Coherent Interconnect (CCI) is the management of cache
coherency by hardware. CCI DEVFREQ is DVFS driver for power saving by
scaling clock frequency and supply voltage of CCI. CCI uses the same
input clock source and power rail as LITTLE CPUs on Mediatek SoCs.
This series depends on:
Chanwoo's repo: kernel/git/chanwoo/linux.git
branch: devfreq-testing
[1]: PM / devfreq: Export devfreq_get_freq_range symbol within devfreq
[2]: PM / devfreq: Add cpu based scaling support to passive governor
[3]: PM / devfreq: passive: Reduce duplicate code when passive_devfreq case
[4]: PM / devfreq: passive: Update frequency when start governor
Resend v4:
- CC interconnect maintainer.
- Change sign-off sequence in commit message.
Changes in v4:
- Add a maintainer in the binding document.
- Modify clock description.
- Add binding document into MAINTAINERS.
- Replace format specifier %d with %ld.
Changes in v3:
- Move binding document to 'interconnect' and rename it.
- Add COMPILE_TEST dependence symbol.
- Remove need_voltage_tracking variable.
- Move mtk_ccifreq_voltage_tracking() code into mtk_ccifreq_set_voltage().
- Add an interation limit in the while() loop.
- Replace 'cci_dev' with 'dev'
- Replace old_* with pre_*
- Remove of_match_ptr()
- Use module_platform_driver()
Changes in v2:
- Take MT8183 as example in binding document.
- Use dev_err() instead of pr_err().
- Use 'goto' statement to handle error case.
- Clean up driver code.
Johnson Wang (2):
dt-bindings: interconnect: Add MediaTek CCI dt-bindings
PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
.../bindings/interconnect/mediatek,cci.yaml | 140 ++++++
MAINTAINERS | 1 +
drivers/devfreq/Kconfig | 10 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/mtk-cci-devfreq.c | 474 ++++++++++++++++++
5 files changed, 626 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 30+ messages in thread
* [RESEND v4 0/2] Introduce MediaTek CCI devfreq driver
@ 2022-05-13 3:28 ` Johnson Wang
0 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-13 3:28 UTC (permalink / raw)
To: cw00.choi, krzk+dt, robh+dt, kyungmin.park
Cc: djakov, khilman, linux-pm, linux-kernel, devicetree,
linux-arm-kernel, linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group, Johnson Wang
The Cache Coherent Interconnect (CCI) is the management of cache
coherency by hardware. CCI DEVFREQ is DVFS driver for power saving by
scaling clock frequency and supply voltage of CCI. CCI uses the same
input clock source and power rail as LITTLE CPUs on Mediatek SoCs.
This series depends on:
Chanwoo's repo: kernel/git/chanwoo/linux.git
branch: devfreq-testing
[1]: PM / devfreq: Export devfreq_get_freq_range symbol within devfreq
[2]: PM / devfreq: Add cpu based scaling support to passive governor
[3]: PM / devfreq: passive: Reduce duplicate code when passive_devfreq case
[4]: PM / devfreq: passive: Update frequency when start governor
Resend v4:
- CC interconnect maintainer.
- Change sign-off sequence in commit message.
Changes in v4:
- Add a maintainer in the binding document.
- Modify clock description.
- Add binding document into MAINTAINERS.
- Replace format specifier %d with %ld.
Changes in v3:
- Move binding document to 'interconnect' and rename it.
- Add COMPILE_TEST dependence symbol.
- Remove need_voltage_tracking variable.
- Move mtk_ccifreq_voltage_tracking() code into mtk_ccifreq_set_voltage().
- Add an interation limit in the while() loop.
- Replace 'cci_dev' with 'dev'
- Replace old_* with pre_*
- Remove of_match_ptr()
- Use module_platform_driver()
Changes in v2:
- Take MT8183 as example in binding document.
- Use dev_err() instead of pr_err().
- Use 'goto' statement to handle error case.
- Clean up driver code.
Johnson Wang (2):
dt-bindings: interconnect: Add MediaTek CCI dt-bindings
PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
.../bindings/interconnect/mediatek,cci.yaml | 140 ++++++
MAINTAINERS | 1 +
drivers/devfreq/Kconfig | 10 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/mtk-cci-devfreq.c | 474 ++++++++++++++++++
5 files changed, 626 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* [RESEND v4 1/2] dt-bindings: interconnect: Add MediaTek CCI dt-bindings
2022-05-13 3:28 ` Johnson Wang
(?)
@ 2022-05-13 3:28 ` Johnson Wang
-1 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-13 3:28 UTC (permalink / raw)
To: cw00.choi, krzk+dt, robh+dt, kyungmin.park
Cc: djakov, khilman, linux-pm, linux-kernel, devicetree,
linux-arm-kernel, linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group, Johnson Wang
Add devicetree binding of MediaTek CCI on MT8183 and MT8186.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
---
.../bindings/interconnect/mediatek,cci.yaml | 140 ++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 141 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
new file mode 100644
index 000000000000..034c3b38ca3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
+
+maintainers:
+ - Jia-Wei Chang <jia-wei.chang@mediatek.com>
+ - Johnson Wang <johnson.wang@mediatek.com>
+
+description: |
+ MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
+ MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
+ hardware. It can also optimize the voltage to reduce the power consumption.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8183-cci
+ - mediatek,mt8186-cci
+
+ clocks:
+ items:
+ - description:
+ The multiplexer for clock input of the bus.
+ - description:
+ A parent of "cpu" clock which is used as an intermediate clock source
+ when the original CPU is under transition and not stable yet.
+
+ clock-names:
+ items:
+ - const: cci
+ - const: intermediate
+
+ operating-points-v2: true
+ opp-table: true
+
+ proc-supply:
+ description:
+ Phandle of the regulator for CCI that provides the supply voltage.
+
+ sram-supply:
+ description:
+ Phandle of the regulator for sram of CCI that provides the supply
+ voltage. When it is present, the implementation needs to do
+ "voltage tracking" to step by step scale up/down Vproc and Vsram to fit
+ SoC specific needs. When absent, the voltage scaling flow is handled by
+ hardware, hence no software "voltage tracking" is needed.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - operating-points-v2
+ - proc-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ cci: cci {
+ compatible = "mediatek,mt8183-cci";
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cci", "intermediate";
+ operating-points-v2 = <&cci_opp>;
+ proc-supply = <&mt6358_vproc12_reg>;
+ };
+
+ cci_opp: opp-table-cci {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp2_00: opp-273000000 {
+ opp-hz = /bits/ 64 <273000000>;
+ opp-microvolt = <650000>;
+ };
+ opp2_01: opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ opp-microvolt = <687500>;
+ };
+ opp2_02: opp-403000000 {
+ opp-hz = /bits/ 64 <403000000>;
+ opp-microvolt = <718750>;
+ };
+ opp2_03: opp-463000000 {
+ opp-hz = /bits/ 64 <463000000>;
+ opp-microvolt = <756250>;
+ };
+ opp2_04: opp-546000000 {
+ opp-hz = /bits/ 64 <546000000>;
+ opp-microvolt = <800000>;
+ };
+ opp2_05: opp-624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <818750>;
+ };
+ opp2_06: opp-689000000 {
+ opp-hz = /bits/ 64 <689000000>;
+ opp-microvolt = <850000>;
+ };
+ opp2_07: opp-767000000 {
+ opp-hz = /bits/ 64 <767000000>;
+ opp-microvolt = <868750>;
+ };
+ opp2_08: opp-845000000 {
+ opp-hz = /bits/ 64 <845000000>;
+ opp-microvolt = <893750>;
+ };
+ opp2_09: opp-871000000 {
+ opp-hz = /bits/ 64 <871000000>;
+ opp-microvolt = <906250>;
+ };
+ opp2_10: opp-923000000 {
+ opp-hz = /bits/ 64 <923000000>;
+ opp-microvolt = <931250>;
+ };
+ opp2_11: opp-962000000 {
+ opp-hz = /bits/ 64 <962000000>;
+ opp-microvolt = <943750>;
+ };
+ opp2_12: opp-1027000000 {
+ opp-hz = /bits/ 64 <1027000000>;
+ opp-microvolt = <975000>;
+ };
+ opp2_13: opp-1092000000 {
+ opp-hz = /bits/ 64 <1092000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp2_14: opp-1144000000 {
+ opp-hz = /bits/ 64 <1144000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp2_15: opp-1196000000 {
+ opp-hz = /bits/ 64 <1196000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index e8c52d0192a6..69f03077f77c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5698,6 +5698,7 @@ L: linux-pm@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git
F: Documentation/devicetree/bindings/devfreq/
+F: Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
F: drivers/devfreq/
F: include/linux/devfreq.h
F: include/trace/events/devfreq.h
--
2.18.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [RESEND v4 1/2] dt-bindings: interconnect: Add MediaTek CCI dt-bindings
@ 2022-05-13 3:28 ` Johnson Wang
0 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-13 3:28 UTC (permalink / raw)
To: cw00.choi, krzk+dt, robh+dt, kyungmin.park
Cc: djakov, khilman, linux-pm, linux-kernel, devicetree,
linux-arm-kernel, linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group, Johnson Wang
Add devicetree binding of MediaTek CCI on MT8183 and MT8186.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
---
.../bindings/interconnect/mediatek,cci.yaml | 140 ++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 141 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
new file mode 100644
index 000000000000..034c3b38ca3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
+
+maintainers:
+ - Jia-Wei Chang <jia-wei.chang@mediatek.com>
+ - Johnson Wang <johnson.wang@mediatek.com>
+
+description: |
+ MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
+ MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
+ hardware. It can also optimize the voltage to reduce the power consumption.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8183-cci
+ - mediatek,mt8186-cci
+
+ clocks:
+ items:
+ - description:
+ The multiplexer for clock input of the bus.
+ - description:
+ A parent of "cpu" clock which is used as an intermediate clock source
+ when the original CPU is under transition and not stable yet.
+
+ clock-names:
+ items:
+ - const: cci
+ - const: intermediate
+
+ operating-points-v2: true
+ opp-table: true
+
+ proc-supply:
+ description:
+ Phandle of the regulator for CCI that provides the supply voltage.
+
+ sram-supply:
+ description:
+ Phandle of the regulator for sram of CCI that provides the supply
+ voltage. When it is present, the implementation needs to do
+ "voltage tracking" to step by step scale up/down Vproc and Vsram to fit
+ SoC specific needs. When absent, the voltage scaling flow is handled by
+ hardware, hence no software "voltage tracking" is needed.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - operating-points-v2
+ - proc-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ cci: cci {
+ compatible = "mediatek,mt8183-cci";
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cci", "intermediate";
+ operating-points-v2 = <&cci_opp>;
+ proc-supply = <&mt6358_vproc12_reg>;
+ };
+
+ cci_opp: opp-table-cci {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp2_00: opp-273000000 {
+ opp-hz = /bits/ 64 <273000000>;
+ opp-microvolt = <650000>;
+ };
+ opp2_01: opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ opp-microvolt = <687500>;
+ };
+ opp2_02: opp-403000000 {
+ opp-hz = /bits/ 64 <403000000>;
+ opp-microvolt = <718750>;
+ };
+ opp2_03: opp-463000000 {
+ opp-hz = /bits/ 64 <463000000>;
+ opp-microvolt = <756250>;
+ };
+ opp2_04: opp-546000000 {
+ opp-hz = /bits/ 64 <546000000>;
+ opp-microvolt = <800000>;
+ };
+ opp2_05: opp-624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <818750>;
+ };
+ opp2_06: opp-689000000 {
+ opp-hz = /bits/ 64 <689000000>;
+ opp-microvolt = <850000>;
+ };
+ opp2_07: opp-767000000 {
+ opp-hz = /bits/ 64 <767000000>;
+ opp-microvolt = <868750>;
+ };
+ opp2_08: opp-845000000 {
+ opp-hz = /bits/ 64 <845000000>;
+ opp-microvolt = <893750>;
+ };
+ opp2_09: opp-871000000 {
+ opp-hz = /bits/ 64 <871000000>;
+ opp-microvolt = <906250>;
+ };
+ opp2_10: opp-923000000 {
+ opp-hz = /bits/ 64 <923000000>;
+ opp-microvolt = <931250>;
+ };
+ opp2_11: opp-962000000 {
+ opp-hz = /bits/ 64 <962000000>;
+ opp-microvolt = <943750>;
+ };
+ opp2_12: opp-1027000000 {
+ opp-hz = /bits/ 64 <1027000000>;
+ opp-microvolt = <975000>;
+ };
+ opp2_13: opp-1092000000 {
+ opp-hz = /bits/ 64 <1092000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp2_14: opp-1144000000 {
+ opp-hz = /bits/ 64 <1144000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp2_15: opp-1196000000 {
+ opp-hz = /bits/ 64 <1196000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index e8c52d0192a6..69f03077f77c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5698,6 +5698,7 @@ L: linux-pm@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git
F: Documentation/devicetree/bindings/devfreq/
+F: Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
F: drivers/devfreq/
F: include/linux/devfreq.h
F: include/trace/events/devfreq.h
--
2.18.0
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [RESEND v4 1/2] dt-bindings: interconnect: Add MediaTek CCI dt-bindings
@ 2022-05-13 3:28 ` Johnson Wang
0 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-13 3:28 UTC (permalink / raw)
To: cw00.choi, krzk+dt, robh+dt, kyungmin.park
Cc: djakov, khilman, linux-pm, linux-kernel, devicetree,
linux-arm-kernel, linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group, Johnson Wang
Add devicetree binding of MediaTek CCI on MT8183 and MT8186.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
---
.../bindings/interconnect/mediatek,cci.yaml | 140 ++++++++++++++++++
MAINTAINERS | 1 +
2 files changed, 141 insertions(+)
create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
new file mode 100644
index 000000000000..034c3b38ca3d
--- /dev/null
+++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
@@ -0,0 +1,140 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
+
+maintainers:
+ - Jia-Wei Chang <jia-wei.chang@mediatek.com>
+ - Johnson Wang <johnson.wang@mediatek.com>
+
+description: |
+ MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
+ MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
+ hardware. It can also optimize the voltage to reduce the power consumption.
+
+properties:
+ compatible:
+ enum:
+ - mediatek,mt8183-cci
+ - mediatek,mt8186-cci
+
+ clocks:
+ items:
+ - description:
+ The multiplexer for clock input of the bus.
+ - description:
+ A parent of "cpu" clock which is used as an intermediate clock source
+ when the original CPU is under transition and not stable yet.
+
+ clock-names:
+ items:
+ - const: cci
+ - const: intermediate
+
+ operating-points-v2: true
+ opp-table: true
+
+ proc-supply:
+ description:
+ Phandle of the regulator for CCI that provides the supply voltage.
+
+ sram-supply:
+ description:
+ Phandle of the regulator for sram of CCI that provides the supply
+ voltage. When it is present, the implementation needs to do
+ "voltage tracking" to step by step scale up/down Vproc and Vsram to fit
+ SoC specific needs. When absent, the voltage scaling flow is handled by
+ hardware, hence no software "voltage tracking" is needed.
+
+required:
+ - compatible
+ - clocks
+ - clock-names
+ - operating-points-v2
+ - proc-supply
+
+additionalProperties: false
+
+examples:
+ - |
+ #include <dt-bindings/clock/mt8183-clk.h>
+ cci: cci {
+ compatible = "mediatek,mt8183-cci";
+ clocks = <&mcucfg CLK_MCU_BUS_SEL>,
+ <&topckgen CLK_TOP_ARMPLL_DIV_PLL1>;
+ clock-names = "cci", "intermediate";
+ operating-points-v2 = <&cci_opp>;
+ proc-supply = <&mt6358_vproc12_reg>;
+ };
+
+ cci_opp: opp-table-cci {
+ compatible = "operating-points-v2";
+ opp-shared;
+ opp2_00: opp-273000000 {
+ opp-hz = /bits/ 64 <273000000>;
+ opp-microvolt = <650000>;
+ };
+ opp2_01: opp-338000000 {
+ opp-hz = /bits/ 64 <338000000>;
+ opp-microvolt = <687500>;
+ };
+ opp2_02: opp-403000000 {
+ opp-hz = /bits/ 64 <403000000>;
+ opp-microvolt = <718750>;
+ };
+ opp2_03: opp-463000000 {
+ opp-hz = /bits/ 64 <463000000>;
+ opp-microvolt = <756250>;
+ };
+ opp2_04: opp-546000000 {
+ opp-hz = /bits/ 64 <546000000>;
+ opp-microvolt = <800000>;
+ };
+ opp2_05: opp-624000000 {
+ opp-hz = /bits/ 64 <624000000>;
+ opp-microvolt = <818750>;
+ };
+ opp2_06: opp-689000000 {
+ opp-hz = /bits/ 64 <689000000>;
+ opp-microvolt = <850000>;
+ };
+ opp2_07: opp-767000000 {
+ opp-hz = /bits/ 64 <767000000>;
+ opp-microvolt = <868750>;
+ };
+ opp2_08: opp-845000000 {
+ opp-hz = /bits/ 64 <845000000>;
+ opp-microvolt = <893750>;
+ };
+ opp2_09: opp-871000000 {
+ opp-hz = /bits/ 64 <871000000>;
+ opp-microvolt = <906250>;
+ };
+ opp2_10: opp-923000000 {
+ opp-hz = /bits/ 64 <923000000>;
+ opp-microvolt = <931250>;
+ };
+ opp2_11: opp-962000000 {
+ opp-hz = /bits/ 64 <962000000>;
+ opp-microvolt = <943750>;
+ };
+ opp2_12: opp-1027000000 {
+ opp-hz = /bits/ 64 <1027000000>;
+ opp-microvolt = <975000>;
+ };
+ opp2_13: opp-1092000000 {
+ opp-hz = /bits/ 64 <1092000000>;
+ opp-microvolt = <1000000>;
+ };
+ opp2_14: opp-1144000000 {
+ opp-hz = /bits/ 64 <1144000000>;
+ opp-microvolt = <1025000>;
+ };
+ opp2_15: opp-1196000000 {
+ opp-hz = /bits/ 64 <1196000000>;
+ opp-microvolt = <1050000>;
+ };
+ };
diff --git a/MAINTAINERS b/MAINTAINERS
index e8c52d0192a6..69f03077f77c 100644
--- a/MAINTAINERS
+++ b/MAINTAINERS
@@ -5698,6 +5698,7 @@ L: linux-pm@vger.kernel.org
S: Maintained
T: git git://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git
F: Documentation/devicetree/bindings/devfreq/
+F: Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
F: drivers/devfreq/
F: include/linux/devfreq.h
F: include/trace/events/devfreq.h
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
2022-05-13 3:28 ` Johnson Wang
(?)
@ 2022-05-13 3:28 ` Johnson Wang
-1 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-13 3:28 UTC (permalink / raw)
To: cw00.choi, krzk+dt, robh+dt, kyungmin.park
Cc: djakov, khilman, linux-pm, linux-kernel, devicetree,
linux-arm-kernel, linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group, Johnson Wang
We introduce a devfreq driver for the MediaTek Cache Coherent Interconnect
(CCI) used by some MediaTek SoCs.
In this driver, we use the passive devfreq driver to get target frequencies
and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek CCI
is supplied by the same regulators with the little core CPUs.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
---
This patch depends on "devfreq-testing"[1].
[1]https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing
---
drivers/devfreq/Kconfig | 10 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/mtk-cci-devfreq.c | 474 ++++++++++++++++++++++++++++++
3 files changed, 485 insertions(+)
create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 87eb2b837e68..9754d8b31621 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
It reads ACTMON counters of memory controllers and adjusts the
operating frequencies and voltages with OPP support.
+config ARM_MEDIATEK_CCI_DEVFREQ
+ tristate "MEDIATEK CCI DEVFREQ Driver"
+ depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
+ select DEVFREQ_GOV_PASSIVE
+ help
+ This adds a devfreq driver for MediaTek Cache Coherent Interconnect
+ which is shared the same regulators with the cpu cluster. It can track
+ buck voltages and update a proper CCI frequency. Use the notification
+ to get the regulator status.
+
config ARM_RK3399_DMC_DEVFREQ
tristate "ARM RK3399 DMC DEVFREQ Driver"
depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 0b6be92a25d9..bf40d04928d0 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
+obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
diff --git a/drivers/devfreq/mtk-cci-devfreq.c b/drivers/devfreq/mtk-cci-devfreq.c
new file mode 100644
index 000000000000..aa8c37eb4a06
--- /dev/null
+++ b/drivers/devfreq/mtk-cci-devfreq.c
@@ -0,0 +1,474 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/devfreq.h>
+#include <linux/minmax.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+#include <linux/regulator/consumer.h>
+
+struct mtk_ccifreq_platform_data {
+ int min_volt_shift;
+ int max_volt_shift;
+ int proc_max_volt;
+ int sram_min_volt;
+ int sram_max_volt;
+};
+
+struct mtk_ccifreq_drv {
+ struct device *dev;
+ struct devfreq *devfreq;
+ struct regulator *proc_reg;
+ struct regulator *sram_reg;
+ struct clk *cci_clk;
+ struct clk *inter_clk;
+ int inter_voltage;
+ int pre_voltage;
+ unsigned long pre_freq;
+ /* Avoid race condition for regulators between notify and policy */
+ struct mutex reg_lock;
+ struct notifier_block opp_nb;
+ const struct mtk_ccifreq_platform_data *soc_data;
+ int vtrack_max;
+};
+
+static int mtk_ccifreq_set_voltage(struct mtk_ccifreq_drv *drv, int new_voltage)
+{
+ const struct mtk_ccifreq_platform_data *soc_data = drv->soc_data;
+ struct device *dev = drv->dev;
+ int pre_voltage, pre_vsram, new_vsram, vsram, voltage, ret;
+ int retry_max = drv->vtrack_max;
+
+ if (!drv->sram_reg) {
+ ret = regulator_set_voltage(drv->proc_reg, new_voltage,
+ drv->soc_data->proc_max_volt);
+ goto out_set_voltage;
+ }
+
+ pre_voltage = regulator_get_voltage(drv->proc_reg);
+ if (pre_voltage < 0) {
+ dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
+ return pre_voltage;
+ }
+
+ pre_vsram = regulator_get_voltage(drv->sram_reg);
+ if (pre_vsram < 0) {
+ dev_err(dev, "invalid vsram value: %d\n", pre_vsram);
+ return pre_vsram;
+ }
+
+ new_vsram = clamp(new_voltage + soc_data->min_volt_shift,
+ soc_data->sram_min_volt, soc_data->sram_max_volt);
+
+ do {
+ if (pre_voltage <= new_voltage) {
+ vsram = clamp(pre_voltage + soc_data->max_volt_shift,
+ soc_data->sram_min_volt, new_vsram);
+ ret = regulator_set_voltage(drv->sram_reg, vsram,
+ soc_data->sram_max_volt);
+ if (ret)
+ return ret;
+
+ if (vsram == soc_data->sram_max_volt ||
+ new_vsram == soc_data->sram_min_volt)
+ voltage = new_voltage;
+ else
+ voltage = vsram - soc_data->min_volt_shift;
+
+ ret = regulator_set_voltage(drv->proc_reg, voltage,
+ soc_data->proc_max_volt);
+ if (ret) {
+ regulator_set_voltage(drv->sram_reg, pre_vsram,
+ soc_data->sram_max_volt);
+ return ret;
+ }
+ } else if (pre_voltage > new_voltage) {
+ voltage = max(new_voltage,
+ pre_vsram - soc_data->max_volt_shift);
+ ret = regulator_set_voltage(drv->proc_reg, voltage,
+ soc_data->proc_max_volt);
+ if (ret)
+ return ret;
+
+ if (voltage == new_voltage)
+ vsram = new_vsram;
+ else
+ vsram = max(new_vsram,
+ voltage + soc_data->min_volt_shift);
+
+ ret = regulator_set_voltage(drv->sram_reg, vsram,
+ soc_data->sram_max_volt);
+ if (ret) {
+ regulator_set_voltage(drv->proc_reg, pre_voltage,
+ soc_data->proc_max_volt);
+ return ret;
+ }
+ }
+
+ pre_voltage = voltage;
+ pre_vsram = vsram;
+
+ if (--retry_max < 0) {
+ dev_err(dev,
+ "over loop count, failed to set voltage\n");
+ return -EINVAL;
+ }
+ } while (voltage != new_voltage || vsram != new_vsram);
+
+out_set_voltage:
+ if (!ret)
+ drv->pre_voltage = new_voltage;
+
+ return ret;
+}
+
+static int mtk_ccifreq_target(struct device *dev, unsigned long *freq,
+ u32 flags)
+{
+ struct mtk_ccifreq_drv *drv = dev_get_drvdata(dev);
+ struct clk *cci_pll = clk_get_parent(drv->cci_clk);
+ struct dev_pm_opp *opp;
+ unsigned long opp_rate;
+ int voltage, pre_voltage, inter_voltage, target_voltage, ret;
+
+ if (!drv)
+ return -EINVAL;
+
+ if (drv->pre_freq == *freq)
+ return 0;
+
+ inter_voltage = drv->inter_voltage;
+
+ opp_rate = *freq;
+ opp = devfreq_recommended_opp(dev, &opp_rate, 1);
+ if (IS_ERR(opp)) {
+ dev_err(dev, "failed to find opp for freq: %ld\n", opp_rate);
+ return PTR_ERR(opp);
+ }
+
+ mutex_lock(&drv->reg_lock);
+
+ voltage = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+
+ if (unlikely(drv->pre_voltage <= 0))
+ pre_voltage = regulator_get_voltage(drv->proc_reg);
+ else
+ pre_voltage = drv->pre_voltage;
+
+ if (pre_voltage < 0) {
+ dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
+ return pre_voltage;
+ }
+
+ /* scale up: set voltage first then freq. */
+ target_voltage = max(inter_voltage, voltage);
+ if (pre_voltage <= target_voltage) {
+ ret = mtk_ccifreq_set_voltage(drv, target_voltage);
+ if (ret) {
+ dev_err(dev, "failed to scale up voltage\n");
+ goto out_restore_voltage;
+ }
+ }
+
+ /* switch the cci clock to intermediate clock source. */
+ ret = clk_set_parent(drv->cci_clk, drv->inter_clk);
+ if (ret) {
+ dev_err(dev, "failed to re-parent cci clock\n");
+ goto out_restore_voltage;
+ }
+
+ /* set the original clock to target rate. */
+ ret = clk_set_rate(cci_pll, *freq);
+ if (ret) {
+ dev_err(dev, "failed to set cci pll rate: %d\n", ret);
+ clk_set_parent(drv->cci_clk, cci_pll);
+ goto out_restore_voltage;
+ }
+
+ /* switch the cci clock back to the original clock source. */
+ ret = clk_set_parent(drv->cci_clk, cci_pll);
+ if (ret) {
+ dev_err(dev, "failed to re-parent cci clock\n");
+ mtk_ccifreq_set_voltage(drv, inter_voltage);
+ goto out_unlock;
+ }
+
+ /*
+ * If the new voltage is lower than the intermediate voltage or the
+ * original voltage, scale down to the new voltage.
+ */
+ if (voltage < inter_voltage || voltage < pre_voltage) {
+ ret = mtk_ccifreq_set_voltage(drv, voltage);
+ if (ret) {
+ dev_err(dev, "failed to scale down voltage\n");
+ goto out_unlock;
+ }
+ }
+
+ drv->pre_freq = *freq;
+ mutex_unlock(&drv->reg_lock);
+
+ return 0;
+
+out_restore_voltage:
+ mtk_ccifreq_set_voltage(drv, pre_voltage);
+
+out_unlock:
+ mutex_unlock(&drv->reg_lock);
+ return ret;
+}
+
+static int mtk_ccifreq_opp_notifier(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct dev_pm_opp *opp = data;
+ struct mtk_ccifreq_drv *drv;
+ unsigned long freq, volt;
+
+ drv = container_of(nb, struct mtk_ccifreq_drv, opp_nb);
+
+ if (event == OPP_EVENT_ADJUST_VOLTAGE) {
+ freq = dev_pm_opp_get_freq(opp);
+
+ mutex_lock(&drv->reg_lock);
+ /* current opp item is changed */
+ if (freq == drv->pre_freq) {
+ volt = dev_pm_opp_get_voltage(opp);
+ mtk_ccifreq_set_voltage(drv, volt);
+ }
+ mutex_unlock(&drv->reg_lock);
+ }
+
+ return 0;
+}
+
+static struct devfreq_dev_profile mtk_ccifreq_profile = {
+ .target = mtk_ccifreq_target,
+};
+
+static int mtk_ccifreq_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ccifreq_drv *drv;
+ struct devfreq_passive_data *passive_data;
+ struct dev_pm_opp *opp;
+ unsigned long rate, opp_volt;
+ int ret;
+
+ drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
+ if (!drv)
+ return -ENOMEM;
+
+ drv->dev = dev;
+ drv->soc_data = (const struct mtk_ccifreq_platform_data *)
+ of_device_get_match_data(&pdev->dev);
+ mutex_init(&drv->reg_lock);
+ platform_set_drvdata(pdev, drv);
+
+ drv->cci_clk = devm_clk_get(dev, "cci");
+ if (IS_ERR(drv->cci_clk)) {
+ ret = PTR_ERR(drv->cci_clk);
+ return dev_err_probe(dev, ret,
+ "failed to get cci clk: %d\n", ret);
+ }
+
+ drv->inter_clk = devm_clk_get(dev, "intermediate");
+ if (IS_ERR(drv->inter_clk)) {
+ ret = PTR_ERR(drv->inter_clk);
+ dev_err_probe(dev, ret,
+ "failed to get intermediate clk: %d\n", ret);
+ goto out_free_resources;
+ }
+
+ drv->proc_reg = devm_regulator_get_optional(dev, "proc");
+ if (IS_ERR(drv->proc_reg)) {
+ ret = PTR_ERR(drv->proc_reg);
+ dev_err_probe(dev, ret,
+ "failed to get proc regulator: %d\n", ret);
+ goto out_free_resources;
+ }
+
+ ret = regulator_enable(drv->proc_reg);
+ if (ret) {
+ dev_err(dev, "failed to enable proc regulator\n");
+ goto out_free_resources;
+ }
+
+ drv->sram_reg = regulator_get_optional(dev, "sram");
+ if (IS_ERR(drv->sram_reg))
+ drv->sram_reg = NULL;
+ else {
+ ret = regulator_enable(drv->sram_reg);
+ if (ret) {
+ dev_err(dev, "failed to enable sram regulator\n");
+ goto out_free_resources;
+ }
+ }
+
+ /*
+ * We assume min voltage is 0 and tracking target voltage using
+ * min_volt_shift for each iteration.
+ * The retry_max is 3 times of expeted iteration count.
+ */
+ drv->vtrack_max = 3 * DIV_ROUND_UP(max(drv->soc_data->sram_max_volt,
+ drv->soc_data->proc_max_volt),
+ drv->soc_data->min_volt_shift);
+
+ ret = clk_prepare_enable(drv->cci_clk);
+ if (ret)
+ goto out_free_resources;
+
+ ret = clk_prepare_enable(drv->inter_clk);
+ if (ret)
+ goto out_disable_cci_clk;
+
+ ret = dev_pm_opp_of_add_table(dev);
+ if (ret) {
+ dev_err(dev, "failed to add opp table: %d\n", ret);
+ goto out_disable_inter_clk;
+ }
+
+ rate = clk_get_rate(drv->inter_clk);
+ opp = dev_pm_opp_find_freq_ceil(dev, &rate);
+ if (IS_ERR(opp)) {
+ ret = PTR_ERR(opp);
+ dev_err(dev, "failed to get intermediate opp: %d\n", ret);
+ goto out_remove_opp_table;
+ }
+ drv->inter_voltage = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+
+ rate = U32_MAX;
+ opp = dev_pm_opp_find_freq_floor(drv->dev, &rate);
+ if (IS_ERR(opp)) {
+ dev_err(dev, "failed to get opp\n");
+ ret = PTR_ERR(opp);
+ goto out_remove_opp_table;
+ }
+
+ opp_volt = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+ ret = mtk_ccifreq_set_voltage(drv, opp_volt);
+ if (ret) {
+ dev_err(dev, "failed to scale to highest voltage %lu in proc_reg\n",
+ opp_volt);
+ goto out_remove_opp_table;
+ }
+
+ passive_data = devm_kzalloc(dev, sizeof(struct devfreq_passive_data),
+ GFP_KERNEL);
+ if (!passive_data) {
+ ret = -ENOMEM;
+ goto out_remove_opp_table;
+ }
+
+ passive_data->parent_type = CPUFREQ_PARENT_DEV;
+ drv->devfreq = devm_devfreq_add_device(dev, &mtk_ccifreq_profile,
+ DEVFREQ_GOV_PASSIVE,
+ passive_data);
+ if (IS_ERR(drv->devfreq)) {
+ ret = -EPROBE_DEFER;
+ dev_err(dev, "failed to add devfreq device: %ld\n",
+ PTR_ERR(drv->devfreq));
+ goto out_remove_opp_table;
+ }
+
+ drv->opp_nb.notifier_call = mtk_ccifreq_opp_notifier;
+ ret = dev_pm_opp_register_notifier(dev, &drv->opp_nb);
+ if (ret) {
+ dev_err(dev, "failed to register opp notifier: %d\n", ret);
+ goto out_remove_devfreq_device;
+ }
+ return 0;
+
+out_remove_devfreq_device:
+ devm_devfreq_remove_device(dev, drv->devfreq);
+
+out_remove_opp_table:
+ dev_pm_opp_of_remove_table(dev);
+
+out_disable_inter_clk:
+ clk_disable_unprepare(drv->inter_clk);
+
+out_disable_cci_clk:
+ clk_disable_unprepare(drv->cci_clk);
+
+out_free_resources:
+ if (regulator_is_enabled(drv->proc_reg))
+ regulator_disable(drv->proc_reg);
+ if (drv->sram_reg && regulator_is_enabled(drv->sram_reg))
+ regulator_disable(drv->sram_reg);
+
+ if (!IS_ERR(drv->proc_reg))
+ regulator_put(drv->proc_reg);
+ if (!IS_ERR(drv->sram_reg))
+ regulator_put(drv->sram_reg);
+ if (!IS_ERR(drv->cci_clk))
+ clk_put(drv->cci_clk);
+ if (!IS_ERR(drv->inter_clk))
+ clk_put(drv->inter_clk);
+
+ return ret;
+}
+
+static int mtk_ccifreq_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ccifreq_drv *drv;
+
+ drv = platform_get_drvdata(pdev);
+
+ dev_pm_opp_unregister_notifier(dev, &drv->opp_nb);
+ dev_pm_opp_of_remove_table(dev);
+ clk_disable_unprepare(drv->inter_clk);
+ clk_disable_unprepare(drv->cci_clk);
+ regulator_disable(drv->proc_reg);
+ if (drv->sram_reg)
+ regulator_disable(drv->sram_reg);
+
+ return 0;
+}
+
+static const struct mtk_ccifreq_platform_data mt8183_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 200000,
+ .proc_max_volt = 1150000,
+ .sram_min_volt = 0,
+ .sram_max_volt = 1150000,
+};
+
+static const struct mtk_ccifreq_platform_data mt8186_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 250000,
+ .proc_max_volt = 1118750,
+ .sram_min_volt = 850000,
+ .sram_max_volt = 1118750,
+};
+
+static const struct of_device_id mtk_ccifreq_machines[] = {
+ { .compatible = "mediatek,mt8183-cci", .data = &mt8183_platform_data },
+ { .compatible = "mediatek,mt8186-cci", .data = &mt8186_platform_data },
+ { },
+};
+MODULE_DEVICE_TABLE(of, mtk_ccifreq_machines);
+
+static struct platform_driver mtk_ccifreq_platdrv = {
+ .probe = mtk_ccifreq_probe,
+ .remove = mtk_ccifreq_remove,
+ .driver = {
+ .name = "mtk-ccifreq",
+ .of_match_table = mtk_ccifreq_machines,
+ },
+};
+module_platform_driver(mtk_ccifreq_platdrv);
+
+MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
+MODULE_AUTHOR("Jia-Wei Chang <jia-wei.chang@mediatek.com>");
+MODULE_LICENSE("GPL v2");
--
2.18.0
^ permalink raw reply related [flat|nested] 30+ messages in thread
* [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
@ 2022-05-13 3:28 ` Johnson Wang
0 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-13 3:28 UTC (permalink / raw)
To: cw00.choi, krzk+dt, robh+dt, kyungmin.park
Cc: djakov, khilman, linux-pm, linux-kernel, devicetree,
linux-arm-kernel, linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group, Johnson Wang
We introduce a devfreq driver for the MediaTek Cache Coherent Interconnect
(CCI) used by some MediaTek SoCs.
In this driver, we use the passive devfreq driver to get target frequencies
and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek CCI
is supplied by the same regulators with the little core CPUs.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
---
This patch depends on "devfreq-testing"[1].
[1]https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing
---
drivers/devfreq/Kconfig | 10 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/mtk-cci-devfreq.c | 474 ++++++++++++++++++++++++++++++
3 files changed, 485 insertions(+)
create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 87eb2b837e68..9754d8b31621 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
It reads ACTMON counters of memory controllers and adjusts the
operating frequencies and voltages with OPP support.
+config ARM_MEDIATEK_CCI_DEVFREQ
+ tristate "MEDIATEK CCI DEVFREQ Driver"
+ depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
+ select DEVFREQ_GOV_PASSIVE
+ help
+ This adds a devfreq driver for MediaTek Cache Coherent Interconnect
+ which is shared the same regulators with the cpu cluster. It can track
+ buck voltages and update a proper CCI frequency. Use the notification
+ to get the regulator status.
+
config ARM_RK3399_DMC_DEVFREQ
tristate "ARM RK3399 DMC DEVFREQ Driver"
depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 0b6be92a25d9..bf40d04928d0 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
+obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
diff --git a/drivers/devfreq/mtk-cci-devfreq.c b/drivers/devfreq/mtk-cci-devfreq.c
new file mode 100644
index 000000000000..aa8c37eb4a06
--- /dev/null
+++ b/drivers/devfreq/mtk-cci-devfreq.c
@@ -0,0 +1,474 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/devfreq.h>
+#include <linux/minmax.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+#include <linux/regulator/consumer.h>
+
+struct mtk_ccifreq_platform_data {
+ int min_volt_shift;
+ int max_volt_shift;
+ int proc_max_volt;
+ int sram_min_volt;
+ int sram_max_volt;
+};
+
+struct mtk_ccifreq_drv {
+ struct device *dev;
+ struct devfreq *devfreq;
+ struct regulator *proc_reg;
+ struct regulator *sram_reg;
+ struct clk *cci_clk;
+ struct clk *inter_clk;
+ int inter_voltage;
+ int pre_voltage;
+ unsigned long pre_freq;
+ /* Avoid race condition for regulators between notify and policy */
+ struct mutex reg_lock;
+ struct notifier_block opp_nb;
+ const struct mtk_ccifreq_platform_data *soc_data;
+ int vtrack_max;
+};
+
+static int mtk_ccifreq_set_voltage(struct mtk_ccifreq_drv *drv, int new_voltage)
+{
+ const struct mtk_ccifreq_platform_data *soc_data = drv->soc_data;
+ struct device *dev = drv->dev;
+ int pre_voltage, pre_vsram, new_vsram, vsram, voltage, ret;
+ int retry_max = drv->vtrack_max;
+
+ if (!drv->sram_reg) {
+ ret = regulator_set_voltage(drv->proc_reg, new_voltage,
+ drv->soc_data->proc_max_volt);
+ goto out_set_voltage;
+ }
+
+ pre_voltage = regulator_get_voltage(drv->proc_reg);
+ if (pre_voltage < 0) {
+ dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
+ return pre_voltage;
+ }
+
+ pre_vsram = regulator_get_voltage(drv->sram_reg);
+ if (pre_vsram < 0) {
+ dev_err(dev, "invalid vsram value: %d\n", pre_vsram);
+ return pre_vsram;
+ }
+
+ new_vsram = clamp(new_voltage + soc_data->min_volt_shift,
+ soc_data->sram_min_volt, soc_data->sram_max_volt);
+
+ do {
+ if (pre_voltage <= new_voltage) {
+ vsram = clamp(pre_voltage + soc_data->max_volt_shift,
+ soc_data->sram_min_volt, new_vsram);
+ ret = regulator_set_voltage(drv->sram_reg, vsram,
+ soc_data->sram_max_volt);
+ if (ret)
+ return ret;
+
+ if (vsram == soc_data->sram_max_volt ||
+ new_vsram == soc_data->sram_min_volt)
+ voltage = new_voltage;
+ else
+ voltage = vsram - soc_data->min_volt_shift;
+
+ ret = regulator_set_voltage(drv->proc_reg, voltage,
+ soc_data->proc_max_volt);
+ if (ret) {
+ regulator_set_voltage(drv->sram_reg, pre_vsram,
+ soc_data->sram_max_volt);
+ return ret;
+ }
+ } else if (pre_voltage > new_voltage) {
+ voltage = max(new_voltage,
+ pre_vsram - soc_data->max_volt_shift);
+ ret = regulator_set_voltage(drv->proc_reg, voltage,
+ soc_data->proc_max_volt);
+ if (ret)
+ return ret;
+
+ if (voltage == new_voltage)
+ vsram = new_vsram;
+ else
+ vsram = max(new_vsram,
+ voltage + soc_data->min_volt_shift);
+
+ ret = regulator_set_voltage(drv->sram_reg, vsram,
+ soc_data->sram_max_volt);
+ if (ret) {
+ regulator_set_voltage(drv->proc_reg, pre_voltage,
+ soc_data->proc_max_volt);
+ return ret;
+ }
+ }
+
+ pre_voltage = voltage;
+ pre_vsram = vsram;
+
+ if (--retry_max < 0) {
+ dev_err(dev,
+ "over loop count, failed to set voltage\n");
+ return -EINVAL;
+ }
+ } while (voltage != new_voltage || vsram != new_vsram);
+
+out_set_voltage:
+ if (!ret)
+ drv->pre_voltage = new_voltage;
+
+ return ret;
+}
+
+static int mtk_ccifreq_target(struct device *dev, unsigned long *freq,
+ u32 flags)
+{
+ struct mtk_ccifreq_drv *drv = dev_get_drvdata(dev);
+ struct clk *cci_pll = clk_get_parent(drv->cci_clk);
+ struct dev_pm_opp *opp;
+ unsigned long opp_rate;
+ int voltage, pre_voltage, inter_voltage, target_voltage, ret;
+
+ if (!drv)
+ return -EINVAL;
+
+ if (drv->pre_freq == *freq)
+ return 0;
+
+ inter_voltage = drv->inter_voltage;
+
+ opp_rate = *freq;
+ opp = devfreq_recommended_opp(dev, &opp_rate, 1);
+ if (IS_ERR(opp)) {
+ dev_err(dev, "failed to find opp for freq: %ld\n", opp_rate);
+ return PTR_ERR(opp);
+ }
+
+ mutex_lock(&drv->reg_lock);
+
+ voltage = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+
+ if (unlikely(drv->pre_voltage <= 0))
+ pre_voltage = regulator_get_voltage(drv->proc_reg);
+ else
+ pre_voltage = drv->pre_voltage;
+
+ if (pre_voltage < 0) {
+ dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
+ return pre_voltage;
+ }
+
+ /* scale up: set voltage first then freq. */
+ target_voltage = max(inter_voltage, voltage);
+ if (pre_voltage <= target_voltage) {
+ ret = mtk_ccifreq_set_voltage(drv, target_voltage);
+ if (ret) {
+ dev_err(dev, "failed to scale up voltage\n");
+ goto out_restore_voltage;
+ }
+ }
+
+ /* switch the cci clock to intermediate clock source. */
+ ret = clk_set_parent(drv->cci_clk, drv->inter_clk);
+ if (ret) {
+ dev_err(dev, "failed to re-parent cci clock\n");
+ goto out_restore_voltage;
+ }
+
+ /* set the original clock to target rate. */
+ ret = clk_set_rate(cci_pll, *freq);
+ if (ret) {
+ dev_err(dev, "failed to set cci pll rate: %d\n", ret);
+ clk_set_parent(drv->cci_clk, cci_pll);
+ goto out_restore_voltage;
+ }
+
+ /* switch the cci clock back to the original clock source. */
+ ret = clk_set_parent(drv->cci_clk, cci_pll);
+ if (ret) {
+ dev_err(dev, "failed to re-parent cci clock\n");
+ mtk_ccifreq_set_voltage(drv, inter_voltage);
+ goto out_unlock;
+ }
+
+ /*
+ * If the new voltage is lower than the intermediate voltage or the
+ * original voltage, scale down to the new voltage.
+ */
+ if (voltage < inter_voltage || voltage < pre_voltage) {
+ ret = mtk_ccifreq_set_voltage(drv, voltage);
+ if (ret) {
+ dev_err(dev, "failed to scale down voltage\n");
+ goto out_unlock;
+ }
+ }
+
+ drv->pre_freq = *freq;
+ mutex_unlock(&drv->reg_lock);
+
+ return 0;
+
+out_restore_voltage:
+ mtk_ccifreq_set_voltage(drv, pre_voltage);
+
+out_unlock:
+ mutex_unlock(&drv->reg_lock);
+ return ret;
+}
+
+static int mtk_ccifreq_opp_notifier(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct dev_pm_opp *opp = data;
+ struct mtk_ccifreq_drv *drv;
+ unsigned long freq, volt;
+
+ drv = container_of(nb, struct mtk_ccifreq_drv, opp_nb);
+
+ if (event == OPP_EVENT_ADJUST_VOLTAGE) {
+ freq = dev_pm_opp_get_freq(opp);
+
+ mutex_lock(&drv->reg_lock);
+ /* current opp item is changed */
+ if (freq == drv->pre_freq) {
+ volt = dev_pm_opp_get_voltage(opp);
+ mtk_ccifreq_set_voltage(drv, volt);
+ }
+ mutex_unlock(&drv->reg_lock);
+ }
+
+ return 0;
+}
+
+static struct devfreq_dev_profile mtk_ccifreq_profile = {
+ .target = mtk_ccifreq_target,
+};
+
+static int mtk_ccifreq_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ccifreq_drv *drv;
+ struct devfreq_passive_data *passive_data;
+ struct dev_pm_opp *opp;
+ unsigned long rate, opp_volt;
+ int ret;
+
+ drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
+ if (!drv)
+ return -ENOMEM;
+
+ drv->dev = dev;
+ drv->soc_data = (const struct mtk_ccifreq_platform_data *)
+ of_device_get_match_data(&pdev->dev);
+ mutex_init(&drv->reg_lock);
+ platform_set_drvdata(pdev, drv);
+
+ drv->cci_clk = devm_clk_get(dev, "cci");
+ if (IS_ERR(drv->cci_clk)) {
+ ret = PTR_ERR(drv->cci_clk);
+ return dev_err_probe(dev, ret,
+ "failed to get cci clk: %d\n", ret);
+ }
+
+ drv->inter_clk = devm_clk_get(dev, "intermediate");
+ if (IS_ERR(drv->inter_clk)) {
+ ret = PTR_ERR(drv->inter_clk);
+ dev_err_probe(dev, ret,
+ "failed to get intermediate clk: %d\n", ret);
+ goto out_free_resources;
+ }
+
+ drv->proc_reg = devm_regulator_get_optional(dev, "proc");
+ if (IS_ERR(drv->proc_reg)) {
+ ret = PTR_ERR(drv->proc_reg);
+ dev_err_probe(dev, ret,
+ "failed to get proc regulator: %d\n", ret);
+ goto out_free_resources;
+ }
+
+ ret = regulator_enable(drv->proc_reg);
+ if (ret) {
+ dev_err(dev, "failed to enable proc regulator\n");
+ goto out_free_resources;
+ }
+
+ drv->sram_reg = regulator_get_optional(dev, "sram");
+ if (IS_ERR(drv->sram_reg))
+ drv->sram_reg = NULL;
+ else {
+ ret = regulator_enable(drv->sram_reg);
+ if (ret) {
+ dev_err(dev, "failed to enable sram regulator\n");
+ goto out_free_resources;
+ }
+ }
+
+ /*
+ * We assume min voltage is 0 and tracking target voltage using
+ * min_volt_shift for each iteration.
+ * The retry_max is 3 times of expeted iteration count.
+ */
+ drv->vtrack_max = 3 * DIV_ROUND_UP(max(drv->soc_data->sram_max_volt,
+ drv->soc_data->proc_max_volt),
+ drv->soc_data->min_volt_shift);
+
+ ret = clk_prepare_enable(drv->cci_clk);
+ if (ret)
+ goto out_free_resources;
+
+ ret = clk_prepare_enable(drv->inter_clk);
+ if (ret)
+ goto out_disable_cci_clk;
+
+ ret = dev_pm_opp_of_add_table(dev);
+ if (ret) {
+ dev_err(dev, "failed to add opp table: %d\n", ret);
+ goto out_disable_inter_clk;
+ }
+
+ rate = clk_get_rate(drv->inter_clk);
+ opp = dev_pm_opp_find_freq_ceil(dev, &rate);
+ if (IS_ERR(opp)) {
+ ret = PTR_ERR(opp);
+ dev_err(dev, "failed to get intermediate opp: %d\n", ret);
+ goto out_remove_opp_table;
+ }
+ drv->inter_voltage = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+
+ rate = U32_MAX;
+ opp = dev_pm_opp_find_freq_floor(drv->dev, &rate);
+ if (IS_ERR(opp)) {
+ dev_err(dev, "failed to get opp\n");
+ ret = PTR_ERR(opp);
+ goto out_remove_opp_table;
+ }
+
+ opp_volt = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+ ret = mtk_ccifreq_set_voltage(drv, opp_volt);
+ if (ret) {
+ dev_err(dev, "failed to scale to highest voltage %lu in proc_reg\n",
+ opp_volt);
+ goto out_remove_opp_table;
+ }
+
+ passive_data = devm_kzalloc(dev, sizeof(struct devfreq_passive_data),
+ GFP_KERNEL);
+ if (!passive_data) {
+ ret = -ENOMEM;
+ goto out_remove_opp_table;
+ }
+
+ passive_data->parent_type = CPUFREQ_PARENT_DEV;
+ drv->devfreq = devm_devfreq_add_device(dev, &mtk_ccifreq_profile,
+ DEVFREQ_GOV_PASSIVE,
+ passive_data);
+ if (IS_ERR(drv->devfreq)) {
+ ret = -EPROBE_DEFER;
+ dev_err(dev, "failed to add devfreq device: %ld\n",
+ PTR_ERR(drv->devfreq));
+ goto out_remove_opp_table;
+ }
+
+ drv->opp_nb.notifier_call = mtk_ccifreq_opp_notifier;
+ ret = dev_pm_opp_register_notifier(dev, &drv->opp_nb);
+ if (ret) {
+ dev_err(dev, "failed to register opp notifier: %d\n", ret);
+ goto out_remove_devfreq_device;
+ }
+ return 0;
+
+out_remove_devfreq_device:
+ devm_devfreq_remove_device(dev, drv->devfreq);
+
+out_remove_opp_table:
+ dev_pm_opp_of_remove_table(dev);
+
+out_disable_inter_clk:
+ clk_disable_unprepare(drv->inter_clk);
+
+out_disable_cci_clk:
+ clk_disable_unprepare(drv->cci_clk);
+
+out_free_resources:
+ if (regulator_is_enabled(drv->proc_reg))
+ regulator_disable(drv->proc_reg);
+ if (drv->sram_reg && regulator_is_enabled(drv->sram_reg))
+ regulator_disable(drv->sram_reg);
+
+ if (!IS_ERR(drv->proc_reg))
+ regulator_put(drv->proc_reg);
+ if (!IS_ERR(drv->sram_reg))
+ regulator_put(drv->sram_reg);
+ if (!IS_ERR(drv->cci_clk))
+ clk_put(drv->cci_clk);
+ if (!IS_ERR(drv->inter_clk))
+ clk_put(drv->inter_clk);
+
+ return ret;
+}
+
+static int mtk_ccifreq_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ccifreq_drv *drv;
+
+ drv = platform_get_drvdata(pdev);
+
+ dev_pm_opp_unregister_notifier(dev, &drv->opp_nb);
+ dev_pm_opp_of_remove_table(dev);
+ clk_disable_unprepare(drv->inter_clk);
+ clk_disable_unprepare(drv->cci_clk);
+ regulator_disable(drv->proc_reg);
+ if (drv->sram_reg)
+ regulator_disable(drv->sram_reg);
+
+ return 0;
+}
+
+static const struct mtk_ccifreq_platform_data mt8183_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 200000,
+ .proc_max_volt = 1150000,
+ .sram_min_volt = 0,
+ .sram_max_volt = 1150000,
+};
+
+static const struct mtk_ccifreq_platform_data mt8186_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 250000,
+ .proc_max_volt = 1118750,
+ .sram_min_volt = 850000,
+ .sram_max_volt = 1118750,
+};
+
+static const struct of_device_id mtk_ccifreq_machines[] = {
+ { .compatible = "mediatek,mt8183-cci", .data = &mt8183_platform_data },
+ { .compatible = "mediatek,mt8186-cci", .data = &mt8186_platform_data },
+ { },
+};
+MODULE_DEVICE_TABLE(of, mtk_ccifreq_machines);
+
+static struct platform_driver mtk_ccifreq_platdrv = {
+ .probe = mtk_ccifreq_probe,
+ .remove = mtk_ccifreq_remove,
+ .driver = {
+ .name = "mtk-ccifreq",
+ .of_match_table = mtk_ccifreq_machines,
+ },
+};
+module_platform_driver(mtk_ccifreq_platdrv);
+
+MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
+MODULE_AUTHOR("Jia-Wei Chang <jia-wei.chang@mediatek.com>");
+MODULE_LICENSE("GPL v2");
--
2.18.0
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^ permalink raw reply related [flat|nested] 30+ messages in thread
* [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
@ 2022-05-13 3:28 ` Johnson Wang
0 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-13 3:28 UTC (permalink / raw)
To: cw00.choi, krzk+dt, robh+dt, kyungmin.park
Cc: djakov, khilman, linux-pm, linux-kernel, devicetree,
linux-arm-kernel, linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group, Johnson Wang
We introduce a devfreq driver for the MediaTek Cache Coherent Interconnect
(CCI) used by some MediaTek SoCs.
In this driver, we use the passive devfreq driver to get target frequencies
and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek CCI
is supplied by the same regulators with the little core CPUs.
Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
---
This patch depends on "devfreq-testing"[1].
[1]https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing
---
drivers/devfreq/Kconfig | 10 +
drivers/devfreq/Makefile | 1 +
drivers/devfreq/mtk-cci-devfreq.c | 474 ++++++++++++++++++++++++++++++
3 files changed, 485 insertions(+)
create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
index 87eb2b837e68..9754d8b31621 100644
--- a/drivers/devfreq/Kconfig
+++ b/drivers/devfreq/Kconfig
@@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
It reads ACTMON counters of memory controllers and adjusts the
operating frequencies and voltages with OPP support.
+config ARM_MEDIATEK_CCI_DEVFREQ
+ tristate "MEDIATEK CCI DEVFREQ Driver"
+ depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
+ select DEVFREQ_GOV_PASSIVE
+ help
+ This adds a devfreq driver for MediaTek Cache Coherent Interconnect
+ which is shared the same regulators with the cpu cluster. It can track
+ buck voltages and update a proper CCI frequency. Use the notification
+ to get the regulator status.
+
config ARM_RK3399_DMC_DEVFREQ
tristate "ARM RK3399 DMC DEVFREQ Driver"
depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
index 0b6be92a25d9..bf40d04928d0 100644
--- a/drivers/devfreq/Makefile
+++ b/drivers/devfreq/Makefile
@@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
+obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
diff --git a/drivers/devfreq/mtk-cci-devfreq.c b/drivers/devfreq/mtk-cci-devfreq.c
new file mode 100644
index 000000000000..aa8c37eb4a06
--- /dev/null
+++ b/drivers/devfreq/mtk-cci-devfreq.c
@@ -0,0 +1,474 @@
+// SPDX-License-Identifier: GPL-2.0-only
+/*
+ * Copyright (C) 2022 MediaTek Inc.
+ */
+
+#include <linux/clk.h>
+#include <linux/devfreq.h>
+#include <linux/minmax.h>
+#include <linux/module.h>
+#include <linux/of.h>
+#include <linux/of_device.h>
+#include <linux/platform_device.h>
+#include <linux/pm_opp.h>
+#include <linux/regulator/consumer.h>
+
+struct mtk_ccifreq_platform_data {
+ int min_volt_shift;
+ int max_volt_shift;
+ int proc_max_volt;
+ int sram_min_volt;
+ int sram_max_volt;
+};
+
+struct mtk_ccifreq_drv {
+ struct device *dev;
+ struct devfreq *devfreq;
+ struct regulator *proc_reg;
+ struct regulator *sram_reg;
+ struct clk *cci_clk;
+ struct clk *inter_clk;
+ int inter_voltage;
+ int pre_voltage;
+ unsigned long pre_freq;
+ /* Avoid race condition for regulators between notify and policy */
+ struct mutex reg_lock;
+ struct notifier_block opp_nb;
+ const struct mtk_ccifreq_platform_data *soc_data;
+ int vtrack_max;
+};
+
+static int mtk_ccifreq_set_voltage(struct mtk_ccifreq_drv *drv, int new_voltage)
+{
+ const struct mtk_ccifreq_platform_data *soc_data = drv->soc_data;
+ struct device *dev = drv->dev;
+ int pre_voltage, pre_vsram, new_vsram, vsram, voltage, ret;
+ int retry_max = drv->vtrack_max;
+
+ if (!drv->sram_reg) {
+ ret = regulator_set_voltage(drv->proc_reg, new_voltage,
+ drv->soc_data->proc_max_volt);
+ goto out_set_voltage;
+ }
+
+ pre_voltage = regulator_get_voltage(drv->proc_reg);
+ if (pre_voltage < 0) {
+ dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
+ return pre_voltage;
+ }
+
+ pre_vsram = regulator_get_voltage(drv->sram_reg);
+ if (pre_vsram < 0) {
+ dev_err(dev, "invalid vsram value: %d\n", pre_vsram);
+ return pre_vsram;
+ }
+
+ new_vsram = clamp(new_voltage + soc_data->min_volt_shift,
+ soc_data->sram_min_volt, soc_data->sram_max_volt);
+
+ do {
+ if (pre_voltage <= new_voltage) {
+ vsram = clamp(pre_voltage + soc_data->max_volt_shift,
+ soc_data->sram_min_volt, new_vsram);
+ ret = regulator_set_voltage(drv->sram_reg, vsram,
+ soc_data->sram_max_volt);
+ if (ret)
+ return ret;
+
+ if (vsram == soc_data->sram_max_volt ||
+ new_vsram == soc_data->sram_min_volt)
+ voltage = new_voltage;
+ else
+ voltage = vsram - soc_data->min_volt_shift;
+
+ ret = regulator_set_voltage(drv->proc_reg, voltage,
+ soc_data->proc_max_volt);
+ if (ret) {
+ regulator_set_voltage(drv->sram_reg, pre_vsram,
+ soc_data->sram_max_volt);
+ return ret;
+ }
+ } else if (pre_voltage > new_voltage) {
+ voltage = max(new_voltage,
+ pre_vsram - soc_data->max_volt_shift);
+ ret = regulator_set_voltage(drv->proc_reg, voltage,
+ soc_data->proc_max_volt);
+ if (ret)
+ return ret;
+
+ if (voltage == new_voltage)
+ vsram = new_vsram;
+ else
+ vsram = max(new_vsram,
+ voltage + soc_data->min_volt_shift);
+
+ ret = regulator_set_voltage(drv->sram_reg, vsram,
+ soc_data->sram_max_volt);
+ if (ret) {
+ regulator_set_voltage(drv->proc_reg, pre_voltage,
+ soc_data->proc_max_volt);
+ return ret;
+ }
+ }
+
+ pre_voltage = voltage;
+ pre_vsram = vsram;
+
+ if (--retry_max < 0) {
+ dev_err(dev,
+ "over loop count, failed to set voltage\n");
+ return -EINVAL;
+ }
+ } while (voltage != new_voltage || vsram != new_vsram);
+
+out_set_voltage:
+ if (!ret)
+ drv->pre_voltage = new_voltage;
+
+ return ret;
+}
+
+static int mtk_ccifreq_target(struct device *dev, unsigned long *freq,
+ u32 flags)
+{
+ struct mtk_ccifreq_drv *drv = dev_get_drvdata(dev);
+ struct clk *cci_pll = clk_get_parent(drv->cci_clk);
+ struct dev_pm_opp *opp;
+ unsigned long opp_rate;
+ int voltage, pre_voltage, inter_voltage, target_voltage, ret;
+
+ if (!drv)
+ return -EINVAL;
+
+ if (drv->pre_freq == *freq)
+ return 0;
+
+ inter_voltage = drv->inter_voltage;
+
+ opp_rate = *freq;
+ opp = devfreq_recommended_opp(dev, &opp_rate, 1);
+ if (IS_ERR(opp)) {
+ dev_err(dev, "failed to find opp for freq: %ld\n", opp_rate);
+ return PTR_ERR(opp);
+ }
+
+ mutex_lock(&drv->reg_lock);
+
+ voltage = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+
+ if (unlikely(drv->pre_voltage <= 0))
+ pre_voltage = regulator_get_voltage(drv->proc_reg);
+ else
+ pre_voltage = drv->pre_voltage;
+
+ if (pre_voltage < 0) {
+ dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
+ return pre_voltage;
+ }
+
+ /* scale up: set voltage first then freq. */
+ target_voltage = max(inter_voltage, voltage);
+ if (pre_voltage <= target_voltage) {
+ ret = mtk_ccifreq_set_voltage(drv, target_voltage);
+ if (ret) {
+ dev_err(dev, "failed to scale up voltage\n");
+ goto out_restore_voltage;
+ }
+ }
+
+ /* switch the cci clock to intermediate clock source. */
+ ret = clk_set_parent(drv->cci_clk, drv->inter_clk);
+ if (ret) {
+ dev_err(dev, "failed to re-parent cci clock\n");
+ goto out_restore_voltage;
+ }
+
+ /* set the original clock to target rate. */
+ ret = clk_set_rate(cci_pll, *freq);
+ if (ret) {
+ dev_err(dev, "failed to set cci pll rate: %d\n", ret);
+ clk_set_parent(drv->cci_clk, cci_pll);
+ goto out_restore_voltage;
+ }
+
+ /* switch the cci clock back to the original clock source. */
+ ret = clk_set_parent(drv->cci_clk, cci_pll);
+ if (ret) {
+ dev_err(dev, "failed to re-parent cci clock\n");
+ mtk_ccifreq_set_voltage(drv, inter_voltage);
+ goto out_unlock;
+ }
+
+ /*
+ * If the new voltage is lower than the intermediate voltage or the
+ * original voltage, scale down to the new voltage.
+ */
+ if (voltage < inter_voltage || voltage < pre_voltage) {
+ ret = mtk_ccifreq_set_voltage(drv, voltage);
+ if (ret) {
+ dev_err(dev, "failed to scale down voltage\n");
+ goto out_unlock;
+ }
+ }
+
+ drv->pre_freq = *freq;
+ mutex_unlock(&drv->reg_lock);
+
+ return 0;
+
+out_restore_voltage:
+ mtk_ccifreq_set_voltage(drv, pre_voltage);
+
+out_unlock:
+ mutex_unlock(&drv->reg_lock);
+ return ret;
+}
+
+static int mtk_ccifreq_opp_notifier(struct notifier_block *nb,
+ unsigned long event, void *data)
+{
+ struct dev_pm_opp *opp = data;
+ struct mtk_ccifreq_drv *drv;
+ unsigned long freq, volt;
+
+ drv = container_of(nb, struct mtk_ccifreq_drv, opp_nb);
+
+ if (event == OPP_EVENT_ADJUST_VOLTAGE) {
+ freq = dev_pm_opp_get_freq(opp);
+
+ mutex_lock(&drv->reg_lock);
+ /* current opp item is changed */
+ if (freq == drv->pre_freq) {
+ volt = dev_pm_opp_get_voltage(opp);
+ mtk_ccifreq_set_voltage(drv, volt);
+ }
+ mutex_unlock(&drv->reg_lock);
+ }
+
+ return 0;
+}
+
+static struct devfreq_dev_profile mtk_ccifreq_profile = {
+ .target = mtk_ccifreq_target,
+};
+
+static int mtk_ccifreq_probe(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ccifreq_drv *drv;
+ struct devfreq_passive_data *passive_data;
+ struct dev_pm_opp *opp;
+ unsigned long rate, opp_volt;
+ int ret;
+
+ drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
+ if (!drv)
+ return -ENOMEM;
+
+ drv->dev = dev;
+ drv->soc_data = (const struct mtk_ccifreq_platform_data *)
+ of_device_get_match_data(&pdev->dev);
+ mutex_init(&drv->reg_lock);
+ platform_set_drvdata(pdev, drv);
+
+ drv->cci_clk = devm_clk_get(dev, "cci");
+ if (IS_ERR(drv->cci_clk)) {
+ ret = PTR_ERR(drv->cci_clk);
+ return dev_err_probe(dev, ret,
+ "failed to get cci clk: %d\n", ret);
+ }
+
+ drv->inter_clk = devm_clk_get(dev, "intermediate");
+ if (IS_ERR(drv->inter_clk)) {
+ ret = PTR_ERR(drv->inter_clk);
+ dev_err_probe(dev, ret,
+ "failed to get intermediate clk: %d\n", ret);
+ goto out_free_resources;
+ }
+
+ drv->proc_reg = devm_regulator_get_optional(dev, "proc");
+ if (IS_ERR(drv->proc_reg)) {
+ ret = PTR_ERR(drv->proc_reg);
+ dev_err_probe(dev, ret,
+ "failed to get proc regulator: %d\n", ret);
+ goto out_free_resources;
+ }
+
+ ret = regulator_enable(drv->proc_reg);
+ if (ret) {
+ dev_err(dev, "failed to enable proc regulator\n");
+ goto out_free_resources;
+ }
+
+ drv->sram_reg = regulator_get_optional(dev, "sram");
+ if (IS_ERR(drv->sram_reg))
+ drv->sram_reg = NULL;
+ else {
+ ret = regulator_enable(drv->sram_reg);
+ if (ret) {
+ dev_err(dev, "failed to enable sram regulator\n");
+ goto out_free_resources;
+ }
+ }
+
+ /*
+ * We assume min voltage is 0 and tracking target voltage using
+ * min_volt_shift for each iteration.
+ * The retry_max is 3 times of expeted iteration count.
+ */
+ drv->vtrack_max = 3 * DIV_ROUND_UP(max(drv->soc_data->sram_max_volt,
+ drv->soc_data->proc_max_volt),
+ drv->soc_data->min_volt_shift);
+
+ ret = clk_prepare_enable(drv->cci_clk);
+ if (ret)
+ goto out_free_resources;
+
+ ret = clk_prepare_enable(drv->inter_clk);
+ if (ret)
+ goto out_disable_cci_clk;
+
+ ret = dev_pm_opp_of_add_table(dev);
+ if (ret) {
+ dev_err(dev, "failed to add opp table: %d\n", ret);
+ goto out_disable_inter_clk;
+ }
+
+ rate = clk_get_rate(drv->inter_clk);
+ opp = dev_pm_opp_find_freq_ceil(dev, &rate);
+ if (IS_ERR(opp)) {
+ ret = PTR_ERR(opp);
+ dev_err(dev, "failed to get intermediate opp: %d\n", ret);
+ goto out_remove_opp_table;
+ }
+ drv->inter_voltage = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+
+ rate = U32_MAX;
+ opp = dev_pm_opp_find_freq_floor(drv->dev, &rate);
+ if (IS_ERR(opp)) {
+ dev_err(dev, "failed to get opp\n");
+ ret = PTR_ERR(opp);
+ goto out_remove_opp_table;
+ }
+
+ opp_volt = dev_pm_opp_get_voltage(opp);
+ dev_pm_opp_put(opp);
+ ret = mtk_ccifreq_set_voltage(drv, opp_volt);
+ if (ret) {
+ dev_err(dev, "failed to scale to highest voltage %lu in proc_reg\n",
+ opp_volt);
+ goto out_remove_opp_table;
+ }
+
+ passive_data = devm_kzalloc(dev, sizeof(struct devfreq_passive_data),
+ GFP_KERNEL);
+ if (!passive_data) {
+ ret = -ENOMEM;
+ goto out_remove_opp_table;
+ }
+
+ passive_data->parent_type = CPUFREQ_PARENT_DEV;
+ drv->devfreq = devm_devfreq_add_device(dev, &mtk_ccifreq_profile,
+ DEVFREQ_GOV_PASSIVE,
+ passive_data);
+ if (IS_ERR(drv->devfreq)) {
+ ret = -EPROBE_DEFER;
+ dev_err(dev, "failed to add devfreq device: %ld\n",
+ PTR_ERR(drv->devfreq));
+ goto out_remove_opp_table;
+ }
+
+ drv->opp_nb.notifier_call = mtk_ccifreq_opp_notifier;
+ ret = dev_pm_opp_register_notifier(dev, &drv->opp_nb);
+ if (ret) {
+ dev_err(dev, "failed to register opp notifier: %d\n", ret);
+ goto out_remove_devfreq_device;
+ }
+ return 0;
+
+out_remove_devfreq_device:
+ devm_devfreq_remove_device(dev, drv->devfreq);
+
+out_remove_opp_table:
+ dev_pm_opp_of_remove_table(dev);
+
+out_disable_inter_clk:
+ clk_disable_unprepare(drv->inter_clk);
+
+out_disable_cci_clk:
+ clk_disable_unprepare(drv->cci_clk);
+
+out_free_resources:
+ if (regulator_is_enabled(drv->proc_reg))
+ regulator_disable(drv->proc_reg);
+ if (drv->sram_reg && regulator_is_enabled(drv->sram_reg))
+ regulator_disable(drv->sram_reg);
+
+ if (!IS_ERR(drv->proc_reg))
+ regulator_put(drv->proc_reg);
+ if (!IS_ERR(drv->sram_reg))
+ regulator_put(drv->sram_reg);
+ if (!IS_ERR(drv->cci_clk))
+ clk_put(drv->cci_clk);
+ if (!IS_ERR(drv->inter_clk))
+ clk_put(drv->inter_clk);
+
+ return ret;
+}
+
+static int mtk_ccifreq_remove(struct platform_device *pdev)
+{
+ struct device *dev = &pdev->dev;
+ struct mtk_ccifreq_drv *drv;
+
+ drv = platform_get_drvdata(pdev);
+
+ dev_pm_opp_unregister_notifier(dev, &drv->opp_nb);
+ dev_pm_opp_of_remove_table(dev);
+ clk_disable_unprepare(drv->inter_clk);
+ clk_disable_unprepare(drv->cci_clk);
+ regulator_disable(drv->proc_reg);
+ if (drv->sram_reg)
+ regulator_disable(drv->sram_reg);
+
+ return 0;
+}
+
+static const struct mtk_ccifreq_platform_data mt8183_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 200000,
+ .proc_max_volt = 1150000,
+ .sram_min_volt = 0,
+ .sram_max_volt = 1150000,
+};
+
+static const struct mtk_ccifreq_platform_data mt8186_platform_data = {
+ .min_volt_shift = 100000,
+ .max_volt_shift = 250000,
+ .proc_max_volt = 1118750,
+ .sram_min_volt = 850000,
+ .sram_max_volt = 1118750,
+};
+
+static const struct of_device_id mtk_ccifreq_machines[] = {
+ { .compatible = "mediatek,mt8183-cci", .data = &mt8183_platform_data },
+ { .compatible = "mediatek,mt8186-cci", .data = &mt8186_platform_data },
+ { },
+};
+MODULE_DEVICE_TABLE(of, mtk_ccifreq_machines);
+
+static struct platform_driver mtk_ccifreq_platdrv = {
+ .probe = mtk_ccifreq_probe,
+ .remove = mtk_ccifreq_remove,
+ .driver = {
+ .name = "mtk-ccifreq",
+ .of_match_table = mtk_ccifreq_machines,
+ },
+};
+module_platform_driver(mtk_ccifreq_platdrv);
+
+MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
+MODULE_AUTHOR("Jia-Wei Chang <jia-wei.chang@mediatek.com>");
+MODULE_LICENSE("GPL v2");
--
2.18.0
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply related [flat|nested] 30+ messages in thread
* Re: [RESEND v4 1/2] dt-bindings: interconnect: Add MediaTek CCI dt-bindings
2022-05-13 3:28 ` Johnson Wang
(?)
@ 2022-05-13 3:35 ` Chen-Yu Tsai
-1 siblings, 0 replies; 30+ messages in thread
From: Chen-Yu Tsai @ 2022-05-13 3:35 UTC (permalink / raw)
To: Johnson Wang
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Fri, May 13, 2022 at 11:31 AM Johnson Wang <johnson.wang@mediatek.com> wrote:
>
> Add devicetree binding of MediaTek CCI on MT8183 and MT8186.
>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> .../bindings/interconnect/mediatek,cci.yaml | 140 ++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 141 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
>
> diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> new file mode 100644
> index 000000000000..034c3b38ca3d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> @@ -0,0 +1,140 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
> +
> +maintainers:
> + - Jia-Wei Chang <jia-wei.chang@mediatek.com>
> + - Johnson Wang <johnson.wang@mediatek.com>
> +
> +description: |
> + MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
> + MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
> + hardware. It can also optimize the voltage to reduce the power consumption.
> +
> +properties:
> + compatible:
> + enum:
> + - mediatek,mt8183-cci
> + - mediatek,mt8186-cci
> +
> + clocks:
> + items:
> + - description:
> + The multiplexer for clock input of the bus.
> + - description:
> + A parent of "cpu" clock which is used as an intermediate clock source
Replace "cpu" with "bus"?
> + when the original CPU is under transition and not stable yet.
And also, "when the original clock source (PLL) is under transition ..."
Otherwise,
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 1/2] dt-bindings: interconnect: Add MediaTek CCI dt-bindings
@ 2022-05-13 3:35 ` Chen-Yu Tsai
0 siblings, 0 replies; 30+ messages in thread
From: Chen-Yu Tsai @ 2022-05-13 3:35 UTC (permalink / raw)
To: Johnson Wang
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Fri, May 13, 2022 at 11:31 AM Johnson Wang <johnson.wang@mediatek.com> wrote:
>
> Add devicetree binding of MediaTek CCI on MT8183 and MT8186.
>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> .../bindings/interconnect/mediatek,cci.yaml | 140 ++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 141 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
>
> diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> new file mode 100644
> index 000000000000..034c3b38ca3d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> @@ -0,0 +1,140 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
> +
> +maintainers:
> + - Jia-Wei Chang <jia-wei.chang@mediatek.com>
> + - Johnson Wang <johnson.wang@mediatek.com>
> +
> +description: |
> + MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
> + MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
> + hardware. It can also optimize the voltage to reduce the power consumption.
> +
> +properties:
> + compatible:
> + enum:
> + - mediatek,mt8183-cci
> + - mediatek,mt8186-cci
> +
> + clocks:
> + items:
> + - description:
> + The multiplexer for clock input of the bus.
> + - description:
> + A parent of "cpu" clock which is used as an intermediate clock source
Replace "cpu" with "bus"?
> + when the original CPU is under transition and not stable yet.
And also, "when the original clock source (PLL) is under transition ..."
Otherwise,
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 1/2] dt-bindings: interconnect: Add MediaTek CCI dt-bindings
@ 2022-05-13 3:35 ` Chen-Yu Tsai
0 siblings, 0 replies; 30+ messages in thread
From: Chen-Yu Tsai @ 2022-05-13 3:35 UTC (permalink / raw)
To: Johnson Wang
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Fri, May 13, 2022 at 11:31 AM Johnson Wang <johnson.wang@mediatek.com> wrote:
>
> Add devicetree binding of MediaTek CCI on MT8183 and MT8186.
>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> .../bindings/interconnect/mediatek,cci.yaml | 140 ++++++++++++++++++
> MAINTAINERS | 1 +
> 2 files changed, 141 insertions(+)
> create mode 100644 Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
>
> diff --git a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> new file mode 100644
> index 000000000000..034c3b38ca3d
> --- /dev/null
> +++ b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> @@ -0,0 +1,140 @@
> +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> +%YAML 1.2
> +---
> +$id: http://devicetree.org/schemas/interconnect/mediatek,cci.yaml#
> +$schema: http://devicetree.org/meta-schemas/core.yaml#
> +
> +title: MediaTek Cache Coherent Interconnect (CCI) frequency and voltage scaling
> +
> +maintainers:
> + - Jia-Wei Chang <jia-wei.chang@mediatek.com>
> + - Johnson Wang <johnson.wang@mediatek.com>
> +
> +description: |
> + MediaTek Cache Coherent Interconnect (CCI) is a hardware engine used by
> + MT8183 and MT8186 SoCs to scale the frequency and adjust the voltage in
> + hardware. It can also optimize the voltage to reduce the power consumption.
> +
> +properties:
> + compatible:
> + enum:
> + - mediatek,mt8183-cci
> + - mediatek,mt8186-cci
> +
> + clocks:
> + items:
> + - description:
> + The multiplexer for clock input of the bus.
> + - description:
> + A parent of "cpu" clock which is used as an intermediate clock source
Replace "cpu" with "bus"?
> + when the original CPU is under transition and not stable yet.
And also, "when the original clock source (PLL) is under transition ..."
Otherwise,
Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
2022-05-13 3:28 ` Johnson Wang
(?)
@ 2022-05-13 3:54 ` Chen-Yu Tsai
-1 siblings, 0 replies; 30+ messages in thread
From: Chen-Yu Tsai @ 2022-05-13 3:54 UTC (permalink / raw)
To: Johnson Wang
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Fri, May 13, 2022 at 11:31 AM Johnson Wang <johnson.wang@mediatek.com> wrote:
>
> We introduce a devfreq driver for the MediaTek Cache Coherent Interconnect
> (CCI) used by some MediaTek SoCs.
>
> In this driver, we use the passive devfreq driver to get target frequencies
> and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek CCI
> is supplied by the same regulators with the little core CPUs.
>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> This patch depends on "devfreq-testing"[1].
> [1]https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing
> ---
> drivers/devfreq/Kconfig | 10 +
> drivers/devfreq/Makefile | 1 +
> drivers/devfreq/mtk-cci-devfreq.c | 474 ++++++++++++++++++++++++++++++
> 3 files changed, 485 insertions(+)
> create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
>
> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> index 87eb2b837e68..9754d8b31621 100644
> --- a/drivers/devfreq/Kconfig
> +++ b/drivers/devfreq/Kconfig
> @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> It reads ACTMON counters of memory controllers and adjusts the
> operating frequencies and voltages with OPP support.
>
> +config ARM_MEDIATEK_CCI_DEVFREQ
> + tristate "MEDIATEK CCI DEVFREQ Driver"
> + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> + select DEVFREQ_GOV_PASSIVE
> + help
> + This adds a devfreq driver for MediaTek Cache Coherent Interconnect
> + which is shared the same regulators with the cpu cluster. It can track
> + buck voltages and update a proper CCI frequency. Use the notification
> + to get the regulator status.
> +
> config ARM_RK3399_DMC_DEVFREQ
> tristate "ARM RK3399 DMC DEVFREQ Driver"
> depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> index 0b6be92a25d9..bf40d04928d0 100644
> --- a/drivers/devfreq/Makefile
> +++ b/drivers/devfreq/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
> obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
> obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
> diff --git a/drivers/devfreq/mtk-cci-devfreq.c b/drivers/devfreq/mtk-cci-devfreq.c
> new file mode 100644
> index 000000000000..aa8c37eb4a06
> --- /dev/null
> +++ b/drivers/devfreq/mtk-cci-devfreq.c
> @@ -0,0 +1,474 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/devfreq.h>
> +#include <linux/minmax.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/regulator/consumer.h>
> +
> +struct mtk_ccifreq_platform_data {
> + int min_volt_shift;
> + int max_volt_shift;
> + int proc_max_volt;
> + int sram_min_volt;
> + int sram_max_volt;
> +};
> +
> +struct mtk_ccifreq_drv {
> + struct device *dev;
> + struct devfreq *devfreq;
> + struct regulator *proc_reg;
> + struct regulator *sram_reg;
> + struct clk *cci_clk;
> + struct clk *inter_clk;
> + int inter_voltage;
> + int pre_voltage;
> + unsigned long pre_freq;
> + /* Avoid race condition for regulators between notify and policy */
> + struct mutex reg_lock;
> + struct notifier_block opp_nb;
> + const struct mtk_ccifreq_platform_data *soc_data;
> + int vtrack_max;
> +};
> +
> +static int mtk_ccifreq_set_voltage(struct mtk_ccifreq_drv *drv, int new_voltage)
> +{
> + const struct mtk_ccifreq_platform_data *soc_data = drv->soc_data;
> + struct device *dev = drv->dev;
> + int pre_voltage, pre_vsram, new_vsram, vsram, voltage, ret;
> + int retry_max = drv->vtrack_max;
> +
> + if (!drv->sram_reg) {
> + ret = regulator_set_voltage(drv->proc_reg, new_voltage,
> + drv->soc_data->proc_max_volt);
> + goto out_set_voltage;
> + }
> +
> + pre_voltage = regulator_get_voltage(drv->proc_reg);
> + if (pre_voltage < 0) {
> + dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
> + return pre_voltage;
> + }
> +
> + pre_vsram = regulator_get_voltage(drv->sram_reg);
> + if (pre_vsram < 0) {
> + dev_err(dev, "invalid vsram value: %d\n", pre_vsram);
> + return pre_vsram;
> + }
> +
> + new_vsram = clamp(new_voltage + soc_data->min_volt_shift,
> + soc_data->sram_min_volt, soc_data->sram_max_volt);
> +
> + do {
> + if (pre_voltage <= new_voltage) {
> + vsram = clamp(pre_voltage + soc_data->max_volt_shift,
> + soc_data->sram_min_volt, new_vsram);
> + ret = regulator_set_voltage(drv->sram_reg, vsram,
> + soc_data->sram_max_volt);
> + if (ret)
> + return ret;
> +
> + if (vsram == soc_data->sram_max_volt ||
> + new_vsram == soc_data->sram_min_volt)
> + voltage = new_voltage;
> + else
> + voltage = vsram - soc_data->min_volt_shift;
> +
> + ret = regulator_set_voltage(drv->proc_reg, voltage,
> + soc_data->proc_max_volt);
> + if (ret) {
> + regulator_set_voltage(drv->sram_reg, pre_vsram,
> + soc_data->sram_max_volt);
> + return ret;
> + }
> + } else if (pre_voltage > new_voltage) {
> + voltage = max(new_voltage,
> + pre_vsram - soc_data->max_volt_shift);
> + ret = regulator_set_voltage(drv->proc_reg, voltage,
> + soc_data->proc_max_volt);
> + if (ret)
> + return ret;
> +
> + if (voltage == new_voltage)
> + vsram = new_vsram;
> + else
> + vsram = max(new_vsram,
> + voltage + soc_data->min_volt_shift);
> +
> + ret = regulator_set_voltage(drv->sram_reg, vsram,
> + soc_data->sram_max_volt);
> + if (ret) {
> + regulator_set_voltage(drv->proc_reg, pre_voltage,
> + soc_data->proc_max_volt);
> + return ret;
> + }
> + }
> +
> + pre_voltage = voltage;
> + pre_vsram = vsram;
> +
> + if (--retry_max < 0) {
> + dev_err(dev,
> + "over loop count, failed to set voltage\n");
> + return -EINVAL;
> + }
> + } while (voltage != new_voltage || vsram != new_vsram);
> +
> +out_set_voltage:
> + if (!ret)
> + drv->pre_voltage = new_voltage;
> +
> + return ret;
> +}
> +
> +static int mtk_ccifreq_target(struct device *dev, unsigned long *freq,
> + u32 flags)
> +{
> + struct mtk_ccifreq_drv *drv = dev_get_drvdata(dev);
> + struct clk *cci_pll = clk_get_parent(drv->cci_clk);
> + struct dev_pm_opp *opp;
> + unsigned long opp_rate;
> + int voltage, pre_voltage, inter_voltage, target_voltage, ret;
> +
> + if (!drv)
> + return -EINVAL;
> +
> + if (drv->pre_freq == *freq)
> + return 0;
> +
> + inter_voltage = drv->inter_voltage;
> +
> + opp_rate = *freq;
> + opp = devfreq_recommended_opp(dev, &opp_rate, 1);
> + if (IS_ERR(opp)) {
> + dev_err(dev, "failed to find opp for freq: %ld\n", opp_rate);
> + return PTR_ERR(opp);
> + }
> +
> + mutex_lock(&drv->reg_lock);
> +
> + voltage = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> +
> + if (unlikely(drv->pre_voltage <= 0))
> + pre_voltage = regulator_get_voltage(drv->proc_reg);
> + else
> + pre_voltage = drv->pre_voltage;
Could you explain why the previous voltage setting is cached like this?
The CCI is sharing the regulator supply with one of the CPU clusters,
and cpufreq could also change the voltage, so it's better to always
retrieve the current setting directly from the regulator core. And
those values might be cached iun the core, so it's unlikely to incur
a significant cost.
> +
> + if (pre_voltage < 0) {
> + dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
> + return pre_voltage;
> + }
> +
> + /* scale up: set voltage first then freq. */
> + target_voltage = max(inter_voltage, voltage);
> + if (pre_voltage <= target_voltage) {
> + ret = mtk_ccifreq_set_voltage(drv, target_voltage);
> + if (ret) {
> + dev_err(dev, "failed to scale up voltage\n");
> + goto out_restore_voltage;
> + }
> + }
> +
> + /* switch the cci clock to intermediate clock source. */
> + ret = clk_set_parent(drv->cci_clk, drv->inter_clk);
> + if (ret) {
> + dev_err(dev, "failed to re-parent cci clock\n");
> + goto out_restore_voltage;
> + }
> +
> + /* set the original clock to target rate. */
> + ret = clk_set_rate(cci_pll, *freq);
> + if (ret) {
> + dev_err(dev, "failed to set cci pll rate: %d\n", ret);
> + clk_set_parent(drv->cci_clk, cci_pll);
> + goto out_restore_voltage;
> + }
> +
> + /* switch the cci clock back to the original clock source. */
> + ret = clk_set_parent(drv->cci_clk, cci_pll);
> + if (ret) {
> + dev_err(dev, "failed to re-parent cci clock\n");
> + mtk_ccifreq_set_voltage(drv, inter_voltage);
> + goto out_unlock;
> + }
> +
> + /*
> + * If the new voltage is lower than the intermediate voltage or the
> + * original voltage, scale down to the new voltage.
> + */
> + if (voltage < inter_voltage || voltage < pre_voltage) {
> + ret = mtk_ccifreq_set_voltage(drv, voltage);
> + if (ret) {
> + dev_err(dev, "failed to scale down voltage\n");
> + goto out_unlock;
> + }
> + }
> +
> + drv->pre_freq = *freq;
> + mutex_unlock(&drv->reg_lock);
> +
> + return 0;
> +
> +out_restore_voltage:
> + mtk_ccifreq_set_voltage(drv, pre_voltage);
> +
> +out_unlock:
> + mutex_unlock(&drv->reg_lock);
> + return ret;
> +}
> +
> +static int mtk_ccifreq_opp_notifier(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct dev_pm_opp *opp = data;
> + struct mtk_ccifreq_drv *drv;
> + unsigned long freq, volt;
> +
> + drv = container_of(nb, struct mtk_ccifreq_drv, opp_nb);
> +
> + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + mutex_lock(&drv->reg_lock);
> + /* current opp item is changed */
> + if (freq == drv->pre_freq) {
> + volt = dev_pm_opp_get_voltage(opp);
> + mtk_ccifreq_set_voltage(drv, volt);
> + }
> + mutex_unlock(&drv->reg_lock);
> + }
> +
> + return 0;
> +}
> +
> +static struct devfreq_dev_profile mtk_ccifreq_profile = {
> + .target = mtk_ccifreq_target,
> +};
> +
> +static int mtk_ccifreq_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ccifreq_drv *drv;
> + struct devfreq_passive_data *passive_data;
> + struct dev_pm_opp *opp;
> + unsigned long rate, opp_volt;
> + int ret;
> +
> + drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
> + if (!drv)
> + return -ENOMEM;
> +
> + drv->dev = dev;
> + drv->soc_data = (const struct mtk_ccifreq_platform_data *)
> + of_device_get_match_data(&pdev->dev);
> + mutex_init(&drv->reg_lock);
> + platform_set_drvdata(pdev, drv);
> +
> + drv->cci_clk = devm_clk_get(dev, "cci");
> + if (IS_ERR(drv->cci_clk)) {
> + ret = PTR_ERR(drv->cci_clk);
> + return dev_err_probe(dev, ret,
> + "failed to get cci clk: %d\n", ret);
> + }
> +
> + drv->inter_clk = devm_clk_get(dev, "intermediate");
> + if (IS_ERR(drv->inter_clk)) {
> + ret = PTR_ERR(drv->inter_clk);
> + dev_err_probe(dev, ret,
> + "failed to get intermediate clk: %d\n", ret);
> + goto out_free_resources;
> + }
> +
> + drv->proc_reg = devm_regulator_get_optional(dev, "proc");
> + if (IS_ERR(drv->proc_reg)) {
> + ret = PTR_ERR(drv->proc_reg);
> + dev_err_probe(dev, ret,
> + "failed to get proc regulator: %d\n", ret);
> + goto out_free_resources;
> + }
> +
> + ret = regulator_enable(drv->proc_reg);
> + if (ret) {
> + dev_err(dev, "failed to enable proc regulator\n");
> + goto out_free_resources;
> + }
> +
> + drv->sram_reg = regulator_get_optional(dev, "sram");
devm_ for this as well?
> + if (IS_ERR(drv->sram_reg))
> + drv->sram_reg = NULL;
> + else {
> + ret = regulator_enable(drv->sram_reg);
> + if (ret) {
> + dev_err(dev, "failed to enable sram regulator\n");
> + goto out_free_resources;
> + }
> + }
> +
> + /*
> + * We assume min voltage is 0 and tracking target voltage using
> + * min_volt_shift for each iteration.
> + * The retry_max is 3 times of expeted iteration count.
expected?
> + */
> + drv->vtrack_max = 3 * DIV_ROUND_UP(max(drv->soc_data->sram_max_volt,
> + drv->soc_data->proc_max_volt),
> + drv->soc_data->min_volt_shift);
> +
> + ret = clk_prepare_enable(drv->cci_clk);
> + if (ret)
> + goto out_free_resources;
> +
> + ret = clk_prepare_enable(drv->inter_clk);
You don't need to enable the intermediate clock here. You shouldn't need
to at all, as the CCF core will do it when the CCI clock is reparented
over to it.
> + if (ret)
> + goto out_disable_cci_clk;
> +
> + ret = dev_pm_opp_of_add_table(dev);
> + if (ret) {
> + dev_err(dev, "failed to add opp table: %d\n", ret);
> + goto out_disable_inter_clk;
> + }
> +
> + rate = clk_get_rate(drv->inter_clk);
> + opp = dev_pm_opp_find_freq_ceil(dev, &rate);
> + if (IS_ERR(opp)) {
> + ret = PTR_ERR(opp);
> + dev_err(dev, "failed to get intermediate opp: %d\n", ret);
> + goto out_remove_opp_table;
> + }
> + drv->inter_voltage = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> +
> + rate = U32_MAX;
> + opp = dev_pm_opp_find_freq_floor(drv->dev, &rate);
> + if (IS_ERR(opp)) {
> + dev_err(dev, "failed to get opp\n");
> + ret = PTR_ERR(opp);
> + goto out_remove_opp_table;
> + }
> +
> + opp_volt = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> + ret = mtk_ccifreq_set_voltage(drv, opp_volt);
> + if (ret) {
> + dev_err(dev, "failed to scale to highest voltage %lu in proc_reg\n",
> + opp_volt);
> + goto out_remove_opp_table;
> + }
> +
> + passive_data = devm_kzalloc(dev, sizeof(struct devfreq_passive_data),
> + GFP_KERNEL);
> + if (!passive_data) {
> + ret = -ENOMEM;
> + goto out_remove_opp_table;
> + }
> +
> + passive_data->parent_type = CPUFREQ_PARENT_DEV;
> + drv->devfreq = devm_devfreq_add_device(dev, &mtk_ccifreq_profile,
> + DEVFREQ_GOV_PASSIVE,
> + passive_data);
> + if (IS_ERR(drv->devfreq)) {
> + ret = -EPROBE_DEFER;
> + dev_err(dev, "failed to add devfreq device: %ld\n",
> + PTR_ERR(drv->devfreq));
> + goto out_remove_opp_table;
> + }
> +
> + drv->opp_nb.notifier_call = mtk_ccifreq_opp_notifier;
> + ret = dev_pm_opp_register_notifier(dev, &drv->opp_nb);
> + if (ret) {
> + dev_err(dev, "failed to register opp notifier: %d\n", ret);
> + goto out_remove_devfreq_device;
> + }
> + return 0;
> +
> +out_remove_devfreq_device:
> + devm_devfreq_remove_device(dev, drv->devfreq);
> +
> +out_remove_opp_table:
> + dev_pm_opp_of_remove_table(dev);
> +
> +out_disable_inter_clk:
> + clk_disable_unprepare(drv->inter_clk);
> +
> +out_disable_cci_clk:
> + clk_disable_unprepare(drv->cci_clk);
> +
> +out_free_resources:
> + if (regulator_is_enabled(drv->proc_reg))
> + regulator_disable(drv->proc_reg);
> + if (drv->sram_reg && regulator_is_enabled(drv->sram_reg))
> + regulator_disable(drv->sram_reg);
> +
> + if (!IS_ERR(drv->proc_reg))
> + regulator_put(drv->proc_reg);
> + if (!IS_ERR(drv->sram_reg))
> + regulator_put(drv->sram_reg);
> + if (!IS_ERR(drv->cci_clk))
> + clk_put(drv->cci_clk);
> + if (!IS_ERR(drv->inter_clk))
> + clk_put(drv->inter_clk);
You don't need to "put" the resources you got using devm_ variants.
If you really want to, you need to use devm_(clk|regulator)_put.
> +
> + return ret;
> +}
> +
> +static int mtk_ccifreq_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ccifreq_drv *drv;
> +
> + drv = platform_get_drvdata(pdev);
> +
> + dev_pm_opp_unregister_notifier(dev, &drv->opp_nb);
> + dev_pm_opp_of_remove_table(dev);
> + clk_disable_unprepare(drv->inter_clk);
> + clk_disable_unprepare(drv->cci_clk);
> + regulator_disable(drv->proc_reg);
> + if (drv->sram_reg)
> + regulator_disable(drv->sram_reg);
> +
> + return 0;
> +}
> +
> +static const struct mtk_ccifreq_platform_data mt8183_platform_data = {
> + .min_volt_shift = 100000,
> + .max_volt_shift = 200000,
> + .proc_max_volt = 1150000,
> + .sram_min_volt = 0,
> + .sram_max_volt = 1150000,
AFAICT there's no sram supply for MT8183, so set max to zero as well?
And you can just drop the two lines instead of explicitly setting
them to zero.
> +};
> +
> +static const struct mtk_ccifreq_platform_data mt8186_platform_data = {
> + .min_volt_shift = 100000,
> + .max_volt_shift = 250000,
> + .proc_max_volt = 1118750,
> + .sram_min_volt = 850000,
> + .sram_max_volt = 1118750,
A side note about this: the min/max voltage values should also be set
on the regulator nodes in the device tree. The range then gets enforced
by the regulator core.
Regards
ChenYu
> +};
> +
> +static const struct of_device_id mtk_ccifreq_machines[] = {
> + { .compatible = "mediatek,mt8183-cci", .data = &mt8183_platform_data },
> + { .compatible = "mediatek,mt8186-cci", .data = &mt8186_platform_data },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_ccifreq_machines);
> +
> +static struct platform_driver mtk_ccifreq_platdrv = {
> + .probe = mtk_ccifreq_probe,
> + .remove = mtk_ccifreq_remove,
> + .driver = {
> + .name = "mtk-ccifreq",
> + .of_match_table = mtk_ccifreq_machines,
> + },
> +};
> +module_platform_driver(mtk_ccifreq_platdrv);
> +
> +MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
> +MODULE_AUTHOR("Jia-Wei Chang <jia-wei.chang@mediatek.com>");
> +MODULE_LICENSE("GPL v2");
> --
> 2.18.0
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
@ 2022-05-13 3:54 ` Chen-Yu Tsai
0 siblings, 0 replies; 30+ messages in thread
From: Chen-Yu Tsai @ 2022-05-13 3:54 UTC (permalink / raw)
To: Johnson Wang
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Fri, May 13, 2022 at 11:31 AM Johnson Wang <johnson.wang@mediatek.com> wrote:
>
> We introduce a devfreq driver for the MediaTek Cache Coherent Interconnect
> (CCI) used by some MediaTek SoCs.
>
> In this driver, we use the passive devfreq driver to get target frequencies
> and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek CCI
> is supplied by the same regulators with the little core CPUs.
>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> This patch depends on "devfreq-testing"[1].
> [1]https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing
> ---
> drivers/devfreq/Kconfig | 10 +
> drivers/devfreq/Makefile | 1 +
> drivers/devfreq/mtk-cci-devfreq.c | 474 ++++++++++++++++++++++++++++++
> 3 files changed, 485 insertions(+)
> create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
>
> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> index 87eb2b837e68..9754d8b31621 100644
> --- a/drivers/devfreq/Kconfig
> +++ b/drivers/devfreq/Kconfig
> @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> It reads ACTMON counters of memory controllers and adjusts the
> operating frequencies and voltages with OPP support.
>
> +config ARM_MEDIATEK_CCI_DEVFREQ
> + tristate "MEDIATEK CCI DEVFREQ Driver"
> + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> + select DEVFREQ_GOV_PASSIVE
> + help
> + This adds a devfreq driver for MediaTek Cache Coherent Interconnect
> + which is shared the same regulators with the cpu cluster. It can track
> + buck voltages and update a proper CCI frequency. Use the notification
> + to get the regulator status.
> +
> config ARM_RK3399_DMC_DEVFREQ
> tristate "ARM RK3399 DMC DEVFREQ Driver"
> depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> index 0b6be92a25d9..bf40d04928d0 100644
> --- a/drivers/devfreq/Makefile
> +++ b/drivers/devfreq/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
> obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
> obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
> diff --git a/drivers/devfreq/mtk-cci-devfreq.c b/drivers/devfreq/mtk-cci-devfreq.c
> new file mode 100644
> index 000000000000..aa8c37eb4a06
> --- /dev/null
> +++ b/drivers/devfreq/mtk-cci-devfreq.c
> @@ -0,0 +1,474 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/devfreq.h>
> +#include <linux/minmax.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/regulator/consumer.h>
> +
> +struct mtk_ccifreq_platform_data {
> + int min_volt_shift;
> + int max_volt_shift;
> + int proc_max_volt;
> + int sram_min_volt;
> + int sram_max_volt;
> +};
> +
> +struct mtk_ccifreq_drv {
> + struct device *dev;
> + struct devfreq *devfreq;
> + struct regulator *proc_reg;
> + struct regulator *sram_reg;
> + struct clk *cci_clk;
> + struct clk *inter_clk;
> + int inter_voltage;
> + int pre_voltage;
> + unsigned long pre_freq;
> + /* Avoid race condition for regulators between notify and policy */
> + struct mutex reg_lock;
> + struct notifier_block opp_nb;
> + const struct mtk_ccifreq_platform_data *soc_data;
> + int vtrack_max;
> +};
> +
> +static int mtk_ccifreq_set_voltage(struct mtk_ccifreq_drv *drv, int new_voltage)
> +{
> + const struct mtk_ccifreq_platform_data *soc_data = drv->soc_data;
> + struct device *dev = drv->dev;
> + int pre_voltage, pre_vsram, new_vsram, vsram, voltage, ret;
> + int retry_max = drv->vtrack_max;
> +
> + if (!drv->sram_reg) {
> + ret = regulator_set_voltage(drv->proc_reg, new_voltage,
> + drv->soc_data->proc_max_volt);
> + goto out_set_voltage;
> + }
> +
> + pre_voltage = regulator_get_voltage(drv->proc_reg);
> + if (pre_voltage < 0) {
> + dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
> + return pre_voltage;
> + }
> +
> + pre_vsram = regulator_get_voltage(drv->sram_reg);
> + if (pre_vsram < 0) {
> + dev_err(dev, "invalid vsram value: %d\n", pre_vsram);
> + return pre_vsram;
> + }
> +
> + new_vsram = clamp(new_voltage + soc_data->min_volt_shift,
> + soc_data->sram_min_volt, soc_data->sram_max_volt);
> +
> + do {
> + if (pre_voltage <= new_voltage) {
> + vsram = clamp(pre_voltage + soc_data->max_volt_shift,
> + soc_data->sram_min_volt, new_vsram);
> + ret = regulator_set_voltage(drv->sram_reg, vsram,
> + soc_data->sram_max_volt);
> + if (ret)
> + return ret;
> +
> + if (vsram == soc_data->sram_max_volt ||
> + new_vsram == soc_data->sram_min_volt)
> + voltage = new_voltage;
> + else
> + voltage = vsram - soc_data->min_volt_shift;
> +
> + ret = regulator_set_voltage(drv->proc_reg, voltage,
> + soc_data->proc_max_volt);
> + if (ret) {
> + regulator_set_voltage(drv->sram_reg, pre_vsram,
> + soc_data->sram_max_volt);
> + return ret;
> + }
> + } else if (pre_voltage > new_voltage) {
> + voltage = max(new_voltage,
> + pre_vsram - soc_data->max_volt_shift);
> + ret = regulator_set_voltage(drv->proc_reg, voltage,
> + soc_data->proc_max_volt);
> + if (ret)
> + return ret;
> +
> + if (voltage == new_voltage)
> + vsram = new_vsram;
> + else
> + vsram = max(new_vsram,
> + voltage + soc_data->min_volt_shift);
> +
> + ret = regulator_set_voltage(drv->sram_reg, vsram,
> + soc_data->sram_max_volt);
> + if (ret) {
> + regulator_set_voltage(drv->proc_reg, pre_voltage,
> + soc_data->proc_max_volt);
> + return ret;
> + }
> + }
> +
> + pre_voltage = voltage;
> + pre_vsram = vsram;
> +
> + if (--retry_max < 0) {
> + dev_err(dev,
> + "over loop count, failed to set voltage\n");
> + return -EINVAL;
> + }
> + } while (voltage != new_voltage || vsram != new_vsram);
> +
> +out_set_voltage:
> + if (!ret)
> + drv->pre_voltage = new_voltage;
> +
> + return ret;
> +}
> +
> +static int mtk_ccifreq_target(struct device *dev, unsigned long *freq,
> + u32 flags)
> +{
> + struct mtk_ccifreq_drv *drv = dev_get_drvdata(dev);
> + struct clk *cci_pll = clk_get_parent(drv->cci_clk);
> + struct dev_pm_opp *opp;
> + unsigned long opp_rate;
> + int voltage, pre_voltage, inter_voltage, target_voltage, ret;
> +
> + if (!drv)
> + return -EINVAL;
> +
> + if (drv->pre_freq == *freq)
> + return 0;
> +
> + inter_voltage = drv->inter_voltage;
> +
> + opp_rate = *freq;
> + opp = devfreq_recommended_opp(dev, &opp_rate, 1);
> + if (IS_ERR(opp)) {
> + dev_err(dev, "failed to find opp for freq: %ld\n", opp_rate);
> + return PTR_ERR(opp);
> + }
> +
> + mutex_lock(&drv->reg_lock);
> +
> + voltage = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> +
> + if (unlikely(drv->pre_voltage <= 0))
> + pre_voltage = regulator_get_voltage(drv->proc_reg);
> + else
> + pre_voltage = drv->pre_voltage;
Could you explain why the previous voltage setting is cached like this?
The CCI is sharing the regulator supply with one of the CPU clusters,
and cpufreq could also change the voltage, so it's better to always
retrieve the current setting directly from the regulator core. And
those values might be cached iun the core, so it's unlikely to incur
a significant cost.
> +
> + if (pre_voltage < 0) {
> + dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
> + return pre_voltage;
> + }
> +
> + /* scale up: set voltage first then freq. */
> + target_voltage = max(inter_voltage, voltage);
> + if (pre_voltage <= target_voltage) {
> + ret = mtk_ccifreq_set_voltage(drv, target_voltage);
> + if (ret) {
> + dev_err(dev, "failed to scale up voltage\n");
> + goto out_restore_voltage;
> + }
> + }
> +
> + /* switch the cci clock to intermediate clock source. */
> + ret = clk_set_parent(drv->cci_clk, drv->inter_clk);
> + if (ret) {
> + dev_err(dev, "failed to re-parent cci clock\n");
> + goto out_restore_voltage;
> + }
> +
> + /* set the original clock to target rate. */
> + ret = clk_set_rate(cci_pll, *freq);
> + if (ret) {
> + dev_err(dev, "failed to set cci pll rate: %d\n", ret);
> + clk_set_parent(drv->cci_clk, cci_pll);
> + goto out_restore_voltage;
> + }
> +
> + /* switch the cci clock back to the original clock source. */
> + ret = clk_set_parent(drv->cci_clk, cci_pll);
> + if (ret) {
> + dev_err(dev, "failed to re-parent cci clock\n");
> + mtk_ccifreq_set_voltage(drv, inter_voltage);
> + goto out_unlock;
> + }
> +
> + /*
> + * If the new voltage is lower than the intermediate voltage or the
> + * original voltage, scale down to the new voltage.
> + */
> + if (voltage < inter_voltage || voltage < pre_voltage) {
> + ret = mtk_ccifreq_set_voltage(drv, voltage);
> + if (ret) {
> + dev_err(dev, "failed to scale down voltage\n");
> + goto out_unlock;
> + }
> + }
> +
> + drv->pre_freq = *freq;
> + mutex_unlock(&drv->reg_lock);
> +
> + return 0;
> +
> +out_restore_voltage:
> + mtk_ccifreq_set_voltage(drv, pre_voltage);
> +
> +out_unlock:
> + mutex_unlock(&drv->reg_lock);
> + return ret;
> +}
> +
> +static int mtk_ccifreq_opp_notifier(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct dev_pm_opp *opp = data;
> + struct mtk_ccifreq_drv *drv;
> + unsigned long freq, volt;
> +
> + drv = container_of(nb, struct mtk_ccifreq_drv, opp_nb);
> +
> + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + mutex_lock(&drv->reg_lock);
> + /* current opp item is changed */
> + if (freq == drv->pre_freq) {
> + volt = dev_pm_opp_get_voltage(opp);
> + mtk_ccifreq_set_voltage(drv, volt);
> + }
> + mutex_unlock(&drv->reg_lock);
> + }
> +
> + return 0;
> +}
> +
> +static struct devfreq_dev_profile mtk_ccifreq_profile = {
> + .target = mtk_ccifreq_target,
> +};
> +
> +static int mtk_ccifreq_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ccifreq_drv *drv;
> + struct devfreq_passive_data *passive_data;
> + struct dev_pm_opp *opp;
> + unsigned long rate, opp_volt;
> + int ret;
> +
> + drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
> + if (!drv)
> + return -ENOMEM;
> +
> + drv->dev = dev;
> + drv->soc_data = (const struct mtk_ccifreq_platform_data *)
> + of_device_get_match_data(&pdev->dev);
> + mutex_init(&drv->reg_lock);
> + platform_set_drvdata(pdev, drv);
> +
> + drv->cci_clk = devm_clk_get(dev, "cci");
> + if (IS_ERR(drv->cci_clk)) {
> + ret = PTR_ERR(drv->cci_clk);
> + return dev_err_probe(dev, ret,
> + "failed to get cci clk: %d\n", ret);
> + }
> +
> + drv->inter_clk = devm_clk_get(dev, "intermediate");
> + if (IS_ERR(drv->inter_clk)) {
> + ret = PTR_ERR(drv->inter_clk);
> + dev_err_probe(dev, ret,
> + "failed to get intermediate clk: %d\n", ret);
> + goto out_free_resources;
> + }
> +
> + drv->proc_reg = devm_regulator_get_optional(dev, "proc");
> + if (IS_ERR(drv->proc_reg)) {
> + ret = PTR_ERR(drv->proc_reg);
> + dev_err_probe(dev, ret,
> + "failed to get proc regulator: %d\n", ret);
> + goto out_free_resources;
> + }
> +
> + ret = regulator_enable(drv->proc_reg);
> + if (ret) {
> + dev_err(dev, "failed to enable proc regulator\n");
> + goto out_free_resources;
> + }
> +
> + drv->sram_reg = regulator_get_optional(dev, "sram");
devm_ for this as well?
> + if (IS_ERR(drv->sram_reg))
> + drv->sram_reg = NULL;
> + else {
> + ret = regulator_enable(drv->sram_reg);
> + if (ret) {
> + dev_err(dev, "failed to enable sram regulator\n");
> + goto out_free_resources;
> + }
> + }
> +
> + /*
> + * We assume min voltage is 0 and tracking target voltage using
> + * min_volt_shift for each iteration.
> + * The retry_max is 3 times of expeted iteration count.
expected?
> + */
> + drv->vtrack_max = 3 * DIV_ROUND_UP(max(drv->soc_data->sram_max_volt,
> + drv->soc_data->proc_max_volt),
> + drv->soc_data->min_volt_shift);
> +
> + ret = clk_prepare_enable(drv->cci_clk);
> + if (ret)
> + goto out_free_resources;
> +
> + ret = clk_prepare_enable(drv->inter_clk);
You don't need to enable the intermediate clock here. You shouldn't need
to at all, as the CCF core will do it when the CCI clock is reparented
over to it.
> + if (ret)
> + goto out_disable_cci_clk;
> +
> + ret = dev_pm_opp_of_add_table(dev);
> + if (ret) {
> + dev_err(dev, "failed to add opp table: %d\n", ret);
> + goto out_disable_inter_clk;
> + }
> +
> + rate = clk_get_rate(drv->inter_clk);
> + opp = dev_pm_opp_find_freq_ceil(dev, &rate);
> + if (IS_ERR(opp)) {
> + ret = PTR_ERR(opp);
> + dev_err(dev, "failed to get intermediate opp: %d\n", ret);
> + goto out_remove_opp_table;
> + }
> + drv->inter_voltage = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> +
> + rate = U32_MAX;
> + opp = dev_pm_opp_find_freq_floor(drv->dev, &rate);
> + if (IS_ERR(opp)) {
> + dev_err(dev, "failed to get opp\n");
> + ret = PTR_ERR(opp);
> + goto out_remove_opp_table;
> + }
> +
> + opp_volt = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> + ret = mtk_ccifreq_set_voltage(drv, opp_volt);
> + if (ret) {
> + dev_err(dev, "failed to scale to highest voltage %lu in proc_reg\n",
> + opp_volt);
> + goto out_remove_opp_table;
> + }
> +
> + passive_data = devm_kzalloc(dev, sizeof(struct devfreq_passive_data),
> + GFP_KERNEL);
> + if (!passive_data) {
> + ret = -ENOMEM;
> + goto out_remove_opp_table;
> + }
> +
> + passive_data->parent_type = CPUFREQ_PARENT_DEV;
> + drv->devfreq = devm_devfreq_add_device(dev, &mtk_ccifreq_profile,
> + DEVFREQ_GOV_PASSIVE,
> + passive_data);
> + if (IS_ERR(drv->devfreq)) {
> + ret = -EPROBE_DEFER;
> + dev_err(dev, "failed to add devfreq device: %ld\n",
> + PTR_ERR(drv->devfreq));
> + goto out_remove_opp_table;
> + }
> +
> + drv->opp_nb.notifier_call = mtk_ccifreq_opp_notifier;
> + ret = dev_pm_opp_register_notifier(dev, &drv->opp_nb);
> + if (ret) {
> + dev_err(dev, "failed to register opp notifier: %d\n", ret);
> + goto out_remove_devfreq_device;
> + }
> + return 0;
> +
> +out_remove_devfreq_device:
> + devm_devfreq_remove_device(dev, drv->devfreq);
> +
> +out_remove_opp_table:
> + dev_pm_opp_of_remove_table(dev);
> +
> +out_disable_inter_clk:
> + clk_disable_unprepare(drv->inter_clk);
> +
> +out_disable_cci_clk:
> + clk_disable_unprepare(drv->cci_clk);
> +
> +out_free_resources:
> + if (regulator_is_enabled(drv->proc_reg))
> + regulator_disable(drv->proc_reg);
> + if (drv->sram_reg && regulator_is_enabled(drv->sram_reg))
> + regulator_disable(drv->sram_reg);
> +
> + if (!IS_ERR(drv->proc_reg))
> + regulator_put(drv->proc_reg);
> + if (!IS_ERR(drv->sram_reg))
> + regulator_put(drv->sram_reg);
> + if (!IS_ERR(drv->cci_clk))
> + clk_put(drv->cci_clk);
> + if (!IS_ERR(drv->inter_clk))
> + clk_put(drv->inter_clk);
You don't need to "put" the resources you got using devm_ variants.
If you really want to, you need to use devm_(clk|regulator)_put.
> +
> + return ret;
> +}
> +
> +static int mtk_ccifreq_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ccifreq_drv *drv;
> +
> + drv = platform_get_drvdata(pdev);
> +
> + dev_pm_opp_unregister_notifier(dev, &drv->opp_nb);
> + dev_pm_opp_of_remove_table(dev);
> + clk_disable_unprepare(drv->inter_clk);
> + clk_disable_unprepare(drv->cci_clk);
> + regulator_disable(drv->proc_reg);
> + if (drv->sram_reg)
> + regulator_disable(drv->sram_reg);
> +
> + return 0;
> +}
> +
> +static const struct mtk_ccifreq_platform_data mt8183_platform_data = {
> + .min_volt_shift = 100000,
> + .max_volt_shift = 200000,
> + .proc_max_volt = 1150000,
> + .sram_min_volt = 0,
> + .sram_max_volt = 1150000,
AFAICT there's no sram supply for MT8183, so set max to zero as well?
And you can just drop the two lines instead of explicitly setting
them to zero.
> +};
> +
> +static const struct mtk_ccifreq_platform_data mt8186_platform_data = {
> + .min_volt_shift = 100000,
> + .max_volt_shift = 250000,
> + .proc_max_volt = 1118750,
> + .sram_min_volt = 850000,
> + .sram_max_volt = 1118750,
A side note about this: the min/max voltage values should also be set
on the regulator nodes in the device tree. The range then gets enforced
by the regulator core.
Regards
ChenYu
> +};
> +
> +static const struct of_device_id mtk_ccifreq_machines[] = {
> + { .compatible = "mediatek,mt8183-cci", .data = &mt8183_platform_data },
> + { .compatible = "mediatek,mt8186-cci", .data = &mt8186_platform_data },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_ccifreq_machines);
> +
> +static struct platform_driver mtk_ccifreq_platdrv = {
> + .probe = mtk_ccifreq_probe,
> + .remove = mtk_ccifreq_remove,
> + .driver = {
> + .name = "mtk-ccifreq",
> + .of_match_table = mtk_ccifreq_machines,
> + },
> +};
> +module_platform_driver(mtk_ccifreq_platdrv);
> +
> +MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
> +MODULE_AUTHOR("Jia-Wei Chang <jia-wei.chang@mediatek.com>");
> +MODULE_LICENSE("GPL v2");
> --
> 2.18.0
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
@ 2022-05-13 3:54 ` Chen-Yu Tsai
0 siblings, 0 replies; 30+ messages in thread
From: Chen-Yu Tsai @ 2022-05-13 3:54 UTC (permalink / raw)
To: Johnson Wang
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Fri, May 13, 2022 at 11:31 AM Johnson Wang <johnson.wang@mediatek.com> wrote:
>
> We introduce a devfreq driver for the MediaTek Cache Coherent Interconnect
> (CCI) used by some MediaTek SoCs.
>
> In this driver, we use the passive devfreq driver to get target frequencies
> and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek CCI
> is supplied by the same regulators with the little core CPUs.
>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> This patch depends on "devfreq-testing"[1].
> [1]https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing
> ---
> drivers/devfreq/Kconfig | 10 +
> drivers/devfreq/Makefile | 1 +
> drivers/devfreq/mtk-cci-devfreq.c | 474 ++++++++++++++++++++++++++++++
> 3 files changed, 485 insertions(+)
> create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
>
> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> index 87eb2b837e68..9754d8b31621 100644
> --- a/drivers/devfreq/Kconfig
> +++ b/drivers/devfreq/Kconfig
> @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> It reads ACTMON counters of memory controllers and adjusts the
> operating frequencies and voltages with OPP support.
>
> +config ARM_MEDIATEK_CCI_DEVFREQ
> + tristate "MEDIATEK CCI DEVFREQ Driver"
> + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> + select DEVFREQ_GOV_PASSIVE
> + help
> + This adds a devfreq driver for MediaTek Cache Coherent Interconnect
> + which is shared the same regulators with the cpu cluster. It can track
> + buck voltages and update a proper CCI frequency. Use the notification
> + to get the regulator status.
> +
> config ARM_RK3399_DMC_DEVFREQ
> tristate "ARM RK3399 DMC DEVFREQ Driver"
> depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> index 0b6be92a25d9..bf40d04928d0 100644
> --- a/drivers/devfreq/Makefile
> +++ b/drivers/devfreq/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) += governor_passive.o
> obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
> obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
> diff --git a/drivers/devfreq/mtk-cci-devfreq.c b/drivers/devfreq/mtk-cci-devfreq.c
> new file mode 100644
> index 000000000000..aa8c37eb4a06
> --- /dev/null
> +++ b/drivers/devfreq/mtk-cci-devfreq.c
> @@ -0,0 +1,474 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/devfreq.h>
> +#include <linux/minmax.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/regulator/consumer.h>
> +
> +struct mtk_ccifreq_platform_data {
> + int min_volt_shift;
> + int max_volt_shift;
> + int proc_max_volt;
> + int sram_min_volt;
> + int sram_max_volt;
> +};
> +
> +struct mtk_ccifreq_drv {
> + struct device *dev;
> + struct devfreq *devfreq;
> + struct regulator *proc_reg;
> + struct regulator *sram_reg;
> + struct clk *cci_clk;
> + struct clk *inter_clk;
> + int inter_voltage;
> + int pre_voltage;
> + unsigned long pre_freq;
> + /* Avoid race condition for regulators between notify and policy */
> + struct mutex reg_lock;
> + struct notifier_block opp_nb;
> + const struct mtk_ccifreq_platform_data *soc_data;
> + int vtrack_max;
> +};
> +
> +static int mtk_ccifreq_set_voltage(struct mtk_ccifreq_drv *drv, int new_voltage)
> +{
> + const struct mtk_ccifreq_platform_data *soc_data = drv->soc_data;
> + struct device *dev = drv->dev;
> + int pre_voltage, pre_vsram, new_vsram, vsram, voltage, ret;
> + int retry_max = drv->vtrack_max;
> +
> + if (!drv->sram_reg) {
> + ret = regulator_set_voltage(drv->proc_reg, new_voltage,
> + drv->soc_data->proc_max_volt);
> + goto out_set_voltage;
> + }
> +
> + pre_voltage = regulator_get_voltage(drv->proc_reg);
> + if (pre_voltage < 0) {
> + dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
> + return pre_voltage;
> + }
> +
> + pre_vsram = regulator_get_voltage(drv->sram_reg);
> + if (pre_vsram < 0) {
> + dev_err(dev, "invalid vsram value: %d\n", pre_vsram);
> + return pre_vsram;
> + }
> +
> + new_vsram = clamp(new_voltage + soc_data->min_volt_shift,
> + soc_data->sram_min_volt, soc_data->sram_max_volt);
> +
> + do {
> + if (pre_voltage <= new_voltage) {
> + vsram = clamp(pre_voltage + soc_data->max_volt_shift,
> + soc_data->sram_min_volt, new_vsram);
> + ret = regulator_set_voltage(drv->sram_reg, vsram,
> + soc_data->sram_max_volt);
> + if (ret)
> + return ret;
> +
> + if (vsram == soc_data->sram_max_volt ||
> + new_vsram == soc_data->sram_min_volt)
> + voltage = new_voltage;
> + else
> + voltage = vsram - soc_data->min_volt_shift;
> +
> + ret = regulator_set_voltage(drv->proc_reg, voltage,
> + soc_data->proc_max_volt);
> + if (ret) {
> + regulator_set_voltage(drv->sram_reg, pre_vsram,
> + soc_data->sram_max_volt);
> + return ret;
> + }
> + } else if (pre_voltage > new_voltage) {
> + voltage = max(new_voltage,
> + pre_vsram - soc_data->max_volt_shift);
> + ret = regulator_set_voltage(drv->proc_reg, voltage,
> + soc_data->proc_max_volt);
> + if (ret)
> + return ret;
> +
> + if (voltage == new_voltage)
> + vsram = new_vsram;
> + else
> + vsram = max(new_vsram,
> + voltage + soc_data->min_volt_shift);
> +
> + ret = regulator_set_voltage(drv->sram_reg, vsram,
> + soc_data->sram_max_volt);
> + if (ret) {
> + regulator_set_voltage(drv->proc_reg, pre_voltage,
> + soc_data->proc_max_volt);
> + return ret;
> + }
> + }
> +
> + pre_voltage = voltage;
> + pre_vsram = vsram;
> +
> + if (--retry_max < 0) {
> + dev_err(dev,
> + "over loop count, failed to set voltage\n");
> + return -EINVAL;
> + }
> + } while (voltage != new_voltage || vsram != new_vsram);
> +
> +out_set_voltage:
> + if (!ret)
> + drv->pre_voltage = new_voltage;
> +
> + return ret;
> +}
> +
> +static int mtk_ccifreq_target(struct device *dev, unsigned long *freq,
> + u32 flags)
> +{
> + struct mtk_ccifreq_drv *drv = dev_get_drvdata(dev);
> + struct clk *cci_pll = clk_get_parent(drv->cci_clk);
> + struct dev_pm_opp *opp;
> + unsigned long opp_rate;
> + int voltage, pre_voltage, inter_voltage, target_voltage, ret;
> +
> + if (!drv)
> + return -EINVAL;
> +
> + if (drv->pre_freq == *freq)
> + return 0;
> +
> + inter_voltage = drv->inter_voltage;
> +
> + opp_rate = *freq;
> + opp = devfreq_recommended_opp(dev, &opp_rate, 1);
> + if (IS_ERR(opp)) {
> + dev_err(dev, "failed to find opp for freq: %ld\n", opp_rate);
> + return PTR_ERR(opp);
> + }
> +
> + mutex_lock(&drv->reg_lock);
> +
> + voltage = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> +
> + if (unlikely(drv->pre_voltage <= 0))
> + pre_voltage = regulator_get_voltage(drv->proc_reg);
> + else
> + pre_voltage = drv->pre_voltage;
Could you explain why the previous voltage setting is cached like this?
The CCI is sharing the regulator supply with one of the CPU clusters,
and cpufreq could also change the voltage, so it's better to always
retrieve the current setting directly from the regulator core. And
those values might be cached iun the core, so it's unlikely to incur
a significant cost.
> +
> + if (pre_voltage < 0) {
> + dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
> + return pre_voltage;
> + }
> +
> + /* scale up: set voltage first then freq. */
> + target_voltage = max(inter_voltage, voltage);
> + if (pre_voltage <= target_voltage) {
> + ret = mtk_ccifreq_set_voltage(drv, target_voltage);
> + if (ret) {
> + dev_err(dev, "failed to scale up voltage\n");
> + goto out_restore_voltage;
> + }
> + }
> +
> + /* switch the cci clock to intermediate clock source. */
> + ret = clk_set_parent(drv->cci_clk, drv->inter_clk);
> + if (ret) {
> + dev_err(dev, "failed to re-parent cci clock\n");
> + goto out_restore_voltage;
> + }
> +
> + /* set the original clock to target rate. */
> + ret = clk_set_rate(cci_pll, *freq);
> + if (ret) {
> + dev_err(dev, "failed to set cci pll rate: %d\n", ret);
> + clk_set_parent(drv->cci_clk, cci_pll);
> + goto out_restore_voltage;
> + }
> +
> + /* switch the cci clock back to the original clock source. */
> + ret = clk_set_parent(drv->cci_clk, cci_pll);
> + if (ret) {
> + dev_err(dev, "failed to re-parent cci clock\n");
> + mtk_ccifreq_set_voltage(drv, inter_voltage);
> + goto out_unlock;
> + }
> +
> + /*
> + * If the new voltage is lower than the intermediate voltage or the
> + * original voltage, scale down to the new voltage.
> + */
> + if (voltage < inter_voltage || voltage < pre_voltage) {
> + ret = mtk_ccifreq_set_voltage(drv, voltage);
> + if (ret) {
> + dev_err(dev, "failed to scale down voltage\n");
> + goto out_unlock;
> + }
> + }
> +
> + drv->pre_freq = *freq;
> + mutex_unlock(&drv->reg_lock);
> +
> + return 0;
> +
> +out_restore_voltage:
> + mtk_ccifreq_set_voltage(drv, pre_voltage);
> +
> +out_unlock:
> + mutex_unlock(&drv->reg_lock);
> + return ret;
> +}
> +
> +static int mtk_ccifreq_opp_notifier(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct dev_pm_opp *opp = data;
> + struct mtk_ccifreq_drv *drv;
> + unsigned long freq, volt;
> +
> + drv = container_of(nb, struct mtk_ccifreq_drv, opp_nb);
> +
> + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + mutex_lock(&drv->reg_lock);
> + /* current opp item is changed */
> + if (freq == drv->pre_freq) {
> + volt = dev_pm_opp_get_voltage(opp);
> + mtk_ccifreq_set_voltage(drv, volt);
> + }
> + mutex_unlock(&drv->reg_lock);
> + }
> +
> + return 0;
> +}
> +
> +static struct devfreq_dev_profile mtk_ccifreq_profile = {
> + .target = mtk_ccifreq_target,
> +};
> +
> +static int mtk_ccifreq_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ccifreq_drv *drv;
> + struct devfreq_passive_data *passive_data;
> + struct dev_pm_opp *opp;
> + unsigned long rate, opp_volt;
> + int ret;
> +
> + drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
> + if (!drv)
> + return -ENOMEM;
> +
> + drv->dev = dev;
> + drv->soc_data = (const struct mtk_ccifreq_platform_data *)
> + of_device_get_match_data(&pdev->dev);
> + mutex_init(&drv->reg_lock);
> + platform_set_drvdata(pdev, drv);
> +
> + drv->cci_clk = devm_clk_get(dev, "cci");
> + if (IS_ERR(drv->cci_clk)) {
> + ret = PTR_ERR(drv->cci_clk);
> + return dev_err_probe(dev, ret,
> + "failed to get cci clk: %d\n", ret);
> + }
> +
> + drv->inter_clk = devm_clk_get(dev, "intermediate");
> + if (IS_ERR(drv->inter_clk)) {
> + ret = PTR_ERR(drv->inter_clk);
> + dev_err_probe(dev, ret,
> + "failed to get intermediate clk: %d\n", ret);
> + goto out_free_resources;
> + }
> +
> + drv->proc_reg = devm_regulator_get_optional(dev, "proc");
> + if (IS_ERR(drv->proc_reg)) {
> + ret = PTR_ERR(drv->proc_reg);
> + dev_err_probe(dev, ret,
> + "failed to get proc regulator: %d\n", ret);
> + goto out_free_resources;
> + }
> +
> + ret = regulator_enable(drv->proc_reg);
> + if (ret) {
> + dev_err(dev, "failed to enable proc regulator\n");
> + goto out_free_resources;
> + }
> +
> + drv->sram_reg = regulator_get_optional(dev, "sram");
devm_ for this as well?
> + if (IS_ERR(drv->sram_reg))
> + drv->sram_reg = NULL;
> + else {
> + ret = regulator_enable(drv->sram_reg);
> + if (ret) {
> + dev_err(dev, "failed to enable sram regulator\n");
> + goto out_free_resources;
> + }
> + }
> +
> + /*
> + * We assume min voltage is 0 and tracking target voltage using
> + * min_volt_shift for each iteration.
> + * The retry_max is 3 times of expeted iteration count.
expected?
> + */
> + drv->vtrack_max = 3 * DIV_ROUND_UP(max(drv->soc_data->sram_max_volt,
> + drv->soc_data->proc_max_volt),
> + drv->soc_data->min_volt_shift);
> +
> + ret = clk_prepare_enable(drv->cci_clk);
> + if (ret)
> + goto out_free_resources;
> +
> + ret = clk_prepare_enable(drv->inter_clk);
You don't need to enable the intermediate clock here. You shouldn't need
to at all, as the CCF core will do it when the CCI clock is reparented
over to it.
> + if (ret)
> + goto out_disable_cci_clk;
> +
> + ret = dev_pm_opp_of_add_table(dev);
> + if (ret) {
> + dev_err(dev, "failed to add opp table: %d\n", ret);
> + goto out_disable_inter_clk;
> + }
> +
> + rate = clk_get_rate(drv->inter_clk);
> + opp = dev_pm_opp_find_freq_ceil(dev, &rate);
> + if (IS_ERR(opp)) {
> + ret = PTR_ERR(opp);
> + dev_err(dev, "failed to get intermediate opp: %d\n", ret);
> + goto out_remove_opp_table;
> + }
> + drv->inter_voltage = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> +
> + rate = U32_MAX;
> + opp = dev_pm_opp_find_freq_floor(drv->dev, &rate);
> + if (IS_ERR(opp)) {
> + dev_err(dev, "failed to get opp\n");
> + ret = PTR_ERR(opp);
> + goto out_remove_opp_table;
> + }
> +
> + opp_volt = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> + ret = mtk_ccifreq_set_voltage(drv, opp_volt);
> + if (ret) {
> + dev_err(dev, "failed to scale to highest voltage %lu in proc_reg\n",
> + opp_volt);
> + goto out_remove_opp_table;
> + }
> +
> + passive_data = devm_kzalloc(dev, sizeof(struct devfreq_passive_data),
> + GFP_KERNEL);
> + if (!passive_data) {
> + ret = -ENOMEM;
> + goto out_remove_opp_table;
> + }
> +
> + passive_data->parent_type = CPUFREQ_PARENT_DEV;
> + drv->devfreq = devm_devfreq_add_device(dev, &mtk_ccifreq_profile,
> + DEVFREQ_GOV_PASSIVE,
> + passive_data);
> + if (IS_ERR(drv->devfreq)) {
> + ret = -EPROBE_DEFER;
> + dev_err(dev, "failed to add devfreq device: %ld\n",
> + PTR_ERR(drv->devfreq));
> + goto out_remove_opp_table;
> + }
> +
> + drv->opp_nb.notifier_call = mtk_ccifreq_opp_notifier;
> + ret = dev_pm_opp_register_notifier(dev, &drv->opp_nb);
> + if (ret) {
> + dev_err(dev, "failed to register opp notifier: %d\n", ret);
> + goto out_remove_devfreq_device;
> + }
> + return 0;
> +
> +out_remove_devfreq_device:
> + devm_devfreq_remove_device(dev, drv->devfreq);
> +
> +out_remove_opp_table:
> + dev_pm_opp_of_remove_table(dev);
> +
> +out_disable_inter_clk:
> + clk_disable_unprepare(drv->inter_clk);
> +
> +out_disable_cci_clk:
> + clk_disable_unprepare(drv->cci_clk);
> +
> +out_free_resources:
> + if (regulator_is_enabled(drv->proc_reg))
> + regulator_disable(drv->proc_reg);
> + if (drv->sram_reg && regulator_is_enabled(drv->sram_reg))
> + regulator_disable(drv->sram_reg);
> +
> + if (!IS_ERR(drv->proc_reg))
> + regulator_put(drv->proc_reg);
> + if (!IS_ERR(drv->sram_reg))
> + regulator_put(drv->sram_reg);
> + if (!IS_ERR(drv->cci_clk))
> + clk_put(drv->cci_clk);
> + if (!IS_ERR(drv->inter_clk))
> + clk_put(drv->inter_clk);
You don't need to "put" the resources you got using devm_ variants.
If you really want to, you need to use devm_(clk|regulator)_put.
> +
> + return ret;
> +}
> +
> +static int mtk_ccifreq_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ccifreq_drv *drv;
> +
> + drv = platform_get_drvdata(pdev);
> +
> + dev_pm_opp_unregister_notifier(dev, &drv->opp_nb);
> + dev_pm_opp_of_remove_table(dev);
> + clk_disable_unprepare(drv->inter_clk);
> + clk_disable_unprepare(drv->cci_clk);
> + regulator_disable(drv->proc_reg);
> + if (drv->sram_reg)
> + regulator_disable(drv->sram_reg);
> +
> + return 0;
> +}
> +
> +static const struct mtk_ccifreq_platform_data mt8183_platform_data = {
> + .min_volt_shift = 100000,
> + .max_volt_shift = 200000,
> + .proc_max_volt = 1150000,
> + .sram_min_volt = 0,
> + .sram_max_volt = 1150000,
AFAICT there's no sram supply for MT8183, so set max to zero as well?
And you can just drop the two lines instead of explicitly setting
them to zero.
> +};
> +
> +static const struct mtk_ccifreq_platform_data mt8186_platform_data = {
> + .min_volt_shift = 100000,
> + .max_volt_shift = 250000,
> + .proc_max_volt = 1118750,
> + .sram_min_volt = 850000,
> + .sram_max_volt = 1118750,
A side note about this: the min/max voltage values should also be set
on the regulator nodes in the device tree. The range then gets enforced
by the regulator core.
Regards
ChenYu
> +};
> +
> +static const struct of_device_id mtk_ccifreq_machines[] = {
> + { .compatible = "mediatek,mt8183-cci", .data = &mt8183_platform_data },
> + { .compatible = "mediatek,mt8186-cci", .data = &mt8186_platform_data },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_ccifreq_machines);
> +
> +static struct platform_driver mtk_ccifreq_platdrv = {
> + .probe = mtk_ccifreq_probe,
> + .remove = mtk_ccifreq_remove,
> + .driver = {
> + .name = "mtk-ccifreq",
> + .of_match_table = mtk_ccifreq_machines,
> + },
> +};
> +module_platform_driver(mtk_ccifreq_platdrv);
> +
> +MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
> +MODULE_AUTHOR("Jia-Wei Chang <jia-wei.chang@mediatek.com>");
> +MODULE_LICENSE("GPL v2");
> --
> 2.18.0
>
>
> _______________________________________________
> Linux-mediatek mailing list
> Linux-mediatek@lists.infradead.org
> http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
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linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
2022-05-13 3:28 ` Johnson Wang
(?)
@ 2022-05-13 4:39 ` Rex-BC Chen
-1 siblings, 0 replies; 30+ messages in thread
From: Rex-BC Chen @ 2022-05-13 4:39 UTC (permalink / raw)
To: Johnson Wang, cw00.choi, krzk+dt, robh+dt, kyungmin.park
Cc: djakov, khilman, linux-pm, linux-kernel, devicetree,
linux-arm-kernel, linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Fri, 2022-05-13 at 11:28 +0800, Johnson Wang wrote:
> We introduce a devfreq driver for the MediaTek Cache Coherent
> Interconnect
> (CCI) used by some MediaTek SoCs.
>
> In this driver, we use the passive devfreq driver to get target
> frequencies
> and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek
> CCI
> is supplied by the same regulators with the little core CPUs.
>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> This patch depends on "devfreq-testing"[1].
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing
> ---
> drivers/devfreq/Kconfig | 10 +
> drivers/devfreq/Makefile | 1 +
> drivers/devfreq/mtk-cci-devfreq.c | 474
> ++++++++++++++++++++++++++++++
> 3 files changed, 485 insertions(+)
> create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
>
> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> index 87eb2b837e68..9754d8b31621 100644
> --- a/drivers/devfreq/Kconfig
> +++ b/drivers/devfreq/Kconfig
> @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> It reads ACTMON counters of memory controllers and adjusts
> the
> operating frequencies and voltages with OPP support.
>
> +config ARM_MEDIATEK_CCI_DEVFREQ
> + tristate "MEDIATEK CCI DEVFREQ Driver"
> + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> + select DEVFREQ_GOV_PASSIVE
> + help
> + This adds a devfreq driver for MediaTek Cache Coherent
> Interconnect
> + which is shared the same regulators with the cpu cluster. It
> can track
> + buck voltages and update a proper CCI frequency. Use the
> notification
> + to get the regulator status.
> +
> config ARM_RK3399_DMC_DEVFREQ
> tristate "ARM RK3399 DMC DEVFREQ Driver"
> depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> index 0b6be92a25d9..bf40d04928d0 100644
> --- a/drivers/devfreq/Makefile
> +++ b/drivers/devfreq/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=
> governor_passive.o
> obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
> obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
> diff --git a/drivers/devfreq/mtk-cci-devfreq.c b/drivers/devfreq/mtk-
> cci-devfreq.c
> new file mode 100644
> index 000000000000..aa8c37eb4a06
> --- /dev/null
> +++ b/drivers/devfreq/mtk-cci-devfreq.c
> @@ -0,0 +1,474 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/devfreq.h>
> +#include <linux/minmax.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/regulator/consumer.h>
> +
> +struct mtk_ccifreq_platform_data {
> + int min_volt_shift;
> + int max_volt_shift;
> + int proc_max_volt;
> + int sram_min_volt;
> + int sram_max_volt;
> +};
> +
> +struct mtk_ccifreq_drv {
> + struct device *dev;
> + struct devfreq *devfreq;
> + struct regulator *proc_reg;
> + struct regulator *sram_reg;
> + struct clk *cci_clk;
> + struct clk *inter_clk;
> + int inter_voltage;
> + int pre_voltage;
> + unsigned long pre_freq;
> + /* Avoid race condition for regulators between notify and
> policy */
> + struct mutex reg_lock;
> + struct notifier_block opp_nb;
> + const struct mtk_ccifreq_platform_data *soc_data;
> + int vtrack_max;
> +};
> +
> +static int mtk_ccifreq_set_voltage(struct mtk_ccifreq_drv *drv, int
> new_voltage)
> +{
> + const struct mtk_ccifreq_platform_data *soc_data = drv-
> >soc_data;
> + struct device *dev = drv->dev;
> + int pre_voltage, pre_vsram, new_vsram, vsram, voltage, ret;
> + int retry_max = drv->vtrack_max;
> +
> + if (!drv->sram_reg) {
> + ret = regulator_set_voltage(drv->proc_reg, new_voltage,
> + drv->soc_data-
> >proc_max_volt);
> + goto out_set_voltage;
> + }
> +
> + pre_voltage = regulator_get_voltage(drv->proc_reg);
> + if (pre_voltage < 0) {
> + dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
> + return pre_voltage;
> + }
> +
> + pre_vsram = regulator_get_voltage(drv->sram_reg);
> + if (pre_vsram < 0) {
> + dev_err(dev, "invalid vsram value: %d\n", pre_vsram);
> + return pre_vsram;
> + }
> +
> + new_vsram = clamp(new_voltage + soc_data->min_volt_shift,
> + soc_data->sram_min_volt, soc_data-
> >sram_max_volt);
> +
> + do {
> + if (pre_voltage <= new_voltage) {
> + vsram = clamp(pre_voltage + soc_data-
> >max_volt_shift,
> + soc_data->sram_min_volt,
> new_vsram);
> + ret = regulator_set_voltage(drv->sram_reg,
> vsram,
> + soc_data-
> >sram_max_volt);
> + if (ret)
> + return ret;
> +
> + if (vsram == soc_data->sram_max_volt ||
> + new_vsram == soc_data->sram_min_volt)
> + voltage = new_voltage;
> + else
> + voltage = vsram - soc_data-
> >min_volt_shift;
> +
> + ret = regulator_set_voltage(drv->proc_reg,
> voltage,
> + soc_data-
> >proc_max_volt);
> + if (ret) {
> + regulator_set_voltage(drv->sram_reg,
> pre_vsram,
> + soc_data-
> >sram_max_volt);
> + return ret;
> + }
> + } else if (pre_voltage > new_voltage) {
> + voltage = max(new_voltage,
> + pre_vsram - soc_data-
> >max_volt_shift);
> + ret = regulator_set_voltage(drv->proc_reg,
> voltage,
> + soc_data-
> >proc_max_volt);
> + if (ret)
> + return ret;
> +
> + if (voltage == new_voltage)
> + vsram = new_vsram;
> + else
> + vsram = max(new_vsram,
> + voltage + soc_data-
> >min_volt_shift);
> +
> + ret = regulator_set_voltage(drv->sram_reg,
> vsram,
> + soc_data-
> >sram_max_volt);
> + if (ret) {
> + regulator_set_voltage(drv->proc_reg,
> pre_voltage,
> + soc_data-
> >proc_max_volt);
> + return ret;
> + }
> + }
> +
> + pre_voltage = voltage;
> + pre_vsram = vsram;
> +
> + if (--retry_max < 0) {
> + dev_err(dev,
> + "over loop count, failed to set
> voltage\n");
> + return -EINVAL;
> + }
> + } while (voltage != new_voltage || vsram != new_vsram);
> +
> +out_set_voltage:
> + if (!ret)
> + drv->pre_voltage = new_voltage;
> +
> + return ret;
> +}
> +
> +static int mtk_ccifreq_target(struct device *dev, unsigned long
> *freq,
> + u32 flags)
> +{
> + struct mtk_ccifreq_drv *drv = dev_get_drvdata(dev);
> + struct clk *cci_pll = clk_get_parent(drv->cci_clk);
> + struct dev_pm_opp *opp;
> + unsigned long opp_rate;
> + int voltage, pre_voltage, inter_voltage, target_voltage, ret;
> +
> + if (!drv)
> + return -EINVAL;
> +
> + if (drv->pre_freq == *freq)
> + return 0;
> +
> + inter_voltage = drv->inter_voltage;
> +
> + opp_rate = *freq;
> + opp = devfreq_recommended_opp(dev, &opp_rate, 1);
> + if (IS_ERR(opp)) {
> + dev_err(dev, "failed to find opp for freq: %ld\n",
> opp_rate);
> + return PTR_ERR(opp);
> + }
> +
> + mutex_lock(&drv->reg_lock);
> +
> + voltage = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> +
> + if (unlikely(drv->pre_voltage <= 0))
> + pre_voltage = regulator_get_voltage(drv->proc_reg);
> + else
> + pre_voltage = drv->pre_voltage;
> +
> + if (pre_voltage < 0) {
> + dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
> + return pre_voltage;
this should be:
goto out_restore_voltage;
the mutex will not be unlocked.
> + }
> +
> + /* scale up: set voltage first then freq. */
> + target_voltage = max(inter_voltage, voltage);
> + if (pre_voltage <= target_voltage) {
> + ret = mtk_ccifreq_set_voltage(drv, target_voltage);
> + if (ret) {
> + dev_err(dev, "failed to scale up voltage\n");
> + goto out_restore_voltage;
> + }
> + }
> +
> + /* switch the cci clock to intermediate clock source. */
> + ret = clk_set_parent(drv->cci_clk, drv->inter_clk);
> + if (ret) {
> + dev_err(dev, "failed to re-parent cci clock\n");
> + goto out_restore_voltage;
> + }
> +
> + /* set the original clock to target rate. */
> + ret = clk_set_rate(cci_pll, *freq);
> + if (ret) {
> + dev_err(dev, "failed to set cci pll rate: %d\n", ret);
> + clk_set_parent(drv->cci_clk, cci_pll);
> + goto out_restore_voltage;
> + }
> +
> + /* switch the cci clock back to the original clock source. */
> + ret = clk_set_parent(drv->cci_clk, cci_pll);
> + if (ret) {
> + dev_err(dev, "failed to re-parent cci clock\n");
> + mtk_ccifreq_set_voltage(drv, inter_voltage);
> + goto out_unlock;
> + }
> +
> + /*
> + * If the new voltage is lower than the intermediate voltage or
> the
> + * original voltage, scale down to the new voltage.
> + */
> + if (voltage < inter_voltage || voltage < pre_voltage) {
> + ret = mtk_ccifreq_set_voltage(drv, voltage);
> + if (ret) {
> + dev_err(dev, "failed to scale down voltage\n");
> + goto out_unlock;
> + }
> + }
> +
> + drv->pre_freq = *freq;
> + mutex_unlock(&drv->reg_lock);
> +
> + return 0;
> +
> +out_restore_voltage:
> + mtk_ccifreq_set_voltage(drv, pre_voltage);
> +
> +out_unlock:
> + mutex_unlock(&drv->reg_lock);
> + return ret;
> +}
> +
> +static int mtk_ccifreq_opp_notifier(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct dev_pm_opp *opp = data;
> + struct mtk_ccifreq_drv *drv;
> + unsigned long freq, volt;
> +
> + drv = container_of(nb, struct mtk_ccifreq_drv, opp_nb);
> +
> + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + mutex_lock(&drv->reg_lock);
> + /* current opp item is changed */
> + if (freq == drv->pre_freq) {
> + volt = dev_pm_opp_get_voltage(opp);
> + mtk_ccifreq_set_voltage(drv, volt);
> + }
> + mutex_unlock(&drv->reg_lock);
> + }
> +
> + return 0;
> +}
> +
> +static struct devfreq_dev_profile mtk_ccifreq_profile = {
> + .target = mtk_ccifreq_target,
> +};
> +
> +static int mtk_ccifreq_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ccifreq_drv *drv;
> + struct devfreq_passive_data *passive_data;
> + struct dev_pm_opp *opp;
> + unsigned long rate, opp_volt;
> + int ret;
> +
> + drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
> + if (!drv)
> + return -ENOMEM;
> +
> + drv->dev = dev;
> + drv->soc_data = (const struct mtk_ccifreq_platform_data *)
> + of_device_get_match_data(&pdev->dev);
> + mutex_init(&drv->reg_lock);
> + platform_set_drvdata(pdev, drv);
> +
> + drv->cci_clk = devm_clk_get(dev, "cci");
> + if (IS_ERR(drv->cci_clk)) {
> + ret = PTR_ERR(drv->cci_clk);
> + return dev_err_probe(dev, ret,
> + "failed to get cci clk: %d\n",
> ret);
> + }
> +
> + drv->inter_clk = devm_clk_get(dev, "intermediate");
> + if (IS_ERR(drv->inter_clk)) {
> + ret = PTR_ERR(drv->inter_clk);
> + dev_err_probe(dev, ret,
> + "failed to get intermediate clk: %d\n",
> ret);
> + goto out_free_resources;
> + }
> +
> + drv->proc_reg = devm_regulator_get_optional(dev, "proc");
> + if (IS_ERR(drv->proc_reg)) {
> + ret = PTR_ERR(drv->proc_reg);
> + dev_err_probe(dev, ret,
> + "failed to get proc regulator: %d\n",
> ret);
> + goto out_free_resources;
> + }
> +
> + ret = regulator_enable(drv->proc_reg);
> + if (ret) {
> + dev_err(dev, "failed to enable proc regulator\n");
> + goto out_free_resources;
> + }
> +
> + drv->sram_reg = regulator_get_optional(dev, "sram");
> + if (IS_ERR(drv->sram_reg))
> + drv->sram_reg = NULL;
> + else {
> + ret = regulator_enable(drv->sram_reg);
> + if (ret) {
> + dev_err(dev, "failed to enable sram
> regulator\n");
> + goto out_free_resources;
> + }
> + }
> +
> + /*
> + * We assume min voltage is 0 and tracking target voltage using
> + * min_volt_shift for each iteration.
> + * The retry_max is 3 times of expeted iteration count.
> + */
> + drv->vtrack_max = 3 * DIV_ROUND_UP(max(drv->soc_data-
> >sram_max_volt,
> + drv->soc_data-
> >proc_max_volt),
> + drv->soc_data-
> >min_volt_shift);
> +
> + ret = clk_prepare_enable(drv->cci_clk);
> + if (ret)
> + goto out_free_resources;
> +
> + ret = clk_prepare_enable(drv->inter_clk);
> + if (ret)
> + goto out_disable_cci_clk;
> +
> + ret = dev_pm_opp_of_add_table(dev);
> + if (ret) {
> + dev_err(dev, "failed to add opp table: %d\n", ret);
> + goto out_disable_inter_clk;
> + }
> +
> + rate = clk_get_rate(drv->inter_clk);
> + opp = dev_pm_opp_find_freq_ceil(dev, &rate);
> + if (IS_ERR(opp)) {
> + ret = PTR_ERR(opp);
> + dev_err(dev, "failed to get intermediate opp: %d\n",
> ret);
> + goto out_remove_opp_table;
> + }
> + drv->inter_voltage = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> +
> + rate = U32_MAX;
> + opp = dev_pm_opp_find_freq_floor(drv->dev, &rate);
> + if (IS_ERR(opp)) {
> + dev_err(dev, "failed to get opp\n");
> + ret = PTR_ERR(opp);
> + goto out_remove_opp_table;
> + }
> +
> + opp_volt = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> + ret = mtk_ccifreq_set_voltage(drv, opp_volt);
> + if (ret) {
> + dev_err(dev, "failed to scale to highest voltage %lu in
> proc_reg\n",
> + opp_volt);
> + goto out_remove_opp_table;
> + }
> +
> + passive_data = devm_kzalloc(dev, sizeof(struct
> devfreq_passive_data),
> + GFP_KERNEL);
> + if (!passive_data) {
> + ret = -ENOMEM;
> + goto out_remove_opp_table;
> + }
> +
> + passive_data->parent_type = CPUFREQ_PARENT_DEV;
> + drv->devfreq = devm_devfreq_add_device(dev,
> &mtk_ccifreq_profile,
> + DEVFREQ_GOV_PASSIVE,
> + passive_data);
> + if (IS_ERR(drv->devfreq)) {
> + ret = -EPROBE_DEFER;
> + dev_err(dev, "failed to add devfreq device: %ld\n",
> + PTR_ERR(drv->devfreq));
> + goto out_remove_opp_table;
> + }
> +
> + drv->opp_nb.notifier_call = mtk_ccifreq_opp_notifier;
> + ret = dev_pm_opp_register_notifier(dev, &drv->opp_nb);
> + if (ret) {
> + dev_err(dev, "failed to register opp notifier: %d\n",
> ret);
> + goto out_remove_devfreq_device;
> + }
> + return 0;
> +
> +out_remove_devfreq_device:
> + devm_devfreq_remove_device(dev, drv->devfreq);
> +
> +out_remove_opp_table:
> + dev_pm_opp_of_remove_table(dev);
> +
> +out_disable_inter_clk:
> + clk_disable_unprepare(drv->inter_clk);
> +
> +out_disable_cci_clk:
> + clk_disable_unprepare(drv->cci_clk);
> +
> +out_free_resources:
> + if (regulator_is_enabled(drv->proc_reg))
> + regulator_disable(drv->proc_reg);
> + if (drv->sram_reg && regulator_is_enabled(drv->sram_reg))
> + regulator_disable(drv->sram_reg);
> +
> + if (!IS_ERR(drv->proc_reg))
> + regulator_put(drv->proc_reg);
> + if (!IS_ERR(drv->sram_reg))
> + regulator_put(drv->sram_reg);
> + if (!IS_ERR(drv->cci_clk))
> + clk_put(drv->cci_clk);
> + if (!IS_ERR(drv->inter_clk))
> + clk_put(drv->inter_clk);
> +
> + return ret;
> +}
> +
> +static int mtk_ccifreq_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ccifreq_drv *drv;
> +
> + drv = platform_get_drvdata(pdev);
> +
> + dev_pm_opp_unregister_notifier(dev, &drv->opp_nb);
> + dev_pm_opp_of_remove_table(dev);
> + clk_disable_unprepare(drv->inter_clk);
> + clk_disable_unprepare(drv->cci_clk);
> + regulator_disable(drv->proc_reg);
> + if (drv->sram_reg)
> + regulator_disable(drv->sram_reg);
> +
> + return 0;
> +}
> +
> +static const struct mtk_ccifreq_platform_data mt8183_platform_data =
> {
> + .min_volt_shift = 100000,
> + .max_volt_shift = 200000,
> + .proc_max_volt = 1150000,
> + .sram_min_volt = 0,
> + .sram_max_volt = 1150000,
> +};
> +
> +static const struct mtk_ccifreq_platform_data mt8186_platform_data =
> {
> + .min_volt_shift = 100000,
> + .max_volt_shift = 250000,
> + .proc_max_volt = 1118750,
> + .sram_min_volt = 850000,
> + .sram_max_volt = 1118750,
> +};
> +
> +static const struct of_device_id mtk_ccifreq_machines[] = {
> + { .compatible = "mediatek,mt8183-cci", .data =
> &mt8183_platform_data },
> + { .compatible = "mediatek,mt8186-cci", .data =
> &mt8186_platform_data },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_ccifreq_machines);
> +
> +static struct platform_driver mtk_ccifreq_platdrv = {
> + .probe = mtk_ccifreq_probe,
> + .remove = mtk_ccifreq_remove,
> + .driver = {
> + .name = "mtk-ccifreq",
> + .of_match_table = mtk_ccifreq_machines,
> + },
> +};
> +module_platform_driver(mtk_ccifreq_platdrv);
> +
> +MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
> +MODULE_AUTHOR("Jia-Wei Chang <jia-wei.chang@mediatek.com>");
> +MODULE_LICENSE("GPL v2");
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
@ 2022-05-13 4:39 ` Rex-BC Chen
0 siblings, 0 replies; 30+ messages in thread
From: Rex-BC Chen @ 2022-05-13 4:39 UTC (permalink / raw)
To: Johnson Wang, cw00.choi, krzk+dt, robh+dt, kyungmin.park
Cc: djakov, khilman, linux-pm, linux-kernel, devicetree,
linux-arm-kernel, linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Fri, 2022-05-13 at 11:28 +0800, Johnson Wang wrote:
> We introduce a devfreq driver for the MediaTek Cache Coherent
> Interconnect
> (CCI) used by some MediaTek SoCs.
>
> In this driver, we use the passive devfreq driver to get target
> frequencies
> and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek
> CCI
> is supplied by the same regulators with the little core CPUs.
>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> This patch depends on "devfreq-testing"[1].
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing
> ---
> drivers/devfreq/Kconfig | 10 +
> drivers/devfreq/Makefile | 1 +
> drivers/devfreq/mtk-cci-devfreq.c | 474
> ++++++++++++++++++++++++++++++
> 3 files changed, 485 insertions(+)
> create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
>
> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> index 87eb2b837e68..9754d8b31621 100644
> --- a/drivers/devfreq/Kconfig
> +++ b/drivers/devfreq/Kconfig
> @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> It reads ACTMON counters of memory controllers and adjusts
> the
> operating frequencies and voltages with OPP support.
>
> +config ARM_MEDIATEK_CCI_DEVFREQ
> + tristate "MEDIATEK CCI DEVFREQ Driver"
> + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> + select DEVFREQ_GOV_PASSIVE
> + help
> + This adds a devfreq driver for MediaTek Cache Coherent
> Interconnect
> + which is shared the same regulators with the cpu cluster. It
> can track
> + buck voltages and update a proper CCI frequency. Use the
> notification
> + to get the regulator status.
> +
> config ARM_RK3399_DMC_DEVFREQ
> tristate "ARM RK3399 DMC DEVFREQ Driver"
> depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> index 0b6be92a25d9..bf40d04928d0 100644
> --- a/drivers/devfreq/Makefile
> +++ b/drivers/devfreq/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=
> governor_passive.o
> obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
> obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
> diff --git a/drivers/devfreq/mtk-cci-devfreq.c b/drivers/devfreq/mtk-
> cci-devfreq.c
> new file mode 100644
> index 000000000000..aa8c37eb4a06
> --- /dev/null
> +++ b/drivers/devfreq/mtk-cci-devfreq.c
> @@ -0,0 +1,474 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/devfreq.h>
> +#include <linux/minmax.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/regulator/consumer.h>
> +
> +struct mtk_ccifreq_platform_data {
> + int min_volt_shift;
> + int max_volt_shift;
> + int proc_max_volt;
> + int sram_min_volt;
> + int sram_max_volt;
> +};
> +
> +struct mtk_ccifreq_drv {
> + struct device *dev;
> + struct devfreq *devfreq;
> + struct regulator *proc_reg;
> + struct regulator *sram_reg;
> + struct clk *cci_clk;
> + struct clk *inter_clk;
> + int inter_voltage;
> + int pre_voltage;
> + unsigned long pre_freq;
> + /* Avoid race condition for regulators between notify and
> policy */
> + struct mutex reg_lock;
> + struct notifier_block opp_nb;
> + const struct mtk_ccifreq_platform_data *soc_data;
> + int vtrack_max;
> +};
> +
> +static int mtk_ccifreq_set_voltage(struct mtk_ccifreq_drv *drv, int
> new_voltage)
> +{
> + const struct mtk_ccifreq_platform_data *soc_data = drv-
> >soc_data;
> + struct device *dev = drv->dev;
> + int pre_voltage, pre_vsram, new_vsram, vsram, voltage, ret;
> + int retry_max = drv->vtrack_max;
> +
> + if (!drv->sram_reg) {
> + ret = regulator_set_voltage(drv->proc_reg, new_voltage,
> + drv->soc_data-
> >proc_max_volt);
> + goto out_set_voltage;
> + }
> +
> + pre_voltage = regulator_get_voltage(drv->proc_reg);
> + if (pre_voltage < 0) {
> + dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
> + return pre_voltage;
> + }
> +
> + pre_vsram = regulator_get_voltage(drv->sram_reg);
> + if (pre_vsram < 0) {
> + dev_err(dev, "invalid vsram value: %d\n", pre_vsram);
> + return pre_vsram;
> + }
> +
> + new_vsram = clamp(new_voltage + soc_data->min_volt_shift,
> + soc_data->sram_min_volt, soc_data-
> >sram_max_volt);
> +
> + do {
> + if (pre_voltage <= new_voltage) {
> + vsram = clamp(pre_voltage + soc_data-
> >max_volt_shift,
> + soc_data->sram_min_volt,
> new_vsram);
> + ret = regulator_set_voltage(drv->sram_reg,
> vsram,
> + soc_data-
> >sram_max_volt);
> + if (ret)
> + return ret;
> +
> + if (vsram == soc_data->sram_max_volt ||
> + new_vsram == soc_data->sram_min_volt)
> + voltage = new_voltage;
> + else
> + voltage = vsram - soc_data-
> >min_volt_shift;
> +
> + ret = regulator_set_voltage(drv->proc_reg,
> voltage,
> + soc_data-
> >proc_max_volt);
> + if (ret) {
> + regulator_set_voltage(drv->sram_reg,
> pre_vsram,
> + soc_data-
> >sram_max_volt);
> + return ret;
> + }
> + } else if (pre_voltage > new_voltage) {
> + voltage = max(new_voltage,
> + pre_vsram - soc_data-
> >max_volt_shift);
> + ret = regulator_set_voltage(drv->proc_reg,
> voltage,
> + soc_data-
> >proc_max_volt);
> + if (ret)
> + return ret;
> +
> + if (voltage == new_voltage)
> + vsram = new_vsram;
> + else
> + vsram = max(new_vsram,
> + voltage + soc_data-
> >min_volt_shift);
> +
> + ret = regulator_set_voltage(drv->sram_reg,
> vsram,
> + soc_data-
> >sram_max_volt);
> + if (ret) {
> + regulator_set_voltage(drv->proc_reg,
> pre_voltage,
> + soc_data-
> >proc_max_volt);
> + return ret;
> + }
> + }
> +
> + pre_voltage = voltage;
> + pre_vsram = vsram;
> +
> + if (--retry_max < 0) {
> + dev_err(dev,
> + "over loop count, failed to set
> voltage\n");
> + return -EINVAL;
> + }
> + } while (voltage != new_voltage || vsram != new_vsram);
> +
> +out_set_voltage:
> + if (!ret)
> + drv->pre_voltage = new_voltage;
> +
> + return ret;
> +}
> +
> +static int mtk_ccifreq_target(struct device *dev, unsigned long
> *freq,
> + u32 flags)
> +{
> + struct mtk_ccifreq_drv *drv = dev_get_drvdata(dev);
> + struct clk *cci_pll = clk_get_parent(drv->cci_clk);
> + struct dev_pm_opp *opp;
> + unsigned long opp_rate;
> + int voltage, pre_voltage, inter_voltage, target_voltage, ret;
> +
> + if (!drv)
> + return -EINVAL;
> +
> + if (drv->pre_freq == *freq)
> + return 0;
> +
> + inter_voltage = drv->inter_voltage;
> +
> + opp_rate = *freq;
> + opp = devfreq_recommended_opp(dev, &opp_rate, 1);
> + if (IS_ERR(opp)) {
> + dev_err(dev, "failed to find opp for freq: %ld\n",
> opp_rate);
> + return PTR_ERR(opp);
> + }
> +
> + mutex_lock(&drv->reg_lock);
> +
> + voltage = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> +
> + if (unlikely(drv->pre_voltage <= 0))
> + pre_voltage = regulator_get_voltage(drv->proc_reg);
> + else
> + pre_voltage = drv->pre_voltage;
> +
> + if (pre_voltage < 0) {
> + dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
> + return pre_voltage;
this should be:
goto out_restore_voltage;
the mutex will not be unlocked.
> + }
> +
> + /* scale up: set voltage first then freq. */
> + target_voltage = max(inter_voltage, voltage);
> + if (pre_voltage <= target_voltage) {
> + ret = mtk_ccifreq_set_voltage(drv, target_voltage);
> + if (ret) {
> + dev_err(dev, "failed to scale up voltage\n");
> + goto out_restore_voltage;
> + }
> + }
> +
> + /* switch the cci clock to intermediate clock source. */
> + ret = clk_set_parent(drv->cci_clk, drv->inter_clk);
> + if (ret) {
> + dev_err(dev, "failed to re-parent cci clock\n");
> + goto out_restore_voltage;
> + }
> +
> + /* set the original clock to target rate. */
> + ret = clk_set_rate(cci_pll, *freq);
> + if (ret) {
> + dev_err(dev, "failed to set cci pll rate: %d\n", ret);
> + clk_set_parent(drv->cci_clk, cci_pll);
> + goto out_restore_voltage;
> + }
> +
> + /* switch the cci clock back to the original clock source. */
> + ret = clk_set_parent(drv->cci_clk, cci_pll);
> + if (ret) {
> + dev_err(dev, "failed to re-parent cci clock\n");
> + mtk_ccifreq_set_voltage(drv, inter_voltage);
> + goto out_unlock;
> + }
> +
> + /*
> + * If the new voltage is lower than the intermediate voltage or
> the
> + * original voltage, scale down to the new voltage.
> + */
> + if (voltage < inter_voltage || voltage < pre_voltage) {
> + ret = mtk_ccifreq_set_voltage(drv, voltage);
> + if (ret) {
> + dev_err(dev, "failed to scale down voltage\n");
> + goto out_unlock;
> + }
> + }
> +
> + drv->pre_freq = *freq;
> + mutex_unlock(&drv->reg_lock);
> +
> + return 0;
> +
> +out_restore_voltage:
> + mtk_ccifreq_set_voltage(drv, pre_voltage);
> +
> +out_unlock:
> + mutex_unlock(&drv->reg_lock);
> + return ret;
> +}
> +
> +static int mtk_ccifreq_opp_notifier(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct dev_pm_opp *opp = data;
> + struct mtk_ccifreq_drv *drv;
> + unsigned long freq, volt;
> +
> + drv = container_of(nb, struct mtk_ccifreq_drv, opp_nb);
> +
> + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + mutex_lock(&drv->reg_lock);
> + /* current opp item is changed */
> + if (freq == drv->pre_freq) {
> + volt = dev_pm_opp_get_voltage(opp);
> + mtk_ccifreq_set_voltage(drv, volt);
> + }
> + mutex_unlock(&drv->reg_lock);
> + }
> +
> + return 0;
> +}
> +
> +static struct devfreq_dev_profile mtk_ccifreq_profile = {
> + .target = mtk_ccifreq_target,
> +};
> +
> +static int mtk_ccifreq_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ccifreq_drv *drv;
> + struct devfreq_passive_data *passive_data;
> + struct dev_pm_opp *opp;
> + unsigned long rate, opp_volt;
> + int ret;
> +
> + drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
> + if (!drv)
> + return -ENOMEM;
> +
> + drv->dev = dev;
> + drv->soc_data = (const struct mtk_ccifreq_platform_data *)
> + of_device_get_match_data(&pdev->dev);
> + mutex_init(&drv->reg_lock);
> + platform_set_drvdata(pdev, drv);
> +
> + drv->cci_clk = devm_clk_get(dev, "cci");
> + if (IS_ERR(drv->cci_clk)) {
> + ret = PTR_ERR(drv->cci_clk);
> + return dev_err_probe(dev, ret,
> + "failed to get cci clk: %d\n",
> ret);
> + }
> +
> + drv->inter_clk = devm_clk_get(dev, "intermediate");
> + if (IS_ERR(drv->inter_clk)) {
> + ret = PTR_ERR(drv->inter_clk);
> + dev_err_probe(dev, ret,
> + "failed to get intermediate clk: %d\n",
> ret);
> + goto out_free_resources;
> + }
> +
> + drv->proc_reg = devm_regulator_get_optional(dev, "proc");
> + if (IS_ERR(drv->proc_reg)) {
> + ret = PTR_ERR(drv->proc_reg);
> + dev_err_probe(dev, ret,
> + "failed to get proc regulator: %d\n",
> ret);
> + goto out_free_resources;
> + }
> +
> + ret = regulator_enable(drv->proc_reg);
> + if (ret) {
> + dev_err(dev, "failed to enable proc regulator\n");
> + goto out_free_resources;
> + }
> +
> + drv->sram_reg = regulator_get_optional(dev, "sram");
> + if (IS_ERR(drv->sram_reg))
> + drv->sram_reg = NULL;
> + else {
> + ret = regulator_enable(drv->sram_reg);
> + if (ret) {
> + dev_err(dev, "failed to enable sram
> regulator\n");
> + goto out_free_resources;
> + }
> + }
> +
> + /*
> + * We assume min voltage is 0 and tracking target voltage using
> + * min_volt_shift for each iteration.
> + * The retry_max is 3 times of expeted iteration count.
> + */
> + drv->vtrack_max = 3 * DIV_ROUND_UP(max(drv->soc_data-
> >sram_max_volt,
> + drv->soc_data-
> >proc_max_volt),
> + drv->soc_data-
> >min_volt_shift);
> +
> + ret = clk_prepare_enable(drv->cci_clk);
> + if (ret)
> + goto out_free_resources;
> +
> + ret = clk_prepare_enable(drv->inter_clk);
> + if (ret)
> + goto out_disable_cci_clk;
> +
> + ret = dev_pm_opp_of_add_table(dev);
> + if (ret) {
> + dev_err(dev, "failed to add opp table: %d\n", ret);
> + goto out_disable_inter_clk;
> + }
> +
> + rate = clk_get_rate(drv->inter_clk);
> + opp = dev_pm_opp_find_freq_ceil(dev, &rate);
> + if (IS_ERR(opp)) {
> + ret = PTR_ERR(opp);
> + dev_err(dev, "failed to get intermediate opp: %d\n",
> ret);
> + goto out_remove_opp_table;
> + }
> + drv->inter_voltage = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> +
> + rate = U32_MAX;
> + opp = dev_pm_opp_find_freq_floor(drv->dev, &rate);
> + if (IS_ERR(opp)) {
> + dev_err(dev, "failed to get opp\n");
> + ret = PTR_ERR(opp);
> + goto out_remove_opp_table;
> + }
> +
> + opp_volt = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> + ret = mtk_ccifreq_set_voltage(drv, opp_volt);
> + if (ret) {
> + dev_err(dev, "failed to scale to highest voltage %lu in
> proc_reg\n",
> + opp_volt);
> + goto out_remove_opp_table;
> + }
> +
> + passive_data = devm_kzalloc(dev, sizeof(struct
> devfreq_passive_data),
> + GFP_KERNEL);
> + if (!passive_data) {
> + ret = -ENOMEM;
> + goto out_remove_opp_table;
> + }
> +
> + passive_data->parent_type = CPUFREQ_PARENT_DEV;
> + drv->devfreq = devm_devfreq_add_device(dev,
> &mtk_ccifreq_profile,
> + DEVFREQ_GOV_PASSIVE,
> + passive_data);
> + if (IS_ERR(drv->devfreq)) {
> + ret = -EPROBE_DEFER;
> + dev_err(dev, "failed to add devfreq device: %ld\n",
> + PTR_ERR(drv->devfreq));
> + goto out_remove_opp_table;
> + }
> +
> + drv->opp_nb.notifier_call = mtk_ccifreq_opp_notifier;
> + ret = dev_pm_opp_register_notifier(dev, &drv->opp_nb);
> + if (ret) {
> + dev_err(dev, "failed to register opp notifier: %d\n",
> ret);
> + goto out_remove_devfreq_device;
> + }
> + return 0;
> +
> +out_remove_devfreq_device:
> + devm_devfreq_remove_device(dev, drv->devfreq);
> +
> +out_remove_opp_table:
> + dev_pm_opp_of_remove_table(dev);
> +
> +out_disable_inter_clk:
> + clk_disable_unprepare(drv->inter_clk);
> +
> +out_disable_cci_clk:
> + clk_disable_unprepare(drv->cci_clk);
> +
> +out_free_resources:
> + if (regulator_is_enabled(drv->proc_reg))
> + regulator_disable(drv->proc_reg);
> + if (drv->sram_reg && regulator_is_enabled(drv->sram_reg))
> + regulator_disable(drv->sram_reg);
> +
> + if (!IS_ERR(drv->proc_reg))
> + regulator_put(drv->proc_reg);
> + if (!IS_ERR(drv->sram_reg))
> + regulator_put(drv->sram_reg);
> + if (!IS_ERR(drv->cci_clk))
> + clk_put(drv->cci_clk);
> + if (!IS_ERR(drv->inter_clk))
> + clk_put(drv->inter_clk);
> +
> + return ret;
> +}
> +
> +static int mtk_ccifreq_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ccifreq_drv *drv;
> +
> + drv = platform_get_drvdata(pdev);
> +
> + dev_pm_opp_unregister_notifier(dev, &drv->opp_nb);
> + dev_pm_opp_of_remove_table(dev);
> + clk_disable_unprepare(drv->inter_clk);
> + clk_disable_unprepare(drv->cci_clk);
> + regulator_disable(drv->proc_reg);
> + if (drv->sram_reg)
> + regulator_disable(drv->sram_reg);
> +
> + return 0;
> +}
> +
> +static const struct mtk_ccifreq_platform_data mt8183_platform_data =
> {
> + .min_volt_shift = 100000,
> + .max_volt_shift = 200000,
> + .proc_max_volt = 1150000,
> + .sram_min_volt = 0,
> + .sram_max_volt = 1150000,
> +};
> +
> +static const struct mtk_ccifreq_platform_data mt8186_platform_data =
> {
> + .min_volt_shift = 100000,
> + .max_volt_shift = 250000,
> + .proc_max_volt = 1118750,
> + .sram_min_volt = 850000,
> + .sram_max_volt = 1118750,
> +};
> +
> +static const struct of_device_id mtk_ccifreq_machines[] = {
> + { .compatible = "mediatek,mt8183-cci", .data =
> &mt8183_platform_data },
> + { .compatible = "mediatek,mt8186-cci", .data =
> &mt8186_platform_data },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_ccifreq_machines);
> +
> +static struct platform_driver mtk_ccifreq_platdrv = {
> + .probe = mtk_ccifreq_probe,
> + .remove = mtk_ccifreq_remove,
> + .driver = {
> + .name = "mtk-ccifreq",
> + .of_match_table = mtk_ccifreq_machines,
> + },
> +};
> +module_platform_driver(mtk_ccifreq_platdrv);
> +
> +MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
> +MODULE_AUTHOR("Jia-Wei Chang <jia-wei.chang@mediatek.com>");
> +MODULE_LICENSE("GPL v2");
_______________________________________________
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
@ 2022-05-13 4:39 ` Rex-BC Chen
0 siblings, 0 replies; 30+ messages in thread
From: Rex-BC Chen @ 2022-05-13 4:39 UTC (permalink / raw)
To: Johnson Wang, cw00.choi, krzk+dt, robh+dt, kyungmin.park
Cc: djakov, khilman, linux-pm, linux-kernel, devicetree,
linux-arm-kernel, linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Fri, 2022-05-13 at 11:28 +0800, Johnson Wang wrote:
> We introduce a devfreq driver for the MediaTek Cache Coherent
> Interconnect
> (CCI) used by some MediaTek SoCs.
>
> In this driver, we use the passive devfreq driver to get target
> frequencies
> and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek
> CCI
> is supplied by the same regulators with the little core CPUs.
>
> Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> ---
> This patch depends on "devfreq-testing"[1].
> [1]
> https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing
> ---
> drivers/devfreq/Kconfig | 10 +
> drivers/devfreq/Makefile | 1 +
> drivers/devfreq/mtk-cci-devfreq.c | 474
> ++++++++++++++++++++++++++++++
> 3 files changed, 485 insertions(+)
> create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
>
> diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> index 87eb2b837e68..9754d8b31621 100644
> --- a/drivers/devfreq/Kconfig
> +++ b/drivers/devfreq/Kconfig
> @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> It reads ACTMON counters of memory controllers and adjusts
> the
> operating frequencies and voltages with OPP support.
>
> +config ARM_MEDIATEK_CCI_DEVFREQ
> + tristate "MEDIATEK CCI DEVFREQ Driver"
> + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> + select DEVFREQ_GOV_PASSIVE
> + help
> + This adds a devfreq driver for MediaTek Cache Coherent
> Interconnect
> + which is shared the same regulators with the cpu cluster. It
> can track
> + buck voltages and update a proper CCI frequency. Use the
> notification
> + to get the regulator status.
> +
> config ARM_RK3399_DMC_DEVFREQ
> tristate "ARM RK3399 DMC DEVFREQ Driver"
> depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> index 0b6be92a25d9..bf40d04928d0 100644
> --- a/drivers/devfreq/Makefile
> +++ b/drivers/devfreq/Makefile
> @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=
> governor_passive.o
> obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
> obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-devfreq.o
> diff --git a/drivers/devfreq/mtk-cci-devfreq.c b/drivers/devfreq/mtk-
> cci-devfreq.c
> new file mode 100644
> index 000000000000..aa8c37eb4a06
> --- /dev/null
> +++ b/drivers/devfreq/mtk-cci-devfreq.c
> @@ -0,0 +1,474 @@
> +// SPDX-License-Identifier: GPL-2.0-only
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +
> +#include <linux/clk.h>
> +#include <linux/devfreq.h>
> +#include <linux/minmax.h>
> +#include <linux/module.h>
> +#include <linux/of.h>
> +#include <linux/of_device.h>
> +#include <linux/platform_device.h>
> +#include <linux/pm_opp.h>
> +#include <linux/regulator/consumer.h>
> +
> +struct mtk_ccifreq_platform_data {
> + int min_volt_shift;
> + int max_volt_shift;
> + int proc_max_volt;
> + int sram_min_volt;
> + int sram_max_volt;
> +};
> +
> +struct mtk_ccifreq_drv {
> + struct device *dev;
> + struct devfreq *devfreq;
> + struct regulator *proc_reg;
> + struct regulator *sram_reg;
> + struct clk *cci_clk;
> + struct clk *inter_clk;
> + int inter_voltage;
> + int pre_voltage;
> + unsigned long pre_freq;
> + /* Avoid race condition for regulators between notify and
> policy */
> + struct mutex reg_lock;
> + struct notifier_block opp_nb;
> + const struct mtk_ccifreq_platform_data *soc_data;
> + int vtrack_max;
> +};
> +
> +static int mtk_ccifreq_set_voltage(struct mtk_ccifreq_drv *drv, int
> new_voltage)
> +{
> + const struct mtk_ccifreq_platform_data *soc_data = drv-
> >soc_data;
> + struct device *dev = drv->dev;
> + int pre_voltage, pre_vsram, new_vsram, vsram, voltage, ret;
> + int retry_max = drv->vtrack_max;
> +
> + if (!drv->sram_reg) {
> + ret = regulator_set_voltage(drv->proc_reg, new_voltage,
> + drv->soc_data-
> >proc_max_volt);
> + goto out_set_voltage;
> + }
> +
> + pre_voltage = regulator_get_voltage(drv->proc_reg);
> + if (pre_voltage < 0) {
> + dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
> + return pre_voltage;
> + }
> +
> + pre_vsram = regulator_get_voltage(drv->sram_reg);
> + if (pre_vsram < 0) {
> + dev_err(dev, "invalid vsram value: %d\n", pre_vsram);
> + return pre_vsram;
> + }
> +
> + new_vsram = clamp(new_voltage + soc_data->min_volt_shift,
> + soc_data->sram_min_volt, soc_data-
> >sram_max_volt);
> +
> + do {
> + if (pre_voltage <= new_voltage) {
> + vsram = clamp(pre_voltage + soc_data-
> >max_volt_shift,
> + soc_data->sram_min_volt,
> new_vsram);
> + ret = regulator_set_voltage(drv->sram_reg,
> vsram,
> + soc_data-
> >sram_max_volt);
> + if (ret)
> + return ret;
> +
> + if (vsram == soc_data->sram_max_volt ||
> + new_vsram == soc_data->sram_min_volt)
> + voltage = new_voltage;
> + else
> + voltage = vsram - soc_data-
> >min_volt_shift;
> +
> + ret = regulator_set_voltage(drv->proc_reg,
> voltage,
> + soc_data-
> >proc_max_volt);
> + if (ret) {
> + regulator_set_voltage(drv->sram_reg,
> pre_vsram,
> + soc_data-
> >sram_max_volt);
> + return ret;
> + }
> + } else if (pre_voltage > new_voltage) {
> + voltage = max(new_voltage,
> + pre_vsram - soc_data-
> >max_volt_shift);
> + ret = regulator_set_voltage(drv->proc_reg,
> voltage,
> + soc_data-
> >proc_max_volt);
> + if (ret)
> + return ret;
> +
> + if (voltage == new_voltage)
> + vsram = new_vsram;
> + else
> + vsram = max(new_vsram,
> + voltage + soc_data-
> >min_volt_shift);
> +
> + ret = regulator_set_voltage(drv->sram_reg,
> vsram,
> + soc_data-
> >sram_max_volt);
> + if (ret) {
> + regulator_set_voltage(drv->proc_reg,
> pre_voltage,
> + soc_data-
> >proc_max_volt);
> + return ret;
> + }
> + }
> +
> + pre_voltage = voltage;
> + pre_vsram = vsram;
> +
> + if (--retry_max < 0) {
> + dev_err(dev,
> + "over loop count, failed to set
> voltage\n");
> + return -EINVAL;
> + }
> + } while (voltage != new_voltage || vsram != new_vsram);
> +
> +out_set_voltage:
> + if (!ret)
> + drv->pre_voltage = new_voltage;
> +
> + return ret;
> +}
> +
> +static int mtk_ccifreq_target(struct device *dev, unsigned long
> *freq,
> + u32 flags)
> +{
> + struct mtk_ccifreq_drv *drv = dev_get_drvdata(dev);
> + struct clk *cci_pll = clk_get_parent(drv->cci_clk);
> + struct dev_pm_opp *opp;
> + unsigned long opp_rate;
> + int voltage, pre_voltage, inter_voltage, target_voltage, ret;
> +
> + if (!drv)
> + return -EINVAL;
> +
> + if (drv->pre_freq == *freq)
> + return 0;
> +
> + inter_voltage = drv->inter_voltage;
> +
> + opp_rate = *freq;
> + opp = devfreq_recommended_opp(dev, &opp_rate, 1);
> + if (IS_ERR(opp)) {
> + dev_err(dev, "failed to find opp for freq: %ld\n",
> opp_rate);
> + return PTR_ERR(opp);
> + }
> +
> + mutex_lock(&drv->reg_lock);
> +
> + voltage = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> +
> + if (unlikely(drv->pre_voltage <= 0))
> + pre_voltage = regulator_get_voltage(drv->proc_reg);
> + else
> + pre_voltage = drv->pre_voltage;
> +
> + if (pre_voltage < 0) {
> + dev_err(dev, "invalid vproc value: %d\n", pre_voltage);
> + return pre_voltage;
this should be:
goto out_restore_voltage;
the mutex will not be unlocked.
> + }
> +
> + /* scale up: set voltage first then freq. */
> + target_voltage = max(inter_voltage, voltage);
> + if (pre_voltage <= target_voltage) {
> + ret = mtk_ccifreq_set_voltage(drv, target_voltage);
> + if (ret) {
> + dev_err(dev, "failed to scale up voltage\n");
> + goto out_restore_voltage;
> + }
> + }
> +
> + /* switch the cci clock to intermediate clock source. */
> + ret = clk_set_parent(drv->cci_clk, drv->inter_clk);
> + if (ret) {
> + dev_err(dev, "failed to re-parent cci clock\n");
> + goto out_restore_voltage;
> + }
> +
> + /* set the original clock to target rate. */
> + ret = clk_set_rate(cci_pll, *freq);
> + if (ret) {
> + dev_err(dev, "failed to set cci pll rate: %d\n", ret);
> + clk_set_parent(drv->cci_clk, cci_pll);
> + goto out_restore_voltage;
> + }
> +
> + /* switch the cci clock back to the original clock source. */
> + ret = clk_set_parent(drv->cci_clk, cci_pll);
> + if (ret) {
> + dev_err(dev, "failed to re-parent cci clock\n");
> + mtk_ccifreq_set_voltage(drv, inter_voltage);
> + goto out_unlock;
> + }
> +
> + /*
> + * If the new voltage is lower than the intermediate voltage or
> the
> + * original voltage, scale down to the new voltage.
> + */
> + if (voltage < inter_voltage || voltage < pre_voltage) {
> + ret = mtk_ccifreq_set_voltage(drv, voltage);
> + if (ret) {
> + dev_err(dev, "failed to scale down voltage\n");
> + goto out_unlock;
> + }
> + }
> +
> + drv->pre_freq = *freq;
> + mutex_unlock(&drv->reg_lock);
> +
> + return 0;
> +
> +out_restore_voltage:
> + mtk_ccifreq_set_voltage(drv, pre_voltage);
> +
> +out_unlock:
> + mutex_unlock(&drv->reg_lock);
> + return ret;
> +}
> +
> +static int mtk_ccifreq_opp_notifier(struct notifier_block *nb,
> + unsigned long event, void *data)
> +{
> + struct dev_pm_opp *opp = data;
> + struct mtk_ccifreq_drv *drv;
> + unsigned long freq, volt;
> +
> + drv = container_of(nb, struct mtk_ccifreq_drv, opp_nb);
> +
> + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> + freq = dev_pm_opp_get_freq(opp);
> +
> + mutex_lock(&drv->reg_lock);
> + /* current opp item is changed */
> + if (freq == drv->pre_freq) {
> + volt = dev_pm_opp_get_voltage(opp);
> + mtk_ccifreq_set_voltage(drv, volt);
> + }
> + mutex_unlock(&drv->reg_lock);
> + }
> +
> + return 0;
> +}
> +
> +static struct devfreq_dev_profile mtk_ccifreq_profile = {
> + .target = mtk_ccifreq_target,
> +};
> +
> +static int mtk_ccifreq_probe(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ccifreq_drv *drv;
> + struct devfreq_passive_data *passive_data;
> + struct dev_pm_opp *opp;
> + unsigned long rate, opp_volt;
> + int ret;
> +
> + drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
> + if (!drv)
> + return -ENOMEM;
> +
> + drv->dev = dev;
> + drv->soc_data = (const struct mtk_ccifreq_platform_data *)
> + of_device_get_match_data(&pdev->dev);
> + mutex_init(&drv->reg_lock);
> + platform_set_drvdata(pdev, drv);
> +
> + drv->cci_clk = devm_clk_get(dev, "cci");
> + if (IS_ERR(drv->cci_clk)) {
> + ret = PTR_ERR(drv->cci_clk);
> + return dev_err_probe(dev, ret,
> + "failed to get cci clk: %d\n",
> ret);
> + }
> +
> + drv->inter_clk = devm_clk_get(dev, "intermediate");
> + if (IS_ERR(drv->inter_clk)) {
> + ret = PTR_ERR(drv->inter_clk);
> + dev_err_probe(dev, ret,
> + "failed to get intermediate clk: %d\n",
> ret);
> + goto out_free_resources;
> + }
> +
> + drv->proc_reg = devm_regulator_get_optional(dev, "proc");
> + if (IS_ERR(drv->proc_reg)) {
> + ret = PTR_ERR(drv->proc_reg);
> + dev_err_probe(dev, ret,
> + "failed to get proc regulator: %d\n",
> ret);
> + goto out_free_resources;
> + }
> +
> + ret = regulator_enable(drv->proc_reg);
> + if (ret) {
> + dev_err(dev, "failed to enable proc regulator\n");
> + goto out_free_resources;
> + }
> +
> + drv->sram_reg = regulator_get_optional(dev, "sram");
> + if (IS_ERR(drv->sram_reg))
> + drv->sram_reg = NULL;
> + else {
> + ret = regulator_enable(drv->sram_reg);
> + if (ret) {
> + dev_err(dev, "failed to enable sram
> regulator\n");
> + goto out_free_resources;
> + }
> + }
> +
> + /*
> + * We assume min voltage is 0 and tracking target voltage using
> + * min_volt_shift for each iteration.
> + * The retry_max is 3 times of expeted iteration count.
> + */
> + drv->vtrack_max = 3 * DIV_ROUND_UP(max(drv->soc_data-
> >sram_max_volt,
> + drv->soc_data-
> >proc_max_volt),
> + drv->soc_data-
> >min_volt_shift);
> +
> + ret = clk_prepare_enable(drv->cci_clk);
> + if (ret)
> + goto out_free_resources;
> +
> + ret = clk_prepare_enable(drv->inter_clk);
> + if (ret)
> + goto out_disable_cci_clk;
> +
> + ret = dev_pm_opp_of_add_table(dev);
> + if (ret) {
> + dev_err(dev, "failed to add opp table: %d\n", ret);
> + goto out_disable_inter_clk;
> + }
> +
> + rate = clk_get_rate(drv->inter_clk);
> + opp = dev_pm_opp_find_freq_ceil(dev, &rate);
> + if (IS_ERR(opp)) {
> + ret = PTR_ERR(opp);
> + dev_err(dev, "failed to get intermediate opp: %d\n",
> ret);
> + goto out_remove_opp_table;
> + }
> + drv->inter_voltage = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> +
> + rate = U32_MAX;
> + opp = dev_pm_opp_find_freq_floor(drv->dev, &rate);
> + if (IS_ERR(opp)) {
> + dev_err(dev, "failed to get opp\n");
> + ret = PTR_ERR(opp);
> + goto out_remove_opp_table;
> + }
> +
> + opp_volt = dev_pm_opp_get_voltage(opp);
> + dev_pm_opp_put(opp);
> + ret = mtk_ccifreq_set_voltage(drv, opp_volt);
> + if (ret) {
> + dev_err(dev, "failed to scale to highest voltage %lu in
> proc_reg\n",
> + opp_volt);
> + goto out_remove_opp_table;
> + }
> +
> + passive_data = devm_kzalloc(dev, sizeof(struct
> devfreq_passive_data),
> + GFP_KERNEL);
> + if (!passive_data) {
> + ret = -ENOMEM;
> + goto out_remove_opp_table;
> + }
> +
> + passive_data->parent_type = CPUFREQ_PARENT_DEV;
> + drv->devfreq = devm_devfreq_add_device(dev,
> &mtk_ccifreq_profile,
> + DEVFREQ_GOV_PASSIVE,
> + passive_data);
> + if (IS_ERR(drv->devfreq)) {
> + ret = -EPROBE_DEFER;
> + dev_err(dev, "failed to add devfreq device: %ld\n",
> + PTR_ERR(drv->devfreq));
> + goto out_remove_opp_table;
> + }
> +
> + drv->opp_nb.notifier_call = mtk_ccifreq_opp_notifier;
> + ret = dev_pm_opp_register_notifier(dev, &drv->opp_nb);
> + if (ret) {
> + dev_err(dev, "failed to register opp notifier: %d\n",
> ret);
> + goto out_remove_devfreq_device;
> + }
> + return 0;
> +
> +out_remove_devfreq_device:
> + devm_devfreq_remove_device(dev, drv->devfreq);
> +
> +out_remove_opp_table:
> + dev_pm_opp_of_remove_table(dev);
> +
> +out_disable_inter_clk:
> + clk_disable_unprepare(drv->inter_clk);
> +
> +out_disable_cci_clk:
> + clk_disable_unprepare(drv->cci_clk);
> +
> +out_free_resources:
> + if (regulator_is_enabled(drv->proc_reg))
> + regulator_disable(drv->proc_reg);
> + if (drv->sram_reg && regulator_is_enabled(drv->sram_reg))
> + regulator_disable(drv->sram_reg);
> +
> + if (!IS_ERR(drv->proc_reg))
> + regulator_put(drv->proc_reg);
> + if (!IS_ERR(drv->sram_reg))
> + regulator_put(drv->sram_reg);
> + if (!IS_ERR(drv->cci_clk))
> + clk_put(drv->cci_clk);
> + if (!IS_ERR(drv->inter_clk))
> + clk_put(drv->inter_clk);
> +
> + return ret;
> +}
> +
> +static int mtk_ccifreq_remove(struct platform_device *pdev)
> +{
> + struct device *dev = &pdev->dev;
> + struct mtk_ccifreq_drv *drv;
> +
> + drv = platform_get_drvdata(pdev);
> +
> + dev_pm_opp_unregister_notifier(dev, &drv->opp_nb);
> + dev_pm_opp_of_remove_table(dev);
> + clk_disable_unprepare(drv->inter_clk);
> + clk_disable_unprepare(drv->cci_clk);
> + regulator_disable(drv->proc_reg);
> + if (drv->sram_reg)
> + regulator_disable(drv->sram_reg);
> +
> + return 0;
> +}
> +
> +static const struct mtk_ccifreq_platform_data mt8183_platform_data =
> {
> + .min_volt_shift = 100000,
> + .max_volt_shift = 200000,
> + .proc_max_volt = 1150000,
> + .sram_min_volt = 0,
> + .sram_max_volt = 1150000,
> +};
> +
> +static const struct mtk_ccifreq_platform_data mt8186_platform_data =
> {
> + .min_volt_shift = 100000,
> + .max_volt_shift = 250000,
> + .proc_max_volt = 1118750,
> + .sram_min_volt = 850000,
> + .sram_max_volt = 1118750,
> +};
> +
> +static const struct of_device_id mtk_ccifreq_machines[] = {
> + { .compatible = "mediatek,mt8183-cci", .data =
> &mt8183_platform_data },
> + { .compatible = "mediatek,mt8186-cci", .data =
> &mt8186_platform_data },
> + { },
> +};
> +MODULE_DEVICE_TABLE(of, mtk_ccifreq_machines);
> +
> +static struct platform_driver mtk_ccifreq_platdrv = {
> + .probe = mtk_ccifreq_probe,
> + .remove = mtk_ccifreq_remove,
> + .driver = {
> + .name = "mtk-ccifreq",
> + .of_match_table = mtk_ccifreq_machines,
> + },
> +};
> +module_platform_driver(mtk_ccifreq_platdrv);
> +
> +MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
> +MODULE_AUTHOR("Jia-Wei Chang <jia-wei.chang@mediatek.com>");
> +MODULE_LICENSE("GPL v2");
_______________________________________________
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
2022-05-13 3:54 ` Chen-Yu Tsai
(?)
@ 2022-05-18 12:19 ` Johnson Wang
-1 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-18 12:19 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
Hi Chen-Yu,
On Fri, 2022-05-13 at 11:54 +0800, Chen-Yu Tsai wrote:
> On Fri, May 13, 2022 at 11:31 AM Johnson Wang <
> johnson.wang@mediatek.com> wrote:
> >
> > We introduce a devfreq driver for the MediaTek Cache Coherent
> > Interconnect
> > (CCI) used by some MediaTek SoCs.
> >
> > In this driver, we use the passive devfreq driver to get target
> > frequencies
> > and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek
> > CCI
> > is supplied by the same regulators with the little core CPUs.
> >
> > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> > ---
> > This patch depends on "devfreq-testing"[1].
> > [1]
> > https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing__;!!CTRNKA9wMg0ARbw!zzOSoso9udvDV3h6kYlmizFtbn3ACA5aS2jCAjKyvtu4z0fobv1mD5uF9YbPSme8l_NnR05unTxkZfDdzohu8asWZQ$
> >
> > ---
> > drivers/devfreq/Kconfig | 10 +
> > drivers/devfreq/Makefile | 1 +
> > drivers/devfreq/mtk-cci-devfreq.c | 474
> > ++++++++++++++++++++++++++++++
> > 3 files changed, 485 insertions(+)
> > create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
> >
> > diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> > index 87eb2b837e68..9754d8b31621 100644
> > --- a/drivers/devfreq/Kconfig
> > +++ b/drivers/devfreq/Kconfig
> > @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> > It reads ACTMON counters of memory controllers and
> > adjusts the
> > operating frequencies and voltages with OPP support.
> >
> > +config ARM_MEDIATEK_CCI_DEVFREQ
> > + tristate "MEDIATEK CCI DEVFREQ Driver"
> > + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> > + select DEVFREQ_GOV_PASSIVE
> > + help
> > + This adds a devfreq driver for MediaTek Cache Coherent
> > Interconnect
> > + which is shared the same regulators with the cpu cluster.
> > It can track
> > + buck voltages and update a proper CCI frequency. Use the
> > notification
> > + to get the regulator status.
> > +
> > config ARM_RK3399_DMC_DEVFREQ
> > tristate "ARM RK3399 DMC DEVFREQ Driver"
> > depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> > diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> > index 0b6be92a25d9..bf40d04928d0 100644
> > --- a/drivers/devfreq/Makefile
> > +++ b/drivers/devfreq/Makefile
> > @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=
> > governor_passive.o
> > obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> > obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> > obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> > +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> > obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> > obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
> > obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-
> > devfreq.o
> > diff --git a/drivers/devfreq/mtk-cci-devfreq.c
> > b/drivers/devfreq/mtk-cci-devfreq.c
> > new file mode 100644
> > index 000000000000..aa8c37eb4a06
> > --- /dev/null
> > +++ b/drivers/devfreq/mtk-cci-devfreq.c
> > @@ -0,0 +1,474 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (C) 2022 MediaTek Inc.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/devfreq.h>
> > +#include <linux/minmax.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_opp.h>
> > +#include <linux/regulator/consumer.h>
> > +
> > +struct mtk_ccifreq_platform_data {
> > + int min_volt_shift;
> > + int max_volt_shift;
> > + int proc_max_volt;
> > + int sram_min_volt;
> > + int sram_max_volt;
> > +};
> > +
> > +struct mtk_ccifreq_drv {
> > + struct device *dev;
> > + struct devfreq *devfreq;
> > + struct regulator *proc_reg;
> > + struct regulator *sram_reg;
> > + struct clk *cci_clk;
> > + struct clk *inter_clk;
> > + int inter_voltage;
> > + int pre_voltage;
> > + unsigned long pre_freq;
> > + /* Avoid race condition for regulators between notify and
> > policy */
> > + struct mutex reg_lock;
> > + struct notifier_block opp_nb;
> > + const struct mtk_ccifreq_platform_data *soc_data;
> > + int vtrack_max;
> > +};
> > +
> > +static int mtk_ccifreq_set_voltage(struct mtk_ccifreq_drv *drv,
> > int new_voltage)
> > +{
> > + const struct mtk_ccifreq_platform_data *soc_data = drv-
> > >soc_data;
> > + struct device *dev = drv->dev;
> > + int pre_voltage, pre_vsram, new_vsram, vsram, voltage, ret;
> > + int retry_max = drv->vtrack_max;
> > +
> > + if (!drv->sram_reg) {
> > + ret = regulator_set_voltage(drv->proc_reg,
> > new_voltage,
> > + drv->soc_data-
> > >proc_max_volt);
> > + goto out_set_voltage;
> > + }
> > +
> > + pre_voltage = regulator_get_voltage(drv->proc_reg);
> > + if (pre_voltage < 0) {
> > + dev_err(dev, "invalid vproc value: %d\n",
> > pre_voltage);
> > + return pre_voltage;
> > + }
> > +
> > + pre_vsram = regulator_get_voltage(drv->sram_reg);
> > + if (pre_vsram < 0) {
> > + dev_err(dev, "invalid vsram value: %d\n",
> > pre_vsram);
> > + return pre_vsram;
> > + }
> > +
> > + new_vsram = clamp(new_voltage + soc_data->min_volt_shift,
> > + soc_data->sram_min_volt, soc_data-
> > >sram_max_volt);
> > +
> > + do {
> > + if (pre_voltage <= new_voltage) {
> > + vsram = clamp(pre_voltage + soc_data-
> > >max_volt_shift,
> > + soc_data->sram_min_volt,
> > new_vsram);
> > + ret = regulator_set_voltage(drv->sram_reg,
> > vsram,
> > + soc_data-
> > >sram_max_volt);
> > + if (ret)
> > + return ret;
> > +
> > + if (vsram == soc_data->sram_max_volt ||
> > + new_vsram == soc_data->sram_min_volt)
> > + voltage = new_voltage;
> > + else
> > + voltage = vsram - soc_data-
> > >min_volt_shift;
> > +
> > + ret = regulator_set_voltage(drv->proc_reg,
> > voltage,
> > + soc_data-
> > >proc_max_volt);
> > + if (ret) {
> > + regulator_set_voltage(drv-
> > >sram_reg, pre_vsram,
> > + soc_data-
> > >sram_max_volt);
> > + return ret;
> > + }
> > + } else if (pre_voltage > new_voltage) {
> > + voltage = max(new_voltage,
> > + pre_vsram - soc_data-
> > >max_volt_shift);
> > + ret = regulator_set_voltage(drv->proc_reg,
> > voltage,
> > + soc_data-
> > >proc_max_volt);
> > + if (ret)
> > + return ret;
> > +
> > + if (voltage == new_voltage)
> > + vsram = new_vsram;
> > + else
> > + vsram = max(new_vsram,
> > + voltage + soc_data-
> > >min_volt_shift);
> > +
> > + ret = regulator_set_voltage(drv->sram_reg,
> > vsram,
> > + soc_data-
> > >sram_max_volt);
> > + if (ret) {
> > + regulator_set_voltage(drv-
> > >proc_reg, pre_voltage,
> > + soc_data-
> > >proc_max_volt);
> > + return ret;
> > + }
> > + }
> > +
> > + pre_voltage = voltage;
> > + pre_vsram = vsram;
> > +
> > + if (--retry_max < 0) {
> > + dev_err(dev,
> > + "over loop count, failed to set
> > voltage\n");
> > + return -EINVAL;
> > + }
> > + } while (voltage != new_voltage || vsram != new_vsram);
> > +
> > +out_set_voltage:
> > + if (!ret)
> > + drv->pre_voltage = new_voltage;
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_ccifreq_target(struct device *dev, unsigned long
> > *freq,
> > + u32 flags)
> > +{
> > + struct mtk_ccifreq_drv *drv = dev_get_drvdata(dev);
> > + struct clk *cci_pll = clk_get_parent(drv->cci_clk);
> > + struct dev_pm_opp *opp;
> > + unsigned long opp_rate;
> > + int voltage, pre_voltage, inter_voltage, target_voltage,
> > ret;
> > +
> > + if (!drv)
> > + return -EINVAL;
> > +
> > + if (drv->pre_freq == *freq)
> > + return 0;
> > +
> > + inter_voltage = drv->inter_voltage;
> > +
> > + opp_rate = *freq;
> > + opp = devfreq_recommended_opp(dev, &opp_rate, 1);
> > + if (IS_ERR(opp)) {
> > + dev_err(dev, "failed to find opp for freq: %ld\n",
> > opp_rate);
> > + return PTR_ERR(opp);
> > + }
> > +
> > + mutex_lock(&drv->reg_lock);
> > +
> > + voltage = dev_pm_opp_get_voltage(opp);
> > + dev_pm_opp_put(opp);
> > +
> > + if (unlikely(drv->pre_voltage <= 0))
> > + pre_voltage = regulator_get_voltage(drv->proc_reg);
> > + else
> > + pre_voltage = drv->pre_voltage;
>
> Could you explain why the previous voltage setting is cached like
> this?
>
> The CCI is sharing the regulator supply with one of the CPU clusters,
> and cpufreq could also change the voltage, so it's better to always
> retrieve the current setting directly from the regulator core. And
> those values might be cached iun the core, so it's unlikely to incur
> a significant cost.
Thanks for your suggestion.
I will modify it as mtk_ccifreq_set_voltage() does.
In that way I will try to remove pre_voltage member because it's no
longer needed.
> > +
> > + if (pre_voltage < 0) {
> > + dev_err(dev, "invalid vproc value: %d\n",
> > pre_voltage);
> > + return pre_voltage;
> > + }
> > +
> > + /* scale up: set voltage first then freq. */
> > + target_voltage = max(inter_voltage, voltage);
> > + if (pre_voltage <= target_voltage) {
> > + ret = mtk_ccifreq_set_voltage(drv, target_voltage);
> > + if (ret) {
> > + dev_err(dev, "failed to scale up
> > voltage\n");
> > + goto out_restore_voltage;
> > + }
> > + }
> > +
> > + /* switch the cci clock to intermediate clock source. */
> > + ret = clk_set_parent(drv->cci_clk, drv->inter_clk);
> > + if (ret) {
> > + dev_err(dev, "failed to re-parent cci clock\n");
> > + goto out_restore_voltage;
> > + }
> > +
> > + /* set the original clock to target rate. */
> > + ret = clk_set_rate(cci_pll, *freq);
> > + if (ret) {
> > + dev_err(dev, "failed to set cci pll rate: %d\n",
> > ret);
> > + clk_set_parent(drv->cci_clk, cci_pll);
> > + goto out_restore_voltage;
> > + }
> > +
> > + /* switch the cci clock back to the original clock source.
> > */
> > + ret = clk_set_parent(drv->cci_clk, cci_pll);
> > + if (ret) {
> > + dev_err(dev, "failed to re-parent cci clock\n");
> > + mtk_ccifreq_set_voltage(drv, inter_voltage);
> > + goto out_unlock;
> > + }
> > +
> > + /*
> > + * If the new voltage is lower than the intermediate
> > voltage or the
> > + * original voltage, scale down to the new voltage.
> > + */
> > + if (voltage < inter_voltage || voltage < pre_voltage) {
> > + ret = mtk_ccifreq_set_voltage(drv, voltage);
> > + if (ret) {
> > + dev_err(dev, "failed to scale down
> > voltage\n");
> > + goto out_unlock;
> > + }
> > + }
> > +
> > + drv->pre_freq = *freq;
> > + mutex_unlock(&drv->reg_lock);
> > +
> > + return 0;
> > +
> > +out_restore_voltage:
> > + mtk_ccifreq_set_voltage(drv, pre_voltage);
> > +
> > +out_unlock:
> > + mutex_unlock(&drv->reg_lock);
> > + return ret;
> > +}
> > +
> > +static int mtk_ccifreq_opp_notifier(struct notifier_block *nb,
> > + unsigned long event, void
> > *data)
> > +{
> > + struct dev_pm_opp *opp = data;
> > + struct mtk_ccifreq_drv *drv;
> > + unsigned long freq, volt;
> > +
> > + drv = container_of(nb, struct mtk_ccifreq_drv, opp_nb);
> > +
> > + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + mutex_lock(&drv->reg_lock);
> > + /* current opp item is changed */
> > + if (freq == drv->pre_freq) {
> > + volt = dev_pm_opp_get_voltage(opp);
> > + mtk_ccifreq_set_voltage(drv, volt);
> > + }
> > + mutex_unlock(&drv->reg_lock);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static struct devfreq_dev_profile mtk_ccifreq_profile = {
> > + .target = mtk_ccifreq_target,
> > +};
> > +
> > +static int mtk_ccifreq_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct mtk_ccifreq_drv *drv;
> > + struct devfreq_passive_data *passive_data;
> > + struct dev_pm_opp *opp;
> > + unsigned long rate, opp_volt;
> > + int ret;
> > +
> > + drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
> > + if (!drv)
> > + return -ENOMEM;
> > +
> > + drv->dev = dev;
> > + drv->soc_data = (const struct mtk_ccifreq_platform_data *)
> > + of_device_get_match_data(&pdev-
> > >dev);
> > + mutex_init(&drv->reg_lock);
> > + platform_set_drvdata(pdev, drv);
> > +
> > + drv->cci_clk = devm_clk_get(dev, "cci");
> > + if (IS_ERR(drv->cci_clk)) {
> > + ret = PTR_ERR(drv->cci_clk);
> > + return dev_err_probe(dev, ret,
> > + "failed to get cci clk: %d\n",
> > ret);
> > + }
> > +
> > + drv->inter_clk = devm_clk_get(dev, "intermediate");
> > + if (IS_ERR(drv->inter_clk)) {
> > + ret = PTR_ERR(drv->inter_clk);
> > + dev_err_probe(dev, ret,
> > + "failed to get intermediate clk:
> > %d\n", ret);
> > + goto out_free_resources;
> > + }
> > +
> > + drv->proc_reg = devm_regulator_get_optional(dev, "proc");
> > + if (IS_ERR(drv->proc_reg)) {
> > + ret = PTR_ERR(drv->proc_reg);
> > + dev_err_probe(dev, ret,
> > + "failed to get proc regulator: %d\n",
> > ret);
> > + goto out_free_resources;
> > + }
> > +
> > + ret = regulator_enable(drv->proc_reg);
> > + if (ret) {
> > + dev_err(dev, "failed to enable proc regulator\n");
> > + goto out_free_resources;
> > + }
> > +
> > + drv->sram_reg = regulator_get_optional(dev, "sram");
>
> devm_ for this as well?
>
I will modify it in the next version.
> > + if (IS_ERR(drv->sram_reg))
> > + drv->sram_reg = NULL;
> > + else {
> > + ret = regulator_enable(drv->sram_reg);
> > + if (ret) {
> > + dev_err(dev, "failed to enable sram
> > regulator\n");
> > + goto out_free_resources;
> > + }
> > + }
> > +
> > + /*
> > + * We assume min voltage is 0 and tracking target voltage
> > using
> > + * min_volt_shift for each iteration.
> > + * The retry_max is 3 times of expeted iteration count.
>
> expected?
>
Maybe "the maximum" will be more appropriate?
> > + */
> > + drv->vtrack_max = 3 * DIV_ROUND_UP(max(drv->soc_data-
> > >sram_max_volt,
> > + drv->soc_data-
> > >proc_max_volt),
> > + drv->soc_data-
> > >min_volt_shift);
> > +
> > + ret = clk_prepare_enable(drv->cci_clk);
> > + if (ret)
> > + goto out_free_resources;
> > +
> > + ret = clk_prepare_enable(drv->inter_clk);
>
> You don't need to enable the intermediate clock here. You shouldn't
> need
> to at all, as the CCF core will do it when the CCI clock is
> reparented
> over to it.
I will remove it and all of clk_disable_unprepare(drv->inter_clk) in
this file.
>
> > + if (ret)
> > + goto out_disable_cci_clk;
> > +
> > + ret = dev_pm_opp_of_add_table(dev);
> > + if (ret) {
> > + dev_err(dev, "failed to add opp table: %d\n", ret);
> > + goto out_disable_inter_clk;
> > + }
> > +
> > + rate = clk_get_rate(drv->inter_clk);
> > + opp = dev_pm_opp_find_freq_ceil(dev, &rate);
> > + if (IS_ERR(opp)) {
> > + ret = PTR_ERR(opp);
> > + dev_err(dev, "failed to get intermediate opp:
> > %d\n", ret);
> > + goto out_remove_opp_table;
> > + }
> > + drv->inter_voltage = dev_pm_opp_get_voltage(opp);
> > + dev_pm_opp_put(opp);
> > +
> > + rate = U32_MAX;
> > + opp = dev_pm_opp_find_freq_floor(drv->dev, &rate);
> > + if (IS_ERR(opp)) {
> > + dev_err(dev, "failed to get opp\n");
> > + ret = PTR_ERR(opp);
> > + goto out_remove_opp_table;
> > + }
> > +
> > + opp_volt = dev_pm_opp_get_voltage(opp);
> > + dev_pm_opp_put(opp);
> > + ret = mtk_ccifreq_set_voltage(drv, opp_volt);
> > + if (ret) {
> > + dev_err(dev, "failed to scale to highest voltage
> > %lu in proc_reg\n",
> > + opp_volt);
> > + goto out_remove_opp_table;
> > + }
> > +
> > + passive_data = devm_kzalloc(dev, sizeof(struct
> > devfreq_passive_data),
> > + GFP_KERNEL);
> > + if (!passive_data) {
> > + ret = -ENOMEM;
> > + goto out_remove_opp_table;
> > + }
> > +
> > + passive_data->parent_type = CPUFREQ_PARENT_DEV;
> > + drv->devfreq = devm_devfreq_add_device(dev,
> > &mtk_ccifreq_profile,
> > + DEVFREQ_GOV_PASSIVE,
> > + passive_data);
> > + if (IS_ERR(drv->devfreq)) {
> > + ret = -EPROBE_DEFER;
> > + dev_err(dev, "failed to add devfreq device: %ld\n",
> > + PTR_ERR(drv->devfreq));
> > + goto out_remove_opp_table;
> > + }
> > +
> > + drv->opp_nb.notifier_call = mtk_ccifreq_opp_notifier;
> > + ret = dev_pm_opp_register_notifier(dev, &drv->opp_nb);
> > + if (ret) {
> > + dev_err(dev, "failed to register opp notifier:
> > %d\n", ret);
> > + goto out_remove_devfreq_device;
> > + }
> > + return 0;
> > +
> > +out_remove_devfreq_device:
> > + devm_devfreq_remove_device(dev, drv->devfreq);
> > +
> > +out_remove_opp_table:
> > + dev_pm_opp_of_remove_table(dev);
> > +
> > +out_disable_inter_clk:
> > + clk_disable_unprepare(drv->inter_clk);
> > +
> > +out_disable_cci_clk:
> > + clk_disable_unprepare(drv->cci_clk);
> > +
> > +out_free_resources:
> > + if (regulator_is_enabled(drv->proc_reg))
> > + regulator_disable(drv->proc_reg);
> > + if (drv->sram_reg && regulator_is_enabled(drv->sram_reg))
> > + regulator_disable(drv->sram_reg);
> > +
> > + if (!IS_ERR(drv->proc_reg))
> > + regulator_put(drv->proc_reg);
> > + if (!IS_ERR(drv->sram_reg))
> > + regulator_put(drv->sram_reg);
> > + if (!IS_ERR(drv->cci_clk))
> > + clk_put(drv->cci_clk);
> > + if (!IS_ERR(drv->inter_clk))
> > + clk_put(drv->inter_clk);
>
> You don't need to "put" the resources you got using devm_ variants.
> If you really want to, you need to use devm_(clk|regulator)_put.
>
I think I will remove these lines in the next version.
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_ccifreq_remove(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct mtk_ccifreq_drv *drv;
> > +
> > + drv = platform_get_drvdata(pdev);
> > +
> > + dev_pm_opp_unregister_notifier(dev, &drv->opp_nb);
> > + dev_pm_opp_of_remove_table(dev);
> > + clk_disable_unprepare(drv->inter_clk);
> > + clk_disable_unprepare(drv->cci_clk);
> > + regulator_disable(drv->proc_reg);
> > + if (drv->sram_reg)
> > + regulator_disable(drv->sram_reg);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct mtk_ccifreq_platform_data mt8183_platform_data
> > = {
> > + .min_volt_shift = 100000,
> > + .max_volt_shift = 200000,
> > + .proc_max_volt = 1150000,
> > + .sram_min_volt = 0,
> > + .sram_max_volt = 1150000,
>
> AFAICT there's no sram supply for MT8183, so set max to zero as well?
> And you can just drop the two lines instead of explicitly setting
> them to zero.
>
Sure, I will drop these two line.
> > +};
> > +
> > +static const struct mtk_ccifreq_platform_data mt8186_platform_data
> > = {
> > + .min_volt_shift = 100000,
> > + .max_volt_shift = 250000,
> > + .proc_max_volt = 1118750,
> > + .sram_min_volt = 850000,
> > + .sram_max_volt = 1118750,
>
> A side note about this: the min/max voltage values should also be set
> on the regulator nodes in the device tree. The range then gets
> enforced
> by the regulator core.
>
Thanks for your reminder.
We will notice this when we are sending dts patches.
BRs,
Johnson Wang
>
> Regards
> ChenYu
>
> > +};
> > +
> > +static const struct of_device_id mtk_ccifreq_machines[] = {
> > + { .compatible = "mediatek,mt8183-cci", .data =
> > &mt8183_platform_data },
> > + { .compatible = "mediatek,mt8186-cci", .data =
> > &mt8186_platform_data },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_ccifreq_machines);
> > +
> > +static struct platform_driver mtk_ccifreq_platdrv = {
> > + .probe = mtk_ccifreq_probe,
> > + .remove = mtk_ccifreq_remove,
> > + .driver = {
> > + .name = "mtk-ccifreq",
> > + .of_match_table = mtk_ccifreq_machines,
> > + },
> > +};
> > +module_platform_driver(mtk_ccifreq_platdrv);
> > +
> > +MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
> > +MODULE_AUTHOR("Jia-Wei Chang <jia-wei.chang@mediatek.com>");
> > +MODULE_LICENSE("GPL v2");
> > --
> > 2.18.0
> >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
@ 2022-05-18 12:19 ` Johnson Wang
0 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-18 12:19 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
Hi Chen-Yu,
On Fri, 2022-05-13 at 11:54 +0800, Chen-Yu Tsai wrote:
> On Fri, May 13, 2022 at 11:31 AM Johnson Wang <
> johnson.wang@mediatek.com> wrote:
> >
> > We introduce a devfreq driver for the MediaTek Cache Coherent
> > Interconnect
> > (CCI) used by some MediaTek SoCs.
> >
> > In this driver, we use the passive devfreq driver to get target
> > frequencies
> > and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek
> > CCI
> > is supplied by the same regulators with the little core CPUs.
> >
> > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> > ---
> > This patch depends on "devfreq-testing"[1].
> > [1]
> > https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing__;!!CTRNKA9wMg0ARbw!zzOSoso9udvDV3h6kYlmizFtbn3ACA5aS2jCAjKyvtu4z0fobv1mD5uF9YbPSme8l_NnR05unTxkZfDdzohu8asWZQ$
> >
> > ---
> > drivers/devfreq/Kconfig | 10 +
> > drivers/devfreq/Makefile | 1 +
> > drivers/devfreq/mtk-cci-devfreq.c | 474
> > ++++++++++++++++++++++++++++++
> > 3 files changed, 485 insertions(+)
> > create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
> >
> > diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> > index 87eb2b837e68..9754d8b31621 100644
> > --- a/drivers/devfreq/Kconfig
> > +++ b/drivers/devfreq/Kconfig
> > @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> > It reads ACTMON counters of memory controllers and
> > adjusts the
> > operating frequencies and voltages with OPP support.
> >
> > +config ARM_MEDIATEK_CCI_DEVFREQ
> > + tristate "MEDIATEK CCI DEVFREQ Driver"
> > + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> > + select DEVFREQ_GOV_PASSIVE
> > + help
> > + This adds a devfreq driver for MediaTek Cache Coherent
> > Interconnect
> > + which is shared the same regulators with the cpu cluster.
> > It can track
> > + buck voltages and update a proper CCI frequency. Use the
> > notification
> > + to get the regulator status.
> > +
> > config ARM_RK3399_DMC_DEVFREQ
> > tristate "ARM RK3399 DMC DEVFREQ Driver"
> > depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> > diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> > index 0b6be92a25d9..bf40d04928d0 100644
> > --- a/drivers/devfreq/Makefile
> > +++ b/drivers/devfreq/Makefile
> > @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=
> > governor_passive.o
> > obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> > obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> > obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> > +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> > obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> > obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
> > obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-
> > devfreq.o
> > diff --git a/drivers/devfreq/mtk-cci-devfreq.c
> > b/drivers/devfreq/mtk-cci-devfreq.c
> > new file mode 100644
> > index 000000000000..aa8c37eb4a06
> > --- /dev/null
> > +++ b/drivers/devfreq/mtk-cci-devfreq.c
> > @@ -0,0 +1,474 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (C) 2022 MediaTek Inc.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/devfreq.h>
> > +#include <linux/minmax.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_opp.h>
> > +#include <linux/regulator/consumer.h>
> > +
> > +struct mtk_ccifreq_platform_data {
> > + int min_volt_shift;
> > + int max_volt_shift;
> > + int proc_max_volt;
> > + int sram_min_volt;
> > + int sram_max_volt;
> > +};
> > +
> > +struct mtk_ccifreq_drv {
> > + struct device *dev;
> > + struct devfreq *devfreq;
> > + struct regulator *proc_reg;
> > + struct regulator *sram_reg;
> > + struct clk *cci_clk;
> > + struct clk *inter_clk;
> > + int inter_voltage;
> > + int pre_voltage;
> > + unsigned long pre_freq;
> > + /* Avoid race condition for regulators between notify and
> > policy */
> > + struct mutex reg_lock;
> > + struct notifier_block opp_nb;
> > + const struct mtk_ccifreq_platform_data *soc_data;
> > + int vtrack_max;
> > +};
> > +
> > +static int mtk_ccifreq_set_voltage(struct mtk_ccifreq_drv *drv,
> > int new_voltage)
> > +{
> > + const struct mtk_ccifreq_platform_data *soc_data = drv-
> > >soc_data;
> > + struct device *dev = drv->dev;
> > + int pre_voltage, pre_vsram, new_vsram, vsram, voltage, ret;
> > + int retry_max = drv->vtrack_max;
> > +
> > + if (!drv->sram_reg) {
> > + ret = regulator_set_voltage(drv->proc_reg,
> > new_voltage,
> > + drv->soc_data-
> > >proc_max_volt);
> > + goto out_set_voltage;
> > + }
> > +
> > + pre_voltage = regulator_get_voltage(drv->proc_reg);
> > + if (pre_voltage < 0) {
> > + dev_err(dev, "invalid vproc value: %d\n",
> > pre_voltage);
> > + return pre_voltage;
> > + }
> > +
> > + pre_vsram = regulator_get_voltage(drv->sram_reg);
> > + if (pre_vsram < 0) {
> > + dev_err(dev, "invalid vsram value: %d\n",
> > pre_vsram);
> > + return pre_vsram;
> > + }
> > +
> > + new_vsram = clamp(new_voltage + soc_data->min_volt_shift,
> > + soc_data->sram_min_volt, soc_data-
> > >sram_max_volt);
> > +
> > + do {
> > + if (pre_voltage <= new_voltage) {
> > + vsram = clamp(pre_voltage + soc_data-
> > >max_volt_shift,
> > + soc_data->sram_min_volt,
> > new_vsram);
> > + ret = regulator_set_voltage(drv->sram_reg,
> > vsram,
> > + soc_data-
> > >sram_max_volt);
> > + if (ret)
> > + return ret;
> > +
> > + if (vsram == soc_data->sram_max_volt ||
> > + new_vsram == soc_data->sram_min_volt)
> > + voltage = new_voltage;
> > + else
> > + voltage = vsram - soc_data-
> > >min_volt_shift;
> > +
> > + ret = regulator_set_voltage(drv->proc_reg,
> > voltage,
> > + soc_data-
> > >proc_max_volt);
> > + if (ret) {
> > + regulator_set_voltage(drv-
> > >sram_reg, pre_vsram,
> > + soc_data-
> > >sram_max_volt);
> > + return ret;
> > + }
> > + } else if (pre_voltage > new_voltage) {
> > + voltage = max(new_voltage,
> > + pre_vsram - soc_data-
> > >max_volt_shift);
> > + ret = regulator_set_voltage(drv->proc_reg,
> > voltage,
> > + soc_data-
> > >proc_max_volt);
> > + if (ret)
> > + return ret;
> > +
> > + if (voltage == new_voltage)
> > + vsram = new_vsram;
> > + else
> > + vsram = max(new_vsram,
> > + voltage + soc_data-
> > >min_volt_shift);
> > +
> > + ret = regulator_set_voltage(drv->sram_reg,
> > vsram,
> > + soc_data-
> > >sram_max_volt);
> > + if (ret) {
> > + regulator_set_voltage(drv-
> > >proc_reg, pre_voltage,
> > + soc_data-
> > >proc_max_volt);
> > + return ret;
> > + }
> > + }
> > +
> > + pre_voltage = voltage;
> > + pre_vsram = vsram;
> > +
> > + if (--retry_max < 0) {
> > + dev_err(dev,
> > + "over loop count, failed to set
> > voltage\n");
> > + return -EINVAL;
> > + }
> > + } while (voltage != new_voltage || vsram != new_vsram);
> > +
> > +out_set_voltage:
> > + if (!ret)
> > + drv->pre_voltage = new_voltage;
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_ccifreq_target(struct device *dev, unsigned long
> > *freq,
> > + u32 flags)
> > +{
> > + struct mtk_ccifreq_drv *drv = dev_get_drvdata(dev);
> > + struct clk *cci_pll = clk_get_parent(drv->cci_clk);
> > + struct dev_pm_opp *opp;
> > + unsigned long opp_rate;
> > + int voltage, pre_voltage, inter_voltage, target_voltage,
> > ret;
> > +
> > + if (!drv)
> > + return -EINVAL;
> > +
> > + if (drv->pre_freq == *freq)
> > + return 0;
> > +
> > + inter_voltage = drv->inter_voltage;
> > +
> > + opp_rate = *freq;
> > + opp = devfreq_recommended_opp(dev, &opp_rate, 1);
> > + if (IS_ERR(opp)) {
> > + dev_err(dev, "failed to find opp for freq: %ld\n",
> > opp_rate);
> > + return PTR_ERR(opp);
> > + }
> > +
> > + mutex_lock(&drv->reg_lock);
> > +
> > + voltage = dev_pm_opp_get_voltage(opp);
> > + dev_pm_opp_put(opp);
> > +
> > + if (unlikely(drv->pre_voltage <= 0))
> > + pre_voltage = regulator_get_voltage(drv->proc_reg);
> > + else
> > + pre_voltage = drv->pre_voltage;
>
> Could you explain why the previous voltage setting is cached like
> this?
>
> The CCI is sharing the regulator supply with one of the CPU clusters,
> and cpufreq could also change the voltage, so it's better to always
> retrieve the current setting directly from the regulator core. And
> those values might be cached iun the core, so it's unlikely to incur
> a significant cost.
Thanks for your suggestion.
I will modify it as mtk_ccifreq_set_voltage() does.
In that way I will try to remove pre_voltage member because it's no
longer needed.
> > +
> > + if (pre_voltage < 0) {
> > + dev_err(dev, "invalid vproc value: %d\n",
> > pre_voltage);
> > + return pre_voltage;
> > + }
> > +
> > + /* scale up: set voltage first then freq. */
> > + target_voltage = max(inter_voltage, voltage);
> > + if (pre_voltage <= target_voltage) {
> > + ret = mtk_ccifreq_set_voltage(drv, target_voltage);
> > + if (ret) {
> > + dev_err(dev, "failed to scale up
> > voltage\n");
> > + goto out_restore_voltage;
> > + }
> > + }
> > +
> > + /* switch the cci clock to intermediate clock source. */
> > + ret = clk_set_parent(drv->cci_clk, drv->inter_clk);
> > + if (ret) {
> > + dev_err(dev, "failed to re-parent cci clock\n");
> > + goto out_restore_voltage;
> > + }
> > +
> > + /* set the original clock to target rate. */
> > + ret = clk_set_rate(cci_pll, *freq);
> > + if (ret) {
> > + dev_err(dev, "failed to set cci pll rate: %d\n",
> > ret);
> > + clk_set_parent(drv->cci_clk, cci_pll);
> > + goto out_restore_voltage;
> > + }
> > +
> > + /* switch the cci clock back to the original clock source.
> > */
> > + ret = clk_set_parent(drv->cci_clk, cci_pll);
> > + if (ret) {
> > + dev_err(dev, "failed to re-parent cci clock\n");
> > + mtk_ccifreq_set_voltage(drv, inter_voltage);
> > + goto out_unlock;
> > + }
> > +
> > + /*
> > + * If the new voltage is lower than the intermediate
> > voltage or the
> > + * original voltage, scale down to the new voltage.
> > + */
> > + if (voltage < inter_voltage || voltage < pre_voltage) {
> > + ret = mtk_ccifreq_set_voltage(drv, voltage);
> > + if (ret) {
> > + dev_err(dev, "failed to scale down
> > voltage\n");
> > + goto out_unlock;
> > + }
> > + }
> > +
> > + drv->pre_freq = *freq;
> > + mutex_unlock(&drv->reg_lock);
> > +
> > + return 0;
> > +
> > +out_restore_voltage:
> > + mtk_ccifreq_set_voltage(drv, pre_voltage);
> > +
> > +out_unlock:
> > + mutex_unlock(&drv->reg_lock);
> > + return ret;
> > +}
> > +
> > +static int mtk_ccifreq_opp_notifier(struct notifier_block *nb,
> > + unsigned long event, void
> > *data)
> > +{
> > + struct dev_pm_opp *opp = data;
> > + struct mtk_ccifreq_drv *drv;
> > + unsigned long freq, volt;
> > +
> > + drv = container_of(nb, struct mtk_ccifreq_drv, opp_nb);
> > +
> > + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + mutex_lock(&drv->reg_lock);
> > + /* current opp item is changed */
> > + if (freq == drv->pre_freq) {
> > + volt = dev_pm_opp_get_voltage(opp);
> > + mtk_ccifreq_set_voltage(drv, volt);
> > + }
> > + mutex_unlock(&drv->reg_lock);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static struct devfreq_dev_profile mtk_ccifreq_profile = {
> > + .target = mtk_ccifreq_target,
> > +};
> > +
> > +static int mtk_ccifreq_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct mtk_ccifreq_drv *drv;
> > + struct devfreq_passive_data *passive_data;
> > + struct dev_pm_opp *opp;
> > + unsigned long rate, opp_volt;
> > + int ret;
> > +
> > + drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
> > + if (!drv)
> > + return -ENOMEM;
> > +
> > + drv->dev = dev;
> > + drv->soc_data = (const struct mtk_ccifreq_platform_data *)
> > + of_device_get_match_data(&pdev-
> > >dev);
> > + mutex_init(&drv->reg_lock);
> > + platform_set_drvdata(pdev, drv);
> > +
> > + drv->cci_clk = devm_clk_get(dev, "cci");
> > + if (IS_ERR(drv->cci_clk)) {
> > + ret = PTR_ERR(drv->cci_clk);
> > + return dev_err_probe(dev, ret,
> > + "failed to get cci clk: %d\n",
> > ret);
> > + }
> > +
> > + drv->inter_clk = devm_clk_get(dev, "intermediate");
> > + if (IS_ERR(drv->inter_clk)) {
> > + ret = PTR_ERR(drv->inter_clk);
> > + dev_err_probe(dev, ret,
> > + "failed to get intermediate clk:
> > %d\n", ret);
> > + goto out_free_resources;
> > + }
> > +
> > + drv->proc_reg = devm_regulator_get_optional(dev, "proc");
> > + if (IS_ERR(drv->proc_reg)) {
> > + ret = PTR_ERR(drv->proc_reg);
> > + dev_err_probe(dev, ret,
> > + "failed to get proc regulator: %d\n",
> > ret);
> > + goto out_free_resources;
> > + }
> > +
> > + ret = regulator_enable(drv->proc_reg);
> > + if (ret) {
> > + dev_err(dev, "failed to enable proc regulator\n");
> > + goto out_free_resources;
> > + }
> > +
> > + drv->sram_reg = regulator_get_optional(dev, "sram");
>
> devm_ for this as well?
>
I will modify it in the next version.
> > + if (IS_ERR(drv->sram_reg))
> > + drv->sram_reg = NULL;
> > + else {
> > + ret = regulator_enable(drv->sram_reg);
> > + if (ret) {
> > + dev_err(dev, "failed to enable sram
> > regulator\n");
> > + goto out_free_resources;
> > + }
> > + }
> > +
> > + /*
> > + * We assume min voltage is 0 and tracking target voltage
> > using
> > + * min_volt_shift for each iteration.
> > + * The retry_max is 3 times of expeted iteration count.
>
> expected?
>
Maybe "the maximum" will be more appropriate?
> > + */
> > + drv->vtrack_max = 3 * DIV_ROUND_UP(max(drv->soc_data-
> > >sram_max_volt,
> > + drv->soc_data-
> > >proc_max_volt),
> > + drv->soc_data-
> > >min_volt_shift);
> > +
> > + ret = clk_prepare_enable(drv->cci_clk);
> > + if (ret)
> > + goto out_free_resources;
> > +
> > + ret = clk_prepare_enable(drv->inter_clk);
>
> You don't need to enable the intermediate clock here. You shouldn't
> need
> to at all, as the CCF core will do it when the CCI clock is
> reparented
> over to it.
I will remove it and all of clk_disable_unprepare(drv->inter_clk) in
this file.
>
> > + if (ret)
> > + goto out_disable_cci_clk;
> > +
> > + ret = dev_pm_opp_of_add_table(dev);
> > + if (ret) {
> > + dev_err(dev, "failed to add opp table: %d\n", ret);
> > + goto out_disable_inter_clk;
> > + }
> > +
> > + rate = clk_get_rate(drv->inter_clk);
> > + opp = dev_pm_opp_find_freq_ceil(dev, &rate);
> > + if (IS_ERR(opp)) {
> > + ret = PTR_ERR(opp);
> > + dev_err(dev, "failed to get intermediate opp:
> > %d\n", ret);
> > + goto out_remove_opp_table;
> > + }
> > + drv->inter_voltage = dev_pm_opp_get_voltage(opp);
> > + dev_pm_opp_put(opp);
> > +
> > + rate = U32_MAX;
> > + opp = dev_pm_opp_find_freq_floor(drv->dev, &rate);
> > + if (IS_ERR(opp)) {
> > + dev_err(dev, "failed to get opp\n");
> > + ret = PTR_ERR(opp);
> > + goto out_remove_opp_table;
> > + }
> > +
> > + opp_volt = dev_pm_opp_get_voltage(opp);
> > + dev_pm_opp_put(opp);
> > + ret = mtk_ccifreq_set_voltage(drv, opp_volt);
> > + if (ret) {
> > + dev_err(dev, "failed to scale to highest voltage
> > %lu in proc_reg\n",
> > + opp_volt);
> > + goto out_remove_opp_table;
> > + }
> > +
> > + passive_data = devm_kzalloc(dev, sizeof(struct
> > devfreq_passive_data),
> > + GFP_KERNEL);
> > + if (!passive_data) {
> > + ret = -ENOMEM;
> > + goto out_remove_opp_table;
> > + }
> > +
> > + passive_data->parent_type = CPUFREQ_PARENT_DEV;
> > + drv->devfreq = devm_devfreq_add_device(dev,
> > &mtk_ccifreq_profile,
> > + DEVFREQ_GOV_PASSIVE,
> > + passive_data);
> > + if (IS_ERR(drv->devfreq)) {
> > + ret = -EPROBE_DEFER;
> > + dev_err(dev, "failed to add devfreq device: %ld\n",
> > + PTR_ERR(drv->devfreq));
> > + goto out_remove_opp_table;
> > + }
> > +
> > + drv->opp_nb.notifier_call = mtk_ccifreq_opp_notifier;
> > + ret = dev_pm_opp_register_notifier(dev, &drv->opp_nb);
> > + if (ret) {
> > + dev_err(dev, "failed to register opp notifier:
> > %d\n", ret);
> > + goto out_remove_devfreq_device;
> > + }
> > + return 0;
> > +
> > +out_remove_devfreq_device:
> > + devm_devfreq_remove_device(dev, drv->devfreq);
> > +
> > +out_remove_opp_table:
> > + dev_pm_opp_of_remove_table(dev);
> > +
> > +out_disable_inter_clk:
> > + clk_disable_unprepare(drv->inter_clk);
> > +
> > +out_disable_cci_clk:
> > + clk_disable_unprepare(drv->cci_clk);
> > +
> > +out_free_resources:
> > + if (regulator_is_enabled(drv->proc_reg))
> > + regulator_disable(drv->proc_reg);
> > + if (drv->sram_reg && regulator_is_enabled(drv->sram_reg))
> > + regulator_disable(drv->sram_reg);
> > +
> > + if (!IS_ERR(drv->proc_reg))
> > + regulator_put(drv->proc_reg);
> > + if (!IS_ERR(drv->sram_reg))
> > + regulator_put(drv->sram_reg);
> > + if (!IS_ERR(drv->cci_clk))
> > + clk_put(drv->cci_clk);
> > + if (!IS_ERR(drv->inter_clk))
> > + clk_put(drv->inter_clk);
>
> You don't need to "put" the resources you got using devm_ variants.
> If you really want to, you need to use devm_(clk|regulator)_put.
>
I think I will remove these lines in the next version.
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_ccifreq_remove(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct mtk_ccifreq_drv *drv;
> > +
> > + drv = platform_get_drvdata(pdev);
> > +
> > + dev_pm_opp_unregister_notifier(dev, &drv->opp_nb);
> > + dev_pm_opp_of_remove_table(dev);
> > + clk_disable_unprepare(drv->inter_clk);
> > + clk_disable_unprepare(drv->cci_clk);
> > + regulator_disable(drv->proc_reg);
> > + if (drv->sram_reg)
> > + regulator_disable(drv->sram_reg);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct mtk_ccifreq_platform_data mt8183_platform_data
> > = {
> > + .min_volt_shift = 100000,
> > + .max_volt_shift = 200000,
> > + .proc_max_volt = 1150000,
> > + .sram_min_volt = 0,
> > + .sram_max_volt = 1150000,
>
> AFAICT there's no sram supply for MT8183, so set max to zero as well?
> And you can just drop the two lines instead of explicitly setting
> them to zero.
>
Sure, I will drop these two line.
> > +};
> > +
> > +static const struct mtk_ccifreq_platform_data mt8186_platform_data
> > = {
> > + .min_volt_shift = 100000,
> > + .max_volt_shift = 250000,
> > + .proc_max_volt = 1118750,
> > + .sram_min_volt = 850000,
> > + .sram_max_volt = 1118750,
>
> A side note about this: the min/max voltage values should also be set
> on the regulator nodes in the device tree. The range then gets
> enforced
> by the regulator core.
>
Thanks for your reminder.
We will notice this when we are sending dts patches.
BRs,
Johnson Wang
>
> Regards
> ChenYu
>
> > +};
> > +
> > +static const struct of_device_id mtk_ccifreq_machines[] = {
> > + { .compatible = "mediatek,mt8183-cci", .data =
> > &mt8183_platform_data },
> > + { .compatible = "mediatek,mt8186-cci", .data =
> > &mt8186_platform_data },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_ccifreq_machines);
> > +
> > +static struct platform_driver mtk_ccifreq_platdrv = {
> > + .probe = mtk_ccifreq_probe,
> > + .remove = mtk_ccifreq_remove,
> > + .driver = {
> > + .name = "mtk-ccifreq",
> > + .of_match_table = mtk_ccifreq_machines,
> > + },
> > +};
> > +module_platform_driver(mtk_ccifreq_platdrv);
> > +
> > +MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
> > +MODULE_AUTHOR("Jia-Wei Chang <jia-wei.chang@mediatek.com>");
> > +MODULE_LICENSE("GPL v2");
> > --
> > 2.18.0
> >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
@ 2022-05-18 12:19 ` Johnson Wang
0 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-18 12:19 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
Hi Chen-Yu,
On Fri, 2022-05-13 at 11:54 +0800, Chen-Yu Tsai wrote:
> On Fri, May 13, 2022 at 11:31 AM Johnson Wang <
> johnson.wang@mediatek.com> wrote:
> >
> > We introduce a devfreq driver for the MediaTek Cache Coherent
> > Interconnect
> > (CCI) used by some MediaTek SoCs.
> >
> > In this driver, we use the passive devfreq driver to get target
> > frequencies
> > and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek
> > CCI
> > is supplied by the same regulators with the little core CPUs.
> >
> > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> > ---
> > This patch depends on "devfreq-testing"[1].
> > [1]
> > https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing__;!!CTRNKA9wMg0ARbw!zzOSoso9udvDV3h6kYlmizFtbn3ACA5aS2jCAjKyvtu4z0fobv1mD5uF9YbPSme8l_NnR05unTxkZfDdzohu8asWZQ$
> >
> > ---
> > drivers/devfreq/Kconfig | 10 +
> > drivers/devfreq/Makefile | 1 +
> > drivers/devfreq/mtk-cci-devfreq.c | 474
> > ++++++++++++++++++++++++++++++
> > 3 files changed, 485 insertions(+)
> > create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
> >
> > diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> > index 87eb2b837e68..9754d8b31621 100644
> > --- a/drivers/devfreq/Kconfig
> > +++ b/drivers/devfreq/Kconfig
> > @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> > It reads ACTMON counters of memory controllers and
> > adjusts the
> > operating frequencies and voltages with OPP support.
> >
> > +config ARM_MEDIATEK_CCI_DEVFREQ
> > + tristate "MEDIATEK CCI DEVFREQ Driver"
> > + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> > + select DEVFREQ_GOV_PASSIVE
> > + help
> > + This adds a devfreq driver for MediaTek Cache Coherent
> > Interconnect
> > + which is shared the same regulators with the cpu cluster.
> > It can track
> > + buck voltages and update a proper CCI frequency. Use the
> > notification
> > + to get the regulator status.
> > +
> > config ARM_RK3399_DMC_DEVFREQ
> > tristate "ARM RK3399 DMC DEVFREQ Driver"
> > depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> > diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> > index 0b6be92a25d9..bf40d04928d0 100644
> > --- a/drivers/devfreq/Makefile
> > +++ b/drivers/devfreq/Makefile
> > @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=
> > governor_passive.o
> > obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> > obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> > obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> > +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> > obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> > obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
> > obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-
> > devfreq.o
> > diff --git a/drivers/devfreq/mtk-cci-devfreq.c
> > b/drivers/devfreq/mtk-cci-devfreq.c
> > new file mode 100644
> > index 000000000000..aa8c37eb4a06
> > --- /dev/null
> > +++ b/drivers/devfreq/mtk-cci-devfreq.c
> > @@ -0,0 +1,474 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +/*
> > + * Copyright (C) 2022 MediaTek Inc.
> > + */
> > +
> > +#include <linux/clk.h>
> > +#include <linux/devfreq.h>
> > +#include <linux/minmax.h>
> > +#include <linux/module.h>
> > +#include <linux/of.h>
> > +#include <linux/of_device.h>
> > +#include <linux/platform_device.h>
> > +#include <linux/pm_opp.h>
> > +#include <linux/regulator/consumer.h>
> > +
> > +struct mtk_ccifreq_platform_data {
> > + int min_volt_shift;
> > + int max_volt_shift;
> > + int proc_max_volt;
> > + int sram_min_volt;
> > + int sram_max_volt;
> > +};
> > +
> > +struct mtk_ccifreq_drv {
> > + struct device *dev;
> > + struct devfreq *devfreq;
> > + struct regulator *proc_reg;
> > + struct regulator *sram_reg;
> > + struct clk *cci_clk;
> > + struct clk *inter_clk;
> > + int inter_voltage;
> > + int pre_voltage;
> > + unsigned long pre_freq;
> > + /* Avoid race condition for regulators between notify and
> > policy */
> > + struct mutex reg_lock;
> > + struct notifier_block opp_nb;
> > + const struct mtk_ccifreq_platform_data *soc_data;
> > + int vtrack_max;
> > +};
> > +
> > +static int mtk_ccifreq_set_voltage(struct mtk_ccifreq_drv *drv,
> > int new_voltage)
> > +{
> > + const struct mtk_ccifreq_platform_data *soc_data = drv-
> > >soc_data;
> > + struct device *dev = drv->dev;
> > + int pre_voltage, pre_vsram, new_vsram, vsram, voltage, ret;
> > + int retry_max = drv->vtrack_max;
> > +
> > + if (!drv->sram_reg) {
> > + ret = regulator_set_voltage(drv->proc_reg,
> > new_voltage,
> > + drv->soc_data-
> > >proc_max_volt);
> > + goto out_set_voltage;
> > + }
> > +
> > + pre_voltage = regulator_get_voltage(drv->proc_reg);
> > + if (pre_voltage < 0) {
> > + dev_err(dev, "invalid vproc value: %d\n",
> > pre_voltage);
> > + return pre_voltage;
> > + }
> > +
> > + pre_vsram = regulator_get_voltage(drv->sram_reg);
> > + if (pre_vsram < 0) {
> > + dev_err(dev, "invalid vsram value: %d\n",
> > pre_vsram);
> > + return pre_vsram;
> > + }
> > +
> > + new_vsram = clamp(new_voltage + soc_data->min_volt_shift,
> > + soc_data->sram_min_volt, soc_data-
> > >sram_max_volt);
> > +
> > + do {
> > + if (pre_voltage <= new_voltage) {
> > + vsram = clamp(pre_voltage + soc_data-
> > >max_volt_shift,
> > + soc_data->sram_min_volt,
> > new_vsram);
> > + ret = regulator_set_voltage(drv->sram_reg,
> > vsram,
> > + soc_data-
> > >sram_max_volt);
> > + if (ret)
> > + return ret;
> > +
> > + if (vsram == soc_data->sram_max_volt ||
> > + new_vsram == soc_data->sram_min_volt)
> > + voltage = new_voltage;
> > + else
> > + voltage = vsram - soc_data-
> > >min_volt_shift;
> > +
> > + ret = regulator_set_voltage(drv->proc_reg,
> > voltage,
> > + soc_data-
> > >proc_max_volt);
> > + if (ret) {
> > + regulator_set_voltage(drv-
> > >sram_reg, pre_vsram,
> > + soc_data-
> > >sram_max_volt);
> > + return ret;
> > + }
> > + } else if (pre_voltage > new_voltage) {
> > + voltage = max(new_voltage,
> > + pre_vsram - soc_data-
> > >max_volt_shift);
> > + ret = regulator_set_voltage(drv->proc_reg,
> > voltage,
> > + soc_data-
> > >proc_max_volt);
> > + if (ret)
> > + return ret;
> > +
> > + if (voltage == new_voltage)
> > + vsram = new_vsram;
> > + else
> > + vsram = max(new_vsram,
> > + voltage + soc_data-
> > >min_volt_shift);
> > +
> > + ret = regulator_set_voltage(drv->sram_reg,
> > vsram,
> > + soc_data-
> > >sram_max_volt);
> > + if (ret) {
> > + regulator_set_voltage(drv-
> > >proc_reg, pre_voltage,
> > + soc_data-
> > >proc_max_volt);
> > + return ret;
> > + }
> > + }
> > +
> > + pre_voltage = voltage;
> > + pre_vsram = vsram;
> > +
> > + if (--retry_max < 0) {
> > + dev_err(dev,
> > + "over loop count, failed to set
> > voltage\n");
> > + return -EINVAL;
> > + }
> > + } while (voltage != new_voltage || vsram != new_vsram);
> > +
> > +out_set_voltage:
> > + if (!ret)
> > + drv->pre_voltage = new_voltage;
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_ccifreq_target(struct device *dev, unsigned long
> > *freq,
> > + u32 flags)
> > +{
> > + struct mtk_ccifreq_drv *drv = dev_get_drvdata(dev);
> > + struct clk *cci_pll = clk_get_parent(drv->cci_clk);
> > + struct dev_pm_opp *opp;
> > + unsigned long opp_rate;
> > + int voltage, pre_voltage, inter_voltage, target_voltage,
> > ret;
> > +
> > + if (!drv)
> > + return -EINVAL;
> > +
> > + if (drv->pre_freq == *freq)
> > + return 0;
> > +
> > + inter_voltage = drv->inter_voltage;
> > +
> > + opp_rate = *freq;
> > + opp = devfreq_recommended_opp(dev, &opp_rate, 1);
> > + if (IS_ERR(opp)) {
> > + dev_err(dev, "failed to find opp for freq: %ld\n",
> > opp_rate);
> > + return PTR_ERR(opp);
> > + }
> > +
> > + mutex_lock(&drv->reg_lock);
> > +
> > + voltage = dev_pm_opp_get_voltage(opp);
> > + dev_pm_opp_put(opp);
> > +
> > + if (unlikely(drv->pre_voltage <= 0))
> > + pre_voltage = regulator_get_voltage(drv->proc_reg);
> > + else
> > + pre_voltage = drv->pre_voltage;
>
> Could you explain why the previous voltage setting is cached like
> this?
>
> The CCI is sharing the regulator supply with one of the CPU clusters,
> and cpufreq could also change the voltage, so it's better to always
> retrieve the current setting directly from the regulator core. And
> those values might be cached iun the core, so it's unlikely to incur
> a significant cost.
Thanks for your suggestion.
I will modify it as mtk_ccifreq_set_voltage() does.
In that way I will try to remove pre_voltage member because it's no
longer needed.
> > +
> > + if (pre_voltage < 0) {
> > + dev_err(dev, "invalid vproc value: %d\n",
> > pre_voltage);
> > + return pre_voltage;
> > + }
> > +
> > + /* scale up: set voltage first then freq. */
> > + target_voltage = max(inter_voltage, voltage);
> > + if (pre_voltage <= target_voltage) {
> > + ret = mtk_ccifreq_set_voltage(drv, target_voltage);
> > + if (ret) {
> > + dev_err(dev, "failed to scale up
> > voltage\n");
> > + goto out_restore_voltage;
> > + }
> > + }
> > +
> > + /* switch the cci clock to intermediate clock source. */
> > + ret = clk_set_parent(drv->cci_clk, drv->inter_clk);
> > + if (ret) {
> > + dev_err(dev, "failed to re-parent cci clock\n");
> > + goto out_restore_voltage;
> > + }
> > +
> > + /* set the original clock to target rate. */
> > + ret = clk_set_rate(cci_pll, *freq);
> > + if (ret) {
> > + dev_err(dev, "failed to set cci pll rate: %d\n",
> > ret);
> > + clk_set_parent(drv->cci_clk, cci_pll);
> > + goto out_restore_voltage;
> > + }
> > +
> > + /* switch the cci clock back to the original clock source.
> > */
> > + ret = clk_set_parent(drv->cci_clk, cci_pll);
> > + if (ret) {
> > + dev_err(dev, "failed to re-parent cci clock\n");
> > + mtk_ccifreq_set_voltage(drv, inter_voltage);
> > + goto out_unlock;
> > + }
> > +
> > + /*
> > + * If the new voltage is lower than the intermediate
> > voltage or the
> > + * original voltage, scale down to the new voltage.
> > + */
> > + if (voltage < inter_voltage || voltage < pre_voltage) {
> > + ret = mtk_ccifreq_set_voltage(drv, voltage);
> > + if (ret) {
> > + dev_err(dev, "failed to scale down
> > voltage\n");
> > + goto out_unlock;
> > + }
> > + }
> > +
> > + drv->pre_freq = *freq;
> > + mutex_unlock(&drv->reg_lock);
> > +
> > + return 0;
> > +
> > +out_restore_voltage:
> > + mtk_ccifreq_set_voltage(drv, pre_voltage);
> > +
> > +out_unlock:
> > + mutex_unlock(&drv->reg_lock);
> > + return ret;
> > +}
> > +
> > +static int mtk_ccifreq_opp_notifier(struct notifier_block *nb,
> > + unsigned long event, void
> > *data)
> > +{
> > + struct dev_pm_opp *opp = data;
> > + struct mtk_ccifreq_drv *drv;
> > + unsigned long freq, volt;
> > +
> > + drv = container_of(nb, struct mtk_ccifreq_drv, opp_nb);
> > +
> > + if (event == OPP_EVENT_ADJUST_VOLTAGE) {
> > + freq = dev_pm_opp_get_freq(opp);
> > +
> > + mutex_lock(&drv->reg_lock);
> > + /* current opp item is changed */
> > + if (freq == drv->pre_freq) {
> > + volt = dev_pm_opp_get_voltage(opp);
> > + mtk_ccifreq_set_voltage(drv, volt);
> > + }
> > + mutex_unlock(&drv->reg_lock);
> > + }
> > +
> > + return 0;
> > +}
> > +
> > +static struct devfreq_dev_profile mtk_ccifreq_profile = {
> > + .target = mtk_ccifreq_target,
> > +};
> > +
> > +static int mtk_ccifreq_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct mtk_ccifreq_drv *drv;
> > + struct devfreq_passive_data *passive_data;
> > + struct dev_pm_opp *opp;
> > + unsigned long rate, opp_volt;
> > + int ret;
> > +
> > + drv = devm_kzalloc(dev, sizeof(*drv), GFP_KERNEL);
> > + if (!drv)
> > + return -ENOMEM;
> > +
> > + drv->dev = dev;
> > + drv->soc_data = (const struct mtk_ccifreq_platform_data *)
> > + of_device_get_match_data(&pdev-
> > >dev);
> > + mutex_init(&drv->reg_lock);
> > + platform_set_drvdata(pdev, drv);
> > +
> > + drv->cci_clk = devm_clk_get(dev, "cci");
> > + if (IS_ERR(drv->cci_clk)) {
> > + ret = PTR_ERR(drv->cci_clk);
> > + return dev_err_probe(dev, ret,
> > + "failed to get cci clk: %d\n",
> > ret);
> > + }
> > +
> > + drv->inter_clk = devm_clk_get(dev, "intermediate");
> > + if (IS_ERR(drv->inter_clk)) {
> > + ret = PTR_ERR(drv->inter_clk);
> > + dev_err_probe(dev, ret,
> > + "failed to get intermediate clk:
> > %d\n", ret);
> > + goto out_free_resources;
> > + }
> > +
> > + drv->proc_reg = devm_regulator_get_optional(dev, "proc");
> > + if (IS_ERR(drv->proc_reg)) {
> > + ret = PTR_ERR(drv->proc_reg);
> > + dev_err_probe(dev, ret,
> > + "failed to get proc regulator: %d\n",
> > ret);
> > + goto out_free_resources;
> > + }
> > +
> > + ret = regulator_enable(drv->proc_reg);
> > + if (ret) {
> > + dev_err(dev, "failed to enable proc regulator\n");
> > + goto out_free_resources;
> > + }
> > +
> > + drv->sram_reg = regulator_get_optional(dev, "sram");
>
> devm_ for this as well?
>
I will modify it in the next version.
> > + if (IS_ERR(drv->sram_reg))
> > + drv->sram_reg = NULL;
> > + else {
> > + ret = regulator_enable(drv->sram_reg);
> > + if (ret) {
> > + dev_err(dev, "failed to enable sram
> > regulator\n");
> > + goto out_free_resources;
> > + }
> > + }
> > +
> > + /*
> > + * We assume min voltage is 0 and tracking target voltage
> > using
> > + * min_volt_shift for each iteration.
> > + * The retry_max is 3 times of expeted iteration count.
>
> expected?
>
Maybe "the maximum" will be more appropriate?
> > + */
> > + drv->vtrack_max = 3 * DIV_ROUND_UP(max(drv->soc_data-
> > >sram_max_volt,
> > + drv->soc_data-
> > >proc_max_volt),
> > + drv->soc_data-
> > >min_volt_shift);
> > +
> > + ret = clk_prepare_enable(drv->cci_clk);
> > + if (ret)
> > + goto out_free_resources;
> > +
> > + ret = clk_prepare_enable(drv->inter_clk);
>
> You don't need to enable the intermediate clock here. You shouldn't
> need
> to at all, as the CCF core will do it when the CCI clock is
> reparented
> over to it.
I will remove it and all of clk_disable_unprepare(drv->inter_clk) in
this file.
>
> > + if (ret)
> > + goto out_disable_cci_clk;
> > +
> > + ret = dev_pm_opp_of_add_table(dev);
> > + if (ret) {
> > + dev_err(dev, "failed to add opp table: %d\n", ret);
> > + goto out_disable_inter_clk;
> > + }
> > +
> > + rate = clk_get_rate(drv->inter_clk);
> > + opp = dev_pm_opp_find_freq_ceil(dev, &rate);
> > + if (IS_ERR(opp)) {
> > + ret = PTR_ERR(opp);
> > + dev_err(dev, "failed to get intermediate opp:
> > %d\n", ret);
> > + goto out_remove_opp_table;
> > + }
> > + drv->inter_voltage = dev_pm_opp_get_voltage(opp);
> > + dev_pm_opp_put(opp);
> > +
> > + rate = U32_MAX;
> > + opp = dev_pm_opp_find_freq_floor(drv->dev, &rate);
> > + if (IS_ERR(opp)) {
> > + dev_err(dev, "failed to get opp\n");
> > + ret = PTR_ERR(opp);
> > + goto out_remove_opp_table;
> > + }
> > +
> > + opp_volt = dev_pm_opp_get_voltage(opp);
> > + dev_pm_opp_put(opp);
> > + ret = mtk_ccifreq_set_voltage(drv, opp_volt);
> > + if (ret) {
> > + dev_err(dev, "failed to scale to highest voltage
> > %lu in proc_reg\n",
> > + opp_volt);
> > + goto out_remove_opp_table;
> > + }
> > +
> > + passive_data = devm_kzalloc(dev, sizeof(struct
> > devfreq_passive_data),
> > + GFP_KERNEL);
> > + if (!passive_data) {
> > + ret = -ENOMEM;
> > + goto out_remove_opp_table;
> > + }
> > +
> > + passive_data->parent_type = CPUFREQ_PARENT_DEV;
> > + drv->devfreq = devm_devfreq_add_device(dev,
> > &mtk_ccifreq_profile,
> > + DEVFREQ_GOV_PASSIVE,
> > + passive_data);
> > + if (IS_ERR(drv->devfreq)) {
> > + ret = -EPROBE_DEFER;
> > + dev_err(dev, "failed to add devfreq device: %ld\n",
> > + PTR_ERR(drv->devfreq));
> > + goto out_remove_opp_table;
> > + }
> > +
> > + drv->opp_nb.notifier_call = mtk_ccifreq_opp_notifier;
> > + ret = dev_pm_opp_register_notifier(dev, &drv->opp_nb);
> > + if (ret) {
> > + dev_err(dev, "failed to register opp notifier:
> > %d\n", ret);
> > + goto out_remove_devfreq_device;
> > + }
> > + return 0;
> > +
> > +out_remove_devfreq_device:
> > + devm_devfreq_remove_device(dev, drv->devfreq);
> > +
> > +out_remove_opp_table:
> > + dev_pm_opp_of_remove_table(dev);
> > +
> > +out_disable_inter_clk:
> > + clk_disable_unprepare(drv->inter_clk);
> > +
> > +out_disable_cci_clk:
> > + clk_disable_unprepare(drv->cci_clk);
> > +
> > +out_free_resources:
> > + if (regulator_is_enabled(drv->proc_reg))
> > + regulator_disable(drv->proc_reg);
> > + if (drv->sram_reg && regulator_is_enabled(drv->sram_reg))
> > + regulator_disable(drv->sram_reg);
> > +
> > + if (!IS_ERR(drv->proc_reg))
> > + regulator_put(drv->proc_reg);
> > + if (!IS_ERR(drv->sram_reg))
> > + regulator_put(drv->sram_reg);
> > + if (!IS_ERR(drv->cci_clk))
> > + clk_put(drv->cci_clk);
> > + if (!IS_ERR(drv->inter_clk))
> > + clk_put(drv->inter_clk);
>
> You don't need to "put" the resources you got using devm_ variants.
> If you really want to, you need to use devm_(clk|regulator)_put.
>
I think I will remove these lines in the next version.
> > +
> > + return ret;
> > +}
> > +
> > +static int mtk_ccifreq_remove(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct mtk_ccifreq_drv *drv;
> > +
> > + drv = platform_get_drvdata(pdev);
> > +
> > + dev_pm_opp_unregister_notifier(dev, &drv->opp_nb);
> > + dev_pm_opp_of_remove_table(dev);
> > + clk_disable_unprepare(drv->inter_clk);
> > + clk_disable_unprepare(drv->cci_clk);
> > + regulator_disable(drv->proc_reg);
> > + if (drv->sram_reg)
> > + regulator_disable(drv->sram_reg);
> > +
> > + return 0;
> > +}
> > +
> > +static const struct mtk_ccifreq_platform_data mt8183_platform_data
> > = {
> > + .min_volt_shift = 100000,
> > + .max_volt_shift = 200000,
> > + .proc_max_volt = 1150000,
> > + .sram_min_volt = 0,
> > + .sram_max_volt = 1150000,
>
> AFAICT there's no sram supply for MT8183, so set max to zero as well?
> And you can just drop the two lines instead of explicitly setting
> them to zero.
>
Sure, I will drop these two line.
> > +};
> > +
> > +static const struct mtk_ccifreq_platform_data mt8186_platform_data
> > = {
> > + .min_volt_shift = 100000,
> > + .max_volt_shift = 250000,
> > + .proc_max_volt = 1118750,
> > + .sram_min_volt = 850000,
> > + .sram_max_volt = 1118750,
>
> A side note about this: the min/max voltage values should also be set
> on the regulator nodes in the device tree. The range then gets
> enforced
> by the regulator core.
>
Thanks for your reminder.
We will notice this when we are sending dts patches.
BRs,
Johnson Wang
>
> Regards
> ChenYu
>
> > +};
> > +
> > +static const struct of_device_id mtk_ccifreq_machines[] = {
> > + { .compatible = "mediatek,mt8183-cci", .data =
> > &mt8183_platform_data },
> > + { .compatible = "mediatek,mt8186-cci", .data =
> > &mt8186_platform_data },
> > + { },
> > +};
> > +MODULE_DEVICE_TABLE(of, mtk_ccifreq_machines);
> > +
> > +static struct platform_driver mtk_ccifreq_platdrv = {
> > + .probe = mtk_ccifreq_probe,
> > + .remove = mtk_ccifreq_remove,
> > + .driver = {
> > + .name = "mtk-ccifreq",
> > + .of_match_table = mtk_ccifreq_machines,
> > + },
> > +};
> > +module_platform_driver(mtk_ccifreq_platdrv);
> > +
> > +MODULE_DESCRIPTION("MediaTek CCI devfreq driver");
> > +MODULE_AUTHOR("Jia-Wei Chang <jia-wei.chang@mediatek.com>");
> > +MODULE_LICENSE("GPL v2");
> > --
> > 2.18.0
> >
> >
> > _______________________________________________
> > Linux-mediatek mailing list
> > Linux-mediatek@lists.infradead.org
> > http://lists.infradead.org/mailman/listinfo/linux-mediatek
_______________________________________________
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^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
2022-05-18 12:19 ` Johnson Wang
(?)
@ 2022-05-19 3:24 ` Chen-Yu Tsai
-1 siblings, 0 replies; 30+ messages in thread
From: Chen-Yu Tsai @ 2022-05-19 3:24 UTC (permalink / raw)
To: Johnson Wang
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Wed, May 18, 2022 at 8:19 PM Johnson Wang <johnson.wang@mediatek.com> wrote:
>
> Hi Chen-Yu,
>
> On Fri, 2022-05-13 at 11:54 +0800, Chen-Yu Tsai wrote:
> > On Fri, May 13, 2022 at 11:31 AM Johnson Wang <
> > johnson.wang@mediatek.com> wrote:
> > >
> > > We introduce a devfreq driver for the MediaTek Cache Coherent
> > > Interconnect
> > > (CCI) used by some MediaTek SoCs.
> > >
> > > In this driver, we use the passive devfreq driver to get target
> > > frequencies
> > > and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek
> > > CCI
> > > is supplied by the same regulators with the little core CPUs.
> > >
> > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> > > ---
> > > This patch depends on "devfreq-testing"[1].
> > > [1]
> > > https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing__;!!CTRNKA9wMg0ARbw!zzOSoso9udvDV3h6kYlmizFtbn3ACA5aS2jCAjKyvtu4z0fobv1mD5uF9YbPSme8l_NnR05unTxkZfDdzohu8asWZQ$
> > >
> > > ---
> > > drivers/devfreq/Kconfig | 10 +
> > > drivers/devfreq/Makefile | 1 +
> > > drivers/devfreq/mtk-cci-devfreq.c | 474
> > > ++++++++++++++++++++++++++++++
> > > 3 files changed, 485 insertions(+)
> > > create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
> > >
> > > diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> > > index 87eb2b837e68..9754d8b31621 100644
> > > --- a/drivers/devfreq/Kconfig
> > > +++ b/drivers/devfreq/Kconfig
> > > @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> > > It reads ACTMON counters of memory controllers and
> > > adjusts the
> > > operating frequencies and voltages with OPP support.
> > >
> > > +config ARM_MEDIATEK_CCI_DEVFREQ
> > > + tristate "MEDIATEK CCI DEVFREQ Driver"
> > > + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> > > + select DEVFREQ_GOV_PASSIVE
> > > + help
> > > + This adds a devfreq driver for MediaTek Cache Coherent
> > > Interconnect
> > > + which is shared the same regulators with the cpu cluster.
> > > It can track
> > > + buck voltages and update a proper CCI frequency. Use the
> > > notification
> > > + to get the regulator status.
> > > +
> > > config ARM_RK3399_DMC_DEVFREQ
> > > tristate "ARM RK3399 DMC DEVFREQ Driver"
> > > depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> > > diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> > > index 0b6be92a25d9..bf40d04928d0 100644
> > > --- a/drivers/devfreq/Makefile
> > > +++ b/drivers/devfreq/Makefile
> > > @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=
> > > governor_passive.o
> > > obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> > > obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> > > obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> > > +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> > > obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> > > obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
> > > obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-
> > > devfreq.o
> > > diff --git a/drivers/devfreq/mtk-cci-devfreq.c
> > > b/drivers/devfreq/mtk-cci-devfreq.c
> > > new file mode 100644
> > > index 000000000000..aa8c37eb4a06
> > > --- /dev/null
> > > +++ b/drivers/devfreq/mtk-cci-devfreq.c
> > > @@ -0,0 +1,474 @@
[...]
> > > + if (IS_ERR(drv->sram_reg))
> > > + drv->sram_reg = NULL;
> > > + else {
> > > + ret = regulator_enable(drv->sram_reg);
> > > + if (ret) {
> > > + dev_err(dev, "failed to enable sram
> > > regulator\n");
> > > + goto out_free_resources;
> > > + }
> > > + }
> > > +
> > > + /*
> > > + * We assume min voltage is 0 and tracking target voltage
> > > using
> > > + * min_volt_shift for each iteration.
> > > + * The retry_max is 3 times of expeted iteration count.
> >
> > expected?
> >
> Maybe "the maximum" will be more appropriate?
I was merely pointing out a typo in "expeted".
Looking at it again, I'm not sure why retry attempts are tied to the voltage.
ChenYu
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
@ 2022-05-19 3:24 ` Chen-Yu Tsai
0 siblings, 0 replies; 30+ messages in thread
From: Chen-Yu Tsai @ 2022-05-19 3:24 UTC (permalink / raw)
To: Johnson Wang
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Wed, May 18, 2022 at 8:19 PM Johnson Wang <johnson.wang@mediatek.com> wrote:
>
> Hi Chen-Yu,
>
> On Fri, 2022-05-13 at 11:54 +0800, Chen-Yu Tsai wrote:
> > On Fri, May 13, 2022 at 11:31 AM Johnson Wang <
> > johnson.wang@mediatek.com> wrote:
> > >
> > > We introduce a devfreq driver for the MediaTek Cache Coherent
> > > Interconnect
> > > (CCI) used by some MediaTek SoCs.
> > >
> > > In this driver, we use the passive devfreq driver to get target
> > > frequencies
> > > and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek
> > > CCI
> > > is supplied by the same regulators with the little core CPUs.
> > >
> > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> > > ---
> > > This patch depends on "devfreq-testing"[1].
> > > [1]
> > > https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing__;!!CTRNKA9wMg0ARbw!zzOSoso9udvDV3h6kYlmizFtbn3ACA5aS2jCAjKyvtu4z0fobv1mD5uF9YbPSme8l_NnR05unTxkZfDdzohu8asWZQ$
> > >
> > > ---
> > > drivers/devfreq/Kconfig | 10 +
> > > drivers/devfreq/Makefile | 1 +
> > > drivers/devfreq/mtk-cci-devfreq.c | 474
> > > ++++++++++++++++++++++++++++++
> > > 3 files changed, 485 insertions(+)
> > > create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
> > >
> > > diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> > > index 87eb2b837e68..9754d8b31621 100644
> > > --- a/drivers/devfreq/Kconfig
> > > +++ b/drivers/devfreq/Kconfig
> > > @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> > > It reads ACTMON counters of memory controllers and
> > > adjusts the
> > > operating frequencies and voltages with OPP support.
> > >
> > > +config ARM_MEDIATEK_CCI_DEVFREQ
> > > + tristate "MEDIATEK CCI DEVFREQ Driver"
> > > + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> > > + select DEVFREQ_GOV_PASSIVE
> > > + help
> > > + This adds a devfreq driver for MediaTek Cache Coherent
> > > Interconnect
> > > + which is shared the same regulators with the cpu cluster.
> > > It can track
> > > + buck voltages and update a proper CCI frequency. Use the
> > > notification
> > > + to get the regulator status.
> > > +
> > > config ARM_RK3399_DMC_DEVFREQ
> > > tristate "ARM RK3399 DMC DEVFREQ Driver"
> > > depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> > > diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> > > index 0b6be92a25d9..bf40d04928d0 100644
> > > --- a/drivers/devfreq/Makefile
> > > +++ b/drivers/devfreq/Makefile
> > > @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=
> > > governor_passive.o
> > > obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> > > obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> > > obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> > > +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> > > obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> > > obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
> > > obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-
> > > devfreq.o
> > > diff --git a/drivers/devfreq/mtk-cci-devfreq.c
> > > b/drivers/devfreq/mtk-cci-devfreq.c
> > > new file mode 100644
> > > index 000000000000..aa8c37eb4a06
> > > --- /dev/null
> > > +++ b/drivers/devfreq/mtk-cci-devfreq.c
> > > @@ -0,0 +1,474 @@
[...]
> > > + if (IS_ERR(drv->sram_reg))
> > > + drv->sram_reg = NULL;
> > > + else {
> > > + ret = regulator_enable(drv->sram_reg);
> > > + if (ret) {
> > > + dev_err(dev, "failed to enable sram
> > > regulator\n");
> > > + goto out_free_resources;
> > > + }
> > > + }
> > > +
> > > + /*
> > > + * We assume min voltage is 0 and tracking target voltage
> > > using
> > > + * min_volt_shift for each iteration.
> > > + * The retry_max is 3 times of expeted iteration count.
> >
> > expected?
> >
> Maybe "the maximum" will be more appropriate?
I was merely pointing out a typo in "expeted".
Looking at it again, I'm not sure why retry attempts are tied to the voltage.
ChenYu
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
@ 2022-05-19 3:24 ` Chen-Yu Tsai
0 siblings, 0 replies; 30+ messages in thread
From: Chen-Yu Tsai @ 2022-05-19 3:24 UTC (permalink / raw)
To: Johnson Wang
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Wed, May 18, 2022 at 8:19 PM Johnson Wang <johnson.wang@mediatek.com> wrote:
>
> Hi Chen-Yu,
>
> On Fri, 2022-05-13 at 11:54 +0800, Chen-Yu Tsai wrote:
> > On Fri, May 13, 2022 at 11:31 AM Johnson Wang <
> > johnson.wang@mediatek.com> wrote:
> > >
> > > We introduce a devfreq driver for the MediaTek Cache Coherent
> > > Interconnect
> > > (CCI) used by some MediaTek SoCs.
> > >
> > > In this driver, we use the passive devfreq driver to get target
> > > frequencies
> > > and adjust voltages accordingly. In MT8183 and MT8186, the MediaTek
> > > CCI
> > > is supplied by the same regulators with the little core CPUs.
> > >
> > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> > > ---
> > > This patch depends on "devfreq-testing"[1].
> > > [1]
> > > https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing__;!!CTRNKA9wMg0ARbw!zzOSoso9udvDV3h6kYlmizFtbn3ACA5aS2jCAjKyvtu4z0fobv1mD5uF9YbPSme8l_NnR05unTxkZfDdzohu8asWZQ$
> > >
> > > ---
> > > drivers/devfreq/Kconfig | 10 +
> > > drivers/devfreq/Makefile | 1 +
> > > drivers/devfreq/mtk-cci-devfreq.c | 474
> > > ++++++++++++++++++++++++++++++
> > > 3 files changed, 485 insertions(+)
> > > create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
> > >
> > > diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> > > index 87eb2b837e68..9754d8b31621 100644
> > > --- a/drivers/devfreq/Kconfig
> > > +++ b/drivers/devfreq/Kconfig
> > > @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> > > It reads ACTMON counters of memory controllers and
> > > adjusts the
> > > operating frequencies and voltages with OPP support.
> > >
> > > +config ARM_MEDIATEK_CCI_DEVFREQ
> > > + tristate "MEDIATEK CCI DEVFREQ Driver"
> > > + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> > > + select DEVFREQ_GOV_PASSIVE
> > > + help
> > > + This adds a devfreq driver for MediaTek Cache Coherent
> > > Interconnect
> > > + which is shared the same regulators with the cpu cluster.
> > > It can track
> > > + buck voltages and update a proper CCI frequency. Use the
> > > notification
> > > + to get the regulator status.
> > > +
> > > config ARM_RK3399_DMC_DEVFREQ
> > > tristate "ARM RK3399 DMC DEVFREQ Driver"
> > > depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> > > diff --git a/drivers/devfreq/Makefile b/drivers/devfreq/Makefile
> > > index 0b6be92a25d9..bf40d04928d0 100644
> > > --- a/drivers/devfreq/Makefile
> > > +++ b/drivers/devfreq/Makefile
> > > @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=
> > > governor_passive.o
> > > obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> > > obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> > > obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> > > +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> > > obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> > > obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-mbus.o
> > > obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-
> > > devfreq.o
> > > diff --git a/drivers/devfreq/mtk-cci-devfreq.c
> > > b/drivers/devfreq/mtk-cci-devfreq.c
> > > new file mode 100644
> > > index 000000000000..aa8c37eb4a06
> > > --- /dev/null
> > > +++ b/drivers/devfreq/mtk-cci-devfreq.c
> > > @@ -0,0 +1,474 @@
[...]
> > > + if (IS_ERR(drv->sram_reg))
> > > + drv->sram_reg = NULL;
> > > + else {
> > > + ret = regulator_enable(drv->sram_reg);
> > > + if (ret) {
> > > + dev_err(dev, "failed to enable sram
> > > regulator\n");
> > > + goto out_free_resources;
> > > + }
> > > + }
> > > +
> > > + /*
> > > + * We assume min voltage is 0 and tracking target voltage
> > > using
> > > + * min_volt_shift for each iteration.
> > > + * The retry_max is 3 times of expeted iteration count.
> >
> > expected?
> >
> Maybe "the maximum" will be more appropriate?
I was merely pointing out a typo in "expeted".
Looking at it again, I'm not sure why retry attempts are tied to the voltage.
ChenYu
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 1/2] dt-bindings: interconnect: Add MediaTek CCI dt-bindings
2022-05-13 3:35 ` Chen-Yu Tsai
(?)
@ 2022-05-20 9:40 ` Johnson Wang
-1 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-20 9:40 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Fri, 2022-05-13 at 11:35 +0800, Chen-Yu Tsai wrote:
> On Fri, May 13, 2022 at 11:31 AM Johnson Wang <
> johnson.wang@mediatek.com> wrote:
> >
> > Add devicetree binding of MediaTek CCI on MT8183 and MT8186.
> >
> > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> > ---
> > .../bindings/interconnect/mediatek,cci.yaml | 140
> > ++++++++++++++++++
> > MAINTAINERS | 1 +
> > 2 files changed, 141 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> > b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> > new file mode 100644
> > index 000000000000..034c3b38ca3d
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> > @@ -0,0 +1,140 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/interconnect/mediatek,cci.yaml*__;Iw!!CTRNKA9wMg0ARbw!0vYE2yw5meNp-VKz6-Xp4C_qT8rz0tpzc0iPAGI__dVczbtBVpOcQfxdrQADjIdqtgDrrni0ZKWuBFP1QcwD0mHhOw$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!0vYE2yw5meNp-VKz6-Xp4C_qT8rz0tpzc0iPAGI__dVczbtBVpOcQfxdrQADjIdqtgDrrni0ZKWuBFP1QcxLQ8hn_A$
> >
> > +
> > +title: MediaTek Cache Coherent Interconnect (CCI) frequency and
> > voltage scaling
> > +
> > +maintainers:
> > + - Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > + - Johnson Wang <johnson.wang@mediatek.com>
> > +
> > +description: |
> > + MediaTek Cache Coherent Interconnect (CCI) is a hardware engine
> > used by
> > + MT8183 and MT8186 SoCs to scale the frequency and adjust the
> > voltage in
> > + hardware. It can also optimize the voltage to reduce the power
> > consumption.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - mediatek,mt8183-cci
> > + - mediatek,mt8186-cci
> > +
> > + clocks:
> > + items:
> > + - description:
> > + The multiplexer for clock input of the bus.
> > + - description:
> > + A parent of "cpu" clock which is used as an intermediate
> > clock source
>
> Replace "cpu" with "bus"?
>
> > + when the original CPU is under transition and not stable
> > yet.
>
>
> And also, "when the original clock source (PLL) is under transition
> ..."
>
> Otherwise,
>
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Hi Chen-Yu,
I will modify them in the next version.
BRs,
Johnson Wang
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 1/2] dt-bindings: interconnect: Add MediaTek CCI dt-bindings
@ 2022-05-20 9:40 ` Johnson Wang
0 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-20 9:40 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Fri, 2022-05-13 at 11:35 +0800, Chen-Yu Tsai wrote:
> On Fri, May 13, 2022 at 11:31 AM Johnson Wang <
> johnson.wang@mediatek.com> wrote:
> >
> > Add devicetree binding of MediaTek CCI on MT8183 and MT8186.
> >
> > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> > ---
> > .../bindings/interconnect/mediatek,cci.yaml | 140
> > ++++++++++++++++++
> > MAINTAINERS | 1 +
> > 2 files changed, 141 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> > b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> > new file mode 100644
> > index 000000000000..034c3b38ca3d
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> > @@ -0,0 +1,140 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/interconnect/mediatek,cci.yaml*__;Iw!!CTRNKA9wMg0ARbw!0vYE2yw5meNp-VKz6-Xp4C_qT8rz0tpzc0iPAGI__dVczbtBVpOcQfxdrQADjIdqtgDrrni0ZKWuBFP1QcwD0mHhOw$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!0vYE2yw5meNp-VKz6-Xp4C_qT8rz0tpzc0iPAGI__dVczbtBVpOcQfxdrQADjIdqtgDrrni0ZKWuBFP1QcxLQ8hn_A$
> >
> > +
> > +title: MediaTek Cache Coherent Interconnect (CCI) frequency and
> > voltage scaling
> > +
> > +maintainers:
> > + - Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > + - Johnson Wang <johnson.wang@mediatek.com>
> > +
> > +description: |
> > + MediaTek Cache Coherent Interconnect (CCI) is a hardware engine
> > used by
> > + MT8183 and MT8186 SoCs to scale the frequency and adjust the
> > voltage in
> > + hardware. It can also optimize the voltage to reduce the power
> > consumption.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - mediatek,mt8183-cci
> > + - mediatek,mt8186-cci
> > +
> > + clocks:
> > + items:
> > + - description:
> > + The multiplexer for clock input of the bus.
> > + - description:
> > + A parent of "cpu" clock which is used as an intermediate
> > clock source
>
> Replace "cpu" with "bus"?
>
> > + when the original CPU is under transition and not stable
> > yet.
>
>
> And also, "when the original clock source (PLL) is under transition
> ..."
>
> Otherwise,
>
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Hi Chen-Yu,
I will modify them in the next version.
BRs,
Johnson Wang
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 1/2] dt-bindings: interconnect: Add MediaTek CCI dt-bindings
@ 2022-05-20 9:40 ` Johnson Wang
0 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-20 9:40 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Fri, 2022-05-13 at 11:35 +0800, Chen-Yu Tsai wrote:
> On Fri, May 13, 2022 at 11:31 AM Johnson Wang <
> johnson.wang@mediatek.com> wrote:
> >
> > Add devicetree binding of MediaTek CCI on MT8183 and MT8186.
> >
> > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > Reviewed-by: Krzysztof Kozlowski <krzysztof.kozlowski@linaro.org>
> > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> > ---
> > .../bindings/interconnect/mediatek,cci.yaml | 140
> > ++++++++++++++++++
> > MAINTAINERS | 1 +
> > 2 files changed, 141 insertions(+)
> > create mode 100644
> > Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> >
> > diff --git
> > a/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> > b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> > new file mode 100644
> > index 000000000000..034c3b38ca3d
> > --- /dev/null
> > +++
> > b/Documentation/devicetree/bindings/interconnect/mediatek,cci.yaml
> > @@ -0,0 +1,140 @@
> > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > +%YAML 1.2
> > +---
> > +$id:
> > https://urldefense.com/v3/__http://devicetree.org/schemas/interconnect/mediatek,cci.yaml*__;Iw!!CTRNKA9wMg0ARbw!0vYE2yw5meNp-VKz6-Xp4C_qT8rz0tpzc0iPAGI__dVczbtBVpOcQfxdrQADjIdqtgDrrni0ZKWuBFP1QcwD0mHhOw$
> >
> > +$schema:
> > https://urldefense.com/v3/__http://devicetree.org/meta-schemas/core.yaml*__;Iw!!CTRNKA9wMg0ARbw!0vYE2yw5meNp-VKz6-Xp4C_qT8rz0tpzc0iPAGI__dVczbtBVpOcQfxdrQADjIdqtgDrrni0ZKWuBFP1QcxLQ8hn_A$
> >
> > +
> > +title: MediaTek Cache Coherent Interconnect (CCI) frequency and
> > voltage scaling
> > +
> > +maintainers:
> > + - Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > + - Johnson Wang <johnson.wang@mediatek.com>
> > +
> > +description: |
> > + MediaTek Cache Coherent Interconnect (CCI) is a hardware engine
> > used by
> > + MT8183 and MT8186 SoCs to scale the frequency and adjust the
> > voltage in
> > + hardware. It can also optimize the voltage to reduce the power
> > consumption.
> > +
> > +properties:
> > + compatible:
> > + enum:
> > + - mediatek,mt8183-cci
> > + - mediatek,mt8186-cci
> > +
> > + clocks:
> > + items:
> > + - description:
> > + The multiplexer for clock input of the bus.
> > + - description:
> > + A parent of "cpu" clock which is used as an intermediate
> > clock source
>
> Replace "cpu" with "bus"?
>
> > + when the original CPU is under transition and not stable
> > yet.
>
>
> And also, "when the original clock source (PLL) is under transition
> ..."
>
> Otherwise,
>
> Reviewed-by: Chen-Yu Tsai <wenst@chromium.org>
Hi Chen-Yu,
I will modify them in the next version.
BRs,
Johnson Wang
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
2022-05-19 3:24 ` Chen-Yu Tsai
(?)
@ 2022-05-20 9:41 ` Johnson Wang
-1 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-20 9:41 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-05-19 at 11:24 +0800, Chen-Yu Tsai wrote:
> On Wed, May 18, 2022 at 8:19 PM Johnson Wang <
> johnson.wang@mediatek.com> wrote:
> >
> > Hi Chen-Yu,
> >
> > On Fri, 2022-05-13 at 11:54 +0800, Chen-Yu Tsai wrote:
> > > On Fri, May 13, 2022 at 11:31 AM Johnson Wang <
> > > johnson.wang@mediatek.com> wrote:
> > > >
> > > > We introduce a devfreq driver for the MediaTek Cache Coherent
> > > > Interconnect
> > > > (CCI) used by some MediaTek SoCs.
> > > >
> > > > In this driver, we use the passive devfreq driver to get target
> > > > frequencies
> > > > and adjust voltages accordingly. In MT8183 and MT8186, the
> > > > MediaTek
> > > > CCI
> > > > is supplied by the same regulators with the little core CPUs.
> > > >
> > > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > > > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> > > > ---
> > > > This patch depends on "devfreq-testing"[1].
> > > > [1]
> > > >
https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing__;!!CTRNKA9wMg0ARbw!zzOSoso9udvDV3h6kYlmizFtbn3ACA5aS2jCAjKyvtu4z0fobv1mD5uF9YbPSme8l_NnR05unTxkZfDdzohu8asWZQ$
> > > >
> > > > ---
> > > > drivers/devfreq/Kconfig | 10 +
> > > > drivers/devfreq/Makefile | 1 +
> > > > drivers/devfreq/mtk-cci-devfreq.c | 474
> > > > ++++++++++++++++++++++++++++++
> > > > 3 files changed, 485 insertions(+)
> > > > create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
> > > >
> > > > diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> > > > index 87eb2b837e68..9754d8b31621 100644
> > > > --- a/drivers/devfreq/Kconfig
> > > > +++ b/drivers/devfreq/Kconfig
> > > > @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> > > > It reads ACTMON counters of memory controllers and
> > > > adjusts the
> > > > operating frequencies and voltages with OPP support.
> > > >
> > > > +config ARM_MEDIATEK_CCI_DEVFREQ
> > > > + tristate "MEDIATEK CCI DEVFREQ Driver"
> > > > + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> > > > + select DEVFREQ_GOV_PASSIVE
> > > > + help
> > > > + This adds a devfreq driver for MediaTek Cache
> > > > Coherent
> > > > Interconnect
> > > > + which is shared the same regulators with the cpu
> > > > cluster.
> > > > It can track
> > > > + buck voltages and update a proper CCI frequency. Use
> > > > the
> > > > notification
> > > > + to get the regulator status.
> > > > +
> > > > config ARM_RK3399_DMC_DEVFREQ
> > > > tristate "ARM RK3399 DMC DEVFREQ Driver"
> > > > depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> > > > diff --git a/drivers/devfreq/Makefile
> > > > b/drivers/devfreq/Makefile
> > > > index 0b6be92a25d9..bf40d04928d0 100644
> > > > --- a/drivers/devfreq/Makefile
> > > > +++ b/drivers/devfreq/Makefile
> > > > @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=
> > > > governor_passive.o
> > > > obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> > > > obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> > > > obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> > > > +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> > > > obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> > > > obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-
> > > > mbus.o
> > > > obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-
> > > > devfreq.o
> > > > diff --git a/drivers/devfreq/mtk-cci-devfreq.c
> > > > b/drivers/devfreq/mtk-cci-devfreq.c
> > > > new file mode 100644
> > > > index 000000000000..aa8c37eb4a06
> > > > --- /dev/null
> > > > +++ b/drivers/devfreq/mtk-cci-devfreq.c
> > > > @@ -0,0 +1,474 @@
>
> [...]
>
> > > > + if (IS_ERR(drv->sram_reg))
> > > > + drv->sram_reg = NULL;
> > > > + else {
> > > > + ret = regulator_enable(drv->sram_reg);
> > > > + if (ret) {
> > > > + dev_err(dev, "failed to enable sram
> > > > regulator\n");
> > > > + goto out_free_resources;
> > > > + }
> > > > + }
> > > > +
> > > > + /*
> > > > + * We assume min voltage is 0 and tracking target
> > > > voltage
> > > > using
> > > > + * min_volt_shift for each iteration.
> > > > + * The retry_max is 3 times of expeted iteration count.
> > >
> > > expected?
> > >
> >
> > Maybe "the maximum" will be more appropriate?
>
>
> I was merely pointing out a typo in "expeted".
>
> Looking at it again, I'm not sure why retry attempts are tied to the
> voltage.
>
>
> ChenYu
Hi Chen-Yu,
Thanks for you reminder.
Whenever the voltages are scaled up/down one step,
meaning that there is another iteration in the while loop.
Thus, our thought is to use times of the voltages step up/down to set
iteration limit.
BRs,
Johnson Wang
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
@ 2022-05-20 9:41 ` Johnson Wang
0 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-20 9:41 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-05-19 at 11:24 +0800, Chen-Yu Tsai wrote:
> On Wed, May 18, 2022 at 8:19 PM Johnson Wang <
> johnson.wang@mediatek.com> wrote:
> >
> > Hi Chen-Yu,
> >
> > On Fri, 2022-05-13 at 11:54 +0800, Chen-Yu Tsai wrote:
> > > On Fri, May 13, 2022 at 11:31 AM Johnson Wang <
> > > johnson.wang@mediatek.com> wrote:
> > > >
> > > > We introduce a devfreq driver for the MediaTek Cache Coherent
> > > > Interconnect
> > > > (CCI) used by some MediaTek SoCs.
> > > >
> > > > In this driver, we use the passive devfreq driver to get target
> > > > frequencies
> > > > and adjust voltages accordingly. In MT8183 and MT8186, the
> > > > MediaTek
> > > > CCI
> > > > is supplied by the same regulators with the little core CPUs.
> > > >
> > > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > > > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> > > > ---
> > > > This patch depends on "devfreq-testing"[1].
> > > > [1]
> > > >
https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing__;!!CTRNKA9wMg0ARbw!zzOSoso9udvDV3h6kYlmizFtbn3ACA5aS2jCAjKyvtu4z0fobv1mD5uF9YbPSme8l_NnR05unTxkZfDdzohu8asWZQ$
> > > >
> > > > ---
> > > > drivers/devfreq/Kconfig | 10 +
> > > > drivers/devfreq/Makefile | 1 +
> > > > drivers/devfreq/mtk-cci-devfreq.c | 474
> > > > ++++++++++++++++++++++++++++++
> > > > 3 files changed, 485 insertions(+)
> > > > create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
> > > >
> > > > diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> > > > index 87eb2b837e68..9754d8b31621 100644
> > > > --- a/drivers/devfreq/Kconfig
> > > > +++ b/drivers/devfreq/Kconfig
> > > > @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> > > > It reads ACTMON counters of memory controllers and
> > > > adjusts the
> > > > operating frequencies and voltages with OPP support.
> > > >
> > > > +config ARM_MEDIATEK_CCI_DEVFREQ
> > > > + tristate "MEDIATEK CCI DEVFREQ Driver"
> > > > + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> > > > + select DEVFREQ_GOV_PASSIVE
> > > > + help
> > > > + This adds a devfreq driver for MediaTek Cache
> > > > Coherent
> > > > Interconnect
> > > > + which is shared the same regulators with the cpu
> > > > cluster.
> > > > It can track
> > > > + buck voltages and update a proper CCI frequency. Use
> > > > the
> > > > notification
> > > > + to get the regulator status.
> > > > +
> > > > config ARM_RK3399_DMC_DEVFREQ
> > > > tristate "ARM RK3399 DMC DEVFREQ Driver"
> > > > depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> > > > diff --git a/drivers/devfreq/Makefile
> > > > b/drivers/devfreq/Makefile
> > > > index 0b6be92a25d9..bf40d04928d0 100644
> > > > --- a/drivers/devfreq/Makefile
> > > > +++ b/drivers/devfreq/Makefile
> > > > @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=
> > > > governor_passive.o
> > > > obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> > > > obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> > > > obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> > > > +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> > > > obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> > > > obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-
> > > > mbus.o
> > > > obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-
> > > > devfreq.o
> > > > diff --git a/drivers/devfreq/mtk-cci-devfreq.c
> > > > b/drivers/devfreq/mtk-cci-devfreq.c
> > > > new file mode 100644
> > > > index 000000000000..aa8c37eb4a06
> > > > --- /dev/null
> > > > +++ b/drivers/devfreq/mtk-cci-devfreq.c
> > > > @@ -0,0 +1,474 @@
>
> [...]
>
> > > > + if (IS_ERR(drv->sram_reg))
> > > > + drv->sram_reg = NULL;
> > > > + else {
> > > > + ret = regulator_enable(drv->sram_reg);
> > > > + if (ret) {
> > > > + dev_err(dev, "failed to enable sram
> > > > regulator\n");
> > > > + goto out_free_resources;
> > > > + }
> > > > + }
> > > > +
> > > > + /*
> > > > + * We assume min voltage is 0 and tracking target
> > > > voltage
> > > > using
> > > > + * min_volt_shift for each iteration.
> > > > + * The retry_max is 3 times of expeted iteration count.
> > >
> > > expected?
> > >
> >
> > Maybe "the maximum" will be more appropriate?
>
>
> I was merely pointing out a typo in "expeted".
>
> Looking at it again, I'm not sure why retry attempts are tied to the
> voltage.
>
>
> ChenYu
Hi Chen-Yu,
Thanks for you reminder.
Whenever the voltages are scaled up/down one step,
meaning that there is another iteration in the while loop.
Thus, our thought is to use times of the voltages step up/down to set
iteration limit.
BRs,
Johnson Wang
_______________________________________________
Linux-mediatek mailing list
Linux-mediatek@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-mediatek
^ permalink raw reply [flat|nested] 30+ messages in thread
* Re: [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver
@ 2022-05-20 9:41 ` Johnson Wang
0 siblings, 0 replies; 30+ messages in thread
From: Johnson Wang @ 2022-05-20 9:41 UTC (permalink / raw)
To: Chen-Yu Tsai
Cc: cw00.choi, krzk+dt, robh+dt, kyungmin.park, djakov, khilman,
linux-pm, linux-kernel, devicetree, linux-arm-kernel,
linux-mediatek, jia-wei.chang,
Project_Global_Chrome_Upstream_Group
On Thu, 2022-05-19 at 11:24 +0800, Chen-Yu Tsai wrote:
> On Wed, May 18, 2022 at 8:19 PM Johnson Wang <
> johnson.wang@mediatek.com> wrote:
> >
> > Hi Chen-Yu,
> >
> > On Fri, 2022-05-13 at 11:54 +0800, Chen-Yu Tsai wrote:
> > > On Fri, May 13, 2022 at 11:31 AM Johnson Wang <
> > > johnson.wang@mediatek.com> wrote:
> > > >
> > > > We introduce a devfreq driver for the MediaTek Cache Coherent
> > > > Interconnect
> > > > (CCI) used by some MediaTek SoCs.
> > > >
> > > > In this driver, we use the passive devfreq driver to get target
> > > > frequencies
> > > > and adjust voltages accordingly. In MT8183 and MT8186, the
> > > > MediaTek
> > > > CCI
> > > > is supplied by the same regulators with the little core CPUs.
> > > >
> > > > Signed-off-by: Jia-Wei Chang <jia-wei.chang@mediatek.com>
> > > > Signed-off-by: Johnson Wang <johnson.wang@mediatek.com>
> > > > Acked-by: Chanwoo Choi <cw00.choi@samsung.com>
> > > > ---
> > > > This patch depends on "devfreq-testing"[1].
> > > > [1]
> > > >
https://urldefense.com/v3/__https://git.kernel.org/pub/scm/linux/kernel/git/chanwoo/linux.git/log/?h=devfreq-testing__;!!CTRNKA9wMg0ARbw!zzOSoso9udvDV3h6kYlmizFtbn3ACA5aS2jCAjKyvtu4z0fobv1mD5uF9YbPSme8l_NnR05unTxkZfDdzohu8asWZQ$
> > > >
> > > > ---
> > > > drivers/devfreq/Kconfig | 10 +
> > > > drivers/devfreq/Makefile | 1 +
> > > > drivers/devfreq/mtk-cci-devfreq.c | 474
> > > > ++++++++++++++++++++++++++++++
> > > > 3 files changed, 485 insertions(+)
> > > > create mode 100644 drivers/devfreq/mtk-cci-devfreq.c
> > > >
> > > > diff --git a/drivers/devfreq/Kconfig b/drivers/devfreq/Kconfig
> > > > index 87eb2b837e68..9754d8b31621 100644
> > > > --- a/drivers/devfreq/Kconfig
> > > > +++ b/drivers/devfreq/Kconfig
> > > > @@ -120,6 +120,16 @@ config ARM_TEGRA_DEVFREQ
> > > > It reads ACTMON counters of memory controllers and
> > > > adjusts the
> > > > operating frequencies and voltages with OPP support.
> > > >
> > > > +config ARM_MEDIATEK_CCI_DEVFREQ
> > > > + tristate "MEDIATEK CCI DEVFREQ Driver"
> > > > + depends on ARM_MEDIATEK_CPUFREQ || COMPILE_TEST
> > > > + select DEVFREQ_GOV_PASSIVE
> > > > + help
> > > > + This adds a devfreq driver for MediaTek Cache
> > > > Coherent
> > > > Interconnect
> > > > + which is shared the same regulators with the cpu
> > > > cluster.
> > > > It can track
> > > > + buck voltages and update a proper CCI frequency. Use
> > > > the
> > > > notification
> > > > + to get the regulator status.
> > > > +
> > > > config ARM_RK3399_DMC_DEVFREQ
> > > > tristate "ARM RK3399 DMC DEVFREQ Driver"
> > > > depends on (ARCH_ROCKCHIP && HAVE_ARM_SMCCC) || \
> > > > diff --git a/drivers/devfreq/Makefile
> > > > b/drivers/devfreq/Makefile
> > > > index 0b6be92a25d9..bf40d04928d0 100644
> > > > --- a/drivers/devfreq/Makefile
> > > > +++ b/drivers/devfreq/Makefile
> > > > @@ -11,6 +11,7 @@ obj-$(CONFIG_DEVFREQ_GOV_PASSIVE) +=
> > > > governor_passive.o
> > > > obj-$(CONFIG_ARM_EXYNOS_BUS_DEVFREQ) += exynos-bus.o
> > > > obj-$(CONFIG_ARM_IMX_BUS_DEVFREQ) += imx-bus.o
> > > > obj-$(CONFIG_ARM_IMX8M_DDRC_DEVFREQ) += imx8m-ddrc.o
> > > > +obj-$(CONFIG_ARM_MEDIATEK_CCI_DEVFREQ) += mtk-cci-devfreq.o
> > > > obj-$(CONFIG_ARM_RK3399_DMC_DEVFREQ) += rk3399_dmc.o
> > > > obj-$(CONFIG_ARM_SUN8I_A33_MBUS_DEVFREQ) += sun8i-a33-
> > > > mbus.o
> > > > obj-$(CONFIG_ARM_TEGRA_DEVFREQ) += tegra30-
> > > > devfreq.o
> > > > diff --git a/drivers/devfreq/mtk-cci-devfreq.c
> > > > b/drivers/devfreq/mtk-cci-devfreq.c
> > > > new file mode 100644
> > > > index 000000000000..aa8c37eb4a06
> > > > --- /dev/null
> > > > +++ b/drivers/devfreq/mtk-cci-devfreq.c
> > > > @@ -0,0 +1,474 @@
>
> [...]
>
> > > > + if (IS_ERR(drv->sram_reg))
> > > > + drv->sram_reg = NULL;
> > > > + else {
> > > > + ret = regulator_enable(drv->sram_reg);
> > > > + if (ret) {
> > > > + dev_err(dev, "failed to enable sram
> > > > regulator\n");
> > > > + goto out_free_resources;
> > > > + }
> > > > + }
> > > > +
> > > > + /*
> > > > + * We assume min voltage is 0 and tracking target
> > > > voltage
> > > > using
> > > > + * min_volt_shift for each iteration.
> > > > + * The retry_max is 3 times of expeted iteration count.
> > >
> > > expected?
> > >
> >
> > Maybe "the maximum" will be more appropriate?
>
>
> I was merely pointing out a typo in "expeted".
>
> Looking at it again, I'm not sure why retry attempts are tied to the
> voltage.
>
>
> ChenYu
Hi Chen-Yu,
Thanks for you reminder.
Whenever the voltages are scaled up/down one step,
meaning that there is another iteration in the while loop.
Thus, our thought is to use times of the voltages step up/down to set
iteration limit.
BRs,
Johnson Wang
_______________________________________________
linux-arm-kernel mailing list
linux-arm-kernel@lists.infradead.org
http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
^ permalink raw reply [flat|nested] 30+ messages in thread
end of thread, other threads:[~2022-05-20 11:02 UTC | newest]
Thread overview: 30+ messages (download: mbox.gz / follow: Atom feed)
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2022-05-13 3:28 [RESEND v4 0/2] Introduce MediaTek CCI devfreq driver Johnson Wang
2022-05-13 3:28 ` Johnson Wang
2022-05-13 3:28 ` Johnson Wang
2022-05-13 3:28 ` [RESEND v4 1/2] dt-bindings: interconnect: Add MediaTek CCI dt-bindings Johnson Wang
2022-05-13 3:28 ` Johnson Wang
2022-05-13 3:28 ` Johnson Wang
2022-05-13 3:35 ` Chen-Yu Tsai
2022-05-13 3:35 ` Chen-Yu Tsai
2022-05-13 3:35 ` Chen-Yu Tsai
2022-05-20 9:40 ` Johnson Wang
2022-05-20 9:40 ` Johnson Wang
2022-05-20 9:40 ` Johnson Wang
2022-05-13 3:28 ` [RESEND v4 2/2] PM / devfreq: mediatek: Introduce MediaTek CCI devfreq driver Johnson Wang
2022-05-13 3:28 ` Johnson Wang
2022-05-13 3:28 ` Johnson Wang
2022-05-13 3:54 ` Chen-Yu Tsai
2022-05-13 3:54 ` Chen-Yu Tsai
2022-05-13 3:54 ` Chen-Yu Tsai
2022-05-18 12:19 ` Johnson Wang
2022-05-18 12:19 ` Johnson Wang
2022-05-18 12:19 ` Johnson Wang
2022-05-19 3:24 ` Chen-Yu Tsai
2022-05-19 3:24 ` Chen-Yu Tsai
2022-05-19 3:24 ` Chen-Yu Tsai
2022-05-20 9:41 ` Johnson Wang
2022-05-20 9:41 ` Johnson Wang
2022-05-20 9:41 ` Johnson Wang
2022-05-13 4:39 ` Rex-BC Chen
2022-05-13 4:39 ` Rex-BC Chen
2022-05-13 4:39 ` Rex-BC Chen
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