* [PULL 0/4] OpenRISC fixes for QEMU 2022-05-15
@ 2022-05-15 1:39 ` Stafford Horne
0 siblings, 0 replies; 14+ messages in thread
From: Stafford Horne @ 2022-05-15 1:39 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Jason A. Donenfeld, Stafford Horne
The following changes since commit 2e3408b3cc7de4e87a9adafc8c19bfce3abec947:
Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into staging (2022-05-03 09:13:17 -0700)
are available in the Git repository at:
https://github.com/stffrdhrn/qemu.git tags/or1k-pull-request-20220515
for you to fetch changes up to e8f0ab0cd674241cbab7231ce05ac1bfa0b4f5ed:
target/openrisc: Do not reset delay slot flag on early tb exit (2022-05-15 10:33:01 +0900)
----------------------------------------------------------------
OpenRISC Fixes for 7.0
- A few or1ksim fixes and enhancements
- A fix for OpenRISC tcg backend around delay slot handling
----------------------------------------------------------------
Jason A. Donenfeld (3):
hw/openrisc: page-align FDT address
hw/openrisc: support 4 serial ports in or1ksim
hw/openrisc: use right OMPIC size variable
Stafford Horne (1):
target/openrisc: Do not reset delay slot flag on early tb exit
hw/openrisc/openrisc_sim.c | 28 +++++++++++++++++++---------
target/openrisc/cpu.c | 11 +++++++++++
2 files changed, 30 insertions(+), 9 deletions(-)
Jason A. Donenfeld (3):
hw/openrisc: page-align FDT address
hw/openrisc: support 4 serial ports in or1ksim
hw/openrisc: use right OMPIC size variable
Stafford Horne (1):
target/openrisc: Do not reset delay slot flag on early tb exit
hw/openrisc/openrisc_sim.c | 28 +++++++++++++++++++---------
target/openrisc/cpu.c | 11 +++++++++++
2 files changed, 30 insertions(+), 9 deletions(-)
--
2.31.1
^ permalink raw reply [flat|nested] 14+ messages in thread* [PULL 1/4] hw/openrisc: page-align FDT address
2022-05-15 1:39 ` Stafford Horne
@ 2022-05-15 1:39 ` Stafford Horne
-1 siblings, 0 replies; 14+ messages in thread
From: Stafford Horne @ 2022-05-15 1:39 UTC (permalink / raw)
To: QEMU Development; +Cc: Peter Maydell, Jason A. Donenfeld, Openrisc, Jia Liu
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
The QEMU-provided FDT was only being recognized by the kernel when it
was used in conjunction with -initrd. Without it, the magic bytes
wouldn't be there and the kernel couldn't load it. This patch fixes the
issue by page aligning the provided FDT.
Cc: Stafford Horne <shorne@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/openrisc_sim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 8184caa60b..99b14940f4 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -356,7 +356,7 @@ static uint32_t openrisc_load_fdt(Or1ksimState *state, hwaddr load_start,
}
/* We put fdt right after the kernel and/or initrd. */
- fdt_addr = ROUND_UP(load_start, 4);
+ fdt_addr = TARGET_PAGE_ALIGN(load_start);
ret = fdt_pack(fdt);
/* Should only fail if we've built a corrupted tree */
--
2.31.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 1/4] hw/openrisc: page-align FDT address
@ 2022-05-15 1:39 ` Stafford Horne
0 siblings, 0 replies; 14+ messages in thread
From: Stafford Horne @ 2022-05-15 1:39 UTC (permalink / raw)
To: QEMU Development
Cc: Openrisc, Jason A. Donenfeld, Stafford Horne, Peter Maydell, Jia Liu
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
The QEMU-provided FDT was only being recognized by the kernel when it
was used in conjunction with -initrd. Without it, the magic bytes
wouldn't be there and the kernel couldn't load it. This patch fixes the
issue by page aligning the provided FDT.
Cc: Stafford Horne <shorne@gmail.com>
Cc: Peter Maydell <peter.maydell@linaro.org>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/openrisc_sim.c | 2 +-
1 file changed, 1 insertion(+), 1 deletion(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 8184caa60b..99b14940f4 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -356,7 +356,7 @@ static uint32_t openrisc_load_fdt(Or1ksimState *state, hwaddr load_start,
}
/* We put fdt right after the kernel and/or initrd. */
- fdt_addr = ROUND_UP(load_start, 4);
+ fdt_addr = TARGET_PAGE_ALIGN(load_start);
ret = fdt_pack(fdt);
/* Should only fail if we've built a corrupted tree */
--
2.31.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PULL 2/4] hw/openrisc: support 4 serial ports in or1ksim
2022-05-15 1:39 ` Stafford Horne
@ 2022-05-15 1:39 ` Stafford Horne
-1 siblings, 0 replies; 14+ messages in thread
From: Stafford Horne @ 2022-05-15 1:39 UTC (permalink / raw)
To: QEMU Development; +Cc: Jason A. Donenfeld, Openrisc, Jia Liu
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
The 8250 serial controller supports 4 serial ports, so wire them all up,
so that we can have more than one basic I/O channel.
Cc: Stafford Horne <shorne@gmail.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
[smh:Fixup indentation and lines over 80 chars]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/openrisc_sim.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 99b14940f4..6873124f74 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -71,6 +71,10 @@ enum {
OR1KSIM_ETHOC_IRQ = 4,
};
+enum {
+ OR1KSIM_UART_COUNT = 4
+};
+
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
@@ -239,11 +243,13 @@ static void openrisc_sim_ompic_init(Or1ksimState *state, hwaddr base,
static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
hwaddr size, int num_cpus,
- OpenRISCCPU *cpus[], int irq_pin)
+ OpenRISCCPU *cpus[], int irq_pin,
+ int uart_idx)
{
void *fdt = state->fdt;
char *nodename;
qemu_irq serial_irq;
+ char alias[sizeof("uart0")];
int i;
if (num_cpus > 1) {
@@ -258,7 +264,8 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
serial_irq = get_cpu_irq(cpus, 0, irq_pin);
}
serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
- serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1),
+ DEVICE_NATIVE_ENDIAN);
/* Add device tree node for serial. */
nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);
@@ -271,7 +278,8 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
/* The /chosen node is created during fdt creation. */
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
- qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename);
+ snprintf(alias, sizeof(alias), "uart%d", uart_idx);
+ qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename);
g_free(nodename);
}
@@ -414,9 +422,11 @@ static void openrisc_sim_init(MachineState *machine)
smp_cpus, cpus, OR1KSIM_OMPIC_IRQ);
}
- openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base,
- or1ksim_memmap[OR1KSIM_UART].size, smp_cpus, cpus,
- OR1KSIM_UART_IRQ);
+ for (n = 0; n < OR1KSIM_UART_COUNT; ++n)
+ openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base +
+ or1ksim_memmap[OR1KSIM_UART].size * n,
+ or1ksim_memmap[OR1KSIM_UART].size,
+ smp_cpus, cpus, OR1KSIM_UART_IRQ, n);
load_addr = openrisc_load_kernel(ram_size, kernel_filename);
if (load_addr > 0) {
--
2.31.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 2/4] hw/openrisc: support 4 serial ports in or1ksim
@ 2022-05-15 1:39 ` Stafford Horne
0 siblings, 0 replies; 14+ messages in thread
From: Stafford Horne @ 2022-05-15 1:39 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Jason A. Donenfeld, Stafford Horne, Jia Liu
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
The 8250 serial controller supports 4 serial ports, so wire them all up,
so that we can have more than one basic I/O channel.
Cc: Stafford Horne <shorne@gmail.com>
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
[smh:Fixup indentation and lines over 80 chars]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/openrisc_sim.c | 22 ++++++++++++++++------
1 file changed, 16 insertions(+), 6 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 99b14940f4..6873124f74 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -71,6 +71,10 @@ enum {
OR1KSIM_ETHOC_IRQ = 4,
};
+enum {
+ OR1KSIM_UART_COUNT = 4
+};
+
static const struct MemmapEntry {
hwaddr base;
hwaddr size;
@@ -239,11 +243,13 @@ static void openrisc_sim_ompic_init(Or1ksimState *state, hwaddr base,
static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
hwaddr size, int num_cpus,
- OpenRISCCPU *cpus[], int irq_pin)
+ OpenRISCCPU *cpus[], int irq_pin,
+ int uart_idx)
{
void *fdt = state->fdt;
char *nodename;
qemu_irq serial_irq;
+ char alias[sizeof("uart0")];
int i;
if (num_cpus > 1) {
@@ -258,7 +264,8 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
serial_irq = get_cpu_irq(cpus, 0, irq_pin);
}
serial_mm_init(get_system_memory(), base, 0, serial_irq, 115200,
- serial_hd(0), DEVICE_NATIVE_ENDIAN);
+ serial_hd(OR1KSIM_UART_COUNT - uart_idx - 1),
+ DEVICE_NATIVE_ENDIAN);
/* Add device tree node for serial. */
nodename = g_strdup_printf("/serial@%" HWADDR_PRIx, base);
@@ -271,7 +278,8 @@ static void openrisc_sim_serial_init(Or1ksimState *state, hwaddr base,
/* The /chosen node is created during fdt creation. */
qemu_fdt_setprop_string(fdt, "/chosen", "stdout-path", nodename);
- qemu_fdt_setprop_string(fdt, "/aliases", "uart0", nodename);
+ snprintf(alias, sizeof(alias), "uart%d", uart_idx);
+ qemu_fdt_setprop_string(fdt, "/aliases", alias, nodename);
g_free(nodename);
}
@@ -414,9 +422,11 @@ static void openrisc_sim_init(MachineState *machine)
smp_cpus, cpus, OR1KSIM_OMPIC_IRQ);
}
- openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base,
- or1ksim_memmap[OR1KSIM_UART].size, smp_cpus, cpus,
- OR1KSIM_UART_IRQ);
+ for (n = 0; n < OR1KSIM_UART_COUNT; ++n)
+ openrisc_sim_serial_init(state, or1ksim_memmap[OR1KSIM_UART].base +
+ or1ksim_memmap[OR1KSIM_UART].size * n,
+ or1ksim_memmap[OR1KSIM_UART].size,
+ smp_cpus, cpus, OR1KSIM_UART_IRQ, n);
load_addr = openrisc_load_kernel(ram_size, kernel_filename);
if (load_addr > 0) {
--
2.31.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PULL 3/4] hw/openrisc: use right OMPIC size variable
2022-05-15 1:39 ` Stafford Horne
@ 2022-05-15 1:39 ` Stafford Horne
-1 siblings, 0 replies; 14+ messages in thread
From: Stafford Horne @ 2022-05-15 1:39 UTC (permalink / raw)
To: QEMU Development; +Cc: Jason A. Donenfeld, Openrisc, Jia Liu
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
This appears to be a copy and paste error. The UART size was used
instead of the much smaller OMPIC size. But actually that smaller OMPIC
size is wrong too and doesn't allow the IPI to work in Linux. So set it
to the old value.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
[smh:Updated OR1KSIM_OMPIC size to use OR1KSIM_CPUS_MAX]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 6873124f74..35adce17ac 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -82,7 +82,7 @@ static const struct MemmapEntry {
[OR1KSIM_DRAM] = { 0x00000000, 0 },
[OR1KSIM_UART] = { 0x90000000, 0x100 },
[OR1KSIM_ETHOC] = { 0x92000000, 0x800 },
- [OR1KSIM_OMPIC] = { 0x98000000, 16 },
+ [OR1KSIM_OMPIC] = { 0x98000000, OR1KSIM_CPUS_MAX * 8 },
};
static struct openrisc_boot_info {
@@ -418,7 +418,7 @@ static void openrisc_sim_init(MachineState *machine)
if (smp_cpus > 1) {
openrisc_sim_ompic_init(state, or1ksim_memmap[OR1KSIM_OMPIC].base,
- or1ksim_memmap[OR1KSIM_UART].size,
+ or1ksim_memmap[OR1KSIM_OMPIC].size,
smp_cpus, cpus, OR1KSIM_OMPIC_IRQ);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 3/4] hw/openrisc: use right OMPIC size variable
@ 2022-05-15 1:39 ` Stafford Horne
0 siblings, 0 replies; 14+ messages in thread
From: Stafford Horne @ 2022-05-15 1:39 UTC (permalink / raw)
To: QEMU Development; +Cc: Openrisc, Jason A. Donenfeld, Stafford Horne, Jia Liu
From: "Jason A. Donenfeld" <Jason@zx2c4.com>
This appears to be a copy and paste error. The UART size was used
instead of the much smaller OMPIC size. But actually that smaller OMPIC
size is wrong too and doesn't allow the IPI to work in Linux. So set it
to the old value.
Signed-off-by: Jason A. Donenfeld <Jason@zx2c4.com>
[smh:Updated OR1KSIM_OMPIC size to use OR1KSIM_CPUS_MAX]
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
hw/openrisc/openrisc_sim.c | 4 ++--
1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/hw/openrisc/openrisc_sim.c b/hw/openrisc/openrisc_sim.c
index 6873124f74..35adce17ac 100644
--- a/hw/openrisc/openrisc_sim.c
+++ b/hw/openrisc/openrisc_sim.c
@@ -82,7 +82,7 @@ static const struct MemmapEntry {
[OR1KSIM_DRAM] = { 0x00000000, 0 },
[OR1KSIM_UART] = { 0x90000000, 0x100 },
[OR1KSIM_ETHOC] = { 0x92000000, 0x800 },
- [OR1KSIM_OMPIC] = { 0x98000000, 16 },
+ [OR1KSIM_OMPIC] = { 0x98000000, OR1KSIM_CPUS_MAX * 8 },
};
static struct openrisc_boot_info {
@@ -418,7 +418,7 @@ static void openrisc_sim_init(MachineState *machine)
if (smp_cpus > 1) {
openrisc_sim_ompic_init(state, or1ksim_memmap[OR1KSIM_OMPIC].base,
- or1ksim_memmap[OR1KSIM_UART].size,
+ or1ksim_memmap[OR1KSIM_OMPIC].size,
smp_cpus, cpus, OR1KSIM_OMPIC_IRQ);
}
--
2.31.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* [PULL 4/4] target/openrisc: Do not reset delay slot flag on early tb exit
2022-05-15 1:39 ` Stafford Horne
@ 2022-05-15 1:39 ` Stafford Horne
-1 siblings, 0 replies; 14+ messages in thread
From: Stafford Horne @ 2022-05-15 1:39 UTC (permalink / raw)
To: QEMU Development; +Cc: Jason A. Donenfeld, Openrisc, Richard Henderson
This was found when running linux crypto algorithm selftests used by
wireguard. We found that randomly the tests would fail. We found
through investigation that a combination of a tick timer interrupt,
raised when executing a delay slot instruction at a page boundary caused
the issue.
This was caused when handling the TB_EXIT_REQUESTED case in cpu_tb_exec.
On OpenRISC, which doesn't implement synchronize_from_tb, set_pc was
being used as a fallback. The OpenRISC set_pc implementation clears
dflag, which caused the exception handling logic to not account for the
delay slot. This was the bug, because it meant when execution resumed
after the interrupt was handling it resumed in the wrong place.
Fix this by implementing synchronize_from_tb which simply updates pc,
and not clear the delay slot flag.
Reported-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/cpu.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index dfbafc5236..41d1b2a24a 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -21,6 +21,7 @@
#include "qapi/error.h"
#include "qemu/qemu-print.h"
#include "cpu.h"
+#include "exec/exec-all.h"
static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -30,6 +31,15 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.dflag = 0;
}
+static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
+ const TranslationBlock *tb)
+{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+
+ cpu->env.pc = tb->pc;
+}
+
+
static bool openrisc_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & (CPU_INTERRUPT_HARD |
@@ -186,6 +196,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
static const struct TCGCPUOps openrisc_tcg_ops = {
.initialize = openrisc_translate_init,
+ .synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
#ifndef CONFIG_USER_ONLY
.tlb_fill = openrisc_cpu_tlb_fill,
--
2.31.1
^ permalink raw reply related [flat|nested] 14+ messages in thread* [PULL 4/4] target/openrisc: Do not reset delay slot flag on early tb exit
@ 2022-05-15 1:39 ` Stafford Horne
0 siblings, 0 replies; 14+ messages in thread
From: Stafford Horne @ 2022-05-15 1:39 UTC (permalink / raw)
To: QEMU Development
Cc: Openrisc, Jason A. Donenfeld, Stafford Horne, Richard Henderson
This was found when running linux crypto algorithm selftests used by
wireguard. We found that randomly the tests would fail. We found
through investigation that a combination of a tick timer interrupt,
raised when executing a delay slot instruction at a page boundary caused
the issue.
This was caused when handling the TB_EXIT_REQUESTED case in cpu_tb_exec.
On OpenRISC, which doesn't implement synchronize_from_tb, set_pc was
being used as a fallback. The OpenRISC set_pc implementation clears
dflag, which caused the exception handling logic to not account for the
delay slot. This was the bug, because it meant when execution resumed
after the interrupt was handling it resumed in the wrong place.
Fix this by implementing synchronize_from_tb which simply updates pc,
and not clear the delay slot flag.
Reported-by: Jason A. Donenfeld <Jason@zx2c4.com>
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
Signed-off-by: Stafford Horne <shorne@gmail.com>
---
target/openrisc/cpu.c | 11 +++++++++++
1 file changed, 11 insertions(+)
diff --git a/target/openrisc/cpu.c b/target/openrisc/cpu.c
index dfbafc5236..41d1b2a24a 100644
--- a/target/openrisc/cpu.c
+++ b/target/openrisc/cpu.c
@@ -21,6 +21,7 @@
#include "qapi/error.h"
#include "qemu/qemu-print.h"
#include "cpu.h"
+#include "exec/exec-all.h"
static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
{
@@ -30,6 +31,15 @@ static void openrisc_cpu_set_pc(CPUState *cs, vaddr value)
cpu->env.dflag = 0;
}
+static void openrisc_cpu_synchronize_from_tb(CPUState *cs,
+ const TranslationBlock *tb)
+{
+ OpenRISCCPU *cpu = OPENRISC_CPU(cs);
+
+ cpu->env.pc = tb->pc;
+}
+
+
static bool openrisc_cpu_has_work(CPUState *cs)
{
return cs->interrupt_request & (CPU_INTERRUPT_HARD |
@@ -186,6 +196,7 @@ static const struct SysemuCPUOps openrisc_sysemu_ops = {
static const struct TCGCPUOps openrisc_tcg_ops = {
.initialize = openrisc_translate_init,
+ .synchronize_from_tb = openrisc_cpu_synchronize_from_tb,
#ifndef CONFIG_USER_ONLY
.tlb_fill = openrisc_cpu_tlb_fill,
--
2.31.1
^ permalink raw reply related [flat|nested] 14+ messages in thread
* Re: [PULL 0/4] OpenRISC fixes for QEMU 2022-05-15
2022-05-15 1:39 ` Stafford Horne
@ 2022-05-15 23:12 ` Richard Henderson
-1 siblings, 0 replies; 14+ messages in thread
From: Richard Henderson @ 2022-05-15 23:12 UTC (permalink / raw)
To: Stafford Horne, QEMU Development; +Cc: Jason A. Donenfeld, Openrisc
On 5/14/22 18:39, Stafford Horne wrote:
> The following changes since commit 2e3408b3cc7de4e87a9adafc8c19bfce3abec947:
>
> Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into staging (2022-05-03 09:13:17 -0700)
>
> are available in the Git repository at:
>
> https://github.com/stffrdhrn/qemu.git tags/or1k-pull-request-20220515
>
> for you to fetch changes up to e8f0ab0cd674241cbab7231ce05ac1bfa0b4f5ed:
>
> target/openrisc: Do not reset delay slot flag on early tb exit (2022-05-15 10:33:01 +0900)
>
> ----------------------------------------------------------------
> OpenRISC Fixes for 7.0
>
> - A few or1ksim fixes and enhancements
> - A fix for OpenRISC tcg backend around delay slot handling
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.
The gpg key I have for you is expired. Have you refreshed the expiration date and pushed
the new copy somewhere?
r~
>
> ----------------------------------------------------------------
> Jason A. Donenfeld (3):
> hw/openrisc: page-align FDT address
> hw/openrisc: support 4 serial ports in or1ksim
> hw/openrisc: use right OMPIC size variable
>
> Stafford Horne (1):
> target/openrisc: Do not reset delay slot flag on early tb exit
>
> hw/openrisc/openrisc_sim.c | 28 +++++++++++++++++++---------
> target/openrisc/cpu.c | 11 +++++++++++
> 2 files changed, 30 insertions(+), 9 deletions(-)
>
> Jason A. Donenfeld (3):
> hw/openrisc: page-align FDT address
> hw/openrisc: support 4 serial ports in or1ksim
> hw/openrisc: use right OMPIC size variable
>
> Stafford Horne (1):
> target/openrisc: Do not reset delay slot flag on early tb exit
>
> hw/openrisc/openrisc_sim.c | 28 +++++++++++++++++++---------
> target/openrisc/cpu.c | 11 +++++++++++
> 2 files changed, 30 insertions(+), 9 deletions(-)
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PULL 0/4] OpenRISC fixes for QEMU 2022-05-15
@ 2022-05-15 23:12 ` Richard Henderson
0 siblings, 0 replies; 14+ messages in thread
From: Richard Henderson @ 2022-05-15 23:12 UTC (permalink / raw)
To: Stafford Horne, QEMU Development; +Cc: Openrisc, Jason A. Donenfeld
On 5/14/22 18:39, Stafford Horne wrote:
> The following changes since commit 2e3408b3cc7de4e87a9adafc8c19bfce3abec947:
>
> Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into staging (2022-05-03 09:13:17 -0700)
>
> are available in the Git repository at:
>
> https://github.com/stffrdhrn/qemu.git tags/or1k-pull-request-20220515
>
> for you to fetch changes up to e8f0ab0cd674241cbab7231ce05ac1bfa0b4f5ed:
>
> target/openrisc: Do not reset delay slot flag on early tb exit (2022-05-15 10:33:01 +0900)
>
> ----------------------------------------------------------------
> OpenRISC Fixes for 7.0
>
> - A few or1ksim fixes and enhancements
> - A fix for OpenRISC tcg backend around delay slot handling
Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.
The gpg key I have for you is expired. Have you refreshed the expiration date and pushed
the new copy somewhere?
r~
>
> ----------------------------------------------------------------
> Jason A. Donenfeld (3):
> hw/openrisc: page-align FDT address
> hw/openrisc: support 4 serial ports in or1ksim
> hw/openrisc: use right OMPIC size variable
>
> Stafford Horne (1):
> target/openrisc: Do not reset delay slot flag on early tb exit
>
> hw/openrisc/openrisc_sim.c | 28 +++++++++++++++++++---------
> target/openrisc/cpu.c | 11 +++++++++++
> 2 files changed, 30 insertions(+), 9 deletions(-)
>
> Jason A. Donenfeld (3):
> hw/openrisc: page-align FDT address
> hw/openrisc: support 4 serial ports in or1ksim
> hw/openrisc: use right OMPIC size variable
>
> Stafford Horne (1):
> target/openrisc: Do not reset delay slot flag on early tb exit
>
> hw/openrisc/openrisc_sim.c | 28 +++++++++++++++++++---------
> target/openrisc/cpu.c | 11 +++++++++++
> 2 files changed, 30 insertions(+), 9 deletions(-)
>
^ permalink raw reply [flat|nested] 14+ messages in thread
* Re: [PULL 0/4] OpenRISC fixes for QEMU 2022-05-15
2022-05-15 23:12 ` Richard Henderson
@ 2022-05-15 23:50 ` Stafford Horne
-1 siblings, 0 replies; 14+ messages in thread
From: Stafford Horne @ 2022-05-15 23:50 UTC (permalink / raw)
To: Richard Henderson; +Cc: Jason A. Donenfeld, Openrisc, QEMU Development
On Sun, May 15, 2022 at 04:12:50PM -0700, Richard Henderson wrote:
> On 5/14/22 18:39, Stafford Horne wrote:
> > The following changes since commit 2e3408b3cc7de4e87a9adafc8c19bfce3abec947:
> >
> > Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into staging (2022-05-03 09:13:17 -0700)
> >
> > are available in the Git repository at:
> >
> > https://github.com/stffrdhrn/qemu.git tags/or1k-pull-request-20220515
> >
> > for you to fetch changes up to e8f0ab0cd674241cbab7231ce05ac1bfa0b4f5ed:
> >
> > target/openrisc: Do not reset delay slot flag on early tb exit (2022-05-15 10:33:01 +0900)
> >
> > ----------------------------------------------------------------
> > OpenRISC Fixes for 7.0
> >
> > - A few or1ksim fixes and enhancements
> > - A fix for OpenRISC tcg backend around delay slot handling
>
> Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.
>
> The gpg key I have for you is expired. Have you refreshed the expiration
> date and pushed the new copy somewhere?
Hello Richard,
I updated my PGP key (C3B31C2D5E6627E4) last year or so to extend the expiry
day. It should be uploaded to pgp.mit.edu, but for some reason that server is
not responding to searches for me right now.
I have also just uploaded it to keyserver.ubuntu.com if that helps.
- https://keyserver.ubuntu.com/pks/lookup?search=stafford+horne&fingerprint=on&op=index
sec rsa4096/C3B31C2D5E6627E4
created: 2016-09-14 expires: never usage: SC
If you still have any issue I can try to work it out.
-Stafford
^ permalink raw reply [flat|nested] 14+ messages in thread* Re: [PULL 0/4] OpenRISC fixes for QEMU 2022-05-15
@ 2022-05-15 23:50 ` Stafford Horne
0 siblings, 0 replies; 14+ messages in thread
From: Stafford Horne @ 2022-05-15 23:50 UTC (permalink / raw)
To: Richard Henderson; +Cc: QEMU Development, Openrisc, Jason A. Donenfeld
On Sun, May 15, 2022 at 04:12:50PM -0700, Richard Henderson wrote:
> On 5/14/22 18:39, Stafford Horne wrote:
> > The following changes since commit 2e3408b3cc7de4e87a9adafc8c19bfce3abec947:
> >
> > Merge tag 'misc-pull-request' of gitlab.com:marcandre.lureau/qemu into staging (2022-05-03 09:13:17 -0700)
> >
> > are available in the Git repository at:
> >
> > https://github.com/stffrdhrn/qemu.git tags/or1k-pull-request-20220515
> >
> > for you to fetch changes up to e8f0ab0cd674241cbab7231ce05ac1bfa0b4f5ed:
> >
> > target/openrisc: Do not reset delay slot flag on early tb exit (2022-05-15 10:33:01 +0900)
> >
> > ----------------------------------------------------------------
> > OpenRISC Fixes for 7.0
> >
> > - A few or1ksim fixes and enhancements
> > - A fix for OpenRISC tcg backend around delay slot handling
>
> Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/7.1 as appropriate.
>
> The gpg key I have for you is expired. Have you refreshed the expiration
> date and pushed the new copy somewhere?
Hello Richard,
I updated my PGP key (C3B31C2D5E6627E4) last year or so to extend the expiry
day. It should be uploaded to pgp.mit.edu, but for some reason that server is
not responding to searches for me right now.
I have also just uploaded it to keyserver.ubuntu.com if that helps.
- https://keyserver.ubuntu.com/pks/lookup?search=stafford+horne&fingerprint=on&op=index
sec rsa4096/C3B31C2D5E6627E4
created: 2016-09-14 expires: never usage: SC
If you still have any issue I can try to work it out.
-Stafford
^ permalink raw reply [flat|nested] 14+ messages in thread